drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_malloc.h>
  36 #include <rte_memzone.h>
  37 #include <rte_string_fns.h>
  38 #include <rte_dev.h>
  39 #include <rte_spinlock.h>
  40 #include <rte_kvargs.h>
  41
  42 #include "fm10k.h"
  43 #include "base/fm10k_api.h"
  44
  45 /* Default delay to acquire mailbox lock */
  46 #define FM10K_MBXLOCK_DELAY_US 20
  47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  48
  49 #define MAIN_VSI_POOL_NUMBER 0
  50
  51 /* Max try times to acquire switch status */
  52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  53 /* Wait interval to get switch status */
  54 #define WAIT_SWITCH_MSG_US    100000
  55 /* A period of quiescence for switch */
  56 #define FM10K_SWITCH_QUIESCE_US 100000
  57 /* Number of chars per uint32 type */
  58 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  59 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  60
  61 /* default 1:1 map from queue ID to interrupt vector ID */
  62 #define Q2V(dev, queue_id) (dev->pci_dev->intr_handle.intr_vec[queue_id])
  63
  64 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  65 #define MAX_LPORT_NUM    128
  66 #define GLORT_FD_Q_BASE  0x40
  67 #define GLORT_PF_MASK    0xFFC0
  68 #define GLORT_FD_MASK    GLORT_PF_MASK
  69 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  70
  71 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  72 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  73 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  74 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  75 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  76 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  77 static int
  78 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  79 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  80         const u8 *mac, bool add, uint32_t pool);
  81 static void fm10k_tx_queue_release(void *queue);
  82 static void fm10k_rx_queue_release(void *queue);
  83 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  84 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  85 static int fm10k_check_ftag(struct rte_devargs *devargs);
  86 static int fm10k_link_update(struct rte_eth_dev *dev, int wait_to_complete);
  87
  88 struct fm10k_xstats_name_off {
  89         char name[RTE_ETH_XSTATS_NAME_SIZE];
  90         unsigned offset;
  91 };
  92
  93 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  94         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  95         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  96         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  97         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  98         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  99         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
 100         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
 101         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
 102                 nodesc_drop)},
 103 };
 104
 105 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 106                 sizeof(fm10k_hw_stats_strings[0]))
 107
 108 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 109         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 110         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 111         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 112 };
 113
 114 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 115                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 116
 117 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 118         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 119         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 120 };
 121
 122 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 123                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 124
 125 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 126                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 127 static int
 128 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 129
 130 static void
 131 fm10k_mbx_initlock(struct fm10k_hw *hw)
 132 {
 133         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 134 }
 135
 136 static void
 137 fm10k_mbx_lock(struct fm10k_hw *hw)
 138 {
 139         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 140                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 141 }
 142
 143 static void
 144 fm10k_mbx_unlock(struct fm10k_hw *hw)
 145 {
 146         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 147 }
 148
 149 /* Stubs needed for linkage when vPMD is disabled */
 150 int __attribute__((weak))
 151 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 152 {
 153         return -1;
 154 }
 155
 156 uint16_t __attribute__((weak))
 157 fm10k_recv_pkts_vec(
 158         __rte_unused void *rx_queue,
 159         __rte_unused struct rte_mbuf **rx_pkts,
 160         __rte_unused uint16_t nb_pkts)
 161 {
 162         return 0;
 163 }
 164
 165 uint16_t __attribute__((weak))
 166 fm10k_recv_scattered_pkts_vec(
 167                 __rte_unused void *rx_queue,
 168                 __rte_unused struct rte_mbuf **rx_pkts,
 169                 __rte_unused uint16_t nb_pkts)
 170 {
 171         return 0;
 172 }
 173
 174 int __attribute__((weak))
 175 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 176
 177 {
 178         return -1;
 179 }
 180
 181 void __attribute__((weak))
 182 fm10k_rx_queue_release_mbufs_vec(
 183                 __rte_unused struct fm10k_rx_queue *rxq)
 184 {
 185         return;
 186 }
 187
 188 void __attribute__((weak))
 189 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 190 {
 191         return;
 192 }
 193
 194 int __attribute__((weak))
 195 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 196 {
 197         return -1;
 198 }
 199
 200 uint16_t __attribute__((weak))
 201 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
 202                 __rte_unused struct rte_mbuf **tx_pkts,
 203                 __rte_unused uint16_t nb_pkts)
 204 {
 205         return 0;
 206 }
 207
 208 /*
 209  * reset queue to initial state, allocate software buffers used when starting
 210  * device.
 211  * return 0 on success
 212  * return -ENOMEM if buffers cannot be allocated
 213  * return -EINVAL if buffers do not satisfy alignment condition
 214  */
 215 static inline int
 216 rx_queue_reset(struct fm10k_rx_queue *q)
 217 {
 218         static const union fm10k_rx_desc zero = {{0} };
 219         uint64_t dma_addr;
 220         int i, diag;
 221         PMD_INIT_FUNC_TRACE();
 222
 223         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 224         if (diag != 0)
 225                 return -ENOMEM;
 226
 227         for (i = 0; i < q->nb_desc; ++i) {
 228                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 229                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 230                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 231                                                 q->nb_desc);
 232                         return -EINVAL;
 233                 }
 234                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 235                 q->hw_ring[i].q.pkt_addr = dma_addr;
 236                 q->hw_ring[i].q.hdr_addr = dma_addr;
 237         }
 238
 239         /* initialize extra software ring entries. Space for these extra
 240          * entries is always allocated.
 241          */
 242         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 243         for (i = 0; i < q->nb_fake_desc; ++i) {
 244                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 245                 q->hw_ring[q->nb_desc + i] = zero;
 246         }
 247
 248         q->next_dd = 0;
 249         q->next_alloc = 0;
 250         q->next_trigger = q->alloc_thresh - 1;
 251         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 252         q->rxrearm_start = 0;
 253         q->rxrearm_nb = 0;
 254
 255         return 0;
 256 }
 257
 258 /*
 259  * clean queue, descriptor rings, free software buffers used when stopping
 260  * device.
 261  */
 262 static inline void
 263 rx_queue_clean(struct fm10k_rx_queue *q)
 264 {
 265         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 266         uint32_t i;
 267         PMD_INIT_FUNC_TRACE();
 268
 269         /* zero descriptor rings */
 270         for (i = 0; i < q->nb_desc; ++i)
 271                 q->hw_ring[i] = zero;
 272
 273         /* zero faked descriptors */
 274         for (i = 0; i < q->nb_fake_desc; ++i)
 275                 q->hw_ring[q->nb_desc + i] = zero;
 276
 277         /* vPMD driver has a different way of releasing mbufs. */
 278         if (q->rx_using_sse) {
 279                 fm10k_rx_queue_release_mbufs_vec(q);
 280                 return;
 281         }
 282
 283         /* free software buffers */
 284         for (i = 0; i < q->nb_desc; ++i) {
 285                 if (q->sw_ring[i]) {
 286                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 287                         q->sw_ring[i] = NULL;
 288                 }
 289         }
 290 }
 291
 292 /*
 293  * free all queue memory used when releasing the queue (i.e. configure)
 294  */
 295 static inline void
 296 rx_queue_free(struct fm10k_rx_queue *q)
 297 {
 298         PMD_INIT_FUNC_TRACE();
 299         if (q) {
 300                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 301                 rx_queue_clean(q);
 302                 if (q->sw_ring) {
 303                         rte_free(q->sw_ring);
 304                         q->sw_ring = NULL;
 305                 }
 306                 rte_free(q);
 307                 q = NULL;
 308         }
 309 }
 310
 311 /*
 312  * disable RX queue, wait unitl HW finished necessary flush operation
 313  */
 314 static inline int
 315 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 316 {
 317         uint32_t reg, i;
 318
 319         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 320         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 321                         reg & ~FM10K_RXQCTL_ENABLE);
 322
 323         /* Wait 100us at most */
 324         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 325                 rte_delay_us(1);
 326                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 327                 if (!(reg & FM10K_RXQCTL_ENABLE))
 328                         break;
 329         }
 330
 331         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 332                 return -1;
 333
 334         return 0;
 335 }
 336
 337 /*
 338  * reset queue to initial state, allocate software buffers used when starting
 339  * device
 340  */
 341 static inline void
 342 tx_queue_reset(struct fm10k_tx_queue *q)
 343 {
 344         PMD_INIT_FUNC_TRACE();
 345         q->last_free = 0;
 346         q->next_free = 0;
 347         q->nb_used = 0;
 348         q->nb_free = q->nb_desc - 1;
 349         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 350         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 351 }
 352
 353 /*
 354  * clean queue, descriptor rings, free software buffers used when stopping
 355  * device
 356  */
 357 static inline void
 358 tx_queue_clean(struct fm10k_tx_queue *q)
 359 {
 360         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 361         uint32_t i;
 362         PMD_INIT_FUNC_TRACE();
 363
 364         /* zero descriptor rings */
 365         for (i = 0; i < q->nb_desc; ++i)
 366                 q->hw_ring[i] = zero;
 367
 368         /* free software buffers */
 369         for (i = 0; i < q->nb_desc; ++i) {
 370                 if (q->sw_ring[i]) {
 371                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 372                         q->sw_ring[i] = NULL;
 373                 }
 374         }
 375 }
 376
 377 /*
 378  * free all queue memory used when releasing the queue (i.e. configure)
 379  */
 380 static inline void
 381 tx_queue_free(struct fm10k_tx_queue *q)
 382 {
 383         PMD_INIT_FUNC_TRACE();
 384         if (q) {
 385                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 386                 tx_queue_clean(q);
 387                 if (q->rs_tracker.list) {
 388                         rte_free(q->rs_tracker.list);
 389                         q->rs_tracker.list = NULL;
 390                 }
 391                 if (q->sw_ring) {
 392                         rte_free(q->sw_ring);
 393                         q->sw_ring = NULL;
 394                 }
 395                 rte_free(q);
 396                 q = NULL;
 397         }
 398 }
 399
 400 /*
 401  * disable TX queue, wait unitl HW finished necessary flush operation
 402  */
 403 static inline int
 404 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 405 {
 406         uint32_t reg, i;
 407
 408         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 409         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 410                         reg & ~FM10K_TXDCTL_ENABLE);
 411
 412         /* Wait 100us at most */
 413         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 414                 rte_delay_us(1);
 415                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 416                 if (!(reg & FM10K_TXDCTL_ENABLE))
 417                         break;
 418         }
 419
 420         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 421                 return -1;
 422
 423         return 0;
 424 }
 425
 426 static int
 427 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 428 {
 429         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 430         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 431         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 432         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 433
 434         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 435
 436         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 437                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 438                 return -EINVAL;
 439         }
 440
 441         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 442                 return 0;
 443
 444         if (hw->mac.type == fm10k_mac_vf) {
 445                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 446                 return -EINVAL;
 447         }
 448
 449         /* Check VMDQ queue pool number */
 450         if (vmdq_conf->nb_queue_pools >
 451                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 452                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 453                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 454                         vmdq_conf->nb_queue_pools);
 455                 return -EINVAL;
 456         }
 457
 458         return 0;
 459 }
 460
 461 static const struct fm10k_txq_ops def_txq_ops = {
 462         .reset = tx_queue_reset,
 463 };
 464
 465 static int
 466 fm10k_dev_configure(struct rte_eth_dev *dev)
 467 {
 468         int ret;
 469
 470         PMD_INIT_FUNC_TRACE();
 471
 472         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 473                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 474         /* multipe queue mode checking */
 475         ret  = fm10k_check_mq_mode(dev);
 476         if (ret != 0) {
 477                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 478                             ret);
 479                 return ret;
 480         }
 481
 482         return 0;
 483 }
 484
 485 /* fls = find last set bit = 32 minus the number of leading zeros */
 486 #ifndef fls
 487 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 488 #endif
 489
 490 static void
 491 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 492 {
 493         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 494         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 495         uint32_t i;
 496
 497         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 498
 499         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 500                 if (!vmdq_conf->pool_map[i].pools)
 501                         continue;
 502                 fm10k_mbx_lock(hw);
 503                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 504                 fm10k_mbx_unlock(hw);
 505         }
 506 }
 507
 508 static void
 509 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 510 {
 511         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 512
 513         /* Add default mac address */
 514         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 515                 MAIN_VSI_POOL_NUMBER);
 516 }
 517
 518 static void
 519 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 520 {
 521         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 522         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 523         uint32_t mrqc, *key, i, reta, j;
 524         uint64_t hf;
 525
 526 #define RSS_KEY_SIZE 40
 527         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 528                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 529                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 530                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 531                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 532                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 533         };
 534
 535         if (dev->data->nb_rx_queues == 1 ||
 536             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 537             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 538                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 539                 return;
 540         }
 541
 542         /* random key is rss_intel_key (default) or user provided (rss_key) */
 543         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 544                 key = (uint32_t *)rss_intel_key;
 545         else
 546                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 547
 548         /* Now fill our hash function seeds, 4 bytes at a time */
 549         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 550                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 551
 552         /*
 553          * Fill in redirection table
 554          * The byte-swap is needed because NIC registers are in
 555          * little-endian order.
 556          */
 557         reta = 0;
 558         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 559                 if (j == dev->data->nb_rx_queues)
 560                         j = 0;
 561                 reta = (reta << CHAR_BIT) | j;
 562                 if ((i & 3) == 3)
 563                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 564                                         rte_bswap32(reta));
 565         }
 566
 567         /*
 568          * Generate RSS hash based on packet types, TCP/UDP
 569          * port numbers and/or IPv4/v6 src and dst addresses
 570          */
 571         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 572         mrqc = 0;
 573         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 574         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 575         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 577         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 579         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 580         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 581         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 582
 583         if (mrqc == 0) {
 584                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 585                         "supported", hf);
 586                 return;
 587         }
 588
 589         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 590 }
 591
 592 static void
 593 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 594 {
 595         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 596         uint32_t i;
 597
 598         for (i = 0; i < nb_lport_new; i++) {
 599                 /* Set unicast mode by default. App can change
 600                  * to other mode in other API func.
 601                  */
 602                 fm10k_mbx_lock(hw);
 603                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 604                         FM10K_XCAST_MODE_NONE);
 605                 fm10k_mbx_unlock(hw);
 606         }
 607 }
 608
 609 static void
 610 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 611 {
 612         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 613         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 614         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 615         struct fm10k_macvlan_filter_info *macvlan;
 616         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 617         uint16_t nb_lport_new;
 618
 619         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 620         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 621
 622         fm10k_dev_rss_configure(dev);
 623
 624         /* only PF supports VMDQ */
 625         if (hw->mac.type != fm10k_mac_pf)
 626                 return;
 627
 628         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 629                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 630
 631         /* no pool number change, no need to update logic port and VLAN/MAC */
 632         if (macvlan->nb_queue_pools == nb_queue_pools)
 633                 return;
 634
 635         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 636         fm10k_dev_logic_port_update(dev, nb_lport_new);
 637
 638         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 639         memset(dev->data->mac_addrs, 0,
 640                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 641         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 642                 &dev->data->mac_addrs[0]);
 643         memset(macvlan, 0, sizeof(*macvlan));
 644         macvlan->nb_queue_pools = nb_queue_pools;
 645
 646         if (nb_queue_pools)
 647                 fm10k_dev_vmdq_rx_configure(dev);
 648         else
 649                 fm10k_dev_pf_main_vsi_reset(dev);
 650 }
 651
 652 static int
 653 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 654 {
 655         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 656         int i, ret;
 657         struct fm10k_tx_queue *txq;
 658         uint64_t base_addr;
 659         uint32_t size;
 660
 661         /* Disable TXINT to avoid possible interrupt */
 662         for (i = 0; i < hw->mac.max_queues; i++)
 663                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 664                                 3 << FM10K_TXINT_TIMER_SHIFT);
 665
 666         /* Setup TX queue */
 667         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 668                 txq = dev->data->tx_queues[i];
 669                 base_addr = txq->hw_ring_phys_addr;
 670                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 671
 672                 /* disable queue to avoid issues while updating state */
 673                 ret = tx_queue_disable(hw, i);
 674                 if (ret) {
 675                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 676                         return -1;
 677                 }
 678                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 679                  * register is read-only for VF.
 680                  */
 681                 if (fm10k_check_ftag(dev->pci_dev->device.devargs)) {
 682                         if (hw->mac.type == fm10k_mac_pf) {
 683                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 684                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 685                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 686                         } else {
 687                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 688                                 return -ENOTSUP;
 689                         }
 690                 }
 691
 692                 /* set location and size for descriptor ring */
 693                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 694                                 base_addr & UINT64_LOWER_32BITS_MASK);
 695                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 696                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 697                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 698
 699                 /* assign default SGLORT for each TX queue by PF */
 700                 if (hw->mac.type == fm10k_mac_pf)
 701                         FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 702         }
 703
 704         /* set up vector or scalar TX function as appropriate */
 705         fm10k_set_tx_function(dev);
 706
 707         return 0;
 708 }
 709
 710 static int
 711 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 712 {
 713         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 714         struct fm10k_macvlan_filter_info *macvlan;
 715         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 716         int i, ret;
 717         struct fm10k_rx_queue *rxq;
 718         uint64_t base_addr;
 719         uint32_t size;
 720         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 721         uint32_t logic_port = hw->mac.dglort_map;
 722         uint16_t buf_size;
 723         uint16_t queue_stride = 0;
 724
 725         /* enable RXINT for interrupt mode */
 726         i = 0;
 727         if (rte_intr_dp_is_en(intr_handle)) {
 728                 for (; i < dev->data->nb_rx_queues; i++) {
 729                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(dev, i));
 730                         if (hw->mac.type == fm10k_mac_pf)
 731                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
 732                                         FM10K_ITR_AUTOMASK |
 733                                         FM10K_ITR_MASK_CLEAR);
 734                         else
 735                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
 736                                         FM10K_ITR_AUTOMASK |
 737                                         FM10K_ITR_MASK_CLEAR);
 738                 }
 739         }
 740         /* Disable other RXINT to avoid possible interrupt */
 741         for (; i < hw->mac.max_queues; i++)
 742                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 743                         3 << FM10K_RXINT_TIMER_SHIFT);
 744
 745         /* Setup RX queues */
 746         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 747                 rxq = dev->data->rx_queues[i];
 748                 base_addr = rxq->hw_ring_phys_addr;
 749                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 750
 751                 /* disable queue to avoid issues while updating state */
 752                 ret = rx_queue_disable(hw, i);
 753                 if (ret) {
 754                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 755                         return -1;
 756                 }
 757
 758                 /* Setup the Base and Length of the Rx Descriptor Ring */
 759                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 760                                 base_addr & UINT64_LOWER_32BITS_MASK);
 761                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 762                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 763                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 764
 765                 /* Configure the Rx buffer size for one buff without split */
 766                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 767                         RTE_PKTMBUF_HEADROOM);
 768                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 769                  * reserved for this purpose, and the worst case could be 511B.
 770                  * But SRR reg assumes all buffers have the same size. In order
 771                  * to fill the gap, we'll have to consider the worst case and
 772                  * assume 512B is reserved. If we don't do so, it's possible
 773                  * for HW to overwrite data to next mbuf.
 774                  */
 775                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 776
 777                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 778                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 779                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 780
 781                 /* It adds dual VLAN length for supporting dual VLAN */
 782                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 783                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 784                         dev->data->dev_conf.rxmode.enable_scatter) {
 785                         uint32_t reg;
 786                         dev->data->scattered_rx = 1;
 787                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 788                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 789                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 790                 }
 791
 792                 /* Enable drop on empty, it's RO for VF */
 793                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 794                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 795
 796                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 797                 FM10K_WRITE_FLUSH(hw);
 798         }
 799
 800         /* Configure VMDQ/RSS if applicable */
 801         fm10k_dev_mq_rx_configure(dev);
 802
 803         /* Decide the best RX function */
 804         fm10k_set_rx_function(dev);
 805
 806         /* update RX_SGLORT for loopback suppress*/
 807         if (hw->mac.type != fm10k_mac_pf)
 808                 return 0;
 809         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 810         if (macvlan->nb_queue_pools)
 811                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 812         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 813                 if (i && queue_stride && !(i % queue_stride))
 814                         logic_port++;
 815                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int
 822 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 823 {
 824         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 825         int err = -1;
 826         uint32_t reg;
 827         struct fm10k_rx_queue *rxq;
 828
 829         PMD_INIT_FUNC_TRACE();
 830
 831         if (rx_queue_id < dev->data->nb_rx_queues) {
 832                 rxq = dev->data->rx_queues[rx_queue_id];
 833                 err = rx_queue_reset(rxq);
 834                 if (err == -ENOMEM) {
 835                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 836                         return err;
 837                 } else if (err == -EINVAL) {
 838                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 839                                 " %d", err);
 840                         return err;
 841                 }
 842
 843                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 844                  * Note: this must be done AFTER the queue is enabled on real
 845                  * hardware, but BEFORE the queue is enabled when using the
 846                  * emulation platform. Do it in both places for now and remove
 847                  * this comment and the following two register writes when the
 848                  * emulation platform is no longer being used.
 849                  */
 850                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 851                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 852
 853                 /* Set PF ownership flag for PF devices */
 854                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 855                 if (hw->mac.type == fm10k_mac_pf)
 856                         reg |= FM10K_RXQCTL_PF;
 857                 reg |= FM10K_RXQCTL_ENABLE;
 858                 /* enable RX queue */
 859                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 860                 FM10K_WRITE_FLUSH(hw);
 861
 862                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 863                  * Note: this must be done AFTER the queue is enabled
 864                  */
 865                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 866                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 867                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 868         }
 869
 870         return err;
 871 }
 872
 873 static int
 874 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 875 {
 876         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877
 878         PMD_INIT_FUNC_TRACE();
 879
 880         if (rx_queue_id < dev->data->nb_rx_queues) {
 881                 /* Disable RX queue */
 882                 rx_queue_disable(hw, rx_queue_id);
 883
 884                 /* Free mbuf and clean HW ring */
 885                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 886                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 887         }
 888
 889         return 0;
 890 }
 891
 892 static int
 893 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 894 {
 895         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 896         /** @todo - this should be defined in the shared code */
 897 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 898         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 899         int err = 0;
 900
 901         PMD_INIT_FUNC_TRACE();
 902
 903         if (tx_queue_id < dev->data->nb_tx_queues) {
 904                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 905
 906                 q->ops->reset(q);
 907
 908                 /* reset head and tail pointers */
 909                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 910                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 911
 912                 /* enable TX queue */
 913                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 914                                         FM10K_TXDCTL_ENABLE | txdctl);
 915                 FM10K_WRITE_FLUSH(hw);
 916                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 917         } else
 918                 err = -1;
 919
 920         return err;
 921 }
 922
 923 static int
 924 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 925 {
 926         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 927
 928         PMD_INIT_FUNC_TRACE();
 929
 930         if (tx_queue_id < dev->data->nb_tx_queues) {
 931                 tx_queue_disable(hw, tx_queue_id);
 932                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 933                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 940 {
 941         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 942                 != FM10K_DGLORTMAP_NONE);
 943 }
 944
 945 static void
 946 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 947 {
 948         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 949         int status;
 950
 951         PMD_INIT_FUNC_TRACE();
 952
 953         /* Return if it didn't acquire valid glort range */
 954         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 955                 return;
 956
 957         fm10k_mbx_lock(hw);
 958         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 959                                 FM10K_XCAST_MODE_PROMISC);
 960         fm10k_mbx_unlock(hw);
 961
 962         if (status != FM10K_SUCCESS)
 963                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 964 }
 965
 966 static void
 967 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 968 {
 969         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 970         uint8_t mode;
 971         int status;
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         /* Return if it didn't acquire valid glort range */
 976         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 977                 return;
 978
 979         if (dev->data->all_multicast == 1)
 980                 mode = FM10K_XCAST_MODE_ALLMULTI;
 981         else
 982                 mode = FM10K_XCAST_MODE_NONE;
 983
 984         fm10k_mbx_lock(hw);
 985         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 986                                 mode);
 987         fm10k_mbx_unlock(hw);
 988
 989         if (status != FM10K_SUCCESS)
 990                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 991 }
 992
 993 static void
 994 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 995 {
 996         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         int status;
 998
 999         PMD_INIT_FUNC_TRACE();
1000
1001         /* Return if it didn't acquire valid glort range */
1002         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1003                 return;
1004
1005         /* If promiscuous mode is enabled, it doesn't make sense to enable
1006          * allmulticast and disable promiscuous since fm10k only can select
1007          * one of the modes.
1008          */
1009         if (dev->data->promiscuous) {
1010                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1011                         "needn't enable allmulticast");
1012                 return;
1013         }
1014
1015         fm10k_mbx_lock(hw);
1016         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1017                                 FM10K_XCAST_MODE_ALLMULTI);
1018         fm10k_mbx_unlock(hw);
1019
1020         if (status != FM10K_SUCCESS)
1021                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1022 }
1023
1024 static void
1025 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1026 {
1027         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028         int status;
1029
1030         PMD_INIT_FUNC_TRACE();
1031
1032         /* Return if it didn't acquire valid glort range */
1033         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1034                 return;
1035
1036         if (dev->data->promiscuous) {
1037                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1038                         "since promisc mode is enabled");
1039                 return;
1040         }
1041
1042         fm10k_mbx_lock(hw);
1043         /* Change mode to unicast mode */
1044         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1045                                 FM10K_XCAST_MODE_NONE);
1046         fm10k_mbx_unlock(hw);
1047
1048         if (status != FM10K_SUCCESS)
1049                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1050 }
1051
1052 static void
1053 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1054 {
1055         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1057         uint16_t nb_queue_pools;
1058         struct fm10k_macvlan_filter_info *macvlan;
1059
1060         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1061         nb_queue_pools = macvlan->nb_queue_pools;
1062         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1063         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1064
1065         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1066         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1067         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1068                         hw->mac.dglort_map;
1069         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1070         /* Configure VMDQ/RSS DGlort Decoder */
1071         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1072
1073         /* Flow Director configurations, only queue number is valid. */
1074         dglortdec = fls(dev->data->nb_rx_queues - 1);
1075         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1076                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1077         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1078         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1079
1080         /* Invalidate all other GLORT entries */
1081         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1082                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1083                                 FM10K_DGLORTMAP_NONE);
1084 }
1085
1086 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1087 static int
1088 fm10k_dev_start(struct rte_eth_dev *dev)
1089 {
1090         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091         int i, diag;
1092
1093         PMD_INIT_FUNC_TRACE();
1094
1095         /* stop, init, then start the hw */
1096         diag = fm10k_stop_hw(hw);
1097         if (diag != FM10K_SUCCESS) {
1098                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1099                 return -EIO;
1100         }
1101
1102         diag = fm10k_init_hw(hw);
1103         if (diag != FM10K_SUCCESS) {
1104                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1105                 return -EIO;
1106         }
1107
1108         diag = fm10k_start_hw(hw);
1109         if (diag != FM10K_SUCCESS) {
1110                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1111                 return -EIO;
1112         }
1113
1114         diag = fm10k_dev_tx_init(dev);
1115         if (diag) {
1116                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1117                 return diag;
1118         }
1119
1120         if (fm10k_dev_rxq_interrupt_setup(dev))
1121                 return -EIO;
1122
1123         diag = fm10k_dev_rx_init(dev);
1124         if (diag) {
1125                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1126                 return diag;
1127         }
1128
1129         if (hw->mac.type == fm10k_mac_pf)
1130                 fm10k_dev_dglort_map_configure(dev);
1131
1132         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1133                 struct fm10k_rx_queue *rxq;
1134                 rxq = dev->data->rx_queues[i];
1135
1136                 if (rxq->rx_deferred_start)
1137                         continue;
1138                 diag = fm10k_dev_rx_queue_start(dev, i);
1139                 if (diag != 0) {
1140                         int j;
1141                         for (j = 0; j < i; ++j)
1142                                 rx_queue_clean(dev->data->rx_queues[j]);
1143                         return diag;
1144                 }
1145         }
1146
1147         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1148                 struct fm10k_tx_queue *txq;
1149                 txq = dev->data->tx_queues[i];
1150
1151                 if (txq->tx_deferred_start)
1152                         continue;
1153                 diag = fm10k_dev_tx_queue_start(dev, i);
1154                 if (diag != 0) {
1155                         int j;
1156                         for (j = 0; j < i; ++j)
1157                                 tx_queue_clean(dev->data->tx_queues[j]);
1158                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1159                                 rx_queue_clean(dev->data->rx_queues[j]);
1160                         return diag;
1161                 }
1162         }
1163
1164         /* Update default vlan when not in VMDQ mode */
1165         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1166                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1167
1168         fm10k_link_update(dev, 0);
1169
1170         return 0;
1171 }
1172
1173 static void
1174 fm10k_dev_stop(struct rte_eth_dev *dev)
1175 {
1176         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1177         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1178         int i;
1179
1180         PMD_INIT_FUNC_TRACE();
1181
1182         if (dev->data->tx_queues)
1183                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1184                         fm10k_dev_tx_queue_stop(dev, i);
1185
1186         if (dev->data->rx_queues)
1187                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1188                         fm10k_dev_rx_queue_stop(dev, i);
1189
1190         /* Disable datapath event */
1191         if (rte_intr_dp_is_en(intr_handle)) {
1192                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1193                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1194                                 3 << FM10K_RXINT_TIMER_SHIFT);
1195                         if (hw->mac.type == fm10k_mac_pf)
1196                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
1197                                         FM10K_ITR_MASK_SET);
1198                         else
1199                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
1200                                         FM10K_ITR_MASK_SET);
1201                 }
1202         }
1203         /* Clean datapath event and queue/vec mapping */
1204         rte_intr_efd_disable(intr_handle);
1205         rte_free(intr_handle->intr_vec);
1206         intr_handle->intr_vec = NULL;
1207 }
1208
1209 static void
1210 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1211 {
1212         int i;
1213
1214         PMD_INIT_FUNC_TRACE();
1215
1216         if (dev->data->tx_queues) {
1217                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1218                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1219
1220                         tx_queue_free(txq);
1221                 }
1222         }
1223
1224         if (dev->data->rx_queues) {
1225                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1226                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1227         }
1228 }
1229
1230 static void
1231 fm10k_dev_close(struct rte_eth_dev *dev)
1232 {
1233         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234
1235         PMD_INIT_FUNC_TRACE();
1236
1237         fm10k_mbx_lock(hw);
1238         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1239                 MAX_LPORT_NUM, false);
1240         fm10k_mbx_unlock(hw);
1241
1242         /* allow 100ms for device to quiesce */
1243         rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1244
1245         /* Stop mailbox service first */
1246         fm10k_close_mbx_service(hw);
1247         fm10k_dev_stop(dev);
1248         fm10k_dev_queue_release(dev);
1249         fm10k_stop_hw(hw);
1250 }
1251
1252 static int
1253 fm10k_link_update(struct rte_eth_dev *dev,
1254         __rte_unused int wait_to_complete)
1255 {
1256         PMD_INIT_FUNC_TRACE();
1257
1258         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1259          * x8 PCIe interface. For now, we leave the speed undefined since there
1260          * is no 50Gbps Ethernet. */
1261         dev->data->dev_link.link_speed  = 0;
1262         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1263         dev->data->dev_link.link_status = ETH_LINK_UP;
1264
1265         return 0;
1266 }
1267
1268 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1269         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1270 {
1271         unsigned i, q;
1272         unsigned count = 0;
1273
1274         if (xstats_names != NULL) {
1275                 /* Note: limit checked in rte_eth_xstats_names() */
1276
1277                 /* Global stats */
1278                 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1279                         snprintf(xstats_names[count].name,
1280                                 sizeof(xstats_names[count].name),
1281                                 "%s", fm10k_hw_stats_strings[count].name);
1282                         count++;
1283                 }
1284
1285                 /* PF queue stats */
1286                 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1287                         for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1288                                 snprintf(xstats_names[count].name,
1289                                         sizeof(xstats_names[count].name),
1290                                         "rx_q%u_%s", q,
1291                                         fm10k_hw_stats_rx_q_strings[i].name);
1292                                 count++;
1293                         }
1294                         for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1295                                 snprintf(xstats_names[count].name,
1296                                         sizeof(xstats_names[count].name),
1297                                         "tx_q%u_%s", q,
1298                                         fm10k_hw_stats_tx_q_strings[i].name);
1299                                 count++;
1300                         }
1301                 }
1302         }
1303         return FM10K_NB_XSTATS;
1304 }
1305
1306 static int
1307 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1308                  unsigned n)
1309 {
1310         struct fm10k_hw_stats *hw_stats =
1311                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1312         unsigned i, q, count = 0;
1313
1314         if (n < FM10K_NB_XSTATS)
1315                 return FM10K_NB_XSTATS;
1316
1317         /* Global stats */
1318         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1319                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1320                         fm10k_hw_stats_strings[count].offset);
1321                 xstats[count].id = count;
1322                 count++;
1323         }
1324
1325         /* PF queue stats */
1326         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1327                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1328                         xstats[count].value =
1329                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1330                                 fm10k_hw_stats_rx_q_strings[i].offset);
1331                         xstats[count].id = count;
1332                         count++;
1333                 }
1334                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1335                         xstats[count].value =
1336                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1337                                 fm10k_hw_stats_tx_q_strings[i].offset);
1338                         xstats[count].id = count;
1339                         count++;
1340                 }
1341         }
1342
1343         return FM10K_NB_XSTATS;
1344 }
1345
1346 static void
1347 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1348 {
1349         uint64_t ipackets, opackets, ibytes, obytes;
1350         struct fm10k_hw *hw =
1351                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1352         struct fm10k_hw_stats *hw_stats =
1353                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1354         int i;
1355
1356         PMD_INIT_FUNC_TRACE();
1357
1358         fm10k_update_hw_stats(hw, hw_stats);
1359
1360         ipackets = opackets = ibytes = obytes = 0;
1361         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1362                 (i < hw->mac.max_queues); ++i) {
1363                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1364                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1365                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1366                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1367                 ipackets += stats->q_ipackets[i];
1368                 opackets += stats->q_opackets[i];
1369                 ibytes   += stats->q_ibytes[i];
1370                 obytes   += stats->q_obytes[i];
1371         }
1372         stats->ipackets = ipackets;
1373         stats->opackets = opackets;
1374         stats->ibytes = ibytes;
1375         stats->obytes = obytes;
1376 }
1377
1378 static void
1379 fm10k_stats_reset(struct rte_eth_dev *dev)
1380 {
1381         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1382         struct fm10k_hw_stats *hw_stats =
1383                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1384
1385         PMD_INIT_FUNC_TRACE();
1386
1387         memset(hw_stats, 0, sizeof(*hw_stats));
1388         fm10k_rebind_hw_stats(hw, hw_stats);
1389 }
1390
1391 static void
1392 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1393         struct rte_eth_dev_info *dev_info)
1394 {
1395         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396
1397         PMD_INIT_FUNC_TRACE();
1398
1399         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1400         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1401         dev_info->max_rx_queues      = hw->mac.max_queues;
1402         dev_info->max_tx_queues      = hw->mac.max_queues;
1403         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1404         dev_info->max_hash_mac_addrs = 0;
1405         dev_info->max_vfs            = dev->pci_dev->max_vfs;
1406         dev_info->vmdq_pool_base     = 0;
1407         dev_info->vmdq_queue_base    = 0;
1408         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1409         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1410         dev_info->rx_offload_capa =
1411                 DEV_RX_OFFLOAD_VLAN_STRIP |
1412                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1413                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1414                 DEV_RX_OFFLOAD_TCP_CKSUM;
1415         dev_info->tx_offload_capa =
1416                 DEV_TX_OFFLOAD_VLAN_INSERT |
1417                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1418                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1419                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1420                 DEV_TX_OFFLOAD_TCP_TSO;
1421
1422         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1423         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1424
1425         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1426                 .rx_thresh = {
1427                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1428                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1429                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1430                 },
1431                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1432                 .rx_drop_en = 0,
1433         };
1434
1435         dev_info->default_txconf = (struct rte_eth_txconf) {
1436                 .tx_thresh = {
1437                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1438                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1439                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1440                 },
1441                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1442                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1443                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1444         };
1445
1446         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1447                 .nb_max = FM10K_MAX_RX_DESC,
1448                 .nb_min = FM10K_MIN_RX_DESC,
1449                 .nb_align = FM10K_MULT_RX_DESC,
1450         };
1451
1452         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1453                 .nb_max = FM10K_MAX_TX_DESC,
1454                 .nb_min = FM10K_MIN_TX_DESC,
1455                 .nb_align = FM10K_MULT_TX_DESC,
1456         };
1457
1458         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1459                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1460                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1461 }
1462
1463 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1464 static const uint32_t *
1465 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1466 {
1467         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1468             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1469                 static uint32_t ptypes[] = {
1470                         /* refers to rx_desc_to_ol_flags() */
1471                         RTE_PTYPE_L2_ETHER,
1472                         RTE_PTYPE_L3_IPV4,
1473                         RTE_PTYPE_L3_IPV4_EXT,
1474                         RTE_PTYPE_L3_IPV6,
1475                         RTE_PTYPE_L3_IPV6_EXT,
1476                         RTE_PTYPE_L4_TCP,
1477                         RTE_PTYPE_L4_UDP,
1478                         RTE_PTYPE_UNKNOWN
1479                 };
1480
1481                 return ptypes;
1482         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1483                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1484                 static uint32_t ptypes_vec[] = {
1485                         /* refers to fm10k_desc_to_pktype_v() */
1486                         RTE_PTYPE_L3_IPV4,
1487                         RTE_PTYPE_L3_IPV4_EXT,
1488                         RTE_PTYPE_L3_IPV6,
1489                         RTE_PTYPE_L3_IPV6_EXT,
1490                         RTE_PTYPE_L4_TCP,
1491                         RTE_PTYPE_L4_UDP,
1492                         RTE_PTYPE_TUNNEL_GENEVE,
1493                         RTE_PTYPE_TUNNEL_NVGRE,
1494                         RTE_PTYPE_TUNNEL_VXLAN,
1495                         RTE_PTYPE_TUNNEL_GRE,
1496                         RTE_PTYPE_UNKNOWN
1497                 };
1498
1499                 return ptypes_vec;
1500         }
1501
1502         return NULL;
1503 }
1504 #else
1505 static const uint32_t *
1506 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1507 {
1508         return NULL;
1509 }
1510 #endif
1511
1512 static int
1513 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1514 {
1515         s32 result;
1516         uint16_t mac_num = 0;
1517         uint32_t vid_idx, vid_bit, mac_index;
1518         struct fm10k_hw *hw;
1519         struct fm10k_macvlan_filter_info *macvlan;
1520         struct rte_eth_dev_data *data = dev->data;
1521
1522         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1524
1525         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1526                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1527                 return -EINVAL;
1528         }
1529
1530         if (vlan_id > ETH_VLAN_ID_MAX) {
1531                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1532                 return -EINVAL;
1533         }
1534
1535         vid_idx = FM10K_VFTA_IDX(vlan_id);
1536         vid_bit = FM10K_VFTA_BIT(vlan_id);
1537         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1538         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1539                 return 0;
1540         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1541         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1542                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1543                         "in the VLAN filter table");
1544                 return -EINVAL;
1545         }
1546
1547         fm10k_mbx_lock(hw);
1548         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1549         fm10k_mbx_unlock(hw);
1550         if (result != FM10K_SUCCESS) {
1551                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1552                 return -EIO;
1553         }
1554
1555         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1556                         (result == FM10K_SUCCESS); mac_index++) {
1557                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1558                         continue;
1559                 if (mac_num > macvlan->mac_num - 1) {
1560                         PMD_INIT_LOG(ERR, "MAC address number "
1561                                         "not match");
1562                         break;
1563                 }
1564                 fm10k_mbx_lock(hw);
1565                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1566                         data->mac_addrs[mac_index].addr_bytes,
1567                         vlan_id, on, 0);
1568                 fm10k_mbx_unlock(hw);
1569                 mac_num++;
1570         }
1571         if (result != FM10K_SUCCESS) {
1572                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1573                 return -EIO;
1574         }
1575
1576         if (on) {
1577                 macvlan->vlan_num++;
1578                 macvlan->vfta[vid_idx] |= vid_bit;
1579         } else {
1580                 macvlan->vlan_num--;
1581                 macvlan->vfta[vid_idx] &= ~vid_bit;
1582         }
1583         return 0;
1584 }
1585
1586 static void
1587 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1588 {
1589         if (mask & ETH_VLAN_STRIP_MASK) {
1590                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1591                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1592                                         "always on in fm10k");
1593         }
1594
1595         if (mask & ETH_VLAN_EXTEND_MASK) {
1596                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1597                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1598                                         "supported in fm10k");
1599         }
1600
1601         if (mask & ETH_VLAN_FILTER_MASK) {
1602                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1603                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1604         }
1605 }
1606
1607 /* Add/Remove a MAC address, and update filters to main VSI */
1608 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1609                 const u8 *mac, bool add, uint32_t pool)
1610 {
1611         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612         struct fm10k_macvlan_filter_info *macvlan;
1613         uint32_t i, j, k;
1614
1615         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1616
1617         if (pool != MAIN_VSI_POOL_NUMBER) {
1618                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1619                         "mac to pool %u", pool);
1620                 return;
1621         }
1622         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1623                 if (!macvlan->vfta[j])
1624                         continue;
1625                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1626                         if (!(macvlan->vfta[j] & (1 << k)))
1627                                 continue;
1628                         if (i + 1 > macvlan->vlan_num) {
1629                                 PMD_INIT_LOG(ERR, "vlan number not match");
1630                                 return;
1631                         }
1632                         fm10k_mbx_lock(hw);
1633                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1634                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1635                         fm10k_mbx_unlock(hw);
1636                         i++;
1637                 }
1638         }
1639 }
1640
1641 /* Add/Remove a MAC address, and update filters to VMDQ */
1642 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1643                 const u8 *mac, bool add, uint32_t pool)
1644 {
1645         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         struct fm10k_macvlan_filter_info *macvlan;
1647         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1648         uint32_t i;
1649
1650         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1651         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1652
1653         if (pool > macvlan->nb_queue_pools) {
1654                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1655                         " Max pool is %u",
1656                         pool, macvlan->nb_queue_pools);
1657                 return;
1658         }
1659         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1660                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1661                         continue;
1662                 fm10k_mbx_lock(hw);
1663                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1664                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1665                 fm10k_mbx_unlock(hw);
1666         }
1667 }
1668
1669 /* Add/Remove a MAC address, and update filters */
1670 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1671                 const u8 *mac, bool add, uint32_t pool)
1672 {
1673         struct fm10k_macvlan_filter_info *macvlan;
1674
1675         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1676
1677         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1678                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1679         else
1680                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1681
1682         if (add)
1683                 macvlan->mac_num++;
1684         else
1685                 macvlan->mac_num--;
1686 }
1687
1688 /* Add a MAC address, and update filters */
1689 static void
1690 fm10k_macaddr_add(struct rte_eth_dev *dev,
1691                 struct ether_addr *mac_addr,
1692                 uint32_t index,
1693                 uint32_t pool)
1694 {
1695         struct fm10k_macvlan_filter_info *macvlan;
1696
1697         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1698         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1699         macvlan->mac_vmdq_id[index] = pool;
1700 }
1701
1702 /* Remove a MAC address, and update filters */
1703 static void
1704 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1705 {
1706         struct rte_eth_dev_data *data = dev->data;
1707         struct fm10k_macvlan_filter_info *macvlan;
1708
1709         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1710         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1711                         FALSE, macvlan->mac_vmdq_id[index]);
1712         macvlan->mac_vmdq_id[index] = 0;
1713 }
1714
1715 static inline int
1716 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1717 {
1718         if ((request < min) || (request > max) || ((request % mult) != 0))
1719                 return -1;
1720         else
1721                 return 0;
1722 }
1723
1724
1725 static inline int
1726 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1727 {
1728         if ((request < min) || (request > max) || ((div % request) != 0))
1729                 return -1;
1730         else
1731                 return 0;
1732 }
1733
1734 static inline int
1735 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1736 {
1737         uint16_t rx_free_thresh;
1738
1739         if (conf->rx_free_thresh == 0)
1740                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1741         else
1742                 rx_free_thresh = conf->rx_free_thresh;
1743
1744         /* make sure the requested threshold satisfies the constraints */
1745         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1746                         FM10K_RX_FREE_THRESH_MAX(q),
1747                         FM10K_RX_FREE_THRESH_DIV(q),
1748                         rx_free_thresh)) {
1749                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1750                         "less than or equal to %u, "
1751                         "greater than or equal to %u, "
1752                         "and a divisor of %u",
1753                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1754                         FM10K_RX_FREE_THRESH_MIN(q),
1755                         FM10K_RX_FREE_THRESH_DIV(q));
1756                 return -EINVAL;
1757         }
1758
1759         q->alloc_thresh = rx_free_thresh;
1760         q->drop_en = conf->rx_drop_en;
1761         q->rx_deferred_start = conf->rx_deferred_start;
1762
1763         return 0;
1764 }
1765
1766 /*
1767  * Hardware requires specific alignment for Rx packet buffers. At
1768  * least one of the following two conditions must be satisfied.
1769  *  1. Address is 512B aligned
1770  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1771  *
1772  * As such, the driver may need to adjust the DMA address within the
1773  * buffer by up to 512B.
1774  *
1775  * return 1 if the element size is valid, otherwise return 0.
1776  */
1777 static int
1778 mempool_element_size_valid(struct rte_mempool *mp)
1779 {
1780         uint32_t min_size;
1781
1782         /* elt_size includes mbuf header and headroom */
1783         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1784                         RTE_PKTMBUF_HEADROOM;
1785
1786         /* account for up to 512B of alignment */
1787         min_size -= FM10K_RX_DATABUF_ALIGN;
1788
1789         /* sanity check for overflow */
1790         if (min_size > mp->elt_size)
1791                 return 0;
1792
1793         /* size is valid */
1794         return 1;
1795 }
1796
1797 static int
1798 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1799         uint16_t nb_desc, unsigned int socket_id,
1800         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1801 {
1802         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1803         struct fm10k_dev_info *dev_info =
1804                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
1805         struct fm10k_rx_queue *q;
1806         const struct rte_memzone *mz;
1807
1808         PMD_INIT_FUNC_TRACE();
1809
1810         /* make sure the mempool element size can account for alignment. */
1811         if (!mempool_element_size_valid(mp)) {
1812                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1813                 return -EINVAL;
1814         }
1815
1816         /* make sure a valid number of descriptors have been requested */
1817         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1818                                 FM10K_MULT_RX_DESC, nb_desc)) {
1819                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1820                         "less than or equal to %"PRIu32", "
1821                         "greater than or equal to %u, "
1822                         "and a multiple of %u",
1823                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1824                         FM10K_MULT_RX_DESC);
1825                 return -EINVAL;
1826         }
1827
1828         /*
1829          * if this queue existed already, free the associated memory. The
1830          * queue cannot be reused in case we need to allocate memory on
1831          * different socket than was previously used.
1832          */
1833         if (dev->data->rx_queues[queue_id] != NULL) {
1834                 rx_queue_free(dev->data->rx_queues[queue_id]);
1835                 dev->data->rx_queues[queue_id] = NULL;
1836         }
1837
1838         /* allocate memory for the queue structure */
1839         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1840                                 socket_id);
1841         if (q == NULL) {
1842                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1843                 return -ENOMEM;
1844         }
1845
1846         /* setup queue */
1847         q->mp = mp;
1848         q->nb_desc = nb_desc;
1849         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1850         q->port_id = dev->data->port_id;
1851         q->queue_id = queue_id;
1852         q->tail_ptr = (volatile uint32_t *)
1853                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1854         if (handle_rxconf(q, conf))
1855                 return -EINVAL;
1856
1857         /* allocate memory for the software ring */
1858         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1859                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1860                         RTE_CACHE_LINE_SIZE, socket_id);
1861         if (q->sw_ring == NULL) {
1862                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1863                 rte_free(q);
1864                 return -ENOMEM;
1865         }
1866
1867         /*
1868          * allocate memory for the hardware descriptor ring. A memzone large
1869          * enough to hold the maximum ring size is requested to allow for
1870          * resizing in later calls to the queue setup function.
1871          */
1872         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1873                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1874                                       socket_id);
1875         if (mz == NULL) {
1876                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1877                 rte_free(q->sw_ring);
1878                 rte_free(q);
1879                 return -ENOMEM;
1880         }
1881         q->hw_ring = mz->addr;
1882         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1883
1884         /* Check if number of descs satisfied Vector requirement */
1885         if (!rte_is_power_of_2(nb_desc)) {
1886                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1887                                     "preconditions - canceling the feature for "
1888                                     "the whole port[%d]",
1889                              q->queue_id, q->port_id);
1890                 dev_info->rx_vec_allowed = false;
1891         } else
1892                 fm10k_rxq_vec_setup(q);
1893
1894         dev->data->rx_queues[queue_id] = q;
1895         return 0;
1896 }
1897
1898 static void
1899 fm10k_rx_queue_release(void *queue)
1900 {
1901         PMD_INIT_FUNC_TRACE();
1902
1903         rx_queue_free(queue);
1904 }
1905
1906 static inline int
1907 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1908 {
1909         uint16_t tx_free_thresh;
1910         uint16_t tx_rs_thresh;
1911
1912         /* constraint MACROs require that tx_free_thresh is configured
1913          * before tx_rs_thresh */
1914         if (conf->tx_free_thresh == 0)
1915                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1916         else
1917                 tx_free_thresh = conf->tx_free_thresh;
1918
1919         /* make sure the requested threshold satisfies the constraints */
1920         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1921                         FM10K_TX_FREE_THRESH_MAX(q),
1922                         FM10K_TX_FREE_THRESH_DIV(q),
1923                         tx_free_thresh)) {
1924                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1925                         "less than or equal to %u, "
1926                         "greater than or equal to %u, "
1927                         "and a divisor of %u",
1928                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1929                         FM10K_TX_FREE_THRESH_MIN(q),
1930                         FM10K_TX_FREE_THRESH_DIV(q));
1931                 return -EINVAL;
1932         }
1933
1934         q->free_thresh = tx_free_thresh;
1935
1936         if (conf->tx_rs_thresh == 0)
1937                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1938         else
1939                 tx_rs_thresh = conf->tx_rs_thresh;
1940
1941         q->tx_deferred_start = conf->tx_deferred_start;
1942
1943         /* make sure the requested threshold satisfies the constraints */
1944         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1945                         FM10K_TX_RS_THRESH_MAX(q),
1946                         FM10K_TX_RS_THRESH_DIV(q),
1947                         tx_rs_thresh)) {
1948                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1949                         "less than or equal to %u, "
1950                         "greater than or equal to %u, "
1951                         "and a divisor of %u",
1952                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1953                         FM10K_TX_RS_THRESH_MIN(q),
1954                         FM10K_TX_RS_THRESH_DIV(q));
1955                 return -EINVAL;
1956         }
1957
1958         q->rs_thresh = tx_rs_thresh;
1959
1960         return 0;
1961 }
1962
1963 static int
1964 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1965         uint16_t nb_desc, unsigned int socket_id,
1966         const struct rte_eth_txconf *conf)
1967 {
1968         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1969         struct fm10k_tx_queue *q;
1970         const struct rte_memzone *mz;
1971
1972         PMD_INIT_FUNC_TRACE();
1973
1974         /* make sure a valid number of descriptors have been requested */
1975         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1976                                 FM10K_MULT_TX_DESC, nb_desc)) {
1977                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1978                         "less than or equal to %"PRIu32", "
1979                         "greater than or equal to %u, "
1980                         "and a multiple of %u",
1981                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1982                         FM10K_MULT_TX_DESC);
1983                 return -EINVAL;
1984         }
1985
1986         /*
1987          * if this queue existed already, free the associated memory. The
1988          * queue cannot be reused in case we need to allocate memory on
1989          * different socket than was previously used.
1990          */
1991         if (dev->data->tx_queues[queue_id] != NULL) {
1992                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1993
1994                 tx_queue_free(txq);
1995                 dev->data->tx_queues[queue_id] = NULL;
1996         }
1997
1998         /* allocate memory for the queue structure */
1999         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2000                                 socket_id);
2001         if (q == NULL) {
2002                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2003                 return -ENOMEM;
2004         }
2005
2006         /* setup queue */
2007         q->nb_desc = nb_desc;
2008         q->port_id = dev->data->port_id;
2009         q->queue_id = queue_id;
2010         q->txq_flags = conf->txq_flags;
2011         q->ops = &def_txq_ops;
2012         q->tail_ptr = (volatile uint32_t *)
2013                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2014         if (handle_txconf(q, conf))
2015                 return -EINVAL;
2016
2017         /* allocate memory for the software ring */
2018         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2019                                         nb_desc * sizeof(struct rte_mbuf *),
2020                                         RTE_CACHE_LINE_SIZE, socket_id);
2021         if (q->sw_ring == NULL) {
2022                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2023                 rte_free(q);
2024                 return -ENOMEM;
2025         }
2026
2027         /*
2028          * allocate memory for the hardware descriptor ring. A memzone large
2029          * enough to hold the maximum ring size is requested to allow for
2030          * resizing in later calls to the queue setup function.
2031          */
2032         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2033                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2034                                       socket_id);
2035         if (mz == NULL) {
2036                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2037                 rte_free(q->sw_ring);
2038                 rte_free(q);
2039                 return -ENOMEM;
2040         }
2041         q->hw_ring = mz->addr;
2042         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2043
2044         /*
2045          * allocate memory for the RS bit tracker. Enough slots to hold the
2046          * descriptor index for each RS bit needing to be set are required.
2047          */
2048         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2049                                 ((nb_desc + 1) / q->rs_thresh) *
2050                                 sizeof(uint16_t),
2051                                 RTE_CACHE_LINE_SIZE, socket_id);
2052         if (q->rs_tracker.list == NULL) {
2053                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2054                 rte_free(q->sw_ring);
2055                 rte_free(q);
2056                 return -ENOMEM;
2057         }
2058
2059         dev->data->tx_queues[queue_id] = q;
2060         return 0;
2061 }
2062
2063 static void
2064 fm10k_tx_queue_release(void *queue)
2065 {
2066         struct fm10k_tx_queue *q = queue;
2067         PMD_INIT_FUNC_TRACE();
2068
2069         tx_queue_free(q);
2070 }
2071
2072 static int
2073 fm10k_reta_update(struct rte_eth_dev *dev,
2074                         struct rte_eth_rss_reta_entry64 *reta_conf,
2075                         uint16_t reta_size)
2076 {
2077         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         uint16_t i, j, idx, shift;
2079         uint8_t mask;
2080         uint32_t reta;
2081
2082         PMD_INIT_FUNC_TRACE();
2083
2084         if (reta_size > FM10K_MAX_RSS_INDICES) {
2085                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2086                         "(%d) doesn't match the number hardware can supported "
2087                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2088                 return -EINVAL;
2089         }
2090
2091         /*
2092          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2093          * 128-entries in 32 registers
2094          */
2095         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2096                 idx = i / RTE_RETA_GROUP_SIZE;
2097                 shift = i % RTE_RETA_GROUP_SIZE;
2098                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2099                                 BIT_MASK_PER_UINT32);
2100                 if (mask == 0)
2101                         continue;
2102
2103                 reta = 0;
2104                 if (mask != BIT_MASK_PER_UINT32)
2105                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2106
2107                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2108                         if (mask & (0x1 << j)) {
2109                                 if (mask != 0xF)
2110                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2111                                 reta |= reta_conf[idx].reta[shift + j] <<
2112                                                 (CHAR_BIT * j);
2113                         }
2114                 }
2115                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2116         }
2117
2118         return 0;
2119 }
2120
2121 static int
2122 fm10k_reta_query(struct rte_eth_dev *dev,
2123                         struct rte_eth_rss_reta_entry64 *reta_conf,
2124                         uint16_t reta_size)
2125 {
2126         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127         uint16_t i, j, idx, shift;
2128         uint8_t mask;
2129         uint32_t reta;
2130
2131         PMD_INIT_FUNC_TRACE();
2132
2133         if (reta_size < FM10K_MAX_RSS_INDICES) {
2134                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2135                         "(%d) doesn't match the number hardware can supported "
2136                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2137                 return -EINVAL;
2138         }
2139
2140         /*
2141          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2142          * 128-entries in 32 registers
2143          */
2144         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2145                 idx = i / RTE_RETA_GROUP_SIZE;
2146                 shift = i % RTE_RETA_GROUP_SIZE;
2147                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2148                                 BIT_MASK_PER_UINT32);
2149                 if (mask == 0)
2150                         continue;
2151
2152                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2153                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2154                         if (mask & (0x1 << j))
2155                                 reta_conf[idx].reta[shift + j] = ((reta >>
2156                                         CHAR_BIT * j) & UINT8_MAX);
2157                 }
2158         }
2159
2160         return 0;
2161 }
2162
2163 static int
2164 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2165         struct rte_eth_rss_conf *rss_conf)
2166 {
2167         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2169         uint32_t mrqc;
2170         uint64_t hf = rss_conf->rss_hf;
2171         int i;
2172
2173         PMD_INIT_FUNC_TRACE();
2174
2175         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2176                                 FM10K_RSSRK_ENTRIES_PER_REG))
2177                 return -EINVAL;
2178
2179         if (hf == 0)
2180                 return -EINVAL;
2181
2182         mrqc = 0;
2183         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2184         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2185         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2186         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2187         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2188         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2189         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2190         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2191         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2192
2193         /* If the mapping doesn't fit any supported, return */
2194         if (mrqc == 0)
2195                 return -EINVAL;
2196
2197         if (key != NULL)
2198                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2199                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2200
2201         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2202
2203         return 0;
2204 }
2205
2206 static int
2207 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2208         struct rte_eth_rss_conf *rss_conf)
2209 {
2210         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2212         uint32_t mrqc;
2213         uint64_t hf;
2214         int i;
2215
2216         PMD_INIT_FUNC_TRACE();
2217
2218         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2219                                 FM10K_RSSRK_ENTRIES_PER_REG))
2220                 return -EINVAL;
2221
2222         if (key != NULL)
2223                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2224                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2225
2226         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2227         hf = 0;
2228         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2229         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2230         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2231         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2232         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2233         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2234         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2235         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2236         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2237
2238         rss_conf->rss_hf = hf;
2239
2240         return 0;
2241 }
2242
2243 static void
2244 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2245 {
2246         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2248
2249         /* Bind all local non-queue interrupt to vector 0 */
2250         int_map |= FM10K_MISC_VEC_ID;
2251
2252         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2253         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2254         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2255         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2256         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2257         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2258
2259         /* Enable misc causes */
2260         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2261                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2262                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2263                                 FM10K_EIMR_ENABLE(MAILBOX) |
2264                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2265                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2266                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2267                                 FM10K_EIMR_ENABLE(VFLR));
2268
2269         /* Enable ITR 0 */
2270         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2271                                         FM10K_ITR_MASK_CLEAR);
2272         FM10K_WRITE_FLUSH(hw);
2273 }
2274
2275 static void
2276 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2277 {
2278         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2280
2281         int_map |= FM10K_MISC_VEC_ID;
2282
2283         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2284         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2285         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2286         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2287         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2288         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2289
2290         /* Disable misc causes */
2291         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2292                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2293                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2294                                 FM10K_EIMR_DISABLE(MAILBOX) |
2295                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2296                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2297                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2298                                 FM10K_EIMR_DISABLE(VFLR));
2299
2300         /* Disable ITR 0 */
2301         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2302         FM10K_WRITE_FLUSH(hw);
2303 }
2304
2305 static void
2306 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2307 {
2308         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2310
2311         /* Bind all local non-queue interrupt to vector 0 */
2312         int_map |= FM10K_MISC_VEC_ID;
2313
2314         /* Only INT 0 available, other 15 are reserved. */
2315         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2316
2317         /* Enable ITR 0 */
2318         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2319                                         FM10K_ITR_MASK_CLEAR);
2320         FM10K_WRITE_FLUSH(hw);
2321 }
2322
2323 static void
2324 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2325 {
2326         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2327         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2328
2329         int_map |= FM10K_MISC_VEC_ID;
2330
2331         /* Only INT 0 available, other 15 are reserved. */
2332         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2333
2334         /* Disable ITR 0 */
2335         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2336         FM10K_WRITE_FLUSH(hw);
2337 }
2338
2339 static int
2340 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2341 {
2342         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343
2344         /* Enable ITR */
2345         if (hw->mac.type == fm10k_mac_pf)
2346                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2347                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2348         else
2349                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2350                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2351         rte_intr_enable(&dev->pci_dev->intr_handle);
2352         return 0;
2353 }
2354
2355 static int
2356 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2357 {
2358         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359
2360         /* Disable ITR */
2361         if (hw->mac.type == fm10k_mac_pf)
2362                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2363                         FM10K_ITR_MASK_SET);
2364         else
2365                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2366                         FM10K_ITR_MASK_SET);
2367         return 0;
2368 }
2369
2370 static int
2371 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2372 {
2373         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2375         uint32_t intr_vector, vec;
2376         uint16_t queue_id;
2377         int result = 0;
2378
2379         /* fm10k needs one separate interrupt for mailbox,
2380          * so only drivers which support multiple interrupt vectors
2381          * e.g. vfio-pci can work for fm10k interrupt mode
2382          */
2383         if (!rte_intr_cap_multiple(intr_handle) ||
2384                         dev->data->dev_conf.intr_conf.rxq == 0)
2385                 return result;
2386
2387         intr_vector = dev->data->nb_rx_queues;
2388
2389         /* disable interrupt first */
2390         rte_intr_disable(&dev->pci_dev->intr_handle);
2391         if (hw->mac.type == fm10k_mac_pf)
2392                 fm10k_dev_disable_intr_pf(dev);
2393         else
2394                 fm10k_dev_disable_intr_vf(dev);
2395
2396         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2397                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2398                 result = -EIO;
2399         }
2400
2401         if (rte_intr_dp_is_en(intr_handle) && !result) {
2402                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2403                         dev->data->nb_rx_queues * sizeof(int), 0);
2404                 if (intr_handle->intr_vec) {
2405                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2406                                         queue_id < dev->data->nb_rx_queues;
2407                                         queue_id++) {
2408                                 intr_handle->intr_vec[queue_id] = vec;
2409                                 if (vec < intr_handle->nb_efd - 1
2410                                                 + FM10K_RX_VEC_START)
2411                                         vec++;
2412                         }
2413                 } else {
2414                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2415                                 " intr_vec", dev->data->nb_rx_queues);
2416                         rte_intr_efd_disable(intr_handle);
2417                         result = -ENOMEM;
2418                 }
2419         }
2420
2421         if (hw->mac.type == fm10k_mac_pf)
2422                 fm10k_dev_enable_intr_pf(dev);
2423         else
2424                 fm10k_dev_enable_intr_vf(dev);
2425         rte_intr_enable(&dev->pci_dev->intr_handle);
2426         hw->mac.ops.update_int_moderator(hw);
2427         return result;
2428 }
2429
2430 static int
2431 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2432 {
2433         struct fm10k_fault fault;
2434         int err;
2435         const char *estr = "Unknown error";
2436
2437         /* Process PCA fault */
2438         if (eicr & FM10K_EICR_PCA_FAULT) {
2439                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2440                 if (err)
2441                         goto error;
2442                 switch (fault.type) {
2443                 case PCA_NO_FAULT:
2444                         estr = "PCA_NO_FAULT"; break;
2445                 case PCA_UNMAPPED_ADDR:
2446                         estr = "PCA_UNMAPPED_ADDR"; break;
2447                 case PCA_BAD_QACCESS_PF:
2448                         estr = "PCA_BAD_QACCESS_PF"; break;
2449                 case PCA_BAD_QACCESS_VF:
2450                         estr = "PCA_BAD_QACCESS_VF"; break;
2451                 case PCA_MALICIOUS_REQ:
2452                         estr = "PCA_MALICIOUS_REQ"; break;
2453                 case PCA_POISONED_TLP:
2454                         estr = "PCA_POISONED_TLP"; break;
2455                 case PCA_TLP_ABORT:
2456                         estr = "PCA_TLP_ABORT"; break;
2457                 default:
2458                         goto error;
2459                 }
2460                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2461                         estr, fault.func ? "VF" : "PF", fault.func,
2462                         fault.address, fault.specinfo);
2463         }
2464
2465         /* Process THI fault */
2466         if (eicr & FM10K_EICR_THI_FAULT) {
2467                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2468                 if (err)
2469                         goto error;
2470                 switch (fault.type) {
2471                 case THI_NO_FAULT:
2472                         estr = "THI_NO_FAULT"; break;
2473                 case THI_MAL_DIS_Q_FAULT:
2474                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2475                 default:
2476                         goto error;
2477                 }
2478                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2479                         estr, fault.func ? "VF" : "PF", fault.func,
2480                         fault.address, fault.specinfo);
2481         }
2482
2483         /* Process FUM fault */
2484         if (eicr & FM10K_EICR_FUM_FAULT) {
2485                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2486                 if (err)
2487                         goto error;
2488                 switch (fault.type) {
2489                 case FUM_NO_FAULT:
2490                         estr = "FUM_NO_FAULT"; break;
2491                 case FUM_UNMAPPED_ADDR:
2492                         estr = "FUM_UNMAPPED_ADDR"; break;
2493                 case FUM_POISONED_TLP:
2494                         estr = "FUM_POISONED_TLP"; break;
2495                 case FUM_BAD_VF_QACCESS:
2496                         estr = "FUM_BAD_VF_QACCESS"; break;
2497                 case FUM_ADD_DECODE_ERR:
2498                         estr = "FUM_ADD_DECODE_ERR"; break;
2499                 case FUM_RO_ERROR:
2500                         estr = "FUM_RO_ERROR"; break;
2501                 case FUM_QPRC_CRC_ERROR:
2502                         estr = "FUM_QPRC_CRC_ERROR"; break;
2503                 case FUM_CSR_TIMEOUT:
2504                         estr = "FUM_CSR_TIMEOUT"; break;
2505                 case FUM_INVALID_TYPE:
2506                         estr = "FUM_INVALID_TYPE"; break;
2507                 case FUM_INVALID_LENGTH:
2508                         estr = "FUM_INVALID_LENGTH"; break;
2509                 case FUM_INVALID_BE:
2510                         estr = "FUM_INVALID_BE"; break;
2511                 case FUM_INVALID_ALIGN:
2512                         estr = "FUM_INVALID_ALIGN"; break;
2513                 default:
2514                         goto error;
2515                 }
2516                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2517                         estr, fault.func ? "VF" : "PF", fault.func,
2518                         fault.address, fault.specinfo);
2519         }
2520
2521         return 0;
2522 error:
2523         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2524         return err;
2525 }
2526
2527 /**
2528  * PF interrupt handler triggered by NIC for handling specific interrupt.
2529  *
2530  * @param handle
2531  *  Pointer to interrupt handle.
2532  * @param param
2533  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2534  *
2535  * @return
2536  *  void
2537  */
2538 static void
2539 fm10k_dev_interrupt_handler_pf(
2540                         __rte_unused struct rte_intr_handle *handle,
2541                         void *param)
2542 {
2543         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2544         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545         uint32_t cause, status;
2546
2547         if (hw->mac.type != fm10k_mac_pf)
2548                 return;
2549
2550         cause = FM10K_READ_REG(hw, FM10K_EICR);
2551
2552         /* Handle PCI fault cases */
2553         if (cause & FM10K_EICR_FAULT_MASK) {
2554                 PMD_INIT_LOG(ERR, "INT: find fault!");
2555                 fm10k_dev_handle_fault(hw, cause);
2556         }
2557
2558         /* Handle switch up/down */
2559         if (cause & FM10K_EICR_SWITCHNOTREADY)
2560                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2561
2562         if (cause & FM10K_EICR_SWITCHREADY)
2563                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2564
2565         /* Handle mailbox message */
2566         fm10k_mbx_lock(hw);
2567         hw->mbx.ops.process(hw, &hw->mbx);
2568         fm10k_mbx_unlock(hw);
2569
2570         /* Handle SRAM error */
2571         if (cause & FM10K_EICR_SRAMERROR) {
2572                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2573
2574                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2575                 /* Write to clear pending bits */
2576                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2577
2578                 /* Todo: print out error message after shared code  updates */
2579         }
2580
2581         /* Clear these 3 events if having any */
2582         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2583                  FM10K_EICR_SWITCHREADY;
2584         if (cause)
2585                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2586
2587         /* Re-enable interrupt from device side */
2588         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2589                                         FM10K_ITR_MASK_CLEAR);
2590         /* Re-enable interrupt from host side */
2591         rte_intr_enable(&(dev->pci_dev->intr_handle));
2592 }
2593
2594 /**
2595  * VF interrupt handler triggered by NIC for handling specific interrupt.
2596  *
2597  * @param handle
2598  *  Pointer to interrupt handle.
2599  * @param param
2600  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2601  *
2602  * @return
2603  *  void
2604  */
2605 static void
2606 fm10k_dev_interrupt_handler_vf(
2607                         __rte_unused struct rte_intr_handle *handle,
2608                         void *param)
2609 {
2610         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2611         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612
2613         if (hw->mac.type != fm10k_mac_vf)
2614                 return;
2615
2616         /* Handle mailbox message if lock is acquired */
2617         fm10k_mbx_lock(hw);
2618         hw->mbx.ops.process(hw, &hw->mbx);
2619         fm10k_mbx_unlock(hw);
2620
2621         /* Re-enable interrupt from device side */
2622         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2623                                         FM10K_ITR_MASK_CLEAR);
2624         /* Re-enable interrupt from host side */
2625         rte_intr_enable(&(dev->pci_dev->intr_handle));
2626 }
2627
2628 /* Mailbox message handler in VF */
2629 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2630         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2631         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2632         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2633         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2634 };
2635
2636 static int
2637 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2638 {
2639         int err = 0;
2640
2641         /* Initialize mailbox lock */
2642         fm10k_mbx_initlock(hw);
2643
2644         /* Replace default message handler with new ones */
2645         if (hw->mac.type == fm10k_mac_vf)
2646                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2647
2648         if (err) {
2649                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2650                                 err);
2651                 return err;
2652         }
2653         /* Connect to SM for PF device or PF for VF device */
2654         return hw->mbx.ops.connect(hw, &hw->mbx);
2655 }
2656
2657 static void
2658 fm10k_close_mbx_service(struct fm10k_hw *hw)
2659 {
2660         /* Disconnect from SM for PF device or PF for VF device */
2661         hw->mbx.ops.disconnect(hw, &hw->mbx);
2662 }
2663
2664 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2665         .dev_configure          = fm10k_dev_configure,
2666         .dev_start              = fm10k_dev_start,
2667         .dev_stop               = fm10k_dev_stop,
2668         .dev_close              = fm10k_dev_close,
2669         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2670         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2671         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2672         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2673         .stats_get              = fm10k_stats_get,
2674         .xstats_get             = fm10k_xstats_get,
2675         .xstats_get_names       = fm10k_xstats_get_names,
2676         .stats_reset            = fm10k_stats_reset,
2677         .xstats_reset           = fm10k_stats_reset,
2678         .link_update            = fm10k_link_update,
2679         .dev_infos_get          = fm10k_dev_infos_get,
2680         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2681         .vlan_filter_set        = fm10k_vlan_filter_set,
2682         .vlan_offload_set       = fm10k_vlan_offload_set,
2683         .mac_addr_add           = fm10k_macaddr_add,
2684         .mac_addr_remove        = fm10k_macaddr_remove,
2685         .rx_queue_start         = fm10k_dev_rx_queue_start,
2686         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2687         .tx_queue_start         = fm10k_dev_tx_queue_start,
2688         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2689         .rx_queue_setup         = fm10k_rx_queue_setup,
2690         .rx_queue_release       = fm10k_rx_queue_release,
2691         .tx_queue_setup         = fm10k_tx_queue_setup,
2692         .tx_queue_release       = fm10k_tx_queue_release,
2693         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2694         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2695         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2696         .reta_update            = fm10k_reta_update,
2697         .reta_query             = fm10k_reta_query,
2698         .rss_hash_update        = fm10k_rss_hash_update,
2699         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2700 };
2701
2702 static int ftag_check_handler(__rte_unused const char *key,
2703                 const char *value, __rte_unused void *opaque)
2704 {
2705         if (strcmp(value, "1"))
2706                 return -1;
2707
2708         return 0;
2709 }
2710
2711 static int
2712 fm10k_check_ftag(struct rte_devargs *devargs)
2713 {
2714         struct rte_kvargs *kvlist;
2715         const char *ftag_key = "enable_ftag";
2716
2717         if (devargs == NULL)
2718                 return 0;
2719
2720         kvlist = rte_kvargs_parse(devargs->args, NULL);
2721         if (kvlist == NULL)
2722                 return 0;
2723
2724         if (!rte_kvargs_count(kvlist, ftag_key)) {
2725                 rte_kvargs_free(kvlist);
2726                 return 0;
2727         }
2728         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2729         if (rte_kvargs_process(kvlist, ftag_key,
2730                                 ftag_check_handler, NULL) < 0) {
2731                 rte_kvargs_free(kvlist);
2732                 return 0;
2733         }
2734         rte_kvargs_free(kvlist);
2735
2736         return 1;
2737 }
2738
2739 static void __attribute__((cold))
2740 fm10k_set_tx_function(struct rte_eth_dev *dev)
2741 {
2742         struct fm10k_tx_queue *txq;
2743         int i;
2744         int use_sse = 1;
2745         uint16_t tx_ftag_en = 0;
2746
2747         if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2748                 tx_ftag_en = 1;
2749
2750         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2751                 txq = dev->data->tx_queues[i];
2752                 txq->tx_ftag_en = tx_ftag_en;
2753                 /* Check if Vector Tx is satisfied */
2754                 if (fm10k_tx_vec_condition_check(txq))
2755                         use_sse = 0;
2756         }
2757
2758         if (use_sse) {
2759                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2760                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2761                         txq = dev->data->tx_queues[i];
2762                         fm10k_txq_vec_setup(txq);
2763                 }
2764                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2765         } else {
2766                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2767                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2768         }
2769 }
2770
2771 static void __attribute__((cold))
2772 fm10k_set_rx_function(struct rte_eth_dev *dev)
2773 {
2774         struct fm10k_dev_info *dev_info =
2775                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2776         uint16_t i, rx_using_sse;
2777         uint16_t rx_ftag_en = 0;
2778
2779         if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2780                 rx_ftag_en = 1;
2781
2782         /* In order to allow Vector Rx there are a few configuration
2783          * conditions to be met.
2784          */
2785         if (!fm10k_rx_vec_condition_check(dev) &&
2786                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2787                 if (dev->data->scattered_rx)
2788                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2789                 else
2790                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2791         } else if (dev->data->scattered_rx)
2792                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2793         else
2794                 dev->rx_pkt_burst = fm10k_recv_pkts;
2795
2796         rx_using_sse =
2797                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2798                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2799
2800         if (rx_using_sse)
2801                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2802         else
2803                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2804
2805         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2806                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2807
2808                 rxq->rx_using_sse = rx_using_sse;
2809                 rxq->rx_ftag_en = rx_ftag_en;
2810         }
2811 }
2812
2813 static void
2814 fm10k_params_init(struct rte_eth_dev *dev)
2815 {
2816         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817         struct fm10k_dev_info *info =
2818                 FM10K_DEV_PRIVATE_TO_INFO(dev->data->dev_private);
2819
2820         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2821          * there is no way to get link status without reading BAR4.  Until this
2822          * works, assume we have maximum bandwidth.
2823          * @todo - fix bus info
2824          */
2825         hw->bus_caps.speed = fm10k_bus_speed_8000;
2826         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2827         hw->bus_caps.payload = fm10k_bus_payload_512;
2828         hw->bus.speed = fm10k_bus_speed_8000;
2829         hw->bus.width = fm10k_bus_width_pcie_x8;
2830         hw->bus.payload = fm10k_bus_payload_256;
2831
2832         info->rx_vec_allowed = true;
2833 }
2834
2835 static int
2836 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2837 {
2838         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839         int diag, i;
2840         struct fm10k_macvlan_filter_info *macvlan;
2841
2842         PMD_INIT_FUNC_TRACE();
2843
2844         dev->dev_ops = &fm10k_eth_dev_ops;
2845         dev->rx_pkt_burst = &fm10k_recv_pkts;
2846         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2847
2848         /* only initialize in the primary process */
2849         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2850                 return 0;
2851
2852         rte_eth_copy_pci_info(dev, dev->pci_dev);
2853
2854         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2855         memset(macvlan, 0, sizeof(*macvlan));
2856         /* Vendor and Device ID need to be set before init of shared code */
2857         memset(hw, 0, sizeof(*hw));
2858         hw->device_id = dev->pci_dev->id.device_id;
2859         hw->vendor_id = dev->pci_dev->id.vendor_id;
2860         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
2861         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
2862         hw->revision_id = 0;
2863         hw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;
2864         if (hw->hw_addr == NULL) {
2865                 PMD_INIT_LOG(ERR, "Bad mem resource."
2866                         " Try to blacklist unused devices.");
2867                 return -EIO;
2868         }
2869
2870         /* Store fm10k_adapter pointer */
2871         hw->back = dev->data->dev_private;
2872
2873         /* Initialize the shared code */
2874         diag = fm10k_init_shared_code(hw);
2875         if (diag != FM10K_SUCCESS) {
2876                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2877                 return -EIO;
2878         }
2879
2880         /* Initialize parameters */
2881         fm10k_params_init(dev);
2882
2883         /* Initialize the hw */
2884         diag = fm10k_init_hw(hw);
2885         if (diag != FM10K_SUCCESS) {
2886                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2887                 return -EIO;
2888         }
2889
2890         /* Initialize MAC address(es) */
2891         dev->data->mac_addrs = rte_zmalloc("fm10k",
2892                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2893         if (dev->data->mac_addrs == NULL) {
2894                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2895                 return -ENOMEM;
2896         }
2897
2898         diag = fm10k_read_mac_addr(hw);
2899
2900         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2901                         &dev->data->mac_addrs[0]);
2902
2903         if (diag != FM10K_SUCCESS ||
2904                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2905
2906                 /* Generate a random addr */
2907                 eth_random_addr(hw->mac.addr);
2908                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2909                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2910                 &dev->data->mac_addrs[0]);
2911         }
2912
2913         /* Reset the hw statistics */
2914         fm10k_stats_reset(dev);
2915
2916         /* Reset the hw */
2917         diag = fm10k_reset_hw(hw);
2918         if (diag != FM10K_SUCCESS) {
2919                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2920                 return -EIO;
2921         }
2922
2923         /* Setup mailbox service */
2924         diag = fm10k_setup_mbx_service(hw);
2925         if (diag != FM10K_SUCCESS) {
2926                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2927                 return -EIO;
2928         }
2929
2930         /*PF/VF has different interrupt handling mechanism */
2931         if (hw->mac.type == fm10k_mac_pf) {
2932                 /* register callback func to eal lib */
2933                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2934                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2935
2936                 /* enable MISC interrupt */
2937                 fm10k_dev_enable_intr_pf(dev);
2938         } else { /* VF */
2939                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2940                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2941
2942                 fm10k_dev_enable_intr_vf(dev);
2943         }
2944
2945         /* Enable intr after callback registered */
2946         rte_intr_enable(&(dev->pci_dev->intr_handle));
2947
2948         hw->mac.ops.update_int_moderator(hw);
2949
2950         /* Make sure Switch Manager is ready before going forward. */
2951         if (hw->mac.type == fm10k_mac_pf) {
2952                 int switch_ready = 0;
2953
2954                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2955                         fm10k_mbx_lock(hw);
2956                         hw->mac.ops.get_host_state(hw, &switch_ready);
2957                         fm10k_mbx_unlock(hw);
2958                         if (switch_ready)
2959                                 break;
2960                         /* Delay some time to acquire async LPORT_MAP info. */
2961                         rte_delay_us(WAIT_SWITCH_MSG_US);
2962                 }
2963
2964                 if (switch_ready == 0) {
2965                         PMD_INIT_LOG(ERR, "switch is not ready");
2966                         return -1;
2967                 }
2968         }
2969
2970         /*
2971          * Below function will trigger operations on mailbox, acquire lock to
2972          * avoid race condition from interrupt handler. Operations on mailbox
2973          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2974          * will handle and generate an interrupt to our side. Then,  FIFO in
2975          * mailbox will be touched.
2976          */
2977         fm10k_mbx_lock(hw);
2978         /* Enable port first */
2979         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2980                                         MAX_LPORT_NUM, 1);
2981
2982         /* Set unicast mode by default. App can change to other mode in other
2983          * API func.
2984          */
2985         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2986                                         FM10K_XCAST_MODE_NONE);
2987
2988         fm10k_mbx_unlock(hw);
2989
2990         /* Make sure default VID is ready before going forward. */
2991         if (hw->mac.type == fm10k_mac_pf) {
2992                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2993                         if (hw->mac.default_vid)
2994                                 break;
2995                         /* Delay some time to acquire async port VLAN info. */
2996                         rte_delay_us(WAIT_SWITCH_MSG_US);
2997                 }
2998
2999                 if (!hw->mac.default_vid) {
3000                         PMD_INIT_LOG(ERR, "default VID is not ready");
3001                         return -1;
3002                 }
3003         }
3004
3005         /* Add default mac address */
3006         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3007                 MAIN_VSI_POOL_NUMBER);
3008
3009         return 0;
3010 }
3011
3012 static int
3013 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3014 {
3015         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3016
3017         PMD_INIT_FUNC_TRACE();
3018
3019         /* only uninitialize in the primary process */
3020         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3021                 return 0;
3022
3023         /* safe to close dev here */
3024         fm10k_dev_close(dev);
3025
3026         dev->dev_ops = NULL;
3027         dev->rx_pkt_burst = NULL;
3028         dev->tx_pkt_burst = NULL;
3029
3030         /* disable uio/vfio intr */
3031         rte_intr_disable(&(dev->pci_dev->intr_handle));
3032
3033         /*PF/VF has different interrupt handling mechanism */
3034         if (hw->mac.type == fm10k_mac_pf) {
3035                 /* disable interrupt */
3036                 fm10k_dev_disable_intr_pf(dev);
3037
3038                 /* unregister callback func to eal lib */
3039                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3040                         fm10k_dev_interrupt_handler_pf, (void *)dev);
3041         } else {
3042                 /* disable interrupt */
3043                 fm10k_dev_disable_intr_vf(dev);
3044
3045                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3046                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3047         }
3048
3049         /* free mac memory */
3050         if (dev->data->mac_addrs) {
3051                 rte_free(dev->data->mac_addrs);
3052                 dev->data->mac_addrs = NULL;
3053         }
3054
3055         memset(hw, 0, sizeof(*hw));
3056
3057         return 0;
3058 }
3059
3060 /*
3061  * The set of PCI devices this driver supports. This driver will enable both PF
3062  * and SRIOV-VF devices.
3063  */
3064 static const struct rte_pci_id pci_id_fm10k_map[] = {
3065         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3066         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3067         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3068         { .vendor_id = 0, /* sentinel */ },
3069 };
3070
3071 static struct eth_driver rte_pmd_fm10k = {
3072         .pci_drv = {
3073                 .id_table = pci_id_fm10k_map,
3074                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3075                         RTE_PCI_DRV_DETACHABLE,
3076                 .probe = rte_eth_dev_pci_probe,
3077                 .remove = rte_eth_dev_pci_remove,
3078         },
3079         .eth_dev_init = eth_fm10k_dev_init,
3080         .eth_dev_uninit = eth_fm10k_dev_uninit,
3081         .dev_private_size = sizeof(struct fm10k_adapter),
3082 };
3083
3084 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k.pci_drv);
3085 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);