drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_malloc.h>
  36 #include <rte_memzone.h>
  37 #include <rte_string_fns.h>
  38 #include <rte_dev.h>
  39 #include <rte_spinlock.h>
  40 #include <rte_kvargs.h>
  41
  42 #include "fm10k.h"
  43 #include "base/fm10k_api.h"
  44
  45 /* Default delay to acquire mailbox lock */
  46 #define FM10K_MBXLOCK_DELAY_US 20
  47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  48
  49 #define MAIN_VSI_POOL_NUMBER 0
  50
  51 /* Max try times to acquire switch status */
  52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  53 /* Wait interval to get switch status */
  54 #define WAIT_SWITCH_MSG_US    100000
  55 /* A period of quiescence for switch */
  56 #define FM10K_SWITCH_QUIESCE_US 10000
  57 /* Number of chars per uint32 type */
  58 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  59 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  60
  61 /* default 1:1 map from queue ID to interrupt vector ID */
  62 #define Q2V(dev, queue_id) (dev->pci_dev->intr_handle.intr_vec[queue_id])
  63
  64 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  65 #define MAX_LPORT_NUM    128
  66 #define GLORT_FD_Q_BASE  0x40
  67 #define GLORT_PF_MASK    0xFFC0
  68 #define GLORT_FD_MASK    GLORT_PF_MASK
  69 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  70
  71 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  72 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  73 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  74 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  75 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  76 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  77 static int
  78 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  79 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  80         const u8 *mac, bool add, uint32_t pool);
  81 static void fm10k_tx_queue_release(void *queue);
  82 static void fm10k_rx_queue_release(void *queue);
  83 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  84 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  85 static int fm10k_check_ftag(struct rte_devargs *devargs);
  86
  87 struct fm10k_xstats_name_off {
  88         char name[RTE_ETH_XSTATS_NAME_SIZE];
  89         unsigned offset;
  90 };
  91
  92 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  93         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  94         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  95         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  96         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  97         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  98         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
  99         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
 100         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
 101                 nodesc_drop)},
 102 };
 103
 104 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 105                 sizeof(fm10k_hw_stats_strings[0]))
 106
 107 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 108         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 109         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 110         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 111 };
 112
 113 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 114                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 115
 116 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 117         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 118         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 119 };
 120
 121 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 122                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 123
 124 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 125                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 126 static int
 127 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 128
 129 static void
 130 fm10k_mbx_initlock(struct fm10k_hw *hw)
 131 {
 132         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 133 }
 134
 135 static void
 136 fm10k_mbx_lock(struct fm10k_hw *hw)
 137 {
 138         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 139                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 140 }
 141
 142 static void
 143 fm10k_mbx_unlock(struct fm10k_hw *hw)
 144 {
 145         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 146 }
 147
 148 /* Stubs needed for linkage when vPMD is disabled */
 149 int __attribute__((weak))
 150 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 151 {
 152         return -1;
 153 }
 154
 155 uint16_t __attribute__((weak))
 156 fm10k_recv_pkts_vec(
 157         __rte_unused void *rx_queue,
 158         __rte_unused struct rte_mbuf **rx_pkts,
 159         __rte_unused uint16_t nb_pkts)
 160 {
 161         return 0;
 162 }
 163
 164 uint16_t __attribute__((weak))
 165 fm10k_recv_scattered_pkts_vec(
 166                 __rte_unused void *rx_queue,
 167                 __rte_unused struct rte_mbuf **rx_pkts,
 168                 __rte_unused uint16_t nb_pkts)
 169 {
 170         return 0;
 171 }
 172
 173 int __attribute__((weak))
 174 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 175
 176 {
 177         return -1;
 178 }
 179
 180 void __attribute__((weak))
 181 fm10k_rx_queue_release_mbufs_vec(
 182                 __rte_unused struct fm10k_rx_queue *rxq)
 183 {
 184         return;
 185 }
 186
 187 void __attribute__((weak))
 188 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 189 {
 190         return;
 191 }
 192
 193 int __attribute__((weak))
 194 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 195 {
 196         return -1;
 197 }
 198
 199 uint16_t __attribute__((weak))
 200 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
 201                 __rte_unused struct rte_mbuf **tx_pkts,
 202                 __rte_unused uint16_t nb_pkts)
 203 {
 204         return 0;
 205 }
 206
 207 /*
 208  * reset queue to initial state, allocate software buffers used when starting
 209  * device.
 210  * return 0 on success
 211  * return -ENOMEM if buffers cannot be allocated
 212  * return -EINVAL if buffers do not satisfy alignment condition
 213  */
 214 static inline int
 215 rx_queue_reset(struct fm10k_rx_queue *q)
 216 {
 217         static const union fm10k_rx_desc zero = {{0} };
 218         uint64_t dma_addr;
 219         int i, diag;
 220         PMD_INIT_FUNC_TRACE();
 221
 222         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 223         if (diag != 0)
 224                 return -ENOMEM;
 225
 226         for (i = 0; i < q->nb_desc; ++i) {
 227                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 228                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 229                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 230                                                 q->nb_desc);
 231                         return -EINVAL;
 232                 }
 233                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 234                 q->hw_ring[i].q.pkt_addr = dma_addr;
 235                 q->hw_ring[i].q.hdr_addr = dma_addr;
 236         }
 237
 238         /* initialize extra software ring entries. Space for these extra
 239          * entries is always allocated.
 240          */
 241         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 242         for (i = 0; i < q->nb_fake_desc; ++i) {
 243                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 244                 q->hw_ring[q->nb_desc + i] = zero;
 245         }
 246
 247         q->next_dd = 0;
 248         q->next_alloc = 0;
 249         q->next_trigger = q->alloc_thresh - 1;
 250         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 251         q->rxrearm_start = 0;
 252         q->rxrearm_nb = 0;
 253
 254         return 0;
 255 }
 256
 257 /*
 258  * clean queue, descriptor rings, free software buffers used when stopping
 259  * device.
 260  */
 261 static inline void
 262 rx_queue_clean(struct fm10k_rx_queue *q)
 263 {
 264         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 265         uint32_t i;
 266         PMD_INIT_FUNC_TRACE();
 267
 268         /* zero descriptor rings */
 269         for (i = 0; i < q->nb_desc; ++i)
 270                 q->hw_ring[i] = zero;
 271
 272         /* zero faked descriptors */
 273         for (i = 0; i < q->nb_fake_desc; ++i)
 274                 q->hw_ring[q->nb_desc + i] = zero;
 275
 276         /* vPMD driver has a different way of releasing mbufs. */
 277         if (q->rx_using_sse) {
 278                 fm10k_rx_queue_release_mbufs_vec(q);
 279                 return;
 280         }
 281
 282         /* free software buffers */
 283         for (i = 0; i < q->nb_desc; ++i) {
 284                 if (q->sw_ring[i]) {
 285                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 286                         q->sw_ring[i] = NULL;
 287                 }
 288         }
 289 }
 290
 291 /*
 292  * free all queue memory used when releasing the queue (i.e. configure)
 293  */
 294 static inline void
 295 rx_queue_free(struct fm10k_rx_queue *q)
 296 {
 297         PMD_INIT_FUNC_TRACE();
 298         if (q) {
 299                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 300                 rx_queue_clean(q);
 301                 if (q->sw_ring) {
 302                         rte_free(q->sw_ring);
 303                         q->sw_ring = NULL;
 304                 }
 305                 rte_free(q);
 306                 q = NULL;
 307         }
 308 }
 309
 310 /*
 311  * disable RX queue, wait unitl HW finished necessary flush operation
 312  */
 313 static inline int
 314 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 315 {
 316         uint32_t reg, i;
 317
 318         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 319         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 320                         reg & ~FM10K_RXQCTL_ENABLE);
 321
 322         /* Wait 100us at most */
 323         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 324                 rte_delay_us(1);
 325                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 326                 if (!(reg & FM10K_RXQCTL_ENABLE))
 327                         break;
 328         }
 329
 330         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 331                 return -1;
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * reset queue to initial state, allocate software buffers used when starting
 338  * device
 339  */
 340 static inline void
 341 tx_queue_reset(struct fm10k_tx_queue *q)
 342 {
 343         PMD_INIT_FUNC_TRACE();
 344         q->last_free = 0;
 345         q->next_free = 0;
 346         q->nb_used = 0;
 347         q->nb_free = q->nb_desc - 1;
 348         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 349         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 350 }
 351
 352 /*
 353  * clean queue, descriptor rings, free software buffers used when stopping
 354  * device
 355  */
 356 static inline void
 357 tx_queue_clean(struct fm10k_tx_queue *q)
 358 {
 359         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 360         uint32_t i;
 361         PMD_INIT_FUNC_TRACE();
 362
 363         /* zero descriptor rings */
 364         for (i = 0; i < q->nb_desc; ++i)
 365                 q->hw_ring[i] = zero;
 366
 367         /* free software buffers */
 368         for (i = 0; i < q->nb_desc; ++i) {
 369                 if (q->sw_ring[i]) {
 370                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 371                         q->sw_ring[i] = NULL;
 372                 }
 373         }
 374 }
 375
 376 /*
 377  * free all queue memory used when releasing the queue (i.e. configure)
 378  */
 379 static inline void
 380 tx_queue_free(struct fm10k_tx_queue *q)
 381 {
 382         PMD_INIT_FUNC_TRACE();
 383         if (q) {
 384                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 385                 tx_queue_clean(q);
 386                 if (q->rs_tracker.list) {
 387                         rte_free(q->rs_tracker.list);
 388                         q->rs_tracker.list = NULL;
 389                 }
 390                 if (q->sw_ring) {
 391                         rte_free(q->sw_ring);
 392                         q->sw_ring = NULL;
 393                 }
 394                 rte_free(q);
 395                 q = NULL;
 396         }
 397 }
 398
 399 /*
 400  * disable TX queue, wait unitl HW finished necessary flush operation
 401  */
 402 static inline int
 403 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 404 {
 405         uint32_t reg, i;
 406
 407         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 408         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 409                         reg & ~FM10K_TXDCTL_ENABLE);
 410
 411         /* Wait 100us at most */
 412         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 413                 rte_delay_us(1);
 414                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 415                 if (!(reg & FM10K_TXDCTL_ENABLE))
 416                         break;
 417         }
 418
 419         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 420                 return -1;
 421
 422         return 0;
 423 }
 424
 425 static int
 426 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 427 {
 428         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 429         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 430         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 431         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 432
 433         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 434
 435         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 436                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 437                 return -EINVAL;
 438         }
 439
 440         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 441                 return 0;
 442
 443         if (hw->mac.type == fm10k_mac_vf) {
 444                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 445                 return -EINVAL;
 446         }
 447
 448         /* Check VMDQ queue pool number */
 449         if (vmdq_conf->nb_queue_pools >
 450                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 451                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 452                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 453                         vmdq_conf->nb_queue_pools);
 454                 return -EINVAL;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static const struct fm10k_txq_ops def_txq_ops = {
 461         .reset = tx_queue_reset,
 462 };
 463
 464 static int
 465 fm10k_dev_configure(struct rte_eth_dev *dev)
 466 {
 467         int ret;
 468
 469         PMD_INIT_FUNC_TRACE();
 470
 471         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 472                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 473         /* multipe queue mode checking */
 474         ret  = fm10k_check_mq_mode(dev);
 475         if (ret != 0) {
 476                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 477                             ret);
 478                 return ret;
 479         }
 480
 481         return 0;
 482 }
 483
 484 /* fls = find last set bit = 32 minus the number of leading zeros */
 485 #ifndef fls
 486 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 487 #endif
 488
 489 static void
 490 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 491 {
 492         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 493         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 494         uint32_t i;
 495
 496         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 497
 498         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 499                 if (!vmdq_conf->pool_map[i].pools)
 500                         continue;
 501                 fm10k_mbx_lock(hw);
 502                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 503                 fm10k_mbx_unlock(hw);
 504         }
 505 }
 506
 507 static void
 508 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 509 {
 510         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 511
 512         /* Add default mac address */
 513         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 514                 MAIN_VSI_POOL_NUMBER);
 515 }
 516
 517 static void
 518 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 519 {
 520         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 521         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 522         uint32_t mrqc, *key, i, reta, j;
 523         uint64_t hf;
 524
 525 #define RSS_KEY_SIZE 40
 526         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 527                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 528                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 529                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 530                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 531                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 532         };
 533
 534         if (dev->data->nb_rx_queues == 1 ||
 535             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 536             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 537                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 538                 return;
 539         }
 540
 541         /* random key is rss_intel_key (default) or user provided (rss_key) */
 542         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 543                 key = (uint32_t *)rss_intel_key;
 544         else
 545                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 546
 547         /* Now fill our hash function seeds, 4 bytes at a time */
 548         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 549                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 550
 551         /*
 552          * Fill in redirection table
 553          * The byte-swap is needed because NIC registers are in
 554          * little-endian order.
 555          */
 556         reta = 0;
 557         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 558                 if (j == dev->data->nb_rx_queues)
 559                         j = 0;
 560                 reta = (reta << CHAR_BIT) | j;
 561                 if ((i & 3) == 3)
 562                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 563                                         rte_bswap32(reta));
 564         }
 565
 566         /*
 567          * Generate RSS hash based on packet types, TCP/UDP
 568          * port numbers and/or IPv4/v6 src and dst addresses
 569          */
 570         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 571         mrqc = 0;
 572         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 573         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 574         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 575         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 577         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 579         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 580         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 581
 582         if (mrqc == 0) {
 583                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 584                         "supported", hf);
 585                 return;
 586         }
 587
 588         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 589 }
 590
 591 static void
 592 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 593 {
 594         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 595         uint32_t i;
 596
 597         for (i = 0; i < nb_lport_new; i++) {
 598                 /* Set unicast mode by default. App can change
 599                  * to other mode in other API func.
 600                  */
 601                 fm10k_mbx_lock(hw);
 602                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 603                         FM10K_XCAST_MODE_NONE);
 604                 fm10k_mbx_unlock(hw);
 605         }
 606 }
 607
 608 static void
 609 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 610 {
 611         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 612         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 613         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 614         struct fm10k_macvlan_filter_info *macvlan;
 615         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 616         uint16_t nb_lport_new;
 617
 618         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 619         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 620
 621         fm10k_dev_rss_configure(dev);
 622
 623         /* only PF supports VMDQ */
 624         if (hw->mac.type != fm10k_mac_pf)
 625                 return;
 626
 627         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 628                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 629
 630         /* no pool number change, no need to update logic port and VLAN/MAC */
 631         if (macvlan->nb_queue_pools == nb_queue_pools)
 632                 return;
 633
 634         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 635         fm10k_dev_logic_port_update(dev, nb_lport_new);
 636
 637         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 638         memset(dev->data->mac_addrs, 0,
 639                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 640         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 641                 &dev->data->mac_addrs[0]);
 642         memset(macvlan, 0, sizeof(*macvlan));
 643         macvlan->nb_queue_pools = nb_queue_pools;
 644
 645         if (nb_queue_pools)
 646                 fm10k_dev_vmdq_rx_configure(dev);
 647         else
 648                 fm10k_dev_pf_main_vsi_reset(dev);
 649 }
 650
 651 static int
 652 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 653 {
 654         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655         int i, ret;
 656         struct fm10k_tx_queue *txq;
 657         uint64_t base_addr;
 658         uint32_t size;
 659
 660         /* Disable TXINT to avoid possible interrupt */
 661         for (i = 0; i < hw->mac.max_queues; i++)
 662                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 663                                 3 << FM10K_TXINT_TIMER_SHIFT);
 664
 665         /* Setup TX queue */
 666         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 667                 txq = dev->data->tx_queues[i];
 668                 base_addr = txq->hw_ring_phys_addr;
 669                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 670
 671                 /* disable queue to avoid issues while updating state */
 672                 ret = tx_queue_disable(hw, i);
 673                 if (ret) {
 674                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 675                         return -1;
 676                 }
 677                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 678                  * register is read-only for VF.
 679                  */
 680                 if (fm10k_check_ftag(dev->pci_dev->device.devargs)) {
 681                         if (hw->mac.type == fm10k_mac_pf) {
 682                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 683                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 684                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 685                         } else {
 686                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 687                                 return -ENOTSUP;
 688                         }
 689                 }
 690
 691                 /* set location and size for descriptor ring */
 692                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 693                                 base_addr & UINT64_LOWER_32BITS_MASK);
 694                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 695                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 696                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 697
 698                 /* assign default SGLORT for each TX queue by PF */
 699                 if (hw->mac.type == fm10k_mac_pf)
 700                         FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 701         }
 702
 703         /* set up vector or scalar TX function as appropriate */
 704         fm10k_set_tx_function(dev);
 705
 706         return 0;
 707 }
 708
 709 static int
 710 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 711 {
 712         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 713         struct fm10k_macvlan_filter_info *macvlan;
 714         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 715         int i, ret;
 716         struct fm10k_rx_queue *rxq;
 717         uint64_t base_addr;
 718         uint32_t size;
 719         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 720         uint32_t logic_port = hw->mac.dglort_map;
 721         uint16_t buf_size;
 722         uint16_t queue_stride = 0;
 723
 724         /* enable RXINT for interrupt mode */
 725         i = 0;
 726         if (rte_intr_dp_is_en(intr_handle)) {
 727                 for (; i < dev->data->nb_rx_queues; i++) {
 728                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(dev, i));
 729                         if (hw->mac.type == fm10k_mac_pf)
 730                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
 731                                         FM10K_ITR_AUTOMASK |
 732                                         FM10K_ITR_MASK_CLEAR);
 733                         else
 734                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
 735                                         FM10K_ITR_AUTOMASK |
 736                                         FM10K_ITR_MASK_CLEAR);
 737                 }
 738         }
 739         /* Disable other RXINT to avoid possible interrupt */
 740         for (; i < hw->mac.max_queues; i++)
 741                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 742                         3 << FM10K_RXINT_TIMER_SHIFT);
 743
 744         /* Setup RX queues */
 745         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 746                 rxq = dev->data->rx_queues[i];
 747                 base_addr = rxq->hw_ring_phys_addr;
 748                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 749
 750                 /* disable queue to avoid issues while updating state */
 751                 ret = rx_queue_disable(hw, i);
 752                 if (ret) {
 753                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 754                         return -1;
 755                 }
 756
 757                 /* Setup the Base and Length of the Rx Descriptor Ring */
 758                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 759                                 base_addr & UINT64_LOWER_32BITS_MASK);
 760                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 761                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 762                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 763
 764                 /* Configure the Rx buffer size for one buff without split */
 765                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 766                         RTE_PKTMBUF_HEADROOM);
 767                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 768                  * reserved for this purpose, and the worst case could be 511B.
 769                  * But SRR reg assumes all buffers have the same size. In order
 770                  * to fill the gap, we'll have to consider the worst case and
 771                  * assume 512B is reserved. If we don't do so, it's possible
 772                  * for HW to overwrite data to next mbuf.
 773                  */
 774                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 775
 776                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 777                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 778                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 779
 780                 /* It adds dual VLAN length for supporting dual VLAN */
 781                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 782                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 783                         dev->data->dev_conf.rxmode.enable_scatter) {
 784                         uint32_t reg;
 785                         dev->data->scattered_rx = 1;
 786                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 787                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 788                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 789                 }
 790
 791                 /* Enable drop on empty, it's RO for VF */
 792                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 793                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 794
 795                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 796                 FM10K_WRITE_FLUSH(hw);
 797         }
 798
 799         /* Configure VMDQ/RSS if applicable */
 800         fm10k_dev_mq_rx_configure(dev);
 801
 802         /* Decide the best RX function */
 803         fm10k_set_rx_function(dev);
 804
 805         /* update RX_SGLORT for loopback suppress*/
 806         if (hw->mac.type != fm10k_mac_pf)
 807                 return 0;
 808         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 809         if (macvlan->nb_queue_pools)
 810                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 811         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 812                 if (i && queue_stride && !(i % queue_stride))
 813                         logic_port++;
 814                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 815         }
 816
 817         return 0;
 818 }
 819
 820 static int
 821 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 822 {
 823         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 824         int err = -1;
 825         uint32_t reg;
 826         struct fm10k_rx_queue *rxq;
 827
 828         PMD_INIT_FUNC_TRACE();
 829
 830         if (rx_queue_id < dev->data->nb_rx_queues) {
 831                 rxq = dev->data->rx_queues[rx_queue_id];
 832                 err = rx_queue_reset(rxq);
 833                 if (err == -ENOMEM) {
 834                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 835                         return err;
 836                 } else if (err == -EINVAL) {
 837                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 838                                 " %d", err);
 839                         return err;
 840                 }
 841
 842                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 843                  * Note: this must be done AFTER the queue is enabled on real
 844                  * hardware, but BEFORE the queue is enabled when using the
 845                  * emulation platform. Do it in both places for now and remove
 846                  * this comment and the following two register writes when the
 847                  * emulation platform is no longer being used.
 848                  */
 849                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 850                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 851
 852                 /* Set PF ownership flag for PF devices */
 853                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 854                 if (hw->mac.type == fm10k_mac_pf)
 855                         reg |= FM10K_RXQCTL_PF;
 856                 reg |= FM10K_RXQCTL_ENABLE;
 857                 /* enable RX queue */
 858                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 859                 FM10K_WRITE_FLUSH(hw);
 860
 861                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 862                  * Note: this must be done AFTER the queue is enabled
 863                  */
 864                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 865                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 866                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 867         }
 868
 869         return err;
 870 }
 871
 872 static int
 873 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 874 {
 875         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 876
 877         PMD_INIT_FUNC_TRACE();
 878
 879         if (rx_queue_id < dev->data->nb_rx_queues) {
 880                 /* Disable RX queue */
 881                 rx_queue_disable(hw, rx_queue_id);
 882
 883                 /* Free mbuf and clean HW ring */
 884                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 885                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int
 892 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 893 {
 894         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 895         /** @todo - this should be defined in the shared code */
 896 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 897         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 898         int err = 0;
 899
 900         PMD_INIT_FUNC_TRACE();
 901
 902         if (tx_queue_id < dev->data->nb_tx_queues) {
 903                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 904
 905                 q->ops->reset(q);
 906
 907                 /* reset head and tail pointers */
 908                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 909                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 910
 911                 /* enable TX queue */
 912                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 913                                         FM10K_TXDCTL_ENABLE | txdctl);
 914                 FM10K_WRITE_FLUSH(hw);
 915                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 916         } else
 917                 err = -1;
 918
 919         return err;
 920 }
 921
 922 static int
 923 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 924 {
 925         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 926
 927         PMD_INIT_FUNC_TRACE();
 928
 929         if (tx_queue_id < dev->data->nb_tx_queues) {
 930                 tx_queue_disable(hw, tx_queue_id);
 931                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 932                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 939 {
 940         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 941                 != FM10K_DGLORTMAP_NONE);
 942 }
 943
 944 static void
 945 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 946 {
 947         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 948         int status;
 949
 950         PMD_INIT_FUNC_TRACE();
 951
 952         /* Return if it didn't acquire valid glort range */
 953         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 954                 return;
 955
 956         fm10k_mbx_lock(hw);
 957         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 958                                 FM10K_XCAST_MODE_PROMISC);
 959         fm10k_mbx_unlock(hw);
 960
 961         if (status != FM10K_SUCCESS)
 962                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 963 }
 964
 965 static void
 966 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 967 {
 968         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 969         uint8_t mode;
 970         int status;
 971
 972         PMD_INIT_FUNC_TRACE();
 973
 974         /* Return if it didn't acquire valid glort range */
 975         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 976                 return;
 977
 978         if (dev->data->all_multicast == 1)
 979                 mode = FM10K_XCAST_MODE_ALLMULTI;
 980         else
 981                 mode = FM10K_XCAST_MODE_NONE;
 982
 983         fm10k_mbx_lock(hw);
 984         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 985                                 mode);
 986         fm10k_mbx_unlock(hw);
 987
 988         if (status != FM10K_SUCCESS)
 989                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 990 }
 991
 992 static void
 993 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 994 {
 995         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 996         int status;
 997
 998         PMD_INIT_FUNC_TRACE();
 999
1000         /* Return if it didn't acquire valid glort range */
1001         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1002                 return;
1003
1004         /* If promiscuous mode is enabled, it doesn't make sense to enable
1005          * allmulticast and disable promiscuous since fm10k only can select
1006          * one of the modes.
1007          */
1008         if (dev->data->promiscuous) {
1009                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1010                         "needn't enable allmulticast");
1011                 return;
1012         }
1013
1014         fm10k_mbx_lock(hw);
1015         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1016                                 FM10K_XCAST_MODE_ALLMULTI);
1017         fm10k_mbx_unlock(hw);
1018
1019         if (status != FM10K_SUCCESS)
1020                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1021 }
1022
1023 static void
1024 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1025 {
1026         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027         int status;
1028
1029         PMD_INIT_FUNC_TRACE();
1030
1031         /* Return if it didn't acquire valid glort range */
1032         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1033                 return;
1034
1035         if (dev->data->promiscuous) {
1036                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1037                         "since promisc mode is enabled");
1038                 return;
1039         }
1040
1041         fm10k_mbx_lock(hw);
1042         /* Change mode to unicast mode */
1043         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1044                                 FM10K_XCAST_MODE_NONE);
1045         fm10k_mbx_unlock(hw);
1046
1047         if (status != FM10K_SUCCESS)
1048                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1049 }
1050
1051 static void
1052 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1053 {
1054         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1056         uint16_t nb_queue_pools;
1057         struct fm10k_macvlan_filter_info *macvlan;
1058
1059         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1060         nb_queue_pools = macvlan->nb_queue_pools;
1061         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1062         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1063
1064         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1065         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1066         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1067                         hw->mac.dglort_map;
1068         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1069         /* Configure VMDQ/RSS DGlort Decoder */
1070         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1071
1072         /* Flow Director configurations, only queue number is valid. */
1073         dglortdec = fls(dev->data->nb_rx_queues - 1);
1074         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1075                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1076         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1077         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1078
1079         /* Invalidate all other GLORT entries */
1080         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1081                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1082                                 FM10K_DGLORTMAP_NONE);
1083 }
1084
1085 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1086 static int
1087 fm10k_dev_start(struct rte_eth_dev *dev)
1088 {
1089         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090         int i, diag;
1091
1092         PMD_INIT_FUNC_TRACE();
1093
1094         /* stop, init, then start the hw */
1095         diag = fm10k_stop_hw(hw);
1096         if (diag != FM10K_SUCCESS) {
1097                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1098                 return -EIO;
1099         }
1100
1101         diag = fm10k_init_hw(hw);
1102         if (diag != FM10K_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1104                 return -EIO;
1105         }
1106
1107         diag = fm10k_start_hw(hw);
1108         if (diag != FM10K_SUCCESS) {
1109                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1110                 return -EIO;
1111         }
1112
1113         diag = fm10k_dev_tx_init(dev);
1114         if (diag) {
1115                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1116                 return diag;
1117         }
1118
1119         if (fm10k_dev_rxq_interrupt_setup(dev))
1120                 return -EIO;
1121
1122         diag = fm10k_dev_rx_init(dev);
1123         if (diag) {
1124                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1125                 return diag;
1126         }
1127
1128         if (hw->mac.type == fm10k_mac_pf)
1129                 fm10k_dev_dglort_map_configure(dev);
1130
1131         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1132                 struct fm10k_rx_queue *rxq;
1133                 rxq = dev->data->rx_queues[i];
1134
1135                 if (rxq->rx_deferred_start)
1136                         continue;
1137                 diag = fm10k_dev_rx_queue_start(dev, i);
1138                 if (diag != 0) {
1139                         int j;
1140                         for (j = 0; j < i; ++j)
1141                                 rx_queue_clean(dev->data->rx_queues[j]);
1142                         return diag;
1143                 }
1144         }
1145
1146         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1147                 struct fm10k_tx_queue *txq;
1148                 txq = dev->data->tx_queues[i];
1149
1150                 if (txq->tx_deferred_start)
1151                         continue;
1152                 diag = fm10k_dev_tx_queue_start(dev, i);
1153                 if (diag != 0) {
1154                         int j;
1155                         for (j = 0; j < i; ++j)
1156                                 tx_queue_clean(dev->data->tx_queues[j]);
1157                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1158                                 rx_queue_clean(dev->data->rx_queues[j]);
1159                         return diag;
1160                 }
1161         }
1162
1163         /* Update default vlan when not in VMDQ mode */
1164         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1165                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1166
1167         return 0;
1168 }
1169
1170 static void
1171 fm10k_dev_stop(struct rte_eth_dev *dev)
1172 {
1173         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1174         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1175         int i;
1176
1177         PMD_INIT_FUNC_TRACE();
1178
1179         if (dev->data->tx_queues)
1180                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1181                         fm10k_dev_tx_queue_stop(dev, i);
1182
1183         if (dev->data->rx_queues)
1184                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1185                         fm10k_dev_rx_queue_stop(dev, i);
1186
1187         /* Disable datapath event */
1188         if (rte_intr_dp_is_en(intr_handle)) {
1189                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1190                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1191                                 3 << FM10K_RXINT_TIMER_SHIFT);
1192                         if (hw->mac.type == fm10k_mac_pf)
1193                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
1194                                         FM10K_ITR_MASK_SET);
1195                         else
1196                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
1197                                         FM10K_ITR_MASK_SET);
1198                 }
1199         }
1200         /* Clean datapath event and queue/vec mapping */
1201         rte_intr_efd_disable(intr_handle);
1202         rte_free(intr_handle->intr_vec);
1203         intr_handle->intr_vec = NULL;
1204 }
1205
1206 static void
1207 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1208 {
1209         int i;
1210
1211         PMD_INIT_FUNC_TRACE();
1212
1213         if (dev->data->tx_queues) {
1214                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1215                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1216
1217                         tx_queue_free(txq);
1218                 }
1219         }
1220
1221         if (dev->data->rx_queues) {
1222                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1223                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1224         }
1225 }
1226
1227 static void
1228 fm10k_dev_close(struct rte_eth_dev *dev)
1229 {
1230         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231
1232         PMD_INIT_FUNC_TRACE();
1233
1234         fm10k_mbx_lock(hw);
1235         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1236                 MAX_LPORT_NUM, false);
1237         fm10k_mbx_unlock(hw);
1238
1239         /* allow 10ms for device to quiesce */
1240         rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1241
1242         /* Stop mailbox service first */
1243         fm10k_close_mbx_service(hw);
1244         fm10k_dev_stop(dev);
1245         fm10k_dev_queue_release(dev);
1246         fm10k_stop_hw(hw);
1247 }
1248
1249 static int
1250 fm10k_link_update(struct rte_eth_dev *dev,
1251         __rte_unused int wait_to_complete)
1252 {
1253         PMD_INIT_FUNC_TRACE();
1254
1255         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1256          * x8 PCIe interface. For now, we leave the speed undefined since there
1257          * is no 50Gbps Ethernet. */
1258         dev->data->dev_link.link_speed  = 0;
1259         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1260         dev->data->dev_link.link_status = ETH_LINK_UP;
1261
1262         return 0;
1263 }
1264
1265 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1266         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1267 {
1268         unsigned i, q;
1269         unsigned count = 0;
1270
1271         if (xstats_names != NULL) {
1272                 /* Note: limit checked in rte_eth_xstats_names() */
1273
1274                 /* Global stats */
1275                 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1276                         snprintf(xstats_names[count].name,
1277                                 sizeof(xstats_names[count].name),
1278                                 "%s", fm10k_hw_stats_strings[count].name);
1279                         count++;
1280                 }
1281
1282                 /* PF queue stats */
1283                 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1284                         for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1285                                 snprintf(xstats_names[count].name,
1286                                         sizeof(xstats_names[count].name),
1287                                         "rx_q%u_%s", q,
1288                                         fm10k_hw_stats_rx_q_strings[i].name);
1289                                 count++;
1290                         }
1291                         for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1292                                 snprintf(xstats_names[count].name,
1293                                         sizeof(xstats_names[count].name),
1294                                         "tx_q%u_%s", q,
1295                                         fm10k_hw_stats_tx_q_strings[i].name);
1296                                 count++;
1297                         }
1298                 }
1299         }
1300         return FM10K_NB_XSTATS;
1301 }
1302
1303 static int
1304 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1305                  unsigned n)
1306 {
1307         struct fm10k_hw_stats *hw_stats =
1308                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1309         unsigned i, q, count = 0;
1310
1311         if (n < FM10K_NB_XSTATS)
1312                 return FM10K_NB_XSTATS;
1313
1314         /* Global stats */
1315         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1316                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1317                         fm10k_hw_stats_strings[count].offset);
1318                 xstats[count].id = count;
1319                 count++;
1320         }
1321
1322         /* PF queue stats */
1323         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1324                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1325                         xstats[count].value =
1326                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1327                                 fm10k_hw_stats_rx_q_strings[i].offset);
1328                         xstats[count].id = count;
1329                         count++;
1330                 }
1331                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1332                         xstats[count].value =
1333                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1334                                 fm10k_hw_stats_tx_q_strings[i].offset);
1335                         xstats[count].id = count;
1336                         count++;
1337                 }
1338         }
1339
1340         return FM10K_NB_XSTATS;
1341 }
1342
1343 static void
1344 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1345 {
1346         uint64_t ipackets, opackets, ibytes, obytes;
1347         struct fm10k_hw *hw =
1348                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         struct fm10k_hw_stats *hw_stats =
1350                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1351         int i;
1352
1353         PMD_INIT_FUNC_TRACE();
1354
1355         fm10k_update_hw_stats(hw, hw_stats);
1356
1357         ipackets = opackets = ibytes = obytes = 0;
1358         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1359                 (i < hw->mac.max_queues); ++i) {
1360                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1361                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1362                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1363                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1364                 ipackets += stats->q_ipackets[i];
1365                 opackets += stats->q_opackets[i];
1366                 ibytes   += stats->q_ibytes[i];
1367                 obytes   += stats->q_obytes[i];
1368         }
1369         stats->ipackets = ipackets;
1370         stats->opackets = opackets;
1371         stats->ibytes = ibytes;
1372         stats->obytes = obytes;
1373 }
1374
1375 static void
1376 fm10k_stats_reset(struct rte_eth_dev *dev)
1377 {
1378         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379         struct fm10k_hw_stats *hw_stats =
1380                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1381
1382         PMD_INIT_FUNC_TRACE();
1383
1384         memset(hw_stats, 0, sizeof(*hw_stats));
1385         fm10k_rebind_hw_stats(hw, hw_stats);
1386 }
1387
1388 static void
1389 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1390         struct rte_eth_dev_info *dev_info)
1391 {
1392         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1393
1394         PMD_INIT_FUNC_TRACE();
1395
1396         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1397         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1398         dev_info->max_rx_queues      = hw->mac.max_queues;
1399         dev_info->max_tx_queues      = hw->mac.max_queues;
1400         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1401         dev_info->max_hash_mac_addrs = 0;
1402         dev_info->max_vfs            = dev->pci_dev->max_vfs;
1403         dev_info->vmdq_pool_base     = 0;
1404         dev_info->vmdq_queue_base    = 0;
1405         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1406         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1407         dev_info->rx_offload_capa =
1408                 DEV_RX_OFFLOAD_VLAN_STRIP |
1409                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1410                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1411                 DEV_RX_OFFLOAD_TCP_CKSUM;
1412         dev_info->tx_offload_capa =
1413                 DEV_TX_OFFLOAD_VLAN_INSERT |
1414                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1415                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1416                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1417                 DEV_TX_OFFLOAD_TCP_TSO;
1418
1419         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1420         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1421
1422         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1423                 .rx_thresh = {
1424                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1425                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1426                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1427                 },
1428                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1429                 .rx_drop_en = 0,
1430         };
1431
1432         dev_info->default_txconf = (struct rte_eth_txconf) {
1433                 .tx_thresh = {
1434                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1435                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1436                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1437                 },
1438                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1439                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1440                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1441         };
1442
1443         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1444                 .nb_max = FM10K_MAX_RX_DESC,
1445                 .nb_min = FM10K_MIN_RX_DESC,
1446                 .nb_align = FM10K_MULT_RX_DESC,
1447         };
1448
1449         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1450                 .nb_max = FM10K_MAX_TX_DESC,
1451                 .nb_min = FM10K_MIN_TX_DESC,
1452                 .nb_align = FM10K_MULT_TX_DESC,
1453         };
1454
1455         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1456                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1457                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1458 }
1459
1460 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1461 static const uint32_t *
1462 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1463 {
1464         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1465             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1466                 static uint32_t ptypes[] = {
1467                         /* refers to rx_desc_to_ol_flags() */
1468                         RTE_PTYPE_L2_ETHER,
1469                         RTE_PTYPE_L3_IPV4,
1470                         RTE_PTYPE_L3_IPV4_EXT,
1471                         RTE_PTYPE_L3_IPV6,
1472                         RTE_PTYPE_L3_IPV6_EXT,
1473                         RTE_PTYPE_L4_TCP,
1474                         RTE_PTYPE_L4_UDP,
1475                         RTE_PTYPE_UNKNOWN
1476                 };
1477
1478                 return ptypes;
1479         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1480                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1481                 static uint32_t ptypes_vec[] = {
1482                         /* refers to fm10k_desc_to_pktype_v() */
1483                         RTE_PTYPE_L3_IPV4,
1484                         RTE_PTYPE_L3_IPV4_EXT,
1485                         RTE_PTYPE_L3_IPV6,
1486                         RTE_PTYPE_L3_IPV6_EXT,
1487                         RTE_PTYPE_L4_TCP,
1488                         RTE_PTYPE_L4_UDP,
1489                         RTE_PTYPE_TUNNEL_GENEVE,
1490                         RTE_PTYPE_TUNNEL_NVGRE,
1491                         RTE_PTYPE_TUNNEL_VXLAN,
1492                         RTE_PTYPE_TUNNEL_GRE,
1493                         RTE_PTYPE_UNKNOWN
1494                 };
1495
1496                 return ptypes_vec;
1497         }
1498
1499         return NULL;
1500 }
1501 #else
1502 static const uint32_t *
1503 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1504 {
1505         return NULL;
1506 }
1507 #endif
1508
1509 static int
1510 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1511 {
1512         s32 result;
1513         uint16_t mac_num = 0;
1514         uint32_t vid_idx, vid_bit, mac_index;
1515         struct fm10k_hw *hw;
1516         struct fm10k_macvlan_filter_info *macvlan;
1517         struct rte_eth_dev_data *data = dev->data;
1518
1519         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1520         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1521
1522         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1523                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1524                 return -EINVAL;
1525         }
1526
1527         if (vlan_id > ETH_VLAN_ID_MAX) {
1528                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1529                 return -EINVAL;
1530         }
1531
1532         vid_idx = FM10K_VFTA_IDX(vlan_id);
1533         vid_bit = FM10K_VFTA_BIT(vlan_id);
1534         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1535         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1536                 return 0;
1537         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1538         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1539                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1540                         "in the VLAN filter table");
1541                 return -EINVAL;
1542         }
1543
1544         fm10k_mbx_lock(hw);
1545         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1546         fm10k_mbx_unlock(hw);
1547         if (result != FM10K_SUCCESS) {
1548                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1549                 return -EIO;
1550         }
1551
1552         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1553                         (result == FM10K_SUCCESS); mac_index++) {
1554                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1555                         continue;
1556                 if (mac_num > macvlan->mac_num - 1) {
1557                         PMD_INIT_LOG(ERR, "MAC address number "
1558                                         "not match");
1559                         break;
1560                 }
1561                 fm10k_mbx_lock(hw);
1562                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1563                         data->mac_addrs[mac_index].addr_bytes,
1564                         vlan_id, on, 0);
1565                 fm10k_mbx_unlock(hw);
1566                 mac_num++;
1567         }
1568         if (result != FM10K_SUCCESS) {
1569                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1570                 return -EIO;
1571         }
1572
1573         if (on) {
1574                 macvlan->vlan_num++;
1575                 macvlan->vfta[vid_idx] |= vid_bit;
1576         } else {
1577                 macvlan->vlan_num--;
1578                 macvlan->vfta[vid_idx] &= ~vid_bit;
1579         }
1580         return 0;
1581 }
1582
1583 static void
1584 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1585 {
1586         if (mask & ETH_VLAN_STRIP_MASK) {
1587                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1588                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1589                                         "always on in fm10k");
1590         }
1591
1592         if (mask & ETH_VLAN_EXTEND_MASK) {
1593                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1594                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1595                                         "supported in fm10k");
1596         }
1597
1598         if (mask & ETH_VLAN_FILTER_MASK) {
1599                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1600                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1601         }
1602 }
1603
1604 /* Add/Remove a MAC address, and update filters to main VSI */
1605 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1606                 const u8 *mac, bool add, uint32_t pool)
1607 {
1608         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1609         struct fm10k_macvlan_filter_info *macvlan;
1610         uint32_t i, j, k;
1611
1612         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1613
1614         if (pool != MAIN_VSI_POOL_NUMBER) {
1615                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1616                         "mac to pool %u", pool);
1617                 return;
1618         }
1619         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1620                 if (!macvlan->vfta[j])
1621                         continue;
1622                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1623                         if (!(macvlan->vfta[j] & (1 << k)))
1624                                 continue;
1625                         if (i + 1 > macvlan->vlan_num) {
1626                                 PMD_INIT_LOG(ERR, "vlan number not match");
1627                                 return;
1628                         }
1629                         fm10k_mbx_lock(hw);
1630                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1631                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1632                         fm10k_mbx_unlock(hw);
1633                         i++;
1634                 }
1635         }
1636 }
1637
1638 /* Add/Remove a MAC address, and update filters to VMDQ */
1639 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1640                 const u8 *mac, bool add, uint32_t pool)
1641 {
1642         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643         struct fm10k_macvlan_filter_info *macvlan;
1644         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1645         uint32_t i;
1646
1647         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1648         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1649
1650         if (pool > macvlan->nb_queue_pools) {
1651                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1652                         " Max pool is %u",
1653                         pool, macvlan->nb_queue_pools);
1654                 return;
1655         }
1656         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1657                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1658                         continue;
1659                 fm10k_mbx_lock(hw);
1660                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1661                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1662                 fm10k_mbx_unlock(hw);
1663         }
1664 }
1665
1666 /* Add/Remove a MAC address, and update filters */
1667 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1668                 const u8 *mac, bool add, uint32_t pool)
1669 {
1670         struct fm10k_macvlan_filter_info *macvlan;
1671
1672         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1673
1674         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1675                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1676         else
1677                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1678
1679         if (add)
1680                 macvlan->mac_num++;
1681         else
1682                 macvlan->mac_num--;
1683 }
1684
1685 /* Add a MAC address, and update filters */
1686 static void
1687 fm10k_macaddr_add(struct rte_eth_dev *dev,
1688                 struct ether_addr *mac_addr,
1689                 uint32_t index,
1690                 uint32_t pool)
1691 {
1692         struct fm10k_macvlan_filter_info *macvlan;
1693
1694         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1695         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1696         macvlan->mac_vmdq_id[index] = pool;
1697 }
1698
1699 /* Remove a MAC address, and update filters */
1700 static void
1701 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1702 {
1703         struct rte_eth_dev_data *data = dev->data;
1704         struct fm10k_macvlan_filter_info *macvlan;
1705
1706         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1707         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1708                         FALSE, macvlan->mac_vmdq_id[index]);
1709         macvlan->mac_vmdq_id[index] = 0;
1710 }
1711
1712 static inline int
1713 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1714 {
1715         if ((request < min) || (request > max) || ((request % mult) != 0))
1716                 return -1;
1717         else
1718                 return 0;
1719 }
1720
1721
1722 static inline int
1723 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1724 {
1725         if ((request < min) || (request > max) || ((div % request) != 0))
1726                 return -1;
1727         else
1728                 return 0;
1729 }
1730
1731 static inline int
1732 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1733 {
1734         uint16_t rx_free_thresh;
1735
1736         if (conf->rx_free_thresh == 0)
1737                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1738         else
1739                 rx_free_thresh = conf->rx_free_thresh;
1740
1741         /* make sure the requested threshold satisfies the constraints */
1742         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1743                         FM10K_RX_FREE_THRESH_MAX(q),
1744                         FM10K_RX_FREE_THRESH_DIV(q),
1745                         rx_free_thresh)) {
1746                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1747                         "less than or equal to %u, "
1748                         "greater than or equal to %u, "
1749                         "and a divisor of %u",
1750                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1751                         FM10K_RX_FREE_THRESH_MIN(q),
1752                         FM10K_RX_FREE_THRESH_DIV(q));
1753                 return -EINVAL;
1754         }
1755
1756         q->alloc_thresh = rx_free_thresh;
1757         q->drop_en = conf->rx_drop_en;
1758         q->rx_deferred_start = conf->rx_deferred_start;
1759
1760         return 0;
1761 }
1762
1763 /*
1764  * Hardware requires specific alignment for Rx packet buffers. At
1765  * least one of the following two conditions must be satisfied.
1766  *  1. Address is 512B aligned
1767  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1768  *
1769  * As such, the driver may need to adjust the DMA address within the
1770  * buffer by up to 512B.
1771  *
1772  * return 1 if the element size is valid, otherwise return 0.
1773  */
1774 static int
1775 mempool_element_size_valid(struct rte_mempool *mp)
1776 {
1777         uint32_t min_size;
1778
1779         /* elt_size includes mbuf header and headroom */
1780         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1781                         RTE_PKTMBUF_HEADROOM;
1782
1783         /* account for up to 512B of alignment */
1784         min_size -= FM10K_RX_DATABUF_ALIGN;
1785
1786         /* sanity check for overflow */
1787         if (min_size > mp->elt_size)
1788                 return 0;
1789
1790         /* size is valid */
1791         return 1;
1792 }
1793
1794 static int
1795 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1796         uint16_t nb_desc, unsigned int socket_id,
1797         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1798 {
1799         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
1801         struct fm10k_rx_queue *q;
1802         const struct rte_memzone *mz;
1803
1804         PMD_INIT_FUNC_TRACE();
1805
1806         /* make sure the mempool element size can account for alignment. */
1807         if (!mempool_element_size_valid(mp)) {
1808                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1809                 return -EINVAL;
1810         }
1811
1812         /* make sure a valid number of descriptors have been requested */
1813         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1814                                 FM10K_MULT_RX_DESC, nb_desc)) {
1815                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1816                         "less than or equal to %"PRIu32", "
1817                         "greater than or equal to %u, "
1818                         "and a multiple of %u",
1819                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1820                         FM10K_MULT_RX_DESC);
1821                 return -EINVAL;
1822         }
1823
1824         /*
1825          * if this queue existed already, free the associated memory. The
1826          * queue cannot be reused in case we need to allocate memory on
1827          * different socket than was previously used.
1828          */
1829         if (dev->data->rx_queues[queue_id] != NULL) {
1830                 rx_queue_free(dev->data->rx_queues[queue_id]);
1831                 dev->data->rx_queues[queue_id] = NULL;
1832         }
1833
1834         /* allocate memory for the queue structure */
1835         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1836                                 socket_id);
1837         if (q == NULL) {
1838                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1839                 return -ENOMEM;
1840         }
1841
1842         /* setup queue */
1843         q->mp = mp;
1844         q->nb_desc = nb_desc;
1845         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1846         q->port_id = dev->data->port_id;
1847         q->queue_id = queue_id;
1848         q->tail_ptr = (volatile uint32_t *)
1849                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1850         if (handle_rxconf(q, conf))
1851                 return -EINVAL;
1852
1853         /* allocate memory for the software ring */
1854         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1855                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1856                         RTE_CACHE_LINE_SIZE, socket_id);
1857         if (q->sw_ring == NULL) {
1858                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1859                 rte_free(q);
1860                 return -ENOMEM;
1861         }
1862
1863         /*
1864          * allocate memory for the hardware descriptor ring. A memzone large
1865          * enough to hold the maximum ring size is requested to allow for
1866          * resizing in later calls to the queue setup function.
1867          */
1868         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1869                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1870                                       socket_id);
1871         if (mz == NULL) {
1872                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1873                 rte_free(q->sw_ring);
1874                 rte_free(q);
1875                 return -ENOMEM;
1876         }
1877         q->hw_ring = mz->addr;
1878         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1879
1880         /* Check if number of descs satisfied Vector requirement */
1881         if (!rte_is_power_of_2(nb_desc)) {
1882                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1883                                     "preconditions - canceling the feature for "
1884                                     "the whole port[%d]",
1885                              q->queue_id, q->port_id);
1886                 dev_info->rx_vec_allowed = false;
1887         } else
1888                 fm10k_rxq_vec_setup(q);
1889
1890         dev->data->rx_queues[queue_id] = q;
1891         return 0;
1892 }
1893
1894 static void
1895 fm10k_rx_queue_release(void *queue)
1896 {
1897         PMD_INIT_FUNC_TRACE();
1898
1899         rx_queue_free(queue);
1900 }
1901
1902 static inline int
1903 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1904 {
1905         uint16_t tx_free_thresh;
1906         uint16_t tx_rs_thresh;
1907
1908         /* constraint MACROs require that tx_free_thresh is configured
1909          * before tx_rs_thresh */
1910         if (conf->tx_free_thresh == 0)
1911                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1912         else
1913                 tx_free_thresh = conf->tx_free_thresh;
1914
1915         /* make sure the requested threshold satisfies the constraints */
1916         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1917                         FM10K_TX_FREE_THRESH_MAX(q),
1918                         FM10K_TX_FREE_THRESH_DIV(q),
1919                         tx_free_thresh)) {
1920                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1921                         "less than or equal to %u, "
1922                         "greater than or equal to %u, "
1923                         "and a divisor of %u",
1924                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1925                         FM10K_TX_FREE_THRESH_MIN(q),
1926                         FM10K_TX_FREE_THRESH_DIV(q));
1927                 return -EINVAL;
1928         }
1929
1930         q->free_thresh = tx_free_thresh;
1931
1932         if (conf->tx_rs_thresh == 0)
1933                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1934         else
1935                 tx_rs_thresh = conf->tx_rs_thresh;
1936
1937         q->tx_deferred_start = conf->tx_deferred_start;
1938
1939         /* make sure the requested threshold satisfies the constraints */
1940         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1941                         FM10K_TX_RS_THRESH_MAX(q),
1942                         FM10K_TX_RS_THRESH_DIV(q),
1943                         tx_rs_thresh)) {
1944                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1945                         "less than or equal to %u, "
1946                         "greater than or equal to %u, "
1947                         "and a divisor of %u",
1948                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1949                         FM10K_TX_RS_THRESH_MIN(q),
1950                         FM10K_TX_RS_THRESH_DIV(q));
1951                 return -EINVAL;
1952         }
1953
1954         q->rs_thresh = tx_rs_thresh;
1955
1956         return 0;
1957 }
1958
1959 static int
1960 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1961         uint16_t nb_desc, unsigned int socket_id,
1962         const struct rte_eth_txconf *conf)
1963 {
1964         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965         struct fm10k_tx_queue *q;
1966         const struct rte_memzone *mz;
1967
1968         PMD_INIT_FUNC_TRACE();
1969
1970         /* make sure a valid number of descriptors have been requested */
1971         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1972                                 FM10K_MULT_TX_DESC, nb_desc)) {
1973                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1974                         "less than or equal to %"PRIu32", "
1975                         "greater than or equal to %u, "
1976                         "and a multiple of %u",
1977                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1978                         FM10K_MULT_TX_DESC);
1979                 return -EINVAL;
1980         }
1981
1982         /*
1983          * if this queue existed already, free the associated memory. The
1984          * queue cannot be reused in case we need to allocate memory on
1985          * different socket than was previously used.
1986          */
1987         if (dev->data->tx_queues[queue_id] != NULL) {
1988                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1989
1990                 tx_queue_free(txq);
1991                 dev->data->tx_queues[queue_id] = NULL;
1992         }
1993
1994         /* allocate memory for the queue structure */
1995         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1996                                 socket_id);
1997         if (q == NULL) {
1998                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1999                 return -ENOMEM;
2000         }
2001
2002         /* setup queue */
2003         q->nb_desc = nb_desc;
2004         q->port_id = dev->data->port_id;
2005         q->queue_id = queue_id;
2006         q->txq_flags = conf->txq_flags;
2007         q->ops = &def_txq_ops;
2008         q->tail_ptr = (volatile uint32_t *)
2009                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2010         if (handle_txconf(q, conf))
2011                 return -EINVAL;
2012
2013         /* allocate memory for the software ring */
2014         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2015                                         nb_desc * sizeof(struct rte_mbuf *),
2016                                         RTE_CACHE_LINE_SIZE, socket_id);
2017         if (q->sw_ring == NULL) {
2018                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2019                 rte_free(q);
2020                 return -ENOMEM;
2021         }
2022
2023         /*
2024          * allocate memory for the hardware descriptor ring. A memzone large
2025          * enough to hold the maximum ring size is requested to allow for
2026          * resizing in later calls to the queue setup function.
2027          */
2028         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2029                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2030                                       socket_id);
2031         if (mz == NULL) {
2032                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2033                 rte_free(q->sw_ring);
2034                 rte_free(q);
2035                 return -ENOMEM;
2036         }
2037         q->hw_ring = mz->addr;
2038         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2039
2040         /*
2041          * allocate memory for the RS bit tracker. Enough slots to hold the
2042          * descriptor index for each RS bit needing to be set are required.
2043          */
2044         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2045                                 ((nb_desc + 1) / q->rs_thresh) *
2046                                 sizeof(uint16_t),
2047                                 RTE_CACHE_LINE_SIZE, socket_id);
2048         if (q->rs_tracker.list == NULL) {
2049                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2050                 rte_free(q->sw_ring);
2051                 rte_free(q);
2052                 return -ENOMEM;
2053         }
2054
2055         dev->data->tx_queues[queue_id] = q;
2056         return 0;
2057 }
2058
2059 static void
2060 fm10k_tx_queue_release(void *queue)
2061 {
2062         struct fm10k_tx_queue *q = queue;
2063         PMD_INIT_FUNC_TRACE();
2064
2065         tx_queue_free(q);
2066 }
2067
2068 static int
2069 fm10k_reta_update(struct rte_eth_dev *dev,
2070                         struct rte_eth_rss_reta_entry64 *reta_conf,
2071                         uint16_t reta_size)
2072 {
2073         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2074         uint16_t i, j, idx, shift;
2075         uint8_t mask;
2076         uint32_t reta;
2077
2078         PMD_INIT_FUNC_TRACE();
2079
2080         if (reta_size > FM10K_MAX_RSS_INDICES) {
2081                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2082                         "(%d) doesn't match the number hardware can supported "
2083                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2084                 return -EINVAL;
2085         }
2086
2087         /*
2088          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2089          * 128-entries in 32 registers
2090          */
2091         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2092                 idx = i / RTE_RETA_GROUP_SIZE;
2093                 shift = i % RTE_RETA_GROUP_SIZE;
2094                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2095                                 BIT_MASK_PER_UINT32);
2096                 if (mask == 0)
2097                         continue;
2098
2099                 reta = 0;
2100                 if (mask != BIT_MASK_PER_UINT32)
2101                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2102
2103                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2104                         if (mask & (0x1 << j)) {
2105                                 if (mask != 0xF)
2106                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2107                                 reta |= reta_conf[idx].reta[shift + j] <<
2108                                                 (CHAR_BIT * j);
2109                         }
2110                 }
2111                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2112         }
2113
2114         return 0;
2115 }
2116
2117 static int
2118 fm10k_reta_query(struct rte_eth_dev *dev,
2119                         struct rte_eth_rss_reta_entry64 *reta_conf,
2120                         uint16_t reta_size)
2121 {
2122         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2123         uint16_t i, j, idx, shift;
2124         uint8_t mask;
2125         uint32_t reta;
2126
2127         PMD_INIT_FUNC_TRACE();
2128
2129         if (reta_size < FM10K_MAX_RSS_INDICES) {
2130                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2131                         "(%d) doesn't match the number hardware can supported "
2132                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2133                 return -EINVAL;
2134         }
2135
2136         /*
2137          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2138          * 128-entries in 32 registers
2139          */
2140         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2141                 idx = i / RTE_RETA_GROUP_SIZE;
2142                 shift = i % RTE_RETA_GROUP_SIZE;
2143                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2144                                 BIT_MASK_PER_UINT32);
2145                 if (mask == 0)
2146                         continue;
2147
2148                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2149                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2150                         if (mask & (0x1 << j))
2151                                 reta_conf[idx].reta[shift + j] = ((reta >>
2152                                         CHAR_BIT * j) & UINT8_MAX);
2153                 }
2154         }
2155
2156         return 0;
2157 }
2158
2159 static int
2160 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2161         struct rte_eth_rss_conf *rss_conf)
2162 {
2163         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2165         uint32_t mrqc;
2166         uint64_t hf = rss_conf->rss_hf;
2167         int i;
2168
2169         PMD_INIT_FUNC_TRACE();
2170
2171         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2172                                 FM10K_RSSRK_ENTRIES_PER_REG))
2173                 return -EINVAL;
2174
2175         if (hf == 0)
2176                 return -EINVAL;
2177
2178         mrqc = 0;
2179         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2180         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2181         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2182         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2183         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2184         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2185         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2186         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2187         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2188
2189         /* If the mapping doesn't fit any supported, return */
2190         if (mrqc == 0)
2191                 return -EINVAL;
2192
2193         if (key != NULL)
2194                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2195                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2196
2197         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2198
2199         return 0;
2200 }
2201
2202 static int
2203 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2204         struct rte_eth_rss_conf *rss_conf)
2205 {
2206         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2208         uint32_t mrqc;
2209         uint64_t hf;
2210         int i;
2211
2212         PMD_INIT_FUNC_TRACE();
2213
2214         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2215                                 FM10K_RSSRK_ENTRIES_PER_REG))
2216                 return -EINVAL;
2217
2218         if (key != NULL)
2219                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2220                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2221
2222         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2223         hf = 0;
2224         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2225         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2226         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2227         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2228         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2229         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2230         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2231         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2232         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2233
2234         rss_conf->rss_hf = hf;
2235
2236         return 0;
2237 }
2238
2239 static void
2240 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2241 {
2242         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2244
2245         /* Bind all local non-queue interrupt to vector 0 */
2246         int_map |= FM10K_MISC_VEC_ID;
2247
2248         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2249         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2250         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2251         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2252         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2253         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2254
2255         /* Enable misc causes */
2256         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2257                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2258                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2259                                 FM10K_EIMR_ENABLE(MAILBOX) |
2260                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2261                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2262                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2263                                 FM10K_EIMR_ENABLE(VFLR));
2264
2265         /* Enable ITR 0 */
2266         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2267                                         FM10K_ITR_MASK_CLEAR);
2268         FM10K_WRITE_FLUSH(hw);
2269 }
2270
2271 static void
2272 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2273 {
2274         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2276
2277         int_map |= FM10K_MISC_VEC_ID;
2278
2279         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2280         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2281         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2282         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2283         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2284         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2285
2286         /* Disable misc causes */
2287         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2288                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2289                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2290                                 FM10K_EIMR_DISABLE(MAILBOX) |
2291                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2292                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2293                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2294                                 FM10K_EIMR_DISABLE(VFLR));
2295
2296         /* Disable ITR 0 */
2297         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2298         FM10K_WRITE_FLUSH(hw);
2299 }
2300
2301 static void
2302 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2303 {
2304         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2305         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2306
2307         /* Bind all local non-queue interrupt to vector 0 */
2308         int_map |= FM10K_MISC_VEC_ID;
2309
2310         /* Only INT 0 available, other 15 are reserved. */
2311         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2312
2313         /* Enable ITR 0 */
2314         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2315                                         FM10K_ITR_MASK_CLEAR);
2316         FM10K_WRITE_FLUSH(hw);
2317 }
2318
2319 static void
2320 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2321 {
2322         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2324
2325         int_map |= FM10K_MISC_VEC_ID;
2326
2327         /* Only INT 0 available, other 15 are reserved. */
2328         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2329
2330         /* Disable ITR 0 */
2331         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2332         FM10K_WRITE_FLUSH(hw);
2333 }
2334
2335 static int
2336 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2337 {
2338         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339
2340         /* Enable ITR */
2341         if (hw->mac.type == fm10k_mac_pf)
2342                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2343                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2344         else
2345                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2346                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2347         rte_intr_enable(&dev->pci_dev->intr_handle);
2348         return 0;
2349 }
2350
2351 static int
2352 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2353 {
2354         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2355
2356         /* Disable ITR */
2357         if (hw->mac.type == fm10k_mac_pf)
2358                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2359                         FM10K_ITR_MASK_SET);
2360         else
2361                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2362                         FM10K_ITR_MASK_SET);
2363         return 0;
2364 }
2365
2366 static int
2367 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2368 {
2369         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2370         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2371         uint32_t intr_vector, vec;
2372         uint16_t queue_id;
2373         int result = 0;
2374
2375         /* fm10k needs one separate interrupt for mailbox,
2376          * so only drivers which support multiple interrupt vectors
2377          * e.g. vfio-pci can work for fm10k interrupt mode
2378          */
2379         if (!rte_intr_cap_multiple(intr_handle) ||
2380                         dev->data->dev_conf.intr_conf.rxq == 0)
2381                 return result;
2382
2383         intr_vector = dev->data->nb_rx_queues;
2384
2385         /* disable interrupt first */
2386         rte_intr_disable(&dev->pci_dev->intr_handle);
2387         if (hw->mac.type == fm10k_mac_pf)
2388                 fm10k_dev_disable_intr_pf(dev);
2389         else
2390                 fm10k_dev_disable_intr_vf(dev);
2391
2392         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2393                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2394                 result = -EIO;
2395         }
2396
2397         if (rte_intr_dp_is_en(intr_handle) && !result) {
2398                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2399                         dev->data->nb_rx_queues * sizeof(int), 0);
2400                 if (intr_handle->intr_vec) {
2401                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2402                                         queue_id < dev->data->nb_rx_queues;
2403                                         queue_id++) {
2404                                 intr_handle->intr_vec[queue_id] = vec;
2405                                 if (vec < intr_handle->nb_efd - 1
2406                                                 + FM10K_RX_VEC_START)
2407                                         vec++;
2408                         }
2409                 } else {
2410                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2411                                 " intr_vec", dev->data->nb_rx_queues);
2412                         rte_intr_efd_disable(intr_handle);
2413                         result = -ENOMEM;
2414                 }
2415         }
2416
2417         if (hw->mac.type == fm10k_mac_pf)
2418                 fm10k_dev_enable_intr_pf(dev);
2419         else
2420                 fm10k_dev_enable_intr_vf(dev);
2421         rte_intr_enable(&dev->pci_dev->intr_handle);
2422         hw->mac.ops.update_int_moderator(hw);
2423         return result;
2424 }
2425
2426 static int
2427 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2428 {
2429         struct fm10k_fault fault;
2430         int err;
2431         const char *estr = "Unknown error";
2432
2433         /* Process PCA fault */
2434         if (eicr & FM10K_EICR_PCA_FAULT) {
2435                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2436                 if (err)
2437                         goto error;
2438                 switch (fault.type) {
2439                 case PCA_NO_FAULT:
2440                         estr = "PCA_NO_FAULT"; break;
2441                 case PCA_UNMAPPED_ADDR:
2442                         estr = "PCA_UNMAPPED_ADDR"; break;
2443                 case PCA_BAD_QACCESS_PF:
2444                         estr = "PCA_BAD_QACCESS_PF"; break;
2445                 case PCA_BAD_QACCESS_VF:
2446                         estr = "PCA_BAD_QACCESS_VF"; break;
2447                 case PCA_MALICIOUS_REQ:
2448                         estr = "PCA_MALICIOUS_REQ"; break;
2449                 case PCA_POISONED_TLP:
2450                         estr = "PCA_POISONED_TLP"; break;
2451                 case PCA_TLP_ABORT:
2452                         estr = "PCA_TLP_ABORT"; break;
2453                 default:
2454                         goto error;
2455                 }
2456                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2457                         estr, fault.func ? "VF" : "PF", fault.func,
2458                         fault.address, fault.specinfo);
2459         }
2460
2461         /* Process THI fault */
2462         if (eicr & FM10K_EICR_THI_FAULT) {
2463                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2464                 if (err)
2465                         goto error;
2466                 switch (fault.type) {
2467                 case THI_NO_FAULT:
2468                         estr = "THI_NO_FAULT"; break;
2469                 case THI_MAL_DIS_Q_FAULT:
2470                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2471                 default:
2472                         goto error;
2473                 }
2474                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2475                         estr, fault.func ? "VF" : "PF", fault.func,
2476                         fault.address, fault.specinfo);
2477         }
2478
2479         /* Process FUM fault */
2480         if (eicr & FM10K_EICR_FUM_FAULT) {
2481                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2482                 if (err)
2483                         goto error;
2484                 switch (fault.type) {
2485                 case FUM_NO_FAULT:
2486                         estr = "FUM_NO_FAULT"; break;
2487                 case FUM_UNMAPPED_ADDR:
2488                         estr = "FUM_UNMAPPED_ADDR"; break;
2489                 case FUM_POISONED_TLP:
2490                         estr = "FUM_POISONED_TLP"; break;
2491                 case FUM_BAD_VF_QACCESS:
2492                         estr = "FUM_BAD_VF_QACCESS"; break;
2493                 case FUM_ADD_DECODE_ERR:
2494                         estr = "FUM_ADD_DECODE_ERR"; break;
2495                 case FUM_RO_ERROR:
2496                         estr = "FUM_RO_ERROR"; break;
2497                 case FUM_QPRC_CRC_ERROR:
2498                         estr = "FUM_QPRC_CRC_ERROR"; break;
2499                 case FUM_CSR_TIMEOUT:
2500                         estr = "FUM_CSR_TIMEOUT"; break;
2501                 case FUM_INVALID_TYPE:
2502                         estr = "FUM_INVALID_TYPE"; break;
2503                 case FUM_INVALID_LENGTH:
2504                         estr = "FUM_INVALID_LENGTH"; break;
2505                 case FUM_INVALID_BE:
2506                         estr = "FUM_INVALID_BE"; break;
2507                 case FUM_INVALID_ALIGN:
2508                         estr = "FUM_INVALID_ALIGN"; break;
2509                 default:
2510                         goto error;
2511                 }
2512                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2513                         estr, fault.func ? "VF" : "PF", fault.func,
2514                         fault.address, fault.specinfo);
2515         }
2516
2517         return 0;
2518 error:
2519         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2520         return err;
2521 }
2522
2523 /**
2524  * PF interrupt handler triggered by NIC for handling specific interrupt.
2525  *
2526  * @param handle
2527  *  Pointer to interrupt handle.
2528  * @param param
2529  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2530  *
2531  * @return
2532  *  void
2533  */
2534 static void
2535 fm10k_dev_interrupt_handler_pf(
2536                         __rte_unused struct rte_intr_handle *handle,
2537                         void *param)
2538 {
2539         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2540         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         uint32_t cause, status;
2542
2543         if (hw->mac.type != fm10k_mac_pf)
2544                 return;
2545
2546         cause = FM10K_READ_REG(hw, FM10K_EICR);
2547
2548         /* Handle PCI fault cases */
2549         if (cause & FM10K_EICR_FAULT_MASK) {
2550                 PMD_INIT_LOG(ERR, "INT: find fault!");
2551                 fm10k_dev_handle_fault(hw, cause);
2552         }
2553
2554         /* Handle switch up/down */
2555         if (cause & FM10K_EICR_SWITCHNOTREADY)
2556                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2557
2558         if (cause & FM10K_EICR_SWITCHREADY)
2559                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2560
2561         /* Handle mailbox message */
2562         fm10k_mbx_lock(hw);
2563         hw->mbx.ops.process(hw, &hw->mbx);
2564         fm10k_mbx_unlock(hw);
2565
2566         /* Handle SRAM error */
2567         if (cause & FM10K_EICR_SRAMERROR) {
2568                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2569
2570                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2571                 /* Write to clear pending bits */
2572                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2573
2574                 /* Todo: print out error message after shared code  updates */
2575         }
2576
2577         /* Clear these 3 events if having any */
2578         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2579                  FM10K_EICR_SWITCHREADY;
2580         if (cause)
2581                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2582
2583         /* Re-enable interrupt from device side */
2584         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2585                                         FM10K_ITR_MASK_CLEAR);
2586         /* Re-enable interrupt from host side */
2587         rte_intr_enable(&(dev->pci_dev->intr_handle));
2588 }
2589
2590 /**
2591  * VF interrupt handler triggered by NIC for handling specific interrupt.
2592  *
2593  * @param handle
2594  *  Pointer to interrupt handle.
2595  * @param param
2596  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2597  *
2598  * @return
2599  *  void
2600  */
2601 static void
2602 fm10k_dev_interrupt_handler_vf(
2603                         __rte_unused struct rte_intr_handle *handle,
2604                         void *param)
2605 {
2606         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2607         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608
2609         if (hw->mac.type != fm10k_mac_vf)
2610                 return;
2611
2612         /* Handle mailbox message if lock is acquired */
2613         fm10k_mbx_lock(hw);
2614         hw->mbx.ops.process(hw, &hw->mbx);
2615         fm10k_mbx_unlock(hw);
2616
2617         /* Re-enable interrupt from device side */
2618         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2619                                         FM10K_ITR_MASK_CLEAR);
2620         /* Re-enable interrupt from host side */
2621         rte_intr_enable(&(dev->pci_dev->intr_handle));
2622 }
2623
2624 /* Mailbox message handler in VF */
2625 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2626         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2627         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2628         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2629         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2630 };
2631
2632 static int
2633 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2634 {
2635         int err = 0;
2636
2637         /* Initialize mailbox lock */
2638         fm10k_mbx_initlock(hw);
2639
2640         /* Replace default message handler with new ones */
2641         if (hw->mac.type == fm10k_mac_vf)
2642                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2643
2644         if (err) {
2645                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2646                                 err);
2647                 return err;
2648         }
2649         /* Connect to SM for PF device or PF for VF device */
2650         return hw->mbx.ops.connect(hw, &hw->mbx);
2651 }
2652
2653 static void
2654 fm10k_close_mbx_service(struct fm10k_hw *hw)
2655 {
2656         /* Disconnect from SM for PF device or PF for VF device */
2657         hw->mbx.ops.disconnect(hw, &hw->mbx);
2658 }
2659
2660 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2661         .dev_configure          = fm10k_dev_configure,
2662         .dev_start              = fm10k_dev_start,
2663         .dev_stop               = fm10k_dev_stop,
2664         .dev_close              = fm10k_dev_close,
2665         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2666         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2667         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2668         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2669         .stats_get              = fm10k_stats_get,
2670         .xstats_get             = fm10k_xstats_get,
2671         .xstats_get_names       = fm10k_xstats_get_names,
2672         .stats_reset            = fm10k_stats_reset,
2673         .xstats_reset           = fm10k_stats_reset,
2674         .link_update            = fm10k_link_update,
2675         .dev_infos_get          = fm10k_dev_infos_get,
2676         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2677         .vlan_filter_set        = fm10k_vlan_filter_set,
2678         .vlan_offload_set       = fm10k_vlan_offload_set,
2679         .mac_addr_add           = fm10k_macaddr_add,
2680         .mac_addr_remove        = fm10k_macaddr_remove,
2681         .rx_queue_start         = fm10k_dev_rx_queue_start,
2682         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2683         .tx_queue_start         = fm10k_dev_tx_queue_start,
2684         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2685         .rx_queue_setup         = fm10k_rx_queue_setup,
2686         .rx_queue_release       = fm10k_rx_queue_release,
2687         .tx_queue_setup         = fm10k_tx_queue_setup,
2688         .tx_queue_release       = fm10k_tx_queue_release,
2689         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2690         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2691         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2692         .reta_update            = fm10k_reta_update,
2693         .reta_query             = fm10k_reta_query,
2694         .rss_hash_update        = fm10k_rss_hash_update,
2695         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2696 };
2697
2698 static int ftag_check_handler(__rte_unused const char *key,
2699                 const char *value, __rte_unused void *opaque)
2700 {
2701         if (strcmp(value, "1"))
2702                 return -1;
2703
2704         return 0;
2705 }
2706
2707 static int
2708 fm10k_check_ftag(struct rte_devargs *devargs)
2709 {
2710         struct rte_kvargs *kvlist;
2711         const char *ftag_key = "enable_ftag";
2712
2713         if (devargs == NULL)
2714                 return 0;
2715
2716         kvlist = rte_kvargs_parse(devargs->args, NULL);
2717         if (kvlist == NULL)
2718                 return 0;
2719
2720         if (!rte_kvargs_count(kvlist, ftag_key)) {
2721                 rte_kvargs_free(kvlist);
2722                 return 0;
2723         }
2724         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2725         if (rte_kvargs_process(kvlist, ftag_key,
2726                                 ftag_check_handler, NULL) < 0) {
2727                 rte_kvargs_free(kvlist);
2728                 return 0;
2729         }
2730         rte_kvargs_free(kvlist);
2731
2732         return 1;
2733 }
2734
2735 static void __attribute__((cold))
2736 fm10k_set_tx_function(struct rte_eth_dev *dev)
2737 {
2738         struct fm10k_tx_queue *txq;
2739         int i;
2740         int use_sse = 1;
2741         uint16_t tx_ftag_en = 0;
2742
2743         if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2744                 tx_ftag_en = 1;
2745
2746         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2747                 txq = dev->data->tx_queues[i];
2748                 txq->tx_ftag_en = tx_ftag_en;
2749                 /* Check if Vector Tx is satisfied */
2750                 if (fm10k_tx_vec_condition_check(txq))
2751                         use_sse = 0;
2752         }
2753
2754         if (use_sse) {
2755                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2756                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2757                         txq = dev->data->tx_queues[i];
2758                         fm10k_txq_vec_setup(txq);
2759                 }
2760                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2761         } else {
2762                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2763                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2764         }
2765 }
2766
2767 static void __attribute__((cold))
2768 fm10k_set_rx_function(struct rte_eth_dev *dev)
2769 {
2770         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2771         uint16_t i, rx_using_sse;
2772         uint16_t rx_ftag_en = 0;
2773
2774         if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2775                 rx_ftag_en = 1;
2776
2777         /* In order to allow Vector Rx there are a few configuration
2778          * conditions to be met.
2779          */
2780         if (!fm10k_rx_vec_condition_check(dev) &&
2781                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2782                 if (dev->data->scattered_rx)
2783                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2784                 else
2785                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2786         } else if (dev->data->scattered_rx)
2787                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2788         else
2789                 dev->rx_pkt_burst = fm10k_recv_pkts;
2790
2791         rx_using_sse =
2792                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2793                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2794
2795         if (rx_using_sse)
2796                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2797         else
2798                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2799
2800         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2801                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2802
2803                 rxq->rx_using_sse = rx_using_sse;
2804                 rxq->rx_ftag_en = rx_ftag_en;
2805         }
2806 }
2807
2808 static void
2809 fm10k_params_init(struct rte_eth_dev *dev)
2810 {
2811         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812         struct fm10k_dev_info *info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2813
2814         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2815          * there is no way to get link status without reading BAR4.  Until this
2816          * works, assume we have maximum bandwidth.
2817          * @todo - fix bus info
2818          */
2819         hw->bus_caps.speed = fm10k_bus_speed_8000;
2820         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2821         hw->bus_caps.payload = fm10k_bus_payload_512;
2822         hw->bus.speed = fm10k_bus_speed_8000;
2823         hw->bus.width = fm10k_bus_width_pcie_x8;
2824         hw->bus.payload = fm10k_bus_payload_256;
2825
2826         info->rx_vec_allowed = true;
2827 }
2828
2829 static int
2830 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2831 {
2832         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2833         int diag, i;
2834         struct fm10k_macvlan_filter_info *macvlan;
2835
2836         PMD_INIT_FUNC_TRACE();
2837
2838         dev->dev_ops = &fm10k_eth_dev_ops;
2839         dev->rx_pkt_burst = &fm10k_recv_pkts;
2840         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2841
2842         /* only initialize in the primary process */
2843         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2844                 return 0;
2845
2846         rte_eth_copy_pci_info(dev, dev->pci_dev);
2847
2848         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2849         memset(macvlan, 0, sizeof(*macvlan));
2850         /* Vendor and Device ID need to be set before init of shared code */
2851         memset(hw, 0, sizeof(*hw));
2852         hw->device_id = dev->pci_dev->id.device_id;
2853         hw->vendor_id = dev->pci_dev->id.vendor_id;
2854         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
2855         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
2856         hw->revision_id = 0;
2857         hw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;
2858         if (hw->hw_addr == NULL) {
2859                 PMD_INIT_LOG(ERR, "Bad mem resource."
2860                         " Try to blacklist unused devices.");
2861                 return -EIO;
2862         }
2863
2864         /* Store fm10k_adapter pointer */
2865         hw->back = dev->data->dev_private;
2866
2867         /* Initialize the shared code */
2868         diag = fm10k_init_shared_code(hw);
2869         if (diag != FM10K_SUCCESS) {
2870                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2871                 return -EIO;
2872         }
2873
2874         /* Initialize parameters */
2875         fm10k_params_init(dev);
2876
2877         /* Initialize the hw */
2878         diag = fm10k_init_hw(hw);
2879         if (diag != FM10K_SUCCESS) {
2880                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2881                 return -EIO;
2882         }
2883
2884         /* Initialize MAC address(es) */
2885         dev->data->mac_addrs = rte_zmalloc("fm10k",
2886                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2887         if (dev->data->mac_addrs == NULL) {
2888                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2889                 return -ENOMEM;
2890         }
2891
2892         diag = fm10k_read_mac_addr(hw);
2893
2894         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2895                         &dev->data->mac_addrs[0]);
2896
2897         if (diag != FM10K_SUCCESS ||
2898                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2899
2900                 /* Generate a random addr */
2901                 eth_random_addr(hw->mac.addr);
2902                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2903                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2904                 &dev->data->mac_addrs[0]);
2905         }
2906
2907         /* Reset the hw statistics */
2908         fm10k_stats_reset(dev);
2909
2910         /* Reset the hw */
2911         diag = fm10k_reset_hw(hw);
2912         if (diag != FM10K_SUCCESS) {
2913                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2914                 return -EIO;
2915         }
2916
2917         /* Setup mailbox service */
2918         diag = fm10k_setup_mbx_service(hw);
2919         if (diag != FM10K_SUCCESS) {
2920                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2921                 return -EIO;
2922         }
2923
2924         /*PF/VF has different interrupt handling mechanism */
2925         if (hw->mac.type == fm10k_mac_pf) {
2926                 /* register callback func to eal lib */
2927                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2928                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2929
2930                 /* enable MISC interrupt */
2931                 fm10k_dev_enable_intr_pf(dev);
2932         } else { /* VF */
2933                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2934                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2935
2936                 fm10k_dev_enable_intr_vf(dev);
2937         }
2938
2939         /* Enable intr after callback registered */
2940         rte_intr_enable(&(dev->pci_dev->intr_handle));
2941
2942         hw->mac.ops.update_int_moderator(hw);
2943
2944         /* Make sure Switch Manager is ready before going forward. */
2945         if (hw->mac.type == fm10k_mac_pf) {
2946                 int switch_ready = 0;
2947
2948                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2949                         fm10k_mbx_lock(hw);
2950                         hw->mac.ops.get_host_state(hw, &switch_ready);
2951                         fm10k_mbx_unlock(hw);
2952                         if (switch_ready)
2953                                 break;
2954                         /* Delay some time to acquire async LPORT_MAP info. */
2955                         rte_delay_us(WAIT_SWITCH_MSG_US);
2956                 }
2957
2958                 if (switch_ready == 0) {
2959                         PMD_INIT_LOG(ERR, "switch is not ready");
2960                         return -1;
2961                 }
2962         }
2963
2964         /*
2965          * Below function will trigger operations on mailbox, acquire lock to
2966          * avoid race condition from interrupt handler. Operations on mailbox
2967          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2968          * will handle and generate an interrupt to our side. Then,  FIFO in
2969          * mailbox will be touched.
2970          */
2971         fm10k_mbx_lock(hw);
2972         /* Enable port first */
2973         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2974                                         MAX_LPORT_NUM, 1);
2975
2976         /* Set unicast mode by default. App can change to other mode in other
2977          * API func.
2978          */
2979         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2980                                         FM10K_XCAST_MODE_NONE);
2981
2982         fm10k_mbx_unlock(hw);
2983
2984         /* Make sure default VID is ready before going forward. */
2985         if (hw->mac.type == fm10k_mac_pf) {
2986                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2987                         if (hw->mac.default_vid)
2988                                 break;
2989                         /* Delay some time to acquire async port VLAN info. */
2990                         rte_delay_us(WAIT_SWITCH_MSG_US);
2991                 }
2992
2993                 if (!hw->mac.default_vid) {
2994                         PMD_INIT_LOG(ERR, "default VID is not ready");
2995                         return -1;
2996                 }
2997         }
2998
2999         /* Add default mac address */
3000         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3001                 MAIN_VSI_POOL_NUMBER);
3002
3003         return 0;
3004 }
3005
3006 static int
3007 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3008 {
3009         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010
3011         PMD_INIT_FUNC_TRACE();
3012
3013         /* only uninitialize in the primary process */
3014         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3015                 return 0;
3016
3017         /* safe to close dev here */
3018         fm10k_dev_close(dev);
3019
3020         dev->dev_ops = NULL;
3021         dev->rx_pkt_burst = NULL;
3022         dev->tx_pkt_burst = NULL;
3023
3024         /* disable uio/vfio intr */
3025         rte_intr_disable(&(dev->pci_dev->intr_handle));
3026
3027         /*PF/VF has different interrupt handling mechanism */
3028         if (hw->mac.type == fm10k_mac_pf) {
3029                 /* disable interrupt */
3030                 fm10k_dev_disable_intr_pf(dev);
3031
3032                 /* unregister callback func to eal lib */
3033                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3034                         fm10k_dev_interrupt_handler_pf, (void *)dev);
3035         } else {
3036                 /* disable interrupt */
3037                 fm10k_dev_disable_intr_vf(dev);
3038
3039                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3040                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3041         }
3042
3043         /* free mac memory */
3044         if (dev->data->mac_addrs) {
3045                 rte_free(dev->data->mac_addrs);
3046                 dev->data->mac_addrs = NULL;
3047         }
3048
3049         memset(hw, 0, sizeof(*hw));
3050
3051         return 0;
3052 }
3053
3054 /*
3055  * The set of PCI devices this driver supports. This driver will enable both PF
3056  * and SRIOV-VF devices.
3057  */
3058 static const struct rte_pci_id pci_id_fm10k_map[] = {
3059         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3060         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3061         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3062         { .vendor_id = 0, /* sentinel */ },
3063 };
3064
3065 static struct eth_driver rte_pmd_fm10k = {
3066         .pci_drv = {
3067                 .id_table = pci_id_fm10k_map,
3068                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3069                         RTE_PCI_DRV_DETACHABLE,
3070                 .probe = rte_eth_dev_pci_probe,
3071                 .remove = rte_eth_dev_pci_remove,
3072         },
3073         .eth_dev_init = eth_fm10k_dev_init,
3074         .eth_dev_uninit = eth_fm10k_dev_uninit,
3075         .dev_private_size = sizeof(struct fm10k_adapter),
3076 };
3077
3078 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k.pci_drv);
3079 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);