drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_malloc.h>
  36 #include <rte_memzone.h>
  37 #include <rte_string_fns.h>
  38 #include <rte_dev.h>
  39 #include <rte_spinlock.h>
  40 #include <rte_kvargs.h>
  41
  42 #include "fm10k.h"
  43 #include "base/fm10k_api.h"
  44
  45 /* Default delay to acquire mailbox lock */
  46 #define FM10K_MBXLOCK_DELAY_US 20
  47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  48
  49 #define MAIN_VSI_POOL_NUMBER 0
  50
  51 /* Max try times to acquire switch status */
  52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  53 /* Wait interval to get switch status */
  54 #define WAIT_SWITCH_MSG_US    100000
  55 /* Number of chars per uint32 type */
  56 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  57 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  58
  59 /* default 1:1 map from queue ID to interrupt vector ID */
  60 #define Q2V(dev, queue_id) (dev->pci_dev->intr_handle.intr_vec[queue_id])
  61
  62 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  63 #define MAX_LPORT_NUM    128
  64 #define GLORT_FD_Q_BASE  0x40
  65 #define GLORT_PF_MASK    0xFFC0
  66 #define GLORT_FD_MASK    GLORT_PF_MASK
  67 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  68
  69 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  70 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  71 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  72 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  73 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  74 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  75 static int
  76 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  77 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  78         const u8 *mac, bool add, uint32_t pool);
  79 static void fm10k_tx_queue_release(void *queue);
  80 static void fm10k_rx_queue_release(void *queue);
  81 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  82 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  83 static int fm10k_check_ftag(struct rte_devargs *devargs);
  84
  85 struct fm10k_xstats_name_off {
  86         char name[RTE_ETH_XSTATS_NAME_SIZE];
  87         unsigned offset;
  88 };
  89
  90 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  91         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  92         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  93         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  94         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  95         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  96         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
  97         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
  98         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
  99                 nodesc_drop)},
 100 };
 101
 102 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 103                 sizeof(fm10k_hw_stats_strings[0]))
 104
 105 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 106         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 107         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 108         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 109 };
 110
 111 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 112                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 113
 114 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 115         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 116         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 117 };
 118
 119 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 120                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 121
 122 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 123                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 124 static int
 125 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 126
 127 static void
 128 fm10k_mbx_initlock(struct fm10k_hw *hw)
 129 {
 130         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 131 }
 132
 133 static void
 134 fm10k_mbx_lock(struct fm10k_hw *hw)
 135 {
 136         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 137                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 138 }
 139
 140 static void
 141 fm10k_mbx_unlock(struct fm10k_hw *hw)
 142 {
 143         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 144 }
 145
 146 /* Stubs needed for linkage when vPMD is disabled */
 147 int __attribute__((weak))
 148 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 149 {
 150         return -1;
 151 }
 152
 153 uint16_t __attribute__((weak))
 154 fm10k_recv_pkts_vec(
 155         __rte_unused void *rx_queue,
 156         __rte_unused struct rte_mbuf **rx_pkts,
 157         __rte_unused uint16_t nb_pkts)
 158 {
 159         return 0;
 160 }
 161
 162 uint16_t __attribute__((weak))
 163 fm10k_recv_scattered_pkts_vec(
 164                 __rte_unused void *rx_queue,
 165                 __rte_unused struct rte_mbuf **rx_pkts,
 166                 __rte_unused uint16_t nb_pkts)
 167 {
 168         return 0;
 169 }
 170
 171 int __attribute__((weak))
 172 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 173
 174 {
 175         return -1;
 176 }
 177
 178 void __attribute__((weak))
 179 fm10k_rx_queue_release_mbufs_vec(
 180                 __rte_unused struct fm10k_rx_queue *rxq)
 181 {
 182         return;
 183 }
 184
 185 void __attribute__((weak))
 186 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 187 {
 188         return;
 189 }
 190
 191 int __attribute__((weak))
 192 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 193 {
 194         return -1;
 195 }
 196
 197 uint16_t __attribute__((weak))
 198 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
 199                 __rte_unused struct rte_mbuf **tx_pkts,
 200                 __rte_unused uint16_t nb_pkts)
 201 {
 202         return 0;
 203 }
 204
 205 /*
 206  * reset queue to initial state, allocate software buffers used when starting
 207  * device.
 208  * return 0 on success
 209  * return -ENOMEM if buffers cannot be allocated
 210  * return -EINVAL if buffers do not satisfy alignment condition
 211  */
 212 static inline int
 213 rx_queue_reset(struct fm10k_rx_queue *q)
 214 {
 215         static const union fm10k_rx_desc zero = {{0} };
 216         uint64_t dma_addr;
 217         int i, diag;
 218         PMD_INIT_FUNC_TRACE();
 219
 220         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 221         if (diag != 0)
 222                 return -ENOMEM;
 223
 224         for (i = 0; i < q->nb_desc; ++i) {
 225                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 226                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 227                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 228                                                 q->nb_desc);
 229                         return -EINVAL;
 230                 }
 231                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 232                 q->hw_ring[i].q.pkt_addr = dma_addr;
 233                 q->hw_ring[i].q.hdr_addr = dma_addr;
 234         }
 235
 236         /* initialize extra software ring entries. Space for these extra
 237          * entries is always allocated.
 238          */
 239         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 240         for (i = 0; i < q->nb_fake_desc; ++i) {
 241                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 242                 q->hw_ring[q->nb_desc + i] = zero;
 243         }
 244
 245         q->next_dd = 0;
 246         q->next_alloc = 0;
 247         q->next_trigger = q->alloc_thresh - 1;
 248         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 249         q->rxrearm_start = 0;
 250         q->rxrearm_nb = 0;
 251
 252         return 0;
 253 }
 254
 255 /*
 256  * clean queue, descriptor rings, free software buffers used when stopping
 257  * device.
 258  */
 259 static inline void
 260 rx_queue_clean(struct fm10k_rx_queue *q)
 261 {
 262         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 263         uint32_t i;
 264         PMD_INIT_FUNC_TRACE();
 265
 266         /* zero descriptor rings */
 267         for (i = 0; i < q->nb_desc; ++i)
 268                 q->hw_ring[i] = zero;
 269
 270         /* zero faked descriptors */
 271         for (i = 0; i < q->nb_fake_desc; ++i)
 272                 q->hw_ring[q->nb_desc + i] = zero;
 273
 274         /* vPMD driver has a different way of releasing mbufs. */
 275         if (q->rx_using_sse) {
 276                 fm10k_rx_queue_release_mbufs_vec(q);
 277                 return;
 278         }
 279
 280         /* free software buffers */
 281         for (i = 0; i < q->nb_desc; ++i) {
 282                 if (q->sw_ring[i]) {
 283                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 284                         q->sw_ring[i] = NULL;
 285                 }
 286         }
 287 }
 288
 289 /*
 290  * free all queue memory used when releasing the queue (i.e. configure)
 291  */
 292 static inline void
 293 rx_queue_free(struct fm10k_rx_queue *q)
 294 {
 295         PMD_INIT_FUNC_TRACE();
 296         if (q) {
 297                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 298                 rx_queue_clean(q);
 299                 if (q->sw_ring) {
 300                         rte_free(q->sw_ring);
 301                         q->sw_ring = NULL;
 302                 }
 303                 rte_free(q);
 304                 q = NULL;
 305         }
 306 }
 307
 308 /*
 309  * disable RX queue, wait unitl HW finished necessary flush operation
 310  */
 311 static inline int
 312 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 313 {
 314         uint32_t reg, i;
 315
 316         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 317         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 318                         reg & ~FM10K_RXQCTL_ENABLE);
 319
 320         /* Wait 100us at most */
 321         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 322                 rte_delay_us(1);
 323                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 324                 if (!(reg & FM10K_RXQCTL_ENABLE))
 325                         break;
 326         }
 327
 328         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 329                 return -1;
 330
 331         return 0;
 332 }
 333
 334 /*
 335  * reset queue to initial state, allocate software buffers used when starting
 336  * device
 337  */
 338 static inline void
 339 tx_queue_reset(struct fm10k_tx_queue *q)
 340 {
 341         PMD_INIT_FUNC_TRACE();
 342         q->last_free = 0;
 343         q->next_free = 0;
 344         q->nb_used = 0;
 345         q->nb_free = q->nb_desc - 1;
 346         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 347         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 348 }
 349
 350 /*
 351  * clean queue, descriptor rings, free software buffers used when stopping
 352  * device
 353  */
 354 static inline void
 355 tx_queue_clean(struct fm10k_tx_queue *q)
 356 {
 357         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 358         uint32_t i;
 359         PMD_INIT_FUNC_TRACE();
 360
 361         /* zero descriptor rings */
 362         for (i = 0; i < q->nb_desc; ++i)
 363                 q->hw_ring[i] = zero;
 364
 365         /* free software buffers */
 366         for (i = 0; i < q->nb_desc; ++i) {
 367                 if (q->sw_ring[i]) {
 368                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 369                         q->sw_ring[i] = NULL;
 370                 }
 371         }
 372 }
 373
 374 /*
 375  * free all queue memory used when releasing the queue (i.e. configure)
 376  */
 377 static inline void
 378 tx_queue_free(struct fm10k_tx_queue *q)
 379 {
 380         PMD_INIT_FUNC_TRACE();
 381         if (q) {
 382                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 383                 tx_queue_clean(q);
 384                 if (q->rs_tracker.list) {
 385                         rte_free(q->rs_tracker.list);
 386                         q->rs_tracker.list = NULL;
 387                 }
 388                 if (q->sw_ring) {
 389                         rte_free(q->sw_ring);
 390                         q->sw_ring = NULL;
 391                 }
 392                 rte_free(q);
 393                 q = NULL;
 394         }
 395 }
 396
 397 /*
 398  * disable TX queue, wait unitl HW finished necessary flush operation
 399  */
 400 static inline int
 401 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 402 {
 403         uint32_t reg, i;
 404
 405         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 406         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 407                         reg & ~FM10K_TXDCTL_ENABLE);
 408
 409         /* Wait 100us at most */
 410         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 411                 rte_delay_us(1);
 412                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 413                 if (!(reg & FM10K_TXDCTL_ENABLE))
 414                         break;
 415         }
 416
 417         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 418                 return -1;
 419
 420         return 0;
 421 }
 422
 423 static int
 424 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 425 {
 426         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 427         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 428         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 429         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 430
 431         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 432
 433         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 434                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 435                 return -EINVAL;
 436         }
 437
 438         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 439                 return 0;
 440
 441         if (hw->mac.type == fm10k_mac_vf) {
 442                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 443                 return -EINVAL;
 444         }
 445
 446         /* Check VMDQ queue pool number */
 447         if (vmdq_conf->nb_queue_pools >
 448                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 449                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 450                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 451                         vmdq_conf->nb_queue_pools);
 452                 return -EINVAL;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static const struct fm10k_txq_ops def_txq_ops = {
 459         .reset = tx_queue_reset,
 460 };
 461
 462 static int
 463 fm10k_dev_configure(struct rte_eth_dev *dev)
 464 {
 465         int ret;
 466
 467         PMD_INIT_FUNC_TRACE();
 468
 469         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 470                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 471         /* multipe queue mode checking */
 472         ret  = fm10k_check_mq_mode(dev);
 473         if (ret != 0) {
 474                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 475                             ret);
 476                 return ret;
 477         }
 478
 479         return 0;
 480 }
 481
 482 /* fls = find last set bit = 32 minus the number of leading zeros */
 483 #ifndef fls
 484 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 485 #endif
 486
 487 static void
 488 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 489 {
 490         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 491         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 492         uint32_t i;
 493
 494         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 495
 496         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 497                 if (!vmdq_conf->pool_map[i].pools)
 498                         continue;
 499                 fm10k_mbx_lock(hw);
 500                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 501                 fm10k_mbx_unlock(hw);
 502         }
 503 }
 504
 505 static void
 506 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 507 {
 508         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 509
 510         /* Add default mac address */
 511         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 512                 MAIN_VSI_POOL_NUMBER);
 513 }
 514
 515 static void
 516 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 517 {
 518         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 519         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 520         uint32_t mrqc, *key, i, reta, j;
 521         uint64_t hf;
 522
 523 #define RSS_KEY_SIZE 40
 524         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 525                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 526                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 527                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 528                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 529                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 530         };
 531
 532         if (dev->data->nb_rx_queues == 1 ||
 533             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 534             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 535                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 536                 return;
 537         }
 538
 539         /* random key is rss_intel_key (default) or user provided (rss_key) */
 540         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 541                 key = (uint32_t *)rss_intel_key;
 542         else
 543                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 544
 545         /* Now fill our hash function seeds, 4 bytes at a time */
 546         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 547                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 548
 549         /*
 550          * Fill in redirection table
 551          * The byte-swap is needed because NIC registers are in
 552          * little-endian order.
 553          */
 554         reta = 0;
 555         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 556                 if (j == dev->data->nb_rx_queues)
 557                         j = 0;
 558                 reta = (reta << CHAR_BIT) | j;
 559                 if ((i & 3) == 3)
 560                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 561                                         rte_bswap32(reta));
 562         }
 563
 564         /*
 565          * Generate RSS hash based on packet types, TCP/UDP
 566          * port numbers and/or IPv4/v6 src and dst addresses
 567          */
 568         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 569         mrqc = 0;
 570         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 571         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 572         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 573         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 574         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 575         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 577         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 579
 580         if (mrqc == 0) {
 581                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 582                         "supported", hf);
 583                 return;
 584         }
 585
 586         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 587 }
 588
 589 static void
 590 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 591 {
 592         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 593         uint32_t i;
 594
 595         for (i = 0; i < nb_lport_new; i++) {
 596                 /* Set unicast mode by default. App can change
 597                  * to other mode in other API func.
 598                  */
 599                 fm10k_mbx_lock(hw);
 600                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 601                         FM10K_XCAST_MODE_NONE);
 602                 fm10k_mbx_unlock(hw);
 603         }
 604 }
 605
 606 static void
 607 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 608 {
 609         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 610         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 611         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 612         struct fm10k_macvlan_filter_info *macvlan;
 613         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 614         uint16_t nb_lport_new;
 615
 616         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 617         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 618
 619         fm10k_dev_rss_configure(dev);
 620
 621         /* only PF supports VMDQ */
 622         if (hw->mac.type != fm10k_mac_pf)
 623                 return;
 624
 625         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 626                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 627
 628         /* no pool number change, no need to update logic port and VLAN/MAC */
 629         if (macvlan->nb_queue_pools == nb_queue_pools)
 630                 return;
 631
 632         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 633         fm10k_dev_logic_port_update(dev, nb_lport_new);
 634
 635         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 636         memset(dev->data->mac_addrs, 0,
 637                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 638         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 639                 &dev->data->mac_addrs[0]);
 640         memset(macvlan, 0, sizeof(*macvlan));
 641         macvlan->nb_queue_pools = nb_queue_pools;
 642
 643         if (nb_queue_pools)
 644                 fm10k_dev_vmdq_rx_configure(dev);
 645         else
 646                 fm10k_dev_pf_main_vsi_reset(dev);
 647 }
 648
 649 static int
 650 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 651 {
 652         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 653         int i, ret;
 654         struct fm10k_tx_queue *txq;
 655         uint64_t base_addr;
 656         uint32_t size;
 657
 658         /* Disable TXINT to avoid possible interrupt */
 659         for (i = 0; i < hw->mac.max_queues; i++)
 660                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 661                                 3 << FM10K_TXINT_TIMER_SHIFT);
 662
 663         /* Setup TX queue */
 664         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 665                 txq = dev->data->tx_queues[i];
 666                 base_addr = txq->hw_ring_phys_addr;
 667                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 668
 669                 /* disable queue to avoid issues while updating state */
 670                 ret = tx_queue_disable(hw, i);
 671                 if (ret) {
 672                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 673                         return -1;
 674                 }
 675                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 676                  * register is read-only for VF.
 677                  */
 678                 if (fm10k_check_ftag(dev->pci_dev->devargs)) {
 679                         if (hw->mac.type == fm10k_mac_pf) {
 680                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 681                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 682                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 683                         } else {
 684                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 685                                 return -ENOTSUP;
 686                         }
 687                 }
 688
 689                 /* set location and size for descriptor ring */
 690                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 691                                 base_addr & UINT64_LOWER_32BITS_MASK);
 692                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 693                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 694                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 695
 696                 /* assign default SGLORT for each TX queue */
 697                 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 698         }
 699
 700         /* set up vector or scalar TX function as appropriate */
 701         fm10k_set_tx_function(dev);
 702
 703         return 0;
 704 }
 705
 706 static int
 707 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 708 {
 709         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710         struct fm10k_macvlan_filter_info *macvlan;
 711         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 712         int i, ret;
 713         struct fm10k_rx_queue *rxq;
 714         uint64_t base_addr;
 715         uint32_t size;
 716         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 717         uint32_t logic_port = hw->mac.dglort_map;
 718         uint16_t buf_size;
 719         uint16_t queue_stride = 0;
 720
 721         /* enable RXINT for interrupt mode */
 722         i = 0;
 723         if (rte_intr_dp_is_en(intr_handle)) {
 724                 for (; i < dev->data->nb_rx_queues; i++) {
 725                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(dev, i));
 726                         if (hw->mac.type == fm10k_mac_pf)
 727                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
 728                                         FM10K_ITR_AUTOMASK |
 729                                         FM10K_ITR_MASK_CLEAR);
 730                         else
 731                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
 732                                         FM10K_ITR_AUTOMASK |
 733                                         FM10K_ITR_MASK_CLEAR);
 734                 }
 735         }
 736         /* Disable other RXINT to avoid possible interrupt */
 737         for (; i < hw->mac.max_queues; i++)
 738                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 739                         3 << FM10K_RXINT_TIMER_SHIFT);
 740
 741         /* Setup RX queues */
 742         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 743                 rxq = dev->data->rx_queues[i];
 744                 base_addr = rxq->hw_ring_phys_addr;
 745                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 746
 747                 /* disable queue to avoid issues while updating state */
 748                 ret = rx_queue_disable(hw, i);
 749                 if (ret) {
 750                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 751                         return -1;
 752                 }
 753
 754                 /* Setup the Base and Length of the Rx Descriptor Ring */
 755                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 756                                 base_addr & UINT64_LOWER_32BITS_MASK);
 757                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 758                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 759                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 760
 761                 /* Configure the Rx buffer size for one buff without split */
 762                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 763                         RTE_PKTMBUF_HEADROOM);
 764                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 765                  * reserved for this purpose, and the worst case could be 511B.
 766                  * But SRR reg assumes all buffers have the same size. In order
 767                  * to fill the gap, we'll have to consider the worst case and
 768                  * assume 512B is reserved. If we don't do so, it's possible
 769                  * for HW to overwrite data to next mbuf.
 770                  */
 771                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 772
 773                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 774                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 775                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 776
 777                 /* It adds dual VLAN length for supporting dual VLAN */
 778                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 779                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 780                         dev->data->dev_conf.rxmode.enable_scatter) {
 781                         uint32_t reg;
 782                         dev->data->scattered_rx = 1;
 783                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 784                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 785                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 786                 }
 787
 788                 /* Enable drop on empty, it's RO for VF */
 789                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 790                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 791
 792                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 793                 FM10K_WRITE_FLUSH(hw);
 794         }
 795
 796         /* Configure VMDQ/RSS if applicable */
 797         fm10k_dev_mq_rx_configure(dev);
 798
 799         /* Decide the best RX function */
 800         fm10k_set_rx_function(dev);
 801
 802         /* update RX_SGLORT for loopback suppress*/
 803         if (hw->mac.type != fm10k_mac_pf)
 804                 return 0;
 805         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 806         if (macvlan->nb_queue_pools)
 807                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 808         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 809                 if (i && queue_stride && !(i % queue_stride))
 810                         logic_port++;
 811                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 812         }
 813
 814         return 0;
 815 }
 816
 817 static int
 818 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 819 {
 820         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 821         int err = -1;
 822         uint32_t reg;
 823         struct fm10k_rx_queue *rxq;
 824
 825         PMD_INIT_FUNC_TRACE();
 826
 827         if (rx_queue_id < dev->data->nb_rx_queues) {
 828                 rxq = dev->data->rx_queues[rx_queue_id];
 829                 err = rx_queue_reset(rxq);
 830                 if (err == -ENOMEM) {
 831                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 832                         return err;
 833                 } else if (err == -EINVAL) {
 834                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 835                                 " %d", err);
 836                         return err;
 837                 }
 838
 839                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 840                  * Note: this must be done AFTER the queue is enabled on real
 841                  * hardware, but BEFORE the queue is enabled when using the
 842                  * emulation platform. Do it in both places for now and remove
 843                  * this comment and the following two register writes when the
 844                  * emulation platform is no longer being used.
 845                  */
 846                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 847                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 848
 849                 /* Set PF ownership flag for PF devices */
 850                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 851                 if (hw->mac.type == fm10k_mac_pf)
 852                         reg |= FM10K_RXQCTL_PF;
 853                 reg |= FM10K_RXQCTL_ENABLE;
 854                 /* enable RX queue */
 855                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 856                 FM10K_WRITE_FLUSH(hw);
 857
 858                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 859                  * Note: this must be done AFTER the queue is enabled
 860                  */
 861                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 862                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 863                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 864         }
 865
 866         return err;
 867 }
 868
 869 static int
 870 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 871 {
 872         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 873
 874         PMD_INIT_FUNC_TRACE();
 875
 876         if (rx_queue_id < dev->data->nb_rx_queues) {
 877                 /* Disable RX queue */
 878                 rx_queue_disable(hw, rx_queue_id);
 879
 880                 /* Free mbuf and clean HW ring */
 881                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 882                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int
 889 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 890 {
 891         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 892         /** @todo - this should be defined in the shared code */
 893 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 894         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 895         int err = 0;
 896
 897         PMD_INIT_FUNC_TRACE();
 898
 899         if (tx_queue_id < dev->data->nb_tx_queues) {
 900                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 901
 902                 q->ops->reset(q);
 903
 904                 /* reset head and tail pointers */
 905                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 906                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 907
 908                 /* enable TX queue */
 909                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 910                                         FM10K_TXDCTL_ENABLE | txdctl);
 911                 FM10K_WRITE_FLUSH(hw);
 912                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 913         } else
 914                 err = -1;
 915
 916         return err;
 917 }
 918
 919 static int
 920 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 921 {
 922         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         PMD_INIT_FUNC_TRACE();
 925
 926         if (tx_queue_id < dev->data->nb_tx_queues) {
 927                 tx_queue_disable(hw, tx_queue_id);
 928                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 929                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 930         }
 931
 932         return 0;
 933 }
 934
 935 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 936 {
 937         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 938                 != FM10K_DGLORTMAP_NONE);
 939 }
 940
 941 static void
 942 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 943 {
 944         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 945         int status;
 946
 947         PMD_INIT_FUNC_TRACE();
 948
 949         /* Return if it didn't acquire valid glort range */
 950         if (!fm10k_glort_valid(hw))
 951                 return;
 952
 953         fm10k_mbx_lock(hw);
 954         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 955                                 FM10K_XCAST_MODE_PROMISC);
 956         fm10k_mbx_unlock(hw);
 957
 958         if (status != FM10K_SUCCESS)
 959                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 960 }
 961
 962 static void
 963 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 964 {
 965         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         uint8_t mode;
 967         int status;
 968
 969         PMD_INIT_FUNC_TRACE();
 970
 971         /* Return if it didn't acquire valid glort range */
 972         if (!fm10k_glort_valid(hw))
 973                 return;
 974
 975         if (dev->data->all_multicast == 1)
 976                 mode = FM10K_XCAST_MODE_ALLMULTI;
 977         else
 978                 mode = FM10K_XCAST_MODE_NONE;
 979
 980         fm10k_mbx_lock(hw);
 981         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 982                                 mode);
 983         fm10k_mbx_unlock(hw);
 984
 985         if (status != FM10K_SUCCESS)
 986                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 987 }
 988
 989 static void
 990 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 991 {
 992         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 993         int status;
 994
 995         PMD_INIT_FUNC_TRACE();
 996
 997         /* Return if it didn't acquire valid glort range */
 998         if (!fm10k_glort_valid(hw))
 999                 return;
1000
1001         /* If promiscuous mode is enabled, it doesn't make sense to enable
1002          * allmulticast and disable promiscuous since fm10k only can select
1003          * one of the modes.
1004          */
1005         if (dev->data->promiscuous) {
1006                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1007                         "needn't enable allmulticast");
1008                 return;
1009         }
1010
1011         fm10k_mbx_lock(hw);
1012         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1013                                 FM10K_XCAST_MODE_ALLMULTI);
1014         fm10k_mbx_unlock(hw);
1015
1016         if (status != FM10K_SUCCESS)
1017                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1018 }
1019
1020 static void
1021 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1022 {
1023         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         int status;
1025
1026         PMD_INIT_FUNC_TRACE();
1027
1028         /* Return if it didn't acquire valid glort range */
1029         if (!fm10k_glort_valid(hw))
1030                 return;
1031
1032         if (dev->data->promiscuous) {
1033                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1034                         "since promisc mode is enabled");
1035                 return;
1036         }
1037
1038         fm10k_mbx_lock(hw);
1039         /* Change mode to unicast mode */
1040         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1041                                 FM10K_XCAST_MODE_NONE);
1042         fm10k_mbx_unlock(hw);
1043
1044         if (status != FM10K_SUCCESS)
1045                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1046 }
1047
1048 static void
1049 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1050 {
1051         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1053         uint16_t nb_queue_pools;
1054         struct fm10k_macvlan_filter_info *macvlan;
1055
1056         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1057         nb_queue_pools = macvlan->nb_queue_pools;
1058         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1059         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1060
1061         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1062         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1063         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1064                         hw->mac.dglort_map;
1065         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1066         /* Configure VMDQ/RSS DGlort Decoder */
1067         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1068
1069         /* Flow Director configurations, only queue number is valid. */
1070         dglortdec = fls(dev->data->nb_rx_queues - 1);
1071         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1072                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1073         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1074         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1075
1076         /* Invalidate all other GLORT entries */
1077         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1078                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1079                                 FM10K_DGLORTMAP_NONE);
1080 }
1081
1082 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1083 static int
1084 fm10k_dev_start(struct rte_eth_dev *dev)
1085 {
1086         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087         int i, diag;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         /* stop, init, then start the hw */
1092         diag = fm10k_stop_hw(hw);
1093         if (diag != FM10K_SUCCESS) {
1094                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1095                 return -EIO;
1096         }
1097
1098         diag = fm10k_init_hw(hw);
1099         if (diag != FM10K_SUCCESS) {
1100                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1101                 return -EIO;
1102         }
1103
1104         diag = fm10k_start_hw(hw);
1105         if (diag != FM10K_SUCCESS) {
1106                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1107                 return -EIO;
1108         }
1109
1110         diag = fm10k_dev_tx_init(dev);
1111         if (diag) {
1112                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1113                 return diag;
1114         }
1115
1116         if (fm10k_dev_rxq_interrupt_setup(dev))
1117                 return -EIO;
1118
1119         diag = fm10k_dev_rx_init(dev);
1120         if (diag) {
1121                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1122                 return diag;
1123         }
1124
1125         if (hw->mac.type == fm10k_mac_pf)
1126                 fm10k_dev_dglort_map_configure(dev);
1127
1128         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1129                 struct fm10k_rx_queue *rxq;
1130                 rxq = dev->data->rx_queues[i];
1131
1132                 if (rxq->rx_deferred_start)
1133                         continue;
1134                 diag = fm10k_dev_rx_queue_start(dev, i);
1135                 if (diag != 0) {
1136                         int j;
1137                         for (j = 0; j < i; ++j)
1138                                 rx_queue_clean(dev->data->rx_queues[j]);
1139                         return diag;
1140                 }
1141         }
1142
1143         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1144                 struct fm10k_tx_queue *txq;
1145                 txq = dev->data->tx_queues[i];
1146
1147                 if (txq->tx_deferred_start)
1148                         continue;
1149                 diag = fm10k_dev_tx_queue_start(dev, i);
1150                 if (diag != 0) {
1151                         int j;
1152                         for (j = 0; j < i; ++j)
1153                                 tx_queue_clean(dev->data->tx_queues[j]);
1154                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1155                                 rx_queue_clean(dev->data->rx_queues[j]);
1156                         return diag;
1157                 }
1158         }
1159
1160         /* Update default vlan when not in VMDQ mode */
1161         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1162                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1163
1164         return 0;
1165 }
1166
1167 static void
1168 fm10k_dev_stop(struct rte_eth_dev *dev)
1169 {
1170         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1171         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1172         int i;
1173
1174         PMD_INIT_FUNC_TRACE();
1175
1176         if (dev->data->tx_queues)
1177                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1178                         fm10k_dev_tx_queue_stop(dev, i);
1179
1180         if (dev->data->rx_queues)
1181                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1182                         fm10k_dev_rx_queue_stop(dev, i);
1183
1184         /* Disable datapath event */
1185         if (rte_intr_dp_is_en(intr_handle)) {
1186                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1187                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1188                                 3 << FM10K_RXINT_TIMER_SHIFT);
1189                         if (hw->mac.type == fm10k_mac_pf)
1190                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
1191                                         FM10K_ITR_MASK_SET);
1192                         else
1193                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
1194                                         FM10K_ITR_MASK_SET);
1195                 }
1196         }
1197         /* Clean datapath event and queue/vec mapping */
1198         rte_intr_efd_disable(intr_handle);
1199         rte_free(intr_handle->intr_vec);
1200         intr_handle->intr_vec = NULL;
1201 }
1202
1203 static void
1204 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1205 {
1206         int i;
1207
1208         PMD_INIT_FUNC_TRACE();
1209
1210         if (dev->data->tx_queues) {
1211                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1212                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1213
1214                         tx_queue_free(txq);
1215                 }
1216         }
1217
1218         if (dev->data->rx_queues) {
1219                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1220                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1221         }
1222 }
1223
1224 static void
1225 fm10k_dev_close(struct rte_eth_dev *dev)
1226 {
1227         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1228
1229         PMD_INIT_FUNC_TRACE();
1230
1231         fm10k_mbx_lock(hw);
1232         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1233                 MAX_LPORT_NUM, false);
1234         fm10k_mbx_unlock(hw);
1235
1236         /* Stop mailbox service first */
1237         fm10k_close_mbx_service(hw);
1238         fm10k_dev_stop(dev);
1239         fm10k_dev_queue_release(dev);
1240         fm10k_stop_hw(hw);
1241 }
1242
1243 static int
1244 fm10k_link_update(struct rte_eth_dev *dev,
1245         __rte_unused int wait_to_complete)
1246 {
1247         PMD_INIT_FUNC_TRACE();
1248
1249         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1250          * x8 PCIe interface. For now, we leave the speed undefined since there
1251          * is no 50Gbps Ethernet. */
1252         dev->data->dev_link.link_speed  = 0;
1253         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1254         dev->data->dev_link.link_status = ETH_LINK_UP;
1255
1256         return 0;
1257 }
1258
1259 static int
1260 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1261                  unsigned n)
1262 {
1263         struct fm10k_hw_stats *hw_stats =
1264                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1265         unsigned i, q, count = 0;
1266
1267         if (n < FM10K_NB_XSTATS)
1268                 return FM10K_NB_XSTATS;
1269
1270         /* Global stats */
1271         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1272                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1273                          "%s", fm10k_hw_stats_strings[count].name);
1274                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1275                         fm10k_hw_stats_strings[count].offset);
1276                 count++;
1277         }
1278
1279         /* PF queue stats */
1280         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1281                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1282                         snprintf(xstats[count].name, sizeof(xstats[count].name),
1283                                  "rx_q%u_%s", q,
1284                                  fm10k_hw_stats_rx_q_strings[i].name);
1285                         xstats[count].value =
1286                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1287                                 fm10k_hw_stats_rx_q_strings[i].offset);
1288                         count++;
1289                 }
1290                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1291                         snprintf(xstats[count].name, sizeof(xstats[count].name),
1292                                  "tx_q%u_%s", q,
1293                                  fm10k_hw_stats_tx_q_strings[i].name);
1294                         xstats[count].value =
1295                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1296                                 fm10k_hw_stats_tx_q_strings[i].offset);
1297                         count++;
1298                 }
1299         }
1300
1301         return FM10K_NB_XSTATS;
1302 }
1303
1304 static void
1305 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1306 {
1307         uint64_t ipackets, opackets, ibytes, obytes;
1308         struct fm10k_hw *hw =
1309                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1310         struct fm10k_hw_stats *hw_stats =
1311                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1312         int i;
1313
1314         PMD_INIT_FUNC_TRACE();
1315
1316         fm10k_update_hw_stats(hw, hw_stats);
1317
1318         ipackets = opackets = ibytes = obytes = 0;
1319         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1320                 (i < hw->mac.max_queues); ++i) {
1321                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1322                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1323                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1324                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1325                 ipackets += stats->q_ipackets[i];
1326                 opackets += stats->q_opackets[i];
1327                 ibytes   += stats->q_ibytes[i];
1328                 obytes   += stats->q_obytes[i];
1329         }
1330         stats->ipackets = ipackets;
1331         stats->opackets = opackets;
1332         stats->ibytes = ibytes;
1333         stats->obytes = obytes;
1334 }
1335
1336 static void
1337 fm10k_stats_reset(struct rte_eth_dev *dev)
1338 {
1339         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340         struct fm10k_hw_stats *hw_stats =
1341                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1342
1343         PMD_INIT_FUNC_TRACE();
1344
1345         memset(hw_stats, 0, sizeof(*hw_stats));
1346         fm10k_rebind_hw_stats(hw, hw_stats);
1347 }
1348
1349 static void
1350 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1351         struct rte_eth_dev_info *dev_info)
1352 {
1353         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354
1355         PMD_INIT_FUNC_TRACE();
1356
1357         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1358         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1359         dev_info->max_rx_queues      = hw->mac.max_queues;
1360         dev_info->max_tx_queues      = hw->mac.max_queues;
1361         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1362         dev_info->max_hash_mac_addrs = 0;
1363         dev_info->max_vfs            = dev->pci_dev->max_vfs;
1364         dev_info->vmdq_pool_base     = 0;
1365         dev_info->vmdq_queue_base    = 0;
1366         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1367         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1368         dev_info->rx_offload_capa =
1369                 DEV_RX_OFFLOAD_VLAN_STRIP |
1370                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1371                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1372                 DEV_RX_OFFLOAD_TCP_CKSUM;
1373         dev_info->tx_offload_capa =
1374                 DEV_TX_OFFLOAD_VLAN_INSERT |
1375                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1376                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1377                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1378                 DEV_TX_OFFLOAD_TCP_TSO;
1379
1380         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1381         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1382
1383         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1384                 .rx_thresh = {
1385                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1386                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1387                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1388                 },
1389                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1390                 .rx_drop_en = 0,
1391         };
1392
1393         dev_info->default_txconf = (struct rte_eth_txconf) {
1394                 .tx_thresh = {
1395                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1396                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1397                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1398                 },
1399                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1400                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1401                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1402         };
1403
1404         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1405                 .nb_max = FM10K_MAX_RX_DESC,
1406                 .nb_min = FM10K_MIN_RX_DESC,
1407                 .nb_align = FM10K_MULT_RX_DESC,
1408         };
1409
1410         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1411                 .nb_max = FM10K_MAX_TX_DESC,
1412                 .nb_min = FM10K_MIN_TX_DESC,
1413                 .nb_align = FM10K_MULT_TX_DESC,
1414         };
1415
1416         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1417                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1418                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1419 }
1420
1421 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1422 static const uint32_t *
1423 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1424 {
1425         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1426             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1427                 static uint32_t ptypes[] = {
1428                         /* refers to rx_desc_to_ol_flags() */
1429                         RTE_PTYPE_L2_ETHER,
1430                         RTE_PTYPE_L3_IPV4,
1431                         RTE_PTYPE_L3_IPV4_EXT,
1432                         RTE_PTYPE_L3_IPV6,
1433                         RTE_PTYPE_L3_IPV6_EXT,
1434                         RTE_PTYPE_L4_TCP,
1435                         RTE_PTYPE_L4_UDP,
1436                         RTE_PTYPE_UNKNOWN
1437                 };
1438
1439                 return ptypes;
1440         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1441                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1442                 static uint32_t ptypes_vec[] = {
1443                         /* refers to fm10k_desc_to_pktype_v() */
1444                         RTE_PTYPE_L3_IPV4,
1445                         RTE_PTYPE_L3_IPV4_EXT,
1446                         RTE_PTYPE_L3_IPV6,
1447                         RTE_PTYPE_L3_IPV6_EXT,
1448                         RTE_PTYPE_L4_TCP,
1449                         RTE_PTYPE_L4_UDP,
1450                         RTE_PTYPE_TUNNEL_GENEVE,
1451                         RTE_PTYPE_TUNNEL_NVGRE,
1452                         RTE_PTYPE_TUNNEL_VXLAN,
1453                         RTE_PTYPE_TUNNEL_GRE,
1454                         RTE_PTYPE_UNKNOWN
1455                 };
1456
1457                 return ptypes_vec;
1458         }
1459
1460         return NULL;
1461 }
1462 #else
1463 static const uint32_t *
1464 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1465 {
1466         return NULL;
1467 }
1468 #endif
1469
1470 static int
1471 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1472 {
1473         s32 result;
1474         uint16_t mac_num = 0;
1475         uint32_t vid_idx, vid_bit, mac_index;
1476         struct fm10k_hw *hw;
1477         struct fm10k_macvlan_filter_info *macvlan;
1478         struct rte_eth_dev_data *data = dev->data;
1479
1480         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1482
1483         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1484                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1485                 return -EINVAL;
1486         }
1487
1488         if (vlan_id > ETH_VLAN_ID_MAX) {
1489                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1490                 return -EINVAL;
1491         }
1492
1493         vid_idx = FM10K_VFTA_IDX(vlan_id);
1494         vid_bit = FM10K_VFTA_BIT(vlan_id);
1495         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1496         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1497                 return 0;
1498         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1499         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1500                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1501                         "in the VLAN filter table");
1502                 return -EINVAL;
1503         }
1504
1505         fm10k_mbx_lock(hw);
1506         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1507         fm10k_mbx_unlock(hw);
1508         if (result != FM10K_SUCCESS) {
1509                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1510                 return -EIO;
1511         }
1512
1513         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1514                         (result == FM10K_SUCCESS); mac_index++) {
1515                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1516                         continue;
1517                 if (mac_num > macvlan->mac_num - 1) {
1518                         PMD_INIT_LOG(ERR, "MAC address number "
1519                                         "not match");
1520                         break;
1521                 }
1522                 fm10k_mbx_lock(hw);
1523                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1524                         data->mac_addrs[mac_index].addr_bytes,
1525                         vlan_id, on, 0);
1526                 fm10k_mbx_unlock(hw);
1527                 mac_num++;
1528         }
1529         if (result != FM10K_SUCCESS) {
1530                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1531                 return -EIO;
1532         }
1533
1534         if (on) {
1535                 macvlan->vlan_num++;
1536                 macvlan->vfta[vid_idx] |= vid_bit;
1537         } else {
1538                 macvlan->vlan_num--;
1539                 macvlan->vfta[vid_idx] &= ~vid_bit;
1540         }
1541         return 0;
1542 }
1543
1544 static void
1545 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1546 {
1547         if (mask & ETH_VLAN_STRIP_MASK) {
1548                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1549                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1550                                         "always on in fm10k");
1551         }
1552
1553         if (mask & ETH_VLAN_EXTEND_MASK) {
1554                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1555                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1556                                         "supported in fm10k");
1557         }
1558
1559         if (mask & ETH_VLAN_FILTER_MASK) {
1560                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1561                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1562         }
1563 }
1564
1565 /* Add/Remove a MAC address, and update filters to main VSI */
1566 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1567                 const u8 *mac, bool add, uint32_t pool)
1568 {
1569         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570         struct fm10k_macvlan_filter_info *macvlan;
1571         uint32_t i, j, k;
1572
1573         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1574
1575         if (pool != MAIN_VSI_POOL_NUMBER) {
1576                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1577                         "mac to pool %u", pool);
1578                 return;
1579         }
1580         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1581                 if (!macvlan->vfta[j])
1582                         continue;
1583                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1584                         if (!(macvlan->vfta[j] & (1 << k)))
1585                                 continue;
1586                         if (i + 1 > macvlan->vlan_num) {
1587                                 PMD_INIT_LOG(ERR, "vlan number not match");
1588                                 return;
1589                         }
1590                         fm10k_mbx_lock(hw);
1591                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1592                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1593                         fm10k_mbx_unlock(hw);
1594                         i++;
1595                 }
1596         }
1597 }
1598
1599 /* Add/Remove a MAC address, and update filters to VMDQ */
1600 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1601                 const u8 *mac, bool add, uint32_t pool)
1602 {
1603         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604         struct fm10k_macvlan_filter_info *macvlan;
1605         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1606         uint32_t i;
1607
1608         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1609         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1610
1611         if (pool > macvlan->nb_queue_pools) {
1612                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1613                         " Max pool is %u",
1614                         pool, macvlan->nb_queue_pools);
1615                 return;
1616         }
1617         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1618                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1619                         continue;
1620                 fm10k_mbx_lock(hw);
1621                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1622                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1623                 fm10k_mbx_unlock(hw);
1624         }
1625 }
1626
1627 /* Add/Remove a MAC address, and update filters */
1628 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1629                 const u8 *mac, bool add, uint32_t pool)
1630 {
1631         struct fm10k_macvlan_filter_info *macvlan;
1632
1633         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1634
1635         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1636                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1637         else
1638                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1639
1640         if (add)
1641                 macvlan->mac_num++;
1642         else
1643                 macvlan->mac_num--;
1644 }
1645
1646 /* Add a MAC address, and update filters */
1647 static void
1648 fm10k_macaddr_add(struct rte_eth_dev *dev,
1649                 struct ether_addr *mac_addr,
1650                 uint32_t index,
1651                 uint32_t pool)
1652 {
1653         struct fm10k_macvlan_filter_info *macvlan;
1654
1655         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1656         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1657         macvlan->mac_vmdq_id[index] = pool;
1658 }
1659
1660 /* Remove a MAC address, and update filters */
1661 static void
1662 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1663 {
1664         struct rte_eth_dev_data *data = dev->data;
1665         struct fm10k_macvlan_filter_info *macvlan;
1666
1667         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1668         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1669                         FALSE, macvlan->mac_vmdq_id[index]);
1670         macvlan->mac_vmdq_id[index] = 0;
1671 }
1672
1673 static inline int
1674 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1675 {
1676         if ((request < min) || (request > max) || ((request % mult) != 0))
1677                 return -1;
1678         else
1679                 return 0;
1680 }
1681
1682
1683 static inline int
1684 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1685 {
1686         if ((request < min) || (request > max) || ((div % request) != 0))
1687                 return -1;
1688         else
1689                 return 0;
1690 }
1691
1692 static inline int
1693 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1694 {
1695         uint16_t rx_free_thresh;
1696
1697         if (conf->rx_free_thresh == 0)
1698                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1699         else
1700                 rx_free_thresh = conf->rx_free_thresh;
1701
1702         /* make sure the requested threshold satisfies the constraints */
1703         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1704                         FM10K_RX_FREE_THRESH_MAX(q),
1705                         FM10K_RX_FREE_THRESH_DIV(q),
1706                         rx_free_thresh)) {
1707                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1708                         "less than or equal to %u, "
1709                         "greater than or equal to %u, "
1710                         "and a divisor of %u",
1711                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1712                         FM10K_RX_FREE_THRESH_MIN(q),
1713                         FM10K_RX_FREE_THRESH_DIV(q));
1714                 return -EINVAL;
1715         }
1716
1717         q->alloc_thresh = rx_free_thresh;
1718         q->drop_en = conf->rx_drop_en;
1719         q->rx_deferred_start = conf->rx_deferred_start;
1720
1721         return 0;
1722 }
1723
1724 /*
1725  * Hardware requires specific alignment for Rx packet buffers. At
1726  * least one of the following two conditions must be satisfied.
1727  *  1. Address is 512B aligned
1728  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1729  *
1730  * As such, the driver may need to adjust the DMA address within the
1731  * buffer by up to 512B.
1732  *
1733  * return 1 if the element size is valid, otherwise return 0.
1734  */
1735 static int
1736 mempool_element_size_valid(struct rte_mempool *mp)
1737 {
1738         uint32_t min_size;
1739
1740         /* elt_size includes mbuf header and headroom */
1741         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1742                         RTE_PKTMBUF_HEADROOM;
1743
1744         /* account for up to 512B of alignment */
1745         min_size -= FM10K_RX_DATABUF_ALIGN;
1746
1747         /* sanity check for overflow */
1748         if (min_size > mp->elt_size)
1749                 return 0;
1750
1751         /* size is valid */
1752         return 1;
1753 }
1754
1755 static int
1756 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1757         uint16_t nb_desc, unsigned int socket_id,
1758         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1759 {
1760         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
1762         struct fm10k_rx_queue *q;
1763         const struct rte_memzone *mz;
1764
1765         PMD_INIT_FUNC_TRACE();
1766
1767         /* make sure the mempool element size can account for alignment. */
1768         if (!mempool_element_size_valid(mp)) {
1769                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1770                 return -EINVAL;
1771         }
1772
1773         /* make sure a valid number of descriptors have been requested */
1774         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1775                                 FM10K_MULT_RX_DESC, nb_desc)) {
1776                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1777                         "less than or equal to %"PRIu32", "
1778                         "greater than or equal to %u, "
1779                         "and a multiple of %u",
1780                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1781                         FM10K_MULT_RX_DESC);
1782                 return -EINVAL;
1783         }
1784
1785         /*
1786          * if this queue existed already, free the associated memory. The
1787          * queue cannot be reused in case we need to allocate memory on
1788          * different socket than was previously used.
1789          */
1790         if (dev->data->rx_queues[queue_id] != NULL) {
1791                 rx_queue_free(dev->data->rx_queues[queue_id]);
1792                 dev->data->rx_queues[queue_id] = NULL;
1793         }
1794
1795         /* allocate memory for the queue structure */
1796         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1797                                 socket_id);
1798         if (q == NULL) {
1799                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1800                 return -ENOMEM;
1801         }
1802
1803         /* setup queue */
1804         q->mp = mp;
1805         q->nb_desc = nb_desc;
1806         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1807         q->port_id = dev->data->port_id;
1808         q->queue_id = queue_id;
1809         q->tail_ptr = (volatile uint32_t *)
1810                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1811         if (handle_rxconf(q, conf))
1812                 return -EINVAL;
1813
1814         /* allocate memory for the software ring */
1815         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1816                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1817                         RTE_CACHE_LINE_SIZE, socket_id);
1818         if (q->sw_ring == NULL) {
1819                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1820                 rte_free(q);
1821                 return -ENOMEM;
1822         }
1823
1824         /*
1825          * allocate memory for the hardware descriptor ring. A memzone large
1826          * enough to hold the maximum ring size is requested to allow for
1827          * resizing in later calls to the queue setup function.
1828          */
1829         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1830                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1831                                       socket_id);
1832         if (mz == NULL) {
1833                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1834                 rte_free(q->sw_ring);
1835                 rte_free(q);
1836                 return -ENOMEM;
1837         }
1838         q->hw_ring = mz->addr;
1839         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1840
1841         /* Check if number of descs satisfied Vector requirement */
1842         if (!rte_is_power_of_2(nb_desc)) {
1843                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1844                                     "preconditions - canceling the feature for "
1845                                     "the whole port[%d]",
1846                              q->queue_id, q->port_id);
1847                 dev_info->rx_vec_allowed = false;
1848         } else
1849                 fm10k_rxq_vec_setup(q);
1850
1851         dev->data->rx_queues[queue_id] = q;
1852         return 0;
1853 }
1854
1855 static void
1856 fm10k_rx_queue_release(void *queue)
1857 {
1858         PMD_INIT_FUNC_TRACE();
1859
1860         rx_queue_free(queue);
1861 }
1862
1863 static inline int
1864 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1865 {
1866         uint16_t tx_free_thresh;
1867         uint16_t tx_rs_thresh;
1868
1869         /* constraint MACROs require that tx_free_thresh is configured
1870          * before tx_rs_thresh */
1871         if (conf->tx_free_thresh == 0)
1872                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1873         else
1874                 tx_free_thresh = conf->tx_free_thresh;
1875
1876         /* make sure the requested threshold satisfies the constraints */
1877         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1878                         FM10K_TX_FREE_THRESH_MAX(q),
1879                         FM10K_TX_FREE_THRESH_DIV(q),
1880                         tx_free_thresh)) {
1881                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1882                         "less than or equal to %u, "
1883                         "greater than or equal to %u, "
1884                         "and a divisor of %u",
1885                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1886                         FM10K_TX_FREE_THRESH_MIN(q),
1887                         FM10K_TX_FREE_THRESH_DIV(q));
1888                 return -EINVAL;
1889         }
1890
1891         q->free_thresh = tx_free_thresh;
1892
1893         if (conf->tx_rs_thresh == 0)
1894                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1895         else
1896                 tx_rs_thresh = conf->tx_rs_thresh;
1897
1898         q->tx_deferred_start = conf->tx_deferred_start;
1899
1900         /* make sure the requested threshold satisfies the constraints */
1901         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1902                         FM10K_TX_RS_THRESH_MAX(q),
1903                         FM10K_TX_RS_THRESH_DIV(q),
1904                         tx_rs_thresh)) {
1905                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1906                         "less than or equal to %u, "
1907                         "greater than or equal to %u, "
1908                         "and a divisor of %u",
1909                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1910                         FM10K_TX_RS_THRESH_MIN(q),
1911                         FM10K_TX_RS_THRESH_DIV(q));
1912                 return -EINVAL;
1913         }
1914
1915         q->rs_thresh = tx_rs_thresh;
1916
1917         return 0;
1918 }
1919
1920 static int
1921 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1922         uint16_t nb_desc, unsigned int socket_id,
1923         const struct rte_eth_txconf *conf)
1924 {
1925         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct fm10k_tx_queue *q;
1927         const struct rte_memzone *mz;
1928
1929         PMD_INIT_FUNC_TRACE();
1930
1931         /* make sure a valid number of descriptors have been requested */
1932         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1933                                 FM10K_MULT_TX_DESC, nb_desc)) {
1934                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1935                         "less than or equal to %"PRIu32", "
1936                         "greater than or equal to %u, "
1937                         "and a multiple of %u",
1938                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1939                         FM10K_MULT_TX_DESC);
1940                 return -EINVAL;
1941         }
1942
1943         /*
1944          * if this queue existed already, free the associated memory. The
1945          * queue cannot be reused in case we need to allocate memory on
1946          * different socket than was previously used.
1947          */
1948         if (dev->data->tx_queues[queue_id] != NULL) {
1949                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1950
1951                 tx_queue_free(txq);
1952                 dev->data->tx_queues[queue_id] = NULL;
1953         }
1954
1955         /* allocate memory for the queue structure */
1956         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1957                                 socket_id);
1958         if (q == NULL) {
1959                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1960                 return -ENOMEM;
1961         }
1962
1963         /* setup queue */
1964         q->nb_desc = nb_desc;
1965         q->port_id = dev->data->port_id;
1966         q->queue_id = queue_id;
1967         q->txq_flags = conf->txq_flags;
1968         q->ops = &def_txq_ops;
1969         q->tail_ptr = (volatile uint32_t *)
1970                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
1971         if (handle_txconf(q, conf))
1972                 return -EINVAL;
1973
1974         /* allocate memory for the software ring */
1975         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1976                                         nb_desc * sizeof(struct rte_mbuf *),
1977                                         RTE_CACHE_LINE_SIZE, socket_id);
1978         if (q->sw_ring == NULL) {
1979                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1980                 rte_free(q);
1981                 return -ENOMEM;
1982         }
1983
1984         /*
1985          * allocate memory for the hardware descriptor ring. A memzone large
1986          * enough to hold the maximum ring size is requested to allow for
1987          * resizing in later calls to the queue setup function.
1988          */
1989         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
1990                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
1991                                       socket_id);
1992         if (mz == NULL) {
1993                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1994                 rte_free(q->sw_ring);
1995                 rte_free(q);
1996                 return -ENOMEM;
1997         }
1998         q->hw_ring = mz->addr;
1999         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2000
2001         /*
2002          * allocate memory for the RS bit tracker. Enough slots to hold the
2003          * descriptor index for each RS bit needing to be set are required.
2004          */
2005         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2006                                 ((nb_desc + 1) / q->rs_thresh) *
2007                                 sizeof(uint16_t),
2008                                 RTE_CACHE_LINE_SIZE, socket_id);
2009         if (q->rs_tracker.list == NULL) {
2010                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2011                 rte_free(q->sw_ring);
2012                 rte_free(q);
2013                 return -ENOMEM;
2014         }
2015
2016         dev->data->tx_queues[queue_id] = q;
2017         return 0;
2018 }
2019
2020 static void
2021 fm10k_tx_queue_release(void *queue)
2022 {
2023         struct fm10k_tx_queue *q = queue;
2024         PMD_INIT_FUNC_TRACE();
2025
2026         tx_queue_free(q);
2027 }
2028
2029 static int
2030 fm10k_reta_update(struct rte_eth_dev *dev,
2031                         struct rte_eth_rss_reta_entry64 *reta_conf,
2032                         uint16_t reta_size)
2033 {
2034         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2035         uint16_t i, j, idx, shift;
2036         uint8_t mask;
2037         uint32_t reta;
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         if (reta_size > FM10K_MAX_RSS_INDICES) {
2042                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2043                         "(%d) doesn't match the number hardware can supported "
2044                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2045                 return -EINVAL;
2046         }
2047
2048         /*
2049          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2050          * 128-entries in 32 registers
2051          */
2052         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2053                 idx = i / RTE_RETA_GROUP_SIZE;
2054                 shift = i % RTE_RETA_GROUP_SIZE;
2055                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2056                                 BIT_MASK_PER_UINT32);
2057                 if (mask == 0)
2058                         continue;
2059
2060                 reta = 0;
2061                 if (mask != BIT_MASK_PER_UINT32)
2062                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2063
2064                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2065                         if (mask & (0x1 << j)) {
2066                                 if (mask != 0xF)
2067                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2068                                 reta |= reta_conf[idx].reta[shift + j] <<
2069                                                 (CHAR_BIT * j);
2070                         }
2071                 }
2072                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2073         }
2074
2075         return 0;
2076 }
2077
2078 static int
2079 fm10k_reta_query(struct rte_eth_dev *dev,
2080                         struct rte_eth_rss_reta_entry64 *reta_conf,
2081                         uint16_t reta_size)
2082 {
2083         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         uint16_t i, j, idx, shift;
2085         uint8_t mask;
2086         uint32_t reta;
2087
2088         PMD_INIT_FUNC_TRACE();
2089
2090         if (reta_size < FM10K_MAX_RSS_INDICES) {
2091                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2092                         "(%d) doesn't match the number hardware can supported "
2093                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2094                 return -EINVAL;
2095         }
2096
2097         /*
2098          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2099          * 128-entries in 32 registers
2100          */
2101         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2102                 idx = i / RTE_RETA_GROUP_SIZE;
2103                 shift = i % RTE_RETA_GROUP_SIZE;
2104                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2105                                 BIT_MASK_PER_UINT32);
2106                 if (mask == 0)
2107                         continue;
2108
2109                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2110                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2111                         if (mask & (0x1 << j))
2112                                 reta_conf[idx].reta[shift + j] = ((reta >>
2113                                         CHAR_BIT * j) & UINT8_MAX);
2114                 }
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int
2121 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2122         struct rte_eth_rss_conf *rss_conf)
2123 {
2124         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2126         uint32_t mrqc;
2127         uint64_t hf = rss_conf->rss_hf;
2128         int i;
2129
2130         PMD_INIT_FUNC_TRACE();
2131
2132         if (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2133                 FM10K_RSSRK_ENTRIES_PER_REG)
2134                 return -EINVAL;
2135
2136         if (hf == 0)
2137                 return -EINVAL;
2138
2139         mrqc = 0;
2140         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2141         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2142         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2143         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2144         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2145         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2146         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2147         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2148         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2149
2150         /* If the mapping doesn't fit any supported, return */
2151         if (mrqc == 0)
2152                 return -EINVAL;
2153
2154         if (key != NULL)
2155                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2156                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2157
2158         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2159
2160         return 0;
2161 }
2162
2163 static int
2164 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2165         struct rte_eth_rss_conf *rss_conf)
2166 {
2167         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2169         uint32_t mrqc;
2170         uint64_t hf;
2171         int i;
2172
2173         PMD_INIT_FUNC_TRACE();
2174
2175         if (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2176                                 FM10K_RSSRK_ENTRIES_PER_REG)
2177                 return -EINVAL;
2178
2179         if (key != NULL)
2180                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2181                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2182
2183         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2184         hf = 0;
2185         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2186         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2187         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2188         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2189         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2190         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2191         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2192         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2193         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2194
2195         rss_conf->rss_hf = hf;
2196
2197         return 0;
2198 }
2199
2200 static void
2201 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2202 {
2203         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2205
2206         /* Bind all local non-queue interrupt to vector 0 */
2207         int_map |= FM10K_MISC_VEC_ID;
2208
2209         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2210         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2211         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2212         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2213         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2214         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2215
2216         /* Enable misc causes */
2217         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2218                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2219                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2220                                 FM10K_EIMR_ENABLE(MAILBOX) |
2221                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2222                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2223                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2224                                 FM10K_EIMR_ENABLE(VFLR));
2225
2226         /* Enable ITR 0 */
2227         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2228                                         FM10K_ITR_MASK_CLEAR);
2229         FM10K_WRITE_FLUSH(hw);
2230 }
2231
2232 static void
2233 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2234 {
2235         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2236         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2237
2238         int_map |= FM10K_MISC_VEC_ID;
2239
2240         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2241         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2242         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2243         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2244         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2245         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2246
2247         /* Disable misc causes */
2248         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2249                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2250                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2251                                 FM10K_EIMR_DISABLE(MAILBOX) |
2252                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2253                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2254                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2255                                 FM10K_EIMR_DISABLE(VFLR));
2256
2257         /* Disable ITR 0 */
2258         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2259         FM10K_WRITE_FLUSH(hw);
2260 }
2261
2262 static void
2263 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2264 {
2265         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2266         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2267
2268         /* Bind all local non-queue interrupt to vector 0 */
2269         int_map |= FM10K_MISC_VEC_ID;
2270
2271         /* Only INT 0 available, other 15 are reserved. */
2272         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2273
2274         /* Enable ITR 0 */
2275         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2276                                         FM10K_ITR_MASK_CLEAR);
2277         FM10K_WRITE_FLUSH(hw);
2278 }
2279
2280 static void
2281 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2282 {
2283         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2284         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2285
2286         int_map |= FM10K_MISC_VEC_ID;
2287
2288         /* Only INT 0 available, other 15 are reserved. */
2289         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2290
2291         /* Disable ITR 0 */
2292         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2293         FM10K_WRITE_FLUSH(hw);
2294 }
2295
2296 static int
2297 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2298 {
2299         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300
2301         /* Enable ITR */
2302         if (hw->mac.type == fm10k_mac_pf)
2303                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2304                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2305         else
2306                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2307                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2308         rte_intr_enable(&dev->pci_dev->intr_handle);
2309         return 0;
2310 }
2311
2312 static int
2313 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2314 {
2315         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316
2317         /* Disable ITR */
2318         if (hw->mac.type == fm10k_mac_pf)
2319                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2320                         FM10K_ITR_MASK_SET);
2321         else
2322                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2323                         FM10K_ITR_MASK_SET);
2324         return 0;
2325 }
2326
2327 static int
2328 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2329 {
2330         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2332         uint32_t intr_vector, vec;
2333         uint16_t queue_id;
2334         int result = 0;
2335
2336         /* fm10k needs one separate interrupt for mailbox,
2337          * so only drivers which support multiple interrupt vectors
2338          * e.g. vfio-pci can work for fm10k interrupt mode
2339          */
2340         if (!rte_intr_cap_multiple(intr_handle) ||
2341                         dev->data->dev_conf.intr_conf.rxq == 0)
2342                 return result;
2343
2344         intr_vector = dev->data->nb_rx_queues;
2345
2346         /* disable interrupt first */
2347         rte_intr_disable(&dev->pci_dev->intr_handle);
2348         if (hw->mac.type == fm10k_mac_pf)
2349                 fm10k_dev_disable_intr_pf(dev);
2350         else
2351                 fm10k_dev_disable_intr_vf(dev);
2352
2353         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2354                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2355                 result = -EIO;
2356         }
2357
2358         if (rte_intr_dp_is_en(intr_handle) && !result) {
2359                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2360                         dev->data->nb_rx_queues * sizeof(int), 0);
2361                 if (intr_handle->intr_vec) {
2362                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2363                                         queue_id < dev->data->nb_rx_queues;
2364                                         queue_id++) {
2365                                 intr_handle->intr_vec[queue_id] = vec;
2366                                 if (vec < intr_handle->nb_efd - 1
2367                                                 + FM10K_RX_VEC_START)
2368                                         vec++;
2369                         }
2370                 } else {
2371                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2372                                 " intr_vec", dev->data->nb_rx_queues);
2373                         rte_intr_efd_disable(intr_handle);
2374                         result = -ENOMEM;
2375                 }
2376         }
2377
2378         if (hw->mac.type == fm10k_mac_pf)
2379                 fm10k_dev_enable_intr_pf(dev);
2380         else
2381                 fm10k_dev_enable_intr_vf(dev);
2382         rte_intr_enable(&dev->pci_dev->intr_handle);
2383         hw->mac.ops.update_int_moderator(hw);
2384         return result;
2385 }
2386
2387 static int
2388 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2389 {
2390         struct fm10k_fault fault;
2391         int err;
2392         const char *estr = "Unknown error";
2393
2394         /* Process PCA fault */
2395         if (eicr & FM10K_EICR_PCA_FAULT) {
2396                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2397                 if (err)
2398                         goto error;
2399                 switch (fault.type) {
2400                 case PCA_NO_FAULT:
2401                         estr = "PCA_NO_FAULT"; break;
2402                 case PCA_UNMAPPED_ADDR:
2403                         estr = "PCA_UNMAPPED_ADDR"; break;
2404                 case PCA_BAD_QACCESS_PF:
2405                         estr = "PCA_BAD_QACCESS_PF"; break;
2406                 case PCA_BAD_QACCESS_VF:
2407                         estr = "PCA_BAD_QACCESS_VF"; break;
2408                 case PCA_MALICIOUS_REQ:
2409                         estr = "PCA_MALICIOUS_REQ"; break;
2410                 case PCA_POISONED_TLP:
2411                         estr = "PCA_POISONED_TLP"; break;
2412                 case PCA_TLP_ABORT:
2413                         estr = "PCA_TLP_ABORT"; break;
2414                 default:
2415                         goto error;
2416                 }
2417                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2418                         estr, fault.func ? "VF" : "PF", fault.func,
2419                         fault.address, fault.specinfo);
2420         }
2421
2422         /* Process THI fault */
2423         if (eicr & FM10K_EICR_THI_FAULT) {
2424                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2425                 if (err)
2426                         goto error;
2427                 switch (fault.type) {
2428                 case THI_NO_FAULT:
2429                         estr = "THI_NO_FAULT"; break;
2430                 case THI_MAL_DIS_Q_FAULT:
2431                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2432                 default:
2433                         goto error;
2434                 }
2435                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2436                         estr, fault.func ? "VF" : "PF", fault.func,
2437                         fault.address, fault.specinfo);
2438         }
2439
2440         /* Process FUM fault */
2441         if (eicr & FM10K_EICR_FUM_FAULT) {
2442                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2443                 if (err)
2444                         goto error;
2445                 switch (fault.type) {
2446                 case FUM_NO_FAULT:
2447                         estr = "FUM_NO_FAULT"; break;
2448                 case FUM_UNMAPPED_ADDR:
2449                         estr = "FUM_UNMAPPED_ADDR"; break;
2450                 case FUM_POISONED_TLP:
2451                         estr = "FUM_POISONED_TLP"; break;
2452                 case FUM_BAD_VF_QACCESS:
2453                         estr = "FUM_BAD_VF_QACCESS"; break;
2454                 case FUM_ADD_DECODE_ERR:
2455                         estr = "FUM_ADD_DECODE_ERR"; break;
2456                 case FUM_RO_ERROR:
2457                         estr = "FUM_RO_ERROR"; break;
2458                 case FUM_QPRC_CRC_ERROR:
2459                         estr = "FUM_QPRC_CRC_ERROR"; break;
2460                 case FUM_CSR_TIMEOUT:
2461                         estr = "FUM_CSR_TIMEOUT"; break;
2462                 case FUM_INVALID_TYPE:
2463                         estr = "FUM_INVALID_TYPE"; break;
2464                 case FUM_INVALID_LENGTH:
2465                         estr = "FUM_INVALID_LENGTH"; break;
2466                 case FUM_INVALID_BE:
2467                         estr = "FUM_INVALID_BE"; break;
2468                 case FUM_INVALID_ALIGN:
2469                         estr = "FUM_INVALID_ALIGN"; break;
2470                 default:
2471                         goto error;
2472                 }
2473                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2474                         estr, fault.func ? "VF" : "PF", fault.func,
2475                         fault.address, fault.specinfo);
2476         }
2477
2478         return 0;
2479 error:
2480         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2481         return err;
2482 }
2483
2484 /**
2485  * PF interrupt handler triggered by NIC for handling specific interrupt.
2486  *
2487  * @param handle
2488  *  Pointer to interrupt handle.
2489  * @param param
2490  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2491  *
2492  * @return
2493  *  void
2494  */
2495 static void
2496 fm10k_dev_interrupt_handler_pf(
2497                         __rte_unused struct rte_intr_handle *handle,
2498                         void *param)
2499 {
2500         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2501         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502         uint32_t cause, status;
2503
2504         if (hw->mac.type != fm10k_mac_pf)
2505                 return;
2506
2507         cause = FM10K_READ_REG(hw, FM10K_EICR);
2508
2509         /* Handle PCI fault cases */
2510         if (cause & FM10K_EICR_FAULT_MASK) {
2511                 PMD_INIT_LOG(ERR, "INT: find fault!");
2512                 fm10k_dev_handle_fault(hw, cause);
2513         }
2514
2515         /* Handle switch up/down */
2516         if (cause & FM10K_EICR_SWITCHNOTREADY)
2517                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2518
2519         if (cause & FM10K_EICR_SWITCHREADY)
2520                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2521
2522         /* Handle mailbox message */
2523         fm10k_mbx_lock(hw);
2524         hw->mbx.ops.process(hw, &hw->mbx);
2525         fm10k_mbx_unlock(hw);
2526
2527         /* Handle SRAM error */
2528         if (cause & FM10K_EICR_SRAMERROR) {
2529                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2530
2531                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2532                 /* Write to clear pending bits */
2533                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2534
2535                 /* Todo: print out error message after shared code  updates */
2536         }
2537
2538         /* Clear these 3 events if having any */
2539         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2540                  FM10K_EICR_SWITCHREADY;
2541         if (cause)
2542                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2543
2544         /* Re-enable interrupt from device side */
2545         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2546                                         FM10K_ITR_MASK_CLEAR);
2547         /* Re-enable interrupt from host side */
2548         rte_intr_enable(&(dev->pci_dev->intr_handle));
2549 }
2550
2551 /**
2552  * VF interrupt handler triggered by NIC for handling specific interrupt.
2553  *
2554  * @param handle
2555  *  Pointer to interrupt handle.
2556  * @param param
2557  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2558  *
2559  * @return
2560  *  void
2561  */
2562 static void
2563 fm10k_dev_interrupt_handler_vf(
2564                         __rte_unused struct rte_intr_handle *handle,
2565                         void *param)
2566 {
2567         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2568         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569
2570         if (hw->mac.type != fm10k_mac_vf)
2571                 return;
2572
2573         /* Handle mailbox message if lock is acquired */
2574         fm10k_mbx_lock(hw);
2575         hw->mbx.ops.process(hw, &hw->mbx);
2576         fm10k_mbx_unlock(hw);
2577
2578         /* Re-enable interrupt from device side */
2579         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2580                                         FM10K_ITR_MASK_CLEAR);
2581         /* Re-enable interrupt from host side */
2582         rte_intr_enable(&(dev->pci_dev->intr_handle));
2583 }
2584
2585 /* Mailbox message handler in VF */
2586 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2587         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2588         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2589         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2590         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2591 };
2592
2593 static int
2594 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2595 {
2596         int err = 0;
2597
2598         /* Initialize mailbox lock */
2599         fm10k_mbx_initlock(hw);
2600
2601         /* Replace default message handler with new ones */
2602         if (hw->mac.type == fm10k_mac_vf)
2603                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2604
2605         if (err) {
2606                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2607                                 err);
2608                 return err;
2609         }
2610         /* Connect to SM for PF device or PF for VF device */
2611         return hw->mbx.ops.connect(hw, &hw->mbx);
2612 }
2613
2614 static void
2615 fm10k_close_mbx_service(struct fm10k_hw *hw)
2616 {
2617         /* Disconnect from SM for PF device or PF for VF device */
2618         hw->mbx.ops.disconnect(hw, &hw->mbx);
2619 }
2620
2621 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2622         .dev_configure          = fm10k_dev_configure,
2623         .dev_start              = fm10k_dev_start,
2624         .dev_stop               = fm10k_dev_stop,
2625         .dev_close              = fm10k_dev_close,
2626         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2627         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2628         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2629         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2630         .stats_get              = fm10k_stats_get,
2631         .xstats_get             = fm10k_xstats_get,
2632         .stats_reset            = fm10k_stats_reset,
2633         .xstats_reset           = fm10k_stats_reset,
2634         .link_update            = fm10k_link_update,
2635         .dev_infos_get          = fm10k_dev_infos_get,
2636         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2637         .vlan_filter_set        = fm10k_vlan_filter_set,
2638         .vlan_offload_set       = fm10k_vlan_offload_set,
2639         .mac_addr_add           = fm10k_macaddr_add,
2640         .mac_addr_remove        = fm10k_macaddr_remove,
2641         .rx_queue_start         = fm10k_dev_rx_queue_start,
2642         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2643         .tx_queue_start         = fm10k_dev_tx_queue_start,
2644         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2645         .rx_queue_setup         = fm10k_rx_queue_setup,
2646         .rx_queue_release       = fm10k_rx_queue_release,
2647         .tx_queue_setup         = fm10k_tx_queue_setup,
2648         .tx_queue_release       = fm10k_tx_queue_release,
2649         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2650         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2651         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2652         .reta_update            = fm10k_reta_update,
2653         .reta_query             = fm10k_reta_query,
2654         .rss_hash_update        = fm10k_rss_hash_update,
2655         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2656 };
2657
2658 static int ftag_check_handler(__rte_unused const char *key,
2659                 const char *value, __rte_unused void *opaque)
2660 {
2661         if (strcmp(value, "1"))
2662                 return -1;
2663
2664         return 0;
2665 }
2666
2667 static int
2668 fm10k_check_ftag(struct rte_devargs *devargs)
2669 {
2670         struct rte_kvargs *kvlist;
2671         const char *ftag_key = "enable_ftag";
2672
2673         if (devargs == NULL)
2674                 return 0;
2675
2676         kvlist = rte_kvargs_parse(devargs->args, NULL);
2677         if (kvlist == NULL)
2678                 return 0;
2679
2680         if (!rte_kvargs_count(kvlist, ftag_key)) {
2681                 rte_kvargs_free(kvlist);
2682                 return 0;
2683         }
2684         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2685         if (rte_kvargs_process(kvlist, ftag_key,
2686                                 ftag_check_handler, NULL) < 0) {
2687                 rte_kvargs_free(kvlist);
2688                 return 0;
2689         }
2690         rte_kvargs_free(kvlist);
2691
2692         return 1;
2693 }
2694
2695 static void __attribute__((cold))
2696 fm10k_set_tx_function(struct rte_eth_dev *dev)
2697 {
2698         struct fm10k_tx_queue *txq;
2699         int i;
2700         int use_sse = 1;
2701         uint16_t tx_ftag_en = 0;
2702
2703         if (fm10k_check_ftag(dev->pci_dev->devargs))
2704                 tx_ftag_en = 1;
2705
2706         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2707                 txq = dev->data->tx_queues[i];
2708                 txq->tx_ftag_en = tx_ftag_en;
2709                 /* Check if Vector Tx is satisfied */
2710                 if (fm10k_tx_vec_condition_check(txq)) {
2711                         use_sse = 0;
2712                         break;
2713                 }
2714         }
2715
2716         if (use_sse) {
2717                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2718                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2719                         txq = dev->data->tx_queues[i];
2720                         fm10k_txq_vec_setup(txq);
2721                 }
2722                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2723         } else {
2724                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2725                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2726         }
2727 }
2728
2729 static void __attribute__((cold))
2730 fm10k_set_rx_function(struct rte_eth_dev *dev)
2731 {
2732         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2733         uint16_t i, rx_using_sse;
2734         uint16_t rx_ftag_en = 0;
2735
2736         if (fm10k_check_ftag(dev->pci_dev->devargs))
2737                 rx_ftag_en = 1;
2738
2739         /* In order to allow Vector Rx there are a few configuration
2740          * conditions to be met.
2741          */
2742         if (!fm10k_rx_vec_condition_check(dev) &&
2743                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2744                 if (dev->data->scattered_rx)
2745                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2746                 else
2747                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2748         } else if (dev->data->scattered_rx)
2749                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2750         else
2751                 dev->rx_pkt_burst = fm10k_recv_pkts;
2752
2753         rx_using_sse =
2754                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2755                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2756
2757         if (rx_using_sse)
2758                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2759         else
2760                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2761
2762         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2763                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2764
2765                 rxq->rx_using_sse = rx_using_sse;
2766                 rxq->rx_ftag_en = rx_ftag_en;
2767         }
2768 }
2769
2770 static void
2771 fm10k_params_init(struct rte_eth_dev *dev)
2772 {
2773         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         struct fm10k_dev_info *info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2775
2776         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2777          * there is no way to get link status without reading BAR4.  Until this
2778          * works, assume we have maximum bandwidth.
2779          * @todo - fix bus info
2780          */
2781         hw->bus_caps.speed = fm10k_bus_speed_8000;
2782         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2783         hw->bus_caps.payload = fm10k_bus_payload_512;
2784         hw->bus.speed = fm10k_bus_speed_8000;
2785         hw->bus.width = fm10k_bus_width_pcie_x8;
2786         hw->bus.payload = fm10k_bus_payload_256;
2787
2788         info->rx_vec_allowed = true;
2789 }
2790
2791 static int
2792 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2793 {
2794         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795         int diag, i;
2796         struct fm10k_macvlan_filter_info *macvlan;
2797
2798         PMD_INIT_FUNC_TRACE();
2799
2800         dev->dev_ops = &fm10k_eth_dev_ops;
2801         dev->rx_pkt_burst = &fm10k_recv_pkts;
2802         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2803
2804         /* only initialize in the primary process */
2805         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2806                 return 0;
2807
2808         rte_eth_copy_pci_info(dev, dev->pci_dev);
2809
2810         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2811         memset(macvlan, 0, sizeof(*macvlan));
2812         /* Vendor and Device ID need to be set before init of shared code */
2813         memset(hw, 0, sizeof(*hw));
2814         hw->device_id = dev->pci_dev->id.device_id;
2815         hw->vendor_id = dev->pci_dev->id.vendor_id;
2816         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
2817         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
2818         hw->revision_id = 0;
2819         hw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;
2820         if (hw->hw_addr == NULL) {
2821                 PMD_INIT_LOG(ERR, "Bad mem resource."
2822                         " Try to blacklist unused devices.");
2823                 return -EIO;
2824         }
2825
2826         /* Store fm10k_adapter pointer */
2827         hw->back = dev->data->dev_private;
2828
2829         /* Initialize the shared code */
2830         diag = fm10k_init_shared_code(hw);
2831         if (diag != FM10K_SUCCESS) {
2832                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2833                 return -EIO;
2834         }
2835
2836         /* Initialize parameters */
2837         fm10k_params_init(dev);
2838
2839         /* Initialize the hw */
2840         diag = fm10k_init_hw(hw);
2841         if (diag != FM10K_SUCCESS) {
2842                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2843                 return -EIO;
2844         }
2845
2846         /* Initialize MAC address(es) */
2847         dev->data->mac_addrs = rte_zmalloc("fm10k",
2848                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2849         if (dev->data->mac_addrs == NULL) {
2850                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2851                 return -ENOMEM;
2852         }
2853
2854         diag = fm10k_read_mac_addr(hw);
2855
2856         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2857                         &dev->data->mac_addrs[0]);
2858
2859         if (diag != FM10K_SUCCESS ||
2860                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2861
2862                 /* Generate a random addr */
2863                 eth_random_addr(hw->mac.addr);
2864                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2865                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2866                 &dev->data->mac_addrs[0]);
2867         }
2868
2869         /* Reset the hw statistics */
2870         fm10k_stats_reset(dev);
2871
2872         /* Reset the hw */
2873         diag = fm10k_reset_hw(hw);
2874         if (diag != FM10K_SUCCESS) {
2875                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2876                 return -EIO;
2877         }
2878
2879         /* Setup mailbox service */
2880         diag = fm10k_setup_mbx_service(hw);
2881         if (diag != FM10K_SUCCESS) {
2882                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2883                 return -EIO;
2884         }
2885
2886         /*PF/VF has different interrupt handling mechanism */
2887         if (hw->mac.type == fm10k_mac_pf) {
2888                 /* register callback func to eal lib */
2889                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2890                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2891
2892                 /* enable MISC interrupt */
2893                 fm10k_dev_enable_intr_pf(dev);
2894         } else { /* VF */
2895                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2896                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2897
2898                 fm10k_dev_enable_intr_vf(dev);
2899         }
2900
2901         /* Enable intr after callback registered */
2902         rte_intr_enable(&(dev->pci_dev->intr_handle));
2903
2904         hw->mac.ops.update_int_moderator(hw);
2905
2906         /* Make sure Switch Manager is ready before going forward. */
2907         if (hw->mac.type == fm10k_mac_pf) {
2908                 int switch_ready = 0;
2909
2910                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2911                         fm10k_mbx_lock(hw);
2912                         hw->mac.ops.get_host_state(hw, &switch_ready);
2913                         fm10k_mbx_unlock(hw);
2914                         if (switch_ready)
2915                                 break;
2916                         /* Delay some time to acquire async LPORT_MAP info. */
2917                         rte_delay_us(WAIT_SWITCH_MSG_US);
2918                 }
2919
2920                 if (switch_ready == 0) {
2921                         PMD_INIT_LOG(ERR, "switch is not ready");
2922                         return -1;
2923                 }
2924         }
2925
2926         /*
2927          * Below function will trigger operations on mailbox, acquire lock to
2928          * avoid race condition from interrupt handler. Operations on mailbox
2929          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2930          * will handle and generate an interrupt to our side. Then,  FIFO in
2931          * mailbox will be touched.
2932          */
2933         fm10k_mbx_lock(hw);
2934         /* Enable port first */
2935         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2936                                         MAX_LPORT_NUM, 1);
2937
2938         /* Set unicast mode by default. App can change to other mode in other
2939          * API func.
2940          */
2941         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2942                                         FM10K_XCAST_MODE_NONE);
2943
2944         fm10k_mbx_unlock(hw);
2945
2946         /* Make sure default VID is ready before going forward. */
2947         if (hw->mac.type == fm10k_mac_pf) {
2948                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2949                         if (hw->mac.default_vid)
2950                                 break;
2951                         /* Delay some time to acquire async port VLAN info. */
2952                         rte_delay_us(WAIT_SWITCH_MSG_US);
2953                 }
2954
2955                 if (!hw->mac.default_vid) {
2956                         PMD_INIT_LOG(ERR, "default VID is not ready");
2957                         return -1;
2958                 }
2959         }
2960
2961         /* Add default mac address */
2962         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2963                 MAIN_VSI_POOL_NUMBER);
2964
2965         return 0;
2966 }
2967
2968 static int
2969 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
2970 {
2971         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2972
2973         PMD_INIT_FUNC_TRACE();
2974
2975         /* only uninitialize in the primary process */
2976         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2977                 return 0;
2978
2979         /* safe to close dev here */
2980         fm10k_dev_close(dev);
2981
2982         dev->dev_ops = NULL;
2983         dev->rx_pkt_burst = NULL;
2984         dev->tx_pkt_burst = NULL;
2985
2986         /* disable uio/vfio intr */
2987         rte_intr_disable(&(dev->pci_dev->intr_handle));
2988
2989         /*PF/VF has different interrupt handling mechanism */
2990         if (hw->mac.type == fm10k_mac_pf) {
2991                 /* disable interrupt */
2992                 fm10k_dev_disable_intr_pf(dev);
2993
2994                 /* unregister callback func to eal lib */
2995                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
2996                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2997         } else {
2998                 /* disable interrupt */
2999                 fm10k_dev_disable_intr_vf(dev);
3000
3001                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3002                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3003         }
3004
3005         /* free mac memory */
3006         if (dev->data->mac_addrs) {
3007                 rte_free(dev->data->mac_addrs);
3008                 dev->data->mac_addrs = NULL;
3009         }
3010
3011         memset(hw, 0, sizeof(*hw));
3012
3013         return 0;
3014 }
3015
3016 /*
3017  * The set of PCI devices this driver supports. This driver will enable both PF
3018  * and SRIOV-VF devices.
3019  */
3020 static const struct rte_pci_id pci_id_fm10k_map[] = {
3021 #define RTE_PCI_DEV_ID_DECL_FM10K(vend, dev) { RTE_PCI_DEVICE(vend, dev) },
3022 #define RTE_PCI_DEV_ID_DECL_FM10KVF(vend, dev) { RTE_PCI_DEVICE(vend, dev) },
3023 #include "rte_pci_dev_ids.h"
3024         { .vendor_id = 0, /* sentinel */ },
3025 };
3026
3027 static struct eth_driver rte_pmd_fm10k = {
3028         .pci_drv = {
3029                 .name = "rte_pmd_fm10k",
3030                 .id_table = pci_id_fm10k_map,
3031                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3032                         RTE_PCI_DRV_DETACHABLE,
3033         },
3034         .eth_dev_init = eth_fm10k_dev_init,
3035         .eth_dev_uninit = eth_fm10k_dev_uninit,
3036         .dev_private_size = sizeof(struct fm10k_adapter),
3037 };
3038
3039 /*
3040  * Driver initialization routine.
3041  * Invoked once at EAL init time.
3042  * Register itself as the [Poll Mode] Driver of PCI FM10K devices.
3043  */
3044 static int
3045 rte_pmd_fm10k_init(__rte_unused const char *name,
3046         __rte_unused const char *params)
3047 {
3048         PMD_INIT_FUNC_TRACE();
3049         rte_eth_driver_register(&rte_pmd_fm10k);
3050         return 0;
3051 }
3052
3053 static struct rte_driver rte_fm10k_driver = {
3054         .type = PMD_PDEV,
3055         .init = rte_pmd_fm10k_init,
3056 };
3057
3058 PMD_REGISTER_DRIVER(rte_fm10k_driver);