drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_A0_SUPPORT
  75                 case I40E_DEV_ID_X722_A0:
  76 #endif
  77                 case I40E_DEV_ID_KX_X722:
  78                 case I40E_DEV_ID_QSFP_X722:
  79                 case I40E_DEV_ID_SFP_X722:
  80                 case I40E_DEV_ID_1G_BASE_T_X722:
  81                 case I40E_DEV_ID_10G_BASE_T_X722:
  82                 case I40E_DEV_ID_SFP_I_X722:
  83                         hw->mac.type = I40E_MAC_X722;
  84                         break;
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87 #ifdef X722_A0_SUPPORT
  88                 case I40E_DEV_ID_X722_A0_VF:
  89 #endif
  90                         hw->mac.type = I40E_MAC_X722_VF;
  91                         break;
  92 #endif /* INTEGRATED_VF || VF_DRIVER */
  93 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  94                 case I40E_DEV_ID_VF:
  95                 case I40E_DEV_ID_VF_HV:
  96                         hw->mac.type = I40E_MAC_VF;
  97                         break;
  98 #endif
  99                 default:
 100                         hw->mac.type = I40E_MAC_GENERIC;
 101                         break;
 102                 }
 103         } else {
 104                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 105         }
 106
 107         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 108                   hw->mac.type, status);
 109         return status;
 110 }
 111
 112 /**
 113  * i40e_aq_str - convert AQ err code to a string
 114  * @hw: pointer to the HW structure
 115  * @aq_err: the AQ error code to convert
 116  **/
 117 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 118 {
 119         switch (aq_err) {
 120         case I40E_AQ_RC_OK:
 121                 return "OK";
 122         case I40E_AQ_RC_EPERM:
 123                 return "I40E_AQ_RC_EPERM";
 124         case I40E_AQ_RC_ENOENT:
 125                 return "I40E_AQ_RC_ENOENT";
 126         case I40E_AQ_RC_ESRCH:
 127                 return "I40E_AQ_RC_ESRCH";
 128         case I40E_AQ_RC_EINTR:
 129                 return "I40E_AQ_RC_EINTR";
 130         case I40E_AQ_RC_EIO:
 131                 return "I40E_AQ_RC_EIO";
 132         case I40E_AQ_RC_ENXIO:
 133                 return "I40E_AQ_RC_ENXIO";
 134         case I40E_AQ_RC_E2BIG:
 135                 return "I40E_AQ_RC_E2BIG";
 136         case I40E_AQ_RC_EAGAIN:
 137                 return "I40E_AQ_RC_EAGAIN";
 138         case I40E_AQ_RC_ENOMEM:
 139                 return "I40E_AQ_RC_ENOMEM";
 140         case I40E_AQ_RC_EACCES:
 141                 return "I40E_AQ_RC_EACCES";
 142         case I40E_AQ_RC_EFAULT:
 143                 return "I40E_AQ_RC_EFAULT";
 144         case I40E_AQ_RC_EBUSY:
 145                 return "I40E_AQ_RC_EBUSY";
 146         case I40E_AQ_RC_EEXIST:
 147                 return "I40E_AQ_RC_EEXIST";
 148         case I40E_AQ_RC_EINVAL:
 149                 return "I40E_AQ_RC_EINVAL";
 150         case I40E_AQ_RC_ENOTTY:
 151                 return "I40E_AQ_RC_ENOTTY";
 152         case I40E_AQ_RC_ENOSPC:
 153                 return "I40E_AQ_RC_ENOSPC";
 154         case I40E_AQ_RC_ENOSYS:
 155                 return "I40E_AQ_RC_ENOSYS";
 156         case I40E_AQ_RC_ERANGE:
 157                 return "I40E_AQ_RC_ERANGE";
 158         case I40E_AQ_RC_EFLUSHED:
 159                 return "I40E_AQ_RC_EFLUSHED";
 160         case I40E_AQ_RC_BAD_ADDR:
 161                 return "I40E_AQ_RC_BAD_ADDR";
 162         case I40E_AQ_RC_EMODE:
 163                 return "I40E_AQ_RC_EMODE";
 164         case I40E_AQ_RC_EFBIG:
 165                 return "I40E_AQ_RC_EFBIG";
 166         }
 167
 168         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 169         return hw->err_str;
 170 }
 171
 172 /**
 173  * i40e_stat_str - convert status err code to a string
 174  * @hw: pointer to the HW structure
 175  * @stat_err: the status error code to convert
 176  **/
 177 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 178 {
 179         switch (stat_err) {
 180         case I40E_SUCCESS:
 181                 return "OK";
 182         case I40E_ERR_NVM:
 183                 return "I40E_ERR_NVM";
 184         case I40E_ERR_NVM_CHECKSUM:
 185                 return "I40E_ERR_NVM_CHECKSUM";
 186         case I40E_ERR_PHY:
 187                 return "I40E_ERR_PHY";
 188         case I40E_ERR_CONFIG:
 189                 return "I40E_ERR_CONFIG";
 190         case I40E_ERR_PARAM:
 191                 return "I40E_ERR_PARAM";
 192         case I40E_ERR_MAC_TYPE:
 193                 return "I40E_ERR_MAC_TYPE";
 194         case I40E_ERR_UNKNOWN_PHY:
 195                 return "I40E_ERR_UNKNOWN_PHY";
 196         case I40E_ERR_LINK_SETUP:
 197                 return "I40E_ERR_LINK_SETUP";
 198         case I40E_ERR_ADAPTER_STOPPED:
 199                 return "I40E_ERR_ADAPTER_STOPPED";
 200         case I40E_ERR_INVALID_MAC_ADDR:
 201                 return "I40E_ERR_INVALID_MAC_ADDR";
 202         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 203                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 204         case I40E_ERR_MASTER_REQUESTS_PENDING:
 205                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 206         case I40E_ERR_INVALID_LINK_SETTINGS:
 207                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 208         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 209                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 210         case I40E_ERR_RESET_FAILED:
 211                 return "I40E_ERR_RESET_FAILED";
 212         case I40E_ERR_SWFW_SYNC:
 213                 return "I40E_ERR_SWFW_SYNC";
 214         case I40E_ERR_NO_AVAILABLE_VSI:
 215                 return "I40E_ERR_NO_AVAILABLE_VSI";
 216         case I40E_ERR_NO_MEMORY:
 217                 return "I40E_ERR_NO_MEMORY";
 218         case I40E_ERR_BAD_PTR:
 219                 return "I40E_ERR_BAD_PTR";
 220         case I40E_ERR_RING_FULL:
 221                 return "I40E_ERR_RING_FULL";
 222         case I40E_ERR_INVALID_PD_ID:
 223                 return "I40E_ERR_INVALID_PD_ID";
 224         case I40E_ERR_INVALID_QP_ID:
 225                 return "I40E_ERR_INVALID_QP_ID";
 226         case I40E_ERR_INVALID_CQ_ID:
 227                 return "I40E_ERR_INVALID_CQ_ID";
 228         case I40E_ERR_INVALID_CEQ_ID:
 229                 return "I40E_ERR_INVALID_CEQ_ID";
 230         case I40E_ERR_INVALID_AEQ_ID:
 231                 return "I40E_ERR_INVALID_AEQ_ID";
 232         case I40E_ERR_INVALID_SIZE:
 233                 return "I40E_ERR_INVALID_SIZE";
 234         case I40E_ERR_INVALID_ARP_INDEX:
 235                 return "I40E_ERR_INVALID_ARP_INDEX";
 236         case I40E_ERR_INVALID_FPM_FUNC_ID:
 237                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 238         case I40E_ERR_QP_INVALID_MSG_SIZE:
 239                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 240         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 241                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 242         case I40E_ERR_INVALID_FRAG_COUNT:
 243                 return "I40E_ERR_INVALID_FRAG_COUNT";
 244         case I40E_ERR_QUEUE_EMPTY:
 245                 return "I40E_ERR_QUEUE_EMPTY";
 246         case I40E_ERR_INVALID_ALIGNMENT:
 247                 return "I40E_ERR_INVALID_ALIGNMENT";
 248         case I40E_ERR_FLUSHED_QUEUE:
 249                 return "I40E_ERR_FLUSHED_QUEUE";
 250         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 251                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 252         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 253                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 254         case I40E_ERR_TIMEOUT:
 255                 return "I40E_ERR_TIMEOUT";
 256         case I40E_ERR_OPCODE_MISMATCH:
 257                 return "I40E_ERR_OPCODE_MISMATCH";
 258         case I40E_ERR_CQP_COMPL_ERROR:
 259                 return "I40E_ERR_CQP_COMPL_ERROR";
 260         case I40E_ERR_INVALID_VF_ID:
 261                 return "I40E_ERR_INVALID_VF_ID";
 262         case I40E_ERR_INVALID_HMCFN_ID:
 263                 return "I40E_ERR_INVALID_HMCFN_ID";
 264         case I40E_ERR_BACKING_PAGE_ERROR:
 265                 return "I40E_ERR_BACKING_PAGE_ERROR";
 266         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 267                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 268         case I40E_ERR_INVALID_PBLE_INDEX:
 269                 return "I40E_ERR_INVALID_PBLE_INDEX";
 270         case I40E_ERR_INVALID_SD_INDEX:
 271                 return "I40E_ERR_INVALID_SD_INDEX";
 272         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 273                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 274         case I40E_ERR_INVALID_SD_TYPE:
 275                 return "I40E_ERR_INVALID_SD_TYPE";
 276         case I40E_ERR_MEMCPY_FAILED:
 277                 return "I40E_ERR_MEMCPY_FAILED";
 278         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 279                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 280         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 281                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 282         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 283                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 284         case I40E_ERR_SRQ_ENABLED:
 285                 return "I40E_ERR_SRQ_ENABLED";
 286         case I40E_ERR_ADMIN_QUEUE_ERROR:
 287                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 288         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 289                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 290         case I40E_ERR_BUF_TOO_SHORT:
 291                 return "I40E_ERR_BUF_TOO_SHORT";
 292         case I40E_ERR_ADMIN_QUEUE_FULL:
 293                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 294         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 295                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 296         case I40E_ERR_BAD_IWARP_CQE:
 297                 return "I40E_ERR_BAD_IWARP_CQE";
 298         case I40E_ERR_NVM_BLANK_MODE:
 299                 return "I40E_ERR_NVM_BLANK_MODE";
 300         case I40E_ERR_NOT_IMPLEMENTED:
 301                 return "I40E_ERR_NOT_IMPLEMENTED";
 302         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 303                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 304         case I40E_ERR_DIAG_TEST_FAILED:
 305                 return "I40E_ERR_DIAG_TEST_FAILED";
 306         case I40E_ERR_NOT_READY:
 307                 return "I40E_ERR_NOT_READY";
 308         case I40E_NOT_SUPPORTED:
 309                 return "I40E_NOT_SUPPORTED";
 310         case I40E_ERR_FIRMWARE_API_VERSION:
 311                 return "I40E_ERR_FIRMWARE_API_VERSION";
 312         }
 313
 314         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 315         return hw->err_str;
 316 }
 317
 318 /**
 319  * i40e_debug_aq
 320  * @hw: debug mask related to admin queue
 321  * @mask: debug mask
 322  * @desc: pointer to admin queue descriptor
 323  * @buffer: pointer to command buffer
 324  * @buf_len: max length of buffer
 325  *
 326  * Dumps debug log about adminq command with descriptor contents.
 327  **/
 328 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 329                    void *buffer, u16 buf_len)
 330 {
 331         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 332         u16 len = LE16_TO_CPU(aq_desc->datalen);
 333         u8 *buf = (u8 *)buffer;
 334         u16 i = 0;
 335
 336         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 337                 return;
 338
 339         i40e_debug(hw, mask,
 340                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 341                    LE16_TO_CPU(aq_desc->opcode),
 342                    LE16_TO_CPU(aq_desc->flags),
 343                    LE16_TO_CPU(aq_desc->datalen),
 344                    LE16_TO_CPU(aq_desc->retval));
 345         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 346                    LE32_TO_CPU(aq_desc->cookie_high),
 347                    LE32_TO_CPU(aq_desc->cookie_low));
 348         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 349                    LE32_TO_CPU(aq_desc->params.internal.param0),
 350                    LE32_TO_CPU(aq_desc->params.internal.param1));
 351         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 352                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 353                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 354
 355         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 356                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 357                 if (buf_len < len)
 358                         len = buf_len;
 359                 /* write the full 16-byte chunks */
 360                 for (i = 0; i < (len - 16); i += 16)
 361                         i40e_debug(hw, mask,
 362                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 363                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 364                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 365                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 366                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 367                 /* the most we could have left is 16 bytes, pad with zeros */
 368                 if (i < len) {
 369                         char d_buf[16];
 370                         int j, i_sav;
 371
 372                         i_sav = i;
 373                         memset(d_buf, 0, sizeof(d_buf));
 374                         for (j = 0; i < len; j++, i++)
 375                                 d_buf[j] = buf[i];
 376                         i40e_debug(hw, mask,
 377                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 378                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 379                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 380                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 381                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 382                 }
 383         }
 384 }
 385
 386 /**
 387  * i40e_check_asq_alive
 388  * @hw: pointer to the hw struct
 389  *
 390  * Returns true if Queue is enabled else false.
 391  **/
 392 bool i40e_check_asq_alive(struct i40e_hw *hw)
 393 {
 394         if (hw->aq.asq.len)
 395 #ifdef PF_DRIVER
 396 #ifdef INTEGRATED_VF
 397                 if (!i40e_is_vf(hw))
 398                         return !!(rd32(hw, hw->aq.asq.len) &
 399                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 400 #else
 401                 return !!(rd32(hw, hw->aq.asq.len) &
 402                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #endif /* INTEGRATED_VF */
 404 #endif /* PF_DRIVER */
 405 #ifdef VF_DRIVER
 406 #ifdef INTEGRATED_VF
 407                 if (i40e_is_vf(hw))
 408                         return !!(rd32(hw, hw->aq.asq.len) &
 409                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 410 #else
 411                 return !!(rd32(hw, hw->aq.asq.len) &
 412                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #endif /* INTEGRATED_VF */
 414 #endif /* VF_DRIVER */
 415         return false;
 416 }
 417
 418 /**
 419  * i40e_aq_queue_shutdown
 420  * @hw: pointer to the hw struct
 421  * @unloading: is the driver unloading itself
 422  *
 423  * Tell the Firmware that we're shutting down the AdminQ and whether
 424  * or not the driver is unloading as well.
 425  **/
 426 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 427                                              bool unloading)
 428 {
 429         struct i40e_aq_desc desc;
 430         struct i40e_aqc_queue_shutdown *cmd =
 431                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 432         enum i40e_status_code status;
 433
 434         i40e_fill_default_direct_cmd_desc(&desc,
 435                                           i40e_aqc_opc_queue_shutdown);
 436
 437         if (unloading)
 438                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 439         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 440
 441         return status;
 442 }
 443
 444 /**
 445  * i40e_aq_get_set_rss_lut
 446  * @hw: pointer to the hardware structure
 447  * @vsi_id: vsi fw index
 448  * @pf_lut: for PF table set true, for VSI table set false
 449  * @lut: pointer to the lut buffer provided by the caller
 450  * @lut_size: size of the lut buffer
 451  * @set: set true to set the table, false to get the table
 452  *
 453  * Internal function to get or set RSS look up table
 454  **/
 455 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 456                                                      u16 vsi_id, bool pf_lut,
 457                                                      u8 *lut, u16 lut_size,
 458                                                      bool set)
 459 {
 460         enum i40e_status_code status;
 461         struct i40e_aq_desc desc;
 462         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 463                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 464
 465         if (set)
 466                 i40e_fill_default_direct_cmd_desc(&desc,
 467                                                   i40e_aqc_opc_set_rss_lut);
 468         else
 469                 i40e_fill_default_direct_cmd_desc(&desc,
 470                                                   i40e_aqc_opc_get_rss_lut);
 471
 472         /* Indirect command */
 473         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 474         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 475
 476         cmd_resp->vsi_id =
 477                         CPU_TO_LE16((u16)((vsi_id <<
 478                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 479                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 480         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 481
 482         if (pf_lut)
 483                 cmd_resp->flags |= CPU_TO_LE16((u16)
 484                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 485                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 486                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 487         else
 488                 cmd_resp->flags |= CPU_TO_LE16((u16)
 489                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 490                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 491                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 492
 493         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 494
 495         return status;
 496 }
 497
 498 /**
 499  * i40e_aq_get_rss_lut
 500  * @hw: pointer to the hardware structure
 501  * @vsi_id: vsi fw index
 502  * @pf_lut: for PF table set true, for VSI table set false
 503  * @lut: pointer to the lut buffer provided by the caller
 504  * @lut_size: size of the lut buffer
 505  *
 506  * get the RSS lookup table, PF or VSI type
 507  **/
 508 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 509                                           bool pf_lut, u8 *lut, u16 lut_size)
 510 {
 511         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 512                                        false);
 513 }
 514
 515 /**
 516  * i40e_aq_set_rss_lut
 517  * @hw: pointer to the hardware structure
 518  * @vsi_id: vsi fw index
 519  * @pf_lut: for PF table set true, for VSI table set false
 520  * @lut: pointer to the lut buffer provided by the caller
 521  * @lut_size: size of the lut buffer
 522  *
 523  * set the RSS lookup table, PF or VSI type
 524  **/
 525 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 526                                           bool pf_lut, u8 *lut, u16 lut_size)
 527 {
 528         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 529 }
 530
 531 /**
 532  * i40e_aq_get_set_rss_key
 533  * @hw: pointer to the hw struct
 534  * @vsi_id: vsi fw index
 535  * @key: pointer to key info struct
 536  * @set: set true to set the key, false to get the key
 537  *
 538  * get the RSS key per VSI
 539  **/
 540 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 541                                       u16 vsi_id,
 542                                       struct i40e_aqc_get_set_rss_key_data *key,
 543                                       bool set)
 544 {
 545         enum i40e_status_code status;
 546         struct i40e_aq_desc desc;
 547         struct i40e_aqc_get_set_rss_key *cmd_resp =
 548                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 549         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 550
 551         if (set)
 552                 i40e_fill_default_direct_cmd_desc(&desc,
 553                                                   i40e_aqc_opc_set_rss_key);
 554         else
 555                 i40e_fill_default_direct_cmd_desc(&desc,
 556                                                   i40e_aqc_opc_get_rss_key);
 557
 558         /* Indirect command */
 559         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 560         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 561
 562         cmd_resp->vsi_id =
 563                         CPU_TO_LE16((u16)((vsi_id <<
 564                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 565                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 566         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 567
 568         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 569
 570         return status;
 571 }
 572
 573 /**
 574  * i40e_aq_get_rss_key
 575  * @hw: pointer to the hw struct
 576  * @vsi_id: vsi fw index
 577  * @key: pointer to key info struct
 578  *
 579  **/
 580 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 581                                       u16 vsi_id,
 582                                       struct i40e_aqc_get_set_rss_key_data *key)
 583 {
 584         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 585 }
 586
 587 /**
 588  * i40e_aq_set_rss_key
 589  * @hw: pointer to the hw struct
 590  * @vsi_id: vsi fw index
 591  * @key: pointer to key info struct
 592  *
 593  * set the RSS key per VSI
 594  **/
 595 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 596                                       u16 vsi_id,
 597                                       struct i40e_aqc_get_set_rss_key_data *key)
 598 {
 599         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 600 }
 601
 602 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 603  * hardware to a bit-field that can be used by SW to more easily determine the
 604  * packet type.
 605  *
 606  * Macros are used to shorten the table lines and make this table human
 607  * readable.
 608  *
 609  * We store the PTYPE in the top byte of the bit field - this is just so that
 610  * we can check that the table doesn't have a row missing, as the index into
 611  * the table should be the PTYPE.
 612  *
 613  * Typical work flow:
 614  *
 615  * IF NOT i40e_ptype_lookup[ptype].known
 616  * THEN
 617  *      Packet is unknown
 618  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 619  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 620  * ELSE
 621  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 622  * ENDIF
 623  */
 624
 625 /* macro to make the table lines short */
 626 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 627         {       PTYPE, \
 628                 1, \
 629                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 630                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 631                 I40E_RX_PTYPE_##OUTER_FRAG, \
 632                 I40E_RX_PTYPE_TUNNEL_##T, \
 633                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 634                 I40E_RX_PTYPE_##TEF, \
 635                 I40E_RX_PTYPE_INNER_PROT_##I, \
 636                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 637
 638 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 639                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 640
 641 /* shorter macros makes the table fit but are terse */
 642 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 643 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 644 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 645
 646 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 647 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 648         /* L2 Packet types */
 649         I40E_PTT_UNUSED_ENTRY(0),
 650         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 651         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 652         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 653         I40E_PTT_UNUSED_ENTRY(4),
 654         I40E_PTT_UNUSED_ENTRY(5),
 655         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 657         I40E_PTT_UNUSED_ENTRY(8),
 658         I40E_PTT_UNUSED_ENTRY(9),
 659         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 661         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 662         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 663         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 664         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 665         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 666         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671
 672         /* Non Tunneled IPv4 */
 673         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 676         I40E_PTT_UNUSED_ENTRY(25),
 677         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 678         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 679         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 680
 681         /* IPv4 --> IPv4 */
 682         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 683         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 684         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 685         I40E_PTT_UNUSED_ENTRY(32),
 686         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 687         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 688         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 689
 690         /* IPv4 --> IPv6 */
 691         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 692         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 693         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 694         I40E_PTT_UNUSED_ENTRY(39),
 695         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 696         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 697         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 698
 699         /* IPv4 --> GRE/NAT */
 700         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 701
 702         /* IPv4 --> GRE/NAT --> IPv4 */
 703         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 704         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 705         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 706         I40E_PTT_UNUSED_ENTRY(47),
 707         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 708         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 709         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 710
 711         /* IPv4 --> GRE/NAT --> IPv6 */
 712         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 713         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 714         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 715         I40E_PTT_UNUSED_ENTRY(54),
 716         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 717         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 718         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 719
 720         /* IPv4 --> GRE/NAT --> MAC */
 721         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 722
 723         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 724         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 725         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 726         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 727         I40E_PTT_UNUSED_ENTRY(62),
 728         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 729         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 730         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 731
 732         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 733         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 734         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 735         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 736         I40E_PTT_UNUSED_ENTRY(69),
 737         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 738         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 739         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 740
 741         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 742         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 743
 744         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 745         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 746         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 747         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 748         I40E_PTT_UNUSED_ENTRY(77),
 749         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 750         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 751         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 752
 753         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 754         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 755         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 756         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 757         I40E_PTT_UNUSED_ENTRY(84),
 758         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 759         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 760         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 761
 762         /* Non Tunneled IPv6 */
 763         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 764         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 765         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 766         I40E_PTT_UNUSED_ENTRY(91),
 767         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 768         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 769         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 770
 771         /* IPv6 --> IPv4 */
 772         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 773         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 774         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 775         I40E_PTT_UNUSED_ENTRY(98),
 776         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 777         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 778         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 779
 780         /* IPv6 --> IPv6 */
 781         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 782         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 783         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 784         I40E_PTT_UNUSED_ENTRY(105),
 785         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 786         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 787         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 788
 789         /* IPv6 --> GRE/NAT */
 790         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 791
 792         /* IPv6 --> GRE/NAT -> IPv4 */
 793         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 794         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 795         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 796         I40E_PTT_UNUSED_ENTRY(113),
 797         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 798         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 799         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 800
 801         /* IPv6 --> GRE/NAT -> IPv6 */
 802         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 803         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 804         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 805         I40E_PTT_UNUSED_ENTRY(120),
 806         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 807         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 808         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 809
 810         /* IPv6 --> GRE/NAT -> MAC */
 811         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 812
 813         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 814         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 815         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 816         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 817         I40E_PTT_UNUSED_ENTRY(128),
 818         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 819         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 820         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 821
 822         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 823         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 824         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 825         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 826         I40E_PTT_UNUSED_ENTRY(135),
 827         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 828         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 829         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 830
 831         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 832         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 833
 834         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 835         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 836         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 837         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 838         I40E_PTT_UNUSED_ENTRY(143),
 839         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 840         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 841         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 842
 843         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 844         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 845         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 846         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 847         I40E_PTT_UNUSED_ENTRY(150),
 848         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 849         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 850         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 851
 852         /* unused entries */
 853         I40E_PTT_UNUSED_ENTRY(154),
 854         I40E_PTT_UNUSED_ENTRY(155),
 855         I40E_PTT_UNUSED_ENTRY(156),
 856         I40E_PTT_UNUSED_ENTRY(157),
 857         I40E_PTT_UNUSED_ENTRY(158),
 858         I40E_PTT_UNUSED_ENTRY(159),
 859
 860         I40E_PTT_UNUSED_ENTRY(160),
 861         I40E_PTT_UNUSED_ENTRY(161),
 862         I40E_PTT_UNUSED_ENTRY(162),
 863         I40E_PTT_UNUSED_ENTRY(163),
 864         I40E_PTT_UNUSED_ENTRY(164),
 865         I40E_PTT_UNUSED_ENTRY(165),
 866         I40E_PTT_UNUSED_ENTRY(166),
 867         I40E_PTT_UNUSED_ENTRY(167),
 868         I40E_PTT_UNUSED_ENTRY(168),
 869         I40E_PTT_UNUSED_ENTRY(169),
 870
 871         I40E_PTT_UNUSED_ENTRY(170),
 872         I40E_PTT_UNUSED_ENTRY(171),
 873         I40E_PTT_UNUSED_ENTRY(172),
 874         I40E_PTT_UNUSED_ENTRY(173),
 875         I40E_PTT_UNUSED_ENTRY(174),
 876         I40E_PTT_UNUSED_ENTRY(175),
 877         I40E_PTT_UNUSED_ENTRY(176),
 878         I40E_PTT_UNUSED_ENTRY(177),
 879         I40E_PTT_UNUSED_ENTRY(178),
 880         I40E_PTT_UNUSED_ENTRY(179),
 881
 882         I40E_PTT_UNUSED_ENTRY(180),
 883         I40E_PTT_UNUSED_ENTRY(181),
 884         I40E_PTT_UNUSED_ENTRY(182),
 885         I40E_PTT_UNUSED_ENTRY(183),
 886         I40E_PTT_UNUSED_ENTRY(184),
 887         I40E_PTT_UNUSED_ENTRY(185),
 888         I40E_PTT_UNUSED_ENTRY(186),
 889         I40E_PTT_UNUSED_ENTRY(187),
 890         I40E_PTT_UNUSED_ENTRY(188),
 891         I40E_PTT_UNUSED_ENTRY(189),
 892
 893         I40E_PTT_UNUSED_ENTRY(190),
 894         I40E_PTT_UNUSED_ENTRY(191),
 895         I40E_PTT_UNUSED_ENTRY(192),
 896         I40E_PTT_UNUSED_ENTRY(193),
 897         I40E_PTT_UNUSED_ENTRY(194),
 898         I40E_PTT_UNUSED_ENTRY(195),
 899         I40E_PTT_UNUSED_ENTRY(196),
 900         I40E_PTT_UNUSED_ENTRY(197),
 901         I40E_PTT_UNUSED_ENTRY(198),
 902         I40E_PTT_UNUSED_ENTRY(199),
 903
 904         I40E_PTT_UNUSED_ENTRY(200),
 905         I40E_PTT_UNUSED_ENTRY(201),
 906         I40E_PTT_UNUSED_ENTRY(202),
 907         I40E_PTT_UNUSED_ENTRY(203),
 908         I40E_PTT_UNUSED_ENTRY(204),
 909         I40E_PTT_UNUSED_ENTRY(205),
 910         I40E_PTT_UNUSED_ENTRY(206),
 911         I40E_PTT_UNUSED_ENTRY(207),
 912         I40E_PTT_UNUSED_ENTRY(208),
 913         I40E_PTT_UNUSED_ENTRY(209),
 914
 915         I40E_PTT_UNUSED_ENTRY(210),
 916         I40E_PTT_UNUSED_ENTRY(211),
 917         I40E_PTT_UNUSED_ENTRY(212),
 918         I40E_PTT_UNUSED_ENTRY(213),
 919         I40E_PTT_UNUSED_ENTRY(214),
 920         I40E_PTT_UNUSED_ENTRY(215),
 921         I40E_PTT_UNUSED_ENTRY(216),
 922         I40E_PTT_UNUSED_ENTRY(217),
 923         I40E_PTT_UNUSED_ENTRY(218),
 924         I40E_PTT_UNUSED_ENTRY(219),
 925
 926         I40E_PTT_UNUSED_ENTRY(220),
 927         I40E_PTT_UNUSED_ENTRY(221),
 928         I40E_PTT_UNUSED_ENTRY(222),
 929         I40E_PTT_UNUSED_ENTRY(223),
 930         I40E_PTT_UNUSED_ENTRY(224),
 931         I40E_PTT_UNUSED_ENTRY(225),
 932         I40E_PTT_UNUSED_ENTRY(226),
 933         I40E_PTT_UNUSED_ENTRY(227),
 934         I40E_PTT_UNUSED_ENTRY(228),
 935         I40E_PTT_UNUSED_ENTRY(229),
 936
 937         I40E_PTT_UNUSED_ENTRY(230),
 938         I40E_PTT_UNUSED_ENTRY(231),
 939         I40E_PTT_UNUSED_ENTRY(232),
 940         I40E_PTT_UNUSED_ENTRY(233),
 941         I40E_PTT_UNUSED_ENTRY(234),
 942         I40E_PTT_UNUSED_ENTRY(235),
 943         I40E_PTT_UNUSED_ENTRY(236),
 944         I40E_PTT_UNUSED_ENTRY(237),
 945         I40E_PTT_UNUSED_ENTRY(238),
 946         I40E_PTT_UNUSED_ENTRY(239),
 947
 948         I40E_PTT_UNUSED_ENTRY(240),
 949         I40E_PTT_UNUSED_ENTRY(241),
 950         I40E_PTT_UNUSED_ENTRY(242),
 951         I40E_PTT_UNUSED_ENTRY(243),
 952         I40E_PTT_UNUSED_ENTRY(244),
 953         I40E_PTT_UNUSED_ENTRY(245),
 954         I40E_PTT_UNUSED_ENTRY(246),
 955         I40E_PTT_UNUSED_ENTRY(247),
 956         I40E_PTT_UNUSED_ENTRY(248),
 957         I40E_PTT_UNUSED_ENTRY(249),
 958
 959         I40E_PTT_UNUSED_ENTRY(250),
 960         I40E_PTT_UNUSED_ENTRY(251),
 961         I40E_PTT_UNUSED_ENTRY(252),
 962         I40E_PTT_UNUSED_ENTRY(253),
 963         I40E_PTT_UNUSED_ENTRY(254),
 964         I40E_PTT_UNUSED_ENTRY(255)
 965 };
 966
 967
 968 /**
 969  * i40e_validate_mac_addr - Validate unicast MAC address
 970  * @mac_addr: pointer to MAC address
 971  *
 972  * Tests a MAC address to ensure it is a valid Individual Address
 973  **/
 974 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 975 {
 976         enum i40e_status_code status = I40E_SUCCESS;
 977
 978         DEBUGFUNC("i40e_validate_mac_addr");
 979
 980         /* Broadcast addresses ARE multicast addresses
 981          * Make sure it is not a multicast address
 982          * Reject the zero address
 983          */
 984         if (I40E_IS_MULTICAST(mac_addr) ||
 985             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 986               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 987                 status = I40E_ERR_INVALID_MAC_ADDR;
 988
 989         return status;
 990 }
 991 #ifdef PF_DRIVER
 992
 993 /**
 994  * i40e_init_shared_code - Initialize the shared code
 995  * @hw: pointer to hardware structure
 996  *
 997  * This assigns the MAC type and PHY code and inits the NVM.
 998  * Does not touch the hardware. This function must be called prior to any
 999  * other function in the shared code. The i40e_hw structure should be
1000  * memset to 0 prior to calling this function.  The following fields in
1001  * hw structure should be filled in prior to calling this function:
1002  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1003  * subsystem_vendor_id, and revision_id
1004  **/
1005 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1006 {
1007         enum i40e_status_code status = I40E_SUCCESS;
1008         u32 port, ari, func_rid;
1009
1010         DEBUGFUNC("i40e_init_shared_code");
1011
1012         i40e_set_mac_type(hw);
1013
1014         switch (hw->mac.type) {
1015         case I40E_MAC_XL710:
1016         case I40E_MAC_X722:
1017                 break;
1018         default:
1019                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1020         }
1021
1022         hw->phy.get_link_info = true;
1023
1024         /* Determine port number and PF number*/
1025         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1026                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1027         hw->port = (u8)port;
1028         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1029                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1030         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1031         if (ari)
1032                 hw->pf_id = (u8)(func_rid & 0xff);
1033         else
1034                 hw->pf_id = (u8)(func_rid & 0x7);
1035
1036         if (hw->mac.type == I40E_MAC_X722)
1037                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1038
1039         status = i40e_init_nvm(hw);
1040         return status;
1041 }
1042
1043 /**
1044  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1045  * @hw: pointer to the hw struct
1046  * @flags: a return indicator of what addresses were added to the addr store
1047  * @addrs: the requestor's mac addr store
1048  * @cmd_details: pointer to command details structure or NULL
1049  **/
1050 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1051                                    u16 *flags,
1052                                    struct i40e_aqc_mac_address_read_data *addrs,
1053                                    struct i40e_asq_cmd_details *cmd_details)
1054 {
1055         struct i40e_aq_desc desc;
1056         struct i40e_aqc_mac_address_read *cmd_data =
1057                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1058         enum i40e_status_code status;
1059
1060         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1061         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1062
1063         status = i40e_asq_send_command(hw, &desc, addrs,
1064                                        sizeof(*addrs), cmd_details);
1065         *flags = LE16_TO_CPU(cmd_data->command_flags);
1066
1067         return status;
1068 }
1069
1070 /**
1071  * i40e_aq_mac_address_write - Change the MAC addresses
1072  * @hw: pointer to the hw struct
1073  * @flags: indicates which MAC to be written
1074  * @mac_addr: address to write
1075  * @cmd_details: pointer to command details structure or NULL
1076  **/
1077 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1078                                     u16 flags, u8 *mac_addr,
1079                                     struct i40e_asq_cmd_details *cmd_details)
1080 {
1081         struct i40e_aq_desc desc;
1082         struct i40e_aqc_mac_address_write *cmd_data =
1083                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1084         enum i40e_status_code status;
1085
1086         i40e_fill_default_direct_cmd_desc(&desc,
1087                                           i40e_aqc_opc_mac_address_write);
1088         cmd_data->command_flags = CPU_TO_LE16(flags);
1089         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1090         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1091                                         ((u32)mac_addr[3] << 16) |
1092                                         ((u32)mac_addr[4] << 8) |
1093                                         mac_addr[5]);
1094
1095         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1096
1097         return status;
1098 }
1099
1100 /**
1101  * i40e_get_mac_addr - get MAC address
1102  * @hw: pointer to the HW structure
1103  * @mac_addr: pointer to MAC address
1104  *
1105  * Reads the adapter's MAC address from register
1106  **/
1107 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1108 {
1109         struct i40e_aqc_mac_address_read_data addrs;
1110         enum i40e_status_code status;
1111         u16 flags = 0;
1112
1113         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1114
1115         if (flags & I40E_AQC_LAN_ADDR_VALID)
1116                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1117                         I40E_NONDMA_TO_NONDMA);
1118
1119         return status;
1120 }
1121
1122 /**
1123  * i40e_get_port_mac_addr - get Port MAC address
1124  * @hw: pointer to the HW structure
1125  * @mac_addr: pointer to Port MAC address
1126  *
1127  * Reads the adapter's Port MAC address
1128  **/
1129 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1130 {
1131         struct i40e_aqc_mac_address_read_data addrs;
1132         enum i40e_status_code status;
1133         u16 flags = 0;
1134
1135         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1136         if (status)
1137                 return status;
1138
1139         if (flags & I40E_AQC_PORT_ADDR_VALID)
1140                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1141                         I40E_NONDMA_TO_NONDMA);
1142         else
1143                 status = I40E_ERR_INVALID_MAC_ADDR;
1144
1145         return status;
1146 }
1147
1148 /**
1149  * i40e_pre_tx_queue_cfg - pre tx queue configure
1150  * @hw: pointer to the HW structure
1151  * @queue: target pf queue index
1152  * @enable: state change request
1153  *
1154  * Handles hw requirement to indicate intention to enable
1155  * or disable target queue.
1156  **/
1157 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1158 {
1159         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1160         u32 reg_block = 0;
1161         u32 reg_val;
1162
1163         if (abs_queue_idx >= 128) {
1164                 reg_block = abs_queue_idx / 128;
1165                 abs_queue_idx %= 128;
1166         }
1167
1168         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1169         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1170         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1171
1172         if (enable)
1173                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1174         else
1175                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1176
1177         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1178 }
1179
1180 /**
1181  * i40e_get_san_mac_addr - get SAN MAC address
1182  * @hw: pointer to the HW structure
1183  * @mac_addr: pointer to SAN MAC address
1184  *
1185  * Reads the adapter's SAN MAC address from NVM
1186  **/
1187 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1188                                             u8 *mac_addr)
1189 {
1190         struct i40e_aqc_mac_address_read_data addrs;
1191         enum i40e_status_code status;
1192         u16 flags = 0;
1193
1194         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1195         if (status)
1196                 return status;
1197
1198         if (flags & I40E_AQC_SAN_ADDR_VALID)
1199                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1200                         I40E_NONDMA_TO_NONDMA);
1201         else
1202                 status = I40E_ERR_INVALID_MAC_ADDR;
1203
1204         return status;
1205 }
1206
1207 /**
1208  *  i40e_read_pba_string - Reads part number string from EEPROM
1209  *  @hw: pointer to hardware structure
1210  *  @pba_num: stores the part number string from the EEPROM
1211  *  @pba_num_size: part number string buffer length
1212  *
1213  *  Reads the part number string from the EEPROM.
1214  **/
1215 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1216                                             u32 pba_num_size)
1217 {
1218         enum i40e_status_code status = I40E_SUCCESS;
1219         u16 pba_word = 0;
1220         u16 pba_size = 0;
1221         u16 pba_ptr = 0;
1222         u16 i = 0;
1223
1224         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1225         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1226                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1227                 return status;
1228         }
1229
1230         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1231         if (status != I40E_SUCCESS) {
1232                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1233                 return status;
1234         }
1235
1236         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1237         if (status != I40E_SUCCESS) {
1238                 DEBUGOUT("Failed to read PBA Block size.\n");
1239                 return status;
1240         }
1241
1242         /* Subtract one to get PBA word count (PBA Size word is included in
1243          * total size)
1244          */
1245         pba_size--;
1246         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1247                 DEBUGOUT("Buffer to small for PBA data.\n");
1248                 return I40E_ERR_PARAM;
1249         }
1250
1251         for (i = 0; i < pba_size; i++) {
1252                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1253                 if (status != I40E_SUCCESS) {
1254                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1255                         return status;
1256                 }
1257
1258                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1259                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1260         }
1261         pba_num[(pba_size * 2)] = '\0';
1262
1263         return status;
1264 }
1265
1266 /**
1267  * i40e_get_media_type - Gets media type
1268  * @hw: pointer to the hardware structure
1269  **/
1270 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1271 {
1272         enum i40e_media_type media;
1273
1274         switch (hw->phy.link_info.phy_type) {
1275         case I40E_PHY_TYPE_10GBASE_SR:
1276         case I40E_PHY_TYPE_10GBASE_LR:
1277         case I40E_PHY_TYPE_1000BASE_SX:
1278         case I40E_PHY_TYPE_1000BASE_LX:
1279         case I40E_PHY_TYPE_40GBASE_SR4:
1280         case I40E_PHY_TYPE_40GBASE_LR4:
1281         case I40E_PHY_TYPE_25GBASE_LR:
1282         case I40E_PHY_TYPE_25GBASE_SR:
1283                 media = I40E_MEDIA_TYPE_FIBER;
1284                 break;
1285         case I40E_PHY_TYPE_100BASE_TX:
1286         case I40E_PHY_TYPE_1000BASE_T:
1287         case I40E_PHY_TYPE_10GBASE_T:
1288                 media = I40E_MEDIA_TYPE_BASET;
1289                 break;
1290         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1291         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1292         case I40E_PHY_TYPE_10GBASE_CR1:
1293         case I40E_PHY_TYPE_40GBASE_CR4:
1294         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1295         case I40E_PHY_TYPE_40GBASE_AOC:
1296         case I40E_PHY_TYPE_10GBASE_AOC:
1297         case I40E_PHY_TYPE_25GBASE_CR:
1298                 media = I40E_MEDIA_TYPE_DA;
1299                 break;
1300         case I40E_PHY_TYPE_1000BASE_KX:
1301         case I40E_PHY_TYPE_10GBASE_KX4:
1302         case I40E_PHY_TYPE_10GBASE_KR:
1303         case I40E_PHY_TYPE_40GBASE_KR4:
1304         case I40E_PHY_TYPE_20GBASE_KR2:
1305         case I40E_PHY_TYPE_25GBASE_KR:
1306                 media = I40E_MEDIA_TYPE_BACKPLANE;
1307                 break;
1308         case I40E_PHY_TYPE_SGMII:
1309         case I40E_PHY_TYPE_XAUI:
1310         case I40E_PHY_TYPE_XFI:
1311         case I40E_PHY_TYPE_XLAUI:
1312         case I40E_PHY_TYPE_XLPPI:
1313         default:
1314                 media = I40E_MEDIA_TYPE_UNKNOWN;
1315                 break;
1316         }
1317
1318         return media;
1319 }
1320
1321 #define I40E_PF_RESET_WAIT_COUNT        200
1322 /**
1323  * i40e_pf_reset - Reset the PF
1324  * @hw: pointer to the hardware structure
1325  *
1326  * Assuming someone else has triggered a global reset,
1327  * assure the global reset is complete and then reset the PF
1328  **/
1329 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1330 {
1331         u32 cnt = 0;
1332         u32 cnt1 = 0;
1333         u32 reg = 0;
1334         u32 grst_del;
1335
1336         /* Poll for Global Reset steady state in case of recent GRST.
1337          * The grst delay value is in 100ms units, and we'll wait a
1338          * couple counts longer to be sure we don't just miss the end.
1339          */
1340         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1341                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1342                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1343
1344         grst_del = grst_del * 20;
1345
1346         for (cnt = 0; cnt < grst_del; cnt++) {
1347                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1348                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1349                         break;
1350                 i40e_msec_delay(100);
1351         }
1352         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1353                 DEBUGOUT("Global reset polling failed to complete.\n");
1354                 return I40E_ERR_RESET_FAILED;
1355         }
1356
1357         /* Now Wait for the FW to be ready */
1358         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1359                 reg = rd32(hw, I40E_GLNVM_ULD);
1360                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1361                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1362                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1363                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1364                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1365                         break;
1366                 }
1367                 i40e_msec_delay(10);
1368         }
1369         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1370                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1371                 DEBUGOUT("wait for FW Reset complete timedout\n");
1372                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1373                 return I40E_ERR_RESET_FAILED;
1374         }
1375
1376         /* If there was a Global Reset in progress when we got here,
1377          * we don't need to do the PF Reset
1378          */
1379         if (!cnt) {
1380                 reg = rd32(hw, I40E_PFGEN_CTRL);
1381                 wr32(hw, I40E_PFGEN_CTRL,
1382                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1383                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1384                         reg = rd32(hw, I40E_PFGEN_CTRL);
1385                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1386                                 break;
1387                         i40e_msec_delay(1);
1388                 }
1389                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1390                         DEBUGOUT("PF reset polling failed to complete.\n");
1391                         return I40E_ERR_RESET_FAILED;
1392                 }
1393         }
1394
1395         i40e_clear_pxe_mode(hw);
1396
1397
1398         return I40E_SUCCESS;
1399 }
1400
1401 /**
1402  * i40e_clear_hw - clear out any left over hw state
1403  * @hw: pointer to the hw struct
1404  *
1405  * Clear queues and interrupts, typically called at init time,
1406  * but after the capabilities have been found so we know how many
1407  * queues and msix vectors have been allocated.
1408  **/
1409 void i40e_clear_hw(struct i40e_hw *hw)
1410 {
1411         u32 num_queues, base_queue;
1412         u32 num_pf_int;
1413         u32 num_vf_int;
1414         u32 num_vfs;
1415         u32 i, j;
1416         u32 val;
1417         u32 eol = 0x7ff;
1418
1419         /* get number of interrupts, queues, and vfs */
1420         val = rd32(hw, I40E_GLPCI_CNF2);
1421         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1422                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1423         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1424                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1425
1426         val = rd32(hw, I40E_PFLAN_QALLOC);
1427         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1428                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1429         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1430                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1431         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1432                 num_queues = (j - base_queue) + 1;
1433         else
1434                 num_queues = 0;
1435
1436         val = rd32(hw, I40E_PF_VT_PFALLOC);
1437         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1438                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1439         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1440                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1441         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1442                 num_vfs = (j - i) + 1;
1443         else
1444                 num_vfs = 0;
1445
1446         /* stop all the interrupts */
1447         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1448         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1449         for (i = 0; i < num_pf_int - 2; i++)
1450                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1451
1452         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1453         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1454         wr32(hw, I40E_PFINT_LNKLST0, val);
1455         for (i = 0; i < num_pf_int - 2; i++)
1456                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1457         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1458         for (i = 0; i < num_vfs; i++)
1459                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1460         for (i = 0; i < num_vf_int - 2; i++)
1461                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1462
1463         /* warn the HW of the coming Tx disables */
1464         for (i = 0; i < num_queues; i++) {
1465                 u32 abs_queue_idx = base_queue + i;
1466                 u32 reg_block = 0;
1467
1468                 if (abs_queue_idx >= 128) {
1469                         reg_block = abs_queue_idx / 128;
1470                         abs_queue_idx %= 128;
1471                 }
1472
1473                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1474                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1475                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1476                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1477
1478                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1479         }
1480         i40e_usec_delay(400);
1481
1482         /* stop all the queues */
1483         for (i = 0; i < num_queues; i++) {
1484                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1485                 wr32(hw, I40E_QTX_ENA(i), 0);
1486                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1487                 wr32(hw, I40E_QRX_ENA(i), 0);
1488         }
1489
1490         /* short wait for all queue disables to settle */
1491         i40e_usec_delay(50);
1492 }
1493
1494 /**
1495  * i40e_clear_pxe_mode - clear pxe operations mode
1496  * @hw: pointer to the hw struct
1497  *
1498  * Make sure all PXE mode settings are cleared, including things
1499  * like descriptor fetch/write-back mode.
1500  **/
1501 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1502 {
1503         if (i40e_check_asq_alive(hw))
1504                 i40e_aq_clear_pxe_mode(hw, NULL);
1505 }
1506
1507 /**
1508  * i40e_led_is_mine - helper to find matching led
1509  * @hw: pointer to the hw struct
1510  * @idx: index into GPIO registers
1511  *
1512  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1513  */
1514 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1515 {
1516         u32 gpio_val = 0;
1517         u32 port;
1518
1519         if (!hw->func_caps.led[idx])
1520                 return 0;
1521
1522         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1523         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1524                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1525
1526         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1527          * if it is not our port then ignore
1528          */
1529         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1530             (port != hw->port))
1531                 return 0;
1532
1533         return gpio_val;
1534 }
1535
1536 #define I40E_COMBINED_ACTIVITY 0xA
1537 #define I40E_FILTER_ACTIVITY 0xE
1538 #define I40E_LINK_ACTIVITY 0xC
1539 #define I40E_MAC_ACTIVITY 0xD
1540 #define I40E_LED0 22
1541
1542 /**
1543  * i40e_led_get - return current on/off mode
1544  * @hw: pointer to the hw struct
1545  *
1546  * The value returned is the 'mode' field as defined in the
1547  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1548  * values are variations of possible behaviors relating to
1549  * blink, link, and wire.
1550  **/
1551 u32 i40e_led_get(struct i40e_hw *hw)
1552 {
1553         u32 current_mode = 0;
1554         u32 mode = 0;
1555         int i;
1556
1557         /* as per the documentation GPIO 22-29 are the LED
1558          * GPIO pins named LED0..LED7
1559          */
1560         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1561                 u32 gpio_val = i40e_led_is_mine(hw, i);
1562
1563                 if (!gpio_val)
1564                         continue;
1565
1566                 /* ignore gpio LED src mode entries related to the activity
1567                  *  LEDs
1568                  */
1569                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1570                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1571                 switch (current_mode) {
1572                 case I40E_COMBINED_ACTIVITY:
1573                 case I40E_FILTER_ACTIVITY:
1574                 case I40E_MAC_ACTIVITY:
1575                         continue;
1576                 default:
1577                         break;
1578                 }
1579
1580                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1581                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1582                 break;
1583         }
1584
1585         return mode;
1586 }
1587
1588 /**
1589  * i40e_led_set - set new on/off mode
1590  * @hw: pointer to the hw struct
1591  * @mode: 0=off, 0xf=on (else see manual for mode details)
1592  * @blink: true if the LED should blink when on, false if steady
1593  *
1594  * if this function is used to turn on the blink it should
1595  * be used to disable the blink when restoring the original state.
1596  **/
1597 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1598 {
1599         u32 current_mode = 0;
1600         int i;
1601
1602         if (mode & 0xfffffff0)
1603                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1604
1605         /* as per the documentation GPIO 22-29 are the LED
1606          * GPIO pins named LED0..LED7
1607          */
1608         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1609                 u32 gpio_val = i40e_led_is_mine(hw, i);
1610
1611                 if (!gpio_val)
1612                         continue;
1613
1614                 /* ignore gpio LED src mode entries related to the activity
1615                  * LEDs
1616                  */
1617                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1618                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1619                 switch (current_mode) {
1620                 case I40E_COMBINED_ACTIVITY:
1621                 case I40E_FILTER_ACTIVITY:
1622                 case I40E_MAC_ACTIVITY:
1623                         continue;
1624                 default:
1625                         break;
1626                 }
1627
1628                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1629                 /* this & is a bit of paranoia, but serves as a range check */
1630                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1631                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1632
1633                 if (mode == I40E_LINK_ACTIVITY)
1634                         blink = false;
1635
1636                 if (blink)
1637                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1638                 else
1639                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1640
1641                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1642                 break;
1643         }
1644 }
1645
1646 /* Admin command wrappers */
1647
1648 /**
1649  * i40e_aq_get_phy_capabilities
1650  * @hw: pointer to the hw struct
1651  * @abilities: structure for PHY capabilities to be filled
1652  * @qualified_modules: report Qualified Modules
1653  * @report_init: report init capabilities (active are default)
1654  * @cmd_details: pointer to command details structure or NULL
1655  *
1656  * Returns the various PHY abilities supported on the Port.
1657  **/
1658 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1659                         bool qualified_modules, bool report_init,
1660                         struct i40e_aq_get_phy_abilities_resp *abilities,
1661                         struct i40e_asq_cmd_details *cmd_details)
1662 {
1663         struct i40e_aq_desc desc;
1664         enum i40e_status_code status;
1665         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1666
1667         if (!abilities)
1668                 return I40E_ERR_PARAM;
1669
1670         i40e_fill_default_direct_cmd_desc(&desc,
1671                                           i40e_aqc_opc_get_phy_abilities);
1672
1673         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1674         if (abilities_size > I40E_AQ_LARGE_BUF)
1675                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1676
1677         if (qualified_modules)
1678                 desc.params.external.param0 |=
1679                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1680
1681         if (report_init)
1682                 desc.params.external.param0 |=
1683                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1684
1685         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1686                                     cmd_details);
1687
1688         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1689                 status = I40E_ERR_UNKNOWN_PHY;
1690
1691         if (report_init) {
1692                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1693                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1694         }
1695
1696         return status;
1697 }
1698
1699 /**
1700  * i40e_aq_set_phy_config
1701  * @hw: pointer to the hw struct
1702  * @config: structure with PHY configuration to be set
1703  * @cmd_details: pointer to command details structure or NULL
1704  *
1705  * Set the various PHY configuration parameters
1706  * supported on the Port.One or more of the Set PHY config parameters may be
1707  * ignored in an MFP mode as the PF may not have the privilege to set some
1708  * of the PHY Config parameters. This status will be indicated by the
1709  * command response.
1710  **/
1711 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1712                                 struct i40e_aq_set_phy_config *config,
1713                                 struct i40e_asq_cmd_details *cmd_details)
1714 {
1715         struct i40e_aq_desc desc;
1716         struct i40e_aq_set_phy_config *cmd =
1717                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1718         enum i40e_status_code status;
1719
1720         if (!config)
1721                 return I40E_ERR_PARAM;
1722
1723         i40e_fill_default_direct_cmd_desc(&desc,
1724                                           i40e_aqc_opc_set_phy_config);
1725
1726         *cmd = *config;
1727
1728         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1729
1730         return status;
1731 }
1732
1733 /**
1734  * i40e_set_fc
1735  * @hw: pointer to the hw struct
1736  *
1737  * Set the requested flow control mode using set_phy_config.
1738  **/
1739 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1740                                   bool atomic_restart)
1741 {
1742         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1743         struct i40e_aq_get_phy_abilities_resp abilities;
1744         struct i40e_aq_set_phy_config config;
1745         enum i40e_status_code status;
1746         u8 pause_mask = 0x0;
1747
1748         *aq_failures = 0x0;
1749
1750         switch (fc_mode) {
1751         case I40E_FC_FULL:
1752                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1753                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1754                 break;
1755         case I40E_FC_RX_PAUSE:
1756                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1757                 break;
1758         case I40E_FC_TX_PAUSE:
1759                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1760                 break;
1761         default:
1762                 break;
1763         }
1764
1765         /* Get the current phy config */
1766         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1767                                               NULL);
1768         if (status) {
1769                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1770                 return status;
1771         }
1772
1773         memset(&config, 0, sizeof(config));
1774         /* clear the old pause settings */
1775         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1776                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1777         /* set the new abilities */
1778         config.abilities |= pause_mask;
1779         /* If the abilities have changed, then set the new config */
1780         if (config.abilities != abilities.abilities) {
1781                 /* Auto restart link so settings take effect */
1782                 if (atomic_restart)
1783                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1784                 /* Copy over all the old settings */
1785                 config.phy_type = abilities.phy_type;
1786                 config.phy_type_ext = abilities.phy_type_ext;
1787                 config.link_speed = abilities.link_speed;
1788                 config.eee_capability = abilities.eee_capability;
1789                 config.eeer = abilities.eeer_val;
1790                 config.low_power_ctrl = abilities.d3_lpan;
1791                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1792                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1793                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1794
1795                 if (status)
1796                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1797         }
1798         /* Update the link info */
1799         status = i40e_update_link_info(hw);
1800         if (status) {
1801                 /* Wait a little bit (on 40G cards it sometimes takes a really
1802                  * long time for link to come back from the atomic reset)
1803                  * and try once more
1804                  */
1805                 i40e_msec_delay(1000);
1806                 status = i40e_update_link_info(hw);
1807         }
1808         if (status)
1809                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1810
1811         return status;
1812 }
1813
1814 /**
1815  * i40e_aq_set_mac_config
1816  * @hw: pointer to the hw struct
1817  * @max_frame_size: Maximum Frame Size to be supported by the port
1818  * @crc_en: Tell HW to append a CRC to outgoing frames
1819  * @pacing: Pacing configurations
1820  * @cmd_details: pointer to command details structure or NULL
1821  *
1822  * Configure MAC settings for frame size, jumbo frame support and the
1823  * addition of a CRC by the hardware.
1824  **/
1825 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1826                                 u16 max_frame_size,
1827                                 bool crc_en, u16 pacing,
1828                                 struct i40e_asq_cmd_details *cmd_details)
1829 {
1830         struct i40e_aq_desc desc;
1831         struct i40e_aq_set_mac_config *cmd =
1832                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1833         enum i40e_status_code status;
1834
1835         if (max_frame_size == 0)
1836                 return I40E_ERR_PARAM;
1837
1838         i40e_fill_default_direct_cmd_desc(&desc,
1839                                           i40e_aqc_opc_set_mac_config);
1840
1841         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1842         cmd->params = ((u8)pacing & 0x0F) << 3;
1843         if (crc_en)
1844                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1845
1846         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1847
1848         return status;
1849 }
1850
1851 /**
1852  * i40e_aq_clear_pxe_mode
1853  * @hw: pointer to the hw struct
1854  * @cmd_details: pointer to command details structure or NULL
1855  *
1856  * Tell the firmware that the driver is taking over from PXE
1857  **/
1858 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1859                         struct i40e_asq_cmd_details *cmd_details)
1860 {
1861         enum i40e_status_code status;
1862         struct i40e_aq_desc desc;
1863         struct i40e_aqc_clear_pxe *cmd =
1864                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1865
1866         i40e_fill_default_direct_cmd_desc(&desc,
1867                                           i40e_aqc_opc_clear_pxe_mode);
1868
1869         cmd->rx_cnt = 0x2;
1870
1871         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1872
1873         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1874
1875         return status;
1876 }
1877
1878 /**
1879  * i40e_aq_set_link_restart_an
1880  * @hw: pointer to the hw struct
1881  * @enable_link: if true: enable link, if false: disable link
1882  * @cmd_details: pointer to command details structure or NULL
1883  *
1884  * Sets up the link and restarts the Auto-Negotiation over the link.
1885  **/
1886 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1887                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1888 {
1889         struct i40e_aq_desc desc;
1890         struct i40e_aqc_set_link_restart_an *cmd =
1891                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1892         enum i40e_status_code status;
1893
1894         i40e_fill_default_direct_cmd_desc(&desc,
1895                                           i40e_aqc_opc_set_link_restart_an);
1896
1897         cmd->command = I40E_AQ_PHY_RESTART_AN;
1898         if (enable_link)
1899                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1900         else
1901                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1902
1903         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1904
1905         return status;
1906 }
1907
1908 /**
1909  * i40e_aq_get_link_info
1910  * @hw: pointer to the hw struct
1911  * @enable_lse: enable/disable LinkStatusEvent reporting
1912  * @link: pointer to link status structure - optional
1913  * @cmd_details: pointer to command details structure or NULL
1914  *
1915  * Returns the link status of the adapter.
1916  **/
1917 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1918                                 bool enable_lse, struct i40e_link_status *link,
1919                                 struct i40e_asq_cmd_details *cmd_details)
1920 {
1921         struct i40e_aq_desc desc;
1922         struct i40e_aqc_get_link_status *resp =
1923                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1924         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1925         enum i40e_status_code status;
1926         bool tx_pause, rx_pause;
1927         u16 command_flags;
1928
1929         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1930
1931         if (enable_lse)
1932                 command_flags = I40E_AQ_LSE_ENABLE;
1933         else
1934                 command_flags = I40E_AQ_LSE_DISABLE;
1935         resp->command_flags = CPU_TO_LE16(command_flags);
1936
1937         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1938
1939         if (status != I40E_SUCCESS)
1940                 goto aq_get_link_info_exit;
1941
1942         /* save off old link status information */
1943         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1944                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1945
1946         /* update link status */
1947         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1948         hw->phy.media_type = i40e_get_media_type(hw);
1949         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1950         hw_link_info->link_info = resp->link_info;
1951         hw_link_info->an_info = resp->an_info;
1952         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1953                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1954         hw_link_info->ext_info = resp->ext_info;
1955         hw_link_info->loopback = resp->loopback;
1956         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1957         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1958
1959         /* update fc info */
1960         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1961         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1962         if (tx_pause & rx_pause)
1963                 hw->fc.current_mode = I40E_FC_FULL;
1964         else if (tx_pause)
1965                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1966         else if (rx_pause)
1967                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1968         else
1969                 hw->fc.current_mode = I40E_FC_NONE;
1970
1971         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1972                 hw_link_info->crc_enable = true;
1973         else
1974                 hw_link_info->crc_enable = false;
1975
1976         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1977                 hw_link_info->lse_enable = true;
1978         else
1979                 hw_link_info->lse_enable = false;
1980
1981         if ((hw->mac.type == I40E_MAC_XL710) &&
1982             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1983              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1984                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1985
1986         /* save link status information */
1987         if (link)
1988                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1989                             I40E_NONDMA_TO_NONDMA);
1990
1991         /* flag cleared so helper functions don't call AQ again */
1992         hw->phy.get_link_info = false;
1993
1994 aq_get_link_info_exit:
1995         return status;
1996 }
1997
1998 /**
1999  * i40e_aq_set_phy_int_mask
2000  * @hw: pointer to the hw struct
2001  * @mask: interrupt mask to be set
2002  * @cmd_details: pointer to command details structure or NULL
2003  *
2004  * Set link interrupt mask.
2005  **/
2006 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2007                                 u16 mask,
2008                                 struct i40e_asq_cmd_details *cmd_details)
2009 {
2010         struct i40e_aq_desc desc;
2011         struct i40e_aqc_set_phy_int_mask *cmd =
2012                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2013         enum i40e_status_code status;
2014
2015         i40e_fill_default_direct_cmd_desc(&desc,
2016                                           i40e_aqc_opc_set_phy_int_mask);
2017
2018         cmd->event_mask = CPU_TO_LE16(mask);
2019
2020         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2021
2022         return status;
2023 }
2024
2025 /**
2026  * i40e_aq_get_local_advt_reg
2027  * @hw: pointer to the hw struct
2028  * @advt_reg: local AN advertisement register value
2029  * @cmd_details: pointer to command details structure or NULL
2030  *
2031  * Get the Local AN advertisement register value.
2032  **/
2033 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2034                                 u64 *advt_reg,
2035                                 struct i40e_asq_cmd_details *cmd_details)
2036 {
2037         struct i40e_aq_desc desc;
2038         struct i40e_aqc_an_advt_reg *resp =
2039                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2040         enum i40e_status_code status;
2041
2042         i40e_fill_default_direct_cmd_desc(&desc,
2043                                           i40e_aqc_opc_get_local_advt_reg);
2044
2045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046
2047         if (status != I40E_SUCCESS)
2048                 goto aq_get_local_advt_reg_exit;
2049
2050         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2051         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2052
2053 aq_get_local_advt_reg_exit:
2054         return status;
2055 }
2056
2057 /**
2058  * i40e_aq_set_local_advt_reg
2059  * @hw: pointer to the hw struct
2060  * @advt_reg: local AN advertisement register value
2061  * @cmd_details: pointer to command details structure or NULL
2062  *
2063  * Get the Local AN advertisement register value.
2064  **/
2065 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2066                                 u64 advt_reg,
2067                                 struct i40e_asq_cmd_details *cmd_details)
2068 {
2069         struct i40e_aq_desc desc;
2070         struct i40e_aqc_an_advt_reg *cmd =
2071                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2072         enum i40e_status_code status;
2073
2074         i40e_fill_default_direct_cmd_desc(&desc,
2075                                           i40e_aqc_opc_get_local_advt_reg);
2076
2077         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2078         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2079
2080         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2081
2082         return status;
2083 }
2084
2085 /**
2086  * i40e_aq_get_partner_advt
2087  * @hw: pointer to the hw struct
2088  * @advt_reg: AN partner advertisement register value
2089  * @cmd_details: pointer to command details structure or NULL
2090  *
2091  * Get the link partner AN advertisement register value.
2092  **/
2093 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2094                                 u64 *advt_reg,
2095                                 struct i40e_asq_cmd_details *cmd_details)
2096 {
2097         struct i40e_aq_desc desc;
2098         struct i40e_aqc_an_advt_reg *resp =
2099                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2100         enum i40e_status_code status;
2101
2102         i40e_fill_default_direct_cmd_desc(&desc,
2103                                           i40e_aqc_opc_get_partner_advt);
2104
2105         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2106
2107         if (status != I40E_SUCCESS)
2108                 goto aq_get_partner_advt_exit;
2109
2110         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2111         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2112
2113 aq_get_partner_advt_exit:
2114         return status;
2115 }
2116
2117 /**
2118  * i40e_aq_set_lb_modes
2119  * @hw: pointer to the hw struct
2120  * @lb_modes: loopback mode to be set
2121  * @cmd_details: pointer to command details structure or NULL
2122  *
2123  * Sets loopback modes.
2124  **/
2125 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2126                                 u16 lb_modes,
2127                                 struct i40e_asq_cmd_details *cmd_details)
2128 {
2129         struct i40e_aq_desc desc;
2130         struct i40e_aqc_set_lb_mode *cmd =
2131                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2132         enum i40e_status_code status;
2133
2134         i40e_fill_default_direct_cmd_desc(&desc,
2135                                           i40e_aqc_opc_set_lb_modes);
2136
2137         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2138
2139         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2140
2141         return status;
2142 }
2143
2144 /**
2145  * i40e_aq_set_phy_debug
2146  * @hw: pointer to the hw struct
2147  * @cmd_flags: debug command flags
2148  * @cmd_details: pointer to command details structure or NULL
2149  *
2150  * Reset the external PHY.
2151  **/
2152 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2153                                 struct i40e_asq_cmd_details *cmd_details)
2154 {
2155         struct i40e_aq_desc desc;
2156         struct i40e_aqc_set_phy_debug *cmd =
2157                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2158         enum i40e_status_code status;
2159
2160         i40e_fill_default_direct_cmd_desc(&desc,
2161                                           i40e_aqc_opc_set_phy_debug);
2162
2163         cmd->command_flags = cmd_flags;
2164
2165         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2166
2167         return status;
2168 }
2169
2170 /**
2171  * i40e_aq_add_vsi
2172  * @hw: pointer to the hw struct
2173  * @vsi_ctx: pointer to a vsi context struct
2174  * @cmd_details: pointer to command details structure or NULL
2175  *
2176  * Add a VSI context to the hardware.
2177 **/
2178 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2179                                 struct i40e_vsi_context *vsi_ctx,
2180                                 struct i40e_asq_cmd_details *cmd_details)
2181 {
2182         struct i40e_aq_desc desc;
2183         struct i40e_aqc_add_get_update_vsi *cmd =
2184                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2185         struct i40e_aqc_add_get_update_vsi_completion *resp =
2186                 (struct i40e_aqc_add_get_update_vsi_completion *)
2187                 &desc.params.raw;
2188         enum i40e_status_code status;
2189
2190         i40e_fill_default_direct_cmd_desc(&desc,
2191                                           i40e_aqc_opc_add_vsi);
2192
2193         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2194         cmd->connection_type = vsi_ctx->connection_type;
2195         cmd->vf_id = vsi_ctx->vf_num;
2196         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2197
2198         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2199
2200         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2201                                     sizeof(vsi_ctx->info), cmd_details);
2202
2203         if (status != I40E_SUCCESS)
2204                 goto aq_add_vsi_exit;
2205
2206         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2207         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2208         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2209         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2210
2211 aq_add_vsi_exit:
2212         return status;
2213 }
2214
2215 /**
2216  * i40e_aq_set_default_vsi
2217  * @hw: pointer to the hw struct
2218  * @seid: vsi number
2219  * @cmd_details: pointer to command details structure or NULL
2220  **/
2221 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2222                                 u16 seid,
2223                                 struct i40e_asq_cmd_details *cmd_details)
2224 {
2225         struct i40e_aq_desc desc;
2226         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2227                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2228                 &desc.params.raw;
2229         enum i40e_status_code status;
2230
2231         i40e_fill_default_direct_cmd_desc(&desc,
2232                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2233
2234         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2235         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2236         cmd->seid = CPU_TO_LE16(seid);
2237
2238         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2239
2240         return status;
2241 }
2242
2243 /**
2244  * i40e_aq_clear_default_vsi
2245  * @hw: pointer to the hw struct
2246  * @seid: vsi number
2247  * @cmd_details: pointer to command details structure or NULL
2248  **/
2249 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2250                                 u16 seid,
2251                                 struct i40e_asq_cmd_details *cmd_details)
2252 {
2253         struct i40e_aq_desc desc;
2254         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2255                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2256                 &desc.params.raw;
2257         enum i40e_status_code status;
2258
2259         i40e_fill_default_direct_cmd_desc(&desc,
2260                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2261
2262         cmd->promiscuous_flags = CPU_TO_LE16(0);
2263         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2264         cmd->seid = CPU_TO_LE16(seid);
2265
2266         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2267
2268         return status;
2269 }
2270
2271 /**
2272  * i40e_aq_set_vsi_unicast_promiscuous
2273  * @hw: pointer to the hw struct
2274  * @seid: vsi number
2275  * @set: set unicast promiscuous enable/disable
2276  * @cmd_details: pointer to command details structure or NULL
2277  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2278  **/
2279 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2280                                 u16 seid, bool set,
2281                                 struct i40e_asq_cmd_details *cmd_details,
2282                                 bool rx_only_promisc)
2283 {
2284         struct i40e_aq_desc desc;
2285         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2286                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2287         enum i40e_status_code status;
2288         u16 flags = 0;
2289
2290         i40e_fill_default_direct_cmd_desc(&desc,
2291                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2292
2293         if (set) {
2294                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2295                 if (rx_only_promisc &&
2296                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2297                      (hw->aq.api_maj_ver > 1)))
2298                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2299         }
2300
2301         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2302
2303         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2304         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2305              (hw->aq.api_maj_ver > 1))
2306                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2307
2308         cmd->seid = CPU_TO_LE16(seid);
2309         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2310
2311         return status;
2312 }
2313
2314 /**
2315  * i40e_aq_set_vsi_multicast_promiscuous
2316  * @hw: pointer to the hw struct
2317  * @seid: vsi number
2318  * @set: set multicast promiscuous enable/disable
2319  * @cmd_details: pointer to command details structure or NULL
2320  **/
2321 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2322                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2323 {
2324         struct i40e_aq_desc desc;
2325         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2326                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2327         enum i40e_status_code status;
2328         u16 flags = 0;
2329
2330         i40e_fill_default_direct_cmd_desc(&desc,
2331                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2332
2333         if (set)
2334                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2335
2336         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2337
2338         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2339
2340         cmd->seid = CPU_TO_LE16(seid);
2341         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2342
2343         return status;
2344 }
2345
2346 /**
2347 * i40e_aq_set_vsi_full_promiscuous
2348 * @hw: pointer to the hw struct
2349 * @seid: VSI number
2350 * @set: set promiscuous enable/disable
2351 * @cmd_details: pointer to command details structure or NULL
2352 **/
2353 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2354                                 u16 seid, bool set,
2355                                 struct i40e_asq_cmd_details *cmd_details)
2356 {
2357         struct i40e_aq_desc desc;
2358         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2359                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2360         enum i40e_status_code status;
2361         u16 flags = 0;
2362
2363         i40e_fill_default_direct_cmd_desc(&desc,
2364                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2365
2366         if (set)
2367                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2368                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2369                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2370
2371         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2372
2373         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2374                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2375                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2376
2377         cmd->seid = CPU_TO_LE16(seid);
2378         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2379
2380         return status;
2381 }
2382
2383 /**
2384  * i40e_aq_set_vsi_mc_promisc_on_vlan
2385  * @hw: pointer to the hw struct
2386  * @seid: vsi number
2387  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2388  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2389  * @cmd_details: pointer to command details structure or NULL
2390  **/
2391 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2392                                 u16 seid, bool enable, u16 vid,
2393                                 struct i40e_asq_cmd_details *cmd_details)
2394 {
2395         struct i40e_aq_desc desc;
2396         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2397                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2398         enum i40e_status_code status;
2399         u16 flags = 0;
2400
2401         i40e_fill_default_direct_cmd_desc(&desc,
2402                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2403
2404         if (enable)
2405                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2406
2407         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2408         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2409         cmd->seid = CPU_TO_LE16(seid);
2410         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2411
2412         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2413
2414         return status;
2415 }
2416
2417 /**
2418  * i40e_aq_set_vsi_uc_promisc_on_vlan
2419  * @hw: pointer to the hw struct
2420  * @seid: vsi number
2421  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2422  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2423  * @cmd_details: pointer to command details structure or NULL
2424  **/
2425 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2426                                 u16 seid, bool enable, u16 vid,
2427                                 struct i40e_asq_cmd_details *cmd_details)
2428 {
2429         struct i40e_aq_desc desc;
2430         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2431                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2432         enum i40e_status_code status;
2433         u16 flags = 0;
2434
2435         i40e_fill_default_direct_cmd_desc(&desc,
2436                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2437
2438         if (enable)
2439                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2440
2441         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2442         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2443         cmd->seid = CPU_TO_LE16(seid);
2444         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2445
2446         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2447
2448         return status;
2449 }
2450
2451 /**
2452  * i40e_aq_set_vsi_bc_promisc_on_vlan
2453  * @hw: pointer to the hw struct
2454  * @seid: vsi number
2455  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2456  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2457  * @cmd_details: pointer to command details structure or NULL
2458  **/
2459 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2460                                 u16 seid, bool enable, u16 vid,
2461                                 struct i40e_asq_cmd_details *cmd_details)
2462 {
2463         struct i40e_aq_desc desc;
2464         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2465                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2466         enum i40e_status_code status;
2467         u16 flags = 0;
2468
2469         i40e_fill_default_direct_cmd_desc(&desc,
2470                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2471
2472         if (enable)
2473                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2474
2475         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2476         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2477         cmd->seid = CPU_TO_LE16(seid);
2478         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2479
2480         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2481
2482         return status;
2483 }
2484
2485 /**
2486  * i40e_aq_set_vsi_broadcast
2487  * @hw: pointer to the hw struct
2488  * @seid: vsi number
2489  * @set_filter: true to set filter, false to clear filter
2490  * @cmd_details: pointer to command details structure or NULL
2491  *
2492  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2493  **/
2494 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2495                                 u16 seid, bool set_filter,
2496                                 struct i40e_asq_cmd_details *cmd_details)
2497 {
2498         struct i40e_aq_desc desc;
2499         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2500                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2501         enum i40e_status_code status;
2502
2503         i40e_fill_default_direct_cmd_desc(&desc,
2504                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2505
2506         if (set_filter)
2507                 cmd->promiscuous_flags
2508                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2509         else
2510                 cmd->promiscuous_flags
2511                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2512
2513         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2514         cmd->seid = CPU_TO_LE16(seid);
2515         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2516
2517         return status;
2518 }
2519
2520 /**
2521  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2522  * @hw: pointer to the hw struct
2523  * @seid: vsi number
2524  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2525  * @cmd_details: pointer to command details structure or NULL
2526  **/
2527 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2528                                 u16 seid, bool enable,
2529                                 struct i40e_asq_cmd_details *cmd_details)
2530 {
2531         struct i40e_aq_desc desc;
2532         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2533                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2534         enum i40e_status_code status;
2535         u16 flags = 0;
2536
2537         i40e_fill_default_direct_cmd_desc(&desc,
2538                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2539         if (enable)
2540                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2541
2542         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2543         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2544         cmd->seid = CPU_TO_LE16(seid);
2545
2546         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2547
2548         return status;
2549 }
2550
2551 /**
2552  * i40e_get_vsi_params - get VSI configuration info
2553  * @hw: pointer to the hw struct
2554  * @vsi_ctx: pointer to a vsi context struct
2555  * @cmd_details: pointer to command details structure or NULL
2556  **/
2557 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2558                                 struct i40e_vsi_context *vsi_ctx,
2559                                 struct i40e_asq_cmd_details *cmd_details)
2560 {
2561         struct i40e_aq_desc desc;
2562         struct i40e_aqc_add_get_update_vsi *cmd =
2563                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2564         struct i40e_aqc_add_get_update_vsi_completion *resp =
2565                 (struct i40e_aqc_add_get_update_vsi_completion *)
2566                 &desc.params.raw;
2567         enum i40e_status_code status;
2568
2569         UNREFERENCED_1PARAMETER(cmd_details);
2570         i40e_fill_default_direct_cmd_desc(&desc,
2571                                           i40e_aqc_opc_get_vsi_parameters);
2572
2573         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2574
2575         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2576
2577         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2578                                     sizeof(vsi_ctx->info), NULL);
2579
2580         if (status != I40E_SUCCESS)
2581                 goto aq_get_vsi_params_exit;
2582
2583         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2584         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2585         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2586         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2587
2588 aq_get_vsi_params_exit:
2589         return status;
2590 }
2591
2592 /**
2593  * i40e_aq_update_vsi_params
2594  * @hw: pointer to the hw struct
2595  * @vsi_ctx: pointer to a vsi context struct
2596  * @cmd_details: pointer to command details structure or NULL
2597  *
2598  * Update a VSI context.
2599  **/
2600 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2601                                 struct i40e_vsi_context *vsi_ctx,
2602                                 struct i40e_asq_cmd_details *cmd_details)
2603 {
2604         struct i40e_aq_desc desc;
2605         struct i40e_aqc_add_get_update_vsi *cmd =
2606                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2607         struct i40e_aqc_add_get_update_vsi_completion *resp =
2608                 (struct i40e_aqc_add_get_update_vsi_completion *)
2609                 &desc.params.raw;
2610         enum i40e_status_code status;
2611
2612         i40e_fill_default_direct_cmd_desc(&desc,
2613                                           i40e_aqc_opc_update_vsi_parameters);
2614         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2615
2616         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2617
2618         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2619                                     sizeof(vsi_ctx->info), cmd_details);
2620
2621         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2622         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2623
2624         return status;
2625 }
2626
2627 /**
2628  * i40e_aq_get_switch_config
2629  * @hw: pointer to the hardware structure
2630  * @buf: pointer to the result buffer
2631  * @buf_size: length of input buffer
2632  * @start_seid: seid to start for the report, 0 == beginning
2633  * @cmd_details: pointer to command details structure or NULL
2634  *
2635  * Fill the buf with switch configuration returned from AdminQ command
2636  **/
2637 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2638                                 struct i40e_aqc_get_switch_config_resp *buf,
2639                                 u16 buf_size, u16 *start_seid,
2640                                 struct i40e_asq_cmd_details *cmd_details)
2641 {
2642         struct i40e_aq_desc desc;
2643         struct i40e_aqc_switch_seid *scfg =
2644                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2645         enum i40e_status_code status;
2646
2647         i40e_fill_default_direct_cmd_desc(&desc,
2648                                           i40e_aqc_opc_get_switch_config);
2649         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2650         if (buf_size > I40E_AQ_LARGE_BUF)
2651                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2652         scfg->seid = CPU_TO_LE16(*start_seid);
2653
2654         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2655         *start_seid = LE16_TO_CPU(scfg->seid);
2656
2657         return status;
2658 }
2659
2660 /**
2661  * i40e_aq_set_switch_config
2662  * @hw: pointer to the hardware structure
2663  * @flags: bit flag values to set
2664  * @valid_flags: which bit flags to set
2665  * @cmd_details: pointer to command details structure or NULL
2666  *
2667  * Set switch configuration bits
2668  **/
2669 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2670                                 u16 flags, u16 valid_flags,
2671                                 struct i40e_asq_cmd_details *cmd_details)
2672 {
2673         struct i40e_aq_desc desc;
2674         struct i40e_aqc_set_switch_config *scfg =
2675                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2676         enum i40e_status_code status;
2677
2678         i40e_fill_default_direct_cmd_desc(&desc,
2679                                           i40e_aqc_opc_set_switch_config);
2680         scfg->flags = CPU_TO_LE16(flags);
2681         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2682
2683         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2684
2685         return status;
2686 }
2687
2688 /**
2689  * i40e_aq_get_firmware_version
2690  * @hw: pointer to the hw struct
2691  * @fw_major_version: firmware major version
2692  * @fw_minor_version: firmware minor version
2693  * @fw_build: firmware build number
2694  * @api_major_version: major queue version
2695  * @api_minor_version: minor queue version
2696  * @cmd_details: pointer to command details structure or NULL
2697  *
2698  * Get the firmware version from the admin queue commands
2699  **/
2700 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2701                                 u16 *fw_major_version, u16 *fw_minor_version,
2702                                 u32 *fw_build,
2703                                 u16 *api_major_version, u16 *api_minor_version,
2704                                 struct i40e_asq_cmd_details *cmd_details)
2705 {
2706         struct i40e_aq_desc desc;
2707         struct i40e_aqc_get_version *resp =
2708                 (struct i40e_aqc_get_version *)&desc.params.raw;
2709         enum i40e_status_code status;
2710
2711         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2712
2713         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2714
2715         if (status == I40E_SUCCESS) {
2716                 if (fw_major_version != NULL)
2717                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2718                 if (fw_minor_version != NULL)
2719                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2720                 if (fw_build != NULL)
2721                         *fw_build = LE32_TO_CPU(resp->fw_build);
2722                 if (api_major_version != NULL)
2723                         *api_major_version = LE16_TO_CPU(resp->api_major);
2724                 if (api_minor_version != NULL)
2725                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2726
2727                 /* A workaround to fix the API version in SW */
2728                 if (api_major_version && api_minor_version &&
2729                     fw_major_version && fw_minor_version &&
2730                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2731                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2732                      (*fw_major_version > 4)))
2733                         *api_minor_version = 2;
2734         }
2735
2736         return status;
2737 }
2738
2739 /**
2740  * i40e_aq_send_driver_version
2741  * @hw: pointer to the hw struct
2742  * @dv: driver's major, minor version
2743  * @cmd_details: pointer to command details structure or NULL
2744  *
2745  * Send the driver version to the firmware
2746  **/
2747 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2748                                 struct i40e_driver_version *dv,
2749                                 struct i40e_asq_cmd_details *cmd_details)
2750 {
2751         struct i40e_aq_desc desc;
2752         struct i40e_aqc_driver_version *cmd =
2753                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2754         enum i40e_status_code status;
2755         u16 len;
2756
2757         if (dv == NULL)
2758                 return I40E_ERR_PARAM;
2759
2760         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2761
2762         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2763         cmd->driver_major_ver = dv->major_version;
2764         cmd->driver_minor_ver = dv->minor_version;
2765         cmd->driver_build_ver = dv->build_version;
2766         cmd->driver_subbuild_ver = dv->subbuild_version;
2767
2768         len = 0;
2769         while (len < sizeof(dv->driver_string) &&
2770                (dv->driver_string[len] < 0x80) &&
2771                dv->driver_string[len])
2772                 len++;
2773         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2774                                        len, cmd_details);
2775
2776         return status;
2777 }
2778
2779 /**
2780  * i40e_get_link_status - get status of the HW network link
2781  * @hw: pointer to the hw struct
2782  * @link_up: pointer to bool (true/false = linkup/linkdown)
2783  *
2784  * Variable link_up true if link is up, false if link is down.
2785  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2786  *
2787  * Side effect: LinkStatusEvent reporting becomes enabled
2788  **/
2789 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2790 {
2791         enum i40e_status_code status = I40E_SUCCESS;
2792
2793         if (hw->phy.get_link_info) {
2794                 status = i40e_update_link_info(hw);
2795
2796                 if (status != I40E_SUCCESS)
2797                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2798                                    status);
2799         }
2800
2801         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2802
2803         return status;
2804 }
2805
2806 /**
2807  * i40e_updatelink_status - update status of the HW network link
2808  * @hw: pointer to the hw struct
2809  **/
2810 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2811 {
2812         struct i40e_aq_get_phy_abilities_resp abilities;
2813         enum i40e_status_code status = I40E_SUCCESS;
2814
2815         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2816         if (status)
2817                 return status;
2818
2819         /* extra checking needed to ensure link info to user is timely */
2820         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2821             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2822              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2823                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2824                                                       &abilities, NULL);
2825                 if (status)
2826                         return status;
2827
2828                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2829                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2830         }
2831         return status;
2832 }
2833
2834
2835 /**
2836  * i40e_get_link_speed
2837  * @hw: pointer to the hw struct
2838  *
2839  * Returns the link speed of the adapter.
2840  **/
2841 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2842 {
2843         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2844         enum i40e_status_code status = I40E_SUCCESS;
2845
2846         if (hw->phy.get_link_info) {
2847                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2848
2849                 if (status != I40E_SUCCESS)
2850                         goto i40e_link_speed_exit;
2851         }
2852
2853         speed = hw->phy.link_info.link_speed;
2854
2855 i40e_link_speed_exit:
2856         return speed;
2857 }
2858
2859 /**
2860  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2861  * @hw: pointer to the hw struct
2862  * @uplink_seid: the MAC or other gizmo SEID
2863  * @downlink_seid: the VSI SEID
2864  * @enabled_tc: bitmap of TCs to be enabled
2865  * @default_port: true for default port VSI, false for control port
2866  * @veb_seid: pointer to where to put the resulting VEB SEID
2867  * @enable_stats: true to turn on VEB stats
2868  * @cmd_details: pointer to command details structure or NULL
2869  *
2870  * This asks the FW to add a VEB between the uplink and downlink
2871  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2872  **/
2873 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2874                                 u16 downlink_seid, u8 enabled_tc,
2875                                 bool default_port, u16 *veb_seid,
2876                                 bool enable_stats,
2877                                 struct i40e_asq_cmd_details *cmd_details)
2878 {
2879         struct i40e_aq_desc desc;
2880         struct i40e_aqc_add_veb *cmd =
2881                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2882         struct i40e_aqc_add_veb_completion *resp =
2883                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2884         enum i40e_status_code status;
2885         u16 veb_flags = 0;
2886
2887         /* SEIDs need to either both be set or both be 0 for floating VEB */
2888         if (!!uplink_seid != !!downlink_seid)
2889                 return I40E_ERR_PARAM;
2890
2891         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2892
2893         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2894         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2895         cmd->enable_tcs = enabled_tc;
2896         if (!uplink_seid)
2897                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2898         if (default_port)
2899                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2900         else
2901                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2902
2903         /* reverse logic here: set the bitflag to disable the stats */
2904         if (!enable_stats)
2905                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2906
2907         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2908
2909         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2910
2911         if (!status && veb_seid)
2912                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2913
2914         return status;
2915 }
2916
2917 /**
2918  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2919  * @hw: pointer to the hw struct
2920  * @veb_seid: the SEID of the VEB to query
2921  * @switch_id: the uplink switch id
2922  * @floating: set to true if the VEB is floating
2923  * @statistic_index: index of the stats counter block for this VEB
2924  * @vebs_used: number of VEB's used by function
2925  * @vebs_free: total VEB's not reserved by any function
2926  * @cmd_details: pointer to command details structure or NULL
2927  *
2928  * This retrieves the parameters for a particular VEB, specified by
2929  * uplink_seid, and returns them to the caller.
2930  **/
2931 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2932                                 u16 veb_seid, u16 *switch_id,
2933                                 bool *floating, u16 *statistic_index,
2934                                 u16 *vebs_used, u16 *vebs_free,
2935                                 struct i40e_asq_cmd_details *cmd_details)
2936 {
2937         struct i40e_aq_desc desc;
2938         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2939                 (struct i40e_aqc_get_veb_parameters_completion *)
2940                 &desc.params.raw;
2941         enum i40e_status_code status;
2942
2943         if (veb_seid == 0)
2944                 return I40E_ERR_PARAM;
2945
2946         i40e_fill_default_direct_cmd_desc(&desc,
2947                                           i40e_aqc_opc_get_veb_parameters);
2948         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2949
2950         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2951         if (status)
2952                 goto get_veb_exit;
2953
2954         if (switch_id)
2955                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2956         if (statistic_index)
2957                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2958         if (vebs_used)
2959                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2960         if (vebs_free)
2961                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2962         if (floating) {
2963                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2964
2965                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2966                         *floating = true;
2967                 else
2968                         *floating = false;
2969         }
2970
2971 get_veb_exit:
2972         return status;
2973 }
2974
2975 /**
2976  * i40e_aq_add_macvlan
2977  * @hw: pointer to the hw struct
2978  * @seid: VSI for the mac address
2979  * @mv_list: list of macvlans to be added
2980  * @count: length of the list
2981  * @cmd_details: pointer to command details structure or NULL
2982  *
2983  * Add MAC/VLAN addresses to the HW filtering
2984  **/
2985 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2986                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2987                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2988 {
2989         struct i40e_aq_desc desc;
2990         struct i40e_aqc_macvlan *cmd =
2991                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2992         enum i40e_status_code status;
2993         u16 buf_size;
2994         int i;
2995
2996         if (count == 0 || !mv_list || !hw)
2997                 return I40E_ERR_PARAM;
2998
2999         buf_size = count * sizeof(*mv_list);
3000
3001         /* prep the rest of the request */
3002         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3003         cmd->num_addresses = CPU_TO_LE16(count);
3004         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3005         cmd->seid[1] = 0;
3006         cmd->seid[2] = 0;
3007
3008         for (i = 0; i < count; i++)
3009                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3010                         mv_list[i].flags |=
3011                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3012
3013         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3014         if (buf_size > I40E_AQ_LARGE_BUF)
3015                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3016
3017         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3018                                        cmd_details);
3019
3020         return status;
3021 }
3022
3023 /**
3024  * i40e_aq_remove_macvlan
3025  * @hw: pointer to the hw struct
3026  * @seid: VSI for the mac address
3027  * @mv_list: list of macvlans to be removed
3028  * @count: length of the list
3029  * @cmd_details: pointer to command details structure or NULL
3030  *
3031  * Remove MAC/VLAN addresses from the HW filtering
3032  **/
3033 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3034                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3035                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3036 {
3037         struct i40e_aq_desc desc;
3038         struct i40e_aqc_macvlan *cmd =
3039                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3040         enum i40e_status_code status;
3041         u16 buf_size;
3042
3043         if (count == 0 || !mv_list || !hw)
3044                 return I40E_ERR_PARAM;
3045
3046         buf_size = count * sizeof(*mv_list);
3047
3048         /* prep the rest of the request */
3049         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3050         cmd->num_addresses = CPU_TO_LE16(count);
3051         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3052         cmd->seid[1] = 0;
3053         cmd->seid[2] = 0;
3054
3055         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3056         if (buf_size > I40E_AQ_LARGE_BUF)
3057                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3058
3059         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3060                                        cmd_details);
3061
3062         return status;
3063 }
3064
3065 /**
3066  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3067  * @hw: pointer to the hw struct
3068  * @opcode: AQ opcode for add or delete mirror rule
3069  * @sw_seid: Switch SEID (to which rule refers)
3070  * @rule_type: Rule Type (ingress/egress/VLAN)
3071  * @id: Destination VSI SEID or Rule ID
3072  * @count: length of the list
3073  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3074  * @cmd_details: pointer to command details structure or NULL
3075  * @rule_id: Rule ID returned from FW
3076  * @rule_used: Number of rules used in internal switch
3077  * @rule_free: Number of rules free in internal switch
3078  *
3079  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3080  * VEBs/VEPA elements only
3081  **/
3082 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3083                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3084                         u16 count, __le16 *mr_list,
3085                         struct i40e_asq_cmd_details *cmd_details,
3086                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3087 {
3088         struct i40e_aq_desc desc;
3089         struct i40e_aqc_add_delete_mirror_rule *cmd =
3090                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3091         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3092         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3093         enum i40e_status_code status;
3094         u16 buf_size;
3095
3096         buf_size = count * sizeof(*mr_list);
3097
3098         /* prep the rest of the request */
3099         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3100         cmd->seid = CPU_TO_LE16(sw_seid);
3101         cmd->rule_type = CPU_TO_LE16(rule_type &
3102                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3103         cmd->num_entries = CPU_TO_LE16(count);
3104         /* Dest VSI for add, rule_id for delete */
3105         cmd->destination = CPU_TO_LE16(id);
3106         if (mr_list) {
3107                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3108                                                 I40E_AQ_FLAG_RD));
3109                 if (buf_size > I40E_AQ_LARGE_BUF)
3110                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3111         }
3112
3113         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3114                                        cmd_details);
3115         if (status == I40E_SUCCESS ||
3116             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3117                 if (rule_id)
3118                         *rule_id = LE16_TO_CPU(resp->rule_id);
3119                 if (rules_used)
3120                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3121                 if (rules_free)
3122                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3123         }
3124         return status;
3125 }
3126
3127 /**
3128  * i40e_aq_add_mirrorrule - add a mirror rule
3129  * @hw: pointer to the hw struct
3130  * @sw_seid: Switch SEID (to which rule refers)
3131  * @rule_type: Rule Type (ingress/egress/VLAN)
3132  * @dest_vsi: SEID of VSI to which packets will be mirrored
3133  * @count: length of the list
3134  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3135  * @cmd_details: pointer to command details structure or NULL
3136  * @rule_id: Rule ID returned from FW
3137  * @rule_used: Number of rules used in internal switch
3138  * @rule_free: Number of rules free in internal switch
3139  *
3140  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3141  **/
3142 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3143                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3144                         struct i40e_asq_cmd_details *cmd_details,
3145                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3146 {
3147         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3148             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3149                 if (count == 0 || !mr_list)
3150                         return I40E_ERR_PARAM;
3151         }
3152
3153         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3154                                   rule_type, dest_vsi, count, mr_list,
3155                                   cmd_details, rule_id, rules_used, rules_free);
3156 }
3157
3158 /**
3159  * i40e_aq_delete_mirrorrule - delete a mirror rule
3160  * @hw: pointer to the hw struct
3161  * @sw_seid: Switch SEID (to which rule refers)
3162  * @rule_type: Rule Type (ingress/egress/VLAN)
3163  * @count: length of the list
3164  * @rule_id: Rule ID that is returned in the receive desc as part of
3165  *              add_mirrorrule.
3166  * @mr_list: list of mirrored VLAN IDs to be removed
3167  * @cmd_details: pointer to command details structure or NULL
3168  * @rule_used: Number of rules used in internal switch
3169  * @rule_free: Number of rules free in internal switch
3170  *
3171  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3172  **/
3173 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3174                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3175                         struct i40e_asq_cmd_details *cmd_details,
3176                         u16 *rules_used, u16 *rules_free)
3177 {
3178         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3179         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3180                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3181                  * mirroring. For other rule_type, count and rule_type should
3182                  * not matter.
3183                  */
3184                 if (count == 0 || !mr_list)
3185                         return I40E_ERR_PARAM;
3186         }
3187
3188         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3189                                   rule_type, rule_id, count, mr_list,
3190                                   cmd_details, NULL, rules_used, rules_free);
3191 }
3192
3193 /**
3194  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3195  * @hw: pointer to the hw struct
3196  * @seid: VSI for the vlan filters
3197  * @v_list: list of vlan filters to be added
3198  * @count: length of the list
3199  * @cmd_details: pointer to command details structure or NULL
3200  **/
3201 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3202                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3203                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3204 {
3205         struct i40e_aq_desc desc;
3206         struct i40e_aqc_macvlan *cmd =
3207                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3208         enum i40e_status_code status;
3209         u16 buf_size;
3210
3211         if (count == 0 || !v_list || !hw)
3212                 return I40E_ERR_PARAM;
3213
3214         buf_size = count * sizeof(*v_list);
3215
3216         /* prep the rest of the request */
3217         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3218         cmd->num_addresses = CPU_TO_LE16(count);
3219         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3220         cmd->seid[1] = 0;
3221         cmd->seid[2] = 0;
3222
3223         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3224         if (buf_size > I40E_AQ_LARGE_BUF)
3225                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3226
3227         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3228                                        cmd_details);
3229
3230         return status;
3231 }
3232
3233 /**
3234  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3235  * @hw: pointer to the hw struct
3236  * @seid: VSI for the vlan filters
3237  * @v_list: list of macvlans to be removed
3238  * @count: length of the list
3239  * @cmd_details: pointer to command details structure or NULL
3240  **/
3241 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3242                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3243                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3244 {
3245         struct i40e_aq_desc desc;
3246         struct i40e_aqc_macvlan *cmd =
3247                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3248         enum i40e_status_code status;
3249         u16 buf_size;
3250
3251         if (count == 0 || !v_list || !hw)
3252                 return I40E_ERR_PARAM;
3253
3254         buf_size = count * sizeof(*v_list);
3255
3256         /* prep the rest of the request */
3257         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3258         cmd->num_addresses = CPU_TO_LE16(count);
3259         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3260         cmd->seid[1] = 0;
3261         cmd->seid[2] = 0;
3262
3263         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3264         if (buf_size > I40E_AQ_LARGE_BUF)
3265                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3266
3267         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3268                                        cmd_details);
3269
3270         return status;
3271 }
3272
3273 /**
3274  * i40e_aq_send_msg_to_vf
3275  * @hw: pointer to the hardware structure
3276  * @vfid: vf id to send msg
3277  * @v_opcode: opcodes for VF-PF communication
3278  * @v_retval: return error code
3279  * @msg: pointer to the msg buffer
3280  * @msglen: msg length
3281  * @cmd_details: pointer to command details
3282  *
3283  * send msg to vf
3284  **/
3285 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3286                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3287                                 struct i40e_asq_cmd_details *cmd_details)
3288 {
3289         struct i40e_aq_desc desc;
3290         struct i40e_aqc_pf_vf_message *cmd =
3291                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3292         enum i40e_status_code status;
3293
3294         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3295         cmd->id = CPU_TO_LE32(vfid);
3296         desc.cookie_high = CPU_TO_LE32(v_opcode);
3297         desc.cookie_low = CPU_TO_LE32(v_retval);
3298         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3299         if (msglen) {
3300                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3301                                                 I40E_AQ_FLAG_RD));
3302                 if (msglen > I40E_AQ_LARGE_BUF)
3303                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3304                 desc.datalen = CPU_TO_LE16(msglen);
3305         }
3306         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3307
3308         return status;
3309 }
3310
3311 /**
3312  * i40e_aq_debug_read_register
3313  * @hw: pointer to the hw struct
3314  * @reg_addr: register address
3315  * @reg_val: register value
3316  * @cmd_details: pointer to command details structure or NULL
3317  *
3318  * Read the register using the admin queue commands
3319  **/
3320 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3321                                 u32 reg_addr, u64 *reg_val,
3322                                 struct i40e_asq_cmd_details *cmd_details)
3323 {
3324         struct i40e_aq_desc desc;
3325         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3326                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3327         enum i40e_status_code status;
3328
3329         if (reg_val == NULL)
3330                 return I40E_ERR_PARAM;
3331
3332         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3333
3334         cmd_resp->address = CPU_TO_LE32(reg_addr);
3335
3336         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3337
3338         if (status == I40E_SUCCESS) {
3339                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3340                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3341         }
3342
3343         return status;
3344 }
3345
3346 /**
3347  * i40e_aq_debug_write_register
3348  * @hw: pointer to the hw struct
3349  * @reg_addr: register address
3350  * @reg_val: register value
3351  * @cmd_details: pointer to command details structure or NULL
3352  *
3353  * Write to a register using the admin queue commands
3354  **/
3355 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3356                                 u32 reg_addr, u64 reg_val,
3357                                 struct i40e_asq_cmd_details *cmd_details)
3358 {
3359         struct i40e_aq_desc desc;
3360         struct i40e_aqc_debug_reg_read_write *cmd =
3361                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3362         enum i40e_status_code status;
3363
3364         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3365
3366         cmd->address = CPU_TO_LE32(reg_addr);
3367         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3368         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3369
3370         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3371
3372         return status;
3373 }
3374
3375 /**
3376  * i40e_aq_request_resource
3377  * @hw: pointer to the hw struct
3378  * @resource: resource id
3379  * @access: access type
3380  * @sdp_number: resource number
3381  * @timeout: the maximum time in ms that the driver may hold the resource
3382  * @cmd_details: pointer to command details structure or NULL
3383  *
3384  * requests common resource using the admin queue commands
3385  **/
3386 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3387                                 enum i40e_aq_resources_ids resource,
3388                                 enum i40e_aq_resource_access_type access,
3389                                 u8 sdp_number, u64 *timeout,
3390                                 struct i40e_asq_cmd_details *cmd_details)
3391 {
3392         struct i40e_aq_desc desc;
3393         struct i40e_aqc_request_resource *cmd_resp =
3394                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3395         enum i40e_status_code status;
3396
3397         DEBUGFUNC("i40e_aq_request_resource");
3398
3399         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3400
3401         cmd_resp->resource_id = CPU_TO_LE16(resource);
3402         cmd_resp->access_type = CPU_TO_LE16(access);
3403         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3404
3405         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3406         /* The completion specifies the maximum time in ms that the driver
3407          * may hold the resource in the Timeout field.
3408          * If the resource is held by someone else, the command completes with
3409          * busy return value and the timeout field indicates the maximum time
3410          * the current owner of the resource has to free it.
3411          */
3412         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3413                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3414
3415         return status;
3416 }
3417
3418 /**
3419  * i40e_aq_release_resource
3420  * @hw: pointer to the hw struct
3421  * @resource: resource id
3422  * @sdp_number: resource number
3423  * @cmd_details: pointer to command details structure or NULL
3424  *
3425  * release common resource using the admin queue commands
3426  **/
3427 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3428                                 enum i40e_aq_resources_ids resource,
3429                                 u8 sdp_number,
3430                                 struct i40e_asq_cmd_details *cmd_details)
3431 {
3432         struct i40e_aq_desc desc;
3433         struct i40e_aqc_request_resource *cmd =
3434                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3435         enum i40e_status_code status;
3436
3437         DEBUGFUNC("i40e_aq_release_resource");
3438
3439         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3440
3441         cmd->resource_id = CPU_TO_LE16(resource);
3442         cmd->resource_number = CPU_TO_LE32(sdp_number);
3443
3444         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3445
3446         return status;
3447 }
3448
3449 /**
3450  * i40e_aq_read_nvm
3451  * @hw: pointer to the hw struct
3452  * @module_pointer: module pointer location in words from the NVM beginning
3453  * @offset: byte offset from the module beginning
3454  * @length: length of the section to be read (in bytes from the offset)
3455  * @data: command buffer (size [bytes] = length)
3456  * @last_command: tells if this is the last command in a series
3457  * @cmd_details: pointer to command details structure or NULL
3458  *
3459  * Read the NVM using the admin queue commands
3460  **/
3461 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3462                                 u32 offset, u16 length, void *data,
3463                                 bool last_command,
3464                                 struct i40e_asq_cmd_details *cmd_details)
3465 {
3466         struct i40e_aq_desc desc;
3467         struct i40e_aqc_nvm_update *cmd =
3468                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3469         enum i40e_status_code status;
3470
3471         DEBUGFUNC("i40e_aq_read_nvm");
3472
3473         /* In offset the highest byte must be zeroed. */
3474         if (offset & 0xFF000000) {
3475                 status = I40E_ERR_PARAM;
3476                 goto i40e_aq_read_nvm_exit;
3477         }
3478
3479         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3480
3481         /* If this is the last command in a series, set the proper flag. */
3482         if (last_command)
3483                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3484         cmd->module_pointer = module_pointer;
3485         cmd->offset = CPU_TO_LE32(offset);
3486         cmd->length = CPU_TO_LE16(length);
3487
3488         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3489         if (length > I40E_AQ_LARGE_BUF)
3490                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3491
3492         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3493
3494 i40e_aq_read_nvm_exit:
3495         return status;
3496 }
3497
3498 /**
3499  * i40e_aq_read_nvm_config - read an nvm config block
3500  * @hw: pointer to the hw struct
3501  * @cmd_flags: NVM access admin command bits
3502  * @field_id: field or feature id
3503  * @data: buffer for result
3504  * @buf_size: buffer size
3505  * @element_count: pointer to count of elements read by FW
3506  * @cmd_details: pointer to command details structure or NULL
3507  **/
3508 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3509                                 u8 cmd_flags, u32 field_id, void *data,
3510                                 u16 buf_size, u16 *element_count,
3511                                 struct i40e_asq_cmd_details *cmd_details)
3512 {
3513         struct i40e_aq_desc desc;
3514         struct i40e_aqc_nvm_config_read *cmd =
3515                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3516         enum i40e_status_code status;
3517
3518         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3519         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3520         if (buf_size > I40E_AQ_LARGE_BUF)
3521                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3522
3523         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3524         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3525         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3526                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3527         else
3528                 cmd->element_id_msw = 0;
3529
3530         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3531
3532         if (!status && element_count)
3533                 *element_count = LE16_TO_CPU(cmd->element_count);
3534
3535         return status;
3536 }
3537
3538 /**
3539  * i40e_aq_write_nvm_config - write an nvm config block
3540  * @hw: pointer to the hw struct
3541  * @cmd_flags: NVM access admin command bits
3542  * @data: buffer for result
3543  * @buf_size: buffer size
3544  * @element_count: count of elements to be written
3545  * @cmd_details: pointer to command details structure or NULL
3546  **/
3547 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3548                                 u8 cmd_flags, void *data, u16 buf_size,
3549                                 u16 element_count,
3550                                 struct i40e_asq_cmd_details *cmd_details)
3551 {
3552         struct i40e_aq_desc desc;
3553         struct i40e_aqc_nvm_config_write *cmd =
3554                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3555         enum i40e_status_code status;
3556
3557         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3558         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3559         if (buf_size > I40E_AQ_LARGE_BUF)
3560                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3561
3562         cmd->element_count = CPU_TO_LE16(element_count);
3563         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3564         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3565
3566         return status;
3567 }
3568
3569 /**
3570  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3571  * @hw: pointer to the hw struct
3572  * @cmd_details: pointer to command details structure or NULL
3573  **/
3574 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3575                                 void *buff, u16 buff_size,
3576                                 struct i40e_asq_cmd_details *cmd_details)
3577 {
3578         struct i40e_aq_desc desc;
3579         enum i40e_status_code status;
3580
3581         UNREFERENCED_2PARAMETER(buff, buff_size);
3582
3583         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3584         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3585         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3586                 status = I40E_ERR_NOT_IMPLEMENTED;
3587
3588         return status;
3589 }
3590
3591 /**
3592  * i40e_aq_erase_nvm
3593  * @hw: pointer to the hw struct
3594  * @module_pointer: module pointer location in words from the NVM beginning
3595  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3596  * @length: length of the section to be erased (expressed in 4 KB)
3597  * @last_command: tells if this is the last command in a series
3598  * @cmd_details: pointer to command details structure or NULL
3599  *
3600  * Erase the NVM sector using the admin queue commands
3601  **/
3602 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3603                                 u32 offset, u16 length, bool last_command,
3604                                 struct i40e_asq_cmd_details *cmd_details)
3605 {
3606         struct i40e_aq_desc desc;
3607         struct i40e_aqc_nvm_update *cmd =
3608                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3609         enum i40e_status_code status;
3610
3611         DEBUGFUNC("i40e_aq_erase_nvm");
3612
3613         /* In offset the highest byte must be zeroed. */
3614         if (offset & 0xFF000000) {
3615                 status = I40E_ERR_PARAM;
3616                 goto i40e_aq_erase_nvm_exit;
3617         }
3618
3619         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3620
3621         /* If this is the last command in a series, set the proper flag. */
3622         if (last_command)
3623                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3624         cmd->module_pointer = module_pointer;
3625         cmd->offset = CPU_TO_LE32(offset);
3626         cmd->length = CPU_TO_LE16(length);
3627
3628         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3629
3630 i40e_aq_erase_nvm_exit:
3631         return status;
3632 }
3633
3634 /**
3635  * i40e_parse_discover_capabilities
3636  * @hw: pointer to the hw struct
3637  * @buff: pointer to a buffer containing device/function capability records
3638  * @cap_count: number of capability records in the list
3639  * @list_type_opc: type of capabilities list to parse
3640  *
3641  * Parse the device/function capabilities list.
3642  **/
3643 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3644                                      u32 cap_count,
3645                                      enum i40e_admin_queue_opc list_type_opc)
3646 {
3647         struct i40e_aqc_list_capabilities_element_resp *cap;
3648         u32 valid_functions, num_functions;
3649         u32 number, logical_id, phys_id;
3650         struct i40e_hw_capabilities *p;
3651         u8 major_rev;
3652         u32 i = 0;
3653         u16 id;
3654
3655         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3656
3657         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3658                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3659         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3660                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3661         else
3662                 return;
3663
3664         for (i = 0; i < cap_count; i++, cap++) {
3665                 id = LE16_TO_CPU(cap->id);
3666                 number = LE32_TO_CPU(cap->number);
3667                 logical_id = LE32_TO_CPU(cap->logical_id);
3668                 phys_id = LE32_TO_CPU(cap->phys_id);
3669                 major_rev = cap->major_rev;
3670
3671                 switch (id) {
3672                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3673                         p->switch_mode = number;
3674                         i40e_debug(hw, I40E_DEBUG_INIT,
3675                                    "HW Capability: Switch mode = %d\n",
3676                                    p->switch_mode);
3677                         break;
3678                 case I40E_AQ_CAP_ID_MNG_MODE:
3679                         p->management_mode = number;
3680                         if (major_rev > 1) {
3681                                 p->mng_protocols_over_mctp = logical_id;
3682                                 i40e_debug(hw, I40E_DEBUG_INIT,
3683                                            "HW Capability: Protocols over MCTP = %d\n",
3684                                            p->mng_protocols_over_mctp);
3685                         } else {
3686                                 p->mng_protocols_over_mctp = 0;
3687                         }
3688                         i40e_debug(hw, I40E_DEBUG_INIT,
3689                                    "HW Capability: Management Mode = %d\n",
3690                                    p->management_mode);
3691                         break;
3692                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3693                         p->npar_enable = number;
3694                         i40e_debug(hw, I40E_DEBUG_INIT,
3695                                    "HW Capability: NPAR enable = %d\n",
3696                                    p->npar_enable);
3697                         break;
3698                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3699                         p->os2bmc = number;
3700                         i40e_debug(hw, I40E_DEBUG_INIT,
3701                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3702                         break;
3703                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3704                         p->valid_functions = number;
3705                         i40e_debug(hw, I40E_DEBUG_INIT,
3706                                    "HW Capability: Valid Functions = %d\n",
3707                                    p->valid_functions);
3708                         break;
3709                 case I40E_AQ_CAP_ID_SRIOV:
3710                         if (number == 1)
3711                                 p->sr_iov_1_1 = true;
3712                         i40e_debug(hw, I40E_DEBUG_INIT,
3713                                    "HW Capability: SR-IOV = %d\n",
3714                                    p->sr_iov_1_1);
3715                         break;
3716                 case I40E_AQ_CAP_ID_VF:
3717                         p->num_vfs = number;
3718                         p->vf_base_id = logical_id;
3719                         i40e_debug(hw, I40E_DEBUG_INIT,
3720                                    "HW Capability: VF count = %d\n",
3721                                    p->num_vfs);
3722                         i40e_debug(hw, I40E_DEBUG_INIT,
3723                                    "HW Capability: VF base_id = %d\n",
3724                                    p->vf_base_id);
3725                         break;
3726                 case I40E_AQ_CAP_ID_VMDQ:
3727                         if (number == 1)
3728                                 p->vmdq = true;
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3731                         break;
3732                 case I40E_AQ_CAP_ID_8021QBG:
3733                         if (number == 1)
3734                                 p->evb_802_1_qbg = true;
3735                         i40e_debug(hw, I40E_DEBUG_INIT,
3736                                    "HW Capability: 802.1Qbg = %d\n", number);
3737                         break;
3738                 case I40E_AQ_CAP_ID_8021QBR:
3739                         if (number == 1)
3740                                 p->evb_802_1_qbh = true;
3741                         i40e_debug(hw, I40E_DEBUG_INIT,
3742                                    "HW Capability: 802.1Qbh = %d\n", number);
3743                         break;
3744                 case I40E_AQ_CAP_ID_VSI:
3745                         p->num_vsis = number;
3746                         i40e_debug(hw, I40E_DEBUG_INIT,
3747                                    "HW Capability: VSI count = %d\n",
3748                                    p->num_vsis);
3749                         break;
3750                 case I40E_AQ_CAP_ID_DCB:
3751                         if (number == 1) {
3752                                 p->dcb = true;
3753                                 p->enabled_tcmap = logical_id;
3754                                 p->maxtc = phys_id;
3755                         }
3756                         i40e_debug(hw, I40E_DEBUG_INIT,
3757                                    "HW Capability: DCB = %d\n", p->dcb);
3758                         i40e_debug(hw, I40E_DEBUG_INIT,
3759                                    "HW Capability: TC Mapping = %d\n",
3760                                    logical_id);
3761                         i40e_debug(hw, I40E_DEBUG_INIT,
3762                                    "HW Capability: TC Max = %d\n", p->maxtc);
3763                         break;
3764                 case I40E_AQ_CAP_ID_FCOE:
3765                         if (number == 1)
3766                                 p->fcoe = true;
3767                         i40e_debug(hw, I40E_DEBUG_INIT,
3768                                    "HW Capability: FCOE = %d\n", p->fcoe);
3769                         break;
3770                 case I40E_AQ_CAP_ID_ISCSI:
3771                         if (number == 1)
3772                                 p->iscsi = true;
3773                         i40e_debug(hw, I40E_DEBUG_INIT,
3774                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3775                         break;
3776                 case I40E_AQ_CAP_ID_RSS:
3777                         p->rss = true;
3778                         p->rss_table_size = number;
3779                         p->rss_table_entry_width = logical_id;
3780                         i40e_debug(hw, I40E_DEBUG_INIT,
3781                                    "HW Capability: RSS = %d\n", p->rss);
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: RSS table size = %d\n",
3784                                    p->rss_table_size);
3785                         i40e_debug(hw, I40E_DEBUG_INIT,
3786                                    "HW Capability: RSS table width = %d\n",
3787                                    p->rss_table_entry_width);
3788                         break;
3789                 case I40E_AQ_CAP_ID_RXQ:
3790                         p->num_rx_qp = number;
3791                         p->base_queue = phys_id;
3792                         i40e_debug(hw, I40E_DEBUG_INIT,
3793                                    "HW Capability: Rx QP = %d\n", number);
3794                         i40e_debug(hw, I40E_DEBUG_INIT,
3795                                    "HW Capability: base_queue = %d\n",
3796                                    p->base_queue);
3797                         break;
3798                 case I40E_AQ_CAP_ID_TXQ:
3799                         p->num_tx_qp = number;
3800                         p->base_queue = phys_id;
3801                         i40e_debug(hw, I40E_DEBUG_INIT,
3802                                    "HW Capability: Tx QP = %d\n", number);
3803                         i40e_debug(hw, I40E_DEBUG_INIT,
3804                                    "HW Capability: base_queue = %d\n",
3805                                    p->base_queue);
3806                         break;
3807                 case I40E_AQ_CAP_ID_MSIX:
3808                         p->num_msix_vectors = number;
3809                         i40e_debug(hw, I40E_DEBUG_INIT,
3810                                    "HW Capability: MSIX vector count = %d\n",
3811                                    p->num_msix_vectors);
3812                         break;
3813                 case I40E_AQ_CAP_ID_VF_MSIX:
3814                         p->num_msix_vectors_vf = number;
3815                         i40e_debug(hw, I40E_DEBUG_INIT,
3816                                    "HW Capability: MSIX VF vector count = %d\n",
3817                                    p->num_msix_vectors_vf);
3818                         break;
3819                 case I40E_AQ_CAP_ID_FLEX10:
3820                         if (major_rev == 1) {
3821                                 if (number == 1) {
3822                                         p->flex10_enable = true;
3823                                         p->flex10_capable = true;
3824                                 }
3825                         } else {
3826                                 /* Capability revision >= 2 */
3827                                 if (number & 1)
3828                                         p->flex10_enable = true;
3829                                 if (number & 2)
3830                                         p->flex10_capable = true;
3831                         }
3832                         p->flex10_mode = logical_id;
3833                         p->flex10_status = phys_id;
3834                         i40e_debug(hw, I40E_DEBUG_INIT,
3835                                    "HW Capability: Flex10 mode = %d\n",
3836                                    p->flex10_mode);
3837                         i40e_debug(hw, I40E_DEBUG_INIT,
3838                                    "HW Capability: Flex10 status = %d\n",
3839                                    p->flex10_status);
3840                         break;
3841                 case I40E_AQ_CAP_ID_CEM:
3842                         if (number == 1)
3843                                 p->mgmt_cem = true;
3844                         i40e_debug(hw, I40E_DEBUG_INIT,
3845                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3846                         break;
3847                 case I40E_AQ_CAP_ID_IWARP:
3848                         if (number == 1)
3849                                 p->iwarp = true;
3850                         i40e_debug(hw, I40E_DEBUG_INIT,
3851                                    "HW Capability: iWARP = %d\n", p->iwarp);
3852                         break;
3853                 case I40E_AQ_CAP_ID_LED:
3854                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3855                                 p->led[phys_id] = true;
3856                         i40e_debug(hw, I40E_DEBUG_INIT,
3857                                    "HW Capability: LED - PIN %d\n", phys_id);
3858                         break;
3859                 case I40E_AQ_CAP_ID_SDP:
3860                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3861                                 p->sdp[phys_id] = true;
3862                         i40e_debug(hw, I40E_DEBUG_INIT,
3863                                    "HW Capability: SDP - PIN %d\n", phys_id);
3864                         break;
3865                 case I40E_AQ_CAP_ID_MDIO:
3866                         if (number == 1) {
3867                                 p->mdio_port_num = phys_id;
3868                                 p->mdio_port_mode = logical_id;
3869                         }
3870                         i40e_debug(hw, I40E_DEBUG_INIT,
3871                                    "HW Capability: MDIO port number = %d\n",
3872                                    p->mdio_port_num);
3873                         i40e_debug(hw, I40E_DEBUG_INIT,
3874                                    "HW Capability: MDIO port mode = %d\n",
3875                                    p->mdio_port_mode);
3876                         break;
3877                 case I40E_AQ_CAP_ID_1588:
3878                         if (number == 1)
3879                                 p->ieee_1588 = true;
3880                         i40e_debug(hw, I40E_DEBUG_INIT,
3881                                    "HW Capability: IEEE 1588 = %d\n",
3882                                    p->ieee_1588);
3883                         break;
3884                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3885                         p->fd = true;
3886                         p->fd_filters_guaranteed = number;
3887                         p->fd_filters_best_effort = logical_id;
3888                         i40e_debug(hw, I40E_DEBUG_INIT,
3889                                    "HW Capability: Flow Director = 1\n");
3890                         i40e_debug(hw, I40E_DEBUG_INIT,
3891                                    "HW Capability: Guaranteed FD filters = %d\n",
3892                                    p->fd_filters_guaranteed);
3893                         break;
3894                 case I40E_AQ_CAP_ID_WSR_PROT:
3895                         p->wr_csr_prot = (u64)number;
3896                         p->wr_csr_prot |= (u64)logical_id << 32;
3897                         i40e_debug(hw, I40E_DEBUG_INIT,
3898                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3899                                    (p->wr_csr_prot & 0xffff));
3900                         break;
3901                 case I40E_AQ_CAP_ID_NVM_MGMT:
3902                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3903                                 p->sec_rev_disabled = true;
3904                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3905                                 p->update_disabled = true;
3906                         break;
3907                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3908                         hw->num_wol_proxy_filters = (u16)number;
3909                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3910                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3911                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3912                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3913                         else
3914                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3915                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3916                         i40e_debug(hw, I40E_DEBUG_INIT,
3917                                    "HW Capability: WOL proxy filters = %d\n",
3918                                    hw->num_wol_proxy_filters);
3919                         break;
3920                 default:
3921                         break;
3922                 }
3923         }
3924
3925         if (p->fcoe)
3926                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3927
3928         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3929         p->fcoe = false;
3930
3931         /* count the enabled ports (aka the "not disabled" ports) */
3932         hw->num_ports = 0;
3933         for (i = 0; i < 4; i++) {
3934                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3935                 u64 port_cfg = 0;
3936
3937                 /* use AQ read to get the physical register offset instead
3938                  * of the port relative offset
3939                  */
3940                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3941                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3942                         hw->num_ports++;
3943         }
3944
3945         valid_functions = p->valid_functions;
3946         num_functions = 0;
3947         while (valid_functions) {
3948                 if (valid_functions & 1)
3949                         num_functions++;
3950                 valid_functions >>= 1;
3951         }
3952
3953         /* partition id is 1-based, and functions are evenly spread
3954          * across the ports as partitions
3955          */
3956         if (hw->num_ports != 0) {
3957                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3958                 hw->num_partitions = num_functions / hw->num_ports;
3959         }
3960
3961         /* additional HW specific goodies that might
3962          * someday be HW version specific
3963          */
3964         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3965 }
3966
3967 /**
3968  * i40e_aq_discover_capabilities
3969  * @hw: pointer to the hw struct
3970  * @buff: a virtual buffer to hold the capabilities
3971  * @buff_size: Size of the virtual buffer
3972  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3973  * @list_type_opc: capabilities type to discover - pass in the command opcode
3974  * @cmd_details: pointer to command details structure or NULL
3975  *
3976  * Get the device capabilities descriptions from the firmware
3977  **/
3978 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3979                                 void *buff, u16 buff_size, u16 *data_size,
3980                                 enum i40e_admin_queue_opc list_type_opc,
3981                                 struct i40e_asq_cmd_details *cmd_details)
3982 {
3983         struct i40e_aqc_list_capabilites *cmd;
3984         struct i40e_aq_desc desc;
3985         enum i40e_status_code status = I40E_SUCCESS;
3986
3987         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3988
3989         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3990                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3991                 status = I40E_ERR_PARAM;
3992                 goto exit;
3993         }
3994
3995         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3996
3997         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3998         if (buff_size > I40E_AQ_LARGE_BUF)
3999                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4000
4001         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4002         *data_size = LE16_TO_CPU(desc.datalen);
4003
4004         if (status)
4005                 goto exit;
4006
4007         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4008                                          list_type_opc);
4009
4010 exit:
4011         return status;
4012 }
4013
4014 /**
4015  * i40e_aq_update_nvm
4016  * @hw: pointer to the hw struct
4017  * @module_pointer: module pointer location in words from the NVM beginning
4018  * @offset: byte offset from the module beginning
4019  * @length: length of the section to be written (in bytes from the offset)
4020  * @data: command buffer (size [bytes] = length)
4021  * @last_command: tells if this is the last command in a series
4022  * @cmd_details: pointer to command details structure or NULL
4023  *
4024  * Update the NVM using the admin queue commands
4025  **/
4026 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4027                                 u32 offset, u16 length, void *data,
4028                                 bool last_command,
4029                                 struct i40e_asq_cmd_details *cmd_details)
4030 {
4031         struct i40e_aq_desc desc;
4032         struct i40e_aqc_nvm_update *cmd =
4033                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4034         enum i40e_status_code status;
4035
4036         DEBUGFUNC("i40e_aq_update_nvm");
4037
4038         /* In offset the highest byte must be zeroed. */
4039         if (offset & 0xFF000000) {
4040                 status = I40E_ERR_PARAM;
4041                 goto i40e_aq_update_nvm_exit;
4042         }
4043
4044         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4045
4046         /* If this is the last command in a series, set the proper flag. */
4047         if (last_command)
4048                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4049         cmd->module_pointer = module_pointer;
4050         cmd->offset = CPU_TO_LE32(offset);
4051         cmd->length = CPU_TO_LE16(length);
4052
4053         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4054         if (length > I40E_AQ_LARGE_BUF)
4055                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4056
4057         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4058
4059 i40e_aq_update_nvm_exit:
4060         return status;
4061 }
4062
4063 /**
4064  * i40e_aq_get_lldp_mib
4065  * @hw: pointer to the hw struct
4066  * @bridge_type: type of bridge requested
4067  * @mib_type: Local, Remote or both Local and Remote MIBs
4068  * @buff: pointer to a user supplied buffer to store the MIB block
4069  * @buff_size: size of the buffer (in bytes)
4070  * @local_len : length of the returned Local LLDP MIB
4071  * @remote_len: length of the returned Remote LLDP MIB
4072  * @cmd_details: pointer to command details structure or NULL
4073  *
4074  * Requests the complete LLDP MIB (entire packet).
4075  **/
4076 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4077                                 u8 mib_type, void *buff, u16 buff_size,
4078                                 u16 *local_len, u16 *remote_len,
4079                                 struct i40e_asq_cmd_details *cmd_details)
4080 {
4081         struct i40e_aq_desc desc;
4082         struct i40e_aqc_lldp_get_mib *cmd =
4083                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4084         struct i40e_aqc_lldp_get_mib *resp =
4085                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4086         enum i40e_status_code status;
4087
4088         if (buff_size == 0 || !buff)
4089                 return I40E_ERR_PARAM;
4090
4091         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4092         /* Indirect Command */
4093         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4094
4095         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4096         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4097                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4098
4099         desc.datalen = CPU_TO_LE16(buff_size);
4100
4101         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4102         if (buff_size > I40E_AQ_LARGE_BUF)
4103                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4104
4105         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4106         if (!status) {
4107                 if (local_len != NULL)
4108                         *local_len = LE16_TO_CPU(resp->local_len);
4109                 if (remote_len != NULL)
4110                         *remote_len = LE16_TO_CPU(resp->remote_len);
4111         }
4112
4113         return status;
4114 }
4115
4116  /**
4117  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4118  * @hw: pointer to the hw struct
4119  * @mib_type: Local, Remote or both Local and Remote MIBs
4120  * @buff: pointer to a user supplied buffer to store the MIB block
4121  * @buff_size: size of the buffer (in bytes)
4122  * @cmd_details: pointer to command details structure or NULL
4123  *
4124  * Set the LLDP MIB.
4125  **/
4126 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4127                                 u8 mib_type, void *buff, u16 buff_size,
4128                                 struct i40e_asq_cmd_details *cmd_details)
4129 {
4130         struct i40e_aq_desc desc;
4131         struct i40e_aqc_lldp_set_local_mib *cmd =
4132                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4133         enum i40e_status_code status;
4134
4135         if (buff_size == 0 || !buff)
4136                 return I40E_ERR_PARAM;
4137
4138         i40e_fill_default_direct_cmd_desc(&desc,
4139                                 i40e_aqc_opc_lldp_set_local_mib);
4140         /* Indirect Command */
4141         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4142         if (buff_size > I40E_AQ_LARGE_BUF)
4143                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4144         desc.datalen = CPU_TO_LE16(buff_size);
4145
4146         cmd->type = mib_type;
4147         cmd->length = CPU_TO_LE16(buff_size);
4148         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4149         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4150
4151         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4152         return status;
4153 }
4154
4155 /**
4156  * i40e_aq_cfg_lldp_mib_change_event
4157  * @hw: pointer to the hw struct
4158  * @enable_update: Enable or Disable event posting
4159  * @cmd_details: pointer to command details structure or NULL
4160  *
4161  * Enable or Disable posting of an event on ARQ when LLDP MIB
4162  * associated with the interface changes
4163  **/
4164 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4165                                 bool enable_update,
4166                                 struct i40e_asq_cmd_details *cmd_details)
4167 {
4168         struct i40e_aq_desc desc;
4169         struct i40e_aqc_lldp_update_mib *cmd =
4170                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4171         enum i40e_status_code status;
4172
4173         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4174
4175         if (!enable_update)
4176                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4177
4178         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4179
4180         return status;
4181 }
4182
4183 /**
4184  * i40e_aq_add_lldp_tlv
4185  * @hw: pointer to the hw struct
4186  * @bridge_type: type of bridge
4187  * @buff: buffer with TLV to add
4188  * @buff_size: length of the buffer
4189  * @tlv_len: length of the TLV to be added
4190  * @mib_len: length of the LLDP MIB returned in response
4191  * @cmd_details: pointer to command details structure or NULL
4192  *
4193  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4194  * it is responsibility of the caller to make sure that the TLV is not
4195  * already present in the LLDPDU.
4196  * In return firmware will write the complete LLDP MIB with the newly
4197  * added TLV in the response buffer.
4198  **/
4199 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4200                                 void *buff, u16 buff_size, u16 tlv_len,
4201                                 u16 *mib_len,
4202                                 struct i40e_asq_cmd_details *cmd_details)
4203 {
4204         struct i40e_aq_desc desc;
4205         struct i40e_aqc_lldp_add_tlv *cmd =
4206                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4207         enum i40e_status_code status;
4208
4209         if (buff_size == 0 || !buff || tlv_len == 0)
4210                 return I40E_ERR_PARAM;
4211
4212         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4213
4214         /* Indirect Command */
4215         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4216         if (buff_size > I40E_AQ_LARGE_BUF)
4217                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4218         desc.datalen = CPU_TO_LE16(buff_size);
4219
4220         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4221                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4222         cmd->len = CPU_TO_LE16(tlv_len);
4223
4224         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4225         if (!status) {
4226                 if (mib_len != NULL)
4227                         *mib_len = LE16_TO_CPU(desc.datalen);
4228         }
4229
4230         return status;
4231 }
4232
4233 /**
4234  * i40e_aq_update_lldp_tlv
4235  * @hw: pointer to the hw struct
4236  * @bridge_type: type of bridge
4237  * @buff: buffer with TLV to update
4238  * @buff_size: size of the buffer holding original and updated TLVs
4239  * @old_len: Length of the Original TLV
4240  * @new_len: Length of the Updated TLV
4241  * @offset: offset of the updated TLV in the buff
4242  * @mib_len: length of the returned LLDP MIB
4243  * @cmd_details: pointer to command details structure or NULL
4244  *
4245  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4246  * Firmware will place the complete LLDP MIB in response buffer with the
4247  * updated TLV.
4248  **/
4249 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4250                                 u8 bridge_type, void *buff, u16 buff_size,
4251                                 u16 old_len, u16 new_len, u16 offset,
4252                                 u16 *mib_len,
4253                                 struct i40e_asq_cmd_details *cmd_details)
4254 {
4255         struct i40e_aq_desc desc;
4256         struct i40e_aqc_lldp_update_tlv *cmd =
4257                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4258         enum i40e_status_code status;
4259
4260         if (buff_size == 0 || !buff || offset == 0 ||
4261             old_len == 0 || new_len == 0)
4262                 return I40E_ERR_PARAM;
4263
4264         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4265
4266         /* Indirect Command */
4267         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4268         if (buff_size > I40E_AQ_LARGE_BUF)
4269                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4270         desc.datalen = CPU_TO_LE16(buff_size);
4271
4272         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4273                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4274         cmd->old_len = CPU_TO_LE16(old_len);
4275         cmd->new_offset = CPU_TO_LE16(offset);
4276         cmd->new_len = CPU_TO_LE16(new_len);
4277
4278         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4279         if (!status) {
4280                 if (mib_len != NULL)
4281                         *mib_len = LE16_TO_CPU(desc.datalen);
4282         }
4283
4284         return status;
4285 }
4286
4287 /**
4288  * i40e_aq_delete_lldp_tlv
4289  * @hw: pointer to the hw struct
4290  * @bridge_type: type of bridge
4291  * @buff: pointer to a user supplied buffer that has the TLV
4292  * @buff_size: length of the buffer
4293  * @tlv_len: length of the TLV to be deleted
4294  * @mib_len: length of the returned LLDP MIB
4295  * @cmd_details: pointer to command details structure or NULL
4296  *
4297  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4298  * The firmware places the entire LLDP MIB in the response buffer.
4299  **/
4300 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4301                                 u8 bridge_type, void *buff, u16 buff_size,
4302                                 u16 tlv_len, u16 *mib_len,
4303                                 struct i40e_asq_cmd_details *cmd_details)
4304 {
4305         struct i40e_aq_desc desc;
4306         struct i40e_aqc_lldp_add_tlv *cmd =
4307                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4308         enum i40e_status_code status;
4309
4310         if (buff_size == 0 || !buff)
4311                 return I40E_ERR_PARAM;
4312
4313         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4314
4315         /* Indirect Command */
4316         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4317         if (buff_size > I40E_AQ_LARGE_BUF)
4318                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4319         desc.datalen = CPU_TO_LE16(buff_size);
4320         cmd->len = CPU_TO_LE16(tlv_len);
4321         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4322                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4323
4324         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4325         if (!status) {
4326                 if (mib_len != NULL)
4327                         *mib_len = LE16_TO_CPU(desc.datalen);
4328         }
4329
4330         return status;
4331 }
4332
4333 /**
4334  * i40e_aq_stop_lldp
4335  * @hw: pointer to the hw struct
4336  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4337  * @cmd_details: pointer to command details structure or NULL
4338  *
4339  * Stop or Shutdown the embedded LLDP Agent
4340  **/
4341 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4342                                 struct i40e_asq_cmd_details *cmd_details)
4343 {
4344         struct i40e_aq_desc desc;
4345         struct i40e_aqc_lldp_stop *cmd =
4346                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4347         enum i40e_status_code status;
4348
4349         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4350
4351         if (shutdown_agent)
4352                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4353
4354         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4355
4356         return status;
4357 }
4358
4359 /**
4360  * i40e_aq_start_lldp
4361  * @hw: pointer to the hw struct
4362  * @cmd_details: pointer to command details structure or NULL
4363  *
4364  * Start the embedded LLDP Agent on all ports.
4365  **/
4366 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4367                                 struct i40e_asq_cmd_details *cmd_details)
4368 {
4369         struct i40e_aq_desc desc;
4370         struct i40e_aqc_lldp_start *cmd =
4371                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4372         enum i40e_status_code status;
4373
4374         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4375
4376         cmd->command = I40E_AQ_LLDP_AGENT_START;
4377
4378         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4379
4380         return status;
4381 }
4382
4383 /**
4384  * i40e_aq_get_cee_dcb_config
4385  * @hw: pointer to the hw struct
4386  * @buff: response buffer that stores CEE operational configuration
4387  * @buff_size: size of the buffer passed
4388  * @cmd_details: pointer to command details structure or NULL
4389  *
4390  * Get CEE DCBX mode operational configuration from firmware
4391  **/
4392 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4393                                 void *buff, u16 buff_size,
4394                                 struct i40e_asq_cmd_details *cmd_details)
4395 {
4396         struct i40e_aq_desc desc;
4397         enum i40e_status_code status;
4398
4399         if (buff_size == 0 || !buff)
4400                 return I40E_ERR_PARAM;
4401
4402         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4403
4404         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4405         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4406                                        cmd_details);
4407
4408         return status;
4409 }
4410
4411 /**
4412  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4413  * @hw: pointer to the hw struct
4414  * @start_agent: True if DCBx Agent needs to be Started
4415  *                              False if DCBx Agent needs to be Stopped
4416  * @cmd_details: pointer to command details structure or NULL
4417  *
4418  * Start/Stop the embedded dcbx Agent
4419  **/
4420 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4421                                 bool start_agent,
4422                                 struct i40e_asq_cmd_details *cmd_details)
4423 {
4424         struct i40e_aq_desc desc;
4425         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4426                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4427                                 &desc.params.raw;
4428         enum i40e_status_code status;
4429
4430         i40e_fill_default_direct_cmd_desc(&desc,
4431                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4432
4433         if (start_agent)
4434                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4435
4436         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4437
4438         return status;
4439 }
4440
4441 /**
4442  * i40e_aq_add_udp_tunnel
4443  * @hw: pointer to the hw struct
4444  * @udp_port: the UDP port to add in Host byte order
4445  * @header_len: length of the tunneling header length in DWords
4446  * @protocol_index: protocol index type
4447  * @filter_index: pointer to filter index
4448  * @cmd_details: pointer to command details structure or NULL
4449  *
4450  * Note: Firmware expects the udp_port value to be in Little Endian format,
4451  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4452  * Little Endian order.
4453  **/
4454 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4455                                 u16 udp_port, u8 protocol_index,
4456                                 u8 *filter_index,
4457                                 struct i40e_asq_cmd_details *cmd_details)
4458 {
4459         struct i40e_aq_desc desc;
4460         struct i40e_aqc_add_udp_tunnel *cmd =
4461                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4462         struct i40e_aqc_del_udp_tunnel_completion *resp =
4463                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4464         enum i40e_status_code status;
4465
4466         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4467
4468         cmd->udp_port = CPU_TO_LE16(udp_port);
4469         cmd->protocol_type = protocol_index;
4470
4471         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4472
4473         if (!status && filter_index)
4474                 *filter_index = resp->index;
4475
4476         return status;
4477 }
4478
4479 /**
4480  * i40e_aq_del_udp_tunnel
4481  * @hw: pointer to the hw struct
4482  * @index: filter index
4483  * @cmd_details: pointer to command details structure or NULL
4484  **/
4485 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4486                                 struct i40e_asq_cmd_details *cmd_details)
4487 {
4488         struct i40e_aq_desc desc;
4489         struct i40e_aqc_remove_udp_tunnel *cmd =
4490                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4491         enum i40e_status_code status;
4492
4493         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4494
4495         cmd->index = index;
4496
4497         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4498
4499         return status;
4500 }
4501
4502 /**
4503  * i40e_aq_get_switch_resource_alloc (0x0204)
4504  * @hw: pointer to the hw struct
4505  * @num_entries: pointer to u8 to store the number of resource entries returned
4506  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4507  *        to store the resource information for all resource types.  Each
4508  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4509  * @count: size, in bytes, of the buffer provided
4510  * @cmd_details: pointer to command details structure or NULL
4511  *
4512  * Query the resources allocated to a function.
4513  **/
4514 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4515                         u8 *num_entries,
4516                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4517                         u16 count,
4518                         struct i40e_asq_cmd_details *cmd_details)
4519 {
4520         struct i40e_aq_desc desc;
4521         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4522                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4523         enum i40e_status_code status;
4524         u16 length = count * sizeof(*buf);
4525
4526         i40e_fill_default_direct_cmd_desc(&desc,
4527                                         i40e_aqc_opc_get_switch_resource_alloc);
4528
4529         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4530         if (length > I40E_AQ_LARGE_BUF)
4531                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4532
4533         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4534
4535         if (!status && num_entries)
4536                 *num_entries = cmd_resp->num_entries;
4537
4538         return status;
4539 }
4540
4541 /**
4542  * i40e_aq_delete_element - Delete switch element
4543  * @hw: pointer to the hw struct
4544  * @seid: the SEID to delete from the switch
4545  * @cmd_details: pointer to command details structure or NULL
4546  *
4547  * This deletes a switch element from the switch.
4548  **/
4549 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4550                                 struct i40e_asq_cmd_details *cmd_details)
4551 {
4552         struct i40e_aq_desc desc;
4553         struct i40e_aqc_switch_seid *cmd =
4554                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4555         enum i40e_status_code status;
4556
4557         if (seid == 0)
4558                 return I40E_ERR_PARAM;
4559
4560         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4561
4562         cmd->seid = CPU_TO_LE16(seid);
4563
4564         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4565
4566         return status;
4567 }
4568
4569 /**
4570  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4571  * @hw: pointer to the hw struct
4572  * @flags: component flags
4573  * @mac_seid: uplink seid (MAC SEID)
4574  * @vsi_seid: connected vsi seid
4575  * @ret_seid: seid of create pv component
4576  *
4577  * This instantiates an i40e port virtualizer with specified flags.
4578  * Depending on specified flags the port virtualizer can act as a
4579  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4580  */
4581 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4582                                        u16 mac_seid, u16 vsi_seid,
4583                                        u16 *ret_seid)
4584 {
4585         struct i40e_aq_desc desc;
4586         struct i40e_aqc_add_update_pv *cmd =
4587                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4588         struct i40e_aqc_add_update_pv_completion *resp =
4589                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4590         enum i40e_status_code status;
4591
4592         if (vsi_seid == 0)
4593                 return I40E_ERR_PARAM;
4594
4595         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4596         cmd->command_flags = CPU_TO_LE16(flags);
4597         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4598         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4599
4600         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4601         if (!status && ret_seid)
4602                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4603
4604         return status;
4605 }
4606
4607 /**
4608  * i40e_aq_add_tag - Add an S/E-tag
4609  * @hw: pointer to the hw struct
4610  * @direct_to_queue: should s-tag direct flow to a specific queue
4611  * @vsi_seid: VSI SEID to use this tag
4612  * @tag: value of the tag
4613  * @queue_num: queue number, only valid is direct_to_queue is true
4614  * @tags_used: return value, number of tags in use by this PF
4615  * @tags_free: return value, number of unallocated tags
4616  * @cmd_details: pointer to command details structure or NULL
4617  *
4618  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4619  * the number of tags allocated by the PF, and the number of unallocated
4620  * tags available.
4621  **/
4622 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4623                                 u16 vsi_seid, u16 tag, u16 queue_num,
4624                                 u16 *tags_used, u16 *tags_free,
4625                                 struct i40e_asq_cmd_details *cmd_details)
4626 {
4627         struct i40e_aq_desc desc;
4628         struct i40e_aqc_add_tag *cmd =
4629                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4630         struct i40e_aqc_add_remove_tag_completion *resp =
4631                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4632         enum i40e_status_code status;
4633
4634         if (vsi_seid == 0)
4635                 return I40E_ERR_PARAM;
4636
4637         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4638
4639         cmd->seid = CPU_TO_LE16(vsi_seid);
4640         cmd->tag = CPU_TO_LE16(tag);
4641         if (direct_to_queue) {
4642                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4643                 cmd->queue_number = CPU_TO_LE16(queue_num);
4644         }
4645
4646         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4647
4648         if (!status) {
4649                 if (tags_used != NULL)
4650                         *tags_used = LE16_TO_CPU(resp->tags_used);
4651                 if (tags_free != NULL)
4652                         *tags_free = LE16_TO_CPU(resp->tags_free);
4653         }
4654
4655         return status;
4656 }
4657
4658 /**
4659  * i40e_aq_remove_tag - Remove an S- or E-tag
4660  * @hw: pointer to the hw struct
4661  * @vsi_seid: VSI SEID this tag is associated with
4662  * @tag: value of the S-tag to delete
4663  * @tags_used: return value, number of tags in use by this PF
4664  * @tags_free: return value, number of unallocated tags
4665  * @cmd_details: pointer to command details structure or NULL
4666  *
4667  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4668  * the number of tags allocated by the PF, and the number of unallocated
4669  * tags available.
4670  **/
4671 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4672                                 u16 tag, u16 *tags_used, u16 *tags_free,
4673                                 struct i40e_asq_cmd_details *cmd_details)
4674 {
4675         struct i40e_aq_desc desc;
4676         struct i40e_aqc_remove_tag *cmd =
4677                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4678         struct i40e_aqc_add_remove_tag_completion *resp =
4679                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4680         enum i40e_status_code status;
4681
4682         if (vsi_seid == 0)
4683                 return I40E_ERR_PARAM;
4684
4685         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4686
4687         cmd->seid = CPU_TO_LE16(vsi_seid);
4688         cmd->tag = CPU_TO_LE16(tag);
4689
4690         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4691
4692         if (!status) {
4693                 if (tags_used != NULL)
4694                         *tags_used = LE16_TO_CPU(resp->tags_used);
4695                 if (tags_free != NULL)
4696                         *tags_free = LE16_TO_CPU(resp->tags_free);
4697         }
4698
4699         return status;
4700 }
4701
4702 /**
4703  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4704  * @hw: pointer to the hw struct
4705  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4706  * @etag: value of E-tag to add
4707  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4708  * @buf: address of indirect buffer
4709  * @tags_used: return value, number of E-tags in use by this port
4710  * @tags_free: return value, number of unallocated M-tags
4711  * @cmd_details: pointer to command details structure or NULL
4712  *
4713  * This associates a multicast E-tag to a port virtualizer.  It will return
4714  * the number of tags allocated by the PF, and the number of unallocated
4715  * tags available.
4716  *
4717  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4718  * num_tags_in_buf long.
4719  **/
4720 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4721                                 u16 etag, u8 num_tags_in_buf, void *buf,
4722                                 u16 *tags_used, u16 *tags_free,
4723                                 struct i40e_asq_cmd_details *cmd_details)
4724 {
4725         struct i40e_aq_desc desc;
4726         struct i40e_aqc_add_remove_mcast_etag *cmd =
4727                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4728         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4729            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4730         enum i40e_status_code status;
4731         u16 length = sizeof(u16) * num_tags_in_buf;
4732
4733         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4734                 return I40E_ERR_PARAM;
4735
4736         i40e_fill_default_direct_cmd_desc(&desc,
4737                                           i40e_aqc_opc_add_multicast_etag);
4738
4739         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4740         cmd->etag = CPU_TO_LE16(etag);
4741         cmd->num_unicast_etags = num_tags_in_buf;
4742
4743         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4744         if (length > I40E_AQ_LARGE_BUF)
4745                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4746
4747         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4748
4749         if (!status) {
4750                 if (tags_used != NULL)
4751                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4752                 if (tags_free != NULL)
4753                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4754         }
4755
4756         return status;
4757 }
4758
4759 /**
4760  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4761  * @hw: pointer to the hw struct
4762  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4763  * @etag: value of the E-tag to remove
4764  * @tags_used: return value, number of tags in use by this port
4765  * @tags_free: return value, number of unallocated tags
4766  * @cmd_details: pointer to command details structure or NULL
4767  *
4768  * This deletes an E-tag from the port virtualizer.  It will return
4769  * the number of tags allocated by the port, and the number of unallocated
4770  * tags available.
4771  **/
4772 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4773                                 u16 etag, u16 *tags_used, u16 *tags_free,
4774                                 struct i40e_asq_cmd_details *cmd_details)
4775 {
4776         struct i40e_aq_desc desc;
4777         struct i40e_aqc_add_remove_mcast_etag *cmd =
4778                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4779         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4780            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4781         enum i40e_status_code status;
4782
4783
4784         if (pv_seid == 0)
4785                 return I40E_ERR_PARAM;
4786
4787         i40e_fill_default_direct_cmd_desc(&desc,
4788                                           i40e_aqc_opc_remove_multicast_etag);
4789
4790         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4791         cmd->etag = CPU_TO_LE16(etag);
4792
4793         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4794
4795         if (!status) {
4796                 if (tags_used != NULL)
4797                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4798                 if (tags_free != NULL)
4799                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4800         }
4801
4802         return status;
4803 }
4804
4805 /**
4806  * i40e_aq_update_tag - Update an S/E-tag
4807  * @hw: pointer to the hw struct
4808  * @vsi_seid: VSI SEID using this S-tag
4809  * @old_tag: old tag value
4810  * @new_tag: new tag value
4811  * @tags_used: return value, number of tags in use by this PF
4812  * @tags_free: return value, number of unallocated tags
4813  * @cmd_details: pointer to command details structure or NULL
4814  *
4815  * This updates the value of the tag currently attached to this VSI
4816  * in the switch complex.  It will return the number of tags allocated
4817  * by the PF, and the number of unallocated tags available.
4818  **/
4819 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4820                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4821                                 u16 *tags_free,
4822                                 struct i40e_asq_cmd_details *cmd_details)
4823 {
4824         struct i40e_aq_desc desc;
4825         struct i40e_aqc_update_tag *cmd =
4826                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4827         struct i40e_aqc_update_tag_completion *resp =
4828                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4829         enum i40e_status_code status;
4830
4831         if (vsi_seid == 0)
4832                 return I40E_ERR_PARAM;
4833
4834         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4835
4836         cmd->seid = CPU_TO_LE16(vsi_seid);
4837         cmd->old_tag = CPU_TO_LE16(old_tag);
4838         cmd->new_tag = CPU_TO_LE16(new_tag);
4839
4840         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4841
4842         if (!status) {
4843                 if (tags_used != NULL)
4844                         *tags_used = LE16_TO_CPU(resp->tags_used);
4845                 if (tags_free != NULL)
4846                         *tags_free = LE16_TO_CPU(resp->tags_free);
4847         }
4848
4849         return status;
4850 }
4851
4852 /**
4853  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4854  * @hw: pointer to the hw struct
4855  * @tcmap: TC map for request/release any ignore PFC condition
4856  * @request: request or release ignore PFC condition
4857  * @tcmap_ret: return TCs for which PFC is currently ignored
4858  * @cmd_details: pointer to command details structure or NULL
4859  *
4860  * This sends out request/release to ignore PFC condition for a TC.
4861  * It will return the TCs for which PFC is currently ignored.
4862  **/
4863 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4864                                 bool request, u8 *tcmap_ret,
4865                                 struct i40e_asq_cmd_details *cmd_details)
4866 {
4867         struct i40e_aq_desc desc;
4868         struct i40e_aqc_pfc_ignore *cmd_resp =
4869                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4870         enum i40e_status_code status;
4871
4872         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4873
4874         if (request)
4875                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4876
4877         cmd_resp->tc_bitmap = tcmap;
4878
4879         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4880
4881         if (!status) {
4882                 if (tcmap_ret != NULL)
4883                         *tcmap_ret = cmd_resp->tc_bitmap;
4884         }
4885
4886         return status;
4887 }
4888
4889 /**
4890  * i40e_aq_dcb_updated - DCB Updated Command
4891  * @hw: pointer to the hw struct
4892  * @cmd_details: pointer to command details structure or NULL
4893  *
4894  * When LLDP is handled in PF this command is used by the PF
4895  * to notify EMP that a DCB setting is modified.
4896  * When LLDP is handled in EMP this command is used by the PF
4897  * to notify EMP whenever one of the following parameters get
4898  * modified:
4899  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4900  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4901  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4902  * EMP will return when the shared RPB settings have been
4903  * recomputed and modified. The retval field in the descriptor
4904  * will be set to 0 when RPB is modified.
4905  **/
4906 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4907                                 struct i40e_asq_cmd_details *cmd_details)
4908 {
4909         struct i40e_aq_desc desc;
4910         enum i40e_status_code status;
4911
4912         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4913
4914         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4915
4916         return status;
4917 }
4918
4919 /**
4920  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4921  * @hw: pointer to the hw struct
4922  * @seid: defines the SEID of the switch for which the stats are requested
4923  * @vlan_id: the VLAN ID for which the statistics are requested
4924  * @stat_index: index of the statistics counters block assigned to this VLAN
4925  * @cmd_details: pointer to command details structure or NULL
4926  *
4927  * XL710 supports 128 smonVlanStats counters.This command is used to
4928  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4929  * switch.
4930  **/
4931 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4932                                 u16 vlan_id, u16 *stat_index,
4933                                 struct i40e_asq_cmd_details *cmd_details)
4934 {
4935         struct i40e_aq_desc desc;
4936         struct i40e_aqc_add_remove_statistics *cmd_resp =
4937                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4938         enum i40e_status_code status;
4939
4940         if ((seid == 0) || (stat_index == NULL))
4941                 return I40E_ERR_PARAM;
4942
4943         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4944
4945         cmd_resp->seid = CPU_TO_LE16(seid);
4946         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4947
4948         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4949
4950         if (!status && stat_index)
4951                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4952
4953         return status;
4954 }
4955
4956 /**
4957  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4958  * @hw: pointer to the hw struct
4959  * @seid: defines the SEID of the switch for which the stats are requested
4960  * @vlan_id: the VLAN ID for which the statistics are requested
4961  * @stat_index: index of the statistics counters block assigned to this VLAN
4962  * @cmd_details: pointer to command details structure or NULL
4963  *
4964  * XL710 supports 128 smonVlanStats counters.This command is used to
4965  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4966  * switch.
4967  **/
4968 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4969                                 u16 vlan_id, u16 stat_index,
4970                                 struct i40e_asq_cmd_details *cmd_details)
4971 {
4972         struct i40e_aq_desc desc;
4973         struct i40e_aqc_add_remove_statistics *cmd =
4974                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4975         enum i40e_status_code status;
4976
4977         if (seid == 0)
4978                 return I40E_ERR_PARAM;
4979
4980         i40e_fill_default_direct_cmd_desc(&desc,
4981                                           i40e_aqc_opc_remove_statistics);
4982
4983         cmd->seid = CPU_TO_LE16(seid);
4984         cmd->vlan  = CPU_TO_LE16(vlan_id);
4985         cmd->stat_index = CPU_TO_LE16(stat_index);
4986
4987         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4988
4989         return status;
4990 }
4991
4992 /**
4993  * i40e_aq_set_port_parameters - set physical port parameters.
4994  * @hw: pointer to the hw struct
4995  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4996  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4997  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4998  * @double_vlan: if set double VLAN is enabled
4999  * @cmd_details: pointer to command details structure or NULL
5000  **/
5001 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5002                                 u16 bad_frame_vsi, bool save_bad_pac,
5003                                 bool pad_short_pac, bool double_vlan,
5004                                 struct i40e_asq_cmd_details *cmd_details)
5005 {
5006         struct i40e_aqc_set_port_parameters *cmd;
5007         enum i40e_status_code status;
5008         struct i40e_aq_desc desc;
5009         u16 command_flags = 0;
5010
5011         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5012
5013         i40e_fill_default_direct_cmd_desc(&desc,
5014                                           i40e_aqc_opc_set_port_parameters);
5015
5016         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5017         if (save_bad_pac)
5018                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5019         if (pad_short_pac)
5020                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5021         if (double_vlan)
5022                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5023         cmd->command_flags = CPU_TO_LE16(command_flags);
5024
5025         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5026
5027         return status;
5028 }
5029
5030 /**
5031  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5032  * @hw: pointer to the hw struct
5033  * @seid: seid for the physical port/switching component/vsi
5034  * @buff: Indirect buffer to hold data parameters and response
5035  * @buff_size: Indirect buffer size
5036  * @opcode: Tx scheduler AQ command opcode
5037  * @cmd_details: pointer to command details structure or NULL
5038  *
5039  * Generic command handler for Tx scheduler AQ commands
5040  **/
5041 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5042                                 void *buff, u16 buff_size,
5043                                  enum i40e_admin_queue_opc opcode,
5044                                 struct i40e_asq_cmd_details *cmd_details)
5045 {
5046         struct i40e_aq_desc desc;
5047         struct i40e_aqc_tx_sched_ind *cmd =
5048                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5049         enum i40e_status_code status;
5050         bool cmd_param_flag = false;
5051
5052         switch (opcode) {
5053         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5054         case i40e_aqc_opc_configure_vsi_tc_bw:
5055         case i40e_aqc_opc_enable_switching_comp_ets:
5056         case i40e_aqc_opc_modify_switching_comp_ets:
5057         case i40e_aqc_opc_disable_switching_comp_ets:
5058         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5059         case i40e_aqc_opc_configure_switching_comp_bw_config:
5060                 cmd_param_flag = true;
5061                 break;
5062         case i40e_aqc_opc_query_vsi_bw_config:
5063         case i40e_aqc_opc_query_vsi_ets_sla_config:
5064         case i40e_aqc_opc_query_switching_comp_ets_config:
5065         case i40e_aqc_opc_query_port_ets_config:
5066         case i40e_aqc_opc_query_switching_comp_bw_config:
5067                 cmd_param_flag = false;
5068                 break;
5069         default:
5070                 return I40E_ERR_PARAM;
5071         }
5072
5073         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5074
5075         /* Indirect command */
5076         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5077         if (cmd_param_flag)
5078                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5079         if (buff_size > I40E_AQ_LARGE_BUF)
5080                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5081
5082         desc.datalen = CPU_TO_LE16(buff_size);
5083
5084         cmd->vsi_seid = CPU_TO_LE16(seid);
5085
5086         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5087
5088         return status;
5089 }
5090
5091 /**
5092  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5093  * @hw: pointer to the hw struct
5094  * @seid: VSI seid
5095  * @credit: BW limit credits (0 = disabled)
5096  * @max_credit: Max BW limit credits
5097  * @cmd_details: pointer to command details structure or NULL
5098  **/
5099 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5100                                 u16 seid, u16 credit, u8 max_credit,
5101                                 struct i40e_asq_cmd_details *cmd_details)
5102 {
5103         struct i40e_aq_desc desc;
5104         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5105                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5106         enum i40e_status_code status;
5107
5108         i40e_fill_default_direct_cmd_desc(&desc,
5109                                           i40e_aqc_opc_configure_vsi_bw_limit);
5110
5111         cmd->vsi_seid = CPU_TO_LE16(seid);
5112         cmd->credit = CPU_TO_LE16(credit);
5113         cmd->max_credit = max_credit;
5114
5115         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5116
5117         return status;
5118 }
5119
5120 /**
5121  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5122  * @hw: pointer to the hw struct
5123  * @seid: switching component seid
5124  * @credit: BW limit credits (0 = disabled)
5125  * @max_bw: Max BW limit credits
5126  * @cmd_details: pointer to command details structure or NULL
5127  **/
5128 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5129                                 u16 seid, u16 credit, u8 max_bw,
5130                                 struct i40e_asq_cmd_details *cmd_details)
5131 {
5132         struct i40e_aq_desc desc;
5133         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5134           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5135         enum i40e_status_code status;
5136
5137         i40e_fill_default_direct_cmd_desc(&desc,
5138                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5139
5140         cmd->seid = CPU_TO_LE16(seid);
5141         cmd->credit = CPU_TO_LE16(credit);
5142         cmd->max_bw = max_bw;
5143
5144         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5145
5146         return status;
5147 }
5148
5149 /**
5150  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5151  * @hw: pointer to the hw struct
5152  * @seid: VSI seid
5153  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5154  * @cmd_details: pointer to command details structure or NULL
5155  **/
5156 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5157                         u16 seid,
5158                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5159                         struct i40e_asq_cmd_details *cmd_details)
5160 {
5161         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5162                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5163                                     cmd_details);
5164 }
5165
5166 /**
5167  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5168  * @hw: pointer to the hw struct
5169  * @seid: VSI seid
5170  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5171  * @cmd_details: pointer to command details structure or NULL
5172  **/
5173 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5174                         u16 seid,
5175                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5176                         struct i40e_asq_cmd_details *cmd_details)
5177 {
5178         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5179                                     i40e_aqc_opc_configure_vsi_tc_bw,
5180                                     cmd_details);
5181 }
5182
5183 /**
5184  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5185  * @hw: pointer to the hw struct
5186  * @seid: seid of the switching component connected to Physical Port
5187  * @ets_data: Buffer holding ETS parameters
5188  * @cmd_details: pointer to command details structure or NULL
5189  **/
5190 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5191                 u16 seid,
5192                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5193                 enum i40e_admin_queue_opc opcode,
5194                 struct i40e_asq_cmd_details *cmd_details)
5195 {
5196         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5197                                     sizeof(*ets_data), opcode, cmd_details);
5198 }
5199
5200 /**
5201  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5202  * @hw: pointer to the hw struct
5203  * @seid: seid of the switching component
5204  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5205  * @cmd_details: pointer to command details structure or NULL
5206  **/
5207 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5208         u16 seid,
5209         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5210         struct i40e_asq_cmd_details *cmd_details)
5211 {
5212         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5213                             i40e_aqc_opc_configure_switching_comp_bw_config,
5214                             cmd_details);
5215 }
5216
5217 /**
5218  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5219  * @hw: pointer to the hw struct
5220  * @seid: seid of the switching component
5221  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5222  * @cmd_details: pointer to command details structure or NULL
5223  **/
5224 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5225         struct i40e_hw *hw, u16 seid,
5226         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5227         struct i40e_asq_cmd_details *cmd_details)
5228 {
5229         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5230                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5231                             cmd_details);
5232 }
5233
5234 /**
5235  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5236  * @hw: pointer to the hw struct
5237  * @seid: seid of the VSI
5238  * @bw_data: Buffer to hold VSI BW configuration
5239  * @cmd_details: pointer to command details structure or NULL
5240  **/
5241 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5242                         u16 seid,
5243                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5244                         struct i40e_asq_cmd_details *cmd_details)
5245 {
5246         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5247                                     i40e_aqc_opc_query_vsi_bw_config,
5248                                     cmd_details);
5249 }
5250
5251 /**
5252  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5253  * @hw: pointer to the hw struct
5254  * @seid: seid of the VSI
5255  * @bw_data: Buffer to hold VSI BW configuration per TC
5256  * @cmd_details: pointer to command details structure or NULL
5257  **/
5258 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5259                         u16 seid,
5260                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5261                         struct i40e_asq_cmd_details *cmd_details)
5262 {
5263         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5264                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5265                                     cmd_details);
5266 }
5267
5268 /**
5269  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5270  * @hw: pointer to the hw struct
5271  * @seid: seid of the switching component
5272  * @bw_data: Buffer to hold switching component's per TC BW config
5273  * @cmd_details: pointer to command details structure or NULL
5274  **/
5275 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5276                 u16 seid,
5277                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5278                 struct i40e_asq_cmd_details *cmd_details)
5279 {
5280         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5281                                    i40e_aqc_opc_query_switching_comp_ets_config,
5282                                    cmd_details);
5283 }
5284
5285 /**
5286  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5287  * @hw: pointer to the hw struct
5288  * @seid: seid of the VSI or switching component connected to Physical Port
5289  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5290  * @cmd_details: pointer to command details structure or NULL
5291  **/
5292 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5293                         u16 seid,
5294                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5295                         struct i40e_asq_cmd_details *cmd_details)
5296 {
5297         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5298                                     i40e_aqc_opc_query_port_ets_config,
5299                                     cmd_details);
5300 }
5301
5302 /**
5303  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5304  * @hw: pointer to the hw struct
5305  * @seid: seid of the switching component
5306  * @bw_data: Buffer to hold switching component's BW configuration
5307  * @cmd_details: pointer to command details structure or NULL
5308  **/
5309 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5310                 u16 seid,
5311                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5312                 struct i40e_asq_cmd_details *cmd_details)
5313 {
5314         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5315                                     i40e_aqc_opc_query_switching_comp_bw_config,
5316                                     cmd_details);
5317 }
5318
5319 /**
5320  * i40e_validate_filter_settings
5321  * @hw: pointer to the hardware structure
5322  * @settings: Filter control settings
5323  *
5324  * Check and validate the filter control settings passed.
5325  * The function checks for the valid filter/context sizes being
5326  * passed for FCoE and PE.
5327  *
5328  * Returns I40E_SUCCESS if the values passed are valid and within
5329  * range else returns an error.
5330  **/
5331 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5332                                 struct i40e_filter_control_settings *settings)
5333 {
5334         u32 fcoe_cntx_size, fcoe_filt_size;
5335         u32 pe_cntx_size, pe_filt_size;
5336         u32 fcoe_fmax;
5337
5338         u32 val;
5339
5340         /* Validate FCoE settings passed */
5341         switch (settings->fcoe_filt_num) {
5342         case I40E_HASH_FILTER_SIZE_1K:
5343         case I40E_HASH_FILTER_SIZE_2K:
5344         case I40E_HASH_FILTER_SIZE_4K:
5345         case I40E_HASH_FILTER_SIZE_8K:
5346         case I40E_HASH_FILTER_SIZE_16K:
5347         case I40E_HASH_FILTER_SIZE_32K:
5348                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5349                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5350                 break;
5351         default:
5352                 return I40E_ERR_PARAM;
5353         }
5354
5355         switch (settings->fcoe_cntx_num) {
5356         case I40E_DMA_CNTX_SIZE_512:
5357         case I40E_DMA_CNTX_SIZE_1K:
5358         case I40E_DMA_CNTX_SIZE_2K:
5359         case I40E_DMA_CNTX_SIZE_4K:
5360                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5361                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5362                 break;
5363         default:
5364                 return I40E_ERR_PARAM;
5365         }
5366
5367         /* Validate PE settings passed */
5368         switch (settings->pe_filt_num) {
5369         case I40E_HASH_FILTER_SIZE_1K:
5370         case I40E_HASH_FILTER_SIZE_2K:
5371         case I40E_HASH_FILTER_SIZE_4K:
5372         case I40E_HASH_FILTER_SIZE_8K:
5373         case I40E_HASH_FILTER_SIZE_16K:
5374         case I40E_HASH_FILTER_SIZE_32K:
5375         case I40E_HASH_FILTER_SIZE_64K:
5376         case I40E_HASH_FILTER_SIZE_128K:
5377         case I40E_HASH_FILTER_SIZE_256K:
5378         case I40E_HASH_FILTER_SIZE_512K:
5379         case I40E_HASH_FILTER_SIZE_1M:
5380                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5381                 pe_filt_size <<= (u32)settings->pe_filt_num;
5382                 break;
5383         default:
5384                 return I40E_ERR_PARAM;
5385         }
5386
5387         switch (settings->pe_cntx_num) {
5388         case I40E_DMA_CNTX_SIZE_512:
5389         case I40E_DMA_CNTX_SIZE_1K:
5390         case I40E_DMA_CNTX_SIZE_2K:
5391         case I40E_DMA_CNTX_SIZE_4K:
5392         case I40E_DMA_CNTX_SIZE_8K:
5393         case I40E_DMA_CNTX_SIZE_16K:
5394         case I40E_DMA_CNTX_SIZE_32K:
5395         case I40E_DMA_CNTX_SIZE_64K:
5396         case I40E_DMA_CNTX_SIZE_128K:
5397         case I40E_DMA_CNTX_SIZE_256K:
5398                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5399                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5400                 break;
5401         default:
5402                 return I40E_ERR_PARAM;
5403         }
5404
5405         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5406         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5407         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5408                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5409         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5410                 return I40E_ERR_INVALID_SIZE;
5411
5412         return I40E_SUCCESS;
5413 }
5414
5415 /**
5416  * i40e_set_filter_control
5417  * @hw: pointer to the hardware structure
5418  * @settings: Filter control settings
5419  *
5420  * Set the Queue Filters for PE/FCoE and enable filters required
5421  * for a single PF. It is expected that these settings are programmed
5422  * at the driver initialization time.
5423  **/
5424 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5425                                 struct i40e_filter_control_settings *settings)
5426 {
5427         enum i40e_status_code ret = I40E_SUCCESS;
5428         u32 hash_lut_size = 0;
5429         u32 val;
5430
5431         if (!settings)
5432                 return I40E_ERR_PARAM;
5433
5434         /* Validate the input settings */
5435         ret = i40e_validate_filter_settings(hw, settings);
5436         if (ret)
5437                 return ret;
5438
5439         /* Read the PF Queue Filter control register */
5440         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5441
5442         /* Program required PE hash buckets for the PF */
5443         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5444         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5445                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5446         /* Program required PE contexts for the PF */
5447         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5448         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5449                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5450
5451         /* Program required FCoE hash buckets for the PF */
5452         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5453         val |= ((u32)settings->fcoe_filt_num <<
5454                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5455                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5456         /* Program required FCoE DDP contexts for the PF */
5457         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5458         val |= ((u32)settings->fcoe_cntx_num <<
5459                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5460                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5461
5462         /* Program Hash LUT size for the PF */
5463         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5464         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5465                 hash_lut_size = 1;
5466         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5467                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5468
5469         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5470         if (settings->enable_fdir)
5471                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5472         if (settings->enable_ethtype)
5473                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5474         if (settings->enable_macvlan)
5475                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5476
5477         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5478
5479         return I40E_SUCCESS;
5480 }
5481
5482 /**
5483  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5484  * @hw: pointer to the hw struct
5485  * @mac_addr: MAC address to use in the filter
5486  * @ethtype: Ethertype to use in the filter
5487  * @flags: Flags that needs to be applied to the filter
5488  * @vsi_seid: seid of the control VSI
5489  * @queue: VSI queue number to send the packet to
5490  * @is_add: Add control packet filter if True else remove
5491  * @stats: Structure to hold information on control filter counts
5492  * @cmd_details: pointer to command details structure or NULL
5493  *
5494  * This command will Add or Remove control packet filter for a control VSI.
5495  * In return it will update the total number of perfect filter count in
5496  * the stats member.
5497  **/
5498 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5499                                 u8 *mac_addr, u16 ethtype, u16 flags,
5500                                 u16 vsi_seid, u16 queue, bool is_add,
5501                                 struct i40e_control_filter_stats *stats,
5502                                 struct i40e_asq_cmd_details *cmd_details)
5503 {
5504         struct i40e_aq_desc desc;
5505         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5506                 (struct i40e_aqc_add_remove_control_packet_filter *)
5507                 &desc.params.raw;
5508         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5509                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5510                 &desc.params.raw;
5511         enum i40e_status_code status;
5512
5513         if (vsi_seid == 0)
5514                 return I40E_ERR_PARAM;
5515
5516         if (is_add) {
5517                 i40e_fill_default_direct_cmd_desc(&desc,
5518                                 i40e_aqc_opc_add_control_packet_filter);
5519                 cmd->queue = CPU_TO_LE16(queue);
5520         } else {
5521                 i40e_fill_default_direct_cmd_desc(&desc,
5522                                 i40e_aqc_opc_remove_control_packet_filter);
5523         }
5524
5525         if (mac_addr)
5526                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5527                             I40E_NONDMA_TO_NONDMA);
5528
5529         cmd->etype = CPU_TO_LE16(ethtype);
5530         cmd->flags = CPU_TO_LE16(flags);
5531         cmd->seid = CPU_TO_LE16(vsi_seid);
5532
5533         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5534
5535         if (!status && stats) {
5536                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5537                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5538                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5539                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5540         }
5541
5542         return status;
5543 }
5544
5545 /**
5546  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5547  * @hw: pointer to the hw struct
5548  * @seid: VSI seid to add ethertype filter from
5549  **/
5550 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5551 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5552                                                     u16 seid)
5553 {
5554         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5555                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5556                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5557         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5558         enum i40e_status_code status;
5559
5560         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5561                                                        seid, 0, true, NULL,
5562                                                        NULL);
5563         if (status)
5564                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5565 }
5566
5567 /**
5568  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5569  * @filters: list of cloud filters
5570  * @filter_count: length of list
5571  *
5572  * There's an issue in the device where the Geneve VNI layout needs
5573  * to be shifted 1 byte over from the VxLAN VNI
5574  **/
5575 STATIC void i40e_fix_up_geneve_vni(
5576         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5577         u8 filter_count)
5578 {
5579         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5580         int i;
5581
5582         for (i = 0; i < filter_count; i++) {
5583                 u16 tnl_type;
5584                 u32 ti;
5585
5586                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5587                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5588                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5589                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5590                         ti = LE32_TO_CPU(f[i].tenant_id);
5591                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5592                 }
5593         }
5594 }
5595
5596 /**
5597  * i40e_aq_add_cloud_filters
5598  * @hw: pointer to the hardware structure
5599  * @seid: VSI seid to add cloud filters from
5600  * @filters: Buffer which contains the filters to be added
5601  * @filter_count: number of filters contained in the buffer
5602  *
5603  * Set the cloud filters for a given VSI.  The contents of the
5604  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5605  * in by the caller of the function.
5606  *
5607  **/
5608 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5609         u16 seid,
5610         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5611         u8 filter_count)
5612 {
5613         struct i40e_aq_desc desc;
5614         struct i40e_aqc_add_remove_cloud_filters *cmd =
5615         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5616         enum i40e_status_code status;
5617         u16 buff_len;
5618
5619         i40e_fill_default_direct_cmd_desc(&desc,
5620                                           i40e_aqc_opc_add_cloud_filters);
5621
5622         buff_len = filter_count * sizeof(*filters);
5623         desc.datalen = CPU_TO_LE16(buff_len);
5624         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5625         cmd->num_filters = filter_count;
5626         cmd->seid = CPU_TO_LE16(seid);
5627
5628         i40e_fix_up_geneve_vni(filters, filter_count);
5629
5630         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5631
5632         return status;
5633 }
5634
5635 /**
5636  * i40e_aq_add_cloud_filters_big_buffer
5637  * @hw: pointer to the hardware structure
5638  * @seid: VSI seid to add cloud filters from
5639  * @filters: Buffer which contains the filters in big buffer to be added
5640  * @filter_count: number of filters contained in the buffer
5641  *
5642  * Set the cloud filters for a given VSI.  The contents of the
5643  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5644  * the function.
5645  *
5646  **/
5647 enum i40e_status_code i40e_aq_add_cloud_filters_big_buffer(struct i40e_hw *hw,
5648         u16 seid,
5649         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5650         u8 filter_count)
5651 {
5652         struct i40e_aq_desc desc;
5653         struct i40e_aqc_add_remove_cloud_filters *cmd =
5654         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5655         enum i40e_status_code status;
5656         u16 buff_len;
5657         int i;
5658
5659         i40e_fill_default_direct_cmd_desc(&desc,
5660                                           i40e_aqc_opc_add_cloud_filters);
5661
5662         buff_len = filter_count * sizeof(*filters);
5663         desc.datalen = CPU_TO_LE16(buff_len);
5664         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5665         cmd->num_filters = filter_count;
5666         cmd->seid = CPU_TO_LE16(seid);
5667         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5668
5669         /* adjust Geneve VNI for HW issue */
5670         for (i = 0; i < filter_count; i++) {
5671                 u16 tnl_type;
5672                 u32 ti;
5673
5674                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5675                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5676                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5677                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5678                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5679                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5680                 }
5681         }
5682
5683         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5684
5685         return status;
5686 }
5687
5688 /**
5689  * i40e_aq_remove_cloud_filters
5690  * @hw: pointer to the hardware structure
5691  * @seid: VSI seid to remove cloud filters from
5692  * @filters: Buffer which contains the filters to be removed
5693  * @filter_count: number of filters contained in the buffer
5694  *
5695  * Remove the cloud filters for a given VSI.  The contents of the
5696  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5697  * in by the caller of the function.
5698  *
5699  **/
5700 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5701         u16 seid,
5702         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5703         u8 filter_count)
5704 {
5705         struct i40e_aq_desc desc;
5706         struct i40e_aqc_add_remove_cloud_filters *cmd =
5707         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5708         enum i40e_status_code status;
5709         u16 buff_len;
5710
5711         i40e_fill_default_direct_cmd_desc(&desc,
5712                                           i40e_aqc_opc_remove_cloud_filters);
5713
5714         buff_len = filter_count * sizeof(*filters);
5715         desc.datalen = CPU_TO_LE16(buff_len);
5716         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5717         cmd->num_filters = filter_count;
5718         cmd->seid = CPU_TO_LE16(seid);
5719
5720         i40e_fix_up_geneve_vni(filters, filter_count);
5721
5722         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5723
5724         return status;
5725 }
5726
5727 /**
5728  * i40e_aq_remove_cloud_filters_big_buffer
5729  * @hw: pointer to the hardware structure
5730  * @seid: VSI seid to remove cloud filters from
5731  * @filters: Buffer which contains the filters in big buffer to be removed
5732  * @filter_count: number of filters contained in the buffer
5733  *
5734  * Remove the cloud filters for a given VSI.  The contents of the
5735  * i40e_aqc_add_rm_cloud_filt_elem_ext are filled in by the caller of
5736  * the function.
5737  *
5738  **/
5739 enum i40e_status_code i40e_aq_remove_cloud_filters_big_buffer(
5740         struct i40e_hw *hw,
5741         u16 seid,
5742         struct i40e_aqc_add_rm_cloud_filt_elem_ext *filters,
5743         u8 filter_count)
5744 {
5745         struct i40e_aq_desc desc;
5746         struct i40e_aqc_add_remove_cloud_filters *cmd =
5747         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5748         enum i40e_status_code status;
5749         u16 buff_len;
5750         int i;
5751
5752         i40e_fill_default_direct_cmd_desc(&desc,
5753                                           i40e_aqc_opc_remove_cloud_filters);
5754
5755         buff_len = filter_count * sizeof(*filters);
5756         desc.datalen = CPU_TO_LE16(buff_len);
5757         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5758         cmd->num_filters = filter_count;
5759         cmd->seid = CPU_TO_LE16(seid);
5760         cmd->big_buffer_flag = I40E_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER;
5761
5762         /* adjust Geneve VNI for HW issue */
5763         for (i = 0; i < filter_count; i++) {
5764                 u16 tnl_type;
5765                 u32 ti;
5766
5767                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5768                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5769                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5770                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5771                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5772                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5773                 }
5774         }
5775
5776         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5777
5778         return status;
5779 }
5780
5781 /**
5782  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5783  * @hw: pointer to the hw struct
5784  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5785  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5786  *
5787  **/
5788 enum
5789 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5790         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5791         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5792 {
5793         struct i40e_aq_desc desc;
5794         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5795                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5796         enum i40e_status_code status = I40E_SUCCESS;
5797         int i = 0;
5798
5799         i40e_fill_default_direct_cmd_desc(&desc,
5800                                           i40e_aqc_opc_replace_cloud_filters);
5801
5802         desc.datalen = CPU_TO_LE16(32);
5803         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5804         cmd->old_filter_type = filters->old_filter_type;
5805         cmd->new_filter_type = filters->new_filter_type;
5806         cmd->valid_flags = filters->valid_flags;
5807         cmd->tr_bit = filters->tr_bit;
5808
5809         status = i40e_asq_send_command(hw, &desc, cmd_buf,
5810                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
5811
5812         /* for get cloud filters command */
5813         for (i = 0; i < 32; i += 4) {
5814                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
5815                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
5816                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
5817                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
5818         }
5819
5820         return status;
5821 }
5822
5823
5824 /**
5825  * i40e_aq_alternate_write
5826  * @hw: pointer to the hardware structure
5827  * @reg_addr0: address of first dword to be read
5828  * @reg_val0: value to be written under 'reg_addr0'
5829  * @reg_addr1: address of second dword to be read
5830  * @reg_val1: value to be written under 'reg_addr1'
5831  *
5832  * Write one or two dwords to alternate structure. Fields are indicated
5833  * by 'reg_addr0' and 'reg_addr1' register numbers.
5834  *
5835  **/
5836 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5837                                 u32 reg_addr0, u32 reg_val0,
5838                                 u32 reg_addr1, u32 reg_val1)
5839 {
5840         struct i40e_aq_desc desc;
5841         struct i40e_aqc_alternate_write *cmd_resp =
5842                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5843         enum i40e_status_code status;
5844
5845         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5846         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5847         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5848         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5849         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5850
5851         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5852
5853         return status;
5854 }
5855
5856 /**
5857  * i40e_aq_alternate_write_indirect
5858  * @hw: pointer to the hardware structure
5859  * @addr: address of a first register to be modified
5860  * @dw_count: number of alternate structure fields to write
5861  * @buffer: pointer to the command buffer
5862  *
5863  * Write 'dw_count' dwords from 'buffer' to alternate structure
5864  * starting at 'addr'.
5865  *
5866  **/
5867 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5868                                 u32 addr, u32 dw_count, void *buffer)
5869 {
5870         struct i40e_aq_desc desc;
5871         struct i40e_aqc_alternate_ind_write *cmd_resp =
5872                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5873         enum i40e_status_code status;
5874
5875         if (buffer == NULL)
5876                 return I40E_ERR_PARAM;
5877
5878         /* Indirect command */
5879         i40e_fill_default_direct_cmd_desc(&desc,
5880                                          i40e_aqc_opc_alternate_write_indirect);
5881
5882         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5883         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5884         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5885                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5886
5887         cmd_resp->address = CPU_TO_LE32(addr);
5888         cmd_resp->length = CPU_TO_LE32(dw_count);
5889
5890         status = i40e_asq_send_command(hw, &desc, buffer,
5891                                        I40E_LO_DWORD(4*dw_count), NULL);
5892
5893         return status;
5894 }
5895
5896 /**
5897  * i40e_aq_alternate_read
5898  * @hw: pointer to the hardware structure
5899  * @reg_addr0: address of first dword to be read
5900  * @reg_val0: pointer for data read from 'reg_addr0'
5901  * @reg_addr1: address of second dword to be read
5902  * @reg_val1: pointer for data read from 'reg_addr1'
5903  *
5904  * Read one or two dwords from alternate structure. Fields are indicated
5905  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5906  * is not passed then only register at 'reg_addr0' is read.
5907  *
5908  **/
5909 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5910                                 u32 reg_addr0, u32 *reg_val0,
5911                                 u32 reg_addr1, u32 *reg_val1)
5912 {
5913         struct i40e_aq_desc desc;
5914         struct i40e_aqc_alternate_write *cmd_resp =
5915                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5916         enum i40e_status_code status;
5917
5918         if (reg_val0 == NULL)
5919                 return I40E_ERR_PARAM;
5920
5921         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5922         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5923         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5924
5925         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5926
5927         if (status == I40E_SUCCESS) {
5928                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5929
5930                 if (reg_val1 != NULL)
5931                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5932         }
5933
5934         return status;
5935 }
5936
5937 /**
5938  * i40e_aq_alternate_read_indirect
5939  * @hw: pointer to the hardware structure
5940  * @addr: address of the alternate structure field
5941  * @dw_count: number of alternate structure fields to read
5942  * @buffer: pointer to the command buffer
5943  *
5944  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5945  * place them in 'buffer'. The buffer should be allocated by caller.
5946  *
5947  **/
5948 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5949                                 u32 addr, u32 dw_count, void *buffer)
5950 {
5951         struct i40e_aq_desc desc;
5952         struct i40e_aqc_alternate_ind_write *cmd_resp =
5953                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5954         enum i40e_status_code status;
5955
5956         if (buffer == NULL)
5957                 return I40E_ERR_PARAM;
5958
5959         /* Indirect command */
5960         i40e_fill_default_direct_cmd_desc(&desc,
5961                 i40e_aqc_opc_alternate_read_indirect);
5962
5963         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5964         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5965         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5966                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5967
5968         cmd_resp->address = CPU_TO_LE32(addr);
5969         cmd_resp->length = CPU_TO_LE32(dw_count);
5970
5971         status = i40e_asq_send_command(hw, &desc, buffer,
5972                                        I40E_LO_DWORD(4*dw_count), NULL);
5973
5974         return status;
5975 }
5976
5977 /**
5978  *  i40e_aq_alternate_clear
5979  *  @hw: pointer to the HW structure.
5980  *
5981  *  Clear the alternate structures of the port from which the function
5982  *  is called.
5983  *
5984  **/
5985 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5986 {
5987         struct i40e_aq_desc desc;
5988         enum i40e_status_code status;
5989
5990         i40e_fill_default_direct_cmd_desc(&desc,
5991                                           i40e_aqc_opc_alternate_clear_port);
5992
5993         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5994
5995         return status;
5996 }
5997
5998 /**
5999  *  i40e_aq_alternate_write_done
6000  *  @hw: pointer to the HW structure.
6001  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6002  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6003  *
6004  *  Indicates to the FW that alternate structures have been changed.
6005  *
6006  **/
6007 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6008                 u8 bios_mode, bool *reset_needed)
6009 {
6010         struct i40e_aq_desc desc;
6011         struct i40e_aqc_alternate_write_done *cmd =
6012                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6013         enum i40e_status_code status;
6014
6015         if (reset_needed == NULL)
6016                 return I40E_ERR_PARAM;
6017
6018         i40e_fill_default_direct_cmd_desc(&desc,
6019                                           i40e_aqc_opc_alternate_write_done);
6020
6021         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6022
6023         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6024         if (!status && reset_needed)
6025                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6026                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6027
6028         return status;
6029 }
6030
6031 /**
6032  *  i40e_aq_set_oem_mode
6033  *  @hw: pointer to the HW structure.
6034  *  @oem_mode: the OEM mode to be used
6035  *
6036  *  Sets the device to a specific operating mode. Currently the only supported
6037  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6038  *
6039  **/
6040 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6041                 u8 oem_mode)
6042 {
6043         struct i40e_aq_desc desc;
6044         struct i40e_aqc_alternate_write_done *cmd =
6045                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6046         enum i40e_status_code status;
6047
6048         i40e_fill_default_direct_cmd_desc(&desc,
6049                                           i40e_aqc_opc_alternate_set_mode);
6050
6051         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6052
6053         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6054
6055         return status;
6056 }
6057
6058 /**
6059  * i40e_aq_resume_port_tx
6060  * @hw: pointer to the hardware structure
6061  * @cmd_details: pointer to command details structure or NULL
6062  *
6063  * Resume port's Tx traffic
6064  **/
6065 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6066                                 struct i40e_asq_cmd_details *cmd_details)
6067 {
6068         struct i40e_aq_desc desc;
6069         enum i40e_status_code status;
6070
6071         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6072
6073         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6074
6075         return status;
6076 }
6077
6078 /**
6079  * i40e_set_pci_config_data - store PCI bus info
6080  * @hw: pointer to hardware structure
6081  * @link_status: the link status word from PCI config space
6082  *
6083  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6084  **/
6085 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6086 {
6087         hw->bus.type = i40e_bus_type_pci_express;
6088
6089         switch (link_status & I40E_PCI_LINK_WIDTH) {
6090         case I40E_PCI_LINK_WIDTH_1:
6091                 hw->bus.width = i40e_bus_width_pcie_x1;
6092                 break;
6093         case I40E_PCI_LINK_WIDTH_2:
6094                 hw->bus.width = i40e_bus_width_pcie_x2;
6095                 break;
6096         case I40E_PCI_LINK_WIDTH_4:
6097                 hw->bus.width = i40e_bus_width_pcie_x4;
6098                 break;
6099         case I40E_PCI_LINK_WIDTH_8:
6100                 hw->bus.width = i40e_bus_width_pcie_x8;
6101                 break;
6102         default:
6103                 hw->bus.width = i40e_bus_width_unknown;
6104                 break;
6105         }
6106
6107         switch (link_status & I40E_PCI_LINK_SPEED) {
6108         case I40E_PCI_LINK_SPEED_2500:
6109                 hw->bus.speed = i40e_bus_speed_2500;
6110                 break;
6111         case I40E_PCI_LINK_SPEED_5000:
6112                 hw->bus.speed = i40e_bus_speed_5000;
6113                 break;
6114         case I40E_PCI_LINK_SPEED_8000:
6115                 hw->bus.speed = i40e_bus_speed_8000;
6116                 break;
6117         default:
6118                 hw->bus.speed = i40e_bus_speed_unknown;
6119                 break;
6120         }
6121 }
6122
6123 /**
6124  * i40e_aq_debug_dump
6125  * @hw: pointer to the hardware structure
6126  * @cluster_id: specific cluster to dump
6127  * @table_id: table id within cluster
6128  * @start_index: index of line in the block to read
6129  * @buff_size: dump buffer size
6130  * @buff: dump buffer
6131  * @ret_buff_size: actual buffer size returned
6132  * @ret_next_table: next block to read
6133  * @ret_next_index: next index to read
6134  *
6135  * Dump internal FW/HW data for debug purposes.
6136  *
6137  **/
6138 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6139                                 u8 table_id, u32 start_index, u16 buff_size,
6140                                 void *buff, u16 *ret_buff_size,
6141                                 u8 *ret_next_table, u32 *ret_next_index,
6142                                 struct i40e_asq_cmd_details *cmd_details)
6143 {
6144         struct i40e_aq_desc desc;
6145         struct i40e_aqc_debug_dump_internals *cmd =
6146                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6147         struct i40e_aqc_debug_dump_internals *resp =
6148                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6149         enum i40e_status_code status;
6150
6151         if (buff_size == 0 || !buff)
6152                 return I40E_ERR_PARAM;
6153
6154         i40e_fill_default_direct_cmd_desc(&desc,
6155                                           i40e_aqc_opc_debug_dump_internals);
6156         /* Indirect Command */
6157         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6158         if (buff_size > I40E_AQ_LARGE_BUF)
6159                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6160
6161         cmd->cluster_id = cluster_id;
6162         cmd->table_id = table_id;
6163         cmd->idx = CPU_TO_LE32(start_index);
6164
6165         desc.datalen = CPU_TO_LE16(buff_size);
6166
6167         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6168         if (!status) {
6169                 if (ret_buff_size != NULL)
6170                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6171                 if (ret_next_table != NULL)
6172                         *ret_next_table = resp->table_id;
6173                 if (ret_next_index != NULL)
6174                         *ret_next_index = LE32_TO_CPU(resp->idx);
6175         }
6176
6177         return status;
6178 }
6179
6180 /**
6181  * i40e_read_bw_from_alt_ram
6182  * @hw: pointer to the hardware structure
6183  * @max_bw: pointer for max_bw read
6184  * @min_bw: pointer for min_bw read
6185  * @min_valid: pointer for bool that is true if min_bw is a valid value
6186  * @max_valid: pointer for bool that is true if max_bw is a valid value
6187  *
6188  * Read bw from the alternate ram for the given pf
6189  **/
6190 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6191                                         u32 *max_bw, u32 *min_bw,
6192                                         bool *min_valid, bool *max_valid)
6193 {
6194         enum i40e_status_code status;
6195         u32 max_bw_addr, min_bw_addr;
6196
6197         /* Calculate the address of the min/max bw registers */
6198         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6199                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6200                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6201         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6202                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6203                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6204
6205         /* Read the bandwidths from alt ram */
6206         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6207                                         min_bw_addr, min_bw);
6208
6209         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6210                 *min_valid = true;
6211         else
6212                 *min_valid = false;
6213
6214         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6215                 *max_valid = true;
6216         else
6217                 *max_valid = false;
6218
6219         return status;
6220 }
6221
6222 /**
6223  * i40e_aq_configure_partition_bw
6224  * @hw: pointer to the hardware structure
6225  * @bw_data: Buffer holding valid pfs and bw limits
6226  * @cmd_details: pointer to command details
6227  *
6228  * Configure partitions guaranteed/max bw
6229  **/
6230 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6231                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6232                         struct i40e_asq_cmd_details *cmd_details)
6233 {
6234         enum i40e_status_code status;
6235         struct i40e_aq_desc desc;
6236         u16 bwd_size = sizeof(*bw_data);
6237
6238         i40e_fill_default_direct_cmd_desc(&desc,
6239                                 i40e_aqc_opc_configure_partition_bw);
6240
6241         /* Indirect command */
6242         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6243         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6244
6245         desc.datalen = CPU_TO_LE16(bwd_size);
6246
6247         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6248
6249         return status;
6250 }
6251
6252 /**
6253  * i40e_read_phy_register_clause22
6254  * @hw: pointer to the HW structure
6255  * @reg: register address in the page
6256  * @phy_adr: PHY address on MDIO interface
6257  * @value: PHY register value
6258  *
6259  * Reads specified PHY register value
6260  **/
6261 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6262                                         u16 reg, u8 phy_addr, u16 *value)
6263 {
6264         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6265         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6266         u32 command = 0;
6267         u16 retry = 1000;
6268
6269         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6270                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6271                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6272                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6273                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6274         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6275         do {
6276                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6277                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6278                         status = I40E_SUCCESS;
6279                         break;
6280                 }
6281                 i40e_usec_delay(10);
6282                 retry--;
6283         } while (retry);
6284
6285         if (status) {
6286                 i40e_debug(hw, I40E_DEBUG_PHY,
6287                            "PHY: Can't write command to external PHY.\n");
6288         } else {
6289                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6290                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6291                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6292         }
6293
6294         return status;
6295 }
6296
6297 /**
6298  * i40e_write_phy_register_clause22
6299  * @hw: pointer to the HW structure
6300  * @reg: register address in the page
6301  * @phy_adr: PHY address on MDIO interface
6302  * @value: PHY register value
6303  *
6304  * Writes specified PHY register value
6305  **/
6306 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6307                                         u16 reg, u8 phy_addr, u16 value)
6308 {
6309         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6310         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6311         u32 command  = 0;
6312         u16 retry = 1000;
6313
6314         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6315         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6316
6317         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6318                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6319                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6320                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6321                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6322
6323         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6324         do {
6325                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6326                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6327                         status = I40E_SUCCESS;
6328                         break;
6329                 }
6330                 i40e_usec_delay(10);
6331                 retry--;
6332         } while (retry);
6333
6334         return status;
6335 }
6336
6337 /**
6338  * i40e_read_phy_register_clause45
6339  * @hw: pointer to the HW structure
6340  * @page: registers page number
6341  * @reg: register address in the page
6342  * @phy_adr: PHY address on MDIO interface
6343  * @value: PHY register value
6344  *
6345  * Reads specified PHY register value
6346  **/
6347 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6348                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6349 {
6350         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6351         u32 command  = 0;
6352         u16 retry = 1000;
6353         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6354
6355         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6356                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6357                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6358                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6359                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6360                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6361                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6362         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6363         do {
6364                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6365                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6366                         status = I40E_SUCCESS;
6367                         break;
6368                 }
6369                 i40e_usec_delay(10);
6370                 retry--;
6371         } while (retry);
6372
6373         if (status) {
6374                 i40e_debug(hw, I40E_DEBUG_PHY,
6375                            "PHY: Can't write command to external PHY.\n");
6376                 goto phy_read_end;
6377         }
6378
6379         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6380                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6381                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6382                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6383                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6384                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6385         status = I40E_ERR_TIMEOUT;
6386         retry = 1000;
6387         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6388         do {
6389                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6390                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6391                         status = I40E_SUCCESS;
6392                         break;
6393                 }
6394                 i40e_usec_delay(10);
6395                 retry--;
6396         } while (retry);
6397
6398         if (!status) {
6399                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6400                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6401                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6402         } else {
6403                 i40e_debug(hw, I40E_DEBUG_PHY,
6404                            "PHY: Can't read register value from external PHY.\n");
6405         }
6406
6407 phy_read_end:
6408         return status;
6409 }
6410
6411 /**
6412  * i40e_write_phy_register_clause45
6413  * @hw: pointer to the HW structure
6414  * @page: registers page number
6415  * @reg: register address in the page
6416  * @phy_adr: PHY address on MDIO interface
6417  * @value: PHY register value
6418  *
6419  * Writes value to specified PHY register
6420  **/
6421 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6422                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6423 {
6424         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6425         u32 command  = 0;
6426         u16 retry = 1000;
6427         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6428
6429         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6430                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6431                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6432                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6433                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6434                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6435                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6436         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6437         do {
6438                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6439                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6440                         status = I40E_SUCCESS;
6441                         break;
6442                 }
6443                 i40e_usec_delay(10);
6444                 retry--;
6445         } while (retry);
6446         if (status) {
6447                 i40e_debug(hw, I40E_DEBUG_PHY,
6448                            "PHY: Can't write command to external PHY.\n");
6449                 goto phy_write_end;
6450         }
6451
6452         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6453         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6454
6455         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6456                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6457                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6458                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6459                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6460                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6461         status = I40E_ERR_TIMEOUT;
6462         retry = 1000;
6463         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6464         do {
6465                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6466                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6467                         status = I40E_SUCCESS;
6468                         break;
6469                 }
6470                 i40e_usec_delay(10);
6471                 retry--;
6472         } while (retry);
6473
6474 phy_write_end:
6475         return status;
6476 }
6477
6478 /**
6479  * i40e_write_phy_register
6480  * @hw: pointer to the HW structure
6481  * @page: registers page number
6482  * @reg: register address in the page
6483  * @phy_adr: PHY address on MDIO interface
6484  * @value: PHY register value
6485  *
6486  * Writes value to specified PHY register
6487  **/
6488 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6489                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6490 {
6491         enum i40e_status_code status;
6492
6493         switch (hw->device_id) {
6494         case I40E_DEV_ID_1G_BASE_T_X722:
6495                 status = i40e_write_phy_register_clause22(hw,
6496                         reg, phy_addr, value);
6497                 break;
6498         case I40E_DEV_ID_10G_BASE_T:
6499         case I40E_DEV_ID_10G_BASE_T4:
6500         case I40E_DEV_ID_10G_BASE_T_X722:
6501         case I40E_DEV_ID_25G_B:
6502         case I40E_DEV_ID_25G_SFP28:
6503                 status = i40e_write_phy_register_clause45(hw,
6504                         page, reg, phy_addr, value);
6505                 break;
6506         default:
6507                 status = I40E_ERR_UNKNOWN_PHY;
6508                 break;
6509         }
6510
6511         return status;
6512 }
6513
6514 /**
6515  * i40e_read_phy_register
6516  * @hw: pointer to the HW structure
6517  * @page: registers page number
6518  * @reg: register address in the page
6519  * @phy_adr: PHY address on MDIO interface
6520  * @value: PHY register value
6521  *
6522  * Reads specified PHY register value
6523  **/
6524 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6525                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6526 {
6527         enum i40e_status_code status;
6528
6529         switch (hw->device_id) {
6530         case I40E_DEV_ID_1G_BASE_T_X722:
6531                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6532                                                          value);
6533                 break;
6534         case I40E_DEV_ID_10G_BASE_T:
6535         case I40E_DEV_ID_10G_BASE_T4:
6536         case I40E_DEV_ID_10G_BASE_T_X722:
6537         case I40E_DEV_ID_25G_B:
6538         case I40E_DEV_ID_25G_SFP28:
6539                 status = i40e_read_phy_register_clause45(hw, page, reg,
6540                                                          phy_addr, value);
6541                 break;
6542         default:
6543                 status = I40E_ERR_UNKNOWN_PHY;
6544                 break;
6545         }
6546
6547         return status;
6548 }
6549
6550 /**
6551  * i40e_get_phy_address
6552  * @hw: pointer to the HW structure
6553  * @dev_num: PHY port num that address we want
6554  * @phy_addr: Returned PHY address
6555  *
6556  * Gets PHY address for current port
6557  **/
6558 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6559 {
6560         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6561         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6562
6563         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6564 }
6565
6566 /**
6567  * i40e_blink_phy_led
6568  * @hw: pointer to the HW structure
6569  * @time: time how long led will blinks in secs
6570  * @interval: gap between LED on and off in msecs
6571  *
6572  * Blinks PHY link LED
6573  **/
6574 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6575                                               u32 time, u32 interval)
6576 {
6577         enum i40e_status_code status = I40E_SUCCESS;
6578         u32 i;
6579         u16 led_ctl = 0;
6580         u16 gpio_led_port;
6581         u16 led_reg;
6582         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6583         u8 phy_addr = 0;
6584         u8 port_num;
6585
6586         i = rd32(hw, I40E_PFGEN_PORTNUM);
6587         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6588         phy_addr = i40e_get_phy_address(hw, port_num);
6589
6590         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6591              led_addr++) {
6592                 status = i40e_read_phy_register_clause45(hw,
6593                                                          I40E_PHY_COM_REG_PAGE,
6594                                                          led_addr, phy_addr,
6595                                                          &led_reg);
6596                 if (status)
6597                         goto phy_blinking_end;
6598                 led_ctl = led_reg;
6599                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6600                         led_reg = 0;
6601                         status = i40e_write_phy_register_clause45(hw,
6602                                                          I40E_PHY_COM_REG_PAGE,
6603                                                          led_addr, phy_addr,
6604                                                          led_reg);
6605                         if (status)
6606                                 goto phy_blinking_end;
6607                         break;
6608                 }
6609         }
6610
6611         if (time > 0 && interval > 0) {
6612                 for (i = 0; i < time * 1000; i += interval) {
6613                         status = i40e_read_phy_register_clause45(hw,
6614                                                 I40E_PHY_COM_REG_PAGE,
6615                                                 led_addr, phy_addr, &led_reg);
6616                         if (status)
6617                                 goto restore_config;
6618                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6619                                 led_reg = 0;
6620                         else
6621                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6622                         status = i40e_write_phy_register_clause45(hw,
6623                                                 I40E_PHY_COM_REG_PAGE,
6624                                                 led_addr, phy_addr, led_reg);
6625                         if (status)
6626                                 goto restore_config;
6627                         i40e_msec_delay(interval);
6628                 }
6629         }
6630
6631 restore_config:
6632         status = i40e_write_phy_register_clause45(hw,
6633                                                   I40E_PHY_COM_REG_PAGE,
6634                                                   led_addr, phy_addr, led_ctl);
6635
6636 phy_blinking_end:
6637         return status;
6638 }
6639
6640 /**
6641  * i40e_led_get_phy - return current on/off mode
6642  * @hw: pointer to the hw struct
6643  * @led_addr: address of led register to use
6644  * @val: original value of register to use
6645  *
6646  **/
6647 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6648                                        u16 *val)
6649 {
6650         enum i40e_status_code status = I40E_SUCCESS;
6651         u16 gpio_led_port;
6652         u8 phy_addr = 0;
6653         u16 reg_val;
6654         u16 temp_addr;
6655         u8 port_num;
6656         u32 i;
6657
6658         temp_addr = I40E_PHY_LED_PROV_REG_1;
6659         i = rd32(hw, I40E_PFGEN_PORTNUM);
6660         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6661         phy_addr = i40e_get_phy_address(hw, port_num);
6662
6663         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6664              temp_addr++) {
6665                 status = i40e_read_phy_register_clause45(hw,
6666                                                          I40E_PHY_COM_REG_PAGE,
6667                                                          temp_addr, phy_addr,
6668                                                          &reg_val);
6669                 if (status)
6670                         return status;
6671                 *val = reg_val;
6672                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6673                         *led_addr = temp_addr;
6674                         break;
6675                 }
6676         }
6677         return status;
6678 }
6679
6680 /**
6681  * i40e_led_set_phy
6682  * @hw: pointer to the HW structure
6683  * @on: true or false
6684  * @mode: original val plus bit for set or ignore
6685  * Set led's on or off when controlled by the PHY
6686  *
6687  **/
6688 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6689                                        u16 led_addr, u32 mode)
6690 {
6691         enum i40e_status_code status = I40E_SUCCESS;
6692         u16 led_ctl = 0;
6693         u16 led_reg = 0;
6694         u8 phy_addr = 0;
6695         u8 port_num;
6696         u32 i;
6697
6698         i = rd32(hw, I40E_PFGEN_PORTNUM);
6699         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6700         phy_addr = i40e_get_phy_address(hw, port_num);
6701         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6702                                                  led_addr, phy_addr, &led_reg);
6703         if (status)
6704                 return status;
6705         led_ctl = led_reg;
6706         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6707                 led_reg = 0;
6708                 status = i40e_write_phy_register_clause45(hw,
6709                                                           I40E_PHY_COM_REG_PAGE,
6710                                                           led_addr, phy_addr,
6711                                                           led_reg);
6712                 if (status)
6713                         return status;
6714         }
6715         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6716                                                  led_addr, phy_addr, &led_reg);
6717         if (status)
6718                 goto restore_config;
6719         if (on)
6720                 led_reg = I40E_PHY_LED_MANUAL_ON;
6721         else
6722                 led_reg = 0;
6723         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6724                                                   led_addr, phy_addr, led_reg);
6725         if (status)
6726                 goto restore_config;
6727         if (mode & I40E_PHY_LED_MODE_ORIG) {
6728                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6729                 status = i40e_write_phy_register_clause45(hw,
6730                                                  I40E_PHY_COM_REG_PAGE,
6731                                                  led_addr, phy_addr, led_ctl);
6732         }
6733         return status;
6734 restore_config:
6735         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
6736                                                   led_addr, phy_addr, led_ctl);
6737         return status;
6738 }
6739 #endif /* PF_DRIVER */
6740
6741 /**
6742  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6743  * @hw: pointer to the hw struct
6744  * @reg_addr: register address
6745  * @reg_val: ptr to register value
6746  * @cmd_details: pointer to command details structure or NULL
6747  *
6748  * Use the firmware to read the Rx control register,
6749  * especially useful if the Rx unit is under heavy pressure
6750  **/
6751 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6752                                 u32 reg_addr, u32 *reg_val,
6753                                 struct i40e_asq_cmd_details *cmd_details)
6754 {
6755         struct i40e_aq_desc desc;
6756         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6757                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6758         enum i40e_status_code status;
6759
6760         if (reg_val == NULL)
6761                 return I40E_ERR_PARAM;
6762
6763         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6764
6765         cmd_resp->address = CPU_TO_LE32(reg_addr);
6766
6767         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6768
6769         if (status == I40E_SUCCESS)
6770                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6771
6772         return status;
6773 }
6774
6775 /**
6776  * i40e_read_rx_ctl - read from an Rx control register
6777  * @hw: pointer to the hw struct
6778  * @reg_addr: register address
6779  **/
6780 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6781 {
6782         enum i40e_status_code status = I40E_SUCCESS;
6783         bool use_register;
6784         int retry = 5;
6785         u32 val = 0;
6786
6787         use_register = (((hw->aq.api_maj_ver == 1) &&
6788                         (hw->aq.api_min_ver < 5)) ||
6789                         (hw->mac.type == I40E_MAC_X722));
6790         if (!use_register) {
6791 do_retry:
6792                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6793                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6794                         i40e_msec_delay(1);
6795                         retry--;
6796                         goto do_retry;
6797                 }
6798         }
6799
6800         /* if the AQ access failed, try the old-fashioned way */
6801         if (status || use_register)
6802                 val = rd32(hw, reg_addr);
6803
6804         return val;
6805 }
6806
6807 /**
6808  * i40e_aq_rx_ctl_write_register
6809  * @hw: pointer to the hw struct
6810  * @reg_addr: register address
6811  * @reg_val: register value
6812  * @cmd_details: pointer to command details structure or NULL
6813  *
6814  * Use the firmware to write to an Rx control register,
6815  * especially useful if the Rx unit is under heavy pressure
6816  **/
6817 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6818                                 u32 reg_addr, u32 reg_val,
6819                                 struct i40e_asq_cmd_details *cmd_details)
6820 {
6821         struct i40e_aq_desc desc;
6822         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6823                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6824         enum i40e_status_code status;
6825
6826         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6827
6828         cmd->address = CPU_TO_LE32(reg_addr);
6829         cmd->value = CPU_TO_LE32(reg_val);
6830
6831         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6832
6833         return status;
6834 }
6835
6836 /**
6837  * i40e_write_rx_ctl - write to an Rx control register
6838  * @hw: pointer to the hw struct
6839  * @reg_addr: register address
6840  * @reg_val: register value
6841  **/
6842 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6843 {
6844         enum i40e_status_code status = I40E_SUCCESS;
6845         bool use_register;
6846         int retry = 5;
6847
6848         use_register = (((hw->aq.api_maj_ver == 1) &&
6849                         (hw->aq.api_min_ver < 5)) ||
6850                         (hw->mac.type == I40E_MAC_X722));
6851         if (!use_register) {
6852 do_retry:
6853                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6854                                                        reg_val, NULL);
6855                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6856                         i40e_msec_delay(1);
6857                         retry--;
6858                         goto do_retry;
6859                 }
6860         }
6861
6862         /* if the AQ access failed, try the old-fashioned way */
6863         if (status || use_register)
6864                 wr32(hw, reg_addr, reg_val);
6865 }
6866 #ifdef VF_DRIVER
6867
6868 /**
6869  * i40e_aq_send_msg_to_pf
6870  * @hw: pointer to the hardware structure
6871  * @v_opcode: opcodes for VF-PF communication
6872  * @v_retval: return error code
6873  * @msg: pointer to the msg buffer
6874  * @msglen: msg length
6875  * @cmd_details: pointer to command details
6876  *
6877  * Send message to PF driver using admin queue. By default, this message
6878  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6879  * completion before returning.
6880  **/
6881 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6882                                 enum i40e_virtchnl_ops v_opcode,
6883                                 enum i40e_status_code v_retval,
6884                                 u8 *msg, u16 msglen,
6885                                 struct i40e_asq_cmd_details *cmd_details)
6886 {
6887         struct i40e_aq_desc desc;
6888         struct i40e_asq_cmd_details details;
6889         enum i40e_status_code status;
6890
6891         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6892         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6893         desc.cookie_high = CPU_TO_LE32(v_opcode);
6894         desc.cookie_low = CPU_TO_LE32(v_retval);
6895         if (msglen) {
6896                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6897                                                 | I40E_AQ_FLAG_RD));
6898                 if (msglen > I40E_AQ_LARGE_BUF)
6899                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6900                 desc.datalen = CPU_TO_LE16(msglen);
6901         }
6902         if (!cmd_details) {
6903                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6904                 details.async = true;
6905                 cmd_details = &details;
6906         }
6907         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6908                                        msglen, cmd_details);
6909         return status;
6910 }
6911
6912 /**
6913  * i40e_vf_parse_hw_config
6914  * @hw: pointer to the hardware structure
6915  * @msg: pointer to the virtual channel VF resource structure
6916  *
6917  * Given a VF resource message from the PF, populate the hw struct
6918  * with appropriate information.
6919  **/
6920 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6921                              struct i40e_virtchnl_vf_resource *msg)
6922 {
6923         struct i40e_virtchnl_vsi_resource *vsi_res;
6924         int i;
6925
6926         vsi_res = &msg->vsi_res[0];
6927
6928         hw->dev_caps.num_vsis = msg->num_vsis;
6929         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6930         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6931         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6932         hw->dev_caps.dcb = msg->vf_offload_flags &
6933                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6934         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6935                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6936         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6937                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6938         for (i = 0; i < msg->num_vsis; i++) {
6939                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6940                         i40e_memcpy(hw->mac.perm_addr,
6941                                     vsi_res->default_mac_addr,
6942                                     I40E_ETH_LENGTH_OF_ADDRESS,
6943                                     I40E_NONDMA_TO_NONDMA);
6944                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6945                                     I40E_ETH_LENGTH_OF_ADDRESS,
6946                                     I40E_NONDMA_TO_NONDMA);
6947                 }
6948                 vsi_res++;
6949         }
6950 }
6951
6952 /**
6953  * i40e_vf_reset
6954  * @hw: pointer to the hardware structure
6955  *
6956  * Send a VF_RESET message to the PF. Does not wait for response from PF
6957  * as none will be forthcoming. Immediately after calling this function,
6958  * the admin queue should be shut down and (optionally) reinitialized.
6959  **/
6960 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6961 {
6962         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6963                                       I40E_SUCCESS, NULL, 0, NULL);
6964 }
6965 #endif /* VF_DRIVER */
6966
6967 /**
6968  * i40e_aq_set_arp_proxy_config
6969  * @hw: pointer to the HW structure
6970  * @proxy_config - pointer to proxy config command table struct
6971  * @cmd_details: pointer to command details
6972  *
6973  * Set ARP offload parameters from pre-populated
6974  * i40e_aqc_arp_proxy_data struct
6975  **/
6976 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6977                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6978                                 struct i40e_asq_cmd_details *cmd_details)
6979 {
6980         struct i40e_aq_desc desc;
6981         enum i40e_status_code status;
6982
6983         if (!proxy_config)
6984                 return I40E_ERR_PARAM;
6985
6986         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6987
6988         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6989         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6990         desc.params.external.addr_high =
6991                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6992         desc.params.external.addr_low =
6993                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6994         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
6995
6996         status = i40e_asq_send_command(hw, &desc, proxy_config,
6997                                        sizeof(struct i40e_aqc_arp_proxy_data),
6998                                        cmd_details);
6999
7000         return status;
7001 }
7002
7003 /**
7004  * i40e_aq_opc_set_ns_proxy_table_entry
7005  * @hw: pointer to the HW structure
7006  * @ns_proxy_table_entry: pointer to NS table entry command struct
7007  * @cmd_details: pointer to command details
7008  *
7009  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7010  * from pre-populated i40e_aqc_ns_proxy_data struct
7011  **/
7012 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7013                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7014                         struct i40e_asq_cmd_details *cmd_details)
7015 {
7016         struct i40e_aq_desc desc;
7017         enum i40e_status_code status;
7018
7019         if (!ns_proxy_table_entry)
7020                 return I40E_ERR_PARAM;
7021
7022         i40e_fill_default_direct_cmd_desc(&desc,
7023                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7024
7025         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7026         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7027         desc.params.external.addr_high =
7028                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7029         desc.params.external.addr_low =
7030                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7031         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7032
7033         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7034                                        sizeof(struct i40e_aqc_ns_proxy_data),
7035                                        cmd_details);
7036
7037         return status;
7038 }
7039
7040 /**
7041  * i40e_aq_set_clear_wol_filter
7042  * @hw: pointer to the hw struct
7043  * @filter_index: index of filter to modify (0-7)
7044  * @filter: buffer containing filter to be set
7045  * @set_filter: true to set filter, false to clear filter
7046  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7047  *              if false, pass through packets may cause wake-up
7048  * @filter_valid: true if filter action is valid
7049  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7050  * @cmd_details: pointer to command details structure or NULL
7051  *
7052  * Set or clear WoL filter for port attached to the PF
7053  **/
7054 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7055                                 u8 filter_index,
7056                                 struct i40e_aqc_set_wol_filter_data *filter,
7057                                 bool set_filter, bool no_wol_tco,
7058                                 bool filter_valid, bool no_wol_tco_valid,
7059                                 struct i40e_asq_cmd_details *cmd_details)
7060 {
7061         struct i40e_aq_desc desc;
7062         struct i40e_aqc_set_wol_filter *cmd =
7063                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7064         enum i40e_status_code status;
7065         u16 cmd_flags = 0;
7066         u16 valid_flags = 0;
7067         u16 buff_len = 0;
7068
7069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7070
7071         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7072                 return  I40E_ERR_PARAM;
7073         cmd->filter_index = CPU_TO_LE16(filter_index);
7074
7075         if (set_filter) {
7076                 if (!filter)
7077                         return  I40E_ERR_PARAM;
7078
7079                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7080                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7081         }
7082
7083         if (no_wol_tco)
7084                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7085         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7086
7087         if (filter_valid)
7088                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7089         if (no_wol_tco_valid)
7090                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7091         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7092
7093         buff_len = sizeof(*filter);
7094         desc.datalen = CPU_TO_LE16(buff_len);
7095
7096         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7097         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7098
7099         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7100         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7101
7102         status = i40e_asq_send_command(hw, &desc, filter,
7103                                        buff_len, cmd_details);
7104
7105         return status;
7106 }
7107
7108 /**
7109  * i40e_aq_get_wake_event_reason
7110  * @hw: pointer to the hw struct
7111  * @wake_reason: return value, index of matching filter
7112  * @cmd_details: pointer to command details structure or NULL
7113  *
7114  * Get information for the reason of a Wake Up event
7115  **/
7116 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7117                                 u16 *wake_reason,
7118                                 struct i40e_asq_cmd_details *cmd_details)
7119 {
7120         struct i40e_aq_desc desc;
7121         struct i40e_aqc_get_wake_reason_completion *resp =
7122                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7123         enum i40e_status_code status;
7124
7125         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7126
7127         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7128
7129         if (status == I40E_SUCCESS)
7130                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7131
7132         return status;
7133 }
7134
7135 /**
7136 * i40e_aq_clear_all_wol_filters
7137 * @hw: pointer to the hw struct
7138 * @cmd_details: pointer to command details structure or NULL
7139 *
7140 * Get information for the reason of a Wake Up event
7141 **/
7142 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7143         struct i40e_asq_cmd_details *cmd_details)
7144 {
7145         struct i40e_aq_desc desc;
7146         enum i40e_status_code status;
7147
7148         i40e_fill_default_direct_cmd_desc(&desc,
7149                                           i40e_aqc_opc_clear_all_wol_filters);
7150
7151         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7152
7153         return status;
7154 }
7155
7156
7157 /**
7158  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7159  * @hw: pointer to the hw struct
7160  * @buff: command buffer (size in bytes = buff_size)
7161  * @buff_size: buffer size in bytes
7162  * @track_id: package tracking id
7163  * @error_offset: returns error offset
7164  * @error_info: returns error information
7165  * @cmd_details: pointer to command details structure or NULL
7166  **/
7167 enum
7168 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7169                                    u16 buff_size, u32 track_id,
7170                                    u32 *error_offset, u32 *error_info,
7171                                    struct i40e_asq_cmd_details *cmd_details)
7172 {
7173         struct i40e_aq_desc desc;
7174         struct i40e_aqc_write_personalization_profile *cmd =
7175                 (struct i40e_aqc_write_personalization_profile *)
7176                 &desc.params.raw;
7177         struct i40e_aqc_write_ddp_resp *resp;
7178         enum i40e_status_code status;
7179
7180         i40e_fill_default_direct_cmd_desc(&desc,
7181                                   i40e_aqc_opc_write_personalization_profile);
7182
7183         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7184         if (buff_size > I40E_AQ_LARGE_BUF)
7185                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7186
7187         desc.datalen = CPU_TO_LE16(buff_size);
7188
7189         cmd->profile_track_id = CPU_TO_LE32(track_id);
7190
7191         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7192         if (!status) {
7193                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7194                 if (error_offset)
7195                         *error_offset = LE32_TO_CPU(resp->error_offset);
7196                 if (error_info)
7197                         *error_info = LE32_TO_CPU(resp->error_info);
7198         }
7199
7200         return status;
7201 }
7202
7203 /**
7204  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7205  * @hw: pointer to the hw struct
7206  * @buff: command buffer (size in bytes = buff_size)
7207  * @buff_size: buffer size in bytes
7208  * @cmd_details: pointer to command details structure or NULL
7209  **/
7210 enum
7211 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7212                                       u16 buff_size, u8 flags,
7213                                       struct i40e_asq_cmd_details *cmd_details)
7214 {
7215         struct i40e_aq_desc desc;
7216         struct i40e_aqc_get_applied_profiles *cmd =
7217                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7218         enum i40e_status_code status;
7219
7220         i40e_fill_default_direct_cmd_desc(&desc,
7221                           i40e_aqc_opc_get_personalization_profile_list);
7222
7223         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7224         if (buff_size > I40E_AQ_LARGE_BUF)
7225                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7226         desc.datalen = CPU_TO_LE16(buff_size);
7227
7228         cmd->flags = flags;
7229
7230         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7231
7232         return status;
7233 }
7234
7235 /**
7236  * i40e_find_segment_in_package
7237  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7238  * @pkg_hdr: pointer to the package header to be searched
7239  *
7240  * This function searches a package file for a particular segment type. On
7241  * success it returns a pointer to the segment header, otherwise it will
7242  * return NULL.
7243  **/
7244 struct i40e_generic_seg_header *
7245 i40e_find_segment_in_package(u32 segment_type,
7246                              struct i40e_package_header *pkg_hdr)
7247 {
7248         struct i40e_generic_seg_header *segment;
7249         u32 i;
7250
7251         /* Search all package segments for the requested segment type */
7252         for (i = 0; i < pkg_hdr->segment_count; i++) {
7253                 segment =
7254                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7255                          pkg_hdr->segment_offset[i]);
7256
7257                 if (segment->type == segment_type)
7258                         return segment;
7259         }
7260
7261         return NULL;
7262 }
7263
7264 /**
7265  * i40e_write_profile
7266  * @hw: pointer to the hardware structure
7267  * @profile: pointer to the profile segment of the package to be downloaded
7268  * @track_id: package tracking id
7269  *
7270  * Handles the download of a complete package.
7271  */
7272 enum i40e_status_code
7273 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7274                    u32 track_id)
7275 {
7276         enum i40e_status_code status = I40E_SUCCESS;
7277         struct i40e_section_table *sec_tbl;
7278         struct i40e_profile_section_header *sec = NULL;
7279         u32 dev_cnt;
7280         u32 vendor_dev_id;
7281         u32 *nvm;
7282         u32 section_size = 0;
7283         u32 offset = 0, info = 0;
7284         u32 i;
7285
7286         if (!track_id) {
7287                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0.");
7288                 return I40E_NOT_SUPPORTED;
7289         }
7290
7291         dev_cnt = profile->device_table_count;
7292
7293         for (i = 0; i < dev_cnt; i++) {
7294                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7295                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID)
7296                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
7297                                 break;
7298         }
7299         if (i == dev_cnt) {
7300                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
7301                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7302         }
7303
7304         nvm = (u32 *)&profile->device_table[dev_cnt];
7305         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
7306
7307         for (i = 0; i < sec_tbl->section_count; i++) {
7308                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
7309                                              sec_tbl->section_offset[i]);
7310
7311                 /* Skip 'AQ', 'note' and 'name' sections */
7312                 if (sec->section.type != SECTION_TYPE_MMIO)
7313                         continue;
7314
7315                 section_size = sec->section.size +
7316                         sizeof(struct i40e_profile_section_header);
7317
7318                 /* Write profile */
7319                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7320                                            track_id, &offset, &info, NULL);
7321                 if (status) {
7322                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7323                                    "Failed to write profile: offset %d, info %d",
7324                                    offset, info);
7325                         break;
7326                 }
7327         }
7328         return status;
7329 }
7330
7331 /**
7332  * i40e_add_pinfo_to_list
7333  * @hw: pointer to the hardware structure
7334  * @profile: pointer to the profile segment of the package
7335  * @profile_info_sec: buffer for information section
7336  * @track_id: package tracking id
7337  *
7338  * Register a profile to the list of loaded profiles.
7339  */
7340 enum i40e_status_code
7341 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7342                        struct i40e_profile_segment *profile,
7343                        u8 *profile_info_sec, u32 track_id)
7344 {
7345         enum i40e_status_code status = I40E_SUCCESS;
7346         struct i40e_profile_section_header *sec = NULL;
7347         struct i40e_profile_info *pinfo;
7348         u32 offset = 0, info = 0;
7349
7350         sec = (struct i40e_profile_section_header *)profile_info_sec;
7351         sec->tbl_size = 1;
7352         sec->data_end = sizeof(struct i40e_profile_section_header) +
7353                         sizeof(struct i40e_profile_info);
7354         sec->section.type = SECTION_TYPE_INFO;
7355         sec->section.offset = sizeof(struct i40e_profile_section_header);
7356         sec->section.size = sizeof(struct i40e_profile_info);
7357         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7358                                              sec->section.offset);
7359         pinfo->track_id = track_id;
7360         pinfo->version = profile->version;
7361         pinfo->op = I40E_DDP_ADD_TRACKID;
7362         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
7363
7364         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7365                                 track_id, &offset, &info, NULL);
7366         return status;
7367 }