drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                 case I40E_DEV_ID_QSFP_I_X722:
  85                         hw->mac.type = I40E_MAC_X722;
  86                         break;
  87 #endif
  88 #ifdef X722_SUPPORT
  89 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  90                 case I40E_DEV_ID_X722_VF:
  91                 case I40E_DEV_ID_X722_VF_HV:
  92 #ifdef X722_A0_SUPPORT
  93                 case I40E_DEV_ID_X722_A0_VF:
  94 #endif
  95                         hw->mac.type = I40E_MAC_X722_VF;
  96                         break;
  97 #endif /* INTEGRATED_VF || VF_DRIVER */
  98 #endif /* X722_SUPPORT */
  99 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
 100                 case I40E_DEV_ID_VF:
 101                 case I40E_DEV_ID_VF_HV:
 102                         hw->mac.type = I40E_MAC_VF;
 103                         break;
 104 #endif
 105                 default:
 106                         hw->mac.type = I40E_MAC_GENERIC;
 107                         break;
 108                 }
 109         } else {
 110                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 111         }
 112
 113         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 114                   hw->mac.type, status);
 115         return status;
 116 }
 117
 118 #ifndef I40E_NDIS_SUPPORT
 119 /**
 120  * i40e_aq_str - convert AQ err code to a string
 121  * @hw: pointer to the HW structure
 122  * @aq_err: the AQ error code to convert
 123  **/
 124 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 125 {
 126         switch (aq_err) {
 127         case I40E_AQ_RC_OK:
 128                 return "OK";
 129         case I40E_AQ_RC_EPERM:
 130                 return "I40E_AQ_RC_EPERM";
 131         case I40E_AQ_RC_ENOENT:
 132                 return "I40E_AQ_RC_ENOENT";
 133         case I40E_AQ_RC_ESRCH:
 134                 return "I40E_AQ_RC_ESRCH";
 135         case I40E_AQ_RC_EINTR:
 136                 return "I40E_AQ_RC_EINTR";
 137         case I40E_AQ_RC_EIO:
 138                 return "I40E_AQ_RC_EIO";
 139         case I40E_AQ_RC_ENXIO:
 140                 return "I40E_AQ_RC_ENXIO";
 141         case I40E_AQ_RC_E2BIG:
 142                 return "I40E_AQ_RC_E2BIG";
 143         case I40E_AQ_RC_EAGAIN:
 144                 return "I40E_AQ_RC_EAGAIN";
 145         case I40E_AQ_RC_ENOMEM:
 146                 return "I40E_AQ_RC_ENOMEM";
 147         case I40E_AQ_RC_EACCES:
 148                 return "I40E_AQ_RC_EACCES";
 149         case I40E_AQ_RC_EFAULT:
 150                 return "I40E_AQ_RC_EFAULT";
 151         case I40E_AQ_RC_EBUSY:
 152                 return "I40E_AQ_RC_EBUSY";
 153         case I40E_AQ_RC_EEXIST:
 154                 return "I40E_AQ_RC_EEXIST";
 155         case I40E_AQ_RC_EINVAL:
 156                 return "I40E_AQ_RC_EINVAL";
 157         case I40E_AQ_RC_ENOTTY:
 158                 return "I40E_AQ_RC_ENOTTY";
 159         case I40E_AQ_RC_ENOSPC:
 160                 return "I40E_AQ_RC_ENOSPC";
 161         case I40E_AQ_RC_ENOSYS:
 162                 return "I40E_AQ_RC_ENOSYS";
 163         case I40E_AQ_RC_ERANGE:
 164                 return "I40E_AQ_RC_ERANGE";
 165         case I40E_AQ_RC_EFLUSHED:
 166                 return "I40E_AQ_RC_EFLUSHED";
 167         case I40E_AQ_RC_BAD_ADDR:
 168                 return "I40E_AQ_RC_BAD_ADDR";
 169         case I40E_AQ_RC_EMODE:
 170                 return "I40E_AQ_RC_EMODE";
 171         case I40E_AQ_RC_EFBIG:
 172                 return "I40E_AQ_RC_EFBIG";
 173         }
 174
 175         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 176         return hw->err_str;
 177 }
 178
 179 /**
 180  * i40e_stat_str - convert status err code to a string
 181  * @hw: pointer to the HW structure
 182  * @stat_err: the status error code to convert
 183  **/
 184 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 185 {
 186         switch (stat_err) {
 187         case I40E_SUCCESS:
 188                 return "OK";
 189         case I40E_ERR_NVM:
 190                 return "I40E_ERR_NVM";
 191         case I40E_ERR_NVM_CHECKSUM:
 192                 return "I40E_ERR_NVM_CHECKSUM";
 193         case I40E_ERR_PHY:
 194                 return "I40E_ERR_PHY";
 195         case I40E_ERR_CONFIG:
 196                 return "I40E_ERR_CONFIG";
 197         case I40E_ERR_PARAM:
 198                 return "I40E_ERR_PARAM";
 199         case I40E_ERR_MAC_TYPE:
 200                 return "I40E_ERR_MAC_TYPE";
 201         case I40E_ERR_UNKNOWN_PHY:
 202                 return "I40E_ERR_UNKNOWN_PHY";
 203         case I40E_ERR_LINK_SETUP:
 204                 return "I40E_ERR_LINK_SETUP";
 205         case I40E_ERR_ADAPTER_STOPPED:
 206                 return "I40E_ERR_ADAPTER_STOPPED";
 207         case I40E_ERR_INVALID_MAC_ADDR:
 208                 return "I40E_ERR_INVALID_MAC_ADDR";
 209         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 210                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 211         case I40E_ERR_MASTER_REQUESTS_PENDING:
 212                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 213         case I40E_ERR_INVALID_LINK_SETTINGS:
 214                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 215         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 216                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 217         case I40E_ERR_RESET_FAILED:
 218                 return "I40E_ERR_RESET_FAILED";
 219         case I40E_ERR_SWFW_SYNC:
 220                 return "I40E_ERR_SWFW_SYNC";
 221         case I40E_ERR_NO_AVAILABLE_VSI:
 222                 return "I40E_ERR_NO_AVAILABLE_VSI";
 223         case I40E_ERR_NO_MEMORY:
 224                 return "I40E_ERR_NO_MEMORY";
 225         case I40E_ERR_BAD_PTR:
 226                 return "I40E_ERR_BAD_PTR";
 227         case I40E_ERR_RING_FULL:
 228                 return "I40E_ERR_RING_FULL";
 229         case I40E_ERR_INVALID_PD_ID:
 230                 return "I40E_ERR_INVALID_PD_ID";
 231         case I40E_ERR_INVALID_QP_ID:
 232                 return "I40E_ERR_INVALID_QP_ID";
 233         case I40E_ERR_INVALID_CQ_ID:
 234                 return "I40E_ERR_INVALID_CQ_ID";
 235         case I40E_ERR_INVALID_CEQ_ID:
 236                 return "I40E_ERR_INVALID_CEQ_ID";
 237         case I40E_ERR_INVALID_AEQ_ID:
 238                 return "I40E_ERR_INVALID_AEQ_ID";
 239         case I40E_ERR_INVALID_SIZE:
 240                 return "I40E_ERR_INVALID_SIZE";
 241         case I40E_ERR_INVALID_ARP_INDEX:
 242                 return "I40E_ERR_INVALID_ARP_INDEX";
 243         case I40E_ERR_INVALID_FPM_FUNC_ID:
 244                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 245         case I40E_ERR_QP_INVALID_MSG_SIZE:
 246                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 247         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 248                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 249         case I40E_ERR_INVALID_FRAG_COUNT:
 250                 return "I40E_ERR_INVALID_FRAG_COUNT";
 251         case I40E_ERR_QUEUE_EMPTY:
 252                 return "I40E_ERR_QUEUE_EMPTY";
 253         case I40E_ERR_INVALID_ALIGNMENT:
 254                 return "I40E_ERR_INVALID_ALIGNMENT";
 255         case I40E_ERR_FLUSHED_QUEUE:
 256                 return "I40E_ERR_FLUSHED_QUEUE";
 257         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 258                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 259         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 260                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 261         case I40E_ERR_TIMEOUT:
 262                 return "I40E_ERR_TIMEOUT";
 263         case I40E_ERR_OPCODE_MISMATCH:
 264                 return "I40E_ERR_OPCODE_MISMATCH";
 265         case I40E_ERR_CQP_COMPL_ERROR:
 266                 return "I40E_ERR_CQP_COMPL_ERROR";
 267         case I40E_ERR_INVALID_VF_ID:
 268                 return "I40E_ERR_INVALID_VF_ID";
 269         case I40E_ERR_INVALID_HMCFN_ID:
 270                 return "I40E_ERR_INVALID_HMCFN_ID";
 271         case I40E_ERR_BACKING_PAGE_ERROR:
 272                 return "I40E_ERR_BACKING_PAGE_ERROR";
 273         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 274                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 275         case I40E_ERR_INVALID_PBLE_INDEX:
 276                 return "I40E_ERR_INVALID_PBLE_INDEX";
 277         case I40E_ERR_INVALID_SD_INDEX:
 278                 return "I40E_ERR_INVALID_SD_INDEX";
 279         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 280                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 281         case I40E_ERR_INVALID_SD_TYPE:
 282                 return "I40E_ERR_INVALID_SD_TYPE";
 283         case I40E_ERR_MEMCPY_FAILED:
 284                 return "I40E_ERR_MEMCPY_FAILED";
 285         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 286                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 287         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 288                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 289         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 290                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 291         case I40E_ERR_SRQ_ENABLED:
 292                 return "I40E_ERR_SRQ_ENABLED";
 293         case I40E_ERR_ADMIN_QUEUE_ERROR:
 294                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 295         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 296                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 297         case I40E_ERR_BUF_TOO_SHORT:
 298                 return "I40E_ERR_BUF_TOO_SHORT";
 299         case I40E_ERR_ADMIN_QUEUE_FULL:
 300                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 301         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 302                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 303         case I40E_ERR_BAD_IWARP_CQE:
 304                 return "I40E_ERR_BAD_IWARP_CQE";
 305         case I40E_ERR_NVM_BLANK_MODE:
 306                 return "I40E_ERR_NVM_BLANK_MODE";
 307         case I40E_ERR_NOT_IMPLEMENTED:
 308                 return "I40E_ERR_NOT_IMPLEMENTED";
 309         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 310                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 311         case I40E_ERR_DIAG_TEST_FAILED:
 312                 return "I40E_ERR_DIAG_TEST_FAILED";
 313         case I40E_ERR_NOT_READY:
 314                 return "I40E_ERR_NOT_READY";
 315         case I40E_NOT_SUPPORTED:
 316                 return "I40E_NOT_SUPPORTED";
 317         case I40E_ERR_FIRMWARE_API_VERSION:
 318                 return "I40E_ERR_FIRMWARE_API_VERSION";
 319         }
 320
 321         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 322         return hw->err_str;
 323 }
 324
 325 #endif /* I40E_NDIS_SUPPORT */
 326 /**
 327  * i40e_debug_aq
 328  * @hw: debug mask related to admin queue
 329  * @mask: debug mask
 330  * @desc: pointer to admin queue descriptor
 331  * @buffer: pointer to command buffer
 332  * @buf_len: max length of buffer
 333  *
 334  * Dumps debug log about adminq command with descriptor contents.
 335  **/
 336 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 337                    void *buffer, u16 buf_len)
 338 {
 339         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 340         u16 len = LE16_TO_CPU(aq_desc->datalen);
 341         u8 *buf = (u8 *)buffer;
 342         u16 i = 0;
 343
 344         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 345                 return;
 346
 347         i40e_debug(hw, mask,
 348                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 349                    LE16_TO_CPU(aq_desc->opcode),
 350                    LE16_TO_CPU(aq_desc->flags),
 351                    LE16_TO_CPU(aq_desc->datalen),
 352                    LE16_TO_CPU(aq_desc->retval));
 353         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 354                    LE32_TO_CPU(aq_desc->cookie_high),
 355                    LE32_TO_CPU(aq_desc->cookie_low));
 356         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 357                    LE32_TO_CPU(aq_desc->params.internal.param0),
 358                    LE32_TO_CPU(aq_desc->params.internal.param1));
 359         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 360                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 361                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 362
 363         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 364                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 365                 if (buf_len < len)
 366                         len = buf_len;
 367                 /* write the full 16-byte chunks */
 368                 for (i = 0; i < (len - 16); i += 16)
 369                         i40e_debug(hw, mask,
 370                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 371                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 372                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 373                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 374                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 375                 /* the most we could have left is 16 bytes, pad with zeros */
 376                 if (i < len) {
 377                         char d_buf[16];
 378                         int j, i_sav;
 379
 380                         i_sav = i;
 381                         memset(d_buf, 0, sizeof(d_buf));
 382                         for (j = 0; i < len; j++, i++)
 383                                 d_buf[j] = buf[i];
 384                         i40e_debug(hw, mask,
 385                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 386                                    i_sav, d_buf[0], d_buf[1],
 387                                    d_buf[2], d_buf[3],
 388                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 389                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 390                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 391                 }
 392         }
 393 }
 394
 395 /**
 396  * i40e_check_asq_alive
 397  * @hw: pointer to the hw struct
 398  *
 399  * Returns true if Queue is enabled else false.
 400  **/
 401 bool i40e_check_asq_alive(struct i40e_hw *hw)
 402 {
 403         if (hw->aq.asq.len)
 404 #ifdef PF_DRIVER
 405 #ifdef INTEGRATED_VF
 406                 if (!i40e_is_vf(hw))
 407                         return !!(rd32(hw, hw->aq.asq.len) &
 408                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 409 #else
 410                 return !!(rd32(hw, hw->aq.asq.len) &
 411                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 412 #endif /* INTEGRATED_VF */
 413 #endif /* PF_DRIVER */
 414 #ifdef VF_DRIVER
 415 #ifdef INTEGRATED_VF
 416                 if (i40e_is_vf(hw))
 417                         return !!(rd32(hw, hw->aq.asq.len) &
 418                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 419 #else
 420                 return !!(rd32(hw, hw->aq.asq.len) &
 421                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 422 #endif /* INTEGRATED_VF */
 423 #endif /* VF_DRIVER */
 424         return false;
 425 }
 426
 427 /**
 428  * i40e_aq_queue_shutdown
 429  * @hw: pointer to the hw struct
 430  * @unloading: is the driver unloading itself
 431  *
 432  * Tell the Firmware that we're shutting down the AdminQ and whether
 433  * or not the driver is unloading as well.
 434  **/
 435 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 436                                              bool unloading)
 437 {
 438         struct i40e_aq_desc desc;
 439         struct i40e_aqc_queue_shutdown *cmd =
 440                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 441         enum i40e_status_code status;
 442
 443         i40e_fill_default_direct_cmd_desc(&desc,
 444                                           i40e_aqc_opc_queue_shutdown);
 445
 446         if (unloading)
 447                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 448         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 449
 450         return status;
 451 }
 452 #ifdef X722_SUPPORT
 453
 454 /**
 455  * i40e_aq_get_set_rss_lut
 456  * @hw: pointer to the hardware structure
 457  * @vsi_id: vsi fw index
 458  * @pf_lut: for PF table set true, for VSI table set false
 459  * @lut: pointer to the lut buffer provided by the caller
 460  * @lut_size: size of the lut buffer
 461  * @set: set true to set the table, false to get the table
 462  *
 463  * Internal function to get or set RSS look up table
 464  **/
 465 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 466                                                      u16 vsi_id, bool pf_lut,
 467                                                      u8 *lut, u16 lut_size,
 468                                                      bool set)
 469 {
 470         enum i40e_status_code status;
 471         struct i40e_aq_desc desc;
 472         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 473                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 474
 475         if (set)
 476                 i40e_fill_default_direct_cmd_desc(&desc,
 477                                                   i40e_aqc_opc_set_rss_lut);
 478         else
 479                 i40e_fill_default_direct_cmd_desc(&desc,
 480                                                   i40e_aqc_opc_get_rss_lut);
 481
 482         /* Indirect command */
 483         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 484         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 485
 486         cmd_resp->vsi_id =
 487                         CPU_TO_LE16((u16)((vsi_id <<
 488                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 489                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 490         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 491
 492         if (pf_lut)
 493                 cmd_resp->flags |= CPU_TO_LE16((u16)
 494                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 495                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 496                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 497         else
 498                 cmd_resp->flags |= CPU_TO_LE16((u16)
 499                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 500                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 501                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 502
 503         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 504
 505         return status;
 506 }
 507
 508 /**
 509  * i40e_aq_get_rss_lut
 510  * @hw: pointer to the hardware structure
 511  * @vsi_id: vsi fw index
 512  * @pf_lut: for PF table set true, for VSI table set false
 513  * @lut: pointer to the lut buffer provided by the caller
 514  * @lut_size: size of the lut buffer
 515  *
 516  * get the RSS lookup table, PF or VSI type
 517  **/
 518 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 519                                           bool pf_lut, u8 *lut, u16 lut_size)
 520 {
 521         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 522                                        false);
 523 }
 524
 525 /**
 526  * i40e_aq_set_rss_lut
 527  * @hw: pointer to the hardware structure
 528  * @vsi_id: vsi fw index
 529  * @pf_lut: for PF table set true, for VSI table set false
 530  * @lut: pointer to the lut buffer provided by the caller
 531  * @lut_size: size of the lut buffer
 532  *
 533  * set the RSS lookup table, PF or VSI type
 534  **/
 535 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 536                                           bool pf_lut, u8 *lut, u16 lut_size)
 537 {
 538         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 539 }
 540
 541 /**
 542  * i40e_aq_get_set_rss_key
 543  * @hw: pointer to the hw struct
 544  * @vsi_id: vsi fw index
 545  * @key: pointer to key info struct
 546  * @set: set true to set the key, false to get the key
 547  *
 548  * get the RSS key per VSI
 549  **/
 550 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 551                                       u16 vsi_id,
 552                                       struct i40e_aqc_get_set_rss_key_data *key,
 553                                       bool set)
 554 {
 555         enum i40e_status_code status;
 556         struct i40e_aq_desc desc;
 557         struct i40e_aqc_get_set_rss_key *cmd_resp =
 558                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 559         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 560
 561         if (set)
 562                 i40e_fill_default_direct_cmd_desc(&desc,
 563                                                   i40e_aqc_opc_set_rss_key);
 564         else
 565                 i40e_fill_default_direct_cmd_desc(&desc,
 566                                                   i40e_aqc_opc_get_rss_key);
 567
 568         /* Indirect command */
 569         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 570         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 571
 572         cmd_resp->vsi_id =
 573                         CPU_TO_LE16((u16)((vsi_id <<
 574                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 575                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 576         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 577
 578         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 579
 580         return status;
 581 }
 582
 583 /**
 584  * i40e_aq_get_rss_key
 585  * @hw: pointer to the hw struct
 586  * @vsi_id: vsi fw index
 587  * @key: pointer to key info struct
 588  *
 589  **/
 590 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 591                                       u16 vsi_id,
 592                                       struct i40e_aqc_get_set_rss_key_data *key)
 593 {
 594         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 595 }
 596
 597 /**
 598  * i40e_aq_set_rss_key
 599  * @hw: pointer to the hw struct
 600  * @vsi_id: vsi fw index
 601  * @key: pointer to key info struct
 602  *
 603  * set the RSS key per VSI
 604  **/
 605 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 606                                       u16 vsi_id,
 607                                       struct i40e_aqc_get_set_rss_key_data *key)
 608 {
 609         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 610 }
 611 #endif /* X722_SUPPORT */
 612
 613 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 614  * hardware to a bit-field that can be used by SW to more easily determine the
 615  * packet type.
 616  *
 617  * Macros are used to shorten the table lines and make this table human
 618  * readable.
 619  *
 620  * We store the PTYPE in the top byte of the bit field - this is just so that
 621  * we can check that the table doesn't have a row missing, as the index into
 622  * the table should be the PTYPE.
 623  *
 624  * Typical work flow:
 625  *
 626  * IF NOT i40e_ptype_lookup[ptype].known
 627  * THEN
 628  *      Packet is unknown
 629  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 630  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 631  * ELSE
 632  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 633  * ENDIF
 634  */
 635
 636 /* macro to make the table lines short */
 637 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 638         {       PTYPE, \
 639                 1, \
 640                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 641                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 642                 I40E_RX_PTYPE_##OUTER_FRAG, \
 643                 I40E_RX_PTYPE_TUNNEL_##T, \
 644                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 645                 I40E_RX_PTYPE_##TEF, \
 646                 I40E_RX_PTYPE_INNER_PROT_##I, \
 647                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 648
 649 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 650                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 651
 652 /* shorter macros makes the table fit but are terse */
 653 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 654 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 655 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 656
 657 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 658 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 659         /* L2 Packet types */
 660         I40E_PTT_UNUSED_ENTRY(0),
 661         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 663         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 664         I40E_PTT_UNUSED_ENTRY(4),
 665         I40E_PTT_UNUSED_ENTRY(5),
 666         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 667         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 668         I40E_PTT_UNUSED_ENTRY(8),
 669         I40E_PTT_UNUSED_ENTRY(9),
 670         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 671         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 672         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 680         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 681         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 682
 683         /* Non Tunneled IPv4 */
 684         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 685         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 686         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 687         I40E_PTT_UNUSED_ENTRY(25),
 688         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 689         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 690         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 691
 692         /* IPv4 --> IPv4 */
 693         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 694         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 695         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 696         I40E_PTT_UNUSED_ENTRY(32),
 697         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 698         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 699         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 700
 701         /* IPv4 --> IPv6 */
 702         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 703         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 704         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 705         I40E_PTT_UNUSED_ENTRY(39),
 706         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 707         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 708         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 709
 710         /* IPv4 --> GRE/NAT */
 711         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 712
 713         /* IPv4 --> GRE/NAT --> IPv4 */
 714         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 715         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 716         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 717         I40E_PTT_UNUSED_ENTRY(47),
 718         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 719         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 720         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 721
 722         /* IPv4 --> GRE/NAT --> IPv6 */
 723         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 724         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 725         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 726         I40E_PTT_UNUSED_ENTRY(54),
 727         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 728         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 729         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 730
 731         /* IPv4 --> GRE/NAT --> MAC */
 732         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 733
 734         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 735         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 736         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 737         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 738         I40E_PTT_UNUSED_ENTRY(62),
 739         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 740         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 741         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 742
 743         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 744         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 745         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 746         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 747         I40E_PTT_UNUSED_ENTRY(69),
 748         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 749         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 750         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 751
 752         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 753         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 754
 755         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 756         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 757         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 758         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(77),
 760         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 761         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 762         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 763
 764         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 765         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 766         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 767         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 768         I40E_PTT_UNUSED_ENTRY(84),
 769         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 770         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 771         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 772
 773         /* Non Tunneled IPv6 */
 774         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 775         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 776         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 777         I40E_PTT_UNUSED_ENTRY(91),
 778         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 779         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 780         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 781
 782         /* IPv6 --> IPv4 */
 783         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 784         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 785         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 786         I40E_PTT_UNUSED_ENTRY(98),
 787         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 788         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 789         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 790
 791         /* IPv6 --> IPv6 */
 792         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 793         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 794         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 795         I40E_PTT_UNUSED_ENTRY(105),
 796         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 797         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 798         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 799
 800         /* IPv6 --> GRE/NAT */
 801         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 802
 803         /* IPv6 --> GRE/NAT -> IPv4 */
 804         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 805         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 806         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 807         I40E_PTT_UNUSED_ENTRY(113),
 808         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 809         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 810         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 811
 812         /* IPv6 --> GRE/NAT -> IPv6 */
 813         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 814         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 815         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 816         I40E_PTT_UNUSED_ENTRY(120),
 817         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 818         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 819         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 820
 821         /* IPv6 --> GRE/NAT -> MAC */
 822         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 823
 824         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 825         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 826         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 827         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 828         I40E_PTT_UNUSED_ENTRY(128),
 829         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 830         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 831         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 832
 833         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 834         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 835         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 836         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 837         I40E_PTT_UNUSED_ENTRY(135),
 838         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 839         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 840         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 841
 842         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 843         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 844
 845         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 846         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 847         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 848         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 849         I40E_PTT_UNUSED_ENTRY(143),
 850         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 851         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 852         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 853
 854         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 855         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 856         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 857         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 858         I40E_PTT_UNUSED_ENTRY(150),
 859         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 860         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 861         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 862
 863         /* unused entries */
 864         I40E_PTT_UNUSED_ENTRY(154),
 865         I40E_PTT_UNUSED_ENTRY(155),
 866         I40E_PTT_UNUSED_ENTRY(156),
 867         I40E_PTT_UNUSED_ENTRY(157),
 868         I40E_PTT_UNUSED_ENTRY(158),
 869         I40E_PTT_UNUSED_ENTRY(159),
 870
 871         I40E_PTT_UNUSED_ENTRY(160),
 872         I40E_PTT_UNUSED_ENTRY(161),
 873         I40E_PTT_UNUSED_ENTRY(162),
 874         I40E_PTT_UNUSED_ENTRY(163),
 875         I40E_PTT_UNUSED_ENTRY(164),
 876         I40E_PTT_UNUSED_ENTRY(165),
 877         I40E_PTT_UNUSED_ENTRY(166),
 878         I40E_PTT_UNUSED_ENTRY(167),
 879         I40E_PTT_UNUSED_ENTRY(168),
 880         I40E_PTT_UNUSED_ENTRY(169),
 881
 882         I40E_PTT_UNUSED_ENTRY(170),
 883         I40E_PTT_UNUSED_ENTRY(171),
 884         I40E_PTT_UNUSED_ENTRY(172),
 885         I40E_PTT_UNUSED_ENTRY(173),
 886         I40E_PTT_UNUSED_ENTRY(174),
 887         I40E_PTT_UNUSED_ENTRY(175),
 888         I40E_PTT_UNUSED_ENTRY(176),
 889         I40E_PTT_UNUSED_ENTRY(177),
 890         I40E_PTT_UNUSED_ENTRY(178),
 891         I40E_PTT_UNUSED_ENTRY(179),
 892
 893         I40E_PTT_UNUSED_ENTRY(180),
 894         I40E_PTT_UNUSED_ENTRY(181),
 895         I40E_PTT_UNUSED_ENTRY(182),
 896         I40E_PTT_UNUSED_ENTRY(183),
 897         I40E_PTT_UNUSED_ENTRY(184),
 898         I40E_PTT_UNUSED_ENTRY(185),
 899         I40E_PTT_UNUSED_ENTRY(186),
 900         I40E_PTT_UNUSED_ENTRY(187),
 901         I40E_PTT_UNUSED_ENTRY(188),
 902         I40E_PTT_UNUSED_ENTRY(189),
 903
 904         I40E_PTT_UNUSED_ENTRY(190),
 905         I40E_PTT_UNUSED_ENTRY(191),
 906         I40E_PTT_UNUSED_ENTRY(192),
 907         I40E_PTT_UNUSED_ENTRY(193),
 908         I40E_PTT_UNUSED_ENTRY(194),
 909         I40E_PTT_UNUSED_ENTRY(195),
 910         I40E_PTT_UNUSED_ENTRY(196),
 911         I40E_PTT_UNUSED_ENTRY(197),
 912         I40E_PTT_UNUSED_ENTRY(198),
 913         I40E_PTT_UNUSED_ENTRY(199),
 914
 915         I40E_PTT_UNUSED_ENTRY(200),
 916         I40E_PTT_UNUSED_ENTRY(201),
 917         I40E_PTT_UNUSED_ENTRY(202),
 918         I40E_PTT_UNUSED_ENTRY(203),
 919         I40E_PTT_UNUSED_ENTRY(204),
 920         I40E_PTT_UNUSED_ENTRY(205),
 921         I40E_PTT_UNUSED_ENTRY(206),
 922         I40E_PTT_UNUSED_ENTRY(207),
 923         I40E_PTT_UNUSED_ENTRY(208),
 924         I40E_PTT_UNUSED_ENTRY(209),
 925
 926         I40E_PTT_UNUSED_ENTRY(210),
 927         I40E_PTT_UNUSED_ENTRY(211),
 928         I40E_PTT_UNUSED_ENTRY(212),
 929         I40E_PTT_UNUSED_ENTRY(213),
 930         I40E_PTT_UNUSED_ENTRY(214),
 931         I40E_PTT_UNUSED_ENTRY(215),
 932         I40E_PTT_UNUSED_ENTRY(216),
 933         I40E_PTT_UNUSED_ENTRY(217),
 934         I40E_PTT_UNUSED_ENTRY(218),
 935         I40E_PTT_UNUSED_ENTRY(219),
 936
 937         I40E_PTT_UNUSED_ENTRY(220),
 938         I40E_PTT_UNUSED_ENTRY(221),
 939         I40E_PTT_UNUSED_ENTRY(222),
 940         I40E_PTT_UNUSED_ENTRY(223),
 941         I40E_PTT_UNUSED_ENTRY(224),
 942         I40E_PTT_UNUSED_ENTRY(225),
 943         I40E_PTT_UNUSED_ENTRY(226),
 944         I40E_PTT_UNUSED_ENTRY(227),
 945         I40E_PTT_UNUSED_ENTRY(228),
 946         I40E_PTT_UNUSED_ENTRY(229),
 947
 948         I40E_PTT_UNUSED_ENTRY(230),
 949         I40E_PTT_UNUSED_ENTRY(231),
 950         I40E_PTT_UNUSED_ENTRY(232),
 951         I40E_PTT_UNUSED_ENTRY(233),
 952         I40E_PTT_UNUSED_ENTRY(234),
 953         I40E_PTT_UNUSED_ENTRY(235),
 954         I40E_PTT_UNUSED_ENTRY(236),
 955         I40E_PTT_UNUSED_ENTRY(237),
 956         I40E_PTT_UNUSED_ENTRY(238),
 957         I40E_PTT_UNUSED_ENTRY(239),
 958
 959         I40E_PTT_UNUSED_ENTRY(240),
 960         I40E_PTT_UNUSED_ENTRY(241),
 961         I40E_PTT_UNUSED_ENTRY(242),
 962         I40E_PTT_UNUSED_ENTRY(243),
 963         I40E_PTT_UNUSED_ENTRY(244),
 964         I40E_PTT_UNUSED_ENTRY(245),
 965         I40E_PTT_UNUSED_ENTRY(246),
 966         I40E_PTT_UNUSED_ENTRY(247),
 967         I40E_PTT_UNUSED_ENTRY(248),
 968         I40E_PTT_UNUSED_ENTRY(249),
 969
 970         I40E_PTT_UNUSED_ENTRY(250),
 971         I40E_PTT_UNUSED_ENTRY(251),
 972         I40E_PTT_UNUSED_ENTRY(252),
 973         I40E_PTT_UNUSED_ENTRY(253),
 974         I40E_PTT_UNUSED_ENTRY(254),
 975         I40E_PTT_UNUSED_ENTRY(255)
 976 };
 977
 978
 979 /**
 980  * i40e_validate_mac_addr - Validate unicast MAC address
 981  * @mac_addr: pointer to MAC address
 982  *
 983  * Tests a MAC address to ensure it is a valid Individual Address
 984  **/
 985 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 986 {
 987         enum i40e_status_code status = I40E_SUCCESS;
 988
 989         DEBUGFUNC("i40e_validate_mac_addr");
 990
 991         /* Broadcast addresses ARE multicast addresses
 992          * Make sure it is not a multicast address
 993          * Reject the zero address
 994          */
 995         if (I40E_IS_MULTICAST(mac_addr) ||
 996             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 997               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 998                 status = I40E_ERR_INVALID_MAC_ADDR;
 999
1000         return status;
1001 }
1002 #ifdef PF_DRIVER
1003
1004 /**
1005  * i40e_init_shared_code - Initialize the shared code
1006  * @hw: pointer to hardware structure
1007  *
1008  * This assigns the MAC type and PHY code and inits the NVM.
1009  * Does not touch the hardware. This function must be called prior to any
1010  * other function in the shared code. The i40e_hw structure should be
1011  * memset to 0 prior to calling this function.  The following fields in
1012  * hw structure should be filled in prior to calling this function:
1013  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1014  * subsystem_vendor_id, and revision_id
1015  **/
1016 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1017 {
1018         enum i40e_status_code status = I40E_SUCCESS;
1019         u32 port, ari, func_rid;
1020
1021         DEBUGFUNC("i40e_init_shared_code");
1022
1023         i40e_set_mac_type(hw);
1024
1025         switch (hw->mac.type) {
1026         case I40E_MAC_XL710:
1027 #ifdef X722_SUPPORT
1028         case I40E_MAC_X722:
1029 #endif
1030                 break;
1031         default:
1032                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1033         }
1034
1035         hw->phy.get_link_info = true;
1036
1037         /* Determine port number and PF number*/
1038         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1039                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1040         hw->port = (u8)port;
1041         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1042                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1043         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1044         if (ari)
1045                 hw->pf_id = (u8)(func_rid & 0xff);
1046         else
1047                 hw->pf_id = (u8)(func_rid & 0x7);
1048
1049 #ifdef X722_SUPPORT
1050         if (hw->mac.type == I40E_MAC_X722)
1051                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1052
1053 #endif
1054         status = i40e_init_nvm(hw);
1055         return status;
1056 }
1057
1058 /**
1059  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1060  * @hw: pointer to the hw struct
1061  * @flags: a return indicator of what addresses were added to the addr store
1062  * @addrs: the requestor's mac addr store
1063  * @cmd_details: pointer to command details structure or NULL
1064  **/
1065 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1066                                    u16 *flags,
1067                                    struct i40e_aqc_mac_address_read_data *addrs,
1068                                    struct i40e_asq_cmd_details *cmd_details)
1069 {
1070         struct i40e_aq_desc desc;
1071         struct i40e_aqc_mac_address_read *cmd_data =
1072                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1073         enum i40e_status_code status;
1074
1075         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1076         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1077
1078         status = i40e_asq_send_command(hw, &desc, addrs,
1079                                        sizeof(*addrs), cmd_details);
1080         *flags = LE16_TO_CPU(cmd_data->command_flags);
1081
1082         return status;
1083 }
1084
1085 /**
1086  * i40e_aq_mac_address_write - Change the MAC addresses
1087  * @hw: pointer to the hw struct
1088  * @flags: indicates which MAC to be written
1089  * @mac_addr: address to write
1090  * @cmd_details: pointer to command details structure or NULL
1091  **/
1092 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1093                                     u16 flags, u8 *mac_addr,
1094                                     struct i40e_asq_cmd_details *cmd_details)
1095 {
1096         struct i40e_aq_desc desc;
1097         struct i40e_aqc_mac_address_write *cmd_data =
1098                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1099         enum i40e_status_code status;
1100
1101         i40e_fill_default_direct_cmd_desc(&desc,
1102                                           i40e_aqc_opc_mac_address_write);
1103         cmd_data->command_flags = CPU_TO_LE16(flags);
1104         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1105         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1106                                         ((u32)mac_addr[3] << 16) |
1107                                         ((u32)mac_addr[4] << 8) |
1108                                         mac_addr[5]);
1109
1110         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1111
1112         return status;
1113 }
1114
1115 /**
1116  * i40e_get_mac_addr - get MAC address
1117  * @hw: pointer to the HW structure
1118  * @mac_addr: pointer to MAC address
1119  *
1120  * Reads the adapter's MAC address from register
1121  **/
1122 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1123 {
1124         struct i40e_aqc_mac_address_read_data addrs;
1125         enum i40e_status_code status;
1126         u16 flags = 0;
1127
1128         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1129
1130         if (flags & I40E_AQC_LAN_ADDR_VALID)
1131                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1132
1133         return status;
1134 }
1135
1136 /**
1137  * i40e_get_port_mac_addr - get Port MAC address
1138  * @hw: pointer to the HW structure
1139  * @mac_addr: pointer to Port MAC address
1140  *
1141  * Reads the adapter's Port MAC address
1142  **/
1143 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1144 {
1145         struct i40e_aqc_mac_address_read_data addrs;
1146         enum i40e_status_code status;
1147         u16 flags = 0;
1148
1149         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1150         if (status)
1151                 return status;
1152
1153         if (flags & I40E_AQC_PORT_ADDR_VALID)
1154                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1155         else
1156                 status = I40E_ERR_INVALID_MAC_ADDR;
1157
1158         return status;
1159 }
1160
1161 /**
1162  * i40e_pre_tx_queue_cfg - pre tx queue configure
1163  * @hw: pointer to the HW structure
1164  * @queue: target pf queue index
1165  * @enable: state change request
1166  *
1167  * Handles hw requirement to indicate intention to enable
1168  * or disable target queue.
1169  **/
1170 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1171 {
1172         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1173         u32 reg_block = 0;
1174         u32 reg_val;
1175
1176         if (abs_queue_idx >= 128) {
1177                 reg_block = abs_queue_idx / 128;
1178                 abs_queue_idx %= 128;
1179         }
1180
1181         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1182         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1183         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1184
1185         if (enable)
1186                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1187         else
1188                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1189
1190         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1191 }
1192
1193 /**
1194  *  i40e_read_pba_string - Reads part number string from EEPROM
1195  *  @hw: pointer to hardware structure
1196  *  @pba_num: stores the part number string from the EEPROM
1197  *  @pba_num_size: part number string buffer length
1198  *
1199  *  Reads the part number string from the EEPROM.
1200  **/
1201 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1202                                             u32 pba_num_size)
1203 {
1204         enum i40e_status_code status = I40E_SUCCESS;
1205         u16 pba_word = 0;
1206         u16 pba_size = 0;
1207         u16 pba_ptr = 0;
1208         u16 i = 0;
1209
1210         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1211         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1212                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1213                 return status;
1214         }
1215
1216         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1217         if (status != I40E_SUCCESS) {
1218                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1219                 return status;
1220         }
1221
1222         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1223         if (status != I40E_SUCCESS) {
1224                 DEBUGOUT("Failed to read PBA Block size.\n");
1225                 return status;
1226         }
1227
1228         /* Subtract one to get PBA word count (PBA Size word is included in
1229          * total size)
1230          */
1231         pba_size--;
1232         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1233                 DEBUGOUT("Buffer to small for PBA data.\n");
1234                 return I40E_ERR_PARAM;
1235         }
1236
1237         for (i = 0; i < pba_size; i++) {
1238                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1239                 if (status != I40E_SUCCESS) {
1240                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1241                         return status;
1242                 }
1243
1244                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1245                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1246         }
1247         pba_num[(pba_size * 2)] = '\0';
1248
1249         return status;
1250 }
1251
1252 /**
1253  * i40e_get_media_type - Gets media type
1254  * @hw: pointer to the hardware structure
1255  **/
1256 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1257 {
1258         enum i40e_media_type media;
1259
1260         switch (hw->phy.link_info.phy_type) {
1261         case I40E_PHY_TYPE_10GBASE_SR:
1262         case I40E_PHY_TYPE_10GBASE_LR:
1263         case I40E_PHY_TYPE_1000BASE_SX:
1264         case I40E_PHY_TYPE_1000BASE_LX:
1265         case I40E_PHY_TYPE_40GBASE_SR4:
1266         case I40E_PHY_TYPE_40GBASE_LR4:
1267                 media = I40E_MEDIA_TYPE_FIBER;
1268                 break;
1269         case I40E_PHY_TYPE_100BASE_TX:
1270         case I40E_PHY_TYPE_1000BASE_T:
1271         case I40E_PHY_TYPE_10GBASE_T:
1272                 media = I40E_MEDIA_TYPE_BASET;
1273                 break;
1274         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1275         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1276         case I40E_PHY_TYPE_10GBASE_CR1:
1277         case I40E_PHY_TYPE_40GBASE_CR4:
1278         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1279         case I40E_PHY_TYPE_40GBASE_AOC:
1280         case I40E_PHY_TYPE_10GBASE_AOC:
1281                 media = I40E_MEDIA_TYPE_DA;
1282                 break;
1283         case I40E_PHY_TYPE_1000BASE_KX:
1284         case I40E_PHY_TYPE_10GBASE_KX4:
1285         case I40E_PHY_TYPE_10GBASE_KR:
1286         case I40E_PHY_TYPE_40GBASE_KR4:
1287         case I40E_PHY_TYPE_20GBASE_KR2:
1288                 media = I40E_MEDIA_TYPE_BACKPLANE;
1289                 break;
1290         case I40E_PHY_TYPE_SGMII:
1291         case I40E_PHY_TYPE_XAUI:
1292         case I40E_PHY_TYPE_XFI:
1293         case I40E_PHY_TYPE_XLAUI:
1294         case I40E_PHY_TYPE_XLPPI:
1295         default:
1296                 media = I40E_MEDIA_TYPE_UNKNOWN;
1297                 break;
1298         }
1299
1300         return media;
1301 }
1302
1303 #define I40E_PF_RESET_WAIT_COUNT        200
1304 /**
1305  * i40e_pf_reset - Reset the PF
1306  * @hw: pointer to the hardware structure
1307  *
1308  * Assuming someone else has triggered a global reset,
1309  * assure the global reset is complete and then reset the PF
1310  **/
1311 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1312 {
1313         u32 cnt = 0;
1314         u32 cnt1 = 0;
1315         u32 reg = 0;
1316         u32 grst_del;
1317
1318         /* Poll for Global Reset steady state in case of recent GRST.
1319          * The grst delay value is in 100ms units, and we'll wait a
1320          * couple counts longer to be sure we don't just miss the end.
1321          */
1322         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1323                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1324                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1325
1326         grst_del = grst_del * 20;
1327
1328         for (cnt = 0; cnt < grst_del; cnt++) {
1329                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1330                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1331                         break;
1332                 i40e_msec_delay(100);
1333         }
1334         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1335                 DEBUGOUT("Global reset polling failed to complete.\n");
1336                 return I40E_ERR_RESET_FAILED;
1337         }
1338
1339         /* Now Wait for the FW to be ready */
1340         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1341                 reg = rd32(hw, I40E_GLNVM_ULD);
1342                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1343                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1344                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1345                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1346                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1347                         break;
1348                 }
1349                 i40e_msec_delay(10);
1350         }
1351         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1352                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1353                 DEBUGOUT("wait for FW Reset complete timedout\n");
1354                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1355                 return I40E_ERR_RESET_FAILED;
1356         }
1357
1358         /* If there was a Global Reset in progress when we got here,
1359          * we don't need to do the PF Reset
1360          */
1361         if (!cnt) {
1362                 reg = rd32(hw, I40E_PFGEN_CTRL);
1363                 wr32(hw, I40E_PFGEN_CTRL,
1364                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1365                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1366                         reg = rd32(hw, I40E_PFGEN_CTRL);
1367                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1368                                 break;
1369                         i40e_msec_delay(1);
1370                 }
1371                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1372                         DEBUGOUT("PF reset polling failed to complete.\n");
1373                         return I40E_ERR_RESET_FAILED;
1374                 }
1375         }
1376
1377         i40e_clear_pxe_mode(hw);
1378
1379
1380         return I40E_SUCCESS;
1381 }
1382
1383 /**
1384  * i40e_clear_hw - clear out any left over hw state
1385  * @hw: pointer to the hw struct
1386  *
1387  * Clear queues and interrupts, typically called at init time,
1388  * but after the capabilities have been found so we know how many
1389  * queues and msix vectors have been allocated.
1390  **/
1391 void i40e_clear_hw(struct i40e_hw *hw)
1392 {
1393         u32 num_queues, base_queue;
1394         u32 num_pf_int;
1395         u32 num_vf_int;
1396         u32 num_vfs;
1397         u32 i, j;
1398         u32 val;
1399         u32 eol = 0x7ff;
1400
1401         /* get number of interrupts, queues, and vfs */
1402         val = rd32(hw, I40E_GLPCI_CNF2);
1403         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1404                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1405         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1406                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1407
1408         val = rd32(hw, I40E_PFLAN_QALLOC);
1409         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1410                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1411         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1412                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1413         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1414                 num_queues = (j - base_queue) + 1;
1415         else
1416                 num_queues = 0;
1417
1418         val = rd32(hw, I40E_PF_VT_PFALLOC);
1419         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1420                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1421         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1422                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1423         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1424                 num_vfs = (j - i) + 1;
1425         else
1426                 num_vfs = 0;
1427
1428         /* stop all the interrupts */
1429         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1430         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1431         for (i = 0; i < num_pf_int - 2; i++)
1432                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1433
1434         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1435         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1436         wr32(hw, I40E_PFINT_LNKLST0, val);
1437         for (i = 0; i < num_pf_int - 2; i++)
1438                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1439         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1440         for (i = 0; i < num_vfs; i++)
1441                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1442         for (i = 0; i < num_vf_int - 2; i++)
1443                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1444
1445         /* warn the HW of the coming Tx disables */
1446         for (i = 0; i < num_queues; i++) {
1447                 u32 abs_queue_idx = base_queue + i;
1448                 u32 reg_block = 0;
1449
1450                 if (abs_queue_idx >= 128) {
1451                         reg_block = abs_queue_idx / 128;
1452                         abs_queue_idx %= 128;
1453                 }
1454
1455                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1456                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1457                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1458                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1459
1460                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1461         }
1462         i40e_usec_delay(400);
1463
1464         /* stop all the queues */
1465         for (i = 0; i < num_queues; i++) {
1466                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1467                 wr32(hw, I40E_QTX_ENA(i), 0);
1468                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1469                 wr32(hw, I40E_QRX_ENA(i), 0);
1470         }
1471
1472         /* short wait for all queue disables to settle */
1473         i40e_usec_delay(50);
1474 }
1475
1476 /**
1477  * i40e_clear_pxe_mode - clear pxe operations mode
1478  * @hw: pointer to the hw struct
1479  *
1480  * Make sure all PXE mode settings are cleared, including things
1481  * like descriptor fetch/write-back mode.
1482  **/
1483 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1484 {
1485         if (i40e_check_asq_alive(hw))
1486                 i40e_aq_clear_pxe_mode(hw, NULL);
1487 }
1488
1489 /**
1490  * i40e_led_is_mine - helper to find matching led
1491  * @hw: pointer to the hw struct
1492  * @idx: index into GPIO registers
1493  *
1494  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1495  */
1496 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1497 {
1498         u32 gpio_val = 0;
1499         u32 port;
1500
1501         if (!hw->func_caps.led[idx])
1502                 return 0;
1503
1504         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1505         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1506                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1507
1508         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1509          * if it is not our port then ignore
1510          */
1511         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1512             (port != hw->port))
1513                 return 0;
1514
1515         return gpio_val;
1516 }
1517
1518 #define I40E_COMBINED_ACTIVITY 0xA
1519 #define I40E_FILTER_ACTIVITY 0xE
1520 #define I40E_LINK_ACTIVITY 0xC
1521 #define I40E_MAC_ACTIVITY 0xD
1522 #define I40E_LED0 22
1523
1524 /**
1525  * i40e_led_get - return current on/off mode
1526  * @hw: pointer to the hw struct
1527  *
1528  * The value returned is the 'mode' field as defined in the
1529  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1530  * values are variations of possible behaviors relating to
1531  * blink, link, and wire.
1532  **/
1533 u32 i40e_led_get(struct i40e_hw *hw)
1534 {
1535         u32 current_mode = 0;
1536         u32 mode = 0;
1537         int i;
1538
1539         /* as per the documentation GPIO 22-29 are the LED
1540          * GPIO pins named LED0..LED7
1541          */
1542         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1543                 u32 gpio_val = i40e_led_is_mine(hw, i);
1544
1545                 if (!gpio_val)
1546                         continue;
1547
1548                 /* ignore gpio LED src mode entries related to the activity
1549                  *  LEDs
1550                  */
1551                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1552                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1553                 switch (current_mode) {
1554                 case I40E_COMBINED_ACTIVITY:
1555                 case I40E_FILTER_ACTIVITY:
1556                 case I40E_MAC_ACTIVITY:
1557                         continue;
1558                 default:
1559                         break;
1560                 }
1561
1562                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1563                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1564                 break;
1565         }
1566
1567         return mode;
1568 }
1569
1570 /**
1571  * i40e_led_set - set new on/off mode
1572  * @hw: pointer to the hw struct
1573  * @mode: 0=off, 0xf=on (else see manual for mode details)
1574  * @blink: true if the LED should blink when on, false if steady
1575  *
1576  * if this function is used to turn on the blink it should
1577  * be used to disable the blink when restoring the original state.
1578  **/
1579 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1580 {
1581         u32 current_mode = 0;
1582         int i;
1583
1584         if (mode & 0xfffffff0)
1585                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1586
1587         /* as per the documentation GPIO 22-29 are the LED
1588          * GPIO pins named LED0..LED7
1589          */
1590         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1591                 u32 gpio_val = i40e_led_is_mine(hw, i);
1592
1593                 if (!gpio_val)
1594                         continue;
1595
1596                 /* ignore gpio LED src mode entries related to the activity
1597                  * LEDs
1598                  */
1599                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1600                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1601                 switch (current_mode) {
1602                 case I40E_COMBINED_ACTIVITY:
1603                 case I40E_FILTER_ACTIVITY:
1604                 case I40E_MAC_ACTIVITY:
1605                         continue;
1606                 default:
1607                         break;
1608                 }
1609
1610                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1611                 /* this & is a bit of paranoia, but serves as a range check */
1612                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1613                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1614
1615                 if (mode == I40E_LINK_ACTIVITY)
1616                         blink = false;
1617
1618                 if (blink)
1619                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1620                 else
1621                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1622
1623                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1624                 break;
1625         }
1626 }
1627
1628 /* Admin command wrappers */
1629
1630 /**
1631  * i40e_aq_get_phy_capabilities
1632  * @hw: pointer to the hw struct
1633  * @abilities: structure for PHY capabilities to be filled
1634  * @qualified_modules: report Qualified Modules
1635  * @report_init: report init capabilities (active are default)
1636  * @cmd_details: pointer to command details structure or NULL
1637  *
1638  * Returns the various PHY abilities supported on the Port.
1639  **/
1640 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1641                         bool qualified_modules, bool report_init,
1642                         struct i40e_aq_get_phy_abilities_resp *abilities,
1643                         struct i40e_asq_cmd_details *cmd_details)
1644 {
1645         struct i40e_aq_desc desc;
1646         enum i40e_status_code status;
1647         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1648
1649         if (!abilities)
1650                 return I40E_ERR_PARAM;
1651
1652         i40e_fill_default_direct_cmd_desc(&desc,
1653                                           i40e_aqc_opc_get_phy_abilities);
1654
1655         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1656         if (abilities_size > I40E_AQ_LARGE_BUF)
1657                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1658
1659         if (qualified_modules)
1660                 desc.params.external.param0 |=
1661                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1662
1663         if (report_init)
1664                 desc.params.external.param0 |=
1665                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1666
1667         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1668                                     cmd_details);
1669
1670         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1671                 status = I40E_ERR_UNKNOWN_PHY;
1672
1673         if (report_init)
1674                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1675
1676         return status;
1677 }
1678
1679 /**
1680  * i40e_aq_set_phy_config
1681  * @hw: pointer to the hw struct
1682  * @config: structure with PHY configuration to be set
1683  * @cmd_details: pointer to command details structure or NULL
1684  *
1685  * Set the various PHY configuration parameters
1686  * supported on the Port.One or more of the Set PHY config parameters may be
1687  * ignored in an MFP mode as the PF may not have the privilege to set some
1688  * of the PHY Config parameters. This status will be indicated by the
1689  * command response.
1690  **/
1691 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1692                                 struct i40e_aq_set_phy_config *config,
1693                                 struct i40e_asq_cmd_details *cmd_details)
1694 {
1695         struct i40e_aq_desc desc;
1696         struct i40e_aq_set_phy_config *cmd =
1697                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1698         enum i40e_status_code status;
1699
1700         if (!config)
1701                 return I40E_ERR_PARAM;
1702
1703         i40e_fill_default_direct_cmd_desc(&desc,
1704                                           i40e_aqc_opc_set_phy_config);
1705
1706         *cmd = *config;
1707
1708         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1709
1710         return status;
1711 }
1712
1713 /**
1714  * i40e_set_fc
1715  * @hw: pointer to the hw struct
1716  *
1717  * Set the requested flow control mode using set_phy_config.
1718  **/
1719 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1720                                   bool atomic_restart)
1721 {
1722         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1723         struct i40e_aq_get_phy_abilities_resp abilities;
1724         struct i40e_aq_set_phy_config config;
1725         enum i40e_status_code status;
1726         u8 pause_mask = 0x0;
1727
1728         *aq_failures = 0x0;
1729
1730         switch (fc_mode) {
1731         case I40E_FC_FULL:
1732                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1733                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1734                 break;
1735         case I40E_FC_RX_PAUSE:
1736                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1737                 break;
1738         case I40E_FC_TX_PAUSE:
1739                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1740                 break;
1741         default:
1742                 break;
1743         }
1744
1745         /* Get the current phy config */
1746         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1747                                               NULL);
1748         if (status) {
1749                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1750                 return status;
1751         }
1752
1753         memset(&config, 0, sizeof(config));
1754         /* clear the old pause settings */
1755         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1756                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1757         /* set the new abilities */
1758         config.abilities |= pause_mask;
1759         /* If the abilities have changed, then set the new config */
1760         if (config.abilities != abilities.abilities) {
1761                 /* Auto restart link so settings take effect */
1762                 if (atomic_restart)
1763                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1764                 /* Copy over all the old settings */
1765                 config.phy_type = abilities.phy_type;
1766                 config.link_speed = abilities.link_speed;
1767                 config.eee_capability = abilities.eee_capability;
1768                 config.eeer = abilities.eeer_val;
1769                 config.low_power_ctrl = abilities.d3_lpan;
1770                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1771
1772                 if (status)
1773                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1774         }
1775         /* Update the link info */
1776         status = i40e_update_link_info(hw);
1777         if (status) {
1778                 /* Wait a little bit (on 40G cards it sometimes takes a really
1779                  * long time for link to come back from the atomic reset)
1780                  * and try once more
1781                  */
1782                 i40e_msec_delay(1000);
1783                 status = i40e_update_link_info(hw);
1784         }
1785         if (status)
1786                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1787
1788         return status;
1789 }
1790
1791 /**
1792  * i40e_aq_set_mac_config
1793  * @hw: pointer to the hw struct
1794  * @max_frame_size: Maximum Frame Size to be supported by the port
1795  * @crc_en: Tell HW to append a CRC to outgoing frames
1796  * @pacing: Pacing configurations
1797  * @cmd_details: pointer to command details structure or NULL
1798  *
1799  * Configure MAC settings for frame size, jumbo frame support and the
1800  * addition of a CRC by the hardware.
1801  **/
1802 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1803                                 u16 max_frame_size,
1804                                 bool crc_en, u16 pacing,
1805                                 struct i40e_asq_cmd_details *cmd_details)
1806 {
1807         struct i40e_aq_desc desc;
1808         struct i40e_aq_set_mac_config *cmd =
1809                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1810         enum i40e_status_code status;
1811
1812         if (max_frame_size == 0)
1813                 return I40E_ERR_PARAM;
1814
1815         i40e_fill_default_direct_cmd_desc(&desc,
1816                                           i40e_aqc_opc_set_mac_config);
1817
1818         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1819         cmd->params = ((u8)pacing & 0x0F) << 3;
1820         if (crc_en)
1821                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1822
1823         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1824
1825         return status;
1826 }
1827
1828 /**
1829  * i40e_aq_clear_pxe_mode
1830  * @hw: pointer to the hw struct
1831  * @cmd_details: pointer to command details structure or NULL
1832  *
1833  * Tell the firmware that the driver is taking over from PXE
1834  **/
1835 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1836                         struct i40e_asq_cmd_details *cmd_details)
1837 {
1838         enum i40e_status_code status;
1839         struct i40e_aq_desc desc;
1840         struct i40e_aqc_clear_pxe *cmd =
1841                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1842
1843         i40e_fill_default_direct_cmd_desc(&desc,
1844                                           i40e_aqc_opc_clear_pxe_mode);
1845
1846         cmd->rx_cnt = 0x2;
1847
1848         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1849
1850         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1851
1852         return status;
1853 }
1854
1855 /**
1856  * i40e_aq_set_link_restart_an
1857  * @hw: pointer to the hw struct
1858  * @enable_link: if true: enable link, if false: disable link
1859  * @cmd_details: pointer to command details structure or NULL
1860  *
1861  * Sets up the link and restarts the Auto-Negotiation over the link.
1862  **/
1863 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1864                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1865 {
1866         struct i40e_aq_desc desc;
1867         struct i40e_aqc_set_link_restart_an *cmd =
1868                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1869         enum i40e_status_code status;
1870
1871         i40e_fill_default_direct_cmd_desc(&desc,
1872                                           i40e_aqc_opc_set_link_restart_an);
1873
1874         cmd->command = I40E_AQ_PHY_RESTART_AN;
1875         if (enable_link)
1876                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1877         else
1878                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1879
1880         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1881
1882         return status;
1883 }
1884
1885 /**
1886  * i40e_aq_get_link_info
1887  * @hw: pointer to the hw struct
1888  * @enable_lse: enable/disable LinkStatusEvent reporting
1889  * @link: pointer to link status structure - optional
1890  * @cmd_details: pointer to command details structure or NULL
1891  *
1892  * Returns the link status of the adapter.
1893  **/
1894 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1895                                 bool enable_lse, struct i40e_link_status *link,
1896                                 struct i40e_asq_cmd_details *cmd_details)
1897 {
1898         struct i40e_aq_desc desc;
1899         struct i40e_aqc_get_link_status *resp =
1900                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1901         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1902         enum i40e_status_code status;
1903         bool tx_pause, rx_pause;
1904         u16 command_flags;
1905
1906         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1907
1908         if (enable_lse)
1909                 command_flags = I40E_AQ_LSE_ENABLE;
1910         else
1911                 command_flags = I40E_AQ_LSE_DISABLE;
1912         resp->command_flags = CPU_TO_LE16(command_flags);
1913
1914         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1915
1916         if (status != I40E_SUCCESS)
1917                 goto aq_get_link_info_exit;
1918
1919         /* save off old link status information */
1920         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1921                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1922
1923         /* update link status */
1924         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1925         hw->phy.media_type = i40e_get_media_type(hw);
1926         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1927         hw_link_info->link_info = resp->link_info;
1928         hw_link_info->an_info = resp->an_info;
1929         hw_link_info->ext_info = resp->ext_info;
1930         hw_link_info->loopback = resp->loopback;
1931         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1932         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1933
1934         /* update fc info */
1935         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1936         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1937         if (tx_pause & rx_pause)
1938                 hw->fc.current_mode = I40E_FC_FULL;
1939         else if (tx_pause)
1940                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1941         else if (rx_pause)
1942                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1943         else
1944                 hw->fc.current_mode = I40E_FC_NONE;
1945
1946         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1947                 hw_link_info->crc_enable = true;
1948         else
1949                 hw_link_info->crc_enable = false;
1950
1951         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1952                 hw_link_info->lse_enable = true;
1953         else
1954                 hw_link_info->lse_enable = false;
1955
1956         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1957              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1958                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1959
1960         /* save link status information */
1961         if (link)
1962                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1963                             I40E_NONDMA_TO_NONDMA);
1964
1965         /* flag cleared so helper functions don't call AQ again */
1966         hw->phy.get_link_info = false;
1967
1968 aq_get_link_info_exit:
1969         return status;
1970 }
1971
1972 /**
1973  * i40e_aq_set_phy_int_mask
1974  * @hw: pointer to the hw struct
1975  * @mask: interrupt mask to be set
1976  * @cmd_details: pointer to command details structure or NULL
1977  *
1978  * Set link interrupt mask.
1979  **/
1980 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1981                                 u16 mask,
1982                                 struct i40e_asq_cmd_details *cmd_details)
1983 {
1984         struct i40e_aq_desc desc;
1985         struct i40e_aqc_set_phy_int_mask *cmd =
1986                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1987         enum i40e_status_code status;
1988
1989         i40e_fill_default_direct_cmd_desc(&desc,
1990                                           i40e_aqc_opc_set_phy_int_mask);
1991
1992         cmd->event_mask = CPU_TO_LE16(mask);
1993
1994         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1995
1996         return status;
1997 }
1998
1999 /**
2000  * i40e_aq_get_local_advt_reg
2001  * @hw: pointer to the hw struct
2002  * @advt_reg: local AN advertisement register value
2003  * @cmd_details: pointer to command details structure or NULL
2004  *
2005  * Get the Local AN advertisement register value.
2006  **/
2007 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2008                                 u64 *advt_reg,
2009                                 struct i40e_asq_cmd_details *cmd_details)
2010 {
2011         struct i40e_aq_desc desc;
2012         struct i40e_aqc_an_advt_reg *resp =
2013                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2014         enum i40e_status_code status;
2015
2016         i40e_fill_default_direct_cmd_desc(&desc,
2017                                           i40e_aqc_opc_get_local_advt_reg);
2018
2019         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2020
2021         if (status != I40E_SUCCESS)
2022                 goto aq_get_local_advt_reg_exit;
2023
2024         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2025         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2026
2027 aq_get_local_advt_reg_exit:
2028         return status;
2029 }
2030
2031 /**
2032  * i40e_aq_set_local_advt_reg
2033  * @hw: pointer to the hw struct
2034  * @advt_reg: local AN advertisement register value
2035  * @cmd_details: pointer to command details structure or NULL
2036  *
2037  * Get the Local AN advertisement register value.
2038  **/
2039 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2040                                 u64 advt_reg,
2041                                 struct i40e_asq_cmd_details *cmd_details)
2042 {
2043         struct i40e_aq_desc desc;
2044         struct i40e_aqc_an_advt_reg *cmd =
2045                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2046         enum i40e_status_code status;
2047
2048         i40e_fill_default_direct_cmd_desc(&desc,
2049                                           i40e_aqc_opc_get_local_advt_reg);
2050
2051         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2052         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2053
2054         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2055
2056         return status;
2057 }
2058
2059 /**
2060  * i40e_aq_get_partner_advt
2061  * @hw: pointer to the hw struct
2062  * @advt_reg: AN partner advertisement register value
2063  * @cmd_details: pointer to command details structure or NULL
2064  *
2065  * Get the link partner AN advertisement register value.
2066  **/
2067 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2068                                 u64 *advt_reg,
2069                                 struct i40e_asq_cmd_details *cmd_details)
2070 {
2071         struct i40e_aq_desc desc;
2072         struct i40e_aqc_an_advt_reg *resp =
2073                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2074         enum i40e_status_code status;
2075
2076         i40e_fill_default_direct_cmd_desc(&desc,
2077                                           i40e_aqc_opc_get_partner_advt);
2078
2079         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2080
2081         if (status != I40E_SUCCESS)
2082                 goto aq_get_partner_advt_exit;
2083
2084         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2085         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2086
2087 aq_get_partner_advt_exit:
2088         return status;
2089 }
2090
2091 /**
2092  * i40e_aq_set_lb_modes
2093  * @hw: pointer to the hw struct
2094  * @lb_modes: loopback mode to be set
2095  * @cmd_details: pointer to command details structure or NULL
2096  *
2097  * Sets loopback modes.
2098  **/
2099 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2100                                 u16 lb_modes,
2101                                 struct i40e_asq_cmd_details *cmd_details)
2102 {
2103         struct i40e_aq_desc desc;
2104         struct i40e_aqc_set_lb_mode *cmd =
2105                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2106         enum i40e_status_code status;
2107
2108         i40e_fill_default_direct_cmd_desc(&desc,
2109                                           i40e_aqc_opc_set_lb_modes);
2110
2111         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2112
2113         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2114
2115         return status;
2116 }
2117
2118 /**
2119  * i40e_aq_set_phy_debug
2120  * @hw: pointer to the hw struct
2121  * @cmd_flags: debug command flags
2122  * @cmd_details: pointer to command details structure or NULL
2123  *
2124  * Reset the external PHY.
2125  **/
2126 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2127                                 struct i40e_asq_cmd_details *cmd_details)
2128 {
2129         struct i40e_aq_desc desc;
2130         struct i40e_aqc_set_phy_debug *cmd =
2131                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2132         enum i40e_status_code status;
2133
2134         i40e_fill_default_direct_cmd_desc(&desc,
2135                                           i40e_aqc_opc_set_phy_debug);
2136
2137         cmd->command_flags = cmd_flags;
2138
2139         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2140
2141         return status;
2142 }
2143
2144 /**
2145  * i40e_aq_add_vsi
2146  * @hw: pointer to the hw struct
2147  * @vsi_ctx: pointer to a vsi context struct
2148  * @cmd_details: pointer to command details structure or NULL
2149  *
2150  * Add a VSI context to the hardware.
2151 **/
2152 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2153                                 struct i40e_vsi_context *vsi_ctx,
2154                                 struct i40e_asq_cmd_details *cmd_details)
2155 {
2156         struct i40e_aq_desc desc;
2157         struct i40e_aqc_add_get_update_vsi *cmd =
2158                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2159         struct i40e_aqc_add_get_update_vsi_completion *resp =
2160                 (struct i40e_aqc_add_get_update_vsi_completion *)
2161                 &desc.params.raw;
2162         enum i40e_status_code status;
2163
2164         i40e_fill_default_direct_cmd_desc(&desc,
2165                                           i40e_aqc_opc_add_vsi);
2166
2167         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2168         cmd->connection_type = vsi_ctx->connection_type;
2169         cmd->vf_id = vsi_ctx->vf_num;
2170         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2171
2172         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2173
2174         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2175                                     sizeof(vsi_ctx->info), cmd_details);
2176
2177         if (status != I40E_SUCCESS)
2178                 goto aq_add_vsi_exit;
2179
2180         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2181         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2182         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2183         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2184
2185 aq_add_vsi_exit:
2186         return status;
2187 }
2188
2189 /**
2190  * i40e_aq_set_default_vsi
2191  * @hw: pointer to the hw struct
2192  * @seid: vsi number
2193  * @cmd_details: pointer to command details structure or NULL
2194  **/
2195 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2196                                 u16 seid,
2197                                 struct i40e_asq_cmd_details *cmd_details)
2198 {
2199         struct i40e_aq_desc desc;
2200         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2201                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2202                 &desc.params.raw;
2203         enum i40e_status_code status;
2204
2205         i40e_fill_default_direct_cmd_desc(&desc,
2206                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2207
2208         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2209         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2210         cmd->seid = CPU_TO_LE16(seid);
2211
2212         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2213
2214         return status;
2215 }
2216
2217 /**
2218  * i40e_aq_set_vsi_unicast_promiscuous
2219  * @hw: pointer to the hw struct
2220  * @seid: vsi number
2221  * @set: set unicast promiscuous enable/disable
2222  * @cmd_details: pointer to command details structure or NULL
2223  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2224  **/
2225 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2226                                 u16 seid, bool set,
2227                                 struct i40e_asq_cmd_details *cmd_details,
2228                                 bool rx_only_promisc)
2229 {
2230         struct i40e_aq_desc desc;
2231         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2232                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2233         enum i40e_status_code status;
2234         u16 flags = 0;
2235
2236         i40e_fill_default_direct_cmd_desc(&desc,
2237                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2238
2239         if (set) {
2240                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2241                 if (rx_only_promisc &&
2242                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2243                      (hw->aq.api_maj_ver > 1)))
2244                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2245         }
2246
2247         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2248
2249         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2250         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2251              (hw->aq.api_maj_ver > 1))
2252                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2253
2254         cmd->seid = CPU_TO_LE16(seid);
2255         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2256
2257         return status;
2258 }
2259
2260 /**
2261  * i40e_aq_set_vsi_multicast_promiscuous
2262  * @hw: pointer to the hw struct
2263  * @seid: vsi number
2264  * @set: set multicast promiscuous enable/disable
2265  * @cmd_details: pointer to command details structure or NULL
2266  **/
2267 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2268                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2269 {
2270         struct i40e_aq_desc desc;
2271         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2272                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2273         enum i40e_status_code status;
2274         u16 flags = 0;
2275
2276         i40e_fill_default_direct_cmd_desc(&desc,
2277                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2278
2279         if (set)
2280                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2281
2282         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2283
2284         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2285
2286         cmd->seid = CPU_TO_LE16(seid);
2287         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2288
2289         return status;
2290 }
2291
2292 /**
2293  * i40e_aq_set_vsi_mc_promisc_on_vlan
2294  * @hw: pointer to the hw struct
2295  * @seid: vsi number
2296  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2297  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2298  * @cmd_details: pointer to command details structure or NULL
2299  **/
2300 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2301                                 u16 seid, bool enable, u16 vid,
2302                                 struct i40e_asq_cmd_details *cmd_details)
2303 {
2304         struct i40e_aq_desc desc;
2305         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2306                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2307         enum i40e_status_code status;
2308         u16 flags = 0;
2309
2310         i40e_fill_default_direct_cmd_desc(&desc,
2311                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2312
2313         if (enable)
2314                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2315
2316         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2317         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2318         cmd->seid = CPU_TO_LE16(seid);
2319         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2320
2321         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2322
2323         return status;
2324 }
2325
2326 /**
2327  * i40e_aq_set_vsi_uc_promisc_on_vlan
2328  * @hw: pointer to the hw struct
2329  * @seid: vsi number
2330  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2331  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2332  * @cmd_details: pointer to command details structure or NULL
2333  **/
2334 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2335                                 u16 seid, bool enable, u16 vid,
2336                                 struct i40e_asq_cmd_details *cmd_details)
2337 {
2338         struct i40e_aq_desc desc;
2339         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2340                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2341         enum i40e_status_code status;
2342         u16 flags = 0;
2343
2344         i40e_fill_default_direct_cmd_desc(&desc,
2345                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2346
2347         if (enable)
2348                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2349
2350         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2351         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2352         cmd->seid = CPU_TO_LE16(seid);
2353         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2354
2355         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2356
2357         return status;
2358 }
2359
2360 /**
2361  * i40e_aq_set_vsi_broadcast
2362  * @hw: pointer to the hw struct
2363  * @seid: vsi number
2364  * @set_filter: true to set filter, false to clear filter
2365  * @cmd_details: pointer to command details structure or NULL
2366  *
2367  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2368  **/
2369 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2370                                 u16 seid, bool set_filter,
2371                                 struct i40e_asq_cmd_details *cmd_details)
2372 {
2373         struct i40e_aq_desc desc;
2374         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2375                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2376         enum i40e_status_code status;
2377
2378         i40e_fill_default_direct_cmd_desc(&desc,
2379                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2380
2381         if (set_filter)
2382                 cmd->promiscuous_flags
2383                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2384         else
2385                 cmd->promiscuous_flags
2386                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2387
2388         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2389         cmd->seid = CPU_TO_LE16(seid);
2390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2391
2392         return status;
2393 }
2394
2395 /**
2396  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2397  * @hw: pointer to the hw struct
2398  * @seid: vsi number
2399  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2400  * @cmd_details: pointer to command details structure or NULL
2401  **/
2402 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2403                                 u16 seid, bool enable,
2404                                 struct i40e_asq_cmd_details *cmd_details)
2405 {
2406         struct i40e_aq_desc desc;
2407         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2408                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2409         enum i40e_status_code status;
2410         u16 flags = 0;
2411
2412         i40e_fill_default_direct_cmd_desc(&desc,
2413                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2414         if (enable)
2415                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2416
2417         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2418         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2419         cmd->seid = CPU_TO_LE16(seid);
2420
2421         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2422
2423         return status;
2424 }
2425
2426 /**
2427  * i40e_get_vsi_params - get VSI configuration info
2428  * @hw: pointer to the hw struct
2429  * @vsi_ctx: pointer to a vsi context struct
2430  * @cmd_details: pointer to command details structure or NULL
2431  **/
2432 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2433                                 struct i40e_vsi_context *vsi_ctx,
2434                                 struct i40e_asq_cmd_details *cmd_details)
2435 {
2436         struct i40e_aq_desc desc;
2437         struct i40e_aqc_add_get_update_vsi *cmd =
2438                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2439         struct i40e_aqc_add_get_update_vsi_completion *resp =
2440                 (struct i40e_aqc_add_get_update_vsi_completion *)
2441                 &desc.params.raw;
2442         enum i40e_status_code status;
2443
2444         UNREFERENCED_1PARAMETER(cmd_details);
2445         i40e_fill_default_direct_cmd_desc(&desc,
2446                                           i40e_aqc_opc_get_vsi_parameters);
2447
2448         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2449
2450         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2451
2452         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2453                                     sizeof(vsi_ctx->info), NULL);
2454
2455         if (status != I40E_SUCCESS)
2456                 goto aq_get_vsi_params_exit;
2457
2458         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2459         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2460         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2461         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2462
2463 aq_get_vsi_params_exit:
2464         return status;
2465 }
2466
2467 /**
2468  * i40e_aq_update_vsi_params
2469  * @hw: pointer to the hw struct
2470  * @vsi_ctx: pointer to a vsi context struct
2471  * @cmd_details: pointer to command details structure or NULL
2472  *
2473  * Update a VSI context.
2474  **/
2475 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2476                                 struct i40e_vsi_context *vsi_ctx,
2477                                 struct i40e_asq_cmd_details *cmd_details)
2478 {
2479         struct i40e_aq_desc desc;
2480         struct i40e_aqc_add_get_update_vsi *cmd =
2481                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2482         struct i40e_aqc_add_get_update_vsi_completion *resp =
2483                 (struct i40e_aqc_add_get_update_vsi_completion *)
2484                 &desc.params.raw;
2485         enum i40e_status_code status;
2486
2487         i40e_fill_default_direct_cmd_desc(&desc,
2488                                           i40e_aqc_opc_update_vsi_parameters);
2489         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2490
2491         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2492
2493         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2494                                     sizeof(vsi_ctx->info), cmd_details);
2495
2496         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2497         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2498
2499         return status;
2500 }
2501
2502 /**
2503  * i40e_aq_get_switch_config
2504  * @hw: pointer to the hardware structure
2505  * @buf: pointer to the result buffer
2506  * @buf_size: length of input buffer
2507  * @start_seid: seid to start for the report, 0 == beginning
2508  * @cmd_details: pointer to command details structure or NULL
2509  *
2510  * Fill the buf with switch configuration returned from AdminQ command
2511  **/
2512 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2513                                 struct i40e_aqc_get_switch_config_resp *buf,
2514                                 u16 buf_size, u16 *start_seid,
2515                                 struct i40e_asq_cmd_details *cmd_details)
2516 {
2517         struct i40e_aq_desc desc;
2518         struct i40e_aqc_switch_seid *scfg =
2519                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2520         enum i40e_status_code status;
2521
2522         i40e_fill_default_direct_cmd_desc(&desc,
2523                                           i40e_aqc_opc_get_switch_config);
2524         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2525         if (buf_size > I40E_AQ_LARGE_BUF)
2526                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2527         scfg->seid = CPU_TO_LE16(*start_seid);
2528
2529         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2530         *start_seid = LE16_TO_CPU(scfg->seid);
2531
2532         return status;
2533 }
2534
2535 /**
2536  * i40e_aq_set_switch_config
2537  * @hw: pointer to the hardware structure
2538  * @flags: bit flag values to set
2539  * @valid_flags: which bit flags to set
2540  * @cmd_details: pointer to command details structure or NULL
2541  *
2542  * Set switch configuration bits
2543  **/
2544 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2545                                 u16 flags, u16 valid_flags,
2546                                 struct i40e_asq_cmd_details *cmd_details)
2547 {
2548         struct i40e_aq_desc desc;
2549         struct i40e_aqc_set_switch_config *scfg =
2550                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2551         enum i40e_status_code status;
2552
2553         i40e_fill_default_direct_cmd_desc(&desc,
2554                                           i40e_aqc_opc_set_switch_config);
2555         scfg->flags = CPU_TO_LE16(flags);
2556         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2557
2558         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2559
2560         return status;
2561 }
2562
2563 /**
2564  * i40e_aq_get_firmware_version
2565  * @hw: pointer to the hw struct
2566  * @fw_major_version: firmware major version
2567  * @fw_minor_version: firmware minor version
2568  * @fw_build: firmware build number
2569  * @api_major_version: major queue version
2570  * @api_minor_version: minor queue version
2571  * @cmd_details: pointer to command details structure or NULL
2572  *
2573  * Get the firmware version from the admin queue commands
2574  **/
2575 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2576                                 u16 *fw_major_version, u16 *fw_minor_version,
2577                                 u32 *fw_build,
2578                                 u16 *api_major_version, u16 *api_minor_version,
2579                                 struct i40e_asq_cmd_details *cmd_details)
2580 {
2581         struct i40e_aq_desc desc;
2582         struct i40e_aqc_get_version *resp =
2583                 (struct i40e_aqc_get_version *)&desc.params.raw;
2584         enum i40e_status_code status;
2585
2586         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2587
2588         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2589
2590         if (status == I40E_SUCCESS) {
2591                 if (fw_major_version != NULL)
2592                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2593                 if (fw_minor_version != NULL)
2594                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2595                 if (fw_build != NULL)
2596                         *fw_build = LE32_TO_CPU(resp->fw_build);
2597                 if (api_major_version != NULL)
2598                         *api_major_version = LE16_TO_CPU(resp->api_major);
2599                 if (api_minor_version != NULL)
2600                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2601
2602                 /* A workaround to fix the API version in SW */
2603                 if (api_major_version && api_minor_version &&
2604                     fw_major_version && fw_minor_version &&
2605                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2606                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2607                      (*fw_major_version > 4)))
2608                         *api_minor_version = 2;
2609         }
2610
2611         return status;
2612 }
2613
2614 /**
2615  * i40e_aq_send_driver_version
2616  * @hw: pointer to the hw struct
2617  * @dv: driver's major, minor version
2618  * @cmd_details: pointer to command details structure or NULL
2619  *
2620  * Send the driver version to the firmware
2621  **/
2622 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2623                                 struct i40e_driver_version *dv,
2624                                 struct i40e_asq_cmd_details *cmd_details)
2625 {
2626         struct i40e_aq_desc desc;
2627         struct i40e_aqc_driver_version *cmd =
2628                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2629         enum i40e_status_code status;
2630         u16 len;
2631
2632         if (dv == NULL)
2633                 return I40E_ERR_PARAM;
2634
2635         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2636
2637         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2638         cmd->driver_major_ver = dv->major_version;
2639         cmd->driver_minor_ver = dv->minor_version;
2640         cmd->driver_build_ver = dv->build_version;
2641         cmd->driver_subbuild_ver = dv->subbuild_version;
2642
2643         len = 0;
2644         while (len < sizeof(dv->driver_string) &&
2645                (dv->driver_string[len] < 0x80) &&
2646                dv->driver_string[len])
2647                 len++;
2648         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2649                                        len, cmd_details);
2650
2651         return status;
2652 }
2653
2654 /**
2655  * i40e_get_link_status - get status of the HW network link
2656  * @hw: pointer to the hw struct
2657  * @link_up: pointer to bool (true/false = linkup/linkdown)
2658  *
2659  * Variable link_up true if link is up, false if link is down.
2660  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2661  *
2662  * Side effect: LinkStatusEvent reporting becomes enabled
2663  **/
2664 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2665 {
2666         enum i40e_status_code status = I40E_SUCCESS;
2667
2668         if (hw->phy.get_link_info) {
2669                 status = i40e_update_link_info(hw);
2670
2671                 if (status != I40E_SUCCESS)
2672                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2673                                    status);
2674         }
2675
2676         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2677
2678         return status;
2679 }
2680
2681 /**
2682  * i40e_updatelink_status - update status of the HW network link
2683  * @hw: pointer to the hw struct
2684  **/
2685 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2686 {
2687         struct i40e_aq_get_phy_abilities_resp abilities;
2688         enum i40e_status_code status = I40E_SUCCESS;
2689
2690         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2691         if (status)
2692                 return status;
2693
2694         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2695                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2696                                                       &abilities, NULL);
2697                 if (status)
2698                         return status;
2699
2700                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2701                         sizeof(hw->phy.link_info.module_type));
2702         }
2703         return status;
2704 }
2705
2706
2707 /**
2708  * i40e_get_link_speed
2709  * @hw: pointer to the hw struct
2710  *
2711  * Returns the link speed of the adapter.
2712  **/
2713 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2714 {
2715         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2716         enum i40e_status_code status = I40E_SUCCESS;
2717
2718         if (hw->phy.get_link_info) {
2719                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2720
2721                 if (status != I40E_SUCCESS)
2722                         goto i40e_link_speed_exit;
2723         }
2724
2725         speed = hw->phy.link_info.link_speed;
2726
2727 i40e_link_speed_exit:
2728         return speed;
2729 }
2730
2731 /**
2732  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2733  * @hw: pointer to the hw struct
2734  * @uplink_seid: the MAC or other gizmo SEID
2735  * @downlink_seid: the VSI SEID
2736  * @enabled_tc: bitmap of TCs to be enabled
2737  * @default_port: true for default port VSI, false for control port
2738  * @veb_seid: pointer to where to put the resulting VEB SEID
2739  * @enable_stats: true to turn on VEB stats
2740  * @cmd_details: pointer to command details structure or NULL
2741  *
2742  * This asks the FW to add a VEB between the uplink and downlink
2743  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2744  **/
2745 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2746                                 u16 downlink_seid, u8 enabled_tc,
2747                                 bool default_port, u16 *veb_seid,
2748                                 bool enable_stats,
2749                                 struct i40e_asq_cmd_details *cmd_details)
2750 {
2751         struct i40e_aq_desc desc;
2752         struct i40e_aqc_add_veb *cmd =
2753                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2754         struct i40e_aqc_add_veb_completion *resp =
2755                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2756         enum i40e_status_code status;
2757         u16 veb_flags = 0;
2758
2759         /* SEIDs need to either both be set or both be 0 for floating VEB */
2760         if (!!uplink_seid != !!downlink_seid)
2761                 return I40E_ERR_PARAM;
2762
2763         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2764
2765         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2766         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2767         cmd->enable_tcs = enabled_tc;
2768         if (!uplink_seid)
2769                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2770         if (default_port)
2771                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2772         else
2773                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2774
2775         /* reverse logic here: set the bitflag to disable the stats */
2776         if (!enable_stats)
2777                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2778
2779         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2780
2781         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2782
2783         if (!status && veb_seid)
2784                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2785
2786         return status;
2787 }
2788
2789 /**
2790  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2791  * @hw: pointer to the hw struct
2792  * @veb_seid: the SEID of the VEB to query
2793  * @switch_id: the uplink switch id
2794  * @floating: set to true if the VEB is floating
2795  * @statistic_index: index of the stats counter block for this VEB
2796  * @vebs_used: number of VEB's used by function
2797  * @vebs_free: total VEB's not reserved by any function
2798  * @cmd_details: pointer to command details structure or NULL
2799  *
2800  * This retrieves the parameters for a particular VEB, specified by
2801  * uplink_seid, and returns them to the caller.
2802  **/
2803 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2804                                 u16 veb_seid, u16 *switch_id,
2805                                 bool *floating, u16 *statistic_index,
2806                                 u16 *vebs_used, u16 *vebs_free,
2807                                 struct i40e_asq_cmd_details *cmd_details)
2808 {
2809         struct i40e_aq_desc desc;
2810         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2811                 (struct i40e_aqc_get_veb_parameters_completion *)
2812                 &desc.params.raw;
2813         enum i40e_status_code status;
2814
2815         if (veb_seid == 0)
2816                 return I40E_ERR_PARAM;
2817
2818         i40e_fill_default_direct_cmd_desc(&desc,
2819                                           i40e_aqc_opc_get_veb_parameters);
2820         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2821
2822         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2823         if (status)
2824                 goto get_veb_exit;
2825
2826         if (switch_id)
2827                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2828         if (statistic_index)
2829                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2830         if (vebs_used)
2831                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2832         if (vebs_free)
2833                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2834         if (floating) {
2835                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2836
2837                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2838                         *floating = true;
2839                 else
2840                         *floating = false;
2841         }
2842
2843 get_veb_exit:
2844         return status;
2845 }
2846
2847 /**
2848  * i40e_aq_add_macvlan
2849  * @hw: pointer to the hw struct
2850  * @seid: VSI for the mac address
2851  * @mv_list: list of macvlans to be added
2852  * @count: length of the list
2853  * @cmd_details: pointer to command details structure or NULL
2854  *
2855  * Add MAC/VLAN addresses to the HW filtering
2856  **/
2857 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2858                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2859                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2860 {
2861         struct i40e_aq_desc desc;
2862         struct i40e_aqc_macvlan *cmd =
2863                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2864         enum i40e_status_code status;
2865         u16 buf_size;
2866         int i;
2867
2868         if (count == 0 || !mv_list || !hw)
2869                 return I40E_ERR_PARAM;
2870
2871         buf_size = count * sizeof(*mv_list);
2872
2873         /* prep the rest of the request */
2874         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2875         cmd->num_addresses = CPU_TO_LE16(count);
2876         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2877         cmd->seid[1] = 0;
2878         cmd->seid[2] = 0;
2879
2880         for (i = 0; i < count; i++)
2881                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2882                         mv_list[i].flags |=
2883                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2884
2885         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2886         if (buf_size > I40E_AQ_LARGE_BUF)
2887                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2888
2889         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2890                                        cmd_details);
2891
2892         return status;
2893 }
2894
2895 /**
2896  * i40e_aq_remove_macvlan
2897  * @hw: pointer to the hw struct
2898  * @seid: VSI for the mac address
2899  * @mv_list: list of macvlans to be removed
2900  * @count: length of the list
2901  * @cmd_details: pointer to command details structure or NULL
2902  *
2903  * Remove MAC/VLAN addresses from the HW filtering
2904  **/
2905 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2906                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2907                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2908 {
2909         struct i40e_aq_desc desc;
2910         struct i40e_aqc_macvlan *cmd =
2911                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2912         enum i40e_status_code status;
2913         u16 buf_size;
2914
2915         if (count == 0 || !mv_list || !hw)
2916                 return I40E_ERR_PARAM;
2917
2918         buf_size = count * sizeof(*mv_list);
2919
2920         /* prep the rest of the request */
2921         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2922         cmd->num_addresses = CPU_TO_LE16(count);
2923         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2924         cmd->seid[1] = 0;
2925         cmd->seid[2] = 0;
2926
2927         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2928         if (buf_size > I40E_AQ_LARGE_BUF)
2929                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2930
2931         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2932                                        cmd_details);
2933
2934         return status;
2935 }
2936
2937 /**
2938  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2939  * @hw: pointer to the hw struct
2940  * @opcode: AQ opcode for add or delete mirror rule
2941  * @sw_seid: Switch SEID (to which rule refers)
2942  * @rule_type: Rule Type (ingress/egress/VLAN)
2943  * @id: Destination VSI SEID or Rule ID
2944  * @count: length of the list
2945  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2946  * @cmd_details: pointer to command details structure or NULL
2947  * @rule_id: Rule ID returned from FW
2948  * @rule_used: Number of rules used in internal switch
2949  * @rule_free: Number of rules free in internal switch
2950  *
2951  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2952  * VEBs/VEPA elements only
2953  **/
2954 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2955                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2956                         u16 count, __le16 *mr_list,
2957                         struct i40e_asq_cmd_details *cmd_details,
2958                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2959 {
2960         struct i40e_aq_desc desc;
2961         struct i40e_aqc_add_delete_mirror_rule *cmd =
2962                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2963         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2964         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2965         enum i40e_status_code status;
2966         u16 buf_size;
2967
2968         buf_size = count * sizeof(*mr_list);
2969
2970         /* prep the rest of the request */
2971         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2972         cmd->seid = CPU_TO_LE16(sw_seid);
2973         cmd->rule_type = CPU_TO_LE16(rule_type &
2974                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2975         cmd->num_entries = CPU_TO_LE16(count);
2976         /* Dest VSI for add, rule_id for delete */
2977         cmd->destination = CPU_TO_LE16(id);
2978         if (mr_list) {
2979                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2980                                                 I40E_AQ_FLAG_RD));
2981                 if (buf_size > I40E_AQ_LARGE_BUF)
2982                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2983         }
2984
2985         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2986                                        cmd_details);
2987         if (status == I40E_SUCCESS ||
2988             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2989                 if (rule_id)
2990                         *rule_id = LE16_TO_CPU(resp->rule_id);
2991                 if (rules_used)
2992                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2993                 if (rules_free)
2994                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2995         }
2996         return status;
2997 }
2998
2999 /**
3000  * i40e_aq_add_mirrorrule - add a mirror rule
3001  * @hw: pointer to the hw struct
3002  * @sw_seid: Switch SEID (to which rule refers)
3003  * @rule_type: Rule Type (ingress/egress/VLAN)
3004  * @dest_vsi: SEID of VSI to which packets will be mirrored
3005  * @count: length of the list
3006  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3007  * @cmd_details: pointer to command details structure or NULL
3008  * @rule_id: Rule ID returned from FW
3009  * @rule_used: Number of rules used in internal switch
3010  * @rule_free: Number of rules free in internal switch
3011  *
3012  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3013  **/
3014 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3015                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3016                         struct i40e_asq_cmd_details *cmd_details,
3017                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3018 {
3019         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3020             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3021                 if (count == 0 || !mr_list)
3022                         return I40E_ERR_PARAM;
3023         }
3024
3025         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3026                                   rule_type, dest_vsi, count, mr_list,
3027                                   cmd_details, rule_id, rules_used, rules_free);
3028 }
3029
3030 /**
3031  * i40e_aq_delete_mirrorrule - delete a mirror rule
3032  * @hw: pointer to the hw struct
3033  * @sw_seid: Switch SEID (to which rule refers)
3034  * @rule_type: Rule Type (ingress/egress/VLAN)
3035  * @count: length of the list
3036  * @rule_id: Rule ID that is returned in the receive desc as part of
3037  *              add_mirrorrule.
3038  * @mr_list: list of mirrored VLAN IDs to be removed
3039  * @cmd_details: pointer to command details structure or NULL
3040  * @rule_used: Number of rules used in internal switch
3041  * @rule_free: Number of rules free in internal switch
3042  *
3043  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3044  **/
3045 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3046                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3047                         struct i40e_asq_cmd_details *cmd_details,
3048                         u16 *rules_used, u16 *rules_free)
3049 {
3050         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3051         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3052                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3053                  * mirroring. For other rule_type, count and rule_type should
3054                  * not matter.
3055                  */
3056                 if (count == 0 || !mr_list)
3057                         return I40E_ERR_PARAM;
3058         }
3059
3060         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3061                                   rule_type, rule_id, count, mr_list,
3062                                   cmd_details, NULL, rules_used, rules_free);
3063 }
3064
3065 /**
3066  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3067  * @hw: pointer to the hw struct
3068  * @seid: VSI for the vlan filters
3069  * @v_list: list of vlan filters to be added
3070  * @count: length of the list
3071  * @cmd_details: pointer to command details structure or NULL
3072  **/
3073 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3074                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3075                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3076 {
3077         struct i40e_aq_desc desc;
3078         struct i40e_aqc_macvlan *cmd =
3079                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3080         enum i40e_status_code status;
3081         u16 buf_size;
3082
3083         if (count == 0 || !v_list || !hw)
3084                 return I40E_ERR_PARAM;
3085
3086         buf_size = count * sizeof(*v_list);
3087
3088         /* prep the rest of the request */
3089         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3090         cmd->num_addresses = CPU_TO_LE16(count);
3091         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3092         cmd->seid[1] = 0;
3093         cmd->seid[2] = 0;
3094
3095         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3096         if (buf_size > I40E_AQ_LARGE_BUF)
3097                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3098
3099         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3100                                        cmd_details);
3101
3102         return status;
3103 }
3104
3105 /**
3106  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3107  * @hw: pointer to the hw struct
3108  * @seid: VSI for the vlan filters
3109  * @v_list: list of macvlans to be removed
3110  * @count: length of the list
3111  * @cmd_details: pointer to command details structure or NULL
3112  **/
3113 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3114                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3115                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3116 {
3117         struct i40e_aq_desc desc;
3118         struct i40e_aqc_macvlan *cmd =
3119                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3120         enum i40e_status_code status;
3121         u16 buf_size;
3122
3123         if (count == 0 || !v_list || !hw)
3124                 return I40E_ERR_PARAM;
3125
3126         buf_size = count * sizeof(*v_list);
3127
3128         /* prep the rest of the request */
3129         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3130         cmd->num_addresses = CPU_TO_LE16(count);
3131         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3132         cmd->seid[1] = 0;
3133         cmd->seid[2] = 0;
3134
3135         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3136         if (buf_size > I40E_AQ_LARGE_BUF)
3137                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3138
3139         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3140                                        cmd_details);
3141
3142         return status;
3143 }
3144
3145 /**
3146  * i40e_aq_send_msg_to_vf
3147  * @hw: pointer to the hardware structure
3148  * @vfid: vf id to send msg
3149  * @v_opcode: opcodes for VF-PF communication
3150  * @v_retval: return error code
3151  * @msg: pointer to the msg buffer
3152  * @msglen: msg length
3153  * @cmd_details: pointer to command details
3154  *
3155  * send msg to vf
3156  **/
3157 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3158                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3159                                 struct i40e_asq_cmd_details *cmd_details)
3160 {
3161         struct i40e_aq_desc desc;
3162         struct i40e_aqc_pf_vf_message *cmd =
3163                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3164         enum i40e_status_code status;
3165
3166         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3167         cmd->id = CPU_TO_LE32(vfid);
3168         desc.cookie_high = CPU_TO_LE32(v_opcode);
3169         desc.cookie_low = CPU_TO_LE32(v_retval);
3170         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3171         if (msglen) {
3172                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3173                                                 I40E_AQ_FLAG_RD));
3174                 if (msglen > I40E_AQ_LARGE_BUF)
3175                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3176                 desc.datalen = CPU_TO_LE16(msglen);
3177         }
3178         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3179
3180         return status;
3181 }
3182
3183 /**
3184  * i40e_aq_debug_read_register
3185  * @hw: pointer to the hw struct
3186  * @reg_addr: register address
3187  * @reg_val: register value
3188  * @cmd_details: pointer to command details structure or NULL
3189  *
3190  * Read the register using the admin queue commands
3191  **/
3192 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3193                                 u32 reg_addr, u64 *reg_val,
3194                                 struct i40e_asq_cmd_details *cmd_details)
3195 {
3196         struct i40e_aq_desc desc;
3197         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3198                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3199         enum i40e_status_code status;
3200
3201         if (reg_val == NULL)
3202                 return I40E_ERR_PARAM;
3203
3204         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3205
3206         cmd_resp->address = CPU_TO_LE32(reg_addr);
3207
3208         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3209
3210         if (status == I40E_SUCCESS) {
3211                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3212                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3213         }
3214
3215         return status;
3216 }
3217
3218 /**
3219  * i40e_aq_debug_write_register
3220  * @hw: pointer to the hw struct
3221  * @reg_addr: register address
3222  * @reg_val: register value
3223  * @cmd_details: pointer to command details structure or NULL
3224  *
3225  * Write to a register using the admin queue commands
3226  **/
3227 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3228                                 u32 reg_addr, u64 reg_val,
3229                                 struct i40e_asq_cmd_details *cmd_details)
3230 {
3231         struct i40e_aq_desc desc;
3232         struct i40e_aqc_debug_reg_read_write *cmd =
3233                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3234         enum i40e_status_code status;
3235
3236         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3237
3238         cmd->address = CPU_TO_LE32(reg_addr);
3239         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3240         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3241
3242         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3243
3244         return status;
3245 }
3246
3247 /**
3248  * i40e_aq_request_resource
3249  * @hw: pointer to the hw struct
3250  * @resource: resource id
3251  * @access: access type
3252  * @sdp_number: resource number
3253  * @timeout: the maximum time in ms that the driver may hold the resource
3254  * @cmd_details: pointer to command details structure or NULL
3255  *
3256  * requests common resource using the admin queue commands
3257  **/
3258 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3259                                 enum i40e_aq_resources_ids resource,
3260                                 enum i40e_aq_resource_access_type access,
3261                                 u8 sdp_number, u64 *timeout,
3262                                 struct i40e_asq_cmd_details *cmd_details)
3263 {
3264         struct i40e_aq_desc desc;
3265         struct i40e_aqc_request_resource *cmd_resp =
3266                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3267         enum i40e_status_code status;
3268
3269         DEBUGFUNC("i40e_aq_request_resource");
3270
3271         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3272
3273         cmd_resp->resource_id = CPU_TO_LE16(resource);
3274         cmd_resp->access_type = CPU_TO_LE16(access);
3275         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3276
3277         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3278         /* The completion specifies the maximum time in ms that the driver
3279          * may hold the resource in the Timeout field.
3280          * If the resource is held by someone else, the command completes with
3281          * busy return value and the timeout field indicates the maximum time
3282          * the current owner of the resource has to free it.
3283          */
3284         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3285                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3286
3287         return status;
3288 }
3289
3290 /**
3291  * i40e_aq_release_resource
3292  * @hw: pointer to the hw struct
3293  * @resource: resource id
3294  * @sdp_number: resource number
3295  * @cmd_details: pointer to command details structure or NULL
3296  *
3297  * release common resource using the admin queue commands
3298  **/
3299 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3300                                 enum i40e_aq_resources_ids resource,
3301                                 u8 sdp_number,
3302                                 struct i40e_asq_cmd_details *cmd_details)
3303 {
3304         struct i40e_aq_desc desc;
3305         struct i40e_aqc_request_resource *cmd =
3306                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3307         enum i40e_status_code status;
3308
3309         DEBUGFUNC("i40e_aq_release_resource");
3310
3311         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3312
3313         cmd->resource_id = CPU_TO_LE16(resource);
3314         cmd->resource_number = CPU_TO_LE32(sdp_number);
3315
3316         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3317
3318         return status;
3319 }
3320
3321 /**
3322  * i40e_aq_read_nvm
3323  * @hw: pointer to the hw struct
3324  * @module_pointer: module pointer location in words from the NVM beginning
3325  * @offset: byte offset from the module beginning
3326  * @length: length of the section to be read (in bytes from the offset)
3327  * @data: command buffer (size [bytes] = length)
3328  * @last_command: tells if this is the last command in a series
3329  * @cmd_details: pointer to command details structure or NULL
3330  *
3331  * Read the NVM using the admin queue commands
3332  **/
3333 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3334                                 u32 offset, u16 length, void *data,
3335                                 bool last_command,
3336                                 struct i40e_asq_cmd_details *cmd_details)
3337 {
3338         struct i40e_aq_desc desc;
3339         struct i40e_aqc_nvm_update *cmd =
3340                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3341         enum i40e_status_code status;
3342
3343         DEBUGFUNC("i40e_aq_read_nvm");
3344
3345         /* In offset the highest byte must be zeroed. */
3346         if (offset & 0xFF000000) {
3347                 status = I40E_ERR_PARAM;
3348                 goto i40e_aq_read_nvm_exit;
3349         }
3350
3351         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3352
3353         /* If this is the last command in a series, set the proper flag. */
3354         if (last_command)
3355                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3356         cmd->module_pointer = module_pointer;
3357         cmd->offset = CPU_TO_LE32(offset);
3358         cmd->length = CPU_TO_LE16(length);
3359
3360         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3361         if (length > I40E_AQ_LARGE_BUF)
3362                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3363
3364         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3365
3366 i40e_aq_read_nvm_exit:
3367         return status;
3368 }
3369
3370 /**
3371  * i40e_aq_read_nvm_config - read an nvm config block
3372  * @hw: pointer to the hw struct
3373  * @cmd_flags: NVM access admin command bits
3374  * @field_id: field or feature id
3375  * @data: buffer for result
3376  * @buf_size: buffer size
3377  * @element_count: pointer to count of elements read by FW
3378  * @cmd_details: pointer to command details structure or NULL
3379  **/
3380 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3381                                 u8 cmd_flags, u32 field_id, void *data,
3382                                 u16 buf_size, u16 *element_count,
3383                                 struct i40e_asq_cmd_details *cmd_details)
3384 {
3385         struct i40e_aq_desc desc;
3386         struct i40e_aqc_nvm_config_read *cmd =
3387                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3388         enum i40e_status_code status;
3389
3390         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3391         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3392         if (buf_size > I40E_AQ_LARGE_BUF)
3393                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3394
3395         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3396         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3397         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3398                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3399         else
3400                 cmd->element_id_msw = 0;
3401
3402         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3403
3404         if (!status && element_count)
3405                 *element_count = LE16_TO_CPU(cmd->element_count);
3406
3407         return status;
3408 }
3409
3410 /**
3411  * i40e_aq_write_nvm_config - write an nvm config block
3412  * @hw: pointer to the hw struct
3413  * @cmd_flags: NVM access admin command bits
3414  * @data: buffer for result
3415  * @buf_size: buffer size
3416  * @element_count: count of elements to be written
3417  * @cmd_details: pointer to command details structure or NULL
3418  **/
3419 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3420                                 u8 cmd_flags, void *data, u16 buf_size,
3421                                 u16 element_count,
3422                                 struct i40e_asq_cmd_details *cmd_details)
3423 {
3424         struct i40e_aq_desc desc;
3425         struct i40e_aqc_nvm_config_write *cmd =
3426                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3427         enum i40e_status_code status;
3428
3429         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3430         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3431         if (buf_size > I40E_AQ_LARGE_BUF)
3432                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3433
3434         cmd->element_count = CPU_TO_LE16(element_count);
3435         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3436         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3437
3438         return status;
3439 }
3440
3441 /**
3442  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3443  * @hw: pointer to the hw struct
3444  * @cmd_details: pointer to command details structure or NULL
3445  **/
3446 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3447                                 void *buff, u16 buff_size,
3448                                 struct i40e_asq_cmd_details *cmd_details)
3449 {
3450         struct i40e_aq_desc desc;
3451         enum i40e_status_code status;
3452
3453         UNREFERENCED_2PARAMETER(buff, buff_size);
3454
3455         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3456         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3457         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3458                 status = I40E_ERR_NOT_IMPLEMENTED;
3459
3460         return status;
3461 }
3462
3463 /**
3464  * i40e_aq_erase_nvm
3465  * @hw: pointer to the hw struct
3466  * @module_pointer: module pointer location in words from the NVM beginning
3467  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3468  * @length: length of the section to be erased (expressed in 4 KB)
3469  * @last_command: tells if this is the last command in a series
3470  * @cmd_details: pointer to command details structure or NULL
3471  *
3472  * Erase the NVM sector using the admin queue commands
3473  **/
3474 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3475                                 u32 offset, u16 length, bool last_command,
3476                                 struct i40e_asq_cmd_details *cmd_details)
3477 {
3478         struct i40e_aq_desc desc;
3479         struct i40e_aqc_nvm_update *cmd =
3480                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3481         enum i40e_status_code status;
3482
3483         DEBUGFUNC("i40e_aq_erase_nvm");
3484
3485         /* In offset the highest byte must be zeroed. */
3486         if (offset & 0xFF000000) {
3487                 status = I40E_ERR_PARAM;
3488                 goto i40e_aq_erase_nvm_exit;
3489         }
3490
3491         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3492
3493         /* If this is the last command in a series, set the proper flag. */
3494         if (last_command)
3495                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3496         cmd->module_pointer = module_pointer;
3497         cmd->offset = CPU_TO_LE32(offset);
3498         cmd->length = CPU_TO_LE16(length);
3499
3500         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3501
3502 i40e_aq_erase_nvm_exit:
3503         return status;
3504 }
3505
3506 /**
3507  * i40e_parse_discover_capabilities
3508  * @hw: pointer to the hw struct
3509  * @buff: pointer to a buffer containing device/function capability records
3510  * @cap_count: number of capability records in the list
3511  * @list_type_opc: type of capabilities list to parse
3512  *
3513  * Parse the device/function capabilities list.
3514  **/
3515 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3516                                      u32 cap_count,
3517                                      enum i40e_admin_queue_opc list_type_opc)
3518 {
3519         struct i40e_aqc_list_capabilities_element_resp *cap;
3520         u32 valid_functions, num_functions;
3521         u32 number, logical_id, phys_id;
3522         struct i40e_hw_capabilities *p;
3523         u8 major_rev;
3524         u32 i = 0;
3525         u16 id;
3526
3527         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3528
3529         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3530                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3531         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3532                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3533         else
3534                 return;
3535
3536         for (i = 0; i < cap_count; i++, cap++) {
3537                 id = LE16_TO_CPU(cap->id);
3538                 number = LE32_TO_CPU(cap->number);
3539                 logical_id = LE32_TO_CPU(cap->logical_id);
3540                 phys_id = LE32_TO_CPU(cap->phys_id);
3541                 major_rev = cap->major_rev;
3542
3543                 switch (id) {
3544                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3545                         p->switch_mode = number;
3546                         i40e_debug(hw, I40E_DEBUG_INIT,
3547                                    "HW Capability: Switch mode = %d\n",
3548                                    p->switch_mode);
3549                         break;
3550                 case I40E_AQ_CAP_ID_MNG_MODE:
3551                         p->management_mode = number;
3552                         i40e_debug(hw, I40E_DEBUG_INIT,
3553                                    "HW Capability: Management Mode = %d\n",
3554                                    p->management_mode);
3555                         break;
3556                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3557                         p->npar_enable = number;
3558                         i40e_debug(hw, I40E_DEBUG_INIT,
3559                                    "HW Capability: NPAR enable = %d\n",
3560                                    p->npar_enable);
3561                         break;
3562                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3563                         p->os2bmc = number;
3564                         i40e_debug(hw, I40E_DEBUG_INIT,
3565                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3566                         break;
3567                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3568                         p->valid_functions = number;
3569                         i40e_debug(hw, I40E_DEBUG_INIT,
3570                                    "HW Capability: Valid Functions = %d\n",
3571                                    p->valid_functions);
3572                         break;
3573                 case I40E_AQ_CAP_ID_SRIOV:
3574                         if (number == 1)
3575                                 p->sr_iov_1_1 = true;
3576                         i40e_debug(hw, I40E_DEBUG_INIT,
3577                                    "HW Capability: SR-IOV = %d\n",
3578                                    p->sr_iov_1_1);
3579                         break;
3580                 case I40E_AQ_CAP_ID_VF:
3581                         p->num_vfs = number;
3582                         p->vf_base_id = logical_id;
3583                         i40e_debug(hw, I40E_DEBUG_INIT,
3584                                    "HW Capability: VF count = %d\n",
3585                                    p->num_vfs);
3586                         i40e_debug(hw, I40E_DEBUG_INIT,
3587                                    "HW Capability: VF base_id = %d\n",
3588                                    p->vf_base_id);
3589                         break;
3590                 case I40E_AQ_CAP_ID_VMDQ:
3591                         if (number == 1)
3592                                 p->vmdq = true;
3593                         i40e_debug(hw, I40E_DEBUG_INIT,
3594                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3595                         break;
3596                 case I40E_AQ_CAP_ID_8021QBG:
3597                         if (number == 1)
3598                                 p->evb_802_1_qbg = true;
3599                         i40e_debug(hw, I40E_DEBUG_INIT,
3600                                    "HW Capability: 802.1Qbg = %d\n", number);
3601                         break;
3602                 case I40E_AQ_CAP_ID_8021QBR:
3603                         if (number == 1)
3604                                 p->evb_802_1_qbh = true;
3605                         i40e_debug(hw, I40E_DEBUG_INIT,
3606                                    "HW Capability: 802.1Qbh = %d\n", number);
3607                         break;
3608                 case I40E_AQ_CAP_ID_VSI:
3609                         p->num_vsis = number;
3610                         i40e_debug(hw, I40E_DEBUG_INIT,
3611                                    "HW Capability: VSI count = %d\n",
3612                                    p->num_vsis);
3613                         break;
3614                 case I40E_AQ_CAP_ID_DCB:
3615                         if (number == 1) {
3616                                 p->dcb = true;
3617                                 p->enabled_tcmap = logical_id;
3618                                 p->maxtc = phys_id;
3619                         }
3620                         i40e_debug(hw, I40E_DEBUG_INIT,
3621                                    "HW Capability: DCB = %d\n", p->dcb);
3622                         i40e_debug(hw, I40E_DEBUG_INIT,
3623                                    "HW Capability: TC Mapping = %d\n",
3624                                    logical_id);
3625                         i40e_debug(hw, I40E_DEBUG_INIT,
3626                                    "HW Capability: TC Max = %d\n", p->maxtc);
3627                         break;
3628                 case I40E_AQ_CAP_ID_FCOE:
3629                         if (number == 1)
3630                                 p->fcoe = true;
3631                         i40e_debug(hw, I40E_DEBUG_INIT,
3632                                    "HW Capability: FCOE = %d\n", p->fcoe);
3633                         break;
3634                 case I40E_AQ_CAP_ID_ISCSI:
3635                         if (number == 1)
3636                                 p->iscsi = true;
3637                         i40e_debug(hw, I40E_DEBUG_INIT,
3638                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3639                         break;
3640                 case I40E_AQ_CAP_ID_RSS:
3641                         p->rss = true;
3642                         p->rss_table_size = number;
3643                         p->rss_table_entry_width = logical_id;
3644                         i40e_debug(hw, I40E_DEBUG_INIT,
3645                                    "HW Capability: RSS = %d\n", p->rss);
3646                         i40e_debug(hw, I40E_DEBUG_INIT,
3647                                    "HW Capability: RSS table size = %d\n",
3648                                    p->rss_table_size);
3649                         i40e_debug(hw, I40E_DEBUG_INIT,
3650                                    "HW Capability: RSS table width = %d\n",
3651                                    p->rss_table_entry_width);
3652                         break;
3653                 case I40E_AQ_CAP_ID_RXQ:
3654                         p->num_rx_qp = number;
3655                         p->base_queue = phys_id;
3656                         i40e_debug(hw, I40E_DEBUG_INIT,
3657                                    "HW Capability: Rx QP = %d\n", number);
3658                         i40e_debug(hw, I40E_DEBUG_INIT,
3659                                    "HW Capability: base_queue = %d\n",
3660                                    p->base_queue);
3661                         break;
3662                 case I40E_AQ_CAP_ID_TXQ:
3663                         p->num_tx_qp = number;
3664                         p->base_queue = phys_id;
3665                         i40e_debug(hw, I40E_DEBUG_INIT,
3666                                    "HW Capability: Tx QP = %d\n", number);
3667                         i40e_debug(hw, I40E_DEBUG_INIT,
3668                                    "HW Capability: base_queue = %d\n",
3669                                    p->base_queue);
3670                         break;
3671                 case I40E_AQ_CAP_ID_MSIX:
3672                         p->num_msix_vectors = number;
3673                         i40e_debug(hw, I40E_DEBUG_INIT,
3674                                    "HW Capability: MSIX vector count = %d\n",
3675                                    p->num_msix_vectors);
3676                         break;
3677                 case I40E_AQ_CAP_ID_VF_MSIX:
3678                         p->num_msix_vectors_vf = number;
3679                         i40e_debug(hw, I40E_DEBUG_INIT,
3680                                    "HW Capability: MSIX VF vector count = %d\n",
3681                                    p->num_msix_vectors_vf);
3682                         break;
3683                 case I40E_AQ_CAP_ID_FLEX10:
3684                         if (major_rev == 1) {
3685                                 if (number == 1) {
3686                                         p->flex10_enable = true;
3687                                         p->flex10_capable = true;
3688                                 }
3689                         } else {
3690                                 /* Capability revision >= 2 */
3691                                 if (number & 1)
3692                                         p->flex10_enable = true;
3693                                 if (number & 2)
3694                                         p->flex10_capable = true;
3695                         }
3696                         p->flex10_mode = logical_id;
3697                         p->flex10_status = phys_id;
3698                         i40e_debug(hw, I40E_DEBUG_INIT,
3699                                    "HW Capability: Flex10 mode = %d\n",
3700                                    p->flex10_mode);
3701                         i40e_debug(hw, I40E_DEBUG_INIT,
3702                                    "HW Capability: Flex10 status = %d\n",
3703                                    p->flex10_status);
3704                         break;
3705                 case I40E_AQ_CAP_ID_CEM:
3706                         if (number == 1)
3707                                 p->mgmt_cem = true;
3708                         i40e_debug(hw, I40E_DEBUG_INIT,
3709                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3710                         break;
3711                 case I40E_AQ_CAP_ID_IWARP:
3712                         if (number == 1)
3713                                 p->iwarp = true;
3714                         i40e_debug(hw, I40E_DEBUG_INIT,
3715                                    "HW Capability: iWARP = %d\n", p->iwarp);
3716                         break;
3717                 case I40E_AQ_CAP_ID_LED:
3718                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3719                                 p->led[phys_id] = true;
3720                         i40e_debug(hw, I40E_DEBUG_INIT,
3721                                    "HW Capability: LED - PIN %d\n", phys_id);
3722                         break;
3723                 case I40E_AQ_CAP_ID_SDP:
3724                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3725                                 p->sdp[phys_id] = true;
3726                         i40e_debug(hw, I40E_DEBUG_INIT,
3727                                    "HW Capability: SDP - PIN %d\n", phys_id);
3728                         break;
3729                 case I40E_AQ_CAP_ID_MDIO:
3730                         if (number == 1) {
3731                                 p->mdio_port_num = phys_id;
3732                                 p->mdio_port_mode = logical_id;
3733                         }
3734                         i40e_debug(hw, I40E_DEBUG_INIT,
3735                                    "HW Capability: MDIO port number = %d\n",
3736                                    p->mdio_port_num);
3737                         i40e_debug(hw, I40E_DEBUG_INIT,
3738                                    "HW Capability: MDIO port mode = %d\n",
3739                                    p->mdio_port_mode);
3740                         break;
3741                 case I40E_AQ_CAP_ID_1588:
3742                         if (number == 1)
3743                                 p->ieee_1588 = true;
3744                         i40e_debug(hw, I40E_DEBUG_INIT,
3745                                    "HW Capability: IEEE 1588 = %d\n",
3746                                    p->ieee_1588);
3747                         break;
3748                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3749                         p->fd = true;
3750                         p->fd_filters_guaranteed = number;
3751                         p->fd_filters_best_effort = logical_id;
3752                         i40e_debug(hw, I40E_DEBUG_INIT,
3753                                    "HW Capability: Flow Director = 1\n");
3754                         i40e_debug(hw, I40E_DEBUG_INIT,
3755                                    "HW Capability: Guaranteed FD filters = %d\n",
3756                                    p->fd_filters_guaranteed);
3757                         break;
3758                 case I40E_AQ_CAP_ID_WSR_PROT:
3759                         p->wr_csr_prot = (u64)number;
3760                         p->wr_csr_prot |= (u64)logical_id << 32;
3761                         i40e_debug(hw, I40E_DEBUG_INIT,
3762                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3763                                    (p->wr_csr_prot & 0xffff));
3764                         break;
3765                 case I40E_AQ_CAP_ID_NVM_MGMT:
3766                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3767                                 p->sec_rev_disabled = true;
3768                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3769                                 p->update_disabled = true;
3770                         break;
3771 #ifdef X722_SUPPORT
3772                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3773                         hw->num_wol_proxy_filters = (u16)number;
3774                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3775                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3776                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3777                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3778                         else
3779                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3780                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3781                         p->proxy_support = p->proxy_support;
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: WOL proxy filters = %d\n",
3784                                    hw->num_wol_proxy_filters);
3785                         break;
3786 #endif
3787                 default:
3788                         break;
3789                 }
3790         }
3791
3792         if (p->fcoe)
3793                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3794
3795 #ifdef I40E_FCOE_ENA
3796         /* Software override ensuring FCoE is disabled if npar or mfp
3797          * mode because it is not supported in these modes.
3798          */
3799         if (p->npar_enable || p->flex10_enable)
3800                 p->fcoe = false;
3801 #else
3802         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3803         p->fcoe = false;
3804 #endif
3805
3806         /* count the enabled ports (aka the "not disabled" ports) */
3807         hw->num_ports = 0;
3808         for (i = 0; i < 4; i++) {
3809                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3810                 u64 port_cfg = 0;
3811
3812                 /* use AQ read to get the physical register offset instead
3813                  * of the port relative offset
3814                  */
3815                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3816                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3817                         hw->num_ports++;
3818         }
3819
3820         valid_functions = p->valid_functions;
3821         num_functions = 0;
3822         while (valid_functions) {
3823                 if (valid_functions & 1)
3824                         num_functions++;
3825                 valid_functions >>= 1;
3826         }
3827
3828         /* partition id is 1-based, and functions are evenly spread
3829          * across the ports as partitions
3830          */
3831         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3832         hw->num_partitions = num_functions / hw->num_ports;
3833
3834         /* additional HW specific goodies that might
3835          * someday be HW version specific
3836          */
3837         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3838 }
3839
3840 /**
3841  * i40e_aq_discover_capabilities
3842  * @hw: pointer to the hw struct
3843  * @buff: a virtual buffer to hold the capabilities
3844  * @buff_size: Size of the virtual buffer
3845  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3846  * @list_type_opc: capabilities type to discover - pass in the command opcode
3847  * @cmd_details: pointer to command details structure or NULL
3848  *
3849  * Get the device capabilities descriptions from the firmware
3850  **/
3851 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3852                                 void *buff, u16 buff_size, u16 *data_size,
3853                                 enum i40e_admin_queue_opc list_type_opc,
3854                                 struct i40e_asq_cmd_details *cmd_details)
3855 {
3856         struct i40e_aqc_list_capabilites *cmd;
3857         struct i40e_aq_desc desc;
3858         enum i40e_status_code status = I40E_SUCCESS;
3859
3860         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3861
3862         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3863                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3864                 status = I40E_ERR_PARAM;
3865                 goto exit;
3866         }
3867
3868         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3869
3870         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3871         if (buff_size > I40E_AQ_LARGE_BUF)
3872                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3873
3874         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3875         *data_size = LE16_TO_CPU(desc.datalen);
3876
3877         if (status)
3878                 goto exit;
3879
3880         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3881                                          list_type_opc);
3882
3883 exit:
3884         return status;
3885 }
3886
3887 /**
3888  * i40e_aq_update_nvm
3889  * @hw: pointer to the hw struct
3890  * @module_pointer: module pointer location in words from the NVM beginning
3891  * @offset: byte offset from the module beginning
3892  * @length: length of the section to be written (in bytes from the offset)
3893  * @data: command buffer (size [bytes] = length)
3894  * @last_command: tells if this is the last command in a series
3895  * @cmd_details: pointer to command details structure or NULL
3896  *
3897  * Update the NVM using the admin queue commands
3898  **/
3899 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3900                                 u32 offset, u16 length, void *data,
3901                                 bool last_command,
3902                                 struct i40e_asq_cmd_details *cmd_details)
3903 {
3904         struct i40e_aq_desc desc;
3905         struct i40e_aqc_nvm_update *cmd =
3906                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3907         enum i40e_status_code status;
3908
3909         DEBUGFUNC("i40e_aq_update_nvm");
3910
3911         /* In offset the highest byte must be zeroed. */
3912         if (offset & 0xFF000000) {
3913                 status = I40E_ERR_PARAM;
3914                 goto i40e_aq_update_nvm_exit;
3915         }
3916
3917         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3918
3919         /* If this is the last command in a series, set the proper flag. */
3920         if (last_command)
3921                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3922         cmd->module_pointer = module_pointer;
3923         cmd->offset = CPU_TO_LE32(offset);
3924         cmd->length = CPU_TO_LE16(length);
3925
3926         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3927         if (length > I40E_AQ_LARGE_BUF)
3928                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3929
3930         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3931
3932 i40e_aq_update_nvm_exit:
3933         return status;
3934 }
3935
3936 /**
3937  * i40e_aq_get_lldp_mib
3938  * @hw: pointer to the hw struct
3939  * @bridge_type: type of bridge requested
3940  * @mib_type: Local, Remote or both Local and Remote MIBs
3941  * @buff: pointer to a user supplied buffer to store the MIB block
3942  * @buff_size: size of the buffer (in bytes)
3943  * @local_len : length of the returned Local LLDP MIB
3944  * @remote_len: length of the returned Remote LLDP MIB
3945  * @cmd_details: pointer to command details structure or NULL
3946  *
3947  * Requests the complete LLDP MIB (entire packet).
3948  **/
3949 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3950                                 u8 mib_type, void *buff, u16 buff_size,
3951                                 u16 *local_len, u16 *remote_len,
3952                                 struct i40e_asq_cmd_details *cmd_details)
3953 {
3954         struct i40e_aq_desc desc;
3955         struct i40e_aqc_lldp_get_mib *cmd =
3956                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3957         struct i40e_aqc_lldp_get_mib *resp =
3958                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3959         enum i40e_status_code status;
3960
3961         if (buff_size == 0 || !buff)
3962                 return I40E_ERR_PARAM;
3963
3964         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3965         /* Indirect Command */
3966         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3967
3968         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3969         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3970                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3971
3972         desc.datalen = CPU_TO_LE16(buff_size);
3973
3974         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3975         if (buff_size > I40E_AQ_LARGE_BUF)
3976                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3977
3978         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3979         if (!status) {
3980                 if (local_len != NULL)
3981                         *local_len = LE16_TO_CPU(resp->local_len);
3982                 if (remote_len != NULL)
3983                         *remote_len = LE16_TO_CPU(resp->remote_len);
3984         }
3985
3986         return status;
3987 }
3988
3989  /**
3990  * i40e_aq_set_lldp_mib - Set the LLDP MIB
3991  * @hw: pointer to the hw struct
3992  * @mib_type: Local, Remote or both Local and Remote MIBs
3993  * @buff: pointer to a user supplied buffer to store the MIB block
3994  * @buff_size: size of the buffer (in bytes)
3995  * @cmd_details: pointer to command details structure or NULL
3996  *
3997  * Set the LLDP MIB.
3998  **/
3999 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4000                                 u8 mib_type, void *buff, u16 buff_size,
4001                                 struct i40e_asq_cmd_details *cmd_details)
4002 {
4003         struct i40e_aq_desc desc;
4004         struct i40e_aqc_lldp_set_local_mib *cmd =
4005                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4006         enum i40e_status_code status;
4007
4008         if (buff_size == 0 || !buff)
4009                 return I40E_ERR_PARAM;
4010
4011         i40e_fill_default_direct_cmd_desc(&desc,
4012                                 i40e_aqc_opc_lldp_set_local_mib);
4013         /* Indirect Command */
4014         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4015         if (buff_size > I40E_AQ_LARGE_BUF)
4016                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4017         desc.datalen = CPU_TO_LE16(buff_size);
4018
4019         cmd->type = mib_type;
4020         cmd->length = CPU_TO_LE16(buff_size);
4021         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4022         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4023
4024         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4025         return status;
4026 }
4027
4028 /**
4029  * i40e_aq_cfg_lldp_mib_change_event
4030  * @hw: pointer to the hw struct
4031  * @enable_update: Enable or Disable event posting
4032  * @cmd_details: pointer to command details structure or NULL
4033  *
4034  * Enable or Disable posting of an event on ARQ when LLDP MIB
4035  * associated with the interface changes
4036  **/
4037 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4038                                 bool enable_update,
4039                                 struct i40e_asq_cmd_details *cmd_details)
4040 {
4041         struct i40e_aq_desc desc;
4042         struct i40e_aqc_lldp_update_mib *cmd =
4043                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4044         enum i40e_status_code status;
4045
4046         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4047
4048         if (!enable_update)
4049                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4050
4051         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4052
4053         return status;
4054 }
4055
4056 /**
4057  * i40e_aq_add_lldp_tlv
4058  * @hw: pointer to the hw struct
4059  * @bridge_type: type of bridge
4060  * @buff: buffer with TLV to add
4061  * @buff_size: length of the buffer
4062  * @tlv_len: length of the TLV to be added
4063  * @mib_len: length of the LLDP MIB returned in response
4064  * @cmd_details: pointer to command details structure or NULL
4065  *
4066  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4067  * it is responsibility of the caller to make sure that the TLV is not
4068  * already present in the LLDPDU.
4069  * In return firmware will write the complete LLDP MIB with the newly
4070  * added TLV in the response buffer.
4071  **/
4072 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4073                                 void *buff, u16 buff_size, u16 tlv_len,
4074                                 u16 *mib_len,
4075                                 struct i40e_asq_cmd_details *cmd_details)
4076 {
4077         struct i40e_aq_desc desc;
4078         struct i40e_aqc_lldp_add_tlv *cmd =
4079                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4080         enum i40e_status_code status;
4081
4082         if (buff_size == 0 || !buff || tlv_len == 0)
4083                 return I40E_ERR_PARAM;
4084
4085         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4086
4087         /* Indirect Command */
4088         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4089         if (buff_size > I40E_AQ_LARGE_BUF)
4090                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4091         desc.datalen = CPU_TO_LE16(buff_size);
4092
4093         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4094                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4095         cmd->len = CPU_TO_LE16(tlv_len);
4096
4097         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4098         if (!status) {
4099                 if (mib_len != NULL)
4100                         *mib_len = LE16_TO_CPU(desc.datalen);
4101         }
4102
4103         return status;
4104 }
4105
4106 /**
4107  * i40e_aq_update_lldp_tlv
4108  * @hw: pointer to the hw struct
4109  * @bridge_type: type of bridge
4110  * @buff: buffer with TLV to update
4111  * @buff_size: size of the buffer holding original and updated TLVs
4112  * @old_len: Length of the Original TLV
4113  * @new_len: Length of the Updated TLV
4114  * @offset: offset of the updated TLV in the buff
4115  * @mib_len: length of the returned LLDP MIB
4116  * @cmd_details: pointer to command details structure or NULL
4117  *
4118  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4119  * Firmware will place the complete LLDP MIB in response buffer with the
4120  * updated TLV.
4121  **/
4122 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4123                                 u8 bridge_type, void *buff, u16 buff_size,
4124                                 u16 old_len, u16 new_len, u16 offset,
4125                                 u16 *mib_len,
4126                                 struct i40e_asq_cmd_details *cmd_details)
4127 {
4128         struct i40e_aq_desc desc;
4129         struct i40e_aqc_lldp_update_tlv *cmd =
4130                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4131         enum i40e_status_code status;
4132
4133         if (buff_size == 0 || !buff || offset == 0 ||
4134             old_len == 0 || new_len == 0)
4135                 return I40E_ERR_PARAM;
4136
4137         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4138
4139         /* Indirect Command */
4140         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4141         if (buff_size > I40E_AQ_LARGE_BUF)
4142                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4143         desc.datalen = CPU_TO_LE16(buff_size);
4144
4145         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4146                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4147         cmd->old_len = CPU_TO_LE16(old_len);
4148         cmd->new_offset = CPU_TO_LE16(offset);
4149         cmd->new_len = CPU_TO_LE16(new_len);
4150
4151         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4152         if (!status) {
4153                 if (mib_len != NULL)
4154                         *mib_len = LE16_TO_CPU(desc.datalen);
4155         }
4156
4157         return status;
4158 }
4159
4160 /**
4161  * i40e_aq_delete_lldp_tlv
4162  * @hw: pointer to the hw struct
4163  * @bridge_type: type of bridge
4164  * @buff: pointer to a user supplied buffer that has the TLV
4165  * @buff_size: length of the buffer
4166  * @tlv_len: length of the TLV to be deleted
4167  * @mib_len: length of the returned LLDP MIB
4168  * @cmd_details: pointer to command details structure or NULL
4169  *
4170  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4171  * The firmware places the entire LLDP MIB in the response buffer.
4172  **/
4173 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4174                                 u8 bridge_type, void *buff, u16 buff_size,
4175                                 u16 tlv_len, u16 *mib_len,
4176                                 struct i40e_asq_cmd_details *cmd_details)
4177 {
4178         struct i40e_aq_desc desc;
4179         struct i40e_aqc_lldp_add_tlv *cmd =
4180                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4181         enum i40e_status_code status;
4182
4183         if (buff_size == 0 || !buff)
4184                 return I40E_ERR_PARAM;
4185
4186         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4187
4188         /* Indirect Command */
4189         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4190         if (buff_size > I40E_AQ_LARGE_BUF)
4191                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4192         desc.datalen = CPU_TO_LE16(buff_size);
4193         cmd->len = CPU_TO_LE16(tlv_len);
4194         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4195                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4196
4197         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4198         if (!status) {
4199                 if (mib_len != NULL)
4200                         *mib_len = LE16_TO_CPU(desc.datalen);
4201         }
4202
4203         return status;
4204 }
4205
4206 /**
4207  * i40e_aq_stop_lldp
4208  * @hw: pointer to the hw struct
4209  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4210  * @cmd_details: pointer to command details structure or NULL
4211  *
4212  * Stop or Shutdown the embedded LLDP Agent
4213  **/
4214 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4215                                 struct i40e_asq_cmd_details *cmd_details)
4216 {
4217         struct i40e_aq_desc desc;
4218         struct i40e_aqc_lldp_stop *cmd =
4219                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4220         enum i40e_status_code status;
4221
4222         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4223
4224         if (shutdown_agent)
4225                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4226
4227         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4228
4229         return status;
4230 }
4231
4232 /**
4233  * i40e_aq_start_lldp
4234  * @hw: pointer to the hw struct
4235  * @cmd_details: pointer to command details structure or NULL
4236  *
4237  * Start the embedded LLDP Agent on all ports.
4238  **/
4239 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4240                                 struct i40e_asq_cmd_details *cmd_details)
4241 {
4242         struct i40e_aq_desc desc;
4243         struct i40e_aqc_lldp_start *cmd =
4244                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4245         enum i40e_status_code status;
4246
4247         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4248
4249         cmd->command = I40E_AQ_LLDP_AGENT_START;
4250
4251         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4252
4253         return status;
4254 }
4255
4256 /**
4257  * i40e_aq_get_cee_dcb_config
4258  * @hw: pointer to the hw struct
4259  * @buff: response buffer that stores CEE operational configuration
4260  * @buff_size: size of the buffer passed
4261  * @cmd_details: pointer to command details structure or NULL
4262  *
4263  * Get CEE DCBX mode operational configuration from firmware
4264  **/
4265 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4266                                 void *buff, u16 buff_size,
4267                                 struct i40e_asq_cmd_details *cmd_details)
4268 {
4269         struct i40e_aq_desc desc;
4270         enum i40e_status_code status;
4271
4272         if (buff_size == 0 || !buff)
4273                 return I40E_ERR_PARAM;
4274
4275         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4276
4277         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4278         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4279                                        cmd_details);
4280
4281         return status;
4282 }
4283
4284 /**
4285  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4286  * @hw: pointer to the hw struct
4287  * @start_agent: True if DCBx Agent needs to be Started
4288  *                              False if DCBx Agent needs to be Stopped
4289  * @cmd_details: pointer to command details structure or NULL
4290  *
4291  * Start/Stop the embedded dcbx Agent
4292  **/
4293 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4294                                 bool start_agent,
4295                                 struct i40e_asq_cmd_details *cmd_details)
4296 {
4297         struct i40e_aq_desc desc;
4298         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4299                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4300                                 &desc.params.raw;
4301         enum i40e_status_code status;
4302
4303         i40e_fill_default_direct_cmd_desc(&desc,
4304                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4305
4306         if (start_agent)
4307                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4308
4309         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4310
4311         return status;
4312 }
4313
4314 /**
4315  * i40e_aq_add_udp_tunnel
4316  * @hw: pointer to the hw struct
4317  * @udp_port: the UDP port to add
4318  * @header_len: length of the tunneling header length in DWords
4319  * @protocol_index: protocol index type
4320  * @filter_index: pointer to filter index
4321  * @cmd_details: pointer to command details structure or NULL
4322  **/
4323 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4324                                 u16 udp_port, u8 protocol_index,
4325                                 u8 *filter_index,
4326                                 struct i40e_asq_cmd_details *cmd_details)
4327 {
4328         struct i40e_aq_desc desc;
4329         struct i40e_aqc_add_udp_tunnel *cmd =
4330                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4331         struct i40e_aqc_del_udp_tunnel_completion *resp =
4332                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4333         enum i40e_status_code status;
4334
4335         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4336
4337         cmd->udp_port = CPU_TO_LE16(udp_port);
4338         cmd->protocol_type = protocol_index;
4339
4340         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4341
4342         if (!status && filter_index)
4343                 *filter_index = resp->index;
4344
4345         return status;
4346 }
4347
4348 /**
4349  * i40e_aq_del_udp_tunnel
4350  * @hw: pointer to the hw struct
4351  * @index: filter index
4352  * @cmd_details: pointer to command details structure or NULL
4353  **/
4354 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4355                                 struct i40e_asq_cmd_details *cmd_details)
4356 {
4357         struct i40e_aq_desc desc;
4358         struct i40e_aqc_remove_udp_tunnel *cmd =
4359                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4360         enum i40e_status_code status;
4361
4362         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4363
4364         cmd->index = index;
4365
4366         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4367
4368         return status;
4369 }
4370
4371 /**
4372  * i40e_aq_get_switch_resource_alloc (0x0204)
4373  * @hw: pointer to the hw struct
4374  * @num_entries: pointer to u8 to store the number of resource entries returned
4375  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4376  *        to store the resource information for all resource types.  Each
4377  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4378  * @count: size, in bytes, of the buffer provided
4379  * @cmd_details: pointer to command details structure or NULL
4380  *
4381  * Query the resources allocated to a function.
4382  **/
4383 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4384                         u8 *num_entries,
4385                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4386                         u16 count,
4387                         struct i40e_asq_cmd_details *cmd_details)
4388 {
4389         struct i40e_aq_desc desc;
4390         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4391                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4392         enum i40e_status_code status;
4393         u16 length = count * sizeof(*buf);
4394
4395         i40e_fill_default_direct_cmd_desc(&desc,
4396                                         i40e_aqc_opc_get_switch_resource_alloc);
4397
4398         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4399         if (length > I40E_AQ_LARGE_BUF)
4400                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4401
4402         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4403
4404         if (!status && num_entries)
4405                 *num_entries = cmd_resp->num_entries;
4406
4407         return status;
4408 }
4409
4410 /**
4411  * i40e_aq_delete_element - Delete switch element
4412  * @hw: pointer to the hw struct
4413  * @seid: the SEID to delete from the switch
4414  * @cmd_details: pointer to command details structure or NULL
4415  *
4416  * This deletes a switch element from the switch.
4417  **/
4418 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4419                                 struct i40e_asq_cmd_details *cmd_details)
4420 {
4421         struct i40e_aq_desc desc;
4422         struct i40e_aqc_switch_seid *cmd =
4423                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4424         enum i40e_status_code status;
4425
4426         if (seid == 0)
4427                 return I40E_ERR_PARAM;
4428
4429         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4430
4431         cmd->seid = CPU_TO_LE16(seid);
4432
4433         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4434
4435         return status;
4436 }
4437
4438 /**
4439  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4440  * @hw: pointer to the hw struct
4441  * @flags: component flags
4442  * @mac_seid: uplink seid (MAC SEID)
4443  * @vsi_seid: connected vsi seid
4444  * @ret_seid: seid of create pv component
4445  *
4446  * This instantiates an i40e port virtualizer with specified flags.
4447  * Depending on specified flags the port virtualizer can act as a
4448  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4449  */
4450 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4451                                        u16 mac_seid, u16 vsi_seid,
4452                                        u16 *ret_seid)
4453 {
4454         struct i40e_aq_desc desc;
4455         struct i40e_aqc_add_update_pv *cmd =
4456                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4457         struct i40e_aqc_add_update_pv_completion *resp =
4458                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4459         enum i40e_status_code status;
4460
4461         if (vsi_seid == 0)
4462                 return I40E_ERR_PARAM;
4463
4464         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4465         cmd->command_flags = CPU_TO_LE16(flags);
4466         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4467         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4468
4469         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4470         if (!status && ret_seid)
4471                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4472
4473         return status;
4474 }
4475
4476 /**
4477  * i40e_aq_add_tag - Add an S/E-tag
4478  * @hw: pointer to the hw struct
4479  * @direct_to_queue: should s-tag direct flow to a specific queue
4480  * @vsi_seid: VSI SEID to use this tag
4481  * @tag: value of the tag
4482  * @queue_num: queue number, only valid is direct_to_queue is true
4483  * @tags_used: return value, number of tags in use by this PF
4484  * @tags_free: return value, number of unallocated tags
4485  * @cmd_details: pointer to command details structure or NULL
4486  *
4487  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4488  * the number of tags allocated by the PF, and the number of unallocated
4489  * tags available.
4490  **/
4491 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4492                                 u16 vsi_seid, u16 tag, u16 queue_num,
4493                                 u16 *tags_used, u16 *tags_free,
4494                                 struct i40e_asq_cmd_details *cmd_details)
4495 {
4496         struct i40e_aq_desc desc;
4497         struct i40e_aqc_add_tag *cmd =
4498                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4499         struct i40e_aqc_add_remove_tag_completion *resp =
4500                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4501         enum i40e_status_code status;
4502
4503         if (vsi_seid == 0)
4504                 return I40E_ERR_PARAM;
4505
4506         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4507
4508         cmd->seid = CPU_TO_LE16(vsi_seid);
4509         cmd->tag = CPU_TO_LE16(tag);
4510         if (direct_to_queue) {
4511                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4512                 cmd->queue_number = CPU_TO_LE16(queue_num);
4513         }
4514
4515         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4516
4517         if (!status) {
4518                 if (tags_used != NULL)
4519                         *tags_used = LE16_TO_CPU(resp->tags_used);
4520                 if (tags_free != NULL)
4521                         *tags_free = LE16_TO_CPU(resp->tags_free);
4522         }
4523
4524         return status;
4525 }
4526
4527 /**
4528  * i40e_aq_remove_tag - Remove an S- or E-tag
4529  * @hw: pointer to the hw struct
4530  * @vsi_seid: VSI SEID this tag is associated with
4531  * @tag: value of the S-tag to delete
4532  * @tags_used: return value, number of tags in use by this PF
4533  * @tags_free: return value, number of unallocated tags
4534  * @cmd_details: pointer to command details structure or NULL
4535  *
4536  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4537  * the number of tags allocated by the PF, and the number of unallocated
4538  * tags available.
4539  **/
4540 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4541                                 u16 tag, u16 *tags_used, u16 *tags_free,
4542                                 struct i40e_asq_cmd_details *cmd_details)
4543 {
4544         struct i40e_aq_desc desc;
4545         struct i40e_aqc_remove_tag *cmd =
4546                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4547         struct i40e_aqc_add_remove_tag_completion *resp =
4548                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4549         enum i40e_status_code status;
4550
4551         if (vsi_seid == 0)
4552                 return I40E_ERR_PARAM;
4553
4554         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4555
4556         cmd->seid = CPU_TO_LE16(vsi_seid);
4557         cmd->tag = CPU_TO_LE16(tag);
4558
4559         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4560
4561         if (!status) {
4562                 if (tags_used != NULL)
4563                         *tags_used = LE16_TO_CPU(resp->tags_used);
4564                 if (tags_free != NULL)
4565                         *tags_free = LE16_TO_CPU(resp->tags_free);
4566         }
4567
4568         return status;
4569 }
4570
4571 /**
4572  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4573  * @hw: pointer to the hw struct
4574  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4575  * @etag: value of E-tag to add
4576  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4577  * @buf: address of indirect buffer
4578  * @tags_used: return value, number of E-tags in use by this port
4579  * @tags_free: return value, number of unallocated M-tags
4580  * @cmd_details: pointer to command details structure or NULL
4581  *
4582  * This associates a multicast E-tag to a port virtualizer.  It will return
4583  * the number of tags allocated by the PF, and the number of unallocated
4584  * tags available.
4585  *
4586  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4587  * num_tags_in_buf long.
4588  **/
4589 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4590                                 u16 etag, u8 num_tags_in_buf, void *buf,
4591                                 u16 *tags_used, u16 *tags_free,
4592                                 struct i40e_asq_cmd_details *cmd_details)
4593 {
4594         struct i40e_aq_desc desc;
4595         struct i40e_aqc_add_remove_mcast_etag *cmd =
4596                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4597         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4598            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4599         enum i40e_status_code status;
4600         u16 length = sizeof(u16) * num_tags_in_buf;
4601
4602         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4603                 return I40E_ERR_PARAM;
4604
4605         i40e_fill_default_direct_cmd_desc(&desc,
4606                                           i40e_aqc_opc_add_multicast_etag);
4607
4608         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4609         cmd->etag = CPU_TO_LE16(etag);
4610         cmd->num_unicast_etags = num_tags_in_buf;
4611
4612         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4613         if (length > I40E_AQ_LARGE_BUF)
4614                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4615
4616         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4617
4618         if (!status) {
4619                 if (tags_used != NULL)
4620                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4621                 if (tags_free != NULL)
4622                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4623         }
4624
4625         return status;
4626 }
4627
4628 /**
4629  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4630  * @hw: pointer to the hw struct
4631  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4632  * @etag: value of the E-tag to remove
4633  * @tags_used: return value, number of tags in use by this port
4634  * @tags_free: return value, number of unallocated tags
4635  * @cmd_details: pointer to command details structure or NULL
4636  *
4637  * This deletes an E-tag from the port virtualizer.  It will return
4638  * the number of tags allocated by the port, and the number of unallocated
4639  * tags available.
4640  **/
4641 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4642                                 u16 etag, u16 *tags_used, u16 *tags_free,
4643                                 struct i40e_asq_cmd_details *cmd_details)
4644 {
4645         struct i40e_aq_desc desc;
4646         struct i40e_aqc_add_remove_mcast_etag *cmd =
4647                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4648         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4649            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4650         enum i40e_status_code status;
4651
4652
4653         if (pv_seid == 0)
4654                 return I40E_ERR_PARAM;
4655
4656         i40e_fill_default_direct_cmd_desc(&desc,
4657                                           i40e_aqc_opc_remove_multicast_etag);
4658
4659         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4660         cmd->etag = CPU_TO_LE16(etag);
4661
4662         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4663
4664         if (!status) {
4665                 if (tags_used != NULL)
4666                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4667                 if (tags_free != NULL)
4668                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4669         }
4670
4671         return status;
4672 }
4673
4674 /**
4675  * i40e_aq_update_tag - Update an S/E-tag
4676  * @hw: pointer to the hw struct
4677  * @vsi_seid: VSI SEID using this S-tag
4678  * @old_tag: old tag value
4679  * @new_tag: new tag value
4680  * @tags_used: return value, number of tags in use by this PF
4681  * @tags_free: return value, number of unallocated tags
4682  * @cmd_details: pointer to command details structure or NULL
4683  *
4684  * This updates the value of the tag currently attached to this VSI
4685  * in the switch complex.  It will return the number of tags allocated
4686  * by the PF, and the number of unallocated tags available.
4687  **/
4688 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4689                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4690                                 u16 *tags_free,
4691                                 struct i40e_asq_cmd_details *cmd_details)
4692 {
4693         struct i40e_aq_desc desc;
4694         struct i40e_aqc_update_tag *cmd =
4695                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4696         struct i40e_aqc_update_tag_completion *resp =
4697                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4698         enum i40e_status_code status;
4699
4700         if (vsi_seid == 0)
4701                 return I40E_ERR_PARAM;
4702
4703         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4704
4705         cmd->seid = CPU_TO_LE16(vsi_seid);
4706         cmd->old_tag = CPU_TO_LE16(old_tag);
4707         cmd->new_tag = CPU_TO_LE16(new_tag);
4708
4709         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4710
4711         if (!status) {
4712                 if (tags_used != NULL)
4713                         *tags_used = LE16_TO_CPU(resp->tags_used);
4714                 if (tags_free != NULL)
4715                         *tags_free = LE16_TO_CPU(resp->tags_free);
4716         }
4717
4718         return status;
4719 }
4720
4721 /**
4722  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4723  * @hw: pointer to the hw struct
4724  * @tcmap: TC map for request/release any ignore PFC condition
4725  * @request: request or release ignore PFC condition
4726  * @tcmap_ret: return TCs for which PFC is currently ignored
4727  * @cmd_details: pointer to command details structure or NULL
4728  *
4729  * This sends out request/release to ignore PFC condition for a TC.
4730  * It will return the TCs for which PFC is currently ignored.
4731  **/
4732 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4733                                 bool request, u8 *tcmap_ret,
4734                                 struct i40e_asq_cmd_details *cmd_details)
4735 {
4736         struct i40e_aq_desc desc;
4737         struct i40e_aqc_pfc_ignore *cmd_resp =
4738                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4739         enum i40e_status_code status;
4740
4741         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4742
4743         if (request)
4744                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4745
4746         cmd_resp->tc_bitmap = tcmap;
4747
4748         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4749
4750         if (!status) {
4751                 if (tcmap_ret != NULL)
4752                         *tcmap_ret = cmd_resp->tc_bitmap;
4753         }
4754
4755         return status;
4756 }
4757
4758 /**
4759  * i40e_aq_dcb_updated - DCB Updated Command
4760  * @hw: pointer to the hw struct
4761  * @cmd_details: pointer to command details structure or NULL
4762  *
4763  * When LLDP is handled in PF this command is used by the PF
4764  * to notify EMP that a DCB setting is modified.
4765  * When LLDP is handled in EMP this command is used by the PF
4766  * to notify EMP whenever one of the following parameters get
4767  * modified:
4768  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4769  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4770  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4771  * EMP will return when the shared RPB settings have been
4772  * recomputed and modified. The retval field in the descriptor
4773  * will be set to 0 when RPB is modified.
4774  **/
4775 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4776                                 struct i40e_asq_cmd_details *cmd_details)
4777 {
4778         struct i40e_aq_desc desc;
4779         enum i40e_status_code status;
4780
4781         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4782
4783         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4784
4785         return status;
4786 }
4787
4788 /**
4789  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4790  * @hw: pointer to the hw struct
4791  * @seid: defines the SEID of the switch for which the stats are requested
4792  * @vlan_id: the VLAN ID for which the statistics are requested
4793  * @stat_index: index of the statistics counters block assigned to this VLAN
4794  * @cmd_details: pointer to command details structure or NULL
4795  *
4796  * XL710 supports 128 smonVlanStats counters.This command is used to
4797  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4798  * switch.
4799  **/
4800 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4801                                 u16 vlan_id, u16 *stat_index,
4802                                 struct i40e_asq_cmd_details *cmd_details)
4803 {
4804         struct i40e_aq_desc desc;
4805         struct i40e_aqc_add_remove_statistics *cmd_resp =
4806                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4807         enum i40e_status_code status;
4808
4809         if ((seid == 0) || (stat_index == NULL))
4810                 return I40E_ERR_PARAM;
4811
4812         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4813
4814         cmd_resp->seid = CPU_TO_LE16(seid);
4815         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4816
4817         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4818
4819         if (!status && stat_index)
4820                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4821
4822         return status;
4823 }
4824
4825 /**
4826  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4827  * @hw: pointer to the hw struct
4828  * @seid: defines the SEID of the switch for which the stats are requested
4829  * @vlan_id: the VLAN ID for which the statistics are requested
4830  * @stat_index: index of the statistics counters block assigned to this VLAN
4831  * @cmd_details: pointer to command details structure or NULL
4832  *
4833  * XL710 supports 128 smonVlanStats counters.This command is used to
4834  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4835  * switch.
4836  **/
4837 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4838                                 u16 vlan_id, u16 stat_index,
4839                                 struct i40e_asq_cmd_details *cmd_details)
4840 {
4841         struct i40e_aq_desc desc;
4842         struct i40e_aqc_add_remove_statistics *cmd =
4843                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4844         enum i40e_status_code status;
4845
4846         if (seid == 0)
4847                 return I40E_ERR_PARAM;
4848
4849         i40e_fill_default_direct_cmd_desc(&desc,
4850                                           i40e_aqc_opc_remove_statistics);
4851
4852         cmd->seid = CPU_TO_LE16(seid);
4853         cmd->vlan  = CPU_TO_LE16(vlan_id);
4854         cmd->stat_index = CPU_TO_LE16(stat_index);
4855
4856         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4857
4858         return status;
4859 }
4860
4861 /**
4862  * i40e_aq_set_port_parameters - set physical port parameters.
4863  * @hw: pointer to the hw struct
4864  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4865  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4866  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4867  * @double_vlan: if set double VLAN is enabled
4868  * @cmd_details: pointer to command details structure or NULL
4869  **/
4870 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4871                                 u16 bad_frame_vsi, bool save_bad_pac,
4872                                 bool pad_short_pac, bool double_vlan,
4873                                 struct i40e_asq_cmd_details *cmd_details)
4874 {
4875         struct i40e_aqc_set_port_parameters *cmd;
4876         enum i40e_status_code status;
4877         struct i40e_aq_desc desc;
4878         u16 command_flags = 0;
4879
4880         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4881
4882         i40e_fill_default_direct_cmd_desc(&desc,
4883                                           i40e_aqc_opc_set_port_parameters);
4884
4885         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4886         if (save_bad_pac)
4887                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4888         if (pad_short_pac)
4889                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4890         if (double_vlan)
4891                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4892         cmd->command_flags = CPU_TO_LE16(command_flags);
4893
4894         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4895
4896         return status;
4897 }
4898
4899 /**
4900  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4901  * @hw: pointer to the hw struct
4902  * @seid: seid for the physical port/switching component/vsi
4903  * @buff: Indirect buffer to hold data parameters and response
4904  * @buff_size: Indirect buffer size
4905  * @opcode: Tx scheduler AQ command opcode
4906  * @cmd_details: pointer to command details structure or NULL
4907  *
4908  * Generic command handler for Tx scheduler AQ commands
4909  **/
4910 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4911                                 void *buff, u16 buff_size,
4912                                  enum i40e_admin_queue_opc opcode,
4913                                 struct i40e_asq_cmd_details *cmd_details)
4914 {
4915         struct i40e_aq_desc desc;
4916         struct i40e_aqc_tx_sched_ind *cmd =
4917                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4918         enum i40e_status_code status;
4919         bool cmd_param_flag = false;
4920
4921         switch (opcode) {
4922         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4923         case i40e_aqc_opc_configure_vsi_tc_bw:
4924         case i40e_aqc_opc_enable_switching_comp_ets:
4925         case i40e_aqc_opc_modify_switching_comp_ets:
4926         case i40e_aqc_opc_disable_switching_comp_ets:
4927         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4928         case i40e_aqc_opc_configure_switching_comp_bw_config:
4929                 cmd_param_flag = true;
4930                 break;
4931         case i40e_aqc_opc_query_vsi_bw_config:
4932         case i40e_aqc_opc_query_vsi_ets_sla_config:
4933         case i40e_aqc_opc_query_switching_comp_ets_config:
4934         case i40e_aqc_opc_query_port_ets_config:
4935         case i40e_aqc_opc_query_switching_comp_bw_config:
4936                 cmd_param_flag = false;
4937                 break;
4938         default:
4939                 return I40E_ERR_PARAM;
4940         }
4941
4942         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4943
4944         /* Indirect command */
4945         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4946         if (cmd_param_flag)
4947                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4948         if (buff_size > I40E_AQ_LARGE_BUF)
4949                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4950
4951         desc.datalen = CPU_TO_LE16(buff_size);
4952
4953         cmd->vsi_seid = CPU_TO_LE16(seid);
4954
4955         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4956
4957         return status;
4958 }
4959
4960 /**
4961  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
4962  * @hw: pointer to the hw struct
4963  * @seid: VSI seid
4964  * @credit: BW limit credits (0 = disabled)
4965  * @max_credit: Max BW limit credits
4966  * @cmd_details: pointer to command details structure or NULL
4967  **/
4968 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
4969                                 u16 seid, u16 credit, u8 max_credit,
4970                                 struct i40e_asq_cmd_details *cmd_details)
4971 {
4972         struct i40e_aq_desc desc;
4973         struct i40e_aqc_configure_vsi_bw_limit *cmd =
4974                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
4975         enum i40e_status_code status;
4976
4977         i40e_fill_default_direct_cmd_desc(&desc,
4978                                           i40e_aqc_opc_configure_vsi_bw_limit);
4979
4980         cmd->vsi_seid = CPU_TO_LE16(seid);
4981         cmd->credit = CPU_TO_LE16(credit);
4982         cmd->max_credit = max_credit;
4983
4984         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4985
4986         return status;
4987 }
4988
4989 /**
4990  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
4991  * @hw: pointer to the hw struct
4992  * @seid: switching component seid
4993  * @credit: BW limit credits (0 = disabled)
4994  * @max_bw: Max BW limit credits
4995  * @cmd_details: pointer to command details structure or NULL
4996  **/
4997 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
4998                                 u16 seid, u16 credit, u8 max_bw,
4999                                 struct i40e_asq_cmd_details *cmd_details)
5000 {
5001         struct i40e_aq_desc desc;
5002         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5003           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5004         enum i40e_status_code status;
5005
5006         i40e_fill_default_direct_cmd_desc(&desc,
5007                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5008
5009         cmd->seid = CPU_TO_LE16(seid);
5010         cmd->credit = CPU_TO_LE16(credit);
5011         cmd->max_bw = max_bw;
5012
5013         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5014
5015         return status;
5016 }
5017
5018 /**
5019  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5020  * @hw: pointer to the hw struct
5021  * @seid: VSI seid
5022  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5023  * @cmd_details: pointer to command details structure or NULL
5024  **/
5025 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5026                         u16 seid,
5027                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5028                         struct i40e_asq_cmd_details *cmd_details)
5029 {
5030         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5031                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5032                                     cmd_details);
5033 }
5034
5035 /**
5036  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5037  * @hw: pointer to the hw struct
5038  * @seid: VSI seid
5039  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5040  * @cmd_details: pointer to command details structure or NULL
5041  **/
5042 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5043                         u16 seid,
5044                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5045                         struct i40e_asq_cmd_details *cmd_details)
5046 {
5047         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5048                                     i40e_aqc_opc_configure_vsi_tc_bw,
5049                                     cmd_details);
5050 }
5051
5052 /**
5053  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5054  * @hw: pointer to the hw struct
5055  * @seid: seid of the switching component connected to Physical Port
5056  * @ets_data: Buffer holding ETS parameters
5057  * @cmd_details: pointer to command details structure or NULL
5058  **/
5059 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5060                 u16 seid,
5061                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5062                 enum i40e_admin_queue_opc opcode,
5063                 struct i40e_asq_cmd_details *cmd_details)
5064 {
5065         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5066                                     sizeof(*ets_data), opcode, cmd_details);
5067 }
5068
5069 /**
5070  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5071  * @hw: pointer to the hw struct
5072  * @seid: seid of the switching component
5073  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5074  * @cmd_details: pointer to command details structure or NULL
5075  **/
5076 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5077         u16 seid,
5078         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5079         struct i40e_asq_cmd_details *cmd_details)
5080 {
5081         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5082                             i40e_aqc_opc_configure_switching_comp_bw_config,
5083                             cmd_details);
5084 }
5085
5086 /**
5087  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5088  * @hw: pointer to the hw struct
5089  * @seid: seid of the switching component
5090  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5091  * @cmd_details: pointer to command details structure or NULL
5092  **/
5093 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5094         struct i40e_hw *hw, u16 seid,
5095         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5096         struct i40e_asq_cmd_details *cmd_details)
5097 {
5098         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5099                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5100                             cmd_details);
5101 }
5102
5103 /**
5104  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5105  * @hw: pointer to the hw struct
5106  * @seid: seid of the VSI
5107  * @bw_data: Buffer to hold VSI BW configuration
5108  * @cmd_details: pointer to command details structure or NULL
5109  **/
5110 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5111                         u16 seid,
5112                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5113                         struct i40e_asq_cmd_details *cmd_details)
5114 {
5115         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5116                                     i40e_aqc_opc_query_vsi_bw_config,
5117                                     cmd_details);
5118 }
5119
5120 /**
5121  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5122  * @hw: pointer to the hw struct
5123  * @seid: seid of the VSI
5124  * @bw_data: Buffer to hold VSI BW configuration per TC
5125  * @cmd_details: pointer to command details structure or NULL
5126  **/
5127 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5128                         u16 seid,
5129                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5130                         struct i40e_asq_cmd_details *cmd_details)
5131 {
5132         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5133                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5134                                     cmd_details);
5135 }
5136
5137 /**
5138  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5139  * @hw: pointer to the hw struct
5140  * @seid: seid of the switching component
5141  * @bw_data: Buffer to hold switching component's per TC BW config
5142  * @cmd_details: pointer to command details structure or NULL
5143  **/
5144 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5145                 u16 seid,
5146                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5147                 struct i40e_asq_cmd_details *cmd_details)
5148 {
5149         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5150                                    i40e_aqc_opc_query_switching_comp_ets_config,
5151                                    cmd_details);
5152 }
5153
5154 /**
5155  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5156  * @hw: pointer to the hw struct
5157  * @seid: seid of the VSI or switching component connected to Physical Port
5158  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5159  * @cmd_details: pointer to command details structure or NULL
5160  **/
5161 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5162                         u16 seid,
5163                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5164                         struct i40e_asq_cmd_details *cmd_details)
5165 {
5166         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5167                                     i40e_aqc_opc_query_port_ets_config,
5168                                     cmd_details);
5169 }
5170
5171 /**
5172  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5173  * @hw: pointer to the hw struct
5174  * @seid: seid of the switching component
5175  * @bw_data: Buffer to hold switching component's BW configuration
5176  * @cmd_details: pointer to command details structure or NULL
5177  **/
5178 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5179                 u16 seid,
5180                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5181                 struct i40e_asq_cmd_details *cmd_details)
5182 {
5183         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5184                                     i40e_aqc_opc_query_switching_comp_bw_config,
5185                                     cmd_details);
5186 }
5187
5188 /**
5189  * i40e_validate_filter_settings
5190  * @hw: pointer to the hardware structure
5191  * @settings: Filter control settings
5192  *
5193  * Check and validate the filter control settings passed.
5194  * The function checks for the valid filter/context sizes being
5195  * passed for FCoE and PE.
5196  *
5197  * Returns I40E_SUCCESS if the values passed are valid and within
5198  * range else returns an error.
5199  **/
5200 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5201                                 struct i40e_filter_control_settings *settings)
5202 {
5203         u32 fcoe_cntx_size, fcoe_filt_size;
5204         u32 pe_cntx_size, pe_filt_size;
5205         u32 fcoe_fmax;
5206
5207         u32 val;
5208
5209         /* Validate FCoE settings passed */
5210         switch (settings->fcoe_filt_num) {
5211         case I40E_HASH_FILTER_SIZE_1K:
5212         case I40E_HASH_FILTER_SIZE_2K:
5213         case I40E_HASH_FILTER_SIZE_4K:
5214         case I40E_HASH_FILTER_SIZE_8K:
5215         case I40E_HASH_FILTER_SIZE_16K:
5216         case I40E_HASH_FILTER_SIZE_32K:
5217                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5218                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5219                 break;
5220         default:
5221                 return I40E_ERR_PARAM;
5222         }
5223
5224         switch (settings->fcoe_cntx_num) {
5225         case I40E_DMA_CNTX_SIZE_512:
5226         case I40E_DMA_CNTX_SIZE_1K:
5227         case I40E_DMA_CNTX_SIZE_2K:
5228         case I40E_DMA_CNTX_SIZE_4K:
5229                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5230                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5231                 break;
5232         default:
5233                 return I40E_ERR_PARAM;
5234         }
5235
5236         /* Validate PE settings passed */
5237         switch (settings->pe_filt_num) {
5238         case I40E_HASH_FILTER_SIZE_1K:
5239         case I40E_HASH_FILTER_SIZE_2K:
5240         case I40E_HASH_FILTER_SIZE_4K:
5241         case I40E_HASH_FILTER_SIZE_8K:
5242         case I40E_HASH_FILTER_SIZE_16K:
5243         case I40E_HASH_FILTER_SIZE_32K:
5244         case I40E_HASH_FILTER_SIZE_64K:
5245         case I40E_HASH_FILTER_SIZE_128K:
5246         case I40E_HASH_FILTER_SIZE_256K:
5247         case I40E_HASH_FILTER_SIZE_512K:
5248         case I40E_HASH_FILTER_SIZE_1M:
5249                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5250                 pe_filt_size <<= (u32)settings->pe_filt_num;
5251                 break;
5252         default:
5253                 return I40E_ERR_PARAM;
5254         }
5255
5256         switch (settings->pe_cntx_num) {
5257         case I40E_DMA_CNTX_SIZE_512:
5258         case I40E_DMA_CNTX_SIZE_1K:
5259         case I40E_DMA_CNTX_SIZE_2K:
5260         case I40E_DMA_CNTX_SIZE_4K:
5261         case I40E_DMA_CNTX_SIZE_8K:
5262         case I40E_DMA_CNTX_SIZE_16K:
5263         case I40E_DMA_CNTX_SIZE_32K:
5264         case I40E_DMA_CNTX_SIZE_64K:
5265         case I40E_DMA_CNTX_SIZE_128K:
5266         case I40E_DMA_CNTX_SIZE_256K:
5267                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5268                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5269                 break;
5270         default:
5271                 return I40E_ERR_PARAM;
5272         }
5273
5274         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5275         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5276         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5277                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5278         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5279                 return I40E_ERR_INVALID_SIZE;
5280
5281         return I40E_SUCCESS;
5282 }
5283
5284 /**
5285  * i40e_set_filter_control
5286  * @hw: pointer to the hardware structure
5287  * @settings: Filter control settings
5288  *
5289  * Set the Queue Filters for PE/FCoE and enable filters required
5290  * for a single PF. It is expected that these settings are programmed
5291  * at the driver initialization time.
5292  **/
5293 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5294                                 struct i40e_filter_control_settings *settings)
5295 {
5296         enum i40e_status_code ret = I40E_SUCCESS;
5297         u32 hash_lut_size = 0;
5298         u32 val;
5299
5300         if (!settings)
5301                 return I40E_ERR_PARAM;
5302
5303         /* Validate the input settings */
5304         ret = i40e_validate_filter_settings(hw, settings);
5305         if (ret)
5306                 return ret;
5307
5308         /* Read the PF Queue Filter control register */
5309         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5310
5311         /* Program required PE hash buckets for the PF */
5312         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5313         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5314                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5315         /* Program required PE contexts for the PF */
5316         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5317         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5318                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5319
5320         /* Program required FCoE hash buckets for the PF */
5321         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5322         val |= ((u32)settings->fcoe_filt_num <<
5323                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5324                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5325         /* Program required FCoE DDP contexts for the PF */
5326         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5327         val |= ((u32)settings->fcoe_cntx_num <<
5328                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5329                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5330
5331         /* Program Hash LUT size for the PF */
5332         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5333         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5334                 hash_lut_size = 1;
5335         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5336                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5337
5338         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5339         if (settings->enable_fdir)
5340                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5341         if (settings->enable_ethtype)
5342                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5343         if (settings->enable_macvlan)
5344                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5345
5346         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5347
5348         return I40E_SUCCESS;
5349 }
5350
5351 /**
5352  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5353  * @hw: pointer to the hw struct
5354  * @mac_addr: MAC address to use in the filter
5355  * @ethtype: Ethertype to use in the filter
5356  * @flags: Flags that needs to be applied to the filter
5357  * @vsi_seid: seid of the control VSI
5358  * @queue: VSI queue number to send the packet to
5359  * @is_add: Add control packet filter if True else remove
5360  * @stats: Structure to hold information on control filter counts
5361  * @cmd_details: pointer to command details structure or NULL
5362  *
5363  * This command will Add or Remove control packet filter for a control VSI.
5364  * In return it will update the total number of perfect filter count in
5365  * the stats member.
5366  **/
5367 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5368                                 u8 *mac_addr, u16 ethtype, u16 flags,
5369                                 u16 vsi_seid, u16 queue, bool is_add,
5370                                 struct i40e_control_filter_stats *stats,
5371                                 struct i40e_asq_cmd_details *cmd_details)
5372 {
5373         struct i40e_aq_desc desc;
5374         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5375                 (struct i40e_aqc_add_remove_control_packet_filter *)
5376                 &desc.params.raw;
5377         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5378                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5379                 &desc.params.raw;
5380         enum i40e_status_code status;
5381
5382         if (vsi_seid == 0)
5383                 return I40E_ERR_PARAM;
5384
5385         if (is_add) {
5386                 i40e_fill_default_direct_cmd_desc(&desc,
5387                                 i40e_aqc_opc_add_control_packet_filter);
5388                 cmd->queue = CPU_TO_LE16(queue);
5389         } else {
5390                 i40e_fill_default_direct_cmd_desc(&desc,
5391                                 i40e_aqc_opc_remove_control_packet_filter);
5392         }
5393
5394         if (mac_addr)
5395                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5396                             I40E_NONDMA_TO_NONDMA);
5397
5398         cmd->etype = CPU_TO_LE16(ethtype);
5399         cmd->flags = CPU_TO_LE16(flags);
5400         cmd->seid = CPU_TO_LE16(vsi_seid);
5401
5402         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5403
5404         if (!status && stats) {
5405                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5406                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5407                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5408                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5409         }
5410
5411         return status;
5412 }
5413
5414 /**
5415  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5416  * @hw: pointer to the hw struct
5417  * @seid: VSI seid to add ethertype filter from
5418  **/
5419 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5420 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5421                                                     u16 seid)
5422 {
5423         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5424                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5425                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5426         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5427         enum i40e_status_code status;
5428
5429         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5430                                                        seid, 0, true, NULL,
5431                                                        NULL);
5432         if (status)
5433                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5434 }
5435
5436 /**
5437  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5438  * @filters: list of cloud filters
5439  * @filter_count: length of list
5440  *
5441  * There's an issue in the device where the Geneve VNI layout needs
5442  * to be shifted 1 byte over from the VxLAN VNI
5443  **/
5444 STATIC void i40e_fix_up_geneve_vni(
5445         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5446         u8 filter_count)
5447 {
5448         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5449         int i;
5450
5451         for (i = 0; i < filter_count; i++) {
5452                 u16 tnl_type;
5453                 u32 ti;
5454
5455                 tnl_type = (le16_to_cpu(f[i].flags) &
5456                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5457                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5458                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5459                         ti = le32_to_cpu(f[i].tenant_id);
5460                         f[i].tenant_id = cpu_to_le32(ti << 8);
5461                 }
5462         }
5463 }
5464
5465 /**
5466  * i40e_aq_add_cloud_filters
5467  * @hw: pointer to the hardware structure
5468  * @seid: VSI seid to add cloud filters from
5469  * @filters: Buffer which contains the filters to be added
5470  * @filter_count: number of filters contained in the buffer
5471  *
5472  * Set the cloud filters for a given VSI.  The contents of the
5473  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5474  * in by the caller of the function.
5475  *
5476  **/
5477 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5478         u16 seid,
5479         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5480         u8 filter_count)
5481 {
5482         struct i40e_aq_desc desc;
5483         struct i40e_aqc_add_remove_cloud_filters *cmd =
5484         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5485         enum i40e_status_code status;
5486         u16 buff_len;
5487
5488         i40e_fill_default_direct_cmd_desc(&desc,
5489                                           i40e_aqc_opc_add_cloud_filters);
5490
5491         buff_len = filter_count * sizeof(*filters);
5492         desc.datalen = CPU_TO_LE16(buff_len);
5493         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5494         cmd->num_filters = filter_count;
5495         cmd->seid = CPU_TO_LE16(seid);
5496
5497         i40e_fix_up_geneve_vni(filters, filter_count);
5498
5499         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5500
5501         return status;
5502 }
5503
5504 /**
5505  * i40e_aq_remove_cloud_filters
5506  * @hw: pointer to the hardware structure
5507  * @seid: VSI seid to remove cloud filters from
5508  * @filters: Buffer which contains the filters to be removed
5509  * @filter_count: number of filters contained in the buffer
5510  *
5511  * Remove the cloud filters for a given VSI.  The contents of the
5512  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5513  * in by the caller of the function.
5514  *
5515  **/
5516 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5517                 u16 seid,
5518                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5519                 u8 filter_count)
5520 {
5521         struct i40e_aq_desc desc;
5522         struct i40e_aqc_add_remove_cloud_filters *cmd =
5523         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5524         enum i40e_status_code status;
5525         u16 buff_len;
5526
5527         i40e_fill_default_direct_cmd_desc(&desc,
5528                                           i40e_aqc_opc_remove_cloud_filters);
5529
5530         buff_len = filter_count * sizeof(*filters);
5531         desc.datalen = CPU_TO_LE16(buff_len);
5532         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5533         cmd->num_filters = filter_count;
5534         cmd->seid = CPU_TO_LE16(seid);
5535
5536         i40e_fix_up_geneve_vni(filters, filter_count);
5537
5538         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5539
5540         return status;
5541 }
5542
5543 /**
5544  * i40e_aq_alternate_write
5545  * @hw: pointer to the hardware structure
5546  * @reg_addr0: address of first dword to be read
5547  * @reg_val0: value to be written under 'reg_addr0'
5548  * @reg_addr1: address of second dword to be read
5549  * @reg_val1: value to be written under 'reg_addr1'
5550  *
5551  * Write one or two dwords to alternate structure. Fields are indicated
5552  * by 'reg_addr0' and 'reg_addr1' register numbers.
5553  *
5554  **/
5555 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5556                                 u32 reg_addr0, u32 reg_val0,
5557                                 u32 reg_addr1, u32 reg_val1)
5558 {
5559         struct i40e_aq_desc desc;
5560         struct i40e_aqc_alternate_write *cmd_resp =
5561                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5562         enum i40e_status_code status;
5563
5564         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5565         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5566         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5567         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5568         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5569
5570         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5571
5572         return status;
5573 }
5574
5575 /**
5576  * i40e_aq_alternate_write_indirect
5577  * @hw: pointer to the hardware structure
5578  * @addr: address of a first register to be modified
5579  * @dw_count: number of alternate structure fields to write
5580  * @buffer: pointer to the command buffer
5581  *
5582  * Write 'dw_count' dwords from 'buffer' to alternate structure
5583  * starting at 'addr'.
5584  *
5585  **/
5586 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5587                                 u32 addr, u32 dw_count, void *buffer)
5588 {
5589         struct i40e_aq_desc desc;
5590         struct i40e_aqc_alternate_ind_write *cmd_resp =
5591                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5592         enum i40e_status_code status;
5593
5594         if (buffer == NULL)
5595                 return I40E_ERR_PARAM;
5596
5597         /* Indirect command */
5598         i40e_fill_default_direct_cmd_desc(&desc,
5599                                          i40e_aqc_opc_alternate_write_indirect);
5600
5601         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5602         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5603         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5604                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5605
5606         cmd_resp->address = CPU_TO_LE32(addr);
5607         cmd_resp->length = CPU_TO_LE32(dw_count);
5608
5609         status = i40e_asq_send_command(hw, &desc, buffer,
5610                                        I40E_LO_DWORD(4*dw_count), NULL);
5611
5612         return status;
5613 }
5614
5615 /**
5616  * i40e_aq_alternate_read
5617  * @hw: pointer to the hardware structure
5618  * @reg_addr0: address of first dword to be read
5619  * @reg_val0: pointer for data read from 'reg_addr0'
5620  * @reg_addr1: address of second dword to be read
5621  * @reg_val1: pointer for data read from 'reg_addr1'
5622  *
5623  * Read one or two dwords from alternate structure. Fields are indicated
5624  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5625  * is not passed then only register at 'reg_addr0' is read.
5626  *
5627  **/
5628 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5629                                 u32 reg_addr0, u32 *reg_val0,
5630                                 u32 reg_addr1, u32 *reg_val1)
5631 {
5632         struct i40e_aq_desc desc;
5633         struct i40e_aqc_alternate_write *cmd_resp =
5634                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5635         enum i40e_status_code status;
5636
5637         if (reg_val0 == NULL)
5638                 return I40E_ERR_PARAM;
5639
5640         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5641         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5642         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5643
5644         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5645
5646         if (status == I40E_SUCCESS) {
5647                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5648
5649                 if (reg_val1 != NULL)
5650                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5651         }
5652
5653         return status;
5654 }
5655
5656 /**
5657  * i40e_aq_alternate_read_indirect
5658  * @hw: pointer to the hardware structure
5659  * @addr: address of the alternate structure field
5660  * @dw_count: number of alternate structure fields to read
5661  * @buffer: pointer to the command buffer
5662  *
5663  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5664  * place them in 'buffer'. The buffer should be allocated by caller.
5665  *
5666  **/
5667 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5668                                 u32 addr, u32 dw_count, void *buffer)
5669 {
5670         struct i40e_aq_desc desc;
5671         struct i40e_aqc_alternate_ind_write *cmd_resp =
5672                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5673         enum i40e_status_code status;
5674
5675         if (buffer == NULL)
5676                 return I40E_ERR_PARAM;
5677
5678         /* Indirect command */
5679         i40e_fill_default_direct_cmd_desc(&desc,
5680                 i40e_aqc_opc_alternate_read_indirect);
5681
5682         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5683         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5684         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5685                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5686
5687         cmd_resp->address = CPU_TO_LE32(addr);
5688         cmd_resp->length = CPU_TO_LE32(dw_count);
5689
5690         status = i40e_asq_send_command(hw, &desc, buffer,
5691                                        I40E_LO_DWORD(4*dw_count), NULL);
5692
5693         return status;
5694 }
5695
5696 /**
5697  *  i40e_aq_alternate_clear
5698  *  @hw: pointer to the HW structure.
5699  *
5700  *  Clear the alternate structures of the port from which the function
5701  *  is called.
5702  *
5703  **/
5704 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5705 {
5706         struct i40e_aq_desc desc;
5707         enum i40e_status_code status;
5708
5709         i40e_fill_default_direct_cmd_desc(&desc,
5710                                           i40e_aqc_opc_alternate_clear_port);
5711
5712         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5713
5714         return status;
5715 }
5716
5717 /**
5718  *  i40e_aq_alternate_write_done
5719  *  @hw: pointer to the HW structure.
5720  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5721  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5722  *
5723  *  Indicates to the FW that alternate structures have been changed.
5724  *
5725  **/
5726 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5727                 u8 bios_mode, bool *reset_needed)
5728 {
5729         struct i40e_aq_desc desc;
5730         struct i40e_aqc_alternate_write_done *cmd =
5731                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5732         enum i40e_status_code status;
5733
5734         if (reset_needed == NULL)
5735                 return I40E_ERR_PARAM;
5736
5737         i40e_fill_default_direct_cmd_desc(&desc,
5738                                           i40e_aqc_opc_alternate_write_done);
5739
5740         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5741
5742         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5743         if (!status && reset_needed)
5744                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5745                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5746
5747         return status;
5748 }
5749
5750 /**
5751  *  i40e_aq_set_oem_mode
5752  *  @hw: pointer to the HW structure.
5753  *  @oem_mode: the OEM mode to be used
5754  *
5755  *  Sets the device to a specific operating mode. Currently the only supported
5756  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5757  *
5758  **/
5759 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5760                 u8 oem_mode)
5761 {
5762         struct i40e_aq_desc desc;
5763         struct i40e_aqc_alternate_write_done *cmd =
5764                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5765         enum i40e_status_code status;
5766
5767         i40e_fill_default_direct_cmd_desc(&desc,
5768                                           i40e_aqc_opc_alternate_set_mode);
5769
5770         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5771
5772         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5773
5774         return status;
5775 }
5776
5777 /**
5778  * i40e_aq_resume_port_tx
5779  * @hw: pointer to the hardware structure
5780  * @cmd_details: pointer to command details structure or NULL
5781  *
5782  * Resume port's Tx traffic
5783  **/
5784 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5785                                 struct i40e_asq_cmd_details *cmd_details)
5786 {
5787         struct i40e_aq_desc desc;
5788         enum i40e_status_code status;
5789
5790         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5791
5792         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5793
5794         return status;
5795 }
5796
5797 /**
5798  * i40e_set_pci_config_data - store PCI bus info
5799  * @hw: pointer to hardware structure
5800  * @link_status: the link status word from PCI config space
5801  *
5802  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5803  **/
5804 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5805 {
5806         hw->bus.type = i40e_bus_type_pci_express;
5807
5808         switch (link_status & I40E_PCI_LINK_WIDTH) {
5809         case I40E_PCI_LINK_WIDTH_1:
5810                 hw->bus.width = i40e_bus_width_pcie_x1;
5811                 break;
5812         case I40E_PCI_LINK_WIDTH_2:
5813                 hw->bus.width = i40e_bus_width_pcie_x2;
5814                 break;
5815         case I40E_PCI_LINK_WIDTH_4:
5816                 hw->bus.width = i40e_bus_width_pcie_x4;
5817                 break;
5818         case I40E_PCI_LINK_WIDTH_8:
5819                 hw->bus.width = i40e_bus_width_pcie_x8;
5820                 break;
5821         default:
5822                 hw->bus.width = i40e_bus_width_unknown;
5823                 break;
5824         }
5825
5826         switch (link_status & I40E_PCI_LINK_SPEED) {
5827         case I40E_PCI_LINK_SPEED_2500:
5828                 hw->bus.speed = i40e_bus_speed_2500;
5829                 break;
5830         case I40E_PCI_LINK_SPEED_5000:
5831                 hw->bus.speed = i40e_bus_speed_5000;
5832                 break;
5833         case I40E_PCI_LINK_SPEED_8000:
5834                 hw->bus.speed = i40e_bus_speed_8000;
5835                 break;
5836         default:
5837                 hw->bus.speed = i40e_bus_speed_unknown;
5838                 break;
5839         }
5840 }
5841
5842 /**
5843  * i40e_aq_debug_dump
5844  * @hw: pointer to the hardware structure
5845  * @cluster_id: specific cluster to dump
5846  * @table_id: table id within cluster
5847  * @start_index: index of line in the block to read
5848  * @buff_size: dump buffer size
5849  * @buff: dump buffer
5850  * @ret_buff_size: actual buffer size returned
5851  * @ret_next_table: next block to read
5852  * @ret_next_index: next index to read
5853  *
5854  * Dump internal FW/HW data for debug purposes.
5855  *
5856  **/
5857 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5858                                 u8 table_id, u32 start_index, u16 buff_size,
5859                                 void *buff, u16 *ret_buff_size,
5860                                 u8 *ret_next_table, u32 *ret_next_index,
5861                                 struct i40e_asq_cmd_details *cmd_details)
5862 {
5863         struct i40e_aq_desc desc;
5864         struct i40e_aqc_debug_dump_internals *cmd =
5865                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5866         struct i40e_aqc_debug_dump_internals *resp =
5867                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5868         enum i40e_status_code status;
5869
5870         if (buff_size == 0 || !buff)
5871                 return I40E_ERR_PARAM;
5872
5873         i40e_fill_default_direct_cmd_desc(&desc,
5874                                           i40e_aqc_opc_debug_dump_internals);
5875         /* Indirect Command */
5876         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5877         if (buff_size > I40E_AQ_LARGE_BUF)
5878                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5879
5880         cmd->cluster_id = cluster_id;
5881         cmd->table_id = table_id;
5882         cmd->idx = CPU_TO_LE32(start_index);
5883
5884         desc.datalen = CPU_TO_LE16(buff_size);
5885
5886         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5887         if (!status) {
5888                 if (ret_buff_size != NULL)
5889                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5890                 if (ret_next_table != NULL)
5891                         *ret_next_table = resp->table_id;
5892                 if (ret_next_index != NULL)
5893                         *ret_next_index = LE32_TO_CPU(resp->idx);
5894         }
5895
5896         return status;
5897 }
5898
5899 /**
5900  * i40e_read_bw_from_alt_ram
5901  * @hw: pointer to the hardware structure
5902  * @max_bw: pointer for max_bw read
5903  * @min_bw: pointer for min_bw read
5904  * @min_valid: pointer for bool that is true if min_bw is a valid value
5905  * @max_valid: pointer for bool that is true if max_bw is a valid value
5906  *
5907  * Read bw from the alternate ram for the given pf
5908  **/
5909 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5910                                         u32 *max_bw, u32 *min_bw,
5911                                         bool *min_valid, bool *max_valid)
5912 {
5913         enum i40e_status_code status;
5914         u32 max_bw_addr, min_bw_addr;
5915
5916         /* Calculate the address of the min/max bw registers */
5917         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5918                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5919                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5920         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5921                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5922                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5923
5924         /* Read the bandwidths from alt ram */
5925         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5926                                         min_bw_addr, min_bw);
5927
5928         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5929                 *min_valid = true;
5930         else
5931                 *min_valid = false;
5932
5933         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5934                 *max_valid = true;
5935         else
5936                 *max_valid = false;
5937
5938         return status;
5939 }
5940
5941 /**
5942  * i40e_aq_configure_partition_bw
5943  * @hw: pointer to the hardware structure
5944  * @bw_data: Buffer holding valid pfs and bw limits
5945  * @cmd_details: pointer to command details
5946  *
5947  * Configure partitions guaranteed/max bw
5948  **/
5949 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5950                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5951                         struct i40e_asq_cmd_details *cmd_details)
5952 {
5953         enum i40e_status_code status;
5954         struct i40e_aq_desc desc;
5955         u16 bwd_size = sizeof(*bw_data);
5956
5957         i40e_fill_default_direct_cmd_desc(&desc,
5958                                 i40e_aqc_opc_configure_partition_bw);
5959
5960         /* Indirect command */
5961         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5962         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5963
5964         if (bwd_size > I40E_AQ_LARGE_BUF)
5965                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5966
5967         desc.datalen = CPU_TO_LE16(bwd_size);
5968
5969         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5970
5971         return status;
5972 }
5973
5974 /**
5975  * i40e_read_phy_register
5976  * @hw: pointer to the HW structure
5977  * @page: registers page number
5978  * @reg: register address in the page
5979  * @phy_adr: PHY address on MDIO interface
5980  * @value: PHY register value
5981  *
5982  * Reads specified PHY register value
5983  **/
5984 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
5985                                              u8 page, u16 reg, u8 phy_addr,
5986                                              u16 *value)
5987 {
5988         enum i40e_status_code status = I40E_ERR_TIMEOUT;
5989         u32 command  = 0;
5990         u16 retry = 1000;
5991         u8 port_num = (u8)hw->func_caps.mdio_port_num;
5992
5993         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
5994                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
5995                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
5996                   (I40E_MDIO_OPCODE_ADDRESS) |
5997                   (I40E_MDIO_STCODE) |
5998                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
5999                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6000         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6001         do {
6002                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6003                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6004                         status = I40E_SUCCESS;
6005                         break;
6006                 }
6007                 i40e_usec_delay(10);
6008                 retry--;
6009         } while (retry);
6010
6011         if (status) {
6012                 i40e_debug(hw, I40E_DEBUG_PHY,
6013                            "PHY: Can't write command to external PHY.\n");
6014                 goto phy_read_end;
6015         }
6016
6017         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6018                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6019                   (I40E_MDIO_OPCODE_READ) |
6020                   (I40E_MDIO_STCODE) |
6021                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6022                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6023         status = I40E_ERR_TIMEOUT;
6024         retry = 1000;
6025         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6026         do {
6027                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6028                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6029                         status = I40E_SUCCESS;
6030                         break;
6031                 }
6032                 i40e_usec_delay(10);
6033                 retry--;
6034         } while (retry);
6035
6036         if (!status) {
6037                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6038                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6039                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6040         } else {
6041                 i40e_debug(hw, I40E_DEBUG_PHY,
6042                            "PHY: Can't read register value from external PHY.\n");
6043         }
6044
6045 phy_read_end:
6046         return status;
6047 }
6048
6049 /**
6050  * i40e_write_phy_register
6051  * @hw: pointer to the HW structure
6052  * @page: registers page number
6053  * @reg: register address in the page
6054  * @phy_adr: PHY address on MDIO interface
6055  * @value: PHY register value
6056  *
6057  * Writes value to specified PHY register
6058  **/
6059 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6060                                               u8 page, u16 reg, u8 phy_addr,
6061                                               u16 value)
6062 {
6063         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6064         u32 command  = 0;
6065         u16 retry = 1000;
6066         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6067
6068         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6069                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6070                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6071                   (I40E_MDIO_OPCODE_ADDRESS) |
6072                   (I40E_MDIO_STCODE) |
6073                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6074                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6075         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6076         do {
6077                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6078                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6079                         status = I40E_SUCCESS;
6080                         break;
6081                 }
6082                 i40e_usec_delay(10);
6083                 retry--;
6084         } while (retry);
6085         if (status) {
6086                 i40e_debug(hw, I40E_DEBUG_PHY,
6087                            "PHY: Can't write command to external PHY.\n");
6088                 goto phy_write_end;
6089         }
6090
6091         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6092         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6093
6094         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6095                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6096                   (I40E_MDIO_OPCODE_WRITE) |
6097                   (I40E_MDIO_STCODE) |
6098                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6099                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6100         status = I40E_ERR_TIMEOUT;
6101         retry = 1000;
6102         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6103         do {
6104                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6105                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6106                         status = I40E_SUCCESS;
6107                         break;
6108                 }
6109                 i40e_usec_delay(10);
6110                 retry--;
6111         } while (retry);
6112
6113 phy_write_end:
6114         return status;
6115 }
6116
6117 /**
6118  * i40e_get_phy_address
6119  * @hw: pointer to the HW structure
6120  * @dev_num: PHY port num that address we want
6121  * @phy_addr: Returned PHY address
6122  *
6123  * Gets PHY address for current port
6124  **/
6125 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6126 {
6127         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6128         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6129
6130         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6131 }
6132
6133 /**
6134  * i40e_blink_phy_led
6135  * @hw: pointer to the HW structure
6136  * @time: time how long led will blinks in secs
6137  * @interval: gap between LED on and off in msecs
6138  *
6139  * Blinks PHY link LED
6140  **/
6141 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6142                                               u32 time, u32 interval)
6143 {
6144         enum i40e_status_code status = I40E_SUCCESS;
6145         u32 i;
6146         u16 led_ctl = 0;
6147         u16 gpio_led_port;
6148         u16 led_reg;
6149         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6150         u8 phy_addr = 0;
6151         u8 port_num;
6152
6153         i = rd32(hw, I40E_PFGEN_PORTNUM);
6154         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6155         phy_addr = i40e_get_phy_address(hw, port_num);
6156
6157         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6158              led_addr++) {
6159                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6160                                                 led_addr, phy_addr, &led_reg);
6161                 if (status)
6162                         goto phy_blinking_end;
6163                 led_ctl = led_reg;
6164                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6165                         led_reg = 0;
6166                         status = i40e_write_phy_register(hw,
6167                                                          I40E_PHY_COM_REG_PAGE,
6168                                                          led_addr, phy_addr,
6169                                                          led_reg);
6170                         if (status)
6171                                 goto phy_blinking_end;
6172                         break;
6173                 }
6174         }
6175
6176         if (time > 0 && interval > 0) {
6177                 for (i = 0; i < time * 1000; i += interval) {
6178                         status = i40e_read_phy_register(hw,
6179                                                         I40E_PHY_COM_REG_PAGE,
6180                                                         led_addr, phy_addr,
6181                                                         &led_reg);
6182                         if (status)
6183                                 goto restore_config;
6184                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6185                                 led_reg = 0;
6186                         else
6187                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6188                         status = i40e_write_phy_register(hw,
6189                                                          I40E_PHY_COM_REG_PAGE,
6190                                                          led_addr, phy_addr,
6191                                                          led_reg);
6192                         if (status)
6193                                 goto restore_config;
6194                         i40e_msec_delay(interval);
6195                 }
6196         }
6197
6198 restore_config:
6199         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6200                                          phy_addr, led_ctl);
6201
6202 phy_blinking_end:
6203         return status;
6204 }
6205
6206 /**
6207  * i40e_led_get_phy - return current on/off mode
6208  * @hw: pointer to the hw struct
6209  * @led_addr: address of led register to use
6210  * @val: original value of register to use
6211  *
6212  **/
6213 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6214                                        u16 *val)
6215 {
6216         enum i40e_status_code status = I40E_SUCCESS;
6217         u16 gpio_led_port;
6218         u8 phy_addr = 0;
6219         u16 reg_val;
6220         u16 temp_addr;
6221         u8 port_num;
6222         u32 i;
6223
6224         temp_addr = I40E_PHY_LED_PROV_REG_1;
6225         i = rd32(hw, I40E_PFGEN_PORTNUM);
6226         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6227         phy_addr = i40e_get_phy_address(hw, port_num);
6228
6229         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6230              temp_addr++) {
6231                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6232                                                 temp_addr, phy_addr, &reg_val);
6233                 if (status)
6234                         return status;
6235                 *val = reg_val;
6236                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6237                         *led_addr = temp_addr;
6238                         break;
6239                 }
6240         }
6241         return status;
6242 }
6243
6244 /**
6245  * i40e_led_set_phy
6246  * @hw: pointer to the HW structure
6247  * @on: true or false
6248  * @mode: original val plus bit for set or ignore
6249  * Set led's on or off when controlled by the PHY
6250  *
6251  **/
6252 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6253                                        u16 led_addr, u32 mode)
6254 {
6255         enum i40e_status_code status = I40E_SUCCESS;
6256         u16 led_ctl = 0;
6257         u16 led_reg = 0;
6258         u8 phy_addr = 0;
6259         u8 port_num;
6260         u32 i;
6261
6262         i = rd32(hw, I40E_PFGEN_PORTNUM);
6263         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6264         phy_addr = i40e_get_phy_address(hw, port_num);
6265
6266         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6267                                         phy_addr, &led_reg);
6268         if (status)
6269                 return status;
6270         led_ctl = led_reg;
6271         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6272                 led_reg = 0;
6273                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6274                                                  led_addr, phy_addr, led_reg);
6275                 if (status)
6276                         return status;
6277         }
6278         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6279                                         led_addr, phy_addr, &led_reg);
6280         if (status)
6281                 goto restore_config;
6282         if (on)
6283                 led_reg = I40E_PHY_LED_MANUAL_ON;
6284         else
6285                 led_reg = 0;
6286         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6287                                          led_addr, phy_addr, led_reg);
6288         if (status)
6289                 goto restore_config;
6290         if (mode & I40E_PHY_LED_MODE_ORIG) {
6291                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6292                 status = i40e_write_phy_register(hw,
6293                                                  I40E_PHY_COM_REG_PAGE,
6294                                                  led_addr, phy_addr, led_ctl);
6295         }
6296         return status;
6297 restore_config:
6298         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6299                                          phy_addr, led_ctl);
6300         return status;
6301 }
6302 #endif /* PF_DRIVER */
6303
6304 /**
6305  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6306  * @hw: pointer to the hw struct
6307  * @reg_addr: register address
6308  * @reg_val: ptr to register value
6309  * @cmd_details: pointer to command details structure or NULL
6310  *
6311  * Use the firmware to read the Rx control register,
6312  * especially useful if the Rx unit is under heavy pressure
6313  **/
6314 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6315                                 u32 reg_addr, u32 *reg_val,
6316                                 struct i40e_asq_cmd_details *cmd_details)
6317 {
6318         struct i40e_aq_desc desc;
6319         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6320                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6321         enum i40e_status_code status;
6322
6323         if (reg_val == NULL)
6324                 return I40E_ERR_PARAM;
6325
6326         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6327
6328         cmd_resp->address = CPU_TO_LE32(reg_addr);
6329
6330         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6331
6332         if (status == I40E_SUCCESS)
6333                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6334
6335         return status;
6336 }
6337
6338 /**
6339  * i40e_read_rx_ctl - read from an Rx control register
6340  * @hw: pointer to the hw struct
6341  * @reg_addr: register address
6342  **/
6343 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6344 {
6345         enum i40e_status_code status = I40E_SUCCESS;
6346         bool use_register;
6347         int retry = 5;
6348         u32 val = 0;
6349
6350         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6351         if (!use_register) {
6352 do_retry:
6353                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6354                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6355                         i40e_msec_delay(1);
6356                         retry--;
6357                         goto do_retry;
6358                 }
6359         }
6360
6361         /* if the AQ access failed, try the old-fashioned way */
6362         if (status || use_register)
6363                 val = rd32(hw, reg_addr);
6364
6365         return val;
6366 }
6367
6368 /**
6369  * i40e_aq_rx_ctl_write_register
6370  * @hw: pointer to the hw struct
6371  * @reg_addr: register address
6372  * @reg_val: register value
6373  * @cmd_details: pointer to command details structure or NULL
6374  *
6375  * Use the firmware to write to an Rx control register,
6376  * especially useful if the Rx unit is under heavy pressure
6377  **/
6378 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6379                                 u32 reg_addr, u32 reg_val,
6380                                 struct i40e_asq_cmd_details *cmd_details)
6381 {
6382         struct i40e_aq_desc desc;
6383         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6384                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6385         enum i40e_status_code status;
6386
6387         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6388
6389         cmd->address = CPU_TO_LE32(reg_addr);
6390         cmd->value = CPU_TO_LE32(reg_val);
6391
6392         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6393
6394         return status;
6395 }
6396
6397 /**
6398  * i40e_write_rx_ctl - write to an Rx control register
6399  * @hw: pointer to the hw struct
6400  * @reg_addr: register address
6401  * @reg_val: register value
6402  **/
6403 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6404 {
6405         enum i40e_status_code status = I40E_SUCCESS;
6406         bool use_register;
6407         int retry = 5;
6408
6409         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6410         if (!use_register) {
6411 do_retry:
6412                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6413                                                        reg_val, NULL);
6414                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6415                         i40e_msec_delay(1);
6416                         retry--;
6417                         goto do_retry;
6418                 }
6419         }
6420
6421         /* if the AQ access failed, try the old-fashioned way */
6422         if (status || use_register)
6423                 wr32(hw, reg_addr, reg_val);
6424 }
6425 #ifdef VF_DRIVER
6426
6427 /**
6428  * i40e_aq_send_msg_to_pf
6429  * @hw: pointer to the hardware structure
6430  * @v_opcode: opcodes for VF-PF communication
6431  * @v_retval: return error code
6432  * @msg: pointer to the msg buffer
6433  * @msglen: msg length
6434  * @cmd_details: pointer to command details
6435  *
6436  * Send message to PF driver using admin queue. By default, this message
6437  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6438  * completion before returning.
6439  **/
6440 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6441                                 enum i40e_virtchnl_ops v_opcode,
6442                                 enum i40e_status_code v_retval,
6443                                 u8 *msg, u16 msglen,
6444                                 struct i40e_asq_cmd_details *cmd_details)
6445 {
6446         struct i40e_aq_desc desc;
6447         struct i40e_asq_cmd_details details;
6448         enum i40e_status_code status;
6449
6450         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6451         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6452         desc.cookie_high = CPU_TO_LE32(v_opcode);
6453         desc.cookie_low = CPU_TO_LE32(v_retval);
6454         if (msglen) {
6455                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6456                                                 | I40E_AQ_FLAG_RD));
6457                 if (msglen > I40E_AQ_LARGE_BUF)
6458                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6459                 desc.datalen = CPU_TO_LE16(msglen);
6460         }
6461         if (!cmd_details) {
6462                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6463                 details.async = true;
6464                 cmd_details = &details;
6465         }
6466         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6467                                        msglen, cmd_details);
6468         return status;
6469 }
6470
6471 /**
6472  * i40e_vf_parse_hw_config
6473  * @hw: pointer to the hardware structure
6474  * @msg: pointer to the virtual channel VF resource structure
6475  *
6476  * Given a VF resource message from the PF, populate the hw struct
6477  * with appropriate information.
6478  **/
6479 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6480                              struct i40e_virtchnl_vf_resource *msg)
6481 {
6482         struct i40e_virtchnl_vsi_resource *vsi_res;
6483         int i;
6484
6485         vsi_res = &msg->vsi_res[0];
6486
6487         hw->dev_caps.num_vsis = msg->num_vsis;
6488         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6489         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6490         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6491         hw->dev_caps.dcb = msg->vf_offload_flags &
6492                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6493         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6494                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6495         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6496                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6497         for (i = 0; i < msg->num_vsis; i++) {
6498                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6499                         i40e_memcpy(hw->mac.perm_addr,
6500                                     vsi_res->default_mac_addr,
6501                                     I40E_ETH_LENGTH_OF_ADDRESS,
6502                                     I40E_NONDMA_TO_NONDMA);
6503                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6504                                     I40E_ETH_LENGTH_OF_ADDRESS,
6505                                     I40E_NONDMA_TO_NONDMA);
6506                 }
6507                 vsi_res++;
6508         }
6509 }
6510
6511 /**
6512  * i40e_vf_reset
6513  * @hw: pointer to the hardware structure
6514  *
6515  * Send a VF_RESET message to the PF. Does not wait for response from PF
6516  * as none will be forthcoming. Immediately after calling this function,
6517  * the admin queue should be shut down and (optionally) reinitialized.
6518  **/
6519 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6520 {
6521         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6522                                       I40E_SUCCESS, NULL, 0, NULL);
6523 }
6524 #endif /* VF_DRIVER */
6525 #ifdef X722_SUPPORT
6526
6527 /**
6528  * i40e_aq_set_arp_proxy_config
6529  * @hw: pointer to the HW structure
6530  * @proxy_config - pointer to proxy config command table struct
6531  * @cmd_details: pointer to command details
6532  *
6533  * Set ARP offload parameters from pre-populated
6534  * i40e_aqc_arp_proxy_data struct
6535  **/
6536 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6537                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6538                                 struct i40e_asq_cmd_details *cmd_details)
6539 {
6540         struct i40e_aq_desc desc;
6541         enum i40e_status_code status;
6542
6543         if (!proxy_config)
6544                 return I40E_ERR_PARAM;
6545
6546         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6547
6548         desc.params.external.addr_high =
6549                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6550         desc.params.external.addr_low =
6551                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6552
6553         status = i40e_asq_send_command(hw, &desc, proxy_config,
6554                                        sizeof(struct i40e_aqc_arp_proxy_data),
6555                                        cmd_details);
6556
6557         return status;
6558 }
6559
6560 /**
6561  * i40e_aq_opc_set_ns_proxy_table_entry
6562  * @hw: pointer to the HW structure
6563  * @ns_proxy_table_entry: pointer to NS table entry command struct
6564  * @cmd_details: pointer to command details
6565  *
6566  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6567  * from pre-populated i40e_aqc_ns_proxy_data struct
6568  **/
6569 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6570                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6571                         struct i40e_asq_cmd_details *cmd_details)
6572 {
6573         struct i40e_aq_desc desc;
6574         enum i40e_status_code status;
6575
6576         if (!ns_proxy_table_entry)
6577                 return I40E_ERR_PARAM;
6578
6579         i40e_fill_default_direct_cmd_desc(&desc,
6580                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6581
6582         desc.params.external.addr_high =
6583                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6584         desc.params.external.addr_low =
6585                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6586
6587         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6588                                        sizeof(struct i40e_aqc_ns_proxy_data),
6589                                        cmd_details);
6590
6591         return status;
6592 }
6593
6594 /**
6595  * i40e_aq_set_clear_wol_filter
6596  * @hw: pointer to the hw struct
6597  * @filter_index: index of filter to modify (0-7)
6598  * @filter: buffer containing filter to be set
6599  * @set_filter: true to set filter, false to clear filter
6600  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6601  *              if false, pass through packets may cause wake-up
6602  * @filter_valid: true if filter action is valid
6603  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6604  * @cmd_details: pointer to command details structure or NULL
6605  *
6606  * Set or clear WoL filter for port attached to the PF
6607  **/
6608 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6609                                 u8 filter_index,
6610                                 struct i40e_aqc_set_wol_filter_data *filter,
6611                                 bool set_filter, bool no_wol_tco,
6612                                 bool filter_valid, bool no_wol_tco_valid,
6613                                 struct i40e_asq_cmd_details *cmd_details)
6614 {
6615         struct i40e_aq_desc desc;
6616         struct i40e_aqc_set_wol_filter *cmd =
6617                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6618         enum i40e_status_code status;
6619         u16 cmd_flags = 0;
6620         u16 valid_flags = 0;
6621         u16 buff_len = 0;
6622
6623         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6624
6625         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6626                 return  I40E_ERR_PARAM;
6627         cmd->filter_index = CPU_TO_LE16(filter_index);
6628
6629         if (set_filter) {
6630                 if (!filter)
6631                         return  I40E_ERR_PARAM;
6632                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6633                 buff_len = sizeof(*filter);
6634         }
6635         if (no_wol_tco)
6636                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6637         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6638
6639         if (filter_valid)
6640                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6641         if (no_wol_tco_valid)
6642                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6643         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6644
6645         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6646         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6647
6648         status = i40e_asq_send_command(hw, &desc, filter,
6649                                        buff_len, cmd_details);
6650
6651         return status;
6652 }
6653
6654 /**
6655  * i40e_aq_get_wake_event_reason
6656  * @hw: pointer to the hw struct
6657  * @wake_reason: return value, index of matching filter
6658  * @cmd_details: pointer to command details structure or NULL
6659  *
6660  * Get information for the reason of a Wake Up event
6661  **/
6662 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6663                                 u16 *wake_reason,
6664                                 struct i40e_asq_cmd_details *cmd_details)
6665 {
6666         struct i40e_aq_desc desc;
6667         struct i40e_aqc_get_wake_reason_completion *resp =
6668                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6669         enum i40e_status_code status;
6670
6671         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6672
6673         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6674
6675         if (status == I40E_SUCCESS)
6676                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6677
6678         return status;
6679 }
6680
6681 #endif /* X722_SUPPORT */