drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                 case I40E_DEV_ID_25G_B:
  71                 case I40E_DEV_ID_25G_SFP28:
  72                         hw->mac.type = I40E_MAC_XL710;
  73                         break;
  74 #ifdef X722_SUPPORT
  75 #ifdef X722_A0_SUPPORT
  76                 case I40E_DEV_ID_X722_A0:
  77 #endif
  78                 case I40E_DEV_ID_KX_X722:
  79                 case I40E_DEV_ID_QSFP_X722:
  80                 case I40E_DEV_ID_SFP_X722:
  81                 case I40E_DEV_ID_1G_BASE_T_X722:
  82                 case I40E_DEV_ID_10G_BASE_T_X722:
  83                 case I40E_DEV_ID_SFP_I_X722:
  84                         hw->mac.type = I40E_MAC_X722;
  85                         break;
  86 #endif
  87 #ifdef X722_SUPPORT
  88 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  89                 case I40E_DEV_ID_X722_VF:
  90                 case I40E_DEV_ID_X722_VF_HV:
  91 #ifdef X722_A0_SUPPORT
  92                 case I40E_DEV_ID_X722_A0_VF:
  93 #endif
  94                         hw->mac.type = I40E_MAC_X722_VF;
  95                         break;
  96 #endif /* INTEGRATED_VF || VF_DRIVER */
  97 #endif /* X722_SUPPORT */
  98 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  99                 case I40E_DEV_ID_VF:
 100                 case I40E_DEV_ID_VF_HV:
 101                         hw->mac.type = I40E_MAC_VF;
 102                         break;
 103 #endif
 104                 default:
 105                         hw->mac.type = I40E_MAC_GENERIC;
 106                         break;
 107                 }
 108         } else {
 109                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 110         }
 111
 112         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 113                   hw->mac.type, status);
 114         return status;
 115 }
 116
 117 #ifndef I40E_NDIS_SUPPORT
 118 /**
 119  * i40e_aq_str - convert AQ err code to a string
 120  * @hw: pointer to the HW structure
 121  * @aq_err: the AQ error code to convert
 122  **/
 123 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 124 {
 125         switch (aq_err) {
 126         case I40E_AQ_RC_OK:
 127                 return "OK";
 128         case I40E_AQ_RC_EPERM:
 129                 return "I40E_AQ_RC_EPERM";
 130         case I40E_AQ_RC_ENOENT:
 131                 return "I40E_AQ_RC_ENOENT";
 132         case I40E_AQ_RC_ESRCH:
 133                 return "I40E_AQ_RC_ESRCH";
 134         case I40E_AQ_RC_EINTR:
 135                 return "I40E_AQ_RC_EINTR";
 136         case I40E_AQ_RC_EIO:
 137                 return "I40E_AQ_RC_EIO";
 138         case I40E_AQ_RC_ENXIO:
 139                 return "I40E_AQ_RC_ENXIO";
 140         case I40E_AQ_RC_E2BIG:
 141                 return "I40E_AQ_RC_E2BIG";
 142         case I40E_AQ_RC_EAGAIN:
 143                 return "I40E_AQ_RC_EAGAIN";
 144         case I40E_AQ_RC_ENOMEM:
 145                 return "I40E_AQ_RC_ENOMEM";
 146         case I40E_AQ_RC_EACCES:
 147                 return "I40E_AQ_RC_EACCES";
 148         case I40E_AQ_RC_EFAULT:
 149                 return "I40E_AQ_RC_EFAULT";
 150         case I40E_AQ_RC_EBUSY:
 151                 return "I40E_AQ_RC_EBUSY";
 152         case I40E_AQ_RC_EEXIST:
 153                 return "I40E_AQ_RC_EEXIST";
 154         case I40E_AQ_RC_EINVAL:
 155                 return "I40E_AQ_RC_EINVAL";
 156         case I40E_AQ_RC_ENOTTY:
 157                 return "I40E_AQ_RC_ENOTTY";
 158         case I40E_AQ_RC_ENOSPC:
 159                 return "I40E_AQ_RC_ENOSPC";
 160         case I40E_AQ_RC_ENOSYS:
 161                 return "I40E_AQ_RC_ENOSYS";
 162         case I40E_AQ_RC_ERANGE:
 163                 return "I40E_AQ_RC_ERANGE";
 164         case I40E_AQ_RC_EFLUSHED:
 165                 return "I40E_AQ_RC_EFLUSHED";
 166         case I40E_AQ_RC_BAD_ADDR:
 167                 return "I40E_AQ_RC_BAD_ADDR";
 168         case I40E_AQ_RC_EMODE:
 169                 return "I40E_AQ_RC_EMODE";
 170         case I40E_AQ_RC_EFBIG:
 171                 return "I40E_AQ_RC_EFBIG";
 172         }
 173
 174         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 175         return hw->err_str;
 176 }
 177
 178 /**
 179  * i40e_stat_str - convert status err code to a string
 180  * @hw: pointer to the HW structure
 181  * @stat_err: the status error code to convert
 182  **/
 183 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 184 {
 185         switch (stat_err) {
 186         case I40E_SUCCESS:
 187                 return "OK";
 188         case I40E_ERR_NVM:
 189                 return "I40E_ERR_NVM";
 190         case I40E_ERR_NVM_CHECKSUM:
 191                 return "I40E_ERR_NVM_CHECKSUM";
 192         case I40E_ERR_PHY:
 193                 return "I40E_ERR_PHY";
 194         case I40E_ERR_CONFIG:
 195                 return "I40E_ERR_CONFIG";
 196         case I40E_ERR_PARAM:
 197                 return "I40E_ERR_PARAM";
 198         case I40E_ERR_MAC_TYPE:
 199                 return "I40E_ERR_MAC_TYPE";
 200         case I40E_ERR_UNKNOWN_PHY:
 201                 return "I40E_ERR_UNKNOWN_PHY";
 202         case I40E_ERR_LINK_SETUP:
 203                 return "I40E_ERR_LINK_SETUP";
 204         case I40E_ERR_ADAPTER_STOPPED:
 205                 return "I40E_ERR_ADAPTER_STOPPED";
 206         case I40E_ERR_INVALID_MAC_ADDR:
 207                 return "I40E_ERR_INVALID_MAC_ADDR";
 208         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 209                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 210         case I40E_ERR_MASTER_REQUESTS_PENDING:
 211                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 212         case I40E_ERR_INVALID_LINK_SETTINGS:
 213                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 214         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 215                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 216         case I40E_ERR_RESET_FAILED:
 217                 return "I40E_ERR_RESET_FAILED";
 218         case I40E_ERR_SWFW_SYNC:
 219                 return "I40E_ERR_SWFW_SYNC";
 220         case I40E_ERR_NO_AVAILABLE_VSI:
 221                 return "I40E_ERR_NO_AVAILABLE_VSI";
 222         case I40E_ERR_NO_MEMORY:
 223                 return "I40E_ERR_NO_MEMORY";
 224         case I40E_ERR_BAD_PTR:
 225                 return "I40E_ERR_BAD_PTR";
 226         case I40E_ERR_RING_FULL:
 227                 return "I40E_ERR_RING_FULL";
 228         case I40E_ERR_INVALID_PD_ID:
 229                 return "I40E_ERR_INVALID_PD_ID";
 230         case I40E_ERR_INVALID_QP_ID:
 231                 return "I40E_ERR_INVALID_QP_ID";
 232         case I40E_ERR_INVALID_CQ_ID:
 233                 return "I40E_ERR_INVALID_CQ_ID";
 234         case I40E_ERR_INVALID_CEQ_ID:
 235                 return "I40E_ERR_INVALID_CEQ_ID";
 236         case I40E_ERR_INVALID_AEQ_ID:
 237                 return "I40E_ERR_INVALID_AEQ_ID";
 238         case I40E_ERR_INVALID_SIZE:
 239                 return "I40E_ERR_INVALID_SIZE";
 240         case I40E_ERR_INVALID_ARP_INDEX:
 241                 return "I40E_ERR_INVALID_ARP_INDEX";
 242         case I40E_ERR_INVALID_FPM_FUNC_ID:
 243                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 244         case I40E_ERR_QP_INVALID_MSG_SIZE:
 245                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 246         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 247                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 248         case I40E_ERR_INVALID_FRAG_COUNT:
 249                 return "I40E_ERR_INVALID_FRAG_COUNT";
 250         case I40E_ERR_QUEUE_EMPTY:
 251                 return "I40E_ERR_QUEUE_EMPTY";
 252         case I40E_ERR_INVALID_ALIGNMENT:
 253                 return "I40E_ERR_INVALID_ALIGNMENT";
 254         case I40E_ERR_FLUSHED_QUEUE:
 255                 return "I40E_ERR_FLUSHED_QUEUE";
 256         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 257                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 258         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 259                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 260         case I40E_ERR_TIMEOUT:
 261                 return "I40E_ERR_TIMEOUT";
 262         case I40E_ERR_OPCODE_MISMATCH:
 263                 return "I40E_ERR_OPCODE_MISMATCH";
 264         case I40E_ERR_CQP_COMPL_ERROR:
 265                 return "I40E_ERR_CQP_COMPL_ERROR";
 266         case I40E_ERR_INVALID_VF_ID:
 267                 return "I40E_ERR_INVALID_VF_ID";
 268         case I40E_ERR_INVALID_HMCFN_ID:
 269                 return "I40E_ERR_INVALID_HMCFN_ID";
 270         case I40E_ERR_BACKING_PAGE_ERROR:
 271                 return "I40E_ERR_BACKING_PAGE_ERROR";
 272         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 273                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 274         case I40E_ERR_INVALID_PBLE_INDEX:
 275                 return "I40E_ERR_INVALID_PBLE_INDEX";
 276         case I40E_ERR_INVALID_SD_INDEX:
 277                 return "I40E_ERR_INVALID_SD_INDEX";
 278         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 279                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 280         case I40E_ERR_INVALID_SD_TYPE:
 281                 return "I40E_ERR_INVALID_SD_TYPE";
 282         case I40E_ERR_MEMCPY_FAILED:
 283                 return "I40E_ERR_MEMCPY_FAILED";
 284         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 285                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 286         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 287                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 288         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 289                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 290         case I40E_ERR_SRQ_ENABLED:
 291                 return "I40E_ERR_SRQ_ENABLED";
 292         case I40E_ERR_ADMIN_QUEUE_ERROR:
 293                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 294         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 295                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 296         case I40E_ERR_BUF_TOO_SHORT:
 297                 return "I40E_ERR_BUF_TOO_SHORT";
 298         case I40E_ERR_ADMIN_QUEUE_FULL:
 299                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 300         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 301                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 302         case I40E_ERR_BAD_IWARP_CQE:
 303                 return "I40E_ERR_BAD_IWARP_CQE";
 304         case I40E_ERR_NVM_BLANK_MODE:
 305                 return "I40E_ERR_NVM_BLANK_MODE";
 306         case I40E_ERR_NOT_IMPLEMENTED:
 307                 return "I40E_ERR_NOT_IMPLEMENTED";
 308         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 309                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 310         case I40E_ERR_DIAG_TEST_FAILED:
 311                 return "I40E_ERR_DIAG_TEST_FAILED";
 312         case I40E_ERR_NOT_READY:
 313                 return "I40E_ERR_NOT_READY";
 314         case I40E_NOT_SUPPORTED:
 315                 return "I40E_NOT_SUPPORTED";
 316         case I40E_ERR_FIRMWARE_API_VERSION:
 317                 return "I40E_ERR_FIRMWARE_API_VERSION";
 318         }
 319
 320         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 321         return hw->err_str;
 322 }
 323
 324 #endif /* I40E_NDIS_SUPPORT */
 325 /**
 326  * i40e_debug_aq
 327  * @hw: debug mask related to admin queue
 328  * @mask: debug mask
 329  * @desc: pointer to admin queue descriptor
 330  * @buffer: pointer to command buffer
 331  * @buf_len: max length of buffer
 332  *
 333  * Dumps debug log about adminq command with descriptor contents.
 334  **/
 335 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 336                    void *buffer, u16 buf_len)
 337 {
 338         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 339         u16 len = LE16_TO_CPU(aq_desc->datalen);
 340         u8 *buf = (u8 *)buffer;
 341         u16 i = 0;
 342
 343         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 344                 return;
 345
 346         i40e_debug(hw, mask,
 347                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 348                    LE16_TO_CPU(aq_desc->opcode),
 349                    LE16_TO_CPU(aq_desc->flags),
 350                    LE16_TO_CPU(aq_desc->datalen),
 351                    LE16_TO_CPU(aq_desc->retval));
 352         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->cookie_high),
 354                    LE32_TO_CPU(aq_desc->cookie_low));
 355         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.internal.param0),
 357                    LE32_TO_CPU(aq_desc->params.internal.param1));
 358         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 359                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 360                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 361
 362         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 363                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 364                 if (buf_len < len)
 365                         len = buf_len;
 366                 /* write the full 16-byte chunks */
 367                 for (i = 0; i < (len - 16); i += 16)
 368                         i40e_debug(hw, mask,
 369                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 370                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 371                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 372                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 373                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 374                 /* the most we could have left is 16 bytes, pad with zeros */
 375                 if (i < len) {
 376                         char d_buf[16];
 377                         int j, i_sav;
 378
 379                         i_sav = i;
 380                         memset(d_buf, 0, sizeof(d_buf));
 381                         for (j = 0; i < len; j++, i++)
 382                                 d_buf[j] = buf[i];
 383                         i40e_debug(hw, mask,
 384                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 385                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 386                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 387                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 388                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 389                 }
 390         }
 391 }
 392
 393 /**
 394  * i40e_check_asq_alive
 395  * @hw: pointer to the hw struct
 396  *
 397  * Returns true if Queue is enabled else false.
 398  **/
 399 bool i40e_check_asq_alive(struct i40e_hw *hw)
 400 {
 401         if (hw->aq.asq.len)
 402 #ifdef PF_DRIVER
 403 #ifdef INTEGRATED_VF
 404                 if (!i40e_is_vf(hw))
 405                         return !!(rd32(hw, hw->aq.asq.len) &
 406                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 407 #else
 408                 return !!(rd32(hw, hw->aq.asq.len) &
 409                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 410 #endif /* INTEGRATED_VF */
 411 #endif /* PF_DRIVER */
 412 #ifdef VF_DRIVER
 413 #ifdef INTEGRATED_VF
 414                 if (i40e_is_vf(hw))
 415                         return !!(rd32(hw, hw->aq.asq.len) &
 416                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 417 #else
 418                 return !!(rd32(hw, hw->aq.asq.len) &
 419                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 420 #endif /* INTEGRATED_VF */
 421 #endif /* VF_DRIVER */
 422         return false;
 423 }
 424
 425 /**
 426  * i40e_aq_queue_shutdown
 427  * @hw: pointer to the hw struct
 428  * @unloading: is the driver unloading itself
 429  *
 430  * Tell the Firmware that we're shutting down the AdminQ and whether
 431  * or not the driver is unloading as well.
 432  **/
 433 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 434                                              bool unloading)
 435 {
 436         struct i40e_aq_desc desc;
 437         struct i40e_aqc_queue_shutdown *cmd =
 438                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 439         enum i40e_status_code status;
 440
 441         i40e_fill_default_direct_cmd_desc(&desc,
 442                                           i40e_aqc_opc_queue_shutdown);
 443
 444         if (unloading)
 445                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 446         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 447
 448         return status;
 449 }
 450 #ifdef X722_SUPPORT
 451
 452 /**
 453  * i40e_aq_get_set_rss_lut
 454  * @hw: pointer to the hardware structure
 455  * @vsi_id: vsi fw index
 456  * @pf_lut: for PF table set true, for VSI table set false
 457  * @lut: pointer to the lut buffer provided by the caller
 458  * @lut_size: size of the lut buffer
 459  * @set: set true to set the table, false to get the table
 460  *
 461  * Internal function to get or set RSS look up table
 462  **/
 463 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 464                                                      u16 vsi_id, bool pf_lut,
 465                                                      u8 *lut, u16 lut_size,
 466                                                      bool set)
 467 {
 468         enum i40e_status_code status;
 469         struct i40e_aq_desc desc;
 470         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 471                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 472
 473         if (set)
 474                 i40e_fill_default_direct_cmd_desc(&desc,
 475                                                   i40e_aqc_opc_set_rss_lut);
 476         else
 477                 i40e_fill_default_direct_cmd_desc(&desc,
 478                                                   i40e_aqc_opc_get_rss_lut);
 479
 480         /* Indirect command */
 481         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 482         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 483
 484         cmd_resp->vsi_id =
 485                         CPU_TO_LE16((u16)((vsi_id <<
 486                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 487                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 488         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 489
 490         if (pf_lut)
 491                 cmd_resp->flags |= CPU_TO_LE16((u16)
 492                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 493                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 495         else
 496                 cmd_resp->flags |= CPU_TO_LE16((u16)
 497                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 498                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 499                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 500
 501         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 502
 503         return status;
 504 }
 505
 506 /**
 507  * i40e_aq_get_rss_lut
 508  * @hw: pointer to the hardware structure
 509  * @vsi_id: vsi fw index
 510  * @pf_lut: for PF table set true, for VSI table set false
 511  * @lut: pointer to the lut buffer provided by the caller
 512  * @lut_size: size of the lut buffer
 513  *
 514  * get the RSS lookup table, PF or VSI type
 515  **/
 516 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 517                                           bool pf_lut, u8 *lut, u16 lut_size)
 518 {
 519         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 520                                        false);
 521 }
 522
 523 /**
 524  * i40e_aq_set_rss_lut
 525  * @hw: pointer to the hardware structure
 526  * @vsi_id: vsi fw index
 527  * @pf_lut: for PF table set true, for VSI table set false
 528  * @lut: pointer to the lut buffer provided by the caller
 529  * @lut_size: size of the lut buffer
 530  *
 531  * set the RSS lookup table, PF or VSI type
 532  **/
 533 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 534                                           bool pf_lut, u8 *lut, u16 lut_size)
 535 {
 536         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 537 }
 538
 539 /**
 540  * i40e_aq_get_set_rss_key
 541  * @hw: pointer to the hw struct
 542  * @vsi_id: vsi fw index
 543  * @key: pointer to key info struct
 544  * @set: set true to set the key, false to get the key
 545  *
 546  * get the RSS key per VSI
 547  **/
 548 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 549                                       u16 vsi_id,
 550                                       struct i40e_aqc_get_set_rss_key_data *key,
 551                                       bool set)
 552 {
 553         enum i40e_status_code status;
 554         struct i40e_aq_desc desc;
 555         struct i40e_aqc_get_set_rss_key *cmd_resp =
 556                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 557         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 558
 559         if (set)
 560                 i40e_fill_default_direct_cmd_desc(&desc,
 561                                                   i40e_aqc_opc_set_rss_key);
 562         else
 563                 i40e_fill_default_direct_cmd_desc(&desc,
 564                                                   i40e_aqc_opc_get_rss_key);
 565
 566         /* Indirect command */
 567         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 568         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 569
 570         cmd_resp->vsi_id =
 571                         CPU_TO_LE16((u16)((vsi_id <<
 572                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 573                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 574         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 575
 576         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 577
 578         return status;
 579 }
 580
 581 /**
 582  * i40e_aq_get_rss_key
 583  * @hw: pointer to the hw struct
 584  * @vsi_id: vsi fw index
 585  * @key: pointer to key info struct
 586  *
 587  **/
 588 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 589                                       u16 vsi_id,
 590                                       struct i40e_aqc_get_set_rss_key_data *key)
 591 {
 592         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 593 }
 594
 595 /**
 596  * i40e_aq_set_rss_key
 597  * @hw: pointer to the hw struct
 598  * @vsi_id: vsi fw index
 599  * @key: pointer to key info struct
 600  *
 601  * set the RSS key per VSI
 602  **/
 603 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 604                                       u16 vsi_id,
 605                                       struct i40e_aqc_get_set_rss_key_data *key)
 606 {
 607         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 608 }
 609 #endif /* X722_SUPPORT */
 610
 611 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 612  * hardware to a bit-field that can be used by SW to more easily determine the
 613  * packet type.
 614  *
 615  * Macros are used to shorten the table lines and make this table human
 616  * readable.
 617  *
 618  * We store the PTYPE in the top byte of the bit field - this is just so that
 619  * we can check that the table doesn't have a row missing, as the index into
 620  * the table should be the PTYPE.
 621  *
 622  * Typical work flow:
 623  *
 624  * IF NOT i40e_ptype_lookup[ptype].known
 625  * THEN
 626  *      Packet is unknown
 627  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 628  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 629  * ELSE
 630  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 631  * ENDIF
 632  */
 633
 634 /* macro to make the table lines short */
 635 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 636         {       PTYPE, \
 637                 1, \
 638                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 639                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 640                 I40E_RX_PTYPE_##OUTER_FRAG, \
 641                 I40E_RX_PTYPE_TUNNEL_##T, \
 642                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 643                 I40E_RX_PTYPE_##TEF, \
 644                 I40E_RX_PTYPE_INNER_PROT_##I, \
 645                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 646
 647 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 648                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 649
 650 /* shorter macros makes the table fit but are terse */
 651 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 652 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 653 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 654
 655 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 656 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 657         /* L2 Packet types */
 658         I40E_PTT_UNUSED_ENTRY(0),
 659         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 660         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 661         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(4),
 663         I40E_PTT_UNUSED_ENTRY(5),
 664         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 666         I40E_PTT_UNUSED_ENTRY(8),
 667         I40E_PTT_UNUSED_ENTRY(9),
 668         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 669         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 670         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 677         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 678         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 680
 681         /* Non Tunneled IPv4 */
 682         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 683         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 684         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 685         I40E_PTT_UNUSED_ENTRY(25),
 686         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 687         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 688         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 689
 690         /* IPv4 --> IPv4 */
 691         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 692         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 693         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 694         I40E_PTT_UNUSED_ENTRY(32),
 695         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 696         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 697         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 698
 699         /* IPv4 --> IPv6 */
 700         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 701         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 702         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 703         I40E_PTT_UNUSED_ENTRY(39),
 704         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 705         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 706         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 707
 708         /* IPv4 --> GRE/NAT */
 709         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 710
 711         /* IPv4 --> GRE/NAT --> IPv4 */
 712         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 713         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 714         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 715         I40E_PTT_UNUSED_ENTRY(47),
 716         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 717         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 718         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 719
 720         /* IPv4 --> GRE/NAT --> IPv6 */
 721         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 722         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 723         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 724         I40E_PTT_UNUSED_ENTRY(54),
 725         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 726         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 727         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 728
 729         /* IPv4 --> GRE/NAT --> MAC */
 730         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 731
 732         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 733         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 734         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 735         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 736         I40E_PTT_UNUSED_ENTRY(62),
 737         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 738         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 739         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 740
 741         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 742         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 743         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 744         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 745         I40E_PTT_UNUSED_ENTRY(69),
 746         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 747         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 748         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 749
 750         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 751         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 752
 753         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 754         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 755         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 756         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 757         I40E_PTT_UNUSED_ENTRY(77),
 758         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 759         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 760         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 761
 762         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 763         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 764         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 765         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 766         I40E_PTT_UNUSED_ENTRY(84),
 767         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 768         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 769         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 770
 771         /* Non Tunneled IPv6 */
 772         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 773         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 774         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 775         I40E_PTT_UNUSED_ENTRY(91),
 776         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 777         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 778         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 779
 780         /* IPv6 --> IPv4 */
 781         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 782         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 783         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 784         I40E_PTT_UNUSED_ENTRY(98),
 785         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 786         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 787         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 788
 789         /* IPv6 --> IPv6 */
 790         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 791         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 792         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 793         I40E_PTT_UNUSED_ENTRY(105),
 794         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 795         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 796         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 797
 798         /* IPv6 --> GRE/NAT */
 799         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 800
 801         /* IPv6 --> GRE/NAT -> IPv4 */
 802         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 803         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 804         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 805         I40E_PTT_UNUSED_ENTRY(113),
 806         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 807         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 808         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 809
 810         /* IPv6 --> GRE/NAT -> IPv6 */
 811         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 812         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 813         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 814         I40E_PTT_UNUSED_ENTRY(120),
 815         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 816         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 817         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 818
 819         /* IPv6 --> GRE/NAT -> MAC */
 820         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 821
 822         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 823         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 824         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 825         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 826         I40E_PTT_UNUSED_ENTRY(128),
 827         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 828         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 829         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 830
 831         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 832         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 833         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 834         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 835         I40E_PTT_UNUSED_ENTRY(135),
 836         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 837         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 838         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 839
 840         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 841         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 842
 843         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 844         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 845         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 846         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 847         I40E_PTT_UNUSED_ENTRY(143),
 848         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 849         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 850         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 851
 852         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 853         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 854         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 855         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 856         I40E_PTT_UNUSED_ENTRY(150),
 857         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 858         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 859         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 860
 861         /* unused entries */
 862         I40E_PTT_UNUSED_ENTRY(154),
 863         I40E_PTT_UNUSED_ENTRY(155),
 864         I40E_PTT_UNUSED_ENTRY(156),
 865         I40E_PTT_UNUSED_ENTRY(157),
 866         I40E_PTT_UNUSED_ENTRY(158),
 867         I40E_PTT_UNUSED_ENTRY(159),
 868
 869         I40E_PTT_UNUSED_ENTRY(160),
 870         I40E_PTT_UNUSED_ENTRY(161),
 871         I40E_PTT_UNUSED_ENTRY(162),
 872         I40E_PTT_UNUSED_ENTRY(163),
 873         I40E_PTT_UNUSED_ENTRY(164),
 874         I40E_PTT_UNUSED_ENTRY(165),
 875         I40E_PTT_UNUSED_ENTRY(166),
 876         I40E_PTT_UNUSED_ENTRY(167),
 877         I40E_PTT_UNUSED_ENTRY(168),
 878         I40E_PTT_UNUSED_ENTRY(169),
 879
 880         I40E_PTT_UNUSED_ENTRY(170),
 881         I40E_PTT_UNUSED_ENTRY(171),
 882         I40E_PTT_UNUSED_ENTRY(172),
 883         I40E_PTT_UNUSED_ENTRY(173),
 884         I40E_PTT_UNUSED_ENTRY(174),
 885         I40E_PTT_UNUSED_ENTRY(175),
 886         I40E_PTT_UNUSED_ENTRY(176),
 887         I40E_PTT_UNUSED_ENTRY(177),
 888         I40E_PTT_UNUSED_ENTRY(178),
 889         I40E_PTT_UNUSED_ENTRY(179),
 890
 891         I40E_PTT_UNUSED_ENTRY(180),
 892         I40E_PTT_UNUSED_ENTRY(181),
 893         I40E_PTT_UNUSED_ENTRY(182),
 894         I40E_PTT_UNUSED_ENTRY(183),
 895         I40E_PTT_UNUSED_ENTRY(184),
 896         I40E_PTT_UNUSED_ENTRY(185),
 897         I40E_PTT_UNUSED_ENTRY(186),
 898         I40E_PTT_UNUSED_ENTRY(187),
 899         I40E_PTT_UNUSED_ENTRY(188),
 900         I40E_PTT_UNUSED_ENTRY(189),
 901
 902         I40E_PTT_UNUSED_ENTRY(190),
 903         I40E_PTT_UNUSED_ENTRY(191),
 904         I40E_PTT_UNUSED_ENTRY(192),
 905         I40E_PTT_UNUSED_ENTRY(193),
 906         I40E_PTT_UNUSED_ENTRY(194),
 907         I40E_PTT_UNUSED_ENTRY(195),
 908         I40E_PTT_UNUSED_ENTRY(196),
 909         I40E_PTT_UNUSED_ENTRY(197),
 910         I40E_PTT_UNUSED_ENTRY(198),
 911         I40E_PTT_UNUSED_ENTRY(199),
 912
 913         I40E_PTT_UNUSED_ENTRY(200),
 914         I40E_PTT_UNUSED_ENTRY(201),
 915         I40E_PTT_UNUSED_ENTRY(202),
 916         I40E_PTT_UNUSED_ENTRY(203),
 917         I40E_PTT_UNUSED_ENTRY(204),
 918         I40E_PTT_UNUSED_ENTRY(205),
 919         I40E_PTT_UNUSED_ENTRY(206),
 920         I40E_PTT_UNUSED_ENTRY(207),
 921         I40E_PTT_UNUSED_ENTRY(208),
 922         I40E_PTT_UNUSED_ENTRY(209),
 923
 924         I40E_PTT_UNUSED_ENTRY(210),
 925         I40E_PTT_UNUSED_ENTRY(211),
 926         I40E_PTT_UNUSED_ENTRY(212),
 927         I40E_PTT_UNUSED_ENTRY(213),
 928         I40E_PTT_UNUSED_ENTRY(214),
 929         I40E_PTT_UNUSED_ENTRY(215),
 930         I40E_PTT_UNUSED_ENTRY(216),
 931         I40E_PTT_UNUSED_ENTRY(217),
 932         I40E_PTT_UNUSED_ENTRY(218),
 933         I40E_PTT_UNUSED_ENTRY(219),
 934
 935         I40E_PTT_UNUSED_ENTRY(220),
 936         I40E_PTT_UNUSED_ENTRY(221),
 937         I40E_PTT_UNUSED_ENTRY(222),
 938         I40E_PTT_UNUSED_ENTRY(223),
 939         I40E_PTT_UNUSED_ENTRY(224),
 940         I40E_PTT_UNUSED_ENTRY(225),
 941         I40E_PTT_UNUSED_ENTRY(226),
 942         I40E_PTT_UNUSED_ENTRY(227),
 943         I40E_PTT_UNUSED_ENTRY(228),
 944         I40E_PTT_UNUSED_ENTRY(229),
 945
 946         I40E_PTT_UNUSED_ENTRY(230),
 947         I40E_PTT_UNUSED_ENTRY(231),
 948         I40E_PTT_UNUSED_ENTRY(232),
 949         I40E_PTT_UNUSED_ENTRY(233),
 950         I40E_PTT_UNUSED_ENTRY(234),
 951         I40E_PTT_UNUSED_ENTRY(235),
 952         I40E_PTT_UNUSED_ENTRY(236),
 953         I40E_PTT_UNUSED_ENTRY(237),
 954         I40E_PTT_UNUSED_ENTRY(238),
 955         I40E_PTT_UNUSED_ENTRY(239),
 956
 957         I40E_PTT_UNUSED_ENTRY(240),
 958         I40E_PTT_UNUSED_ENTRY(241),
 959         I40E_PTT_UNUSED_ENTRY(242),
 960         I40E_PTT_UNUSED_ENTRY(243),
 961         I40E_PTT_UNUSED_ENTRY(244),
 962         I40E_PTT_UNUSED_ENTRY(245),
 963         I40E_PTT_UNUSED_ENTRY(246),
 964         I40E_PTT_UNUSED_ENTRY(247),
 965         I40E_PTT_UNUSED_ENTRY(248),
 966         I40E_PTT_UNUSED_ENTRY(249),
 967
 968         I40E_PTT_UNUSED_ENTRY(250),
 969         I40E_PTT_UNUSED_ENTRY(251),
 970         I40E_PTT_UNUSED_ENTRY(252),
 971         I40E_PTT_UNUSED_ENTRY(253),
 972         I40E_PTT_UNUSED_ENTRY(254),
 973         I40E_PTT_UNUSED_ENTRY(255)
 974 };
 975
 976
 977 /**
 978  * i40e_validate_mac_addr - Validate unicast MAC address
 979  * @mac_addr: pointer to MAC address
 980  *
 981  * Tests a MAC address to ensure it is a valid Individual Address
 982  **/
 983 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 984 {
 985         enum i40e_status_code status = I40E_SUCCESS;
 986
 987         DEBUGFUNC("i40e_validate_mac_addr");
 988
 989         /* Broadcast addresses ARE multicast addresses
 990          * Make sure it is not a multicast address
 991          * Reject the zero address
 992          */
 993         if (I40E_IS_MULTICAST(mac_addr) ||
 994             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 995               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 996                 status = I40E_ERR_INVALID_MAC_ADDR;
 997
 998         return status;
 999 }
1000 #ifdef PF_DRIVER
1001
1002 /**
1003  * i40e_init_shared_code - Initialize the shared code
1004  * @hw: pointer to hardware structure
1005  *
1006  * This assigns the MAC type and PHY code and inits the NVM.
1007  * Does not touch the hardware. This function must be called prior to any
1008  * other function in the shared code. The i40e_hw structure should be
1009  * memset to 0 prior to calling this function.  The following fields in
1010  * hw structure should be filled in prior to calling this function:
1011  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1012  * subsystem_vendor_id, and revision_id
1013  **/
1014 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1015 {
1016         enum i40e_status_code status = I40E_SUCCESS;
1017         u32 port, ari, func_rid;
1018
1019         DEBUGFUNC("i40e_init_shared_code");
1020
1021         i40e_set_mac_type(hw);
1022
1023         switch (hw->mac.type) {
1024         case I40E_MAC_XL710:
1025 #ifdef X722_SUPPORT
1026         case I40E_MAC_X722:
1027 #endif
1028                 break;
1029         default:
1030                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1031         }
1032
1033         hw->phy.get_link_info = true;
1034
1035         /* Determine port number and PF number*/
1036         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1037                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1038         hw->port = (u8)port;
1039         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1040                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1041         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1042         if (ari)
1043                 hw->pf_id = (u8)(func_rid & 0xff);
1044         else
1045                 hw->pf_id = (u8)(func_rid & 0x7);
1046
1047 #ifdef X722_SUPPORT
1048         if (hw->mac.type == I40E_MAC_X722)
1049                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1050                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1051
1052 #endif
1053         status = i40e_init_nvm(hw);
1054         return status;
1055 }
1056
1057 /**
1058  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1059  * @hw: pointer to the hw struct
1060  * @flags: a return indicator of what addresses were added to the addr store
1061  * @addrs: the requestor's mac addr store
1062  * @cmd_details: pointer to command details structure or NULL
1063  **/
1064 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1065                                    u16 *flags,
1066                                    struct i40e_aqc_mac_address_read_data *addrs,
1067                                    struct i40e_asq_cmd_details *cmd_details)
1068 {
1069         struct i40e_aq_desc desc;
1070         struct i40e_aqc_mac_address_read *cmd_data =
1071                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1072         enum i40e_status_code status;
1073
1074         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1075         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1076
1077         status = i40e_asq_send_command(hw, &desc, addrs,
1078                                        sizeof(*addrs), cmd_details);
1079         *flags = LE16_TO_CPU(cmd_data->command_flags);
1080
1081         return status;
1082 }
1083
1084 /**
1085  * i40e_aq_mac_address_write - Change the MAC addresses
1086  * @hw: pointer to the hw struct
1087  * @flags: indicates which MAC to be written
1088  * @mac_addr: address to write
1089  * @cmd_details: pointer to command details structure or NULL
1090  **/
1091 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1092                                     u16 flags, u8 *mac_addr,
1093                                     struct i40e_asq_cmd_details *cmd_details)
1094 {
1095         struct i40e_aq_desc desc;
1096         struct i40e_aqc_mac_address_write *cmd_data =
1097                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1098         enum i40e_status_code status;
1099
1100         i40e_fill_default_direct_cmd_desc(&desc,
1101                                           i40e_aqc_opc_mac_address_write);
1102         cmd_data->command_flags = CPU_TO_LE16(flags);
1103         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1104         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1105                                         ((u32)mac_addr[3] << 16) |
1106                                         ((u32)mac_addr[4] << 8) |
1107                                         mac_addr[5]);
1108
1109         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1110
1111         return status;
1112 }
1113
1114 /**
1115  * i40e_get_mac_addr - get MAC address
1116  * @hw: pointer to the HW structure
1117  * @mac_addr: pointer to MAC address
1118  *
1119  * Reads the adapter's MAC address from register
1120  **/
1121 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1122 {
1123         struct i40e_aqc_mac_address_read_data addrs;
1124         enum i40e_status_code status;
1125         u16 flags = 0;
1126
1127         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1128
1129         if (flags & I40E_AQC_LAN_ADDR_VALID)
1130                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1131
1132         return status;
1133 }
1134
1135 /**
1136  * i40e_get_port_mac_addr - get Port MAC address
1137  * @hw: pointer to the HW structure
1138  * @mac_addr: pointer to Port MAC address
1139  *
1140  * Reads the adapter's Port MAC address
1141  **/
1142 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1143 {
1144         struct i40e_aqc_mac_address_read_data addrs;
1145         enum i40e_status_code status;
1146         u16 flags = 0;
1147
1148         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1149         if (status)
1150                 return status;
1151
1152         if (flags & I40E_AQC_PORT_ADDR_VALID)
1153                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1154         else
1155                 status = I40E_ERR_INVALID_MAC_ADDR;
1156
1157         return status;
1158 }
1159
1160 /**
1161  * i40e_pre_tx_queue_cfg - pre tx queue configure
1162  * @hw: pointer to the HW structure
1163  * @queue: target pf queue index
1164  * @enable: state change request
1165  *
1166  * Handles hw requirement to indicate intention to enable
1167  * or disable target queue.
1168  **/
1169 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1170 {
1171         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1172         u32 reg_block = 0;
1173         u32 reg_val;
1174
1175         if (abs_queue_idx >= 128) {
1176                 reg_block = abs_queue_idx / 128;
1177                 abs_queue_idx %= 128;
1178         }
1179
1180         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1181         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1182         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1183
1184         if (enable)
1185                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1186         else
1187                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1188
1189         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1190 }
1191
1192 /**
1193  * i40e_get_san_mac_addr - get SAN MAC address
1194  * @hw: pointer to the HW structure
1195  * @mac_addr: pointer to SAN MAC address
1196  *
1197  * Reads the adapter's SAN MAC address from NVM
1198  **/
1199 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1200                                             u8 *mac_addr)
1201 {
1202         struct i40e_aqc_mac_address_read_data addrs;
1203         enum i40e_status_code status;
1204         u16 flags = 0;
1205
1206         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1207         if (status)
1208                 return status;
1209
1210         if (flags & I40E_AQC_SAN_ADDR_VALID)
1211                 memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac));
1212         else
1213                 status = I40E_ERR_INVALID_MAC_ADDR;
1214
1215         return status;
1216 }
1217
1218 /**
1219  *  i40e_read_pba_string - Reads part number string from EEPROM
1220  *  @hw: pointer to hardware structure
1221  *  @pba_num: stores the part number string from the EEPROM
1222  *  @pba_num_size: part number string buffer length
1223  *
1224  *  Reads the part number string from the EEPROM.
1225  **/
1226 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1227                                             u32 pba_num_size)
1228 {
1229         enum i40e_status_code status = I40E_SUCCESS;
1230         u16 pba_word = 0;
1231         u16 pba_size = 0;
1232         u16 pba_ptr = 0;
1233         u16 i = 0;
1234
1235         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1236         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1237                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1238                 return status;
1239         }
1240
1241         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1242         if (status != I40E_SUCCESS) {
1243                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1244                 return status;
1245         }
1246
1247         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1248         if (status != I40E_SUCCESS) {
1249                 DEBUGOUT("Failed to read PBA Block size.\n");
1250                 return status;
1251         }
1252
1253         /* Subtract one to get PBA word count (PBA Size word is included in
1254          * total size)
1255          */
1256         pba_size--;
1257         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1258                 DEBUGOUT("Buffer to small for PBA data.\n");
1259                 return I40E_ERR_PARAM;
1260         }
1261
1262         for (i = 0; i < pba_size; i++) {
1263                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1264                 if (status != I40E_SUCCESS) {
1265                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1266                         return status;
1267                 }
1268
1269                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1270                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1271         }
1272         pba_num[(pba_size * 2)] = '\0';
1273
1274         return status;
1275 }
1276
1277 /**
1278  * i40e_get_media_type - Gets media type
1279  * @hw: pointer to the hardware structure
1280  **/
1281 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1282 {
1283         enum i40e_media_type media;
1284
1285         switch (hw->phy.link_info.phy_type) {
1286         case I40E_PHY_TYPE_10GBASE_SR:
1287         case I40E_PHY_TYPE_10GBASE_LR:
1288         case I40E_PHY_TYPE_1000BASE_SX:
1289         case I40E_PHY_TYPE_1000BASE_LX:
1290         case I40E_PHY_TYPE_40GBASE_SR4:
1291         case I40E_PHY_TYPE_40GBASE_LR4:
1292                 media = I40E_MEDIA_TYPE_FIBER;
1293                 break;
1294         case I40E_PHY_TYPE_100BASE_TX:
1295         case I40E_PHY_TYPE_1000BASE_T:
1296         case I40E_PHY_TYPE_10GBASE_T:
1297                 media = I40E_MEDIA_TYPE_BASET;
1298                 break;
1299         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1300         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1301         case I40E_PHY_TYPE_10GBASE_CR1:
1302         case I40E_PHY_TYPE_40GBASE_CR4:
1303         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1304         case I40E_PHY_TYPE_40GBASE_AOC:
1305         case I40E_PHY_TYPE_10GBASE_AOC:
1306                 media = I40E_MEDIA_TYPE_DA;
1307                 break;
1308         case I40E_PHY_TYPE_1000BASE_KX:
1309         case I40E_PHY_TYPE_10GBASE_KX4:
1310         case I40E_PHY_TYPE_10GBASE_KR:
1311         case I40E_PHY_TYPE_40GBASE_KR4:
1312         case I40E_PHY_TYPE_20GBASE_KR2:
1313                 media = I40E_MEDIA_TYPE_BACKPLANE;
1314                 break;
1315         case I40E_PHY_TYPE_SGMII:
1316         case I40E_PHY_TYPE_XAUI:
1317         case I40E_PHY_TYPE_XFI:
1318         case I40E_PHY_TYPE_XLAUI:
1319         case I40E_PHY_TYPE_XLPPI:
1320         default:
1321                 media = I40E_MEDIA_TYPE_UNKNOWN;
1322                 break;
1323         }
1324
1325         return media;
1326 }
1327
1328 #define I40E_PF_RESET_WAIT_COUNT        200
1329 /**
1330  * i40e_pf_reset - Reset the PF
1331  * @hw: pointer to the hardware structure
1332  *
1333  * Assuming someone else has triggered a global reset,
1334  * assure the global reset is complete and then reset the PF
1335  **/
1336 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1337 {
1338         u32 cnt = 0;
1339         u32 cnt1 = 0;
1340         u32 reg = 0;
1341         u32 grst_del;
1342
1343         /* Poll for Global Reset steady state in case of recent GRST.
1344          * The grst delay value is in 100ms units, and we'll wait a
1345          * couple counts longer to be sure we don't just miss the end.
1346          */
1347         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1348                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1349                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1350
1351         grst_del = min(grst_del * 20, 160U);
1352
1353         for (cnt = 0; cnt < grst_del; cnt++) {
1354                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1355                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1356                         break;
1357                 i40e_msec_delay(100);
1358         }
1359         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1360                 DEBUGOUT("Global reset polling failed to complete.\n");
1361                 return I40E_ERR_RESET_FAILED;
1362         }
1363
1364         /* Now Wait for the FW to be ready */
1365         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1366                 reg = rd32(hw, I40E_GLNVM_ULD);
1367                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1368                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1369                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1370                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1371                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1372                         break;
1373                 }
1374                 i40e_msec_delay(10);
1375         }
1376         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1377                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1378                 DEBUGOUT("wait for FW Reset complete timedout\n");
1379                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1380                 return I40E_ERR_RESET_FAILED;
1381         }
1382
1383         /* If there was a Global Reset in progress when we got here,
1384          * we don't need to do the PF Reset
1385          */
1386         if (!cnt) {
1387                 reg = rd32(hw, I40E_PFGEN_CTRL);
1388                 wr32(hw, I40E_PFGEN_CTRL,
1389                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1390                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1391                         reg = rd32(hw, I40E_PFGEN_CTRL);
1392                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1393                                 break;
1394                         i40e_msec_delay(1);
1395                 }
1396                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1397                         DEBUGOUT("PF reset polling failed to complete.\n");
1398                         return I40E_ERR_RESET_FAILED;
1399                 }
1400         }
1401
1402         i40e_clear_pxe_mode(hw);
1403
1404
1405         return I40E_SUCCESS;
1406 }
1407
1408 /**
1409  * i40e_clear_hw - clear out any left over hw state
1410  * @hw: pointer to the hw struct
1411  *
1412  * Clear queues and interrupts, typically called at init time,
1413  * but after the capabilities have been found so we know how many
1414  * queues and msix vectors have been allocated.
1415  **/
1416 void i40e_clear_hw(struct i40e_hw *hw)
1417 {
1418         u32 num_queues, base_queue;
1419         u32 num_pf_int;
1420         u32 num_vf_int;
1421         u32 num_vfs;
1422         u32 i, j;
1423         u32 val;
1424         u32 eol = 0x7ff;
1425
1426         /* get number of interrupts, queues, and vfs */
1427         val = rd32(hw, I40E_GLPCI_CNF2);
1428         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1429                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1430         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1431                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1432
1433         val = rd32(hw, I40E_PFLAN_QALLOC);
1434         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1435                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1436         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1437                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1438         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1439                 num_queues = (j - base_queue) + 1;
1440         else
1441                 num_queues = 0;
1442
1443         val = rd32(hw, I40E_PF_VT_PFALLOC);
1444         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1445                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1446         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1447                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1448         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1449                 num_vfs = (j - i) + 1;
1450         else
1451                 num_vfs = 0;
1452
1453         /* stop all the interrupts */
1454         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1455         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1456         for (i = 0; i < num_pf_int - 2; i++)
1457                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1458
1459         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1460         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1461         wr32(hw, I40E_PFINT_LNKLST0, val);
1462         for (i = 0; i < num_pf_int - 2; i++)
1463                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1464         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1465         for (i = 0; i < num_vfs; i++)
1466                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1467         for (i = 0; i < num_vf_int - 2; i++)
1468                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1469
1470         /* warn the HW of the coming Tx disables */
1471         for (i = 0; i < num_queues; i++) {
1472                 u32 abs_queue_idx = base_queue + i;
1473                 u32 reg_block = 0;
1474
1475                 if (abs_queue_idx >= 128) {
1476                         reg_block = abs_queue_idx / 128;
1477                         abs_queue_idx %= 128;
1478                 }
1479
1480                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1481                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1482                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1483                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1484
1485                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1486         }
1487         i40e_usec_delay(400);
1488
1489         /* stop all the queues */
1490         for (i = 0; i < num_queues; i++) {
1491                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1492                 wr32(hw, I40E_QTX_ENA(i), 0);
1493                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1494                 wr32(hw, I40E_QRX_ENA(i), 0);
1495         }
1496
1497         /* short wait for all queue disables to settle */
1498         i40e_usec_delay(50);
1499 }
1500
1501 /**
1502  * i40e_clear_pxe_mode - clear pxe operations mode
1503  * @hw: pointer to the hw struct
1504  *
1505  * Make sure all PXE mode settings are cleared, including things
1506  * like descriptor fetch/write-back mode.
1507  **/
1508 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1509 {
1510         if (i40e_check_asq_alive(hw))
1511                 i40e_aq_clear_pxe_mode(hw, NULL);
1512 }
1513
1514 /**
1515  * i40e_led_is_mine - helper to find matching led
1516  * @hw: pointer to the hw struct
1517  * @idx: index into GPIO registers
1518  *
1519  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1520  */
1521 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1522 {
1523         u32 gpio_val = 0;
1524         u32 port;
1525
1526         if (!hw->func_caps.led[idx])
1527                 return 0;
1528
1529         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1530         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1531                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1532
1533         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1534          * if it is not our port then ignore
1535          */
1536         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1537             (port != hw->port))
1538                 return 0;
1539
1540         return gpio_val;
1541 }
1542
1543 #define I40E_COMBINED_ACTIVITY 0xA
1544 #define I40E_FILTER_ACTIVITY 0xE
1545 #define I40E_LINK_ACTIVITY 0xC
1546 #define I40E_MAC_ACTIVITY 0xD
1547 #define I40E_LED0 22
1548
1549 /**
1550  * i40e_led_get - return current on/off mode
1551  * @hw: pointer to the hw struct
1552  *
1553  * The value returned is the 'mode' field as defined in the
1554  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1555  * values are variations of possible behaviors relating to
1556  * blink, link, and wire.
1557  **/
1558 u32 i40e_led_get(struct i40e_hw *hw)
1559 {
1560         u32 current_mode = 0;
1561         u32 mode = 0;
1562         int i;
1563
1564         /* as per the documentation GPIO 22-29 are the LED
1565          * GPIO pins named LED0..LED7
1566          */
1567         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1568                 u32 gpio_val = i40e_led_is_mine(hw, i);
1569
1570                 if (!gpio_val)
1571                         continue;
1572
1573                 /* ignore gpio LED src mode entries related to the activity
1574                  *  LEDs
1575                  */
1576                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1577                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1578                 switch (current_mode) {
1579                 case I40E_COMBINED_ACTIVITY:
1580                 case I40E_FILTER_ACTIVITY:
1581                 case I40E_MAC_ACTIVITY:
1582                 case I40E_LINK_ACTIVITY:
1583                         continue;
1584                 default:
1585                         break;
1586                 }
1587
1588                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1589                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1590                 break;
1591         }
1592
1593         return mode;
1594 }
1595
1596 /**
1597  * i40e_led_set - set new on/off mode
1598  * @hw: pointer to the hw struct
1599  * @mode: 0=off, 0xf=on (else see manual for mode details)
1600  * @blink: true if the LED should blink when on, false if steady
1601  *
1602  * if this function is used to turn on the blink it should
1603  * be used to disable the blink when restoring the original state.
1604  **/
1605 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1606 {
1607         u32 current_mode = 0;
1608         int i;
1609
1610         if (mode & 0xfffffff0)
1611                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1612
1613         /* as per the documentation GPIO 22-29 are the LED
1614          * GPIO pins named LED0..LED7
1615          */
1616         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1617                 u32 gpio_val = i40e_led_is_mine(hw, i);
1618
1619                 if (!gpio_val)
1620                         continue;
1621
1622                 /* ignore gpio LED src mode entries related to the activity
1623                  * LEDs
1624                  */
1625                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1626                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1627                 switch (current_mode) {
1628                 case I40E_COMBINED_ACTIVITY:
1629                 case I40E_FILTER_ACTIVITY:
1630                 case I40E_MAC_ACTIVITY:
1631                 case I40E_LINK_ACTIVITY:
1632                         continue;
1633                 default:
1634                         break;
1635                 }
1636
1637                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1638                 /* this & is a bit of paranoia, but serves as a range check */
1639                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1640                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1641
1642                 if (blink)
1643                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1644                 else
1645                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1646
1647                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1648                 break;
1649         }
1650 }
1651
1652 /* Admin command wrappers */
1653
1654 /**
1655  * i40e_aq_get_phy_capabilities
1656  * @hw: pointer to the hw struct
1657  * @abilities: structure for PHY capabilities to be filled
1658  * @qualified_modules: report Qualified Modules
1659  * @report_init: report init capabilities (active are default)
1660  * @cmd_details: pointer to command details structure or NULL
1661  *
1662  * Returns the various PHY abilities supported on the Port.
1663  **/
1664 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1665                         bool qualified_modules, bool report_init,
1666                         struct i40e_aq_get_phy_abilities_resp *abilities,
1667                         struct i40e_asq_cmd_details *cmd_details)
1668 {
1669         struct i40e_aq_desc desc;
1670         enum i40e_status_code status;
1671         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1672
1673         if (!abilities)
1674                 return I40E_ERR_PARAM;
1675
1676         i40e_fill_default_direct_cmd_desc(&desc,
1677                                           i40e_aqc_opc_get_phy_abilities);
1678
1679         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1680         if (abilities_size > I40E_AQ_LARGE_BUF)
1681                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1682
1683         if (qualified_modules)
1684                 desc.params.external.param0 |=
1685                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1686
1687         if (report_init)
1688                 desc.params.external.param0 |=
1689                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1690
1691         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1692                                     cmd_details);
1693
1694         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1695                 status = I40E_ERR_UNKNOWN_PHY;
1696
1697         if (report_init) {
1698                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1699                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1700         }
1701
1702         return status;
1703 }
1704
1705 /**
1706  * i40e_aq_set_phy_config
1707  * @hw: pointer to the hw struct
1708  * @config: structure with PHY configuration to be set
1709  * @cmd_details: pointer to command details structure or NULL
1710  *
1711  * Set the various PHY configuration parameters
1712  * supported on the Port.One or more of the Set PHY config parameters may be
1713  * ignored in an MFP mode as the PF may not have the privilege to set some
1714  * of the PHY Config parameters. This status will be indicated by the
1715  * command response.
1716  **/
1717 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1718                                 struct i40e_aq_set_phy_config *config,
1719                                 struct i40e_asq_cmd_details *cmd_details)
1720 {
1721         struct i40e_aq_desc desc;
1722         struct i40e_aq_set_phy_config *cmd =
1723                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1724         enum i40e_status_code status;
1725
1726         if (!config)
1727                 return I40E_ERR_PARAM;
1728
1729         i40e_fill_default_direct_cmd_desc(&desc,
1730                                           i40e_aqc_opc_set_phy_config);
1731
1732         *cmd = *config;
1733
1734         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1735
1736         return status;
1737 }
1738
1739 /**
1740  * i40e_set_fc
1741  * @hw: pointer to the hw struct
1742  *
1743  * Set the requested flow control mode using set_phy_config.
1744  **/
1745 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1746                                   bool atomic_restart)
1747 {
1748         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1749         struct i40e_aq_get_phy_abilities_resp abilities;
1750         struct i40e_aq_set_phy_config config;
1751         enum i40e_status_code status;
1752         u8 pause_mask = 0x0;
1753
1754         *aq_failures = 0x0;
1755
1756         switch (fc_mode) {
1757         case I40E_FC_FULL:
1758                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1759                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1760                 break;
1761         case I40E_FC_RX_PAUSE:
1762                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1763                 break;
1764         case I40E_FC_TX_PAUSE:
1765                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1766                 break;
1767         default:
1768                 break;
1769         }
1770
1771         /* Get the current phy config */
1772         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1773                                               NULL);
1774         if (status) {
1775                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1776                 return status;
1777         }
1778
1779         memset(&config, 0, sizeof(config));
1780         /* clear the old pause settings */
1781         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1782                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1783         /* set the new abilities */
1784         config.abilities |= pause_mask;
1785         /* If the abilities have changed, then set the new config */
1786         if (config.abilities != abilities.abilities) {
1787                 /* Auto restart link so settings take effect */
1788                 if (atomic_restart)
1789                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1790                 /* Copy over all the old settings */
1791                 config.phy_type = abilities.phy_type;
1792                 config.link_speed = abilities.link_speed;
1793                 config.eee_capability = abilities.eee_capability;
1794                 config.eeer = abilities.eeer_val;
1795                 config.low_power_ctrl = abilities.d3_lpan;
1796                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1797
1798                 if (status)
1799                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1800         }
1801         /* Update the link info */
1802         status = i40e_update_link_info(hw);
1803         if (status) {
1804                 /* Wait a little bit (on 40G cards it sometimes takes a really
1805                  * long time for link to come back from the atomic reset)
1806                  * and try once more
1807                  */
1808                 i40e_msec_delay(1000);
1809                 status = i40e_update_link_info(hw);
1810         }
1811         if (status)
1812                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1813
1814         return status;
1815 }
1816
1817 /**
1818  * i40e_aq_set_mac_config
1819  * @hw: pointer to the hw struct
1820  * @max_frame_size: Maximum Frame Size to be supported by the port
1821  * @crc_en: Tell HW to append a CRC to outgoing frames
1822  * @pacing: Pacing configurations
1823  * @cmd_details: pointer to command details structure or NULL
1824  *
1825  * Configure MAC settings for frame size, jumbo frame support and the
1826  * addition of a CRC by the hardware.
1827  **/
1828 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1829                                 u16 max_frame_size,
1830                                 bool crc_en, u16 pacing,
1831                                 struct i40e_asq_cmd_details *cmd_details)
1832 {
1833         struct i40e_aq_desc desc;
1834         struct i40e_aq_set_mac_config *cmd =
1835                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1836         enum i40e_status_code status;
1837
1838         if (max_frame_size == 0)
1839                 return I40E_ERR_PARAM;
1840
1841         i40e_fill_default_direct_cmd_desc(&desc,
1842                                           i40e_aqc_opc_set_mac_config);
1843
1844         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1845         cmd->params = ((u8)pacing & 0x0F) << 3;
1846         if (crc_en)
1847                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1848
1849         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1850
1851         return status;
1852 }
1853
1854 /**
1855  * i40e_aq_clear_pxe_mode
1856  * @hw: pointer to the hw struct
1857  * @cmd_details: pointer to command details structure or NULL
1858  *
1859  * Tell the firmware that the driver is taking over from PXE
1860  **/
1861 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1862                         struct i40e_asq_cmd_details *cmd_details)
1863 {
1864         enum i40e_status_code status;
1865         struct i40e_aq_desc desc;
1866         struct i40e_aqc_clear_pxe *cmd =
1867                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1868
1869         i40e_fill_default_direct_cmd_desc(&desc,
1870                                           i40e_aqc_opc_clear_pxe_mode);
1871
1872         cmd->rx_cnt = 0x2;
1873
1874         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1875
1876         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1877
1878         return status;
1879 }
1880
1881 /**
1882  * i40e_aq_set_link_restart_an
1883  * @hw: pointer to the hw struct
1884  * @enable_link: if true: enable link, if false: disable link
1885  * @cmd_details: pointer to command details structure or NULL
1886  *
1887  * Sets up the link and restarts the Auto-Negotiation over the link.
1888  **/
1889 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1890                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1891 {
1892         struct i40e_aq_desc desc;
1893         struct i40e_aqc_set_link_restart_an *cmd =
1894                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1895         enum i40e_status_code status;
1896
1897         i40e_fill_default_direct_cmd_desc(&desc,
1898                                           i40e_aqc_opc_set_link_restart_an);
1899
1900         cmd->command = I40E_AQ_PHY_RESTART_AN;
1901         if (enable_link)
1902                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1903         else
1904                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1905
1906         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1907
1908         return status;
1909 }
1910
1911 /**
1912  * i40e_aq_get_link_info
1913  * @hw: pointer to the hw struct
1914  * @enable_lse: enable/disable LinkStatusEvent reporting
1915  * @link: pointer to link status structure - optional
1916  * @cmd_details: pointer to command details structure or NULL
1917  *
1918  * Returns the link status of the adapter.
1919  **/
1920 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1921                                 bool enable_lse, struct i40e_link_status *link,
1922                                 struct i40e_asq_cmd_details *cmd_details)
1923 {
1924         struct i40e_aq_desc desc;
1925         struct i40e_aqc_get_link_status *resp =
1926                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1927         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1928         enum i40e_status_code status;
1929         bool tx_pause, rx_pause;
1930         u16 command_flags;
1931
1932         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1933
1934         if (enable_lse)
1935                 command_flags = I40E_AQ_LSE_ENABLE;
1936         else
1937                 command_flags = I40E_AQ_LSE_DISABLE;
1938         resp->command_flags = CPU_TO_LE16(command_flags);
1939
1940         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1941
1942         if (status != I40E_SUCCESS)
1943                 goto aq_get_link_info_exit;
1944
1945         /* save off old link status information */
1946         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1947                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1948
1949         /* update link status */
1950         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1951         hw->phy.media_type = i40e_get_media_type(hw);
1952         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1953         hw_link_info->link_info = resp->link_info;
1954         hw_link_info->an_info = resp->an_info;
1955         hw_link_info->ext_info = resp->ext_info;
1956         hw_link_info->loopback = resp->loopback;
1957         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1958         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1959
1960         /* update fc info */
1961         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1962         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1963         if (tx_pause & rx_pause)
1964                 hw->fc.current_mode = I40E_FC_FULL;
1965         else if (tx_pause)
1966                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1967         else if (rx_pause)
1968                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1969         else
1970                 hw->fc.current_mode = I40E_FC_NONE;
1971
1972         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1973                 hw_link_info->crc_enable = true;
1974         else
1975                 hw_link_info->crc_enable = false;
1976
1977         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1978                 hw_link_info->lse_enable = true;
1979         else
1980                 hw_link_info->lse_enable = false;
1981
1982         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1983              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1984                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1985
1986         /* save link status information */
1987         if (link)
1988                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1989                             I40E_NONDMA_TO_NONDMA);
1990
1991         /* flag cleared so helper functions don't call AQ again */
1992         hw->phy.get_link_info = false;
1993
1994 aq_get_link_info_exit:
1995         return status;
1996 }
1997
1998 /**
1999  * i40e_aq_set_phy_int_mask
2000  * @hw: pointer to the hw struct
2001  * @mask: interrupt mask to be set
2002  * @cmd_details: pointer to command details structure or NULL
2003  *
2004  * Set link interrupt mask.
2005  **/
2006 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2007                                 u16 mask,
2008                                 struct i40e_asq_cmd_details *cmd_details)
2009 {
2010         struct i40e_aq_desc desc;
2011         struct i40e_aqc_set_phy_int_mask *cmd =
2012                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2013         enum i40e_status_code status;
2014
2015         i40e_fill_default_direct_cmd_desc(&desc,
2016                                           i40e_aqc_opc_set_phy_int_mask);
2017
2018         cmd->event_mask = CPU_TO_LE16(mask);
2019
2020         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2021
2022         return status;
2023 }
2024
2025 /**
2026  * i40e_aq_get_local_advt_reg
2027  * @hw: pointer to the hw struct
2028  * @advt_reg: local AN advertisement register value
2029  * @cmd_details: pointer to command details structure or NULL
2030  *
2031  * Get the Local AN advertisement register value.
2032  **/
2033 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2034                                 u64 *advt_reg,
2035                                 struct i40e_asq_cmd_details *cmd_details)
2036 {
2037         struct i40e_aq_desc desc;
2038         struct i40e_aqc_an_advt_reg *resp =
2039                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2040         enum i40e_status_code status;
2041
2042         i40e_fill_default_direct_cmd_desc(&desc,
2043                                           i40e_aqc_opc_get_local_advt_reg);
2044
2045         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2046
2047         if (status != I40E_SUCCESS)
2048                 goto aq_get_local_advt_reg_exit;
2049
2050         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2051         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2052
2053 aq_get_local_advt_reg_exit:
2054         return status;
2055 }
2056
2057 /**
2058  * i40e_aq_set_local_advt_reg
2059  * @hw: pointer to the hw struct
2060  * @advt_reg: local AN advertisement register value
2061  * @cmd_details: pointer to command details structure or NULL
2062  *
2063  * Get the Local AN advertisement register value.
2064  **/
2065 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2066                                 u64 advt_reg,
2067                                 struct i40e_asq_cmd_details *cmd_details)
2068 {
2069         struct i40e_aq_desc desc;
2070         struct i40e_aqc_an_advt_reg *cmd =
2071                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2072         enum i40e_status_code status;
2073
2074         i40e_fill_default_direct_cmd_desc(&desc,
2075                                           i40e_aqc_opc_get_local_advt_reg);
2076
2077         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2078         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2079
2080         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2081
2082         return status;
2083 }
2084
2085 /**
2086  * i40e_aq_get_partner_advt
2087  * @hw: pointer to the hw struct
2088  * @advt_reg: AN partner advertisement register value
2089  * @cmd_details: pointer to command details structure or NULL
2090  *
2091  * Get the link partner AN advertisement register value.
2092  **/
2093 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2094                                 u64 *advt_reg,
2095                                 struct i40e_asq_cmd_details *cmd_details)
2096 {
2097         struct i40e_aq_desc desc;
2098         struct i40e_aqc_an_advt_reg *resp =
2099                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2100         enum i40e_status_code status;
2101
2102         i40e_fill_default_direct_cmd_desc(&desc,
2103                                           i40e_aqc_opc_get_partner_advt);
2104
2105         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2106
2107         if (status != I40E_SUCCESS)
2108                 goto aq_get_partner_advt_exit;
2109
2110         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2111         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2112
2113 aq_get_partner_advt_exit:
2114         return status;
2115 }
2116
2117 /**
2118  * i40e_aq_set_lb_modes
2119  * @hw: pointer to the hw struct
2120  * @lb_modes: loopback mode to be set
2121  * @cmd_details: pointer to command details structure or NULL
2122  *
2123  * Sets loopback modes.
2124  **/
2125 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2126                                 u16 lb_modes,
2127                                 struct i40e_asq_cmd_details *cmd_details)
2128 {
2129         struct i40e_aq_desc desc;
2130         struct i40e_aqc_set_lb_mode *cmd =
2131                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2132         enum i40e_status_code status;
2133
2134         i40e_fill_default_direct_cmd_desc(&desc,
2135                                           i40e_aqc_opc_set_lb_modes);
2136
2137         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2138
2139         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2140
2141         return status;
2142 }
2143
2144 /**
2145  * i40e_aq_set_phy_debug
2146  * @hw: pointer to the hw struct
2147  * @cmd_flags: debug command flags
2148  * @cmd_details: pointer to command details structure or NULL
2149  *
2150  * Reset the external PHY.
2151  **/
2152 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2153                                 struct i40e_asq_cmd_details *cmd_details)
2154 {
2155         struct i40e_aq_desc desc;
2156         struct i40e_aqc_set_phy_debug *cmd =
2157                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2158         enum i40e_status_code status;
2159
2160         i40e_fill_default_direct_cmd_desc(&desc,
2161                                           i40e_aqc_opc_set_phy_debug);
2162
2163         cmd->command_flags = cmd_flags;
2164
2165         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2166
2167         return status;
2168 }
2169
2170 /**
2171  * i40e_aq_add_vsi
2172  * @hw: pointer to the hw struct
2173  * @vsi_ctx: pointer to a vsi context struct
2174  * @cmd_details: pointer to command details structure or NULL
2175  *
2176  * Add a VSI context to the hardware.
2177 **/
2178 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2179                                 struct i40e_vsi_context *vsi_ctx,
2180                                 struct i40e_asq_cmd_details *cmd_details)
2181 {
2182         struct i40e_aq_desc desc;
2183         struct i40e_aqc_add_get_update_vsi *cmd =
2184                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2185         struct i40e_aqc_add_get_update_vsi_completion *resp =
2186                 (struct i40e_aqc_add_get_update_vsi_completion *)
2187                 &desc.params.raw;
2188         enum i40e_status_code status;
2189
2190         i40e_fill_default_direct_cmd_desc(&desc,
2191                                           i40e_aqc_opc_add_vsi);
2192
2193         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2194         cmd->connection_type = vsi_ctx->connection_type;
2195         cmd->vf_id = vsi_ctx->vf_num;
2196         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2197
2198         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2199
2200         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2201                                     sizeof(vsi_ctx->info), cmd_details);
2202
2203         if (status != I40E_SUCCESS)
2204                 goto aq_add_vsi_exit;
2205
2206         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2207         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2208         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2209         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2210
2211 aq_add_vsi_exit:
2212         return status;
2213 }
2214
2215 /**
2216  * i40e_aq_set_default_vsi
2217  * @hw: pointer to the hw struct
2218  * @seid: vsi number
2219  * @cmd_details: pointer to command details structure or NULL
2220  **/
2221 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2222                                 u16 seid,
2223                                 struct i40e_asq_cmd_details *cmd_details)
2224 {
2225         struct i40e_aq_desc desc;
2226         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2227                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2228                 &desc.params.raw;
2229         enum i40e_status_code status;
2230
2231         i40e_fill_default_direct_cmd_desc(&desc,
2232                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2233
2234         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2235         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2236         cmd->seid = CPU_TO_LE16(seid);
2237
2238         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2239
2240         return status;
2241 }
2242
2243 /**
2244  * i40e_aq_clear_default_vsi
2245  * @hw: pointer to the hw struct
2246  * @seid: vsi number
2247  * @cmd_details: pointer to command details structure or NULL
2248  **/
2249 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2250                                 u16 seid,
2251                                 struct i40e_asq_cmd_details *cmd_details)
2252 {
2253         struct i40e_aq_desc desc;
2254         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2255                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2256                 &desc.params.raw;
2257         enum i40e_status_code status;
2258
2259         i40e_fill_default_direct_cmd_desc(&desc,
2260                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2261
2262         cmd->promiscuous_flags = CPU_TO_LE16(0);
2263         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2264         cmd->seid = CPU_TO_LE16(seid);
2265
2266         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2267
2268         return status;
2269 }
2270
2271 /**
2272  * i40e_aq_set_vsi_unicast_promiscuous
2273  * @hw: pointer to the hw struct
2274  * @seid: vsi number
2275  * @set: set unicast promiscuous enable/disable
2276  * @cmd_details: pointer to command details structure or NULL
2277  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2278  **/
2279 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2280                                 u16 seid, bool set,
2281                                 struct i40e_asq_cmd_details *cmd_details,
2282                                 bool rx_only_promisc)
2283 {
2284         struct i40e_aq_desc desc;
2285         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2286                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2287         enum i40e_status_code status;
2288         u16 flags = 0;
2289
2290         i40e_fill_default_direct_cmd_desc(&desc,
2291                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2292
2293         if (set) {
2294                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2295                 if (rx_only_promisc &&
2296                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2297                      (hw->aq.api_maj_ver > 1)))
2298                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2299         }
2300
2301         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2302
2303         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2304         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2305              (hw->aq.api_maj_ver > 1))
2306                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2307
2308         cmd->seid = CPU_TO_LE16(seid);
2309         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2310
2311         return status;
2312 }
2313
2314 /**
2315  * i40e_aq_set_vsi_multicast_promiscuous
2316  * @hw: pointer to the hw struct
2317  * @seid: vsi number
2318  * @set: set multicast promiscuous enable/disable
2319  * @cmd_details: pointer to command details structure or NULL
2320  **/
2321 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2322                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2323 {
2324         struct i40e_aq_desc desc;
2325         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2326                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2327         enum i40e_status_code status;
2328         u16 flags = 0;
2329
2330         i40e_fill_default_direct_cmd_desc(&desc,
2331                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2332
2333         if (set)
2334                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2335
2336         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2337
2338         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2339
2340         cmd->seid = CPU_TO_LE16(seid);
2341         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2342
2343         return status;
2344 }
2345
2346 /**
2347  * i40e_aq_set_vsi_mc_promisc_on_vlan
2348  * @hw: pointer to the hw struct
2349  * @seid: vsi number
2350  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2351  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2352  * @cmd_details: pointer to command details structure or NULL
2353  **/
2354 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2355                                 u16 seid, bool enable, u16 vid,
2356                                 struct i40e_asq_cmd_details *cmd_details)
2357 {
2358         struct i40e_aq_desc desc;
2359         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2360                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2361         enum i40e_status_code status;
2362         u16 flags = 0;
2363
2364         i40e_fill_default_direct_cmd_desc(&desc,
2365                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2366
2367         if (enable)
2368                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2369
2370         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2371         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2372         cmd->seid = CPU_TO_LE16(seid);
2373         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2374
2375         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2376
2377         return status;
2378 }
2379
2380 /**
2381  * i40e_aq_set_vsi_uc_promisc_on_vlan
2382  * @hw: pointer to the hw struct
2383  * @seid: vsi number
2384  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2385  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2386  * @cmd_details: pointer to command details structure or NULL
2387  **/
2388 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2389                                 u16 seid, bool enable, u16 vid,
2390                                 struct i40e_asq_cmd_details *cmd_details)
2391 {
2392         struct i40e_aq_desc desc;
2393         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2394                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2395         enum i40e_status_code status;
2396         u16 flags = 0;
2397
2398         i40e_fill_default_direct_cmd_desc(&desc,
2399                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2400
2401         if (enable)
2402                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2403
2404         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2405         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2406         cmd->seid = CPU_TO_LE16(seid);
2407         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2408
2409         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2410
2411         return status;
2412 }
2413
2414 /**
2415  * i40e_aq_set_vsi_broadcast
2416  * @hw: pointer to the hw struct
2417  * @seid: vsi number
2418  * @set_filter: true to set filter, false to clear filter
2419  * @cmd_details: pointer to command details structure or NULL
2420  *
2421  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2422  **/
2423 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2424                                 u16 seid, bool set_filter,
2425                                 struct i40e_asq_cmd_details *cmd_details)
2426 {
2427         struct i40e_aq_desc desc;
2428         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2429                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2430         enum i40e_status_code status;
2431
2432         i40e_fill_default_direct_cmd_desc(&desc,
2433                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2434
2435         if (set_filter)
2436                 cmd->promiscuous_flags
2437                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2438         else
2439                 cmd->promiscuous_flags
2440                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2441
2442         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2443         cmd->seid = CPU_TO_LE16(seid);
2444         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2445
2446         return status;
2447 }
2448
2449 /**
2450  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2451  * @hw: pointer to the hw struct
2452  * @seid: vsi number
2453  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2454  * @cmd_details: pointer to command details structure or NULL
2455  **/
2456 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2457                                 u16 seid, bool enable,
2458                                 struct i40e_asq_cmd_details *cmd_details)
2459 {
2460         struct i40e_aq_desc desc;
2461         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2462                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2463         enum i40e_status_code status;
2464         u16 flags = 0;
2465
2466         i40e_fill_default_direct_cmd_desc(&desc,
2467                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2468         if (enable)
2469                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2470
2471         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2472         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2473         cmd->seid = CPU_TO_LE16(seid);
2474
2475         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2476
2477         return status;
2478 }
2479
2480 /**
2481  * i40e_get_vsi_params - get VSI configuration info
2482  * @hw: pointer to the hw struct
2483  * @vsi_ctx: pointer to a vsi context struct
2484  * @cmd_details: pointer to command details structure or NULL
2485  **/
2486 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2487                                 struct i40e_vsi_context *vsi_ctx,
2488                                 struct i40e_asq_cmd_details *cmd_details)
2489 {
2490         struct i40e_aq_desc desc;
2491         struct i40e_aqc_add_get_update_vsi *cmd =
2492                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2493         struct i40e_aqc_add_get_update_vsi_completion *resp =
2494                 (struct i40e_aqc_add_get_update_vsi_completion *)
2495                 &desc.params.raw;
2496         enum i40e_status_code status;
2497
2498         UNREFERENCED_1PARAMETER(cmd_details);
2499         i40e_fill_default_direct_cmd_desc(&desc,
2500                                           i40e_aqc_opc_get_vsi_parameters);
2501
2502         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2503
2504         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2505
2506         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2507                                     sizeof(vsi_ctx->info), NULL);
2508
2509         if (status != I40E_SUCCESS)
2510                 goto aq_get_vsi_params_exit;
2511
2512         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2513         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2514         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2515         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2516
2517 aq_get_vsi_params_exit:
2518         return status;
2519 }
2520
2521 /**
2522  * i40e_aq_update_vsi_params
2523  * @hw: pointer to the hw struct
2524  * @vsi_ctx: pointer to a vsi context struct
2525  * @cmd_details: pointer to command details structure or NULL
2526  *
2527  * Update a VSI context.
2528  **/
2529 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2530                                 struct i40e_vsi_context *vsi_ctx,
2531                                 struct i40e_asq_cmd_details *cmd_details)
2532 {
2533         struct i40e_aq_desc desc;
2534         struct i40e_aqc_add_get_update_vsi *cmd =
2535                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2536         struct i40e_aqc_add_get_update_vsi_completion *resp =
2537                 (struct i40e_aqc_add_get_update_vsi_completion *)
2538                 &desc.params.raw;
2539         enum i40e_status_code status;
2540
2541         i40e_fill_default_direct_cmd_desc(&desc,
2542                                           i40e_aqc_opc_update_vsi_parameters);
2543         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2544
2545         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2546
2547         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2548                                     sizeof(vsi_ctx->info), cmd_details);
2549
2550         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2551         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2552
2553         return status;
2554 }
2555
2556 /**
2557  * i40e_aq_get_switch_config
2558  * @hw: pointer to the hardware structure
2559  * @buf: pointer to the result buffer
2560  * @buf_size: length of input buffer
2561  * @start_seid: seid to start for the report, 0 == beginning
2562  * @cmd_details: pointer to command details structure or NULL
2563  *
2564  * Fill the buf with switch configuration returned from AdminQ command
2565  **/
2566 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2567                                 struct i40e_aqc_get_switch_config_resp *buf,
2568                                 u16 buf_size, u16 *start_seid,
2569                                 struct i40e_asq_cmd_details *cmd_details)
2570 {
2571         struct i40e_aq_desc desc;
2572         struct i40e_aqc_switch_seid *scfg =
2573                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2574         enum i40e_status_code status;
2575
2576         i40e_fill_default_direct_cmd_desc(&desc,
2577                                           i40e_aqc_opc_get_switch_config);
2578         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2579         if (buf_size > I40E_AQ_LARGE_BUF)
2580                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2581         scfg->seid = CPU_TO_LE16(*start_seid);
2582
2583         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2584         *start_seid = LE16_TO_CPU(scfg->seid);
2585
2586         return status;
2587 }
2588
2589 /**
2590  * i40e_aq_set_switch_config
2591  * @hw: pointer to the hardware structure
2592  * @flags: bit flag values to set
2593  * @valid_flags: which bit flags to set
2594  * @cmd_details: pointer to command details structure or NULL
2595  *
2596  * Set switch configuration bits
2597  **/
2598 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2599                                 u16 flags, u16 valid_flags,
2600                                 struct i40e_asq_cmd_details *cmd_details)
2601 {
2602         struct i40e_aq_desc desc;
2603         struct i40e_aqc_set_switch_config *scfg =
2604                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2605         enum i40e_status_code status;
2606
2607         i40e_fill_default_direct_cmd_desc(&desc,
2608                                           i40e_aqc_opc_set_switch_config);
2609         scfg->flags = CPU_TO_LE16(flags);
2610         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2611
2612         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2613
2614         return status;
2615 }
2616
2617 /**
2618  * i40e_aq_get_firmware_version
2619  * @hw: pointer to the hw struct
2620  * @fw_major_version: firmware major version
2621  * @fw_minor_version: firmware minor version
2622  * @fw_build: firmware build number
2623  * @api_major_version: major queue version
2624  * @api_minor_version: minor queue version
2625  * @cmd_details: pointer to command details structure or NULL
2626  *
2627  * Get the firmware version from the admin queue commands
2628  **/
2629 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2630                                 u16 *fw_major_version, u16 *fw_minor_version,
2631                                 u32 *fw_build,
2632                                 u16 *api_major_version, u16 *api_minor_version,
2633                                 struct i40e_asq_cmd_details *cmd_details)
2634 {
2635         struct i40e_aq_desc desc;
2636         struct i40e_aqc_get_version *resp =
2637                 (struct i40e_aqc_get_version *)&desc.params.raw;
2638         enum i40e_status_code status;
2639
2640         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2641
2642         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2643
2644         if (status == I40E_SUCCESS) {
2645                 if (fw_major_version != NULL)
2646                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2647                 if (fw_minor_version != NULL)
2648                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2649                 if (fw_build != NULL)
2650                         *fw_build = LE32_TO_CPU(resp->fw_build);
2651                 if (api_major_version != NULL)
2652                         *api_major_version = LE16_TO_CPU(resp->api_major);
2653                 if (api_minor_version != NULL)
2654                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2655
2656                 /* A workaround to fix the API version in SW */
2657                 if (api_major_version && api_minor_version &&
2658                     fw_major_version && fw_minor_version &&
2659                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2660                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2661                      (*fw_major_version > 4)))
2662                         *api_minor_version = 2;
2663         }
2664
2665         return status;
2666 }
2667
2668 /**
2669  * i40e_aq_send_driver_version
2670  * @hw: pointer to the hw struct
2671  * @dv: driver's major, minor version
2672  * @cmd_details: pointer to command details structure or NULL
2673  *
2674  * Send the driver version to the firmware
2675  **/
2676 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2677                                 struct i40e_driver_version *dv,
2678                                 struct i40e_asq_cmd_details *cmd_details)
2679 {
2680         struct i40e_aq_desc desc;
2681         struct i40e_aqc_driver_version *cmd =
2682                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2683         enum i40e_status_code status;
2684         u16 len;
2685
2686         if (dv == NULL)
2687                 return I40E_ERR_PARAM;
2688
2689         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2690
2691         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2692         cmd->driver_major_ver = dv->major_version;
2693         cmd->driver_minor_ver = dv->minor_version;
2694         cmd->driver_build_ver = dv->build_version;
2695         cmd->driver_subbuild_ver = dv->subbuild_version;
2696
2697         len = 0;
2698         while (len < sizeof(dv->driver_string) &&
2699                (dv->driver_string[len] < 0x80) &&
2700                dv->driver_string[len])
2701                 len++;
2702         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2703                                        len, cmd_details);
2704
2705         return status;
2706 }
2707
2708 /**
2709  * i40e_get_link_status - get status of the HW network link
2710  * @hw: pointer to the hw struct
2711  * @link_up: pointer to bool (true/false = linkup/linkdown)
2712  *
2713  * Variable link_up true if link is up, false if link is down.
2714  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2715  *
2716  * Side effect: LinkStatusEvent reporting becomes enabled
2717  **/
2718 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2719 {
2720         enum i40e_status_code status = I40E_SUCCESS;
2721
2722         if (hw->phy.get_link_info) {
2723                 status = i40e_update_link_info(hw);
2724
2725                 if (status != I40E_SUCCESS)
2726                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2727                                    status);
2728         }
2729
2730         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2731
2732         return status;
2733 }
2734
2735 /**
2736  * i40e_updatelink_status - update status of the HW network link
2737  * @hw: pointer to the hw struct
2738  **/
2739 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2740 {
2741         struct i40e_aq_get_phy_abilities_resp abilities;
2742         enum i40e_status_code status = I40E_SUCCESS;
2743
2744         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2745         if (status)
2746                 return status;
2747
2748         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2749                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2750                                                       &abilities, NULL);
2751                 if (status)
2752                         return status;
2753
2754                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2755                         sizeof(hw->phy.link_info.module_type));
2756         }
2757         return status;
2758 }
2759
2760
2761 /**
2762  * i40e_get_link_speed
2763  * @hw: pointer to the hw struct
2764  *
2765  * Returns the link speed of the adapter.
2766  **/
2767 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2768 {
2769         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2770         enum i40e_status_code status = I40E_SUCCESS;
2771
2772         if (hw->phy.get_link_info) {
2773                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2774
2775                 if (status != I40E_SUCCESS)
2776                         goto i40e_link_speed_exit;
2777         }
2778
2779         speed = hw->phy.link_info.link_speed;
2780
2781 i40e_link_speed_exit:
2782         return speed;
2783 }
2784
2785 /**
2786  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2787  * @hw: pointer to the hw struct
2788  * @uplink_seid: the MAC or other gizmo SEID
2789  * @downlink_seid: the VSI SEID
2790  * @enabled_tc: bitmap of TCs to be enabled
2791  * @default_port: true for default port VSI, false for control port
2792  * @veb_seid: pointer to where to put the resulting VEB SEID
2793  * @enable_stats: true to turn on VEB stats
2794  * @cmd_details: pointer to command details structure or NULL
2795  *
2796  * This asks the FW to add a VEB between the uplink and downlink
2797  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2798  **/
2799 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2800                                 u16 downlink_seid, u8 enabled_tc,
2801                                 bool default_port, u16 *veb_seid,
2802                                 bool enable_stats,
2803                                 struct i40e_asq_cmd_details *cmd_details)
2804 {
2805         struct i40e_aq_desc desc;
2806         struct i40e_aqc_add_veb *cmd =
2807                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2808         struct i40e_aqc_add_veb_completion *resp =
2809                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2810         enum i40e_status_code status;
2811         u16 veb_flags = 0;
2812
2813         /* SEIDs need to either both be set or both be 0 for floating VEB */
2814         if (!!uplink_seid != !!downlink_seid)
2815                 return I40E_ERR_PARAM;
2816
2817         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2818
2819         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2820         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2821         cmd->enable_tcs = enabled_tc;
2822         if (!uplink_seid)
2823                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2824         if (default_port)
2825                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2826         else
2827                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2828
2829         /* reverse logic here: set the bitflag to disable the stats */
2830         if (!enable_stats)
2831                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2832
2833         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2834
2835         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2836
2837         if (!status && veb_seid)
2838                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2839
2840         return status;
2841 }
2842
2843 /**
2844  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2845  * @hw: pointer to the hw struct
2846  * @veb_seid: the SEID of the VEB to query
2847  * @switch_id: the uplink switch id
2848  * @floating: set to true if the VEB is floating
2849  * @statistic_index: index of the stats counter block for this VEB
2850  * @vebs_used: number of VEB's used by function
2851  * @vebs_free: total VEB's not reserved by any function
2852  * @cmd_details: pointer to command details structure or NULL
2853  *
2854  * This retrieves the parameters for a particular VEB, specified by
2855  * uplink_seid, and returns them to the caller.
2856  **/
2857 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2858                                 u16 veb_seid, u16 *switch_id,
2859                                 bool *floating, u16 *statistic_index,
2860                                 u16 *vebs_used, u16 *vebs_free,
2861                                 struct i40e_asq_cmd_details *cmd_details)
2862 {
2863         struct i40e_aq_desc desc;
2864         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2865                 (struct i40e_aqc_get_veb_parameters_completion *)
2866                 &desc.params.raw;
2867         enum i40e_status_code status;
2868
2869         if (veb_seid == 0)
2870                 return I40E_ERR_PARAM;
2871
2872         i40e_fill_default_direct_cmd_desc(&desc,
2873                                           i40e_aqc_opc_get_veb_parameters);
2874         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2875
2876         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2877         if (status)
2878                 goto get_veb_exit;
2879
2880         if (switch_id)
2881                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2882         if (statistic_index)
2883                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2884         if (vebs_used)
2885                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2886         if (vebs_free)
2887                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2888         if (floating) {
2889                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2890
2891                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2892                         *floating = true;
2893                 else
2894                         *floating = false;
2895         }
2896
2897 get_veb_exit:
2898         return status;
2899 }
2900
2901 /**
2902  * i40e_aq_add_macvlan
2903  * @hw: pointer to the hw struct
2904  * @seid: VSI for the mac address
2905  * @mv_list: list of macvlans to be added
2906  * @count: length of the list
2907  * @cmd_details: pointer to command details structure or NULL
2908  *
2909  * Add MAC/VLAN addresses to the HW filtering
2910  **/
2911 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2912                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2913                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2914 {
2915         struct i40e_aq_desc desc;
2916         struct i40e_aqc_macvlan *cmd =
2917                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2918         enum i40e_status_code status;
2919         u16 buf_size;
2920         int i;
2921
2922         if (count == 0 || !mv_list || !hw)
2923                 return I40E_ERR_PARAM;
2924
2925         buf_size = count * sizeof(*mv_list);
2926
2927         /* prep the rest of the request */
2928         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2929         cmd->num_addresses = CPU_TO_LE16(count);
2930         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2931         cmd->seid[1] = 0;
2932         cmd->seid[2] = 0;
2933
2934         for (i = 0; i < count; i++)
2935                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2936                         mv_list[i].flags |=
2937                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2938
2939         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2940         if (buf_size > I40E_AQ_LARGE_BUF)
2941                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2942
2943         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2944                                        cmd_details);
2945
2946         return status;
2947 }
2948
2949 /**
2950  * i40e_aq_remove_macvlan
2951  * @hw: pointer to the hw struct
2952  * @seid: VSI for the mac address
2953  * @mv_list: list of macvlans to be removed
2954  * @count: length of the list
2955  * @cmd_details: pointer to command details structure or NULL
2956  *
2957  * Remove MAC/VLAN addresses from the HW filtering
2958  **/
2959 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2960                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2961                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2962 {
2963         struct i40e_aq_desc desc;
2964         struct i40e_aqc_macvlan *cmd =
2965                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2966         enum i40e_status_code status;
2967         u16 buf_size;
2968
2969         if (count == 0 || !mv_list || !hw)
2970                 return I40E_ERR_PARAM;
2971
2972         buf_size = count * sizeof(*mv_list);
2973
2974         /* prep the rest of the request */
2975         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2976         cmd->num_addresses = CPU_TO_LE16(count);
2977         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2978         cmd->seid[1] = 0;
2979         cmd->seid[2] = 0;
2980
2981         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2982         if (buf_size > I40E_AQ_LARGE_BUF)
2983                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2984
2985         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2986                                        cmd_details);
2987
2988         return status;
2989 }
2990
2991 /**
2992  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2993  * @hw: pointer to the hw struct
2994  * @opcode: AQ opcode for add or delete mirror rule
2995  * @sw_seid: Switch SEID (to which rule refers)
2996  * @rule_type: Rule Type (ingress/egress/VLAN)
2997  * @id: Destination VSI SEID or Rule ID
2998  * @count: length of the list
2999  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3000  * @cmd_details: pointer to command details structure or NULL
3001  * @rule_id: Rule ID returned from FW
3002  * @rule_used: Number of rules used in internal switch
3003  * @rule_free: Number of rules free in internal switch
3004  *
3005  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3006  * VEBs/VEPA elements only
3007  **/
3008 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3009                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3010                         u16 count, __le16 *mr_list,
3011                         struct i40e_asq_cmd_details *cmd_details,
3012                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3013 {
3014         struct i40e_aq_desc desc;
3015         struct i40e_aqc_add_delete_mirror_rule *cmd =
3016                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3017         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3018         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3019         enum i40e_status_code status;
3020         u16 buf_size;
3021
3022         buf_size = count * sizeof(*mr_list);
3023
3024         /* prep the rest of the request */
3025         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3026         cmd->seid = CPU_TO_LE16(sw_seid);
3027         cmd->rule_type = CPU_TO_LE16(rule_type &
3028                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3029         cmd->num_entries = CPU_TO_LE16(count);
3030         /* Dest VSI for add, rule_id for delete */
3031         cmd->destination = CPU_TO_LE16(id);
3032         if (mr_list) {
3033                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3034                                                 I40E_AQ_FLAG_RD));
3035                 if (buf_size > I40E_AQ_LARGE_BUF)
3036                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3037         }
3038
3039         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3040                                        cmd_details);
3041         if (status == I40E_SUCCESS ||
3042             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3043                 if (rule_id)
3044                         *rule_id = LE16_TO_CPU(resp->rule_id);
3045                 if (rules_used)
3046                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3047                 if (rules_free)
3048                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3049         }
3050         return status;
3051 }
3052
3053 /**
3054  * i40e_aq_add_mirrorrule - add a mirror rule
3055  * @hw: pointer to the hw struct
3056  * @sw_seid: Switch SEID (to which rule refers)
3057  * @rule_type: Rule Type (ingress/egress/VLAN)
3058  * @dest_vsi: SEID of VSI to which packets will be mirrored
3059  * @count: length of the list
3060  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3061  * @cmd_details: pointer to command details structure or NULL
3062  * @rule_id: Rule ID returned from FW
3063  * @rule_used: Number of rules used in internal switch
3064  * @rule_free: Number of rules free in internal switch
3065  *
3066  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3067  **/
3068 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3069                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3070                         struct i40e_asq_cmd_details *cmd_details,
3071                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3072 {
3073         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3074             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3075                 if (count == 0 || !mr_list)
3076                         return I40E_ERR_PARAM;
3077         }
3078
3079         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3080                                   rule_type, dest_vsi, count, mr_list,
3081                                   cmd_details, rule_id, rules_used, rules_free);
3082 }
3083
3084 /**
3085  * i40e_aq_delete_mirrorrule - delete a mirror rule
3086  * @hw: pointer to the hw struct
3087  * @sw_seid: Switch SEID (to which rule refers)
3088  * @rule_type: Rule Type (ingress/egress/VLAN)
3089  * @count: length of the list
3090  * @rule_id: Rule ID that is returned in the receive desc as part of
3091  *              add_mirrorrule.
3092  * @mr_list: list of mirrored VLAN IDs to be removed
3093  * @cmd_details: pointer to command details structure or NULL
3094  * @rule_used: Number of rules used in internal switch
3095  * @rule_free: Number of rules free in internal switch
3096  *
3097  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3098  **/
3099 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3100                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3101                         struct i40e_asq_cmd_details *cmd_details,
3102                         u16 *rules_used, u16 *rules_free)
3103 {
3104         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3105         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3106                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3107                  * mirroring. For other rule_type, count and rule_type should
3108                  * not matter.
3109                  */
3110                 if (count == 0 || !mr_list)
3111                         return I40E_ERR_PARAM;
3112         }
3113
3114         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3115                                   rule_type, rule_id, count, mr_list,
3116                                   cmd_details, NULL, rules_used, rules_free);
3117 }
3118
3119 /**
3120  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3121  * @hw: pointer to the hw struct
3122  * @seid: VSI for the vlan filters
3123  * @v_list: list of vlan filters to be added
3124  * @count: length of the list
3125  * @cmd_details: pointer to command details structure or NULL
3126  **/
3127 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3128                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3129                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3130 {
3131         struct i40e_aq_desc desc;
3132         struct i40e_aqc_macvlan *cmd =
3133                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3134         enum i40e_status_code status;
3135         u16 buf_size;
3136
3137         if (count == 0 || !v_list || !hw)
3138                 return I40E_ERR_PARAM;
3139
3140         buf_size = count * sizeof(*v_list);
3141
3142         /* prep the rest of the request */
3143         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3144         cmd->num_addresses = CPU_TO_LE16(count);
3145         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3146         cmd->seid[1] = 0;
3147         cmd->seid[2] = 0;
3148
3149         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3150         if (buf_size > I40E_AQ_LARGE_BUF)
3151                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3152
3153         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3154                                        cmd_details);
3155
3156         return status;
3157 }
3158
3159 /**
3160  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3161  * @hw: pointer to the hw struct
3162  * @seid: VSI for the vlan filters
3163  * @v_list: list of macvlans to be removed
3164  * @count: length of the list
3165  * @cmd_details: pointer to command details structure or NULL
3166  **/
3167 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3168                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3169                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3170 {
3171         struct i40e_aq_desc desc;
3172         struct i40e_aqc_macvlan *cmd =
3173                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3174         enum i40e_status_code status;
3175         u16 buf_size;
3176
3177         if (count == 0 || !v_list || !hw)
3178                 return I40E_ERR_PARAM;
3179
3180         buf_size = count * sizeof(*v_list);
3181
3182         /* prep the rest of the request */
3183         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3184         cmd->num_addresses = CPU_TO_LE16(count);
3185         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3186         cmd->seid[1] = 0;
3187         cmd->seid[2] = 0;
3188
3189         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3190         if (buf_size > I40E_AQ_LARGE_BUF)
3191                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3192
3193         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3194                                        cmd_details);
3195
3196         return status;
3197 }
3198
3199 /**
3200  * i40e_aq_send_msg_to_vf
3201  * @hw: pointer to the hardware structure
3202  * @vfid: vf id to send msg
3203  * @v_opcode: opcodes for VF-PF communication
3204  * @v_retval: return error code
3205  * @msg: pointer to the msg buffer
3206  * @msglen: msg length
3207  * @cmd_details: pointer to command details
3208  *
3209  * send msg to vf
3210  **/
3211 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3212                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3213                                 struct i40e_asq_cmd_details *cmd_details)
3214 {
3215         struct i40e_aq_desc desc;
3216         struct i40e_aqc_pf_vf_message *cmd =
3217                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3218         enum i40e_status_code status;
3219
3220         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3221         cmd->id = CPU_TO_LE32(vfid);
3222         desc.cookie_high = CPU_TO_LE32(v_opcode);
3223         desc.cookie_low = CPU_TO_LE32(v_retval);
3224         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3225         if (msglen) {
3226                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3227                                                 I40E_AQ_FLAG_RD));
3228                 if (msglen > I40E_AQ_LARGE_BUF)
3229                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3230                 desc.datalen = CPU_TO_LE16(msglen);
3231         }
3232         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3233
3234         return status;
3235 }
3236
3237 /**
3238  * i40e_aq_debug_read_register
3239  * @hw: pointer to the hw struct
3240  * @reg_addr: register address
3241  * @reg_val: register value
3242  * @cmd_details: pointer to command details structure or NULL
3243  *
3244  * Read the register using the admin queue commands
3245  **/
3246 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3247                                 u32 reg_addr, u64 *reg_val,
3248                                 struct i40e_asq_cmd_details *cmd_details)
3249 {
3250         struct i40e_aq_desc desc;
3251         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3252                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3253         enum i40e_status_code status;
3254
3255         if (reg_val == NULL)
3256                 return I40E_ERR_PARAM;
3257
3258         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3259
3260         cmd_resp->address = CPU_TO_LE32(reg_addr);
3261
3262         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3263
3264         if (status == I40E_SUCCESS) {
3265                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3266                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3267         }
3268
3269         return status;
3270 }
3271
3272 /**
3273  * i40e_aq_debug_write_register
3274  * @hw: pointer to the hw struct
3275  * @reg_addr: register address
3276  * @reg_val: register value
3277  * @cmd_details: pointer to command details structure or NULL
3278  *
3279  * Write to a register using the admin queue commands
3280  **/
3281 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3282                                 u32 reg_addr, u64 reg_val,
3283                                 struct i40e_asq_cmd_details *cmd_details)
3284 {
3285         struct i40e_aq_desc desc;
3286         struct i40e_aqc_debug_reg_read_write *cmd =
3287                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3288         enum i40e_status_code status;
3289
3290         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3291
3292         cmd->address = CPU_TO_LE32(reg_addr);
3293         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3294         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3295
3296         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3297
3298         return status;
3299 }
3300
3301 /**
3302  * i40e_aq_request_resource
3303  * @hw: pointer to the hw struct
3304  * @resource: resource id
3305  * @access: access type
3306  * @sdp_number: resource number
3307  * @timeout: the maximum time in ms that the driver may hold the resource
3308  * @cmd_details: pointer to command details structure or NULL
3309  *
3310  * requests common resource using the admin queue commands
3311  **/
3312 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3313                                 enum i40e_aq_resources_ids resource,
3314                                 enum i40e_aq_resource_access_type access,
3315                                 u8 sdp_number, u64 *timeout,
3316                                 struct i40e_asq_cmd_details *cmd_details)
3317 {
3318         struct i40e_aq_desc desc;
3319         struct i40e_aqc_request_resource *cmd_resp =
3320                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3321         enum i40e_status_code status;
3322
3323         DEBUGFUNC("i40e_aq_request_resource");
3324
3325         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3326
3327         cmd_resp->resource_id = CPU_TO_LE16(resource);
3328         cmd_resp->access_type = CPU_TO_LE16(access);
3329         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3330
3331         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3332         /* The completion specifies the maximum time in ms that the driver
3333          * may hold the resource in the Timeout field.
3334          * If the resource is held by someone else, the command completes with
3335          * busy return value and the timeout field indicates the maximum time
3336          * the current owner of the resource has to free it.
3337          */
3338         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3339                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3340
3341         return status;
3342 }
3343
3344 /**
3345  * i40e_aq_release_resource
3346  * @hw: pointer to the hw struct
3347  * @resource: resource id
3348  * @sdp_number: resource number
3349  * @cmd_details: pointer to command details structure or NULL
3350  *
3351  * release common resource using the admin queue commands
3352  **/
3353 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3354                                 enum i40e_aq_resources_ids resource,
3355                                 u8 sdp_number,
3356                                 struct i40e_asq_cmd_details *cmd_details)
3357 {
3358         struct i40e_aq_desc desc;
3359         struct i40e_aqc_request_resource *cmd =
3360                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3361         enum i40e_status_code status;
3362
3363         DEBUGFUNC("i40e_aq_release_resource");
3364
3365         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3366
3367         cmd->resource_id = CPU_TO_LE16(resource);
3368         cmd->resource_number = CPU_TO_LE32(sdp_number);
3369
3370         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3371
3372         return status;
3373 }
3374
3375 /**
3376  * i40e_aq_read_nvm
3377  * @hw: pointer to the hw struct
3378  * @module_pointer: module pointer location in words from the NVM beginning
3379  * @offset: byte offset from the module beginning
3380  * @length: length of the section to be read (in bytes from the offset)
3381  * @data: command buffer (size [bytes] = length)
3382  * @last_command: tells if this is the last command in a series
3383  * @cmd_details: pointer to command details structure or NULL
3384  *
3385  * Read the NVM using the admin queue commands
3386  **/
3387 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3388                                 u32 offset, u16 length, void *data,
3389                                 bool last_command,
3390                                 struct i40e_asq_cmd_details *cmd_details)
3391 {
3392         struct i40e_aq_desc desc;
3393         struct i40e_aqc_nvm_update *cmd =
3394                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3395         enum i40e_status_code status;
3396
3397         DEBUGFUNC("i40e_aq_read_nvm");
3398
3399         /* In offset the highest byte must be zeroed. */
3400         if (offset & 0xFF000000) {
3401                 status = I40E_ERR_PARAM;
3402                 goto i40e_aq_read_nvm_exit;
3403         }
3404
3405         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3406
3407         /* If this is the last command in a series, set the proper flag. */
3408         if (last_command)
3409                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3410         cmd->module_pointer = module_pointer;
3411         cmd->offset = CPU_TO_LE32(offset);
3412         cmd->length = CPU_TO_LE16(length);
3413
3414         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3415         if (length > I40E_AQ_LARGE_BUF)
3416                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3417
3418         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3419
3420 i40e_aq_read_nvm_exit:
3421         return status;
3422 }
3423
3424 /**
3425  * i40e_aq_read_nvm_config - read an nvm config block
3426  * @hw: pointer to the hw struct
3427  * @cmd_flags: NVM access admin command bits
3428  * @field_id: field or feature id
3429  * @data: buffer for result
3430  * @buf_size: buffer size
3431  * @element_count: pointer to count of elements read by FW
3432  * @cmd_details: pointer to command details structure or NULL
3433  **/
3434 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3435                                 u8 cmd_flags, u32 field_id, void *data,
3436                                 u16 buf_size, u16 *element_count,
3437                                 struct i40e_asq_cmd_details *cmd_details)
3438 {
3439         struct i40e_aq_desc desc;
3440         struct i40e_aqc_nvm_config_read *cmd =
3441                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3442         enum i40e_status_code status;
3443
3444         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3445         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3446         if (buf_size > I40E_AQ_LARGE_BUF)
3447                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3448
3449         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3450         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3451         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3452                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3453         else
3454                 cmd->element_id_msw = 0;
3455
3456         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3457
3458         if (!status && element_count)
3459                 *element_count = LE16_TO_CPU(cmd->element_count);
3460
3461         return status;
3462 }
3463
3464 /**
3465  * i40e_aq_write_nvm_config - write an nvm config block
3466  * @hw: pointer to the hw struct
3467  * @cmd_flags: NVM access admin command bits
3468  * @data: buffer for result
3469  * @buf_size: buffer size
3470  * @element_count: count of elements to be written
3471  * @cmd_details: pointer to command details structure or NULL
3472  **/
3473 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3474                                 u8 cmd_flags, void *data, u16 buf_size,
3475                                 u16 element_count,
3476                                 struct i40e_asq_cmd_details *cmd_details)
3477 {
3478         struct i40e_aq_desc desc;
3479         struct i40e_aqc_nvm_config_write *cmd =
3480                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3481         enum i40e_status_code status;
3482
3483         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3484         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3485         if (buf_size > I40E_AQ_LARGE_BUF)
3486                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3487
3488         cmd->element_count = CPU_TO_LE16(element_count);
3489         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3490         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3491
3492         return status;
3493 }
3494
3495 /**
3496  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3497  * @hw: pointer to the hw struct
3498  * @cmd_details: pointer to command details structure or NULL
3499  **/
3500 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3501                                 void *buff, u16 buff_size,
3502                                 struct i40e_asq_cmd_details *cmd_details)
3503 {
3504         struct i40e_aq_desc desc;
3505         enum i40e_status_code status;
3506
3507         UNREFERENCED_2PARAMETER(buff, buff_size);
3508
3509         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3510         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3511         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3512                 status = I40E_ERR_NOT_IMPLEMENTED;
3513
3514         return status;
3515 }
3516
3517 /**
3518  * i40e_aq_erase_nvm
3519  * @hw: pointer to the hw struct
3520  * @module_pointer: module pointer location in words from the NVM beginning
3521  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3522  * @length: length of the section to be erased (expressed in 4 KB)
3523  * @last_command: tells if this is the last command in a series
3524  * @cmd_details: pointer to command details structure or NULL
3525  *
3526  * Erase the NVM sector using the admin queue commands
3527  **/
3528 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3529                                 u32 offset, u16 length, bool last_command,
3530                                 struct i40e_asq_cmd_details *cmd_details)
3531 {
3532         struct i40e_aq_desc desc;
3533         struct i40e_aqc_nvm_update *cmd =
3534                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3535         enum i40e_status_code status;
3536
3537         DEBUGFUNC("i40e_aq_erase_nvm");
3538
3539         /* In offset the highest byte must be zeroed. */
3540         if (offset & 0xFF000000) {
3541                 status = I40E_ERR_PARAM;
3542                 goto i40e_aq_erase_nvm_exit;
3543         }
3544
3545         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3546
3547         /* If this is the last command in a series, set the proper flag. */
3548         if (last_command)
3549                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3550         cmd->module_pointer = module_pointer;
3551         cmd->offset = CPU_TO_LE32(offset);
3552         cmd->length = CPU_TO_LE16(length);
3553
3554         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3555
3556 i40e_aq_erase_nvm_exit:
3557         return status;
3558 }
3559
3560 /**
3561  * i40e_parse_discover_capabilities
3562  * @hw: pointer to the hw struct
3563  * @buff: pointer to a buffer containing device/function capability records
3564  * @cap_count: number of capability records in the list
3565  * @list_type_opc: type of capabilities list to parse
3566  *
3567  * Parse the device/function capabilities list.
3568  **/
3569 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3570                                      u32 cap_count,
3571                                      enum i40e_admin_queue_opc list_type_opc)
3572 {
3573         struct i40e_aqc_list_capabilities_element_resp *cap;
3574         u32 valid_functions, num_functions;
3575         u32 number, logical_id, phys_id;
3576         struct i40e_hw_capabilities *p;
3577         enum i40e_status_code status;
3578         u16 id, ocp_cfg_word0;
3579         u8 major_rev;
3580         u32 i = 0;
3581
3582         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3583
3584         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3585                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3586         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3587                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3588         else
3589                 return;
3590
3591         for (i = 0; i < cap_count; i++, cap++) {
3592                 id = LE16_TO_CPU(cap->id);
3593                 number = LE32_TO_CPU(cap->number);
3594                 logical_id = LE32_TO_CPU(cap->logical_id);
3595                 phys_id = LE32_TO_CPU(cap->phys_id);
3596                 major_rev = cap->major_rev;
3597
3598                 switch (id) {
3599                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3600                         p->switch_mode = number;
3601                         i40e_debug(hw, I40E_DEBUG_INIT,
3602                                    "HW Capability: Switch mode = %d\n",
3603                                    p->switch_mode);
3604                         break;
3605                 case I40E_AQ_CAP_ID_MNG_MODE:
3606                         p->management_mode = number;
3607                         i40e_debug(hw, I40E_DEBUG_INIT,
3608                                    "HW Capability: Management Mode = %d\n",
3609                                    p->management_mode);
3610                         break;
3611                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3612                         p->npar_enable = number;
3613                         i40e_debug(hw, I40E_DEBUG_INIT,
3614                                    "HW Capability: NPAR enable = %d\n",
3615                                    p->npar_enable);
3616                         break;
3617                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3618                         p->os2bmc = number;
3619                         i40e_debug(hw, I40E_DEBUG_INIT,
3620                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3621                         break;
3622                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3623                         p->valid_functions = number;
3624                         i40e_debug(hw, I40E_DEBUG_INIT,
3625                                    "HW Capability: Valid Functions = %d\n",
3626                                    p->valid_functions);
3627                         break;
3628                 case I40E_AQ_CAP_ID_SRIOV:
3629                         if (number == 1)
3630                                 p->sr_iov_1_1 = true;
3631                         i40e_debug(hw, I40E_DEBUG_INIT,
3632                                    "HW Capability: SR-IOV = %d\n",
3633                                    p->sr_iov_1_1);
3634                         break;
3635                 case I40E_AQ_CAP_ID_VF:
3636                         p->num_vfs = number;
3637                         p->vf_base_id = logical_id;
3638                         i40e_debug(hw, I40E_DEBUG_INIT,
3639                                    "HW Capability: VF count = %d\n",
3640                                    p->num_vfs);
3641                         i40e_debug(hw, I40E_DEBUG_INIT,
3642                                    "HW Capability: VF base_id = %d\n",
3643                                    p->vf_base_id);
3644                         break;
3645                 case I40E_AQ_CAP_ID_VMDQ:
3646                         if (number == 1)
3647                                 p->vmdq = true;
3648                         i40e_debug(hw, I40E_DEBUG_INIT,
3649                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3650                         break;
3651                 case I40E_AQ_CAP_ID_8021QBG:
3652                         if (number == 1)
3653                                 p->evb_802_1_qbg = true;
3654                         i40e_debug(hw, I40E_DEBUG_INIT,
3655                                    "HW Capability: 802.1Qbg = %d\n", number);
3656                         break;
3657                 case I40E_AQ_CAP_ID_8021QBR:
3658                         if (number == 1)
3659                                 p->evb_802_1_qbh = true;
3660                         i40e_debug(hw, I40E_DEBUG_INIT,
3661                                    "HW Capability: 802.1Qbh = %d\n", number);
3662                         break;
3663                 case I40E_AQ_CAP_ID_VSI:
3664                         p->num_vsis = number;
3665                         i40e_debug(hw, I40E_DEBUG_INIT,
3666                                    "HW Capability: VSI count = %d\n",
3667                                    p->num_vsis);
3668                         break;
3669                 case I40E_AQ_CAP_ID_DCB:
3670                         if (number == 1) {
3671                                 p->dcb = true;
3672                                 p->enabled_tcmap = logical_id;
3673                                 p->maxtc = phys_id;
3674                         }
3675                         i40e_debug(hw, I40E_DEBUG_INIT,
3676                                    "HW Capability: DCB = %d\n", p->dcb);
3677                         i40e_debug(hw, I40E_DEBUG_INIT,
3678                                    "HW Capability: TC Mapping = %d\n",
3679                                    logical_id);
3680                         i40e_debug(hw, I40E_DEBUG_INIT,
3681                                    "HW Capability: TC Max = %d\n", p->maxtc);
3682                         break;
3683                 case I40E_AQ_CAP_ID_FCOE:
3684                         if (number == 1)
3685                                 p->fcoe = true;
3686                         i40e_debug(hw, I40E_DEBUG_INIT,
3687                                    "HW Capability: FCOE = %d\n", p->fcoe);
3688                         break;
3689                 case I40E_AQ_CAP_ID_ISCSI:
3690                         if (number == 1)
3691                                 p->iscsi = true;
3692                         i40e_debug(hw, I40E_DEBUG_INIT,
3693                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3694                         break;
3695                 case I40E_AQ_CAP_ID_RSS:
3696                         p->rss = true;
3697                         p->rss_table_size = number;
3698                         p->rss_table_entry_width = logical_id;
3699                         i40e_debug(hw, I40E_DEBUG_INIT,
3700                                    "HW Capability: RSS = %d\n", p->rss);
3701                         i40e_debug(hw, I40E_DEBUG_INIT,
3702                                    "HW Capability: RSS table size = %d\n",
3703                                    p->rss_table_size);
3704                         i40e_debug(hw, I40E_DEBUG_INIT,
3705                                    "HW Capability: RSS table width = %d\n",
3706                                    p->rss_table_entry_width);
3707                         break;
3708                 case I40E_AQ_CAP_ID_RXQ:
3709                         p->num_rx_qp = number;
3710                         p->base_queue = phys_id;
3711                         i40e_debug(hw, I40E_DEBUG_INIT,
3712                                    "HW Capability: Rx QP = %d\n", number);
3713                         i40e_debug(hw, I40E_DEBUG_INIT,
3714                                    "HW Capability: base_queue = %d\n",
3715                                    p->base_queue);
3716                         break;
3717                 case I40E_AQ_CAP_ID_TXQ:
3718                         p->num_tx_qp = number;
3719                         p->base_queue = phys_id;
3720                         i40e_debug(hw, I40E_DEBUG_INIT,
3721                                    "HW Capability: Tx QP = %d\n", number);
3722                         i40e_debug(hw, I40E_DEBUG_INIT,
3723                                    "HW Capability: base_queue = %d\n",
3724                                    p->base_queue);
3725                         break;
3726                 case I40E_AQ_CAP_ID_MSIX:
3727                         p->num_msix_vectors = number;
3728                         i40e_debug(hw, I40E_DEBUG_INIT,
3729                                    "HW Capability: MSIX vector count = %d\n",
3730                                    p->num_msix_vectors);
3731                         break;
3732                 case I40E_AQ_CAP_ID_VF_MSIX:
3733                         p->num_msix_vectors_vf = number;
3734                         i40e_debug(hw, I40E_DEBUG_INIT,
3735                                    "HW Capability: MSIX VF vector count = %d\n",
3736                                    p->num_msix_vectors_vf);
3737                         break;
3738                 case I40E_AQ_CAP_ID_FLEX10:
3739                         if (major_rev == 1) {
3740                                 if (number == 1) {
3741                                         p->flex10_enable = true;
3742                                         p->flex10_capable = true;
3743                                 }
3744                         } else {
3745                                 /* Capability revision >= 2 */
3746                                 if (number & 1)
3747                                         p->flex10_enable = true;
3748                                 if (number & 2)
3749                                         p->flex10_capable = true;
3750                         }
3751                         p->flex10_mode = logical_id;
3752                         p->flex10_status = phys_id;
3753                         i40e_debug(hw, I40E_DEBUG_INIT,
3754                                    "HW Capability: Flex10 mode = %d\n",
3755                                    p->flex10_mode);
3756                         i40e_debug(hw, I40E_DEBUG_INIT,
3757                                    "HW Capability: Flex10 status = %d\n",
3758                                    p->flex10_status);
3759                         break;
3760                 case I40E_AQ_CAP_ID_CEM:
3761                         if (number == 1)
3762                                 p->mgmt_cem = true;
3763                         i40e_debug(hw, I40E_DEBUG_INIT,
3764                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3765                         break;
3766                 case I40E_AQ_CAP_ID_IWARP:
3767                         if (number == 1)
3768                                 p->iwarp = true;
3769                         i40e_debug(hw, I40E_DEBUG_INIT,
3770                                    "HW Capability: iWARP = %d\n", p->iwarp);
3771                         break;
3772                 case I40E_AQ_CAP_ID_LED:
3773                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3774                                 p->led[phys_id] = true;
3775                         i40e_debug(hw, I40E_DEBUG_INIT,
3776                                    "HW Capability: LED - PIN %d\n", phys_id);
3777                         break;
3778                 case I40E_AQ_CAP_ID_SDP:
3779                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3780                                 p->sdp[phys_id] = true;
3781                         i40e_debug(hw, I40E_DEBUG_INIT,
3782                                    "HW Capability: SDP - PIN %d\n", phys_id);
3783                         break;
3784                 case I40E_AQ_CAP_ID_MDIO:
3785                         if (number == 1) {
3786                                 p->mdio_port_num = phys_id;
3787                                 p->mdio_port_mode = logical_id;
3788                         }
3789                         i40e_debug(hw, I40E_DEBUG_INIT,
3790                                    "HW Capability: MDIO port number = %d\n",
3791                                    p->mdio_port_num);
3792                         i40e_debug(hw, I40E_DEBUG_INIT,
3793                                    "HW Capability: MDIO port mode = %d\n",
3794                                    p->mdio_port_mode);
3795                         break;
3796                 case I40E_AQ_CAP_ID_1588:
3797                         if (number == 1)
3798                                 p->ieee_1588 = true;
3799                         i40e_debug(hw, I40E_DEBUG_INIT,
3800                                    "HW Capability: IEEE 1588 = %d\n",
3801                                    p->ieee_1588);
3802                         break;
3803                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3804                         p->fd = true;
3805                         p->fd_filters_guaranteed = number;
3806                         p->fd_filters_best_effort = logical_id;
3807                         i40e_debug(hw, I40E_DEBUG_INIT,
3808                                    "HW Capability: Flow Director = 1\n");
3809                         i40e_debug(hw, I40E_DEBUG_INIT,
3810                                    "HW Capability: Guaranteed FD filters = %d\n",
3811                                    p->fd_filters_guaranteed);
3812                         break;
3813                 case I40E_AQ_CAP_ID_WSR_PROT:
3814                         p->wr_csr_prot = (u64)number;
3815                         p->wr_csr_prot |= (u64)logical_id << 32;
3816                         i40e_debug(hw, I40E_DEBUG_INIT,
3817                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3818                                    (p->wr_csr_prot & 0xffff));
3819                         break;
3820                 case I40E_AQ_CAP_ID_NVM_MGMT:
3821                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3822                                 p->sec_rev_disabled = true;
3823                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3824                                 p->update_disabled = true;
3825                         break;
3826 #ifdef X722_SUPPORT
3827                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3828                         hw->num_wol_proxy_filters = (u16)number;
3829                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3830                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3831                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3832                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3833                         else
3834                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3835                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3836                         p->proxy_support = p->proxy_support;
3837                         i40e_debug(hw, I40E_DEBUG_INIT,
3838                                    "HW Capability: WOL proxy filters = %d\n",
3839                                    hw->num_wol_proxy_filters);
3840                         break;
3841 #endif
3842                 default:
3843                         break;
3844                 }
3845         }
3846
3847         if (p->fcoe)
3848                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3849
3850         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3851         p->fcoe = false;
3852
3853         /* count the enabled ports (aka the "not disabled" ports) */
3854         hw->num_ports = 0;
3855         for (i = 0; i < 4; i++) {
3856                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3857                 u64 port_cfg = 0;
3858
3859                 /* use AQ read to get the physical register offset instead
3860                  * of the port relative offset
3861                  */
3862                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3863                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3864                         hw->num_ports++;
3865         }
3866
3867         /* OCP cards case: if a mezz is removed the ethernet port is at
3868          * disabled state in PRTGEN_CNF register. Additional NVM read is
3869          * needed in order to check if we are dealing with OCP card.
3870          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3871          * physical ports results in wrong partition id calculation and thus
3872          * not supporting WoL.
3873          */
3874         if (hw->mac.type == I40E_MAC_X722) {
3875                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
3876                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3877                                                   2 * I40E_SR_OCP_CFG_WORD0,
3878                                                   sizeof(ocp_cfg_word0),
3879                                                   &ocp_cfg_word0, true, NULL);
3880                         if (status == I40E_SUCCESS &&
3881                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3882                                 hw->num_ports = 4;
3883                         i40e_release_nvm(hw);
3884                 }
3885         }
3886
3887         valid_functions = p->valid_functions;
3888         num_functions = 0;
3889         while (valid_functions) {
3890                 if (valid_functions & 1)
3891                         num_functions++;
3892                 valid_functions >>= 1;
3893         }
3894
3895         /* partition id is 1-based, and functions are evenly spread
3896          * across the ports as partitions
3897          */
3898         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3899         hw->num_partitions = num_functions / hw->num_ports;
3900
3901         /* additional HW specific goodies that might
3902          * someday be HW version specific
3903          */
3904         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3905 }
3906
3907 /**
3908  * i40e_aq_discover_capabilities
3909  * @hw: pointer to the hw struct
3910  * @buff: a virtual buffer to hold the capabilities
3911  * @buff_size: Size of the virtual buffer
3912  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3913  * @list_type_opc: capabilities type to discover - pass in the command opcode
3914  * @cmd_details: pointer to command details structure or NULL
3915  *
3916  * Get the device capabilities descriptions from the firmware
3917  **/
3918 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3919                                 void *buff, u16 buff_size, u16 *data_size,
3920                                 enum i40e_admin_queue_opc list_type_opc,
3921                                 struct i40e_asq_cmd_details *cmd_details)
3922 {
3923         struct i40e_aqc_list_capabilites *cmd;
3924         struct i40e_aq_desc desc;
3925         enum i40e_status_code status = I40E_SUCCESS;
3926
3927         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3928
3929         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3930                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3931                 status = I40E_ERR_PARAM;
3932                 goto exit;
3933         }
3934
3935         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3936
3937         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3938         if (buff_size > I40E_AQ_LARGE_BUF)
3939                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3940
3941         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3942         *data_size = LE16_TO_CPU(desc.datalen);
3943
3944         if (status)
3945                 goto exit;
3946
3947         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3948                                          list_type_opc);
3949
3950 exit:
3951         return status;
3952 }
3953
3954 /**
3955  * i40e_aq_update_nvm
3956  * @hw: pointer to the hw struct
3957  * @module_pointer: module pointer location in words from the NVM beginning
3958  * @offset: byte offset from the module beginning
3959  * @length: length of the section to be written (in bytes from the offset)
3960  * @data: command buffer (size [bytes] = length)
3961  * @last_command: tells if this is the last command in a series
3962  * @cmd_details: pointer to command details structure or NULL
3963  *
3964  * Update the NVM using the admin queue commands
3965  **/
3966 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3967                                 u32 offset, u16 length, void *data,
3968                                 bool last_command,
3969                                 struct i40e_asq_cmd_details *cmd_details)
3970 {
3971         struct i40e_aq_desc desc;
3972         struct i40e_aqc_nvm_update *cmd =
3973                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3974         enum i40e_status_code status;
3975
3976         DEBUGFUNC("i40e_aq_update_nvm");
3977
3978         /* In offset the highest byte must be zeroed. */
3979         if (offset & 0xFF000000) {
3980                 status = I40E_ERR_PARAM;
3981                 goto i40e_aq_update_nvm_exit;
3982         }
3983
3984         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3985
3986         /* If this is the last command in a series, set the proper flag. */
3987         if (last_command)
3988                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3989         cmd->module_pointer = module_pointer;
3990         cmd->offset = CPU_TO_LE32(offset);
3991         cmd->length = CPU_TO_LE16(length);
3992
3993         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3994         if (length > I40E_AQ_LARGE_BUF)
3995                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3996
3997         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3998
3999 i40e_aq_update_nvm_exit:
4000         return status;
4001 }
4002
4003 /**
4004  * i40e_aq_get_lldp_mib
4005  * @hw: pointer to the hw struct
4006  * @bridge_type: type of bridge requested
4007  * @mib_type: Local, Remote or both Local and Remote MIBs
4008  * @buff: pointer to a user supplied buffer to store the MIB block
4009  * @buff_size: size of the buffer (in bytes)
4010  * @local_len : length of the returned Local LLDP MIB
4011  * @remote_len: length of the returned Remote LLDP MIB
4012  * @cmd_details: pointer to command details structure or NULL
4013  *
4014  * Requests the complete LLDP MIB (entire packet).
4015  **/
4016 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4017                                 u8 mib_type, void *buff, u16 buff_size,
4018                                 u16 *local_len, u16 *remote_len,
4019                                 struct i40e_asq_cmd_details *cmd_details)
4020 {
4021         struct i40e_aq_desc desc;
4022         struct i40e_aqc_lldp_get_mib *cmd =
4023                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4024         struct i40e_aqc_lldp_get_mib *resp =
4025                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4026         enum i40e_status_code status;
4027
4028         if (buff_size == 0 || !buff)
4029                 return I40E_ERR_PARAM;
4030
4031         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4032         /* Indirect Command */
4033         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4034
4035         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4036         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4037                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4038
4039         desc.datalen = CPU_TO_LE16(buff_size);
4040
4041         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4042         if (buff_size > I40E_AQ_LARGE_BUF)
4043                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4044
4045         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4046         if (!status) {
4047                 if (local_len != NULL)
4048                         *local_len = LE16_TO_CPU(resp->local_len);
4049                 if (remote_len != NULL)
4050                         *remote_len = LE16_TO_CPU(resp->remote_len);
4051         }
4052
4053         return status;
4054 }
4055
4056  /**
4057  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4058  * @hw: pointer to the hw struct
4059  * @mib_type: Local, Remote or both Local and Remote MIBs
4060  * @buff: pointer to a user supplied buffer to store the MIB block
4061  * @buff_size: size of the buffer (in bytes)
4062  * @cmd_details: pointer to command details structure or NULL
4063  *
4064  * Set the LLDP MIB.
4065  **/
4066 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4067                                 u8 mib_type, void *buff, u16 buff_size,
4068                                 struct i40e_asq_cmd_details *cmd_details)
4069 {
4070         struct i40e_aq_desc desc;
4071         struct i40e_aqc_lldp_set_local_mib *cmd =
4072                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4073         enum i40e_status_code status;
4074
4075         if (buff_size == 0 || !buff)
4076                 return I40E_ERR_PARAM;
4077
4078         i40e_fill_default_direct_cmd_desc(&desc,
4079                                 i40e_aqc_opc_lldp_set_local_mib);
4080         /* Indirect Command */
4081         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4082         if (buff_size > I40E_AQ_LARGE_BUF)
4083                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4084         desc.datalen = CPU_TO_LE16(buff_size);
4085
4086         cmd->type = mib_type;
4087         cmd->length = CPU_TO_LE16(buff_size);
4088         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4089         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4090
4091         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4092         return status;
4093 }
4094
4095 /**
4096  * i40e_aq_cfg_lldp_mib_change_event
4097  * @hw: pointer to the hw struct
4098  * @enable_update: Enable or Disable event posting
4099  * @cmd_details: pointer to command details structure or NULL
4100  *
4101  * Enable or Disable posting of an event on ARQ when LLDP MIB
4102  * associated with the interface changes
4103  **/
4104 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4105                                 bool enable_update,
4106                                 struct i40e_asq_cmd_details *cmd_details)
4107 {
4108         struct i40e_aq_desc desc;
4109         struct i40e_aqc_lldp_update_mib *cmd =
4110                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4111         enum i40e_status_code status;
4112
4113         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4114
4115         if (!enable_update)
4116                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4117
4118         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4119
4120         return status;
4121 }
4122
4123 /**
4124  * i40e_aq_add_lldp_tlv
4125  * @hw: pointer to the hw struct
4126  * @bridge_type: type of bridge
4127  * @buff: buffer with TLV to add
4128  * @buff_size: length of the buffer
4129  * @tlv_len: length of the TLV to be added
4130  * @mib_len: length of the LLDP MIB returned in response
4131  * @cmd_details: pointer to command details structure or NULL
4132  *
4133  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4134  * it is responsibility of the caller to make sure that the TLV is not
4135  * already present in the LLDPDU.
4136  * In return firmware will write the complete LLDP MIB with the newly
4137  * added TLV in the response buffer.
4138  **/
4139 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4140                                 void *buff, u16 buff_size, u16 tlv_len,
4141                                 u16 *mib_len,
4142                                 struct i40e_asq_cmd_details *cmd_details)
4143 {
4144         struct i40e_aq_desc desc;
4145         struct i40e_aqc_lldp_add_tlv *cmd =
4146                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4147         enum i40e_status_code status;
4148
4149         if (buff_size == 0 || !buff || tlv_len == 0)
4150                 return I40E_ERR_PARAM;
4151
4152         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4153
4154         /* Indirect Command */
4155         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4156         if (buff_size > I40E_AQ_LARGE_BUF)
4157                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4158         desc.datalen = CPU_TO_LE16(buff_size);
4159
4160         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4161                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4162         cmd->len = CPU_TO_LE16(tlv_len);
4163
4164         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4165         if (!status) {
4166                 if (mib_len != NULL)
4167                         *mib_len = LE16_TO_CPU(desc.datalen);
4168         }
4169
4170         return status;
4171 }
4172
4173 /**
4174  * i40e_aq_update_lldp_tlv
4175  * @hw: pointer to the hw struct
4176  * @bridge_type: type of bridge
4177  * @buff: buffer with TLV to update
4178  * @buff_size: size of the buffer holding original and updated TLVs
4179  * @old_len: Length of the Original TLV
4180  * @new_len: Length of the Updated TLV
4181  * @offset: offset of the updated TLV in the buff
4182  * @mib_len: length of the returned LLDP MIB
4183  * @cmd_details: pointer to command details structure or NULL
4184  *
4185  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4186  * Firmware will place the complete LLDP MIB in response buffer with the
4187  * updated TLV.
4188  **/
4189 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4190                                 u8 bridge_type, void *buff, u16 buff_size,
4191                                 u16 old_len, u16 new_len, u16 offset,
4192                                 u16 *mib_len,
4193                                 struct i40e_asq_cmd_details *cmd_details)
4194 {
4195         struct i40e_aq_desc desc;
4196         struct i40e_aqc_lldp_update_tlv *cmd =
4197                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4198         enum i40e_status_code status;
4199
4200         if (buff_size == 0 || !buff || offset == 0 ||
4201             old_len == 0 || new_len == 0)
4202                 return I40E_ERR_PARAM;
4203
4204         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4205
4206         /* Indirect Command */
4207         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4208         if (buff_size > I40E_AQ_LARGE_BUF)
4209                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4210         desc.datalen = CPU_TO_LE16(buff_size);
4211
4212         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4213                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4214         cmd->old_len = CPU_TO_LE16(old_len);
4215         cmd->new_offset = CPU_TO_LE16(offset);
4216         cmd->new_len = CPU_TO_LE16(new_len);
4217
4218         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4219         if (!status) {
4220                 if (mib_len != NULL)
4221                         *mib_len = LE16_TO_CPU(desc.datalen);
4222         }
4223
4224         return status;
4225 }
4226
4227 /**
4228  * i40e_aq_delete_lldp_tlv
4229  * @hw: pointer to the hw struct
4230  * @bridge_type: type of bridge
4231  * @buff: pointer to a user supplied buffer that has the TLV
4232  * @buff_size: length of the buffer
4233  * @tlv_len: length of the TLV to be deleted
4234  * @mib_len: length of the returned LLDP MIB
4235  * @cmd_details: pointer to command details structure or NULL
4236  *
4237  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4238  * The firmware places the entire LLDP MIB in the response buffer.
4239  **/
4240 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4241                                 u8 bridge_type, void *buff, u16 buff_size,
4242                                 u16 tlv_len, u16 *mib_len,
4243                                 struct i40e_asq_cmd_details *cmd_details)
4244 {
4245         struct i40e_aq_desc desc;
4246         struct i40e_aqc_lldp_add_tlv *cmd =
4247                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4248         enum i40e_status_code status;
4249
4250         if (buff_size == 0 || !buff)
4251                 return I40E_ERR_PARAM;
4252
4253         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4254
4255         /* Indirect Command */
4256         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4257         if (buff_size > I40E_AQ_LARGE_BUF)
4258                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4259         desc.datalen = CPU_TO_LE16(buff_size);
4260         cmd->len = CPU_TO_LE16(tlv_len);
4261         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4262                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4263
4264         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4265         if (!status) {
4266                 if (mib_len != NULL)
4267                         *mib_len = LE16_TO_CPU(desc.datalen);
4268         }
4269
4270         return status;
4271 }
4272
4273 /**
4274  * i40e_aq_stop_lldp
4275  * @hw: pointer to the hw struct
4276  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4277  * @cmd_details: pointer to command details structure or NULL
4278  *
4279  * Stop or Shutdown the embedded LLDP Agent
4280  **/
4281 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4282                                 struct i40e_asq_cmd_details *cmd_details)
4283 {
4284         struct i40e_aq_desc desc;
4285         struct i40e_aqc_lldp_stop *cmd =
4286                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4287         enum i40e_status_code status;
4288
4289         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4290
4291         if (shutdown_agent)
4292                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4293
4294         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4295
4296         return status;
4297 }
4298
4299 /**
4300  * i40e_aq_start_lldp
4301  * @hw: pointer to the hw struct
4302  * @cmd_details: pointer to command details structure or NULL
4303  *
4304  * Start the embedded LLDP Agent on all ports.
4305  **/
4306 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4307                                 struct i40e_asq_cmd_details *cmd_details)
4308 {
4309         struct i40e_aq_desc desc;
4310         struct i40e_aqc_lldp_start *cmd =
4311                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4312         enum i40e_status_code status;
4313
4314         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4315
4316         cmd->command = I40E_AQ_LLDP_AGENT_START;
4317
4318         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4319
4320         return status;
4321 }
4322
4323 /**
4324  * i40e_aq_get_cee_dcb_config
4325  * @hw: pointer to the hw struct
4326  * @buff: response buffer that stores CEE operational configuration
4327  * @buff_size: size of the buffer passed
4328  * @cmd_details: pointer to command details structure or NULL
4329  *
4330  * Get CEE DCBX mode operational configuration from firmware
4331  **/
4332 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4333                                 void *buff, u16 buff_size,
4334                                 struct i40e_asq_cmd_details *cmd_details)
4335 {
4336         struct i40e_aq_desc desc;
4337         enum i40e_status_code status;
4338
4339         if (buff_size == 0 || !buff)
4340                 return I40E_ERR_PARAM;
4341
4342         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4343
4344         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4345         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4346                                        cmd_details);
4347
4348         return status;
4349 }
4350
4351 /**
4352  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4353  * @hw: pointer to the hw struct
4354  * @start_agent: True if DCBx Agent needs to be Started
4355  *                              False if DCBx Agent needs to be Stopped
4356  * @cmd_details: pointer to command details structure or NULL
4357  *
4358  * Start/Stop the embedded dcbx Agent
4359  **/
4360 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4361                                 bool start_agent,
4362                                 struct i40e_asq_cmd_details *cmd_details)
4363 {
4364         struct i40e_aq_desc desc;
4365         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4366                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4367                                 &desc.params.raw;
4368         enum i40e_status_code status;
4369
4370         i40e_fill_default_direct_cmd_desc(&desc,
4371                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4372
4373         if (start_agent)
4374                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4375
4376         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4377
4378         return status;
4379 }
4380
4381 /**
4382  * i40e_aq_add_udp_tunnel
4383  * @hw: pointer to the hw struct
4384  * @udp_port: the UDP port to add
4385  * @header_len: length of the tunneling header length in DWords
4386  * @protocol_index: protocol index type
4387  * @filter_index: pointer to filter index
4388  * @cmd_details: pointer to command details structure or NULL
4389  **/
4390 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4391                                 u16 udp_port, u8 protocol_index,
4392                                 u8 *filter_index,
4393                                 struct i40e_asq_cmd_details *cmd_details)
4394 {
4395         struct i40e_aq_desc desc;
4396         struct i40e_aqc_add_udp_tunnel *cmd =
4397                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4398         struct i40e_aqc_del_udp_tunnel_completion *resp =
4399                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4400         enum i40e_status_code status;
4401
4402         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4403
4404         cmd->udp_port = CPU_TO_LE16(udp_port);
4405         cmd->protocol_type = protocol_index;
4406
4407         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4408
4409         if (!status && filter_index)
4410                 *filter_index = resp->index;
4411
4412         return status;
4413 }
4414
4415 /**
4416  * i40e_aq_del_udp_tunnel
4417  * @hw: pointer to the hw struct
4418  * @index: filter index
4419  * @cmd_details: pointer to command details structure or NULL
4420  **/
4421 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4422                                 struct i40e_asq_cmd_details *cmd_details)
4423 {
4424         struct i40e_aq_desc desc;
4425         struct i40e_aqc_remove_udp_tunnel *cmd =
4426                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4427         enum i40e_status_code status;
4428
4429         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4430
4431         cmd->index = index;
4432
4433         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4434
4435         return status;
4436 }
4437
4438 /**
4439  * i40e_aq_get_switch_resource_alloc (0x0204)
4440  * @hw: pointer to the hw struct
4441  * @num_entries: pointer to u8 to store the number of resource entries returned
4442  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4443  *        to store the resource information for all resource types.  Each
4444  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4445  * @count: size, in bytes, of the buffer provided
4446  * @cmd_details: pointer to command details structure or NULL
4447  *
4448  * Query the resources allocated to a function.
4449  **/
4450 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4451                         u8 *num_entries,
4452                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4453                         u16 count,
4454                         struct i40e_asq_cmd_details *cmd_details)
4455 {
4456         struct i40e_aq_desc desc;
4457         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4458                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4459         enum i40e_status_code status;
4460         u16 length = count * sizeof(*buf);
4461
4462         i40e_fill_default_direct_cmd_desc(&desc,
4463                                         i40e_aqc_opc_get_switch_resource_alloc);
4464
4465         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4466         if (length > I40E_AQ_LARGE_BUF)
4467                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4468
4469         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4470
4471         if (!status && num_entries)
4472                 *num_entries = cmd_resp->num_entries;
4473
4474         return status;
4475 }
4476
4477 /**
4478  * i40e_aq_delete_element - Delete switch element
4479  * @hw: pointer to the hw struct
4480  * @seid: the SEID to delete from the switch
4481  * @cmd_details: pointer to command details structure or NULL
4482  *
4483  * This deletes a switch element from the switch.
4484  **/
4485 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4486                                 struct i40e_asq_cmd_details *cmd_details)
4487 {
4488         struct i40e_aq_desc desc;
4489         struct i40e_aqc_switch_seid *cmd =
4490                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4491         enum i40e_status_code status;
4492
4493         if (seid == 0)
4494                 return I40E_ERR_PARAM;
4495
4496         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4497
4498         cmd->seid = CPU_TO_LE16(seid);
4499
4500         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4501
4502         return status;
4503 }
4504
4505 /**
4506  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4507  * @hw: pointer to the hw struct
4508  * @flags: component flags
4509  * @mac_seid: uplink seid (MAC SEID)
4510  * @vsi_seid: connected vsi seid
4511  * @ret_seid: seid of create pv component
4512  *
4513  * This instantiates an i40e port virtualizer with specified flags.
4514  * Depending on specified flags the port virtualizer can act as a
4515  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4516  */
4517 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4518                                        u16 mac_seid, u16 vsi_seid,
4519                                        u16 *ret_seid)
4520 {
4521         struct i40e_aq_desc desc;
4522         struct i40e_aqc_add_update_pv *cmd =
4523                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4524         struct i40e_aqc_add_update_pv_completion *resp =
4525                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4526         enum i40e_status_code status;
4527
4528         if (vsi_seid == 0)
4529                 return I40E_ERR_PARAM;
4530
4531         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4532         cmd->command_flags = CPU_TO_LE16(flags);
4533         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4534         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4535
4536         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4537         if (!status && ret_seid)
4538                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4539
4540         return status;
4541 }
4542
4543 /**
4544  * i40e_aq_add_tag - Add an S/E-tag
4545  * @hw: pointer to the hw struct
4546  * @direct_to_queue: should s-tag direct flow to a specific queue
4547  * @vsi_seid: VSI SEID to use this tag
4548  * @tag: value of the tag
4549  * @queue_num: queue number, only valid is direct_to_queue is true
4550  * @tags_used: return value, number of tags in use by this PF
4551  * @tags_free: return value, number of unallocated tags
4552  * @cmd_details: pointer to command details structure or NULL
4553  *
4554  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4555  * the number of tags allocated by the PF, and the number of unallocated
4556  * tags available.
4557  **/
4558 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4559                                 u16 vsi_seid, u16 tag, u16 queue_num,
4560                                 u16 *tags_used, u16 *tags_free,
4561                                 struct i40e_asq_cmd_details *cmd_details)
4562 {
4563         struct i40e_aq_desc desc;
4564         struct i40e_aqc_add_tag *cmd =
4565                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4566         struct i40e_aqc_add_remove_tag_completion *resp =
4567                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4568         enum i40e_status_code status;
4569
4570         if (vsi_seid == 0)
4571                 return I40E_ERR_PARAM;
4572
4573         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4574
4575         cmd->seid = CPU_TO_LE16(vsi_seid);
4576         cmd->tag = CPU_TO_LE16(tag);
4577         if (direct_to_queue) {
4578                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4579                 cmd->queue_number = CPU_TO_LE16(queue_num);
4580         }
4581
4582         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4583
4584         if (!status) {
4585                 if (tags_used != NULL)
4586                         *tags_used = LE16_TO_CPU(resp->tags_used);
4587                 if (tags_free != NULL)
4588                         *tags_free = LE16_TO_CPU(resp->tags_free);
4589         }
4590
4591         return status;
4592 }
4593
4594 /**
4595  * i40e_aq_remove_tag - Remove an S- or E-tag
4596  * @hw: pointer to the hw struct
4597  * @vsi_seid: VSI SEID this tag is associated with
4598  * @tag: value of the S-tag to delete
4599  * @tags_used: return value, number of tags in use by this PF
4600  * @tags_free: return value, number of unallocated tags
4601  * @cmd_details: pointer to command details structure or NULL
4602  *
4603  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4604  * the number of tags allocated by the PF, and the number of unallocated
4605  * tags available.
4606  **/
4607 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4608                                 u16 tag, u16 *tags_used, u16 *tags_free,
4609                                 struct i40e_asq_cmd_details *cmd_details)
4610 {
4611         struct i40e_aq_desc desc;
4612         struct i40e_aqc_remove_tag *cmd =
4613                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4614         struct i40e_aqc_add_remove_tag_completion *resp =
4615                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4616         enum i40e_status_code status;
4617
4618         if (vsi_seid == 0)
4619                 return I40E_ERR_PARAM;
4620
4621         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4622
4623         cmd->seid = CPU_TO_LE16(vsi_seid);
4624         cmd->tag = CPU_TO_LE16(tag);
4625
4626         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4627
4628         if (!status) {
4629                 if (tags_used != NULL)
4630                         *tags_used = LE16_TO_CPU(resp->tags_used);
4631                 if (tags_free != NULL)
4632                         *tags_free = LE16_TO_CPU(resp->tags_free);
4633         }
4634
4635         return status;
4636 }
4637
4638 /**
4639  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4640  * @hw: pointer to the hw struct
4641  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4642  * @etag: value of E-tag to add
4643  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4644  * @buf: address of indirect buffer
4645  * @tags_used: return value, number of E-tags in use by this port
4646  * @tags_free: return value, number of unallocated M-tags
4647  * @cmd_details: pointer to command details structure or NULL
4648  *
4649  * This associates a multicast E-tag to a port virtualizer.  It will return
4650  * the number of tags allocated by the PF, and the number of unallocated
4651  * tags available.
4652  *
4653  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4654  * num_tags_in_buf long.
4655  **/
4656 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4657                                 u16 etag, u8 num_tags_in_buf, void *buf,
4658                                 u16 *tags_used, u16 *tags_free,
4659                                 struct i40e_asq_cmd_details *cmd_details)
4660 {
4661         struct i40e_aq_desc desc;
4662         struct i40e_aqc_add_remove_mcast_etag *cmd =
4663                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4664         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4665            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4666         enum i40e_status_code status;
4667         u16 length = sizeof(u16) * num_tags_in_buf;
4668
4669         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4670                 return I40E_ERR_PARAM;
4671
4672         i40e_fill_default_direct_cmd_desc(&desc,
4673                                           i40e_aqc_opc_add_multicast_etag);
4674
4675         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4676         cmd->etag = CPU_TO_LE16(etag);
4677         cmd->num_unicast_etags = num_tags_in_buf;
4678
4679         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4680         if (length > I40E_AQ_LARGE_BUF)
4681                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4682
4683         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4684
4685         if (!status) {
4686                 if (tags_used != NULL)
4687                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4688                 if (tags_free != NULL)
4689                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4690         }
4691
4692         return status;
4693 }
4694
4695 /**
4696  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4697  * @hw: pointer to the hw struct
4698  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4699  * @etag: value of the E-tag to remove
4700  * @tags_used: return value, number of tags in use by this port
4701  * @tags_free: return value, number of unallocated tags
4702  * @cmd_details: pointer to command details structure or NULL
4703  *
4704  * This deletes an E-tag from the port virtualizer.  It will return
4705  * the number of tags allocated by the port, and the number of unallocated
4706  * tags available.
4707  **/
4708 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4709                                 u16 etag, u16 *tags_used, u16 *tags_free,
4710                                 struct i40e_asq_cmd_details *cmd_details)
4711 {
4712         struct i40e_aq_desc desc;
4713         struct i40e_aqc_add_remove_mcast_etag *cmd =
4714                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4715         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4716            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4717         enum i40e_status_code status;
4718
4719
4720         if (pv_seid == 0)
4721                 return I40E_ERR_PARAM;
4722
4723         i40e_fill_default_direct_cmd_desc(&desc,
4724                                           i40e_aqc_opc_remove_multicast_etag);
4725
4726         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4727         cmd->etag = CPU_TO_LE16(etag);
4728
4729         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4730
4731         if (!status) {
4732                 if (tags_used != NULL)
4733                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4734                 if (tags_free != NULL)
4735                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4736         }
4737
4738         return status;
4739 }
4740
4741 /**
4742  * i40e_aq_update_tag - Update an S/E-tag
4743  * @hw: pointer to the hw struct
4744  * @vsi_seid: VSI SEID using this S-tag
4745  * @old_tag: old tag value
4746  * @new_tag: new tag value
4747  * @tags_used: return value, number of tags in use by this PF
4748  * @tags_free: return value, number of unallocated tags
4749  * @cmd_details: pointer to command details structure or NULL
4750  *
4751  * This updates the value of the tag currently attached to this VSI
4752  * in the switch complex.  It will return the number of tags allocated
4753  * by the PF, and the number of unallocated tags available.
4754  **/
4755 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4756                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4757                                 u16 *tags_free,
4758                                 struct i40e_asq_cmd_details *cmd_details)
4759 {
4760         struct i40e_aq_desc desc;
4761         struct i40e_aqc_update_tag *cmd =
4762                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4763         struct i40e_aqc_update_tag_completion *resp =
4764                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4765         enum i40e_status_code status;
4766
4767         if (vsi_seid == 0)
4768                 return I40E_ERR_PARAM;
4769
4770         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4771
4772         cmd->seid = CPU_TO_LE16(vsi_seid);
4773         cmd->old_tag = CPU_TO_LE16(old_tag);
4774         cmd->new_tag = CPU_TO_LE16(new_tag);
4775
4776         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4777
4778         if (!status) {
4779                 if (tags_used != NULL)
4780                         *tags_used = LE16_TO_CPU(resp->tags_used);
4781                 if (tags_free != NULL)
4782                         *tags_free = LE16_TO_CPU(resp->tags_free);
4783         }
4784
4785         return status;
4786 }
4787
4788 /**
4789  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4790  * @hw: pointer to the hw struct
4791  * @tcmap: TC map for request/release any ignore PFC condition
4792  * @request: request or release ignore PFC condition
4793  * @tcmap_ret: return TCs for which PFC is currently ignored
4794  * @cmd_details: pointer to command details structure or NULL
4795  *
4796  * This sends out request/release to ignore PFC condition for a TC.
4797  * It will return the TCs for which PFC is currently ignored.
4798  **/
4799 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4800                                 bool request, u8 *tcmap_ret,
4801                                 struct i40e_asq_cmd_details *cmd_details)
4802 {
4803         struct i40e_aq_desc desc;
4804         struct i40e_aqc_pfc_ignore *cmd_resp =
4805                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4806         enum i40e_status_code status;
4807
4808         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4809
4810         if (request)
4811                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4812
4813         cmd_resp->tc_bitmap = tcmap;
4814
4815         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4816
4817         if (!status) {
4818                 if (tcmap_ret != NULL)
4819                         *tcmap_ret = cmd_resp->tc_bitmap;
4820         }
4821
4822         return status;
4823 }
4824
4825 /**
4826  * i40e_aq_dcb_updated - DCB Updated Command
4827  * @hw: pointer to the hw struct
4828  * @cmd_details: pointer to command details structure or NULL
4829  *
4830  * When LLDP is handled in PF this command is used by the PF
4831  * to notify EMP that a DCB setting is modified.
4832  * When LLDP is handled in EMP this command is used by the PF
4833  * to notify EMP whenever one of the following parameters get
4834  * modified:
4835  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4836  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4837  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4838  * EMP will return when the shared RPB settings have been
4839  * recomputed and modified. The retval field in the descriptor
4840  * will be set to 0 when RPB is modified.
4841  **/
4842 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4843                                 struct i40e_asq_cmd_details *cmd_details)
4844 {
4845         struct i40e_aq_desc desc;
4846         enum i40e_status_code status;
4847
4848         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4849
4850         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4851
4852         return status;
4853 }
4854
4855 /**
4856  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4857  * @hw: pointer to the hw struct
4858  * @seid: defines the SEID of the switch for which the stats are requested
4859  * @vlan_id: the VLAN ID for which the statistics are requested
4860  * @stat_index: index of the statistics counters block assigned to this VLAN
4861  * @cmd_details: pointer to command details structure or NULL
4862  *
4863  * XL710 supports 128 smonVlanStats counters.This command is used to
4864  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4865  * switch.
4866  **/
4867 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4868                                 u16 vlan_id, u16 *stat_index,
4869                                 struct i40e_asq_cmd_details *cmd_details)
4870 {
4871         struct i40e_aq_desc desc;
4872         struct i40e_aqc_add_remove_statistics *cmd_resp =
4873                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4874         enum i40e_status_code status;
4875
4876         if ((seid == 0) || (stat_index == NULL))
4877                 return I40E_ERR_PARAM;
4878
4879         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4880
4881         cmd_resp->seid = CPU_TO_LE16(seid);
4882         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4883
4884         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4885
4886         if (!status && stat_index)
4887                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4888
4889         return status;
4890 }
4891
4892 /**
4893  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4894  * @hw: pointer to the hw struct
4895  * @seid: defines the SEID of the switch for which the stats are requested
4896  * @vlan_id: the VLAN ID for which the statistics are requested
4897  * @stat_index: index of the statistics counters block assigned to this VLAN
4898  * @cmd_details: pointer to command details structure or NULL
4899  *
4900  * XL710 supports 128 smonVlanStats counters.This command is used to
4901  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4902  * switch.
4903  **/
4904 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4905                                 u16 vlan_id, u16 stat_index,
4906                                 struct i40e_asq_cmd_details *cmd_details)
4907 {
4908         struct i40e_aq_desc desc;
4909         struct i40e_aqc_add_remove_statistics *cmd =
4910                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4911         enum i40e_status_code status;
4912
4913         if (seid == 0)
4914                 return I40E_ERR_PARAM;
4915
4916         i40e_fill_default_direct_cmd_desc(&desc,
4917                                           i40e_aqc_opc_remove_statistics);
4918
4919         cmd->seid = CPU_TO_LE16(seid);
4920         cmd->vlan  = CPU_TO_LE16(vlan_id);
4921         cmd->stat_index = CPU_TO_LE16(stat_index);
4922
4923         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4924
4925         return status;
4926 }
4927
4928 /**
4929  * i40e_aq_set_port_parameters - set physical port parameters.
4930  * @hw: pointer to the hw struct
4931  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4932  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4933  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4934  * @double_vlan: if set double VLAN is enabled
4935  * @cmd_details: pointer to command details structure or NULL
4936  **/
4937 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4938                                 u16 bad_frame_vsi, bool save_bad_pac,
4939                                 bool pad_short_pac, bool double_vlan,
4940                                 struct i40e_asq_cmd_details *cmd_details)
4941 {
4942         struct i40e_aqc_set_port_parameters *cmd;
4943         enum i40e_status_code status;
4944         struct i40e_aq_desc desc;
4945         u16 command_flags = 0;
4946
4947         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4948
4949         i40e_fill_default_direct_cmd_desc(&desc,
4950                                           i40e_aqc_opc_set_port_parameters);
4951
4952         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4953         if (save_bad_pac)
4954                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4955         if (pad_short_pac)
4956                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4957         if (double_vlan)
4958                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4959         cmd->command_flags = CPU_TO_LE16(command_flags);
4960
4961         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4962
4963         return status;
4964 }
4965
4966 /**
4967  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4968  * @hw: pointer to the hw struct
4969  * @seid: seid for the physical port/switching component/vsi
4970  * @buff: Indirect buffer to hold data parameters and response
4971  * @buff_size: Indirect buffer size
4972  * @opcode: Tx scheduler AQ command opcode
4973  * @cmd_details: pointer to command details structure or NULL
4974  *
4975  * Generic command handler for Tx scheduler AQ commands
4976  **/
4977 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4978                                 void *buff, u16 buff_size,
4979                                  enum i40e_admin_queue_opc opcode,
4980                                 struct i40e_asq_cmd_details *cmd_details)
4981 {
4982         struct i40e_aq_desc desc;
4983         struct i40e_aqc_tx_sched_ind *cmd =
4984                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4985         enum i40e_status_code status;
4986         bool cmd_param_flag = false;
4987
4988         switch (opcode) {
4989         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4990         case i40e_aqc_opc_configure_vsi_tc_bw:
4991         case i40e_aqc_opc_enable_switching_comp_ets:
4992         case i40e_aqc_opc_modify_switching_comp_ets:
4993         case i40e_aqc_opc_disable_switching_comp_ets:
4994         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4995         case i40e_aqc_opc_configure_switching_comp_bw_config:
4996                 cmd_param_flag = true;
4997                 break;
4998         case i40e_aqc_opc_query_vsi_bw_config:
4999         case i40e_aqc_opc_query_vsi_ets_sla_config:
5000         case i40e_aqc_opc_query_switching_comp_ets_config:
5001         case i40e_aqc_opc_query_port_ets_config:
5002         case i40e_aqc_opc_query_switching_comp_bw_config:
5003                 cmd_param_flag = false;
5004                 break;
5005         default:
5006                 return I40E_ERR_PARAM;
5007         }
5008
5009         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5010
5011         /* Indirect command */
5012         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5013         if (cmd_param_flag)
5014                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5015         if (buff_size > I40E_AQ_LARGE_BUF)
5016                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5017
5018         desc.datalen = CPU_TO_LE16(buff_size);
5019
5020         cmd->vsi_seid = CPU_TO_LE16(seid);
5021
5022         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5023
5024         return status;
5025 }
5026
5027 /**
5028  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5029  * @hw: pointer to the hw struct
5030  * @seid: VSI seid
5031  * @credit: BW limit credits (0 = disabled)
5032  * @max_credit: Max BW limit credits
5033  * @cmd_details: pointer to command details structure or NULL
5034  **/
5035 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5036                                 u16 seid, u16 credit, u8 max_credit,
5037                                 struct i40e_asq_cmd_details *cmd_details)
5038 {
5039         struct i40e_aq_desc desc;
5040         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5041                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5042         enum i40e_status_code status;
5043
5044         i40e_fill_default_direct_cmd_desc(&desc,
5045                                           i40e_aqc_opc_configure_vsi_bw_limit);
5046
5047         cmd->vsi_seid = CPU_TO_LE16(seid);
5048         cmd->credit = CPU_TO_LE16(credit);
5049         cmd->max_credit = max_credit;
5050
5051         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5052
5053         return status;
5054 }
5055
5056 /**
5057  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5058  * @hw: pointer to the hw struct
5059  * @seid: switching component seid
5060  * @credit: BW limit credits (0 = disabled)
5061  * @max_bw: Max BW limit credits
5062  * @cmd_details: pointer to command details structure or NULL
5063  **/
5064 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5065                                 u16 seid, u16 credit, u8 max_bw,
5066                                 struct i40e_asq_cmd_details *cmd_details)
5067 {
5068         struct i40e_aq_desc desc;
5069         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5070           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5071         enum i40e_status_code status;
5072
5073         i40e_fill_default_direct_cmd_desc(&desc,
5074                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5075
5076         cmd->seid = CPU_TO_LE16(seid);
5077         cmd->credit = CPU_TO_LE16(credit);
5078         cmd->max_bw = max_bw;
5079
5080         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5081
5082         return status;
5083 }
5084
5085 /**
5086  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5087  * @hw: pointer to the hw struct
5088  * @seid: VSI seid
5089  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5090  * @cmd_details: pointer to command details structure or NULL
5091  **/
5092 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5093                         u16 seid,
5094                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5095                         struct i40e_asq_cmd_details *cmd_details)
5096 {
5097         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5098                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5099                                     cmd_details);
5100 }
5101
5102 /**
5103  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5104  * @hw: pointer to the hw struct
5105  * @seid: VSI seid
5106  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5107  * @cmd_details: pointer to command details structure or NULL
5108  **/
5109 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5110                         u16 seid,
5111                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5112                         struct i40e_asq_cmd_details *cmd_details)
5113 {
5114         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5115                                     i40e_aqc_opc_configure_vsi_tc_bw,
5116                                     cmd_details);
5117 }
5118
5119 /**
5120  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5121  * @hw: pointer to the hw struct
5122  * @seid: seid of the switching component connected to Physical Port
5123  * @ets_data: Buffer holding ETS parameters
5124  * @cmd_details: pointer to command details structure or NULL
5125  **/
5126 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5127                 u16 seid,
5128                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5129                 enum i40e_admin_queue_opc opcode,
5130                 struct i40e_asq_cmd_details *cmd_details)
5131 {
5132         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5133                                     sizeof(*ets_data), opcode, cmd_details);
5134 }
5135
5136 /**
5137  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5138  * @hw: pointer to the hw struct
5139  * @seid: seid of the switching component
5140  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5141  * @cmd_details: pointer to command details structure or NULL
5142  **/
5143 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5144         u16 seid,
5145         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5146         struct i40e_asq_cmd_details *cmd_details)
5147 {
5148         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5149                             i40e_aqc_opc_configure_switching_comp_bw_config,
5150                             cmd_details);
5151 }
5152
5153 /**
5154  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5155  * @hw: pointer to the hw struct
5156  * @seid: seid of the switching component
5157  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5158  * @cmd_details: pointer to command details structure or NULL
5159  **/
5160 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5161         struct i40e_hw *hw, u16 seid,
5162         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5163         struct i40e_asq_cmd_details *cmd_details)
5164 {
5165         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5166                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5167                             cmd_details);
5168 }
5169
5170 /**
5171  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5172  * @hw: pointer to the hw struct
5173  * @seid: seid of the VSI
5174  * @bw_data: Buffer to hold VSI BW configuration
5175  * @cmd_details: pointer to command details structure or NULL
5176  **/
5177 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5178                         u16 seid,
5179                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5180                         struct i40e_asq_cmd_details *cmd_details)
5181 {
5182         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5183                                     i40e_aqc_opc_query_vsi_bw_config,
5184                                     cmd_details);
5185 }
5186
5187 /**
5188  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5189  * @hw: pointer to the hw struct
5190  * @seid: seid of the VSI
5191  * @bw_data: Buffer to hold VSI BW configuration per TC
5192  * @cmd_details: pointer to command details structure or NULL
5193  **/
5194 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5195                         u16 seid,
5196                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5197                         struct i40e_asq_cmd_details *cmd_details)
5198 {
5199         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5200                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5201                                     cmd_details);
5202 }
5203
5204 /**
5205  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5206  * @hw: pointer to the hw struct
5207  * @seid: seid of the switching component
5208  * @bw_data: Buffer to hold switching component's per TC BW config
5209  * @cmd_details: pointer to command details structure or NULL
5210  **/
5211 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5212                 u16 seid,
5213                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5214                 struct i40e_asq_cmd_details *cmd_details)
5215 {
5216         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5217                                    i40e_aqc_opc_query_switching_comp_ets_config,
5218                                    cmd_details);
5219 }
5220
5221 /**
5222  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5223  * @hw: pointer to the hw struct
5224  * @seid: seid of the VSI or switching component connected to Physical Port
5225  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5226  * @cmd_details: pointer to command details structure or NULL
5227  **/
5228 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5229                         u16 seid,
5230                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5231                         struct i40e_asq_cmd_details *cmd_details)
5232 {
5233         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5234                                     i40e_aqc_opc_query_port_ets_config,
5235                                     cmd_details);
5236 }
5237
5238 /**
5239  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5240  * @hw: pointer to the hw struct
5241  * @seid: seid of the switching component
5242  * @bw_data: Buffer to hold switching component's BW configuration
5243  * @cmd_details: pointer to command details structure or NULL
5244  **/
5245 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5246                 u16 seid,
5247                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5248                 struct i40e_asq_cmd_details *cmd_details)
5249 {
5250         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5251                                     i40e_aqc_opc_query_switching_comp_bw_config,
5252                                     cmd_details);
5253 }
5254
5255 /**
5256  * i40e_validate_filter_settings
5257  * @hw: pointer to the hardware structure
5258  * @settings: Filter control settings
5259  *
5260  * Check and validate the filter control settings passed.
5261  * The function checks for the valid filter/context sizes being
5262  * passed for FCoE and PE.
5263  *
5264  * Returns I40E_SUCCESS if the values passed are valid and within
5265  * range else returns an error.
5266  **/
5267 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5268                                 struct i40e_filter_control_settings *settings)
5269 {
5270         u32 fcoe_cntx_size, fcoe_filt_size;
5271         u32 pe_cntx_size, pe_filt_size;
5272         u32 fcoe_fmax;
5273
5274         u32 val;
5275
5276         /* Validate FCoE settings passed */
5277         switch (settings->fcoe_filt_num) {
5278         case I40E_HASH_FILTER_SIZE_1K:
5279         case I40E_HASH_FILTER_SIZE_2K:
5280         case I40E_HASH_FILTER_SIZE_4K:
5281         case I40E_HASH_FILTER_SIZE_8K:
5282         case I40E_HASH_FILTER_SIZE_16K:
5283         case I40E_HASH_FILTER_SIZE_32K:
5284                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5285                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5286                 break;
5287         default:
5288                 return I40E_ERR_PARAM;
5289         }
5290
5291         switch (settings->fcoe_cntx_num) {
5292         case I40E_DMA_CNTX_SIZE_512:
5293         case I40E_DMA_CNTX_SIZE_1K:
5294         case I40E_DMA_CNTX_SIZE_2K:
5295         case I40E_DMA_CNTX_SIZE_4K:
5296                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5297                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5298                 break;
5299         default:
5300                 return I40E_ERR_PARAM;
5301         }
5302
5303         /* Validate PE settings passed */
5304         switch (settings->pe_filt_num) {
5305         case I40E_HASH_FILTER_SIZE_1K:
5306         case I40E_HASH_FILTER_SIZE_2K:
5307         case I40E_HASH_FILTER_SIZE_4K:
5308         case I40E_HASH_FILTER_SIZE_8K:
5309         case I40E_HASH_FILTER_SIZE_16K:
5310         case I40E_HASH_FILTER_SIZE_32K:
5311         case I40E_HASH_FILTER_SIZE_64K:
5312         case I40E_HASH_FILTER_SIZE_128K:
5313         case I40E_HASH_FILTER_SIZE_256K:
5314         case I40E_HASH_FILTER_SIZE_512K:
5315         case I40E_HASH_FILTER_SIZE_1M:
5316                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5317                 pe_filt_size <<= (u32)settings->pe_filt_num;
5318                 break;
5319         default:
5320                 return I40E_ERR_PARAM;
5321         }
5322
5323         switch (settings->pe_cntx_num) {
5324         case I40E_DMA_CNTX_SIZE_512:
5325         case I40E_DMA_CNTX_SIZE_1K:
5326         case I40E_DMA_CNTX_SIZE_2K:
5327         case I40E_DMA_CNTX_SIZE_4K:
5328         case I40E_DMA_CNTX_SIZE_8K:
5329         case I40E_DMA_CNTX_SIZE_16K:
5330         case I40E_DMA_CNTX_SIZE_32K:
5331         case I40E_DMA_CNTX_SIZE_64K:
5332         case I40E_DMA_CNTX_SIZE_128K:
5333         case I40E_DMA_CNTX_SIZE_256K:
5334                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5335                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5336                 break;
5337         default:
5338                 return I40E_ERR_PARAM;
5339         }
5340
5341         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5342         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5343         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5344                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5345         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5346                 return I40E_ERR_INVALID_SIZE;
5347
5348         return I40E_SUCCESS;
5349 }
5350
5351 /**
5352  * i40e_set_filter_control
5353  * @hw: pointer to the hardware structure
5354  * @settings: Filter control settings
5355  *
5356  * Set the Queue Filters for PE/FCoE and enable filters required
5357  * for a single PF. It is expected that these settings are programmed
5358  * at the driver initialization time.
5359  **/
5360 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5361                                 struct i40e_filter_control_settings *settings)
5362 {
5363         enum i40e_status_code ret = I40E_SUCCESS;
5364         u32 hash_lut_size = 0;
5365         u32 val;
5366
5367         if (!settings)
5368                 return I40E_ERR_PARAM;
5369
5370         /* Validate the input settings */
5371         ret = i40e_validate_filter_settings(hw, settings);
5372         if (ret)
5373                 return ret;
5374
5375         /* Read the PF Queue Filter control register */
5376         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5377
5378         /* Program required PE hash buckets for the PF */
5379         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5380         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5381                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5382         /* Program required PE contexts for the PF */
5383         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5384         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5385                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5386
5387         /* Program required FCoE hash buckets for the PF */
5388         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5389         val |= ((u32)settings->fcoe_filt_num <<
5390                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5391                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5392         /* Program required FCoE DDP contexts for the PF */
5393         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5394         val |= ((u32)settings->fcoe_cntx_num <<
5395                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5396                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5397
5398         /* Program Hash LUT size for the PF */
5399         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5400         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5401                 hash_lut_size = 1;
5402         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5403                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5404
5405         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5406         if (settings->enable_fdir)
5407                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5408         if (settings->enable_ethtype)
5409                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5410         if (settings->enable_macvlan)
5411                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5412
5413         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5414
5415         return I40E_SUCCESS;
5416 }
5417
5418 /**
5419  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5420  * @hw: pointer to the hw struct
5421  * @mac_addr: MAC address to use in the filter
5422  * @ethtype: Ethertype to use in the filter
5423  * @flags: Flags that needs to be applied to the filter
5424  * @vsi_seid: seid of the control VSI
5425  * @queue: VSI queue number to send the packet to
5426  * @is_add: Add control packet filter if True else remove
5427  * @stats: Structure to hold information on control filter counts
5428  * @cmd_details: pointer to command details structure or NULL
5429  *
5430  * This command will Add or Remove control packet filter for a control VSI.
5431  * In return it will update the total number of perfect filter count in
5432  * the stats member.
5433  **/
5434 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5435                                 u8 *mac_addr, u16 ethtype, u16 flags,
5436                                 u16 vsi_seid, u16 queue, bool is_add,
5437                                 struct i40e_control_filter_stats *stats,
5438                                 struct i40e_asq_cmd_details *cmd_details)
5439 {
5440         struct i40e_aq_desc desc;
5441         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5442                 (struct i40e_aqc_add_remove_control_packet_filter *)
5443                 &desc.params.raw;
5444         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5445                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5446                 &desc.params.raw;
5447         enum i40e_status_code status;
5448
5449         if (vsi_seid == 0)
5450                 return I40E_ERR_PARAM;
5451
5452         if (is_add) {
5453                 i40e_fill_default_direct_cmd_desc(&desc,
5454                                 i40e_aqc_opc_add_control_packet_filter);
5455                 cmd->queue = CPU_TO_LE16(queue);
5456         } else {
5457                 i40e_fill_default_direct_cmd_desc(&desc,
5458                                 i40e_aqc_opc_remove_control_packet_filter);
5459         }
5460
5461         if (mac_addr)
5462                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5463                             I40E_NONDMA_TO_NONDMA);
5464
5465         cmd->etype = CPU_TO_LE16(ethtype);
5466         cmd->flags = CPU_TO_LE16(flags);
5467         cmd->seid = CPU_TO_LE16(vsi_seid);
5468
5469         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5470
5471         if (!status && stats) {
5472                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5473                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5474                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5475                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5476         }
5477
5478         return status;
5479 }
5480
5481 /**
5482  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5483  * @hw: pointer to the hw struct
5484  * @seid: VSI seid to add ethertype filter from
5485  **/
5486 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5487 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5488                                                     u16 seid)
5489 {
5490         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5491                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5492                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5493         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5494         enum i40e_status_code status;
5495
5496         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5497                                                        seid, 0, true, NULL,
5498                                                        NULL);
5499         if (status)
5500                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5501 }
5502
5503 /**
5504  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5505  * @filters: list of cloud filters
5506  * @filter_count: length of list
5507  *
5508  * There's an issue in the device where the Geneve VNI layout needs
5509  * to be shifted 1 byte over from the VxLAN VNI
5510  **/
5511 STATIC void i40e_fix_up_geneve_vni(
5512         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5513         u8 filter_count)
5514 {
5515         struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;
5516         int i;
5517
5518         for (i = 0; i < filter_count; i++) {
5519                 u16 tnl_type;
5520                 u32 ti;
5521
5522                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5523                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5524                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5525                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5526                         ti = LE32_TO_CPU(f[i].tenant_id);
5527                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5528                 }
5529         }
5530 }
5531
5532 /**
5533  * i40e_aq_add_cloud_filters
5534  * @hw: pointer to the hardware structure
5535  * @seid: VSI seid to add cloud filters from
5536  * @filters: Buffer which contains the filters to be added
5537  * @filter_count: number of filters contained in the buffer
5538  *
5539  * Set the cloud filters for a given VSI.  The contents of the
5540  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5541  * in by the caller of the function.
5542  *
5543  **/
5544 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5545         u16 seid,
5546         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5547         u8 filter_count)
5548 {
5549         struct i40e_aq_desc desc;
5550         struct i40e_aqc_add_remove_cloud_filters *cmd =
5551         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5552         enum i40e_status_code status;
5553         u16 buff_len;
5554
5555         i40e_fill_default_direct_cmd_desc(&desc,
5556                                           i40e_aqc_opc_add_cloud_filters);
5557
5558         buff_len = filter_count * sizeof(*filters);
5559         desc.datalen = CPU_TO_LE16(buff_len);
5560         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5561         cmd->num_filters = filter_count;
5562         cmd->seid = CPU_TO_LE16(seid);
5563
5564         i40e_fix_up_geneve_vni(filters, filter_count);
5565
5566         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5567
5568         return status;
5569 }
5570
5571 /**
5572  * i40e_aq_remove_cloud_filters
5573  * @hw: pointer to the hardware structure
5574  * @seid: VSI seid to remove cloud filters from
5575  * @filters: Buffer which contains the filters to be removed
5576  * @filter_count: number of filters contained in the buffer
5577  *
5578  * Remove the cloud filters for a given VSI.  The contents of the
5579  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5580  * in by the caller of the function.
5581  *
5582  **/
5583 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5584                 u16 seid,
5585                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5586                 u8 filter_count)
5587 {
5588         struct i40e_aq_desc desc;
5589         struct i40e_aqc_add_remove_cloud_filters *cmd =
5590         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5591         enum i40e_status_code status;
5592         u16 buff_len;
5593
5594         i40e_fill_default_direct_cmd_desc(&desc,
5595                                           i40e_aqc_opc_remove_cloud_filters);
5596
5597         buff_len = filter_count * sizeof(*filters);
5598         desc.datalen = CPU_TO_LE16(buff_len);
5599         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5600         cmd->num_filters = filter_count;
5601         cmd->seid = CPU_TO_LE16(seid);
5602
5603         i40e_fix_up_geneve_vni(filters, filter_count);
5604
5605         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5606
5607         return status;
5608 }
5609
5610 /**
5611  * i40e_aq_alternate_write
5612  * @hw: pointer to the hardware structure
5613  * @reg_addr0: address of first dword to be read
5614  * @reg_val0: value to be written under 'reg_addr0'
5615  * @reg_addr1: address of second dword to be read
5616  * @reg_val1: value to be written under 'reg_addr1'
5617  *
5618  * Write one or two dwords to alternate structure. Fields are indicated
5619  * by 'reg_addr0' and 'reg_addr1' register numbers.
5620  *
5621  **/
5622 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5623                                 u32 reg_addr0, u32 reg_val0,
5624                                 u32 reg_addr1, u32 reg_val1)
5625 {
5626         struct i40e_aq_desc desc;
5627         struct i40e_aqc_alternate_write *cmd_resp =
5628                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5629         enum i40e_status_code status;
5630
5631         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5632         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5633         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5634         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5635         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5636
5637         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5638
5639         return status;
5640 }
5641
5642 /**
5643  * i40e_aq_alternate_write_indirect
5644  * @hw: pointer to the hardware structure
5645  * @addr: address of a first register to be modified
5646  * @dw_count: number of alternate structure fields to write
5647  * @buffer: pointer to the command buffer
5648  *
5649  * Write 'dw_count' dwords from 'buffer' to alternate structure
5650  * starting at 'addr'.
5651  *
5652  **/
5653 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5654                                 u32 addr, u32 dw_count, void *buffer)
5655 {
5656         struct i40e_aq_desc desc;
5657         struct i40e_aqc_alternate_ind_write *cmd_resp =
5658                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5659         enum i40e_status_code status;
5660
5661         if (buffer == NULL)
5662                 return I40E_ERR_PARAM;
5663
5664         /* Indirect command */
5665         i40e_fill_default_direct_cmd_desc(&desc,
5666                                          i40e_aqc_opc_alternate_write_indirect);
5667
5668         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5669         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5670         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5671                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5672
5673         cmd_resp->address = CPU_TO_LE32(addr);
5674         cmd_resp->length = CPU_TO_LE32(dw_count);
5675
5676         status = i40e_asq_send_command(hw, &desc, buffer,
5677                                        I40E_LO_DWORD(4*dw_count), NULL);
5678
5679         return status;
5680 }
5681
5682 /**
5683  * i40e_aq_alternate_read
5684  * @hw: pointer to the hardware structure
5685  * @reg_addr0: address of first dword to be read
5686  * @reg_val0: pointer for data read from 'reg_addr0'
5687  * @reg_addr1: address of second dword to be read
5688  * @reg_val1: pointer for data read from 'reg_addr1'
5689  *
5690  * Read one or two dwords from alternate structure. Fields are indicated
5691  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5692  * is not passed then only register at 'reg_addr0' is read.
5693  *
5694  **/
5695 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5696                                 u32 reg_addr0, u32 *reg_val0,
5697                                 u32 reg_addr1, u32 *reg_val1)
5698 {
5699         struct i40e_aq_desc desc;
5700         struct i40e_aqc_alternate_write *cmd_resp =
5701                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5702         enum i40e_status_code status;
5703
5704         if (reg_val0 == NULL)
5705                 return I40E_ERR_PARAM;
5706
5707         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5708         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5709         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5710
5711         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5712
5713         if (status == I40E_SUCCESS) {
5714                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5715
5716                 if (reg_val1 != NULL)
5717                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5718         }
5719
5720         return status;
5721 }
5722
5723 /**
5724  * i40e_aq_alternate_read_indirect
5725  * @hw: pointer to the hardware structure
5726  * @addr: address of the alternate structure field
5727  * @dw_count: number of alternate structure fields to read
5728  * @buffer: pointer to the command buffer
5729  *
5730  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5731  * place them in 'buffer'. The buffer should be allocated by caller.
5732  *
5733  **/
5734 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5735                                 u32 addr, u32 dw_count, void *buffer)
5736 {
5737         struct i40e_aq_desc desc;
5738         struct i40e_aqc_alternate_ind_write *cmd_resp =
5739                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5740         enum i40e_status_code status;
5741
5742         if (buffer == NULL)
5743                 return I40E_ERR_PARAM;
5744
5745         /* Indirect command */
5746         i40e_fill_default_direct_cmd_desc(&desc,
5747                 i40e_aqc_opc_alternate_read_indirect);
5748
5749         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5750         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5751         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5752                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5753
5754         cmd_resp->address = CPU_TO_LE32(addr);
5755         cmd_resp->length = CPU_TO_LE32(dw_count);
5756
5757         status = i40e_asq_send_command(hw, &desc, buffer,
5758                                        I40E_LO_DWORD(4*dw_count), NULL);
5759
5760         return status;
5761 }
5762
5763 /**
5764  *  i40e_aq_alternate_clear
5765  *  @hw: pointer to the HW structure.
5766  *
5767  *  Clear the alternate structures of the port from which the function
5768  *  is called.
5769  *
5770  **/
5771 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5772 {
5773         struct i40e_aq_desc desc;
5774         enum i40e_status_code status;
5775
5776         i40e_fill_default_direct_cmd_desc(&desc,
5777                                           i40e_aqc_opc_alternate_clear_port);
5778
5779         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5780
5781         return status;
5782 }
5783
5784 /**
5785  *  i40e_aq_alternate_write_done
5786  *  @hw: pointer to the HW structure.
5787  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5788  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5789  *
5790  *  Indicates to the FW that alternate structures have been changed.
5791  *
5792  **/
5793 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5794                 u8 bios_mode, bool *reset_needed)
5795 {
5796         struct i40e_aq_desc desc;
5797         struct i40e_aqc_alternate_write_done *cmd =
5798                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5799         enum i40e_status_code status;
5800
5801         if (reset_needed == NULL)
5802                 return I40E_ERR_PARAM;
5803
5804         i40e_fill_default_direct_cmd_desc(&desc,
5805                                           i40e_aqc_opc_alternate_write_done);
5806
5807         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5808
5809         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5810         if (!status && reset_needed)
5811                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5812                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5813
5814         return status;
5815 }
5816
5817 /**
5818  *  i40e_aq_set_oem_mode
5819  *  @hw: pointer to the HW structure.
5820  *  @oem_mode: the OEM mode to be used
5821  *
5822  *  Sets the device to a specific operating mode. Currently the only supported
5823  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5824  *
5825  **/
5826 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5827                 u8 oem_mode)
5828 {
5829         struct i40e_aq_desc desc;
5830         struct i40e_aqc_alternate_write_done *cmd =
5831                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5832         enum i40e_status_code status;
5833
5834         i40e_fill_default_direct_cmd_desc(&desc,
5835                                           i40e_aqc_opc_alternate_set_mode);
5836
5837         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5838
5839         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5840
5841         return status;
5842 }
5843
5844 /**
5845  * i40e_aq_resume_port_tx
5846  * @hw: pointer to the hardware structure
5847  * @cmd_details: pointer to command details structure or NULL
5848  *
5849  * Resume port's Tx traffic
5850  **/
5851 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5852                                 struct i40e_asq_cmd_details *cmd_details)
5853 {
5854         struct i40e_aq_desc desc;
5855         enum i40e_status_code status;
5856
5857         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5858
5859         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5860
5861         return status;
5862 }
5863
5864 /**
5865  * i40e_set_pci_config_data - store PCI bus info
5866  * @hw: pointer to hardware structure
5867  * @link_status: the link status word from PCI config space
5868  *
5869  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5870  **/
5871 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5872 {
5873         hw->bus.type = i40e_bus_type_pci_express;
5874
5875         switch (link_status & I40E_PCI_LINK_WIDTH) {
5876         case I40E_PCI_LINK_WIDTH_1:
5877                 hw->bus.width = i40e_bus_width_pcie_x1;
5878                 break;
5879         case I40E_PCI_LINK_WIDTH_2:
5880                 hw->bus.width = i40e_bus_width_pcie_x2;
5881                 break;
5882         case I40E_PCI_LINK_WIDTH_4:
5883                 hw->bus.width = i40e_bus_width_pcie_x4;
5884                 break;
5885         case I40E_PCI_LINK_WIDTH_8:
5886                 hw->bus.width = i40e_bus_width_pcie_x8;
5887                 break;
5888         default:
5889                 hw->bus.width = i40e_bus_width_unknown;
5890                 break;
5891         }
5892
5893         switch (link_status & I40E_PCI_LINK_SPEED) {
5894         case I40E_PCI_LINK_SPEED_2500:
5895                 hw->bus.speed = i40e_bus_speed_2500;
5896                 break;
5897         case I40E_PCI_LINK_SPEED_5000:
5898                 hw->bus.speed = i40e_bus_speed_5000;
5899                 break;
5900         case I40E_PCI_LINK_SPEED_8000:
5901                 hw->bus.speed = i40e_bus_speed_8000;
5902                 break;
5903         default:
5904                 hw->bus.speed = i40e_bus_speed_unknown;
5905                 break;
5906         }
5907 }
5908
5909 /**
5910  * i40e_aq_debug_dump
5911  * @hw: pointer to the hardware structure
5912  * @cluster_id: specific cluster to dump
5913  * @table_id: table id within cluster
5914  * @start_index: index of line in the block to read
5915  * @buff_size: dump buffer size
5916  * @buff: dump buffer
5917  * @ret_buff_size: actual buffer size returned
5918  * @ret_next_table: next block to read
5919  * @ret_next_index: next index to read
5920  *
5921  * Dump internal FW/HW data for debug purposes.
5922  *
5923  **/
5924 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5925                                 u8 table_id, u32 start_index, u16 buff_size,
5926                                 void *buff, u16 *ret_buff_size,
5927                                 u8 *ret_next_table, u32 *ret_next_index,
5928                                 struct i40e_asq_cmd_details *cmd_details)
5929 {
5930         struct i40e_aq_desc desc;
5931         struct i40e_aqc_debug_dump_internals *cmd =
5932                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5933         struct i40e_aqc_debug_dump_internals *resp =
5934                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5935         enum i40e_status_code status;
5936
5937         if (buff_size == 0 || !buff)
5938                 return I40E_ERR_PARAM;
5939
5940         i40e_fill_default_direct_cmd_desc(&desc,
5941                                           i40e_aqc_opc_debug_dump_internals);
5942         /* Indirect Command */
5943         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5944         if (buff_size > I40E_AQ_LARGE_BUF)
5945                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5946
5947         cmd->cluster_id = cluster_id;
5948         cmd->table_id = table_id;
5949         cmd->idx = CPU_TO_LE32(start_index);
5950
5951         desc.datalen = CPU_TO_LE16(buff_size);
5952
5953         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5954         if (!status) {
5955                 if (ret_buff_size != NULL)
5956                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5957                 if (ret_next_table != NULL)
5958                         *ret_next_table = resp->table_id;
5959                 if (ret_next_index != NULL)
5960                         *ret_next_index = LE32_TO_CPU(resp->idx);
5961         }
5962
5963         return status;
5964 }
5965
5966 /**
5967  * i40e_read_bw_from_alt_ram
5968  * @hw: pointer to the hardware structure
5969  * @max_bw: pointer for max_bw read
5970  * @min_bw: pointer for min_bw read
5971  * @min_valid: pointer for bool that is true if min_bw is a valid value
5972  * @max_valid: pointer for bool that is true if max_bw is a valid value
5973  *
5974  * Read bw from the alternate ram for the given pf
5975  **/
5976 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5977                                         u32 *max_bw, u32 *min_bw,
5978                                         bool *min_valid, bool *max_valid)
5979 {
5980         enum i40e_status_code status;
5981         u32 max_bw_addr, min_bw_addr;
5982
5983         /* Calculate the address of the min/max bw registers */
5984         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5985                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5986                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5987         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5988                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5989                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5990
5991         /* Read the bandwidths from alt ram */
5992         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5993                                         min_bw_addr, min_bw);
5994
5995         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5996                 *min_valid = true;
5997         else
5998                 *min_valid = false;
5999
6000         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6001                 *max_valid = true;
6002         else
6003                 *max_valid = false;
6004
6005         return status;
6006 }
6007
6008 /**
6009  * i40e_aq_configure_partition_bw
6010  * @hw: pointer to the hardware structure
6011  * @bw_data: Buffer holding valid pfs and bw limits
6012  * @cmd_details: pointer to command details
6013  *
6014  * Configure partitions guaranteed/max bw
6015  **/
6016 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6017                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6018                         struct i40e_asq_cmd_details *cmd_details)
6019 {
6020         enum i40e_status_code status;
6021         struct i40e_aq_desc desc;
6022         u16 bwd_size = sizeof(*bw_data);
6023
6024         i40e_fill_default_direct_cmd_desc(&desc,
6025                                 i40e_aqc_opc_configure_partition_bw);
6026
6027         /* Indirect command */
6028         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6029         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6030
6031         if (bwd_size > I40E_AQ_LARGE_BUF)
6032                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6033
6034         desc.datalen = CPU_TO_LE16(bwd_size);
6035
6036         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6037
6038         return status;
6039 }
6040
6041 /**
6042  * i40e_read_phy_register
6043  * @hw: pointer to the HW structure
6044  * @page: registers page number
6045  * @reg: register address in the page
6046  * @phy_adr: PHY address on MDIO interface
6047  * @value: PHY register value
6048  *
6049  * Reads specified PHY register value
6050  **/
6051 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6052                                              u8 page, u16 reg, u8 phy_addr,
6053                                              u16 *value)
6054 {
6055         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6056         u32 command  = 0;
6057         u16 retry = 1000;
6058         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6059
6060         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6061                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6062                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6063                   (I40E_MDIO_OPCODE_ADDRESS) |
6064                   (I40E_MDIO_STCODE) |
6065                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6066                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6067         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6068         do {
6069                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6070                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6071                         status = I40E_SUCCESS;
6072                         break;
6073                 }
6074                 i40e_usec_delay(10);
6075                 retry--;
6076         } while (retry);
6077
6078         if (status) {
6079                 i40e_debug(hw, I40E_DEBUG_PHY,
6080                            "PHY: Can't write command to external PHY.\n");
6081                 goto phy_read_end;
6082         }
6083
6084         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6085                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6086                   (I40E_MDIO_OPCODE_READ) |
6087                   (I40E_MDIO_STCODE) |
6088                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6089                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6090         status = I40E_ERR_TIMEOUT;
6091         retry = 1000;
6092         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6093         do {
6094                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6095                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6096                         status = I40E_SUCCESS;
6097                         break;
6098                 }
6099                 i40e_usec_delay(10);
6100                 retry--;
6101         } while (retry);
6102
6103         if (!status) {
6104                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6105                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6106                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6107         } else {
6108                 i40e_debug(hw, I40E_DEBUG_PHY,
6109                            "PHY: Can't read register value from external PHY.\n");
6110         }
6111
6112 phy_read_end:
6113         return status;
6114 }
6115
6116 /**
6117  * i40e_write_phy_register
6118  * @hw: pointer to the HW structure
6119  * @page: registers page number
6120  * @reg: register address in the page
6121  * @phy_adr: PHY address on MDIO interface
6122  * @value: PHY register value
6123  *
6124  * Writes value to specified PHY register
6125  **/
6126 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6127                                               u8 page, u16 reg, u8 phy_addr,
6128                                               u16 value)
6129 {
6130         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6131         u32 command  = 0;
6132         u16 retry = 1000;
6133         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6134
6135         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6136                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6137                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6138                   (I40E_MDIO_OPCODE_ADDRESS) |
6139                   (I40E_MDIO_STCODE) |
6140                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6141                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6142         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6143         do {
6144                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6145                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6146                         status = I40E_SUCCESS;
6147                         break;
6148                 }
6149                 i40e_usec_delay(10);
6150                 retry--;
6151         } while (retry);
6152         if (status) {
6153                 i40e_debug(hw, I40E_DEBUG_PHY,
6154                            "PHY: Can't write command to external PHY.\n");
6155                 goto phy_write_end;
6156         }
6157
6158         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6159         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6160
6161         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6162                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6163                   (I40E_MDIO_OPCODE_WRITE) |
6164                   (I40E_MDIO_STCODE) |
6165                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6166                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6167         status = I40E_ERR_TIMEOUT;
6168         retry = 1000;
6169         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6170         do {
6171                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6172                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6173                         status = I40E_SUCCESS;
6174                         break;
6175                 }
6176                 i40e_usec_delay(10);
6177                 retry--;
6178         } while (retry);
6179
6180 phy_write_end:
6181         return status;
6182 }
6183
6184 /**
6185  * i40e_get_phy_address
6186  * @hw: pointer to the HW structure
6187  * @dev_num: PHY port num that address we want
6188  * @phy_addr: Returned PHY address
6189  *
6190  * Gets PHY address for current port
6191  **/
6192 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6193 {
6194         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6195         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6196
6197         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6198 }
6199
6200 /**
6201  * i40e_blink_phy_led
6202  * @hw: pointer to the HW structure
6203  * @time: time how long led will blinks in secs
6204  * @interval: gap between LED on and off in msecs
6205  *
6206  * Blinks PHY link LED
6207  **/
6208 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6209                                               u32 time, u32 interval)
6210 {
6211         enum i40e_status_code status = I40E_SUCCESS;
6212         u32 i;
6213         u16 led_ctl = 0;
6214         u16 gpio_led_port;
6215         u16 led_reg;
6216         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6217         u8 phy_addr = 0;
6218         u8 port_num;
6219
6220         i = rd32(hw, I40E_PFGEN_PORTNUM);
6221         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6222         phy_addr = i40e_get_phy_address(hw, port_num);
6223
6224         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6225              led_addr++) {
6226                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6227                                                 led_addr, phy_addr, &led_reg);
6228                 if (status)
6229                         goto phy_blinking_end;
6230                 led_ctl = led_reg;
6231                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6232                         led_reg = 0;
6233                         status = i40e_write_phy_register(hw,
6234                                                          I40E_PHY_COM_REG_PAGE,
6235                                                          led_addr, phy_addr,
6236                                                          led_reg);
6237                         if (status)
6238                                 goto phy_blinking_end;
6239                         break;
6240                 }
6241         }
6242
6243         if (time > 0 && interval > 0) {
6244                 for (i = 0; i < time * 1000; i += interval) {
6245                         status = i40e_read_phy_register(hw,
6246                                                         I40E_PHY_COM_REG_PAGE,
6247                                                         led_addr, phy_addr,
6248                                                         &led_reg);
6249                         if (status)
6250                                 goto restore_config;
6251                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6252                                 led_reg = 0;
6253                         else
6254                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6255                         status = i40e_write_phy_register(hw,
6256                                                          I40E_PHY_COM_REG_PAGE,
6257                                                          led_addr, phy_addr,
6258                                                          led_reg);
6259                         if (status)
6260                                 goto restore_config;
6261                         i40e_msec_delay(interval);
6262                 }
6263         }
6264
6265 restore_config:
6266         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6267                                          phy_addr, led_ctl);
6268
6269 phy_blinking_end:
6270         return status;
6271 }
6272
6273 /**
6274  * i40e_led_get_phy - return current on/off mode
6275  * @hw: pointer to the hw struct
6276  * @led_addr: address of led register to use
6277  * @val: original value of register to use
6278  *
6279  **/
6280 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6281                                        u16 *val)
6282 {
6283         enum i40e_status_code status = I40E_SUCCESS;
6284         u16 gpio_led_port;
6285         u8 phy_addr = 0;
6286         u16 reg_val;
6287         u16 temp_addr;
6288         u8 port_num;
6289         u32 i;
6290
6291         temp_addr = I40E_PHY_LED_PROV_REG_1;
6292         i = rd32(hw, I40E_PFGEN_PORTNUM);
6293         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6294         phy_addr = i40e_get_phy_address(hw, port_num);
6295
6296         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6297              temp_addr++) {
6298                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6299                                                 temp_addr, phy_addr, &reg_val);
6300                 if (status)
6301                         return status;
6302                 *val = reg_val;
6303                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6304                         *led_addr = temp_addr;
6305                         break;
6306                 }
6307         }
6308         return status;
6309 }
6310
6311 /**
6312  * i40e_led_set_phy
6313  * @hw: pointer to the HW structure
6314  * @on: true or false
6315  * @mode: original val plus bit for set or ignore
6316  * Set led's on or off when controlled by the PHY
6317  *
6318  **/
6319 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6320                                        u16 led_addr, u32 mode)
6321 {
6322         enum i40e_status_code status = I40E_SUCCESS;
6323         u16 led_ctl = 0;
6324         u16 led_reg = 0;
6325         u8 phy_addr = 0;
6326         u8 port_num;
6327         u32 i;
6328
6329         i = rd32(hw, I40E_PFGEN_PORTNUM);
6330         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6331         phy_addr = i40e_get_phy_address(hw, port_num);
6332
6333         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6334                                         phy_addr, &led_reg);
6335         if (status)
6336                 return status;
6337         led_ctl = led_reg;
6338         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6339                 led_reg = 0;
6340                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6341                                                  led_addr, phy_addr, led_reg);
6342                 if (status)
6343                         return status;
6344         }
6345         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6346                                         led_addr, phy_addr, &led_reg);
6347         if (status)
6348                 goto restore_config;
6349         if (on)
6350                 led_reg = I40E_PHY_LED_MANUAL_ON;
6351         else
6352                 led_reg = 0;
6353         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6354                                          led_addr, phy_addr, led_reg);
6355         if (status)
6356                 goto restore_config;
6357         if (mode & I40E_PHY_LED_MODE_ORIG) {
6358                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6359                 status = i40e_write_phy_register(hw,
6360                                                  I40E_PHY_COM_REG_PAGE,
6361                                                  led_addr, phy_addr, led_ctl);
6362         }
6363         return status;
6364 restore_config:
6365         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6366                                          phy_addr, led_ctl);
6367         return status;
6368 }
6369 #endif /* PF_DRIVER */
6370
6371 /**
6372  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6373  * @hw: pointer to the hw struct
6374  * @reg_addr: register address
6375  * @reg_val: ptr to register value
6376  * @cmd_details: pointer to command details structure or NULL
6377  *
6378  * Use the firmware to read the Rx control register,
6379  * especially useful if the Rx unit is under heavy pressure
6380  **/
6381 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6382                                 u32 reg_addr, u32 *reg_val,
6383                                 struct i40e_asq_cmd_details *cmd_details)
6384 {
6385         struct i40e_aq_desc desc;
6386         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6387                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6388         enum i40e_status_code status;
6389
6390         if (reg_val == NULL)
6391                 return I40E_ERR_PARAM;
6392
6393         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6394
6395         cmd_resp->address = CPU_TO_LE32(reg_addr);
6396
6397         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6398
6399         if (status == I40E_SUCCESS)
6400                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6401
6402         return status;
6403 }
6404
6405 /**
6406  * i40e_read_rx_ctl - read from an Rx control register
6407  * @hw: pointer to the hw struct
6408  * @reg_addr: register address
6409  **/
6410 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6411 {
6412         enum i40e_status_code status = I40E_SUCCESS;
6413         bool use_register;
6414         int retry = 5;
6415         u32 val = 0;
6416
6417         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6418         if (!use_register) {
6419 do_retry:
6420                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6421                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6422                         i40e_msec_delay(1);
6423                         retry--;
6424                         goto do_retry;
6425                 }
6426         }
6427
6428         /* if the AQ access failed, try the old-fashioned way */
6429         if (status || use_register)
6430                 val = rd32(hw, reg_addr);
6431
6432         return val;
6433 }
6434
6435 /**
6436  * i40e_aq_rx_ctl_write_register
6437  * @hw: pointer to the hw struct
6438  * @reg_addr: register address
6439  * @reg_val: register value
6440  * @cmd_details: pointer to command details structure or NULL
6441  *
6442  * Use the firmware to write to an Rx control register,
6443  * especially useful if the Rx unit is under heavy pressure
6444  **/
6445 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6446                                 u32 reg_addr, u32 reg_val,
6447                                 struct i40e_asq_cmd_details *cmd_details)
6448 {
6449         struct i40e_aq_desc desc;
6450         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6451                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6452         enum i40e_status_code status;
6453
6454         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6455
6456         cmd->address = CPU_TO_LE32(reg_addr);
6457         cmd->value = CPU_TO_LE32(reg_val);
6458
6459         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6460
6461         return status;
6462 }
6463
6464 /**
6465  * i40e_write_rx_ctl - write to an Rx control register
6466  * @hw: pointer to the hw struct
6467  * @reg_addr: register address
6468  * @reg_val: register value
6469  **/
6470 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6471 {
6472         enum i40e_status_code status = I40E_SUCCESS;
6473         bool use_register;
6474         int retry = 5;
6475
6476         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6477         if (!use_register) {
6478 do_retry:
6479                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6480                                                        reg_val, NULL);
6481                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6482                         i40e_msec_delay(1);
6483                         retry--;
6484                         goto do_retry;
6485                 }
6486         }
6487
6488         /* if the AQ access failed, try the old-fashioned way */
6489         if (status || use_register)
6490                 wr32(hw, reg_addr, reg_val);
6491 }
6492 #ifdef VF_DRIVER
6493
6494 /**
6495  * i40e_aq_send_msg_to_pf
6496  * @hw: pointer to the hardware structure
6497  * @v_opcode: opcodes for VF-PF communication
6498  * @v_retval: return error code
6499  * @msg: pointer to the msg buffer
6500  * @msglen: msg length
6501  * @cmd_details: pointer to command details
6502  *
6503  * Send message to PF driver using admin queue. By default, this message
6504  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6505  * completion before returning.
6506  **/
6507 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6508                                 enum i40e_virtchnl_ops v_opcode,
6509                                 enum i40e_status_code v_retval,
6510                                 u8 *msg, u16 msglen,
6511                                 struct i40e_asq_cmd_details *cmd_details)
6512 {
6513         struct i40e_aq_desc desc;
6514         struct i40e_asq_cmd_details details;
6515         enum i40e_status_code status;
6516
6517         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6518         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6519         desc.cookie_high = CPU_TO_LE32(v_opcode);
6520         desc.cookie_low = CPU_TO_LE32(v_retval);
6521         if (msglen) {
6522                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6523                                                 | I40E_AQ_FLAG_RD));
6524                 if (msglen > I40E_AQ_LARGE_BUF)
6525                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6526                 desc.datalen = CPU_TO_LE16(msglen);
6527         }
6528         if (!cmd_details) {
6529                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6530                 details.async = true;
6531                 cmd_details = &details;
6532         }
6533         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6534                                        msglen, cmd_details);
6535         return status;
6536 }
6537
6538 /**
6539  * i40e_vf_parse_hw_config
6540  * @hw: pointer to the hardware structure
6541  * @msg: pointer to the virtual channel VF resource structure
6542  *
6543  * Given a VF resource message from the PF, populate the hw struct
6544  * with appropriate information.
6545  **/
6546 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6547                              struct i40e_virtchnl_vf_resource *msg)
6548 {
6549         struct i40e_virtchnl_vsi_resource *vsi_res;
6550         int i;
6551
6552         vsi_res = &msg->vsi_res[0];
6553
6554         hw->dev_caps.num_vsis = msg->num_vsis;
6555         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6556         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6557         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6558         hw->dev_caps.dcb = msg->vf_offload_flags &
6559                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6560         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6561                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6562         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6563                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6564         for (i = 0; i < msg->num_vsis; i++) {
6565                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6566                         i40e_memcpy(hw->mac.perm_addr,
6567                                     vsi_res->default_mac_addr,
6568                                     I40E_ETH_LENGTH_OF_ADDRESS,
6569                                     I40E_NONDMA_TO_NONDMA);
6570                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6571                                     I40E_ETH_LENGTH_OF_ADDRESS,
6572                                     I40E_NONDMA_TO_NONDMA);
6573                 }
6574                 vsi_res++;
6575         }
6576 }
6577
6578 /**
6579  * i40e_vf_reset
6580  * @hw: pointer to the hardware structure
6581  *
6582  * Send a VF_RESET message to the PF. Does not wait for response from PF
6583  * as none will be forthcoming. Immediately after calling this function,
6584  * the admin queue should be shut down and (optionally) reinitialized.
6585  **/
6586 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6587 {
6588         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6589                                       I40E_SUCCESS, NULL, 0, NULL);
6590 }
6591 #endif /* VF_DRIVER */
6592 #ifdef X722_SUPPORT
6593
6594 /**
6595  * i40e_aq_set_arp_proxy_config
6596  * @hw: pointer to the HW structure
6597  * @proxy_config - pointer to proxy config command table struct
6598  * @cmd_details: pointer to command details
6599  *
6600  * Set ARP offload parameters from pre-populated
6601  * i40e_aqc_arp_proxy_data struct
6602  **/
6603 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6604                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6605                                 struct i40e_asq_cmd_details *cmd_details)
6606 {
6607         struct i40e_aq_desc desc;
6608         enum i40e_status_code status;
6609
6610         if (!proxy_config)
6611                 return I40E_ERR_PARAM;
6612
6613         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6614
6615         desc.params.external.addr_high =
6616                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6617         desc.params.external.addr_low =
6618                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6619
6620         status = i40e_asq_send_command(hw, &desc, proxy_config,
6621                                        sizeof(struct i40e_aqc_arp_proxy_data),
6622                                        cmd_details);
6623
6624         return status;
6625 }
6626
6627 /**
6628  * i40e_aq_opc_set_ns_proxy_table_entry
6629  * @hw: pointer to the HW structure
6630  * @ns_proxy_table_entry: pointer to NS table entry command struct
6631  * @cmd_details: pointer to command details
6632  *
6633  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6634  * from pre-populated i40e_aqc_ns_proxy_data struct
6635  **/
6636 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6637                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6638                         struct i40e_asq_cmd_details *cmd_details)
6639 {
6640         struct i40e_aq_desc desc;
6641         enum i40e_status_code status;
6642
6643         if (!ns_proxy_table_entry)
6644                 return I40E_ERR_PARAM;
6645
6646         i40e_fill_default_direct_cmd_desc(&desc,
6647                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6648
6649         desc.params.external.addr_high =
6650                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6651         desc.params.external.addr_low =
6652                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6653
6654         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6655                                        sizeof(struct i40e_aqc_ns_proxy_data),
6656                                        cmd_details);
6657
6658         return status;
6659 }
6660
6661 /**
6662  * i40e_aq_set_clear_wol_filter
6663  * @hw: pointer to the hw struct
6664  * @filter_index: index of filter to modify (0-7)
6665  * @filter: buffer containing filter to be set
6666  * @set_filter: true to set filter, false to clear filter
6667  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6668  *              if false, pass through packets may cause wake-up
6669  * @filter_valid: true if filter action is valid
6670  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6671  * @cmd_details: pointer to command details structure or NULL
6672  *
6673  * Set or clear WoL filter for port attached to the PF
6674  **/
6675 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6676                                 u8 filter_index,
6677                                 struct i40e_aqc_set_wol_filter_data *filter,
6678                                 bool set_filter, bool no_wol_tco,
6679                                 bool filter_valid, bool no_wol_tco_valid,
6680                                 struct i40e_asq_cmd_details *cmd_details)
6681 {
6682         struct i40e_aq_desc desc;
6683         struct i40e_aqc_set_wol_filter *cmd =
6684                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6685         enum i40e_status_code status;
6686         u16 cmd_flags = 0;
6687         u16 valid_flags = 0;
6688         u16 buff_len = 0;
6689
6690         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6691
6692         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6693                 return  I40E_ERR_PARAM;
6694         cmd->filter_index = CPU_TO_LE16(filter_index);
6695
6696         if (set_filter) {
6697                 if (!filter)
6698                         return  I40E_ERR_PARAM;
6699                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6700                 buff_len = sizeof(*filter);
6701         }
6702         if (no_wol_tco)
6703                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6704         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6705
6706         if (filter_valid)
6707                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6708         if (no_wol_tco_valid)
6709                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6710         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6711
6712         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6713         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6714
6715         status = i40e_asq_send_command(hw, &desc, filter,
6716                                        buff_len, cmd_details);
6717
6718         return status;
6719 }
6720
6721 /**
6722  * i40e_aq_get_wake_event_reason
6723  * @hw: pointer to the hw struct
6724  * @wake_reason: return value, index of matching filter
6725  * @cmd_details: pointer to command details structure or NULL
6726  *
6727  * Get information for the reason of a Wake Up event
6728  **/
6729 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6730                                 u16 *wake_reason,
6731                                 struct i40e_asq_cmd_details *cmd_details)
6732 {
6733         struct i40e_aq_desc desc;
6734         struct i40e_aqc_get_wake_reason_completion *resp =
6735                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6736         enum i40e_status_code status;
6737
6738         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6739
6740         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6741
6742         if (status == I40E_SUCCESS)
6743                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6744
6745         return status;
6746 }
6747
6748 #endif /* X722_SUPPORT */