drivers/net/i40e/base/i40e_common.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "i40e_type.h"
  35 #include "i40e_adminq.h"
  36 #include "i40e_prototype.h"
  37 #include "i40e_virtchnl.h"
  38
  39
  40 /**
  41  * i40e_set_mac_type - Sets MAC type
  42  * @hw: pointer to the HW structure
  43  *
  44  * This function sets the mac type of the adapter based on the
  45  * vendor ID and device ID stored in the hw structure.
  46  **/
  47 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  49 #else
  50 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  51 #endif
  52 {
  53         enum i40e_status_code status = I40E_SUCCESS;
  54
  55         DEBUGFUNC("i40e_set_mac_type\n");
  56
  57         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  58                 switch (hw->device_id) {
  59                 case I40E_DEV_ID_SFP_XL710:
  60                 case I40E_DEV_ID_QEMU:
  61                 case I40E_DEV_ID_KX_B:
  62                 case I40E_DEV_ID_KX_C:
  63                 case I40E_DEV_ID_QSFP_A:
  64                 case I40E_DEV_ID_QSFP_B:
  65                 case I40E_DEV_ID_QSFP_C:
  66                 case I40E_DEV_ID_10G_BASE_T:
  67                 case I40E_DEV_ID_10G_BASE_T4:
  68                 case I40E_DEV_ID_20G_KR2:
  69                 case I40E_DEV_ID_20G_KR2_A:
  70                         hw->mac.type = I40E_MAC_XL710;
  71                         break;
  72 #ifdef X722_SUPPORT
  73 #ifdef X722_A0_SUPPORT
  74                 case I40E_DEV_ID_X722_A0:
  75 #endif
  76                 case I40E_DEV_ID_KX_X722:
  77                 case I40E_DEV_ID_QSFP_X722:
  78                 case I40E_DEV_ID_SFP_X722:
  79                 case I40E_DEV_ID_1G_BASE_T_X722:
  80                 case I40E_DEV_ID_10G_BASE_T_X722:
  81                         hw->mac.type = I40E_MAC_X722;
  82                         break;
  83 #endif
  84 #ifdef X722_SUPPORT
  85 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  86                 case I40E_DEV_ID_X722_VF:
  87                 case I40E_DEV_ID_X722_VF_HV:
  88 #ifdef X722_A0_SUPPORT
  89                 case I40E_DEV_ID_X722_A0_VF:
  90 #endif
  91                         hw->mac.type = I40E_MAC_X722_VF;
  92                         break;
  93 #endif /* INTEGRATED_VF || VF_DRIVER */
  94 #endif /* X722_SUPPORT */
  95 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  96                 case I40E_DEV_ID_VF:
  97                 case I40E_DEV_ID_VF_HV:
  98                         hw->mac.type = I40E_MAC_VF;
  99                         break;
 100 #endif
 101                 default:
 102                         hw->mac.type = I40E_MAC_GENERIC;
 103                         break;
 104                 }
 105         } else {
 106                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
 107         }
 108
 109         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
 110                   hw->mac.type, status);
 111         return status;
 112 }
 113
 114 #ifndef I40E_NDIS_SUPPORT
 115 /**
 116  * i40e_aq_str - convert AQ err code to a string
 117  * @hw: pointer to the HW structure
 118  * @aq_err: the AQ error code to convert
 119  **/
 120 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
 121 {
 122         switch (aq_err) {
 123         case I40E_AQ_RC_OK:
 124                 return "OK";
 125         case I40E_AQ_RC_EPERM:
 126                 return "I40E_AQ_RC_EPERM";
 127         case I40E_AQ_RC_ENOENT:
 128                 return "I40E_AQ_RC_ENOENT";
 129         case I40E_AQ_RC_ESRCH:
 130                 return "I40E_AQ_RC_ESRCH";
 131         case I40E_AQ_RC_EINTR:
 132                 return "I40E_AQ_RC_EINTR";
 133         case I40E_AQ_RC_EIO:
 134                 return "I40E_AQ_RC_EIO";
 135         case I40E_AQ_RC_ENXIO:
 136                 return "I40E_AQ_RC_ENXIO";
 137         case I40E_AQ_RC_E2BIG:
 138                 return "I40E_AQ_RC_E2BIG";
 139         case I40E_AQ_RC_EAGAIN:
 140                 return "I40E_AQ_RC_EAGAIN";
 141         case I40E_AQ_RC_ENOMEM:
 142                 return "I40E_AQ_RC_ENOMEM";
 143         case I40E_AQ_RC_EACCES:
 144                 return "I40E_AQ_RC_EACCES";
 145         case I40E_AQ_RC_EFAULT:
 146                 return "I40E_AQ_RC_EFAULT";
 147         case I40E_AQ_RC_EBUSY:
 148                 return "I40E_AQ_RC_EBUSY";
 149         case I40E_AQ_RC_EEXIST:
 150                 return "I40E_AQ_RC_EEXIST";
 151         case I40E_AQ_RC_EINVAL:
 152                 return "I40E_AQ_RC_EINVAL";
 153         case I40E_AQ_RC_ENOTTY:
 154                 return "I40E_AQ_RC_ENOTTY";
 155         case I40E_AQ_RC_ENOSPC:
 156                 return "I40E_AQ_RC_ENOSPC";
 157         case I40E_AQ_RC_ENOSYS:
 158                 return "I40E_AQ_RC_ENOSYS";
 159         case I40E_AQ_RC_ERANGE:
 160                 return "I40E_AQ_RC_ERANGE";
 161         case I40E_AQ_RC_EFLUSHED:
 162                 return "I40E_AQ_RC_EFLUSHED";
 163         case I40E_AQ_RC_BAD_ADDR:
 164                 return "I40E_AQ_RC_BAD_ADDR";
 165         case I40E_AQ_RC_EMODE:
 166                 return "I40E_AQ_RC_EMODE";
 167         case I40E_AQ_RC_EFBIG:
 168                 return "I40E_AQ_RC_EFBIG";
 169         }
 170
 171         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 172         return hw->err_str;
 173 }
 174
 175 /**
 176  * i40e_stat_str - convert status err code to a string
 177  * @hw: pointer to the HW structure
 178  * @stat_err: the status error code to convert
 179  **/
 180 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 181 {
 182         switch (stat_err) {
 183         case I40E_SUCCESS:
 184                 return "OK";
 185         case I40E_ERR_NVM:
 186                 return "I40E_ERR_NVM";
 187         case I40E_ERR_NVM_CHECKSUM:
 188                 return "I40E_ERR_NVM_CHECKSUM";
 189         case I40E_ERR_PHY:
 190                 return "I40E_ERR_PHY";
 191         case I40E_ERR_CONFIG:
 192                 return "I40E_ERR_CONFIG";
 193         case I40E_ERR_PARAM:
 194                 return "I40E_ERR_PARAM";
 195         case I40E_ERR_MAC_TYPE:
 196                 return "I40E_ERR_MAC_TYPE";
 197         case I40E_ERR_UNKNOWN_PHY:
 198                 return "I40E_ERR_UNKNOWN_PHY";
 199         case I40E_ERR_LINK_SETUP:
 200                 return "I40E_ERR_LINK_SETUP";
 201         case I40E_ERR_ADAPTER_STOPPED:
 202                 return "I40E_ERR_ADAPTER_STOPPED";
 203         case I40E_ERR_INVALID_MAC_ADDR:
 204                 return "I40E_ERR_INVALID_MAC_ADDR";
 205         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 206                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 207         case I40E_ERR_MASTER_REQUESTS_PENDING:
 208                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 209         case I40E_ERR_INVALID_LINK_SETTINGS:
 210                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 211         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 212                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 213         case I40E_ERR_RESET_FAILED:
 214                 return "I40E_ERR_RESET_FAILED";
 215         case I40E_ERR_SWFW_SYNC:
 216                 return "I40E_ERR_SWFW_SYNC";
 217         case I40E_ERR_NO_AVAILABLE_VSI:
 218                 return "I40E_ERR_NO_AVAILABLE_VSI";
 219         case I40E_ERR_NO_MEMORY:
 220                 return "I40E_ERR_NO_MEMORY";
 221         case I40E_ERR_BAD_PTR:
 222                 return "I40E_ERR_BAD_PTR";
 223         case I40E_ERR_RING_FULL:
 224                 return "I40E_ERR_RING_FULL";
 225         case I40E_ERR_INVALID_PD_ID:
 226                 return "I40E_ERR_INVALID_PD_ID";
 227         case I40E_ERR_INVALID_QP_ID:
 228                 return "I40E_ERR_INVALID_QP_ID";
 229         case I40E_ERR_INVALID_CQ_ID:
 230                 return "I40E_ERR_INVALID_CQ_ID";
 231         case I40E_ERR_INVALID_CEQ_ID:
 232                 return "I40E_ERR_INVALID_CEQ_ID";
 233         case I40E_ERR_INVALID_AEQ_ID:
 234                 return "I40E_ERR_INVALID_AEQ_ID";
 235         case I40E_ERR_INVALID_SIZE:
 236                 return "I40E_ERR_INVALID_SIZE";
 237         case I40E_ERR_INVALID_ARP_INDEX:
 238                 return "I40E_ERR_INVALID_ARP_INDEX";
 239         case I40E_ERR_INVALID_FPM_FUNC_ID:
 240                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 241         case I40E_ERR_QP_INVALID_MSG_SIZE:
 242                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 243         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 244                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 245         case I40E_ERR_INVALID_FRAG_COUNT:
 246                 return "I40E_ERR_INVALID_FRAG_COUNT";
 247         case I40E_ERR_QUEUE_EMPTY:
 248                 return "I40E_ERR_QUEUE_EMPTY";
 249         case I40E_ERR_INVALID_ALIGNMENT:
 250                 return "I40E_ERR_INVALID_ALIGNMENT";
 251         case I40E_ERR_FLUSHED_QUEUE:
 252                 return "I40E_ERR_FLUSHED_QUEUE";
 253         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 254                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 255         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 256                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 257         case I40E_ERR_TIMEOUT:
 258                 return "I40E_ERR_TIMEOUT";
 259         case I40E_ERR_OPCODE_MISMATCH:
 260                 return "I40E_ERR_OPCODE_MISMATCH";
 261         case I40E_ERR_CQP_COMPL_ERROR:
 262                 return "I40E_ERR_CQP_COMPL_ERROR";
 263         case I40E_ERR_INVALID_VF_ID:
 264                 return "I40E_ERR_INVALID_VF_ID";
 265         case I40E_ERR_INVALID_HMCFN_ID:
 266                 return "I40E_ERR_INVALID_HMCFN_ID";
 267         case I40E_ERR_BACKING_PAGE_ERROR:
 268                 return "I40E_ERR_BACKING_PAGE_ERROR";
 269         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 270                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 271         case I40E_ERR_INVALID_PBLE_INDEX:
 272                 return "I40E_ERR_INVALID_PBLE_INDEX";
 273         case I40E_ERR_INVALID_SD_INDEX:
 274                 return "I40E_ERR_INVALID_SD_INDEX";
 275         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 276                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 277         case I40E_ERR_INVALID_SD_TYPE:
 278                 return "I40E_ERR_INVALID_SD_TYPE";
 279         case I40E_ERR_MEMCPY_FAILED:
 280                 return "I40E_ERR_MEMCPY_FAILED";
 281         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 282                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 283         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 284                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 285         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 286                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 287         case I40E_ERR_SRQ_ENABLED:
 288                 return "I40E_ERR_SRQ_ENABLED";
 289         case I40E_ERR_ADMIN_QUEUE_ERROR:
 290                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 291         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 292                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 293         case I40E_ERR_BUF_TOO_SHORT:
 294                 return "I40E_ERR_BUF_TOO_SHORT";
 295         case I40E_ERR_ADMIN_QUEUE_FULL:
 296                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 297         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 298                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 299         case I40E_ERR_BAD_IWARP_CQE:
 300                 return "I40E_ERR_BAD_IWARP_CQE";
 301         case I40E_ERR_NVM_BLANK_MODE:
 302                 return "I40E_ERR_NVM_BLANK_MODE";
 303         case I40E_ERR_NOT_IMPLEMENTED:
 304                 return "I40E_ERR_NOT_IMPLEMENTED";
 305         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 306                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 307         case I40E_ERR_DIAG_TEST_FAILED:
 308                 return "I40E_ERR_DIAG_TEST_FAILED";
 309         case I40E_ERR_NOT_READY:
 310                 return "I40E_ERR_NOT_READY";
 311         case I40E_NOT_SUPPORTED:
 312                 return "I40E_NOT_SUPPORTED";
 313         case I40E_ERR_FIRMWARE_API_VERSION:
 314                 return "I40E_ERR_FIRMWARE_API_VERSION";
 315         }
 316
 317         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 318         return hw->err_str;
 319 }
 320
 321 #endif /* I40E_NDIS_SUPPORT */
 322 /**
 323  * i40e_debug_aq
 324  * @hw: debug mask related to admin queue
 325  * @mask: debug mask
 326  * @desc: pointer to admin queue descriptor
 327  * @buffer: pointer to command buffer
 328  * @buf_len: max length of buffer
 329  *
 330  * Dumps debug log about adminq command with descriptor contents.
 331  **/
 332 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 333                    void *buffer, u16 buf_len)
 334 {
 335         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 336         u16 len = LE16_TO_CPU(aq_desc->datalen);
 337         u8 *buf = (u8 *)buffer;
 338         u16 i = 0;
 339
 340         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 341                 return;
 342
 343         i40e_debug(hw, mask,
 344                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 345                    LE16_TO_CPU(aq_desc->opcode),
 346                    LE16_TO_CPU(aq_desc->flags),
 347                    LE16_TO_CPU(aq_desc->datalen),
 348                    LE16_TO_CPU(aq_desc->retval));
 349         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 350                    LE32_TO_CPU(aq_desc->cookie_high),
 351                    LE32_TO_CPU(aq_desc->cookie_low));
 352         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 353                    LE32_TO_CPU(aq_desc->params.internal.param0),
 354                    LE32_TO_CPU(aq_desc->params.internal.param1));
 355         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 356                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 357                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 358
 359         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 360                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 361                 if (buf_len < len)
 362                         len = buf_len;
 363                 /* write the full 16-byte chunks */
 364                 for (i = 0; i < (len - 16); i += 16)
 365                         i40e_debug(hw, mask,
 366                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 367                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 368                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 369                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 370                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 371                 /* the most we could have left is 16 bytes, pad with zeros */
 372                 if (i < len) {
 373                         char d_buf[16];
 374                         int j;
 375
 376                         memset(d_buf, 0, sizeof(d_buf));
 377                         for (j = 0; i < len; j++, i++)
 378                                 d_buf[j] = buf[i];
 379                         i40e_debug(hw, mask,
 380                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 381                                    i, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 382                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 383                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 384                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 385                 }
 386         }
 387 }
 388
 389 /**
 390  * i40e_check_asq_alive
 391  * @hw: pointer to the hw struct
 392  *
 393  * Returns true if Queue is enabled else false.
 394  **/
 395 bool i40e_check_asq_alive(struct i40e_hw *hw)
 396 {
 397         if (hw->aq.asq.len)
 398 #ifdef PF_DRIVER
 399 #ifdef INTEGRATED_VF
 400                 if (!i40e_is_vf(hw))
 401                         return !!(rd32(hw, hw->aq.asq.len) &
 402                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 403 #else
 404                 return !!(rd32(hw, hw->aq.asq.len) &
 405                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 406 #endif /* INTEGRATED_VF */
 407 #endif /* PF_DRIVER */
 408 #ifdef VF_DRIVER
 409 #ifdef INTEGRATED_VF
 410                 if (i40e_is_vf(hw))
 411                         return !!(rd32(hw, hw->aq.asq.len) &
 412                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 413 #else
 414                 return !!(rd32(hw, hw->aq.asq.len) &
 415                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 416 #endif /* INTEGRATED_VF */
 417 #endif /* VF_DRIVER */
 418         return false;
 419 }
 420
 421 /**
 422  * i40e_aq_queue_shutdown
 423  * @hw: pointer to the hw struct
 424  * @unloading: is the driver unloading itself
 425  *
 426  * Tell the Firmware that we're shutting down the AdminQ and whether
 427  * or not the driver is unloading as well.
 428  **/
 429 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 430                                              bool unloading)
 431 {
 432         struct i40e_aq_desc desc;
 433         struct i40e_aqc_queue_shutdown *cmd =
 434                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 435         enum i40e_status_code status;
 436
 437         i40e_fill_default_direct_cmd_desc(&desc,
 438                                           i40e_aqc_opc_queue_shutdown);
 439
 440         if (unloading)
 441                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 442         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 443
 444         return status;
 445 }
 446 #ifdef X722_SUPPORT
 447
 448 /**
 449  * i40e_aq_get_set_rss_lut
 450  * @hw: pointer to the hardware structure
 451  * @vsi_id: vsi fw index
 452  * @pf_lut: for PF table set true, for VSI table set false
 453  * @lut: pointer to the lut buffer provided by the caller
 454  * @lut_size: size of the lut buffer
 455  * @set: set true to set the table, false to get the table
 456  *
 457  * Internal function to get or set RSS look up table
 458  **/
 459 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 460                                                      u16 vsi_id, bool pf_lut,
 461                                                      u8 *lut, u16 lut_size,
 462                                                      bool set)
 463 {
 464         enum i40e_status_code status;
 465         struct i40e_aq_desc desc;
 466         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 467                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 468
 469         if (set)
 470                 i40e_fill_default_direct_cmd_desc(&desc,
 471                                                   i40e_aqc_opc_set_rss_lut);
 472         else
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_get_rss_lut);
 475
 476         /* Indirect command */
 477         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 478         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 479
 480         cmd_resp->vsi_id =
 481                         CPU_TO_LE16((u16)((vsi_id <<
 482                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 483                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 484         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 485
 486         if (pf_lut)
 487                 cmd_resp->flags |= CPU_TO_LE16((u16)
 488                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 489                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 490                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 491         else
 492                 cmd_resp->flags |= CPU_TO_LE16((u16)
 493                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 494                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 495                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 496
 497         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 498
 499         return status;
 500 }
 501
 502 /**
 503  * i40e_aq_get_rss_lut
 504  * @hw: pointer to the hardware structure
 505  * @vsi_id: vsi fw index
 506  * @pf_lut: for PF table set true, for VSI table set false
 507  * @lut: pointer to the lut buffer provided by the caller
 508  * @lut_size: size of the lut buffer
 509  *
 510  * get the RSS lookup table, PF or VSI type
 511  **/
 512 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 513                                           bool pf_lut, u8 *lut, u16 lut_size)
 514 {
 515         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 516                                        false);
 517 }
 518
 519 /**
 520  * i40e_aq_set_rss_lut
 521  * @hw: pointer to the hardware structure
 522  * @vsi_id: vsi fw index
 523  * @pf_lut: for PF table set true, for VSI table set false
 524  * @lut: pointer to the lut buffer provided by the caller
 525  * @lut_size: size of the lut buffer
 526  *
 527  * set the RSS lookup table, PF or VSI type
 528  **/
 529 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 530                                           bool pf_lut, u8 *lut, u16 lut_size)
 531 {
 532         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 533 }
 534
 535 /**
 536  * i40e_aq_get_set_rss_key
 537  * @hw: pointer to the hw struct
 538  * @vsi_id: vsi fw index
 539  * @key: pointer to key info struct
 540  * @set: set true to set the key, false to get the key
 541  *
 542  * get the RSS key per VSI
 543  **/
 544 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 545                                       u16 vsi_id,
 546                                       struct i40e_aqc_get_set_rss_key_data *key,
 547                                       bool set)
 548 {
 549         enum i40e_status_code status;
 550         struct i40e_aq_desc desc;
 551         struct i40e_aqc_get_set_rss_key *cmd_resp =
 552                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 553         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 554
 555         if (set)
 556                 i40e_fill_default_direct_cmd_desc(&desc,
 557                                                   i40e_aqc_opc_set_rss_key);
 558         else
 559                 i40e_fill_default_direct_cmd_desc(&desc,
 560                                                   i40e_aqc_opc_get_rss_key);
 561
 562         /* Indirect command */
 563         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 564         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 565
 566         cmd_resp->vsi_id =
 567                         CPU_TO_LE16((u16)((vsi_id <<
 568                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 569                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 570         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 571
 572         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 573
 574         return status;
 575 }
 576
 577 /**
 578  * i40e_aq_get_rss_key
 579  * @hw: pointer to the hw struct
 580  * @vsi_id: vsi fw index
 581  * @key: pointer to key info struct
 582  *
 583  **/
 584 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 585                                       u16 vsi_id,
 586                                       struct i40e_aqc_get_set_rss_key_data *key)
 587 {
 588         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 589 }
 590
 591 /**
 592  * i40e_aq_set_rss_key
 593  * @hw: pointer to the hw struct
 594  * @vsi_id: vsi fw index
 595  * @key: pointer to key info struct
 596  *
 597  * set the RSS key per VSI
 598  **/
 599 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 600                                       u16 vsi_id,
 601                                       struct i40e_aqc_get_set_rss_key_data *key)
 602 {
 603         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 604 }
 605 #endif /* X722_SUPPORT */
 606
 607 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 608  * hardware to a bit-field that can be used by SW to more easily determine the
 609  * packet type.
 610  *
 611  * Macros are used to shorten the table lines and make this table human
 612  * readable.
 613  *
 614  * We store the PTYPE in the top byte of the bit field - this is just so that
 615  * we can check that the table doesn't have a row missing, as the index into
 616  * the table should be the PTYPE.
 617  *
 618  * Typical work flow:
 619  *
 620  * IF NOT i40e_ptype_lookup[ptype].known
 621  * THEN
 622  *      Packet is unknown
 623  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 624  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 625  * ELSE
 626  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 627  * ENDIF
 628  */
 629
 630 /* macro to make the table lines short */
 631 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 632         {       PTYPE, \
 633                 1, \
 634                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 635                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 636                 I40E_RX_PTYPE_##OUTER_FRAG, \
 637                 I40E_RX_PTYPE_TUNNEL_##T, \
 638                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 639                 I40E_RX_PTYPE_##TEF, \
 640                 I40E_RX_PTYPE_INNER_PROT_##I, \
 641                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 642
 643 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 644                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 645
 646 /* shorter macros makes the table fit but are terse */
 647 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 648 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 649 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 650
 651 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 652 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 653         /* L2 Packet types */
 654         I40E_PTT_UNUSED_ENTRY(0),
 655         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 656         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 657         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 658         I40E_PTT_UNUSED_ENTRY(4),
 659         I40E_PTT_UNUSED_ENTRY(5),
 660         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 661         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 662         I40E_PTT_UNUSED_ENTRY(8),
 663         I40E_PTT_UNUSED_ENTRY(9),
 664         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 665         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 666         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 667         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 668         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 669         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 670         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 671         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 672         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 673         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 674         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 675         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 676
 677         /* Non Tunneled IPv4 */
 678         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 679         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 680         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 681         I40E_PTT_UNUSED_ENTRY(25),
 682         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 683         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 684         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 685
 686         /* IPv4 --> IPv4 */
 687         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(32),
 691         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 --> IPv6 */
 696         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(39),
 700         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 703
 704         /* IPv4 --> GRE/NAT */
 705         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 706
 707         /* IPv4 --> GRE/NAT --> IPv4 */
 708         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 709         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 710         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 711         I40E_PTT_UNUSED_ENTRY(47),
 712         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 713         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 714         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 715
 716         /* IPv4 --> GRE/NAT --> IPv6 */
 717         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 718         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 719         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 720         I40E_PTT_UNUSED_ENTRY(54),
 721         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 722         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 723         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 724
 725         /* IPv4 --> GRE/NAT --> MAC */
 726         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 727
 728         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 729         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 730         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 731         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 732         I40E_PTT_UNUSED_ENTRY(62),
 733         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 734         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 735         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 736
 737         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 738         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 739         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 740         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 741         I40E_PTT_UNUSED_ENTRY(69),
 742         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 743         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 744         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 745
 746         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 747         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 748
 749         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 750         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 751         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 752         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 753         I40E_PTT_UNUSED_ENTRY(77),
 754         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 755         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 756         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 757
 758         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 759         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 760         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 761         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 762         I40E_PTT_UNUSED_ENTRY(84),
 763         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 764         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 765         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 766
 767         /* Non Tunneled IPv6 */
 768         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 769         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 770         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),
 771         I40E_PTT_UNUSED_ENTRY(91),
 772         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 773         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 774         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 775
 776         /* IPv6 --> IPv4 */
 777         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(98),
 781         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> IPv6 */
 786         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(105),
 790         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 793
 794         /* IPv6 --> GRE/NAT */
 795         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 796
 797         /* IPv6 --> GRE/NAT -> IPv4 */
 798         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 799         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 800         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 801         I40E_PTT_UNUSED_ENTRY(113),
 802         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 803         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 804         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 805
 806         /* IPv6 --> GRE/NAT -> IPv6 */
 807         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 808         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 809         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 810         I40E_PTT_UNUSED_ENTRY(120),
 811         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 812         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 813         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 814
 815         /* IPv6 --> GRE/NAT -> MAC */
 816         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 817
 818         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 819         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 820         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 821         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 822         I40E_PTT_UNUSED_ENTRY(128),
 823         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 824         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 825         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 826
 827         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 828         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 829         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 830         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 831         I40E_PTT_UNUSED_ENTRY(135),
 832         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 833         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 834         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 835
 836         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 837         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 838
 839         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 840         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 841         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 842         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 843         I40E_PTT_UNUSED_ENTRY(143),
 844         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 845         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 846         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 847
 848         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 849         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 850         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 851         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 852         I40E_PTT_UNUSED_ENTRY(150),
 853         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 854         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 855         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 856
 857         /* unused entries */
 858         I40E_PTT_UNUSED_ENTRY(154),
 859         I40E_PTT_UNUSED_ENTRY(155),
 860         I40E_PTT_UNUSED_ENTRY(156),
 861         I40E_PTT_UNUSED_ENTRY(157),
 862         I40E_PTT_UNUSED_ENTRY(158),
 863         I40E_PTT_UNUSED_ENTRY(159),
 864
 865         I40E_PTT_UNUSED_ENTRY(160),
 866         I40E_PTT_UNUSED_ENTRY(161),
 867         I40E_PTT_UNUSED_ENTRY(162),
 868         I40E_PTT_UNUSED_ENTRY(163),
 869         I40E_PTT_UNUSED_ENTRY(164),
 870         I40E_PTT_UNUSED_ENTRY(165),
 871         I40E_PTT_UNUSED_ENTRY(166),
 872         I40E_PTT_UNUSED_ENTRY(167),
 873         I40E_PTT_UNUSED_ENTRY(168),
 874         I40E_PTT_UNUSED_ENTRY(169),
 875
 876         I40E_PTT_UNUSED_ENTRY(170),
 877         I40E_PTT_UNUSED_ENTRY(171),
 878         I40E_PTT_UNUSED_ENTRY(172),
 879         I40E_PTT_UNUSED_ENTRY(173),
 880         I40E_PTT_UNUSED_ENTRY(174),
 881         I40E_PTT_UNUSED_ENTRY(175),
 882         I40E_PTT_UNUSED_ENTRY(176),
 883         I40E_PTT_UNUSED_ENTRY(177),
 884         I40E_PTT_UNUSED_ENTRY(178),
 885         I40E_PTT_UNUSED_ENTRY(179),
 886
 887         I40E_PTT_UNUSED_ENTRY(180),
 888         I40E_PTT_UNUSED_ENTRY(181),
 889         I40E_PTT_UNUSED_ENTRY(182),
 890         I40E_PTT_UNUSED_ENTRY(183),
 891         I40E_PTT_UNUSED_ENTRY(184),
 892         I40E_PTT_UNUSED_ENTRY(185),
 893         I40E_PTT_UNUSED_ENTRY(186),
 894         I40E_PTT_UNUSED_ENTRY(187),
 895         I40E_PTT_UNUSED_ENTRY(188),
 896         I40E_PTT_UNUSED_ENTRY(189),
 897
 898         I40E_PTT_UNUSED_ENTRY(190),
 899         I40E_PTT_UNUSED_ENTRY(191),
 900         I40E_PTT_UNUSED_ENTRY(192),
 901         I40E_PTT_UNUSED_ENTRY(193),
 902         I40E_PTT_UNUSED_ENTRY(194),
 903         I40E_PTT_UNUSED_ENTRY(195),
 904         I40E_PTT_UNUSED_ENTRY(196),
 905         I40E_PTT_UNUSED_ENTRY(197),
 906         I40E_PTT_UNUSED_ENTRY(198),
 907         I40E_PTT_UNUSED_ENTRY(199),
 908
 909         I40E_PTT_UNUSED_ENTRY(200),
 910         I40E_PTT_UNUSED_ENTRY(201),
 911         I40E_PTT_UNUSED_ENTRY(202),
 912         I40E_PTT_UNUSED_ENTRY(203),
 913         I40E_PTT_UNUSED_ENTRY(204),
 914         I40E_PTT_UNUSED_ENTRY(205),
 915         I40E_PTT_UNUSED_ENTRY(206),
 916         I40E_PTT_UNUSED_ENTRY(207),
 917         I40E_PTT_UNUSED_ENTRY(208),
 918         I40E_PTT_UNUSED_ENTRY(209),
 919
 920         I40E_PTT_UNUSED_ENTRY(210),
 921         I40E_PTT_UNUSED_ENTRY(211),
 922         I40E_PTT_UNUSED_ENTRY(212),
 923         I40E_PTT_UNUSED_ENTRY(213),
 924         I40E_PTT_UNUSED_ENTRY(214),
 925         I40E_PTT_UNUSED_ENTRY(215),
 926         I40E_PTT_UNUSED_ENTRY(216),
 927         I40E_PTT_UNUSED_ENTRY(217),
 928         I40E_PTT_UNUSED_ENTRY(218),
 929         I40E_PTT_UNUSED_ENTRY(219),
 930
 931         I40E_PTT_UNUSED_ENTRY(220),
 932         I40E_PTT_UNUSED_ENTRY(221),
 933         I40E_PTT_UNUSED_ENTRY(222),
 934         I40E_PTT_UNUSED_ENTRY(223),
 935         I40E_PTT_UNUSED_ENTRY(224),
 936         I40E_PTT_UNUSED_ENTRY(225),
 937         I40E_PTT_UNUSED_ENTRY(226),
 938         I40E_PTT_UNUSED_ENTRY(227),
 939         I40E_PTT_UNUSED_ENTRY(228),
 940         I40E_PTT_UNUSED_ENTRY(229),
 941
 942         I40E_PTT_UNUSED_ENTRY(230),
 943         I40E_PTT_UNUSED_ENTRY(231),
 944         I40E_PTT_UNUSED_ENTRY(232),
 945         I40E_PTT_UNUSED_ENTRY(233),
 946         I40E_PTT_UNUSED_ENTRY(234),
 947         I40E_PTT_UNUSED_ENTRY(235),
 948         I40E_PTT_UNUSED_ENTRY(236),
 949         I40E_PTT_UNUSED_ENTRY(237),
 950         I40E_PTT_UNUSED_ENTRY(238),
 951         I40E_PTT_UNUSED_ENTRY(239),
 952
 953         I40E_PTT_UNUSED_ENTRY(240),
 954         I40E_PTT_UNUSED_ENTRY(241),
 955         I40E_PTT_UNUSED_ENTRY(242),
 956         I40E_PTT_UNUSED_ENTRY(243),
 957         I40E_PTT_UNUSED_ENTRY(244),
 958         I40E_PTT_UNUSED_ENTRY(245),
 959         I40E_PTT_UNUSED_ENTRY(246),
 960         I40E_PTT_UNUSED_ENTRY(247),
 961         I40E_PTT_UNUSED_ENTRY(248),
 962         I40E_PTT_UNUSED_ENTRY(249),
 963
 964         I40E_PTT_UNUSED_ENTRY(250),
 965         I40E_PTT_UNUSED_ENTRY(251),
 966         I40E_PTT_UNUSED_ENTRY(252),
 967         I40E_PTT_UNUSED_ENTRY(253),
 968         I40E_PTT_UNUSED_ENTRY(254),
 969         I40E_PTT_UNUSED_ENTRY(255)
 970 };
 971
 972
 973 /**
 974  * i40e_validate_mac_addr - Validate unicast MAC address
 975  * @mac_addr: pointer to MAC address
 976  *
 977  * Tests a MAC address to ensure it is a valid Individual Address
 978  **/
 979 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 980 {
 981         enum i40e_status_code status = I40E_SUCCESS;
 982
 983         DEBUGFUNC("i40e_validate_mac_addr");
 984
 985         /* Broadcast addresses ARE multicast addresses
 986          * Make sure it is not a multicast address
 987          * Reject the zero address
 988          */
 989         if (I40E_IS_MULTICAST(mac_addr) ||
 990             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 991               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 992                 status = I40E_ERR_INVALID_MAC_ADDR;
 993
 994         return status;
 995 }
 996 #ifdef PF_DRIVER
 997
 998 /**
 999  * i40e_init_shared_code - Initialize the shared code
1000  * @hw: pointer to hardware structure
1001  *
1002  * This assigns the MAC type and PHY code and inits the NVM.
1003  * Does not touch the hardware. This function must be called prior to any
1004  * other function in the shared code. The i40e_hw structure should be
1005  * memset to 0 prior to calling this function.  The following fields in
1006  * hw structure should be filled in prior to calling this function:
1007  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1008  * subsystem_vendor_id, and revision_id
1009  **/
1010 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
1011 {
1012         enum i40e_status_code status = I40E_SUCCESS;
1013         u32 port, ari, func_rid;
1014
1015         DEBUGFUNC("i40e_init_shared_code");
1016
1017         i40e_set_mac_type(hw);
1018
1019         switch (hw->mac.type) {
1020         case I40E_MAC_XL710:
1021 #ifdef X722_SUPPORT
1022         case I40E_MAC_X722:
1023 #endif
1024                 break;
1025         default:
1026                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1027         }
1028
1029         hw->phy.get_link_info = true;
1030
1031         /* Determine port number and PF number*/
1032         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1033                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1034         hw->port = (u8)port;
1035         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1036                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1037         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1038         if (ari)
1039                 hw->pf_id = (u8)(func_rid & 0xff);
1040         else
1041                 hw->pf_id = (u8)(func_rid & 0x7);
1042
1043 #ifdef X722_SUPPORT
1044         if (hw->mac.type == I40E_MAC_X722)
1045                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
1046
1047 #endif
1048         status = i40e_init_nvm(hw);
1049         return status;
1050 }
1051
1052 /**
1053  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1054  * @hw: pointer to the hw struct
1055  * @flags: a return indicator of what addresses were added to the addr store
1056  * @addrs: the requestor's mac addr store
1057  * @cmd_details: pointer to command details structure or NULL
1058  **/
1059 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1060                                    u16 *flags,
1061                                    struct i40e_aqc_mac_address_read_data *addrs,
1062                                    struct i40e_asq_cmd_details *cmd_details)
1063 {
1064         struct i40e_aq_desc desc;
1065         struct i40e_aqc_mac_address_read *cmd_data =
1066                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1067         enum i40e_status_code status;
1068
1069         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1070         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1071
1072         status = i40e_asq_send_command(hw, &desc, addrs,
1073                                        sizeof(*addrs), cmd_details);
1074         *flags = LE16_TO_CPU(cmd_data->command_flags);
1075
1076         return status;
1077 }
1078
1079 /**
1080  * i40e_aq_mac_address_write - Change the MAC addresses
1081  * @hw: pointer to the hw struct
1082  * @flags: indicates which MAC to be written
1083  * @mac_addr: address to write
1084  * @cmd_details: pointer to command details structure or NULL
1085  **/
1086 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1087                                     u16 flags, u8 *mac_addr,
1088                                     struct i40e_asq_cmd_details *cmd_details)
1089 {
1090         struct i40e_aq_desc desc;
1091         struct i40e_aqc_mac_address_write *cmd_data =
1092                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1093         enum i40e_status_code status;
1094
1095         i40e_fill_default_direct_cmd_desc(&desc,
1096                                           i40e_aqc_opc_mac_address_write);
1097         cmd_data->command_flags = CPU_TO_LE16(flags);
1098         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1099         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1100                                         ((u32)mac_addr[3] << 16) |
1101                                         ((u32)mac_addr[4] << 8) |
1102                                         mac_addr[5]);
1103
1104         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1105
1106         return status;
1107 }
1108
1109 /**
1110  * i40e_get_mac_addr - get MAC address
1111  * @hw: pointer to the HW structure
1112  * @mac_addr: pointer to MAC address
1113  *
1114  * Reads the adapter's MAC address from register
1115  **/
1116 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1117 {
1118         struct i40e_aqc_mac_address_read_data addrs;
1119         enum i40e_status_code status;
1120         u16 flags = 0;
1121
1122         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1123
1124         if (flags & I40E_AQC_LAN_ADDR_VALID)
1125                 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
1126
1127         return status;
1128 }
1129
1130 /**
1131  * i40e_get_port_mac_addr - get Port MAC address
1132  * @hw: pointer to the HW structure
1133  * @mac_addr: pointer to Port MAC address
1134  *
1135  * Reads the adapter's Port MAC address
1136  **/
1137 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1138 {
1139         struct i40e_aqc_mac_address_read_data addrs;
1140         enum i40e_status_code status;
1141         u16 flags = 0;
1142
1143         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1144         if (status)
1145                 return status;
1146
1147         if (flags & I40E_AQC_PORT_ADDR_VALID)
1148                 memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));
1149         else
1150                 status = I40E_ERR_INVALID_MAC_ADDR;
1151
1152         return status;
1153 }
1154
1155 /**
1156  * i40e_pre_tx_queue_cfg - pre tx queue configure
1157  * @hw: pointer to the HW structure
1158  * @queue: target pf queue index
1159  * @enable: state change request
1160  *
1161  * Handles hw requirement to indicate intention to enable
1162  * or disable target queue.
1163  **/
1164 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1165 {
1166         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1167         u32 reg_block = 0;
1168         u32 reg_val;
1169
1170         if (abs_queue_idx >= 128) {
1171                 reg_block = abs_queue_idx / 128;
1172                 abs_queue_idx %= 128;
1173         }
1174
1175         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1176         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1177         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1178
1179         if (enable)
1180                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1181         else
1182                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1183
1184         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1185 }
1186
1187 /**
1188  *  i40e_read_pba_string - Reads part number string from EEPROM
1189  *  @hw: pointer to hardware structure
1190  *  @pba_num: stores the part number string from the EEPROM
1191  *  @pba_num_size: part number string buffer length
1192  *
1193  *  Reads the part number string from the EEPROM.
1194  **/
1195 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1196                                             u32 pba_num_size)
1197 {
1198         enum i40e_status_code status = I40E_SUCCESS;
1199         u16 pba_word = 0;
1200         u16 pba_size = 0;
1201         u16 pba_ptr = 0;
1202         u16 i = 0;
1203
1204         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1205         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1206                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1207                 return status;
1208         }
1209
1210         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1211         if (status != I40E_SUCCESS) {
1212                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1213                 return status;
1214         }
1215
1216         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1217         if (status != I40E_SUCCESS) {
1218                 DEBUGOUT("Failed to read PBA Block size.\n");
1219                 return status;
1220         }
1221
1222         /* Subtract one to get PBA word count (PBA Size word is included in
1223          * total size)
1224          */
1225         pba_size--;
1226         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1227                 DEBUGOUT("Buffer to small for PBA data.\n");
1228                 return I40E_ERR_PARAM;
1229         }
1230
1231         for (i = 0; i < pba_size; i++) {
1232                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1233                 if (status != I40E_SUCCESS) {
1234                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1235                         return status;
1236                 }
1237
1238                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1239                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1240         }
1241         pba_num[(pba_size * 2)] = '\0';
1242
1243         return status;
1244 }
1245
1246 /**
1247  * i40e_get_media_type - Gets media type
1248  * @hw: pointer to the hardware structure
1249  **/
1250 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1251 {
1252         enum i40e_media_type media;
1253
1254         switch (hw->phy.link_info.phy_type) {
1255         case I40E_PHY_TYPE_10GBASE_SR:
1256         case I40E_PHY_TYPE_10GBASE_LR:
1257         case I40E_PHY_TYPE_1000BASE_SX:
1258         case I40E_PHY_TYPE_1000BASE_LX:
1259         case I40E_PHY_TYPE_40GBASE_SR4:
1260         case I40E_PHY_TYPE_40GBASE_LR4:
1261                 media = I40E_MEDIA_TYPE_FIBER;
1262                 break;
1263         case I40E_PHY_TYPE_100BASE_TX:
1264         case I40E_PHY_TYPE_1000BASE_T:
1265         case I40E_PHY_TYPE_10GBASE_T:
1266                 media = I40E_MEDIA_TYPE_BASET;
1267                 break;
1268         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1269         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1270         case I40E_PHY_TYPE_10GBASE_CR1:
1271         case I40E_PHY_TYPE_40GBASE_CR4:
1272         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1273         case I40E_PHY_TYPE_40GBASE_AOC:
1274         case I40E_PHY_TYPE_10GBASE_AOC:
1275                 media = I40E_MEDIA_TYPE_DA;
1276                 break;
1277         case I40E_PHY_TYPE_1000BASE_KX:
1278         case I40E_PHY_TYPE_10GBASE_KX4:
1279         case I40E_PHY_TYPE_10GBASE_KR:
1280         case I40E_PHY_TYPE_40GBASE_KR4:
1281         case I40E_PHY_TYPE_20GBASE_KR2:
1282                 media = I40E_MEDIA_TYPE_BACKPLANE;
1283                 break;
1284         case I40E_PHY_TYPE_SGMII:
1285         case I40E_PHY_TYPE_XAUI:
1286         case I40E_PHY_TYPE_XFI:
1287         case I40E_PHY_TYPE_XLAUI:
1288         case I40E_PHY_TYPE_XLPPI:
1289         default:
1290                 media = I40E_MEDIA_TYPE_UNKNOWN;
1291                 break;
1292         }
1293
1294         return media;
1295 }
1296
1297 #define I40E_PF_RESET_WAIT_COUNT        200
1298 /**
1299  * i40e_pf_reset - Reset the PF
1300  * @hw: pointer to the hardware structure
1301  *
1302  * Assuming someone else has triggered a global reset,
1303  * assure the global reset is complete and then reset the PF
1304  **/
1305 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1306 {
1307         u32 cnt = 0;
1308         u32 cnt1 = 0;
1309         u32 reg = 0;
1310         u32 grst_del;
1311
1312         /* Poll for Global Reset steady state in case of recent GRST.
1313          * The grst delay value is in 100ms units, and we'll wait a
1314          * couple counts longer to be sure we don't just miss the end.
1315          */
1316         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1317                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1318                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1319
1320         /* It can take upto 15 secs for GRST steady state */
1321         grst_del = grst_del * 20; /* bump it to 16 secs max to be safe */
1322
1323         for (cnt = 0; cnt < grst_del; cnt++) {
1324                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1325                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1326                         break;
1327                 i40e_msec_delay(100);
1328         }
1329         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1330                 DEBUGOUT("Global reset polling failed to complete.\n");
1331                 return I40E_ERR_RESET_FAILED;
1332         }
1333
1334         /* Now Wait for the FW to be ready */
1335         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1336                 reg = rd32(hw, I40E_GLNVM_ULD);
1337                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1338                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1339                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1340                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1341                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1342                         break;
1343                 }
1344                 i40e_msec_delay(10);
1345         }
1346         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1347                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1348                 DEBUGOUT("wait for FW Reset complete timedout\n");
1349                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1350                 return I40E_ERR_RESET_FAILED;
1351         }
1352
1353         /* If there was a Global Reset in progress when we got here,
1354          * we don't need to do the PF Reset
1355          */
1356         if (!cnt) {
1357                 reg = rd32(hw, I40E_PFGEN_CTRL);
1358                 wr32(hw, I40E_PFGEN_CTRL,
1359                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1360                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1361                         reg = rd32(hw, I40E_PFGEN_CTRL);
1362                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1363                                 break;
1364                         i40e_msec_delay(1);
1365                 }
1366                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1367                         DEBUGOUT("PF reset polling failed to complete.\n");
1368                         return I40E_ERR_RESET_FAILED;
1369                 }
1370         }
1371
1372         i40e_clear_pxe_mode(hw);
1373
1374
1375         return I40E_SUCCESS;
1376 }
1377
1378 /**
1379  * i40e_clear_hw - clear out any left over hw state
1380  * @hw: pointer to the hw struct
1381  *
1382  * Clear queues and interrupts, typically called at init time,
1383  * but after the capabilities have been found so we know how many
1384  * queues and msix vectors have been allocated.
1385  **/
1386 void i40e_clear_hw(struct i40e_hw *hw)
1387 {
1388         u32 num_queues, base_queue;
1389         u32 num_pf_int;
1390         u32 num_vf_int;
1391         u32 num_vfs;
1392         u32 i, j;
1393         u32 val;
1394         u32 eol = 0x7ff;
1395
1396         /* get number of interrupts, queues, and vfs */
1397         val = rd32(hw, I40E_GLPCI_CNF2);
1398         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1399                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1400         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1401                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1402
1403         val = rd32(hw, I40E_PFLAN_QALLOC);
1404         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1405                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1406         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1407                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1408         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1409                 num_queues = (j - base_queue) + 1;
1410         else
1411                 num_queues = 0;
1412
1413         val = rd32(hw, I40E_PF_VT_PFALLOC);
1414         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1415                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1416         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1417                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1418         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1419                 num_vfs = (j - i) + 1;
1420         else
1421                 num_vfs = 0;
1422
1423         /* stop all the interrupts */
1424         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1425         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1426         for (i = 0; i < num_pf_int - 2; i++)
1427                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1428
1429         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1430         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1431         wr32(hw, I40E_PFINT_LNKLST0, val);
1432         for (i = 0; i < num_pf_int - 2; i++)
1433                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1434         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1435         for (i = 0; i < num_vfs; i++)
1436                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1437         for (i = 0; i < num_vf_int - 2; i++)
1438                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1439
1440         /* warn the HW of the coming Tx disables */
1441         for (i = 0; i < num_queues; i++) {
1442                 u32 abs_queue_idx = base_queue + i;
1443                 u32 reg_block = 0;
1444
1445                 if (abs_queue_idx >= 128) {
1446                         reg_block = abs_queue_idx / 128;
1447                         abs_queue_idx %= 128;
1448                 }
1449
1450                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1451                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1452                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1453                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1454
1455                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1456         }
1457         i40e_usec_delay(400);
1458
1459         /* stop all the queues */
1460         for (i = 0; i < num_queues; i++) {
1461                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1462                 wr32(hw, I40E_QTX_ENA(i), 0);
1463                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1464                 wr32(hw, I40E_QRX_ENA(i), 0);
1465         }
1466
1467         /* short wait for all queue disables to settle */
1468         i40e_usec_delay(50);
1469 }
1470
1471 /**
1472  * i40e_clear_pxe_mode - clear pxe operations mode
1473  * @hw: pointer to the hw struct
1474  *
1475  * Make sure all PXE mode settings are cleared, including things
1476  * like descriptor fetch/write-back mode.
1477  **/
1478 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1479 {
1480         if (i40e_check_asq_alive(hw))
1481                 i40e_aq_clear_pxe_mode(hw, NULL);
1482 }
1483
1484 /**
1485  * i40e_led_is_mine - helper to find matching led
1486  * @hw: pointer to the hw struct
1487  * @idx: index into GPIO registers
1488  *
1489  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1490  */
1491 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1492 {
1493         u32 gpio_val = 0;
1494         u32 port;
1495
1496         if (!hw->func_caps.led[idx])
1497                 return 0;
1498
1499         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1500         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1501                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1502
1503         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1504          * if it is not our port then ignore
1505          */
1506         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1507             (port != hw->port))
1508                 return 0;
1509
1510         return gpio_val;
1511 }
1512
1513 #define I40E_COMBINED_ACTIVITY 0xA
1514 #define I40E_FILTER_ACTIVITY 0xE
1515 #define I40E_LINK_ACTIVITY 0xC
1516 #define I40E_MAC_ACTIVITY 0xD
1517 #define I40E_LED0 22
1518
1519 /**
1520  * i40e_led_get - return current on/off mode
1521  * @hw: pointer to the hw struct
1522  *
1523  * The value returned is the 'mode' field as defined in the
1524  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1525  * values are variations of possible behaviors relating to
1526  * blink, link, and wire.
1527  **/
1528 u32 i40e_led_get(struct i40e_hw *hw)
1529 {
1530         u32 current_mode = 0;
1531         u32 mode = 0;
1532         int i;
1533
1534         /* as per the documentation GPIO 22-29 are the LED
1535          * GPIO pins named LED0..LED7
1536          */
1537         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1538                 u32 gpio_val = i40e_led_is_mine(hw, i);
1539
1540                 if (!gpio_val)
1541                         continue;
1542
1543                 /* ignore gpio LED src mode entries related to the activity
1544                  *  LEDs
1545                  */
1546                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1547                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1548                 switch (current_mode) {
1549                 case I40E_COMBINED_ACTIVITY:
1550                 case I40E_FILTER_ACTIVITY:
1551                 case I40E_MAC_ACTIVITY:
1552                         continue;
1553                 default:
1554                         break;
1555                 }
1556
1557                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1558                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1559                 break;
1560         }
1561
1562         return mode;
1563 }
1564
1565 /**
1566  * i40e_led_set - set new on/off mode
1567  * @hw: pointer to the hw struct
1568  * @mode: 0=off, 0xf=on (else see manual for mode details)
1569  * @blink: true if the LED should blink when on, false if steady
1570  *
1571  * if this function is used to turn on the blink it should
1572  * be used to disable the blink when restoring the original state.
1573  **/
1574 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1575 {
1576         u32 current_mode = 0;
1577         int i;
1578
1579         if (mode & 0xfffffff0)
1580                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1581
1582         /* as per the documentation GPIO 22-29 are the LED
1583          * GPIO pins named LED0..LED7
1584          */
1585         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1586                 u32 gpio_val = i40e_led_is_mine(hw, i);
1587
1588                 if (!gpio_val)
1589                         continue;
1590
1591                 /* ignore gpio LED src mode entries related to the activity
1592                  * LEDs
1593                  */
1594                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1595                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1596                 switch (current_mode) {
1597                 case I40E_COMBINED_ACTIVITY:
1598                 case I40E_FILTER_ACTIVITY:
1599                 case I40E_MAC_ACTIVITY:
1600                         continue;
1601                 default:
1602                         break;
1603                 }
1604
1605                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1606                 /* this & is a bit of paranoia, but serves as a range check */
1607                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1608                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1609
1610                 if (mode == I40E_LINK_ACTIVITY)
1611                         blink = false;
1612
1613                 if (blink)
1614                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1615                 else
1616                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1617
1618                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1619                 break;
1620         }
1621 }
1622
1623 /* Admin command wrappers */
1624
1625 /**
1626  * i40e_aq_get_phy_capabilities
1627  * @hw: pointer to the hw struct
1628  * @abilities: structure for PHY capabilities to be filled
1629  * @qualified_modules: report Qualified Modules
1630  * @report_init: report init capabilities (active are default)
1631  * @cmd_details: pointer to command details structure or NULL
1632  *
1633  * Returns the various PHY abilities supported on the Port.
1634  **/
1635 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1636                         bool qualified_modules, bool report_init,
1637                         struct i40e_aq_get_phy_abilities_resp *abilities,
1638                         struct i40e_asq_cmd_details *cmd_details)
1639 {
1640         struct i40e_aq_desc desc;
1641         enum i40e_status_code status;
1642         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1643
1644         if (!abilities)
1645                 return I40E_ERR_PARAM;
1646
1647         i40e_fill_default_direct_cmd_desc(&desc,
1648                                           i40e_aqc_opc_get_phy_abilities);
1649
1650         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1651         if (abilities_size > I40E_AQ_LARGE_BUF)
1652                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1653
1654         if (qualified_modules)
1655                 desc.params.external.param0 |=
1656                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1657
1658         if (report_init)
1659                 desc.params.external.param0 |=
1660                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1661
1662         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1663                                     cmd_details);
1664
1665         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1666                 status = I40E_ERR_UNKNOWN_PHY;
1667
1668         if (report_init)
1669                 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1670
1671         return status;
1672 }
1673
1674 /**
1675  * i40e_aq_set_phy_config
1676  * @hw: pointer to the hw struct
1677  * @config: structure with PHY configuration to be set
1678  * @cmd_details: pointer to command details structure or NULL
1679  *
1680  * Set the various PHY configuration parameters
1681  * supported on the Port.One or more of the Set PHY config parameters may be
1682  * ignored in an MFP mode as the PF may not have the privilege to set some
1683  * of the PHY Config parameters. This status will be indicated by the
1684  * command response.
1685  **/
1686 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1687                                 struct i40e_aq_set_phy_config *config,
1688                                 struct i40e_asq_cmd_details *cmd_details)
1689 {
1690         struct i40e_aq_desc desc;
1691         struct i40e_aq_set_phy_config *cmd =
1692                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1693         enum i40e_status_code status;
1694
1695         if (!config)
1696                 return I40E_ERR_PARAM;
1697
1698         i40e_fill_default_direct_cmd_desc(&desc,
1699                                           i40e_aqc_opc_set_phy_config);
1700
1701         *cmd = *config;
1702
1703         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1704
1705         return status;
1706 }
1707
1708 /**
1709  * i40e_set_fc
1710  * @hw: pointer to the hw struct
1711  *
1712  * Set the requested flow control mode using set_phy_config.
1713  **/
1714 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1715                                   bool atomic_restart)
1716 {
1717         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1718         struct i40e_aq_get_phy_abilities_resp abilities;
1719         struct i40e_aq_set_phy_config config;
1720         enum i40e_status_code status;
1721         u8 pause_mask = 0x0;
1722
1723         *aq_failures = 0x0;
1724
1725         switch (fc_mode) {
1726         case I40E_FC_FULL:
1727                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1728                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1729                 break;
1730         case I40E_FC_RX_PAUSE:
1731                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1732                 break;
1733         case I40E_FC_TX_PAUSE:
1734                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1735                 break;
1736         default:
1737                 break;
1738         }
1739
1740         /* Get the current phy config */
1741         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1742                                               NULL);
1743         if (status) {
1744                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1745                 return status;
1746         }
1747
1748         memset(&config, 0, sizeof(config));
1749         /* clear the old pause settings */
1750         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1751                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1752         /* set the new abilities */
1753         config.abilities |= pause_mask;
1754         /* If the abilities have changed, then set the new config */
1755         if (config.abilities != abilities.abilities) {
1756                 /* Auto restart link so settings take effect */
1757                 if (atomic_restart)
1758                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1759                 /* Copy over all the old settings */
1760                 config.phy_type = abilities.phy_type;
1761                 config.link_speed = abilities.link_speed;
1762                 config.eee_capability = abilities.eee_capability;
1763                 config.eeer = abilities.eeer_val;
1764                 config.low_power_ctrl = abilities.d3_lpan;
1765                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1766
1767                 if (status)
1768                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1769         }
1770         /* Update the link info */
1771         status = i40e_update_link_info(hw);
1772         if (status) {
1773                 /* Wait a little bit (on 40G cards it sometimes takes a really
1774                  * long time for link to come back from the atomic reset)
1775                  * and try once more
1776                  */
1777                 i40e_msec_delay(1000);
1778                 status = i40e_update_link_info(hw);
1779         }
1780         if (status)
1781                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1782
1783         return status;
1784 }
1785
1786 /**
1787  * i40e_aq_set_mac_config
1788  * @hw: pointer to the hw struct
1789  * @max_frame_size: Maximum Frame Size to be supported by the port
1790  * @crc_en: Tell HW to append a CRC to outgoing frames
1791  * @pacing: Pacing configurations
1792  * @cmd_details: pointer to command details structure or NULL
1793  *
1794  * Configure MAC settings for frame size, jumbo frame support and the
1795  * addition of a CRC by the hardware.
1796  **/
1797 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1798                                 u16 max_frame_size,
1799                                 bool crc_en, u16 pacing,
1800                                 struct i40e_asq_cmd_details *cmd_details)
1801 {
1802         struct i40e_aq_desc desc;
1803         struct i40e_aq_set_mac_config *cmd =
1804                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1805         enum i40e_status_code status;
1806
1807         if (max_frame_size == 0)
1808                 return I40E_ERR_PARAM;
1809
1810         i40e_fill_default_direct_cmd_desc(&desc,
1811                                           i40e_aqc_opc_set_mac_config);
1812
1813         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1814         cmd->params = ((u8)pacing & 0x0F) << 3;
1815         if (crc_en)
1816                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1817
1818         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1819
1820         return status;
1821 }
1822
1823 /**
1824  * i40e_aq_clear_pxe_mode
1825  * @hw: pointer to the hw struct
1826  * @cmd_details: pointer to command details structure or NULL
1827  *
1828  * Tell the firmware that the driver is taking over from PXE
1829  **/
1830 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1831                         struct i40e_asq_cmd_details *cmd_details)
1832 {
1833         enum i40e_status_code status;
1834         struct i40e_aq_desc desc;
1835         struct i40e_aqc_clear_pxe *cmd =
1836                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1837
1838         i40e_fill_default_direct_cmd_desc(&desc,
1839                                           i40e_aqc_opc_clear_pxe_mode);
1840
1841         cmd->rx_cnt = 0x2;
1842
1843         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1844
1845         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1846
1847         return status;
1848 }
1849
1850 /**
1851  * i40e_aq_set_link_restart_an
1852  * @hw: pointer to the hw struct
1853  * @enable_link: if true: enable link, if false: disable link
1854  * @cmd_details: pointer to command details structure or NULL
1855  *
1856  * Sets up the link and restarts the Auto-Negotiation over the link.
1857  **/
1858 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1859                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1860 {
1861         struct i40e_aq_desc desc;
1862         struct i40e_aqc_set_link_restart_an *cmd =
1863                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1864         enum i40e_status_code status;
1865
1866         i40e_fill_default_direct_cmd_desc(&desc,
1867                                           i40e_aqc_opc_set_link_restart_an);
1868
1869         cmd->command = I40E_AQ_PHY_RESTART_AN;
1870         if (enable_link)
1871                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1872         else
1873                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1874
1875         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1876
1877         return status;
1878 }
1879
1880 /**
1881  * i40e_aq_get_link_info
1882  * @hw: pointer to the hw struct
1883  * @enable_lse: enable/disable LinkStatusEvent reporting
1884  * @link: pointer to link status structure - optional
1885  * @cmd_details: pointer to command details structure or NULL
1886  *
1887  * Returns the link status of the adapter.
1888  **/
1889 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1890                                 bool enable_lse, struct i40e_link_status *link,
1891                                 struct i40e_asq_cmd_details *cmd_details)
1892 {
1893         struct i40e_aq_desc desc;
1894         struct i40e_aqc_get_link_status *resp =
1895                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1896         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1897         enum i40e_status_code status;
1898         bool tx_pause, rx_pause;
1899         u16 command_flags;
1900
1901         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1902
1903         if (enable_lse)
1904                 command_flags = I40E_AQ_LSE_ENABLE;
1905         else
1906                 command_flags = I40E_AQ_LSE_DISABLE;
1907         resp->command_flags = CPU_TO_LE16(command_flags);
1908
1909         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1910
1911         if (status != I40E_SUCCESS)
1912                 goto aq_get_link_info_exit;
1913
1914         /* save off old link status information */
1915         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1916                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1917
1918         /* update link status */
1919         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1920         hw->phy.media_type = i40e_get_media_type(hw);
1921         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1922         hw_link_info->link_info = resp->link_info;
1923         hw_link_info->an_info = resp->an_info;
1924         hw_link_info->ext_info = resp->ext_info;
1925         hw_link_info->loopback = resp->loopback;
1926         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1927         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1928
1929         /* update fc info */
1930         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1931         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1932         if (tx_pause & rx_pause)
1933                 hw->fc.current_mode = I40E_FC_FULL;
1934         else if (tx_pause)
1935                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1936         else if (rx_pause)
1937                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1938         else
1939                 hw->fc.current_mode = I40E_FC_NONE;
1940
1941         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1942                 hw_link_info->crc_enable = true;
1943         else
1944                 hw_link_info->crc_enable = false;
1945
1946         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))
1947                 hw_link_info->lse_enable = true;
1948         else
1949                 hw_link_info->lse_enable = false;
1950
1951         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1952              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1953                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1954
1955         /* save link status information */
1956         if (link)
1957                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1958                             I40E_NONDMA_TO_NONDMA);
1959
1960         /* flag cleared so helper functions don't call AQ again */
1961         hw->phy.get_link_info = false;
1962
1963 aq_get_link_info_exit:
1964         return status;
1965 }
1966
1967 /**
1968  * i40e_aq_set_phy_int_mask
1969  * @hw: pointer to the hw struct
1970  * @mask: interrupt mask to be set
1971  * @cmd_details: pointer to command details structure or NULL
1972  *
1973  * Set link interrupt mask.
1974  **/
1975 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1976                                 u16 mask,
1977                                 struct i40e_asq_cmd_details *cmd_details)
1978 {
1979         struct i40e_aq_desc desc;
1980         struct i40e_aqc_set_phy_int_mask *cmd =
1981                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1982         enum i40e_status_code status;
1983
1984         i40e_fill_default_direct_cmd_desc(&desc,
1985                                           i40e_aqc_opc_set_phy_int_mask);
1986
1987         cmd->event_mask = CPU_TO_LE16(mask);
1988
1989         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1990
1991         return status;
1992 }
1993
1994 /**
1995  * i40e_aq_get_local_advt_reg
1996  * @hw: pointer to the hw struct
1997  * @advt_reg: local AN advertisement register value
1998  * @cmd_details: pointer to command details structure or NULL
1999  *
2000  * Get the Local AN advertisement register value.
2001  **/
2002 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2003                                 u64 *advt_reg,
2004                                 struct i40e_asq_cmd_details *cmd_details)
2005 {
2006         struct i40e_aq_desc desc;
2007         struct i40e_aqc_an_advt_reg *resp =
2008                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2009         enum i40e_status_code status;
2010
2011         i40e_fill_default_direct_cmd_desc(&desc,
2012                                           i40e_aqc_opc_get_local_advt_reg);
2013
2014         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2015
2016         if (status != I40E_SUCCESS)
2017                 goto aq_get_local_advt_reg_exit;
2018
2019         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2020         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2021
2022 aq_get_local_advt_reg_exit:
2023         return status;
2024 }
2025
2026 /**
2027  * i40e_aq_set_local_advt_reg
2028  * @hw: pointer to the hw struct
2029  * @advt_reg: local AN advertisement register value
2030  * @cmd_details: pointer to command details structure or NULL
2031  *
2032  * Get the Local AN advertisement register value.
2033  **/
2034 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2035                                 u64 advt_reg,
2036                                 struct i40e_asq_cmd_details *cmd_details)
2037 {
2038         struct i40e_aq_desc desc;
2039         struct i40e_aqc_an_advt_reg *cmd =
2040                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2041         enum i40e_status_code status;
2042
2043         i40e_fill_default_direct_cmd_desc(&desc,
2044                                           i40e_aqc_opc_get_local_advt_reg);
2045
2046         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2047         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2048
2049         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2050
2051         return status;
2052 }
2053
2054 /**
2055  * i40e_aq_get_partner_advt
2056  * @hw: pointer to the hw struct
2057  * @advt_reg: AN partner advertisement register value
2058  * @cmd_details: pointer to command details structure or NULL
2059  *
2060  * Get the link partner AN advertisement register value.
2061  **/
2062 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2063                                 u64 *advt_reg,
2064                                 struct i40e_asq_cmd_details *cmd_details)
2065 {
2066         struct i40e_aq_desc desc;
2067         struct i40e_aqc_an_advt_reg *resp =
2068                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2069         enum i40e_status_code status;
2070
2071         i40e_fill_default_direct_cmd_desc(&desc,
2072                                           i40e_aqc_opc_get_partner_advt);
2073
2074         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2075
2076         if (status != I40E_SUCCESS)
2077                 goto aq_get_partner_advt_exit;
2078
2079         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2080         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2081
2082 aq_get_partner_advt_exit:
2083         return status;
2084 }
2085
2086 /**
2087  * i40e_aq_set_lb_modes
2088  * @hw: pointer to the hw struct
2089  * @lb_modes: loopback mode to be set
2090  * @cmd_details: pointer to command details structure or NULL
2091  *
2092  * Sets loopback modes.
2093  **/
2094 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2095                                 u16 lb_modes,
2096                                 struct i40e_asq_cmd_details *cmd_details)
2097 {
2098         struct i40e_aq_desc desc;
2099         struct i40e_aqc_set_lb_mode *cmd =
2100                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2101         enum i40e_status_code status;
2102
2103         i40e_fill_default_direct_cmd_desc(&desc,
2104                                           i40e_aqc_opc_set_lb_modes);
2105
2106         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2107
2108         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2109
2110         return status;
2111 }
2112
2113 /**
2114  * i40e_aq_set_phy_debug
2115  * @hw: pointer to the hw struct
2116  * @cmd_flags: debug command flags
2117  * @cmd_details: pointer to command details structure or NULL
2118  *
2119  * Reset the external PHY.
2120  **/
2121 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2122                                 struct i40e_asq_cmd_details *cmd_details)
2123 {
2124         struct i40e_aq_desc desc;
2125         struct i40e_aqc_set_phy_debug *cmd =
2126                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2127         enum i40e_status_code status;
2128
2129         i40e_fill_default_direct_cmd_desc(&desc,
2130                                           i40e_aqc_opc_set_phy_debug);
2131
2132         cmd->command_flags = cmd_flags;
2133
2134         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2135
2136         return status;
2137 }
2138
2139 /**
2140  * i40e_aq_add_vsi
2141  * @hw: pointer to the hw struct
2142  * @vsi_ctx: pointer to a vsi context struct
2143  * @cmd_details: pointer to command details structure or NULL
2144  *
2145  * Add a VSI context to the hardware.
2146 **/
2147 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2148                                 struct i40e_vsi_context *vsi_ctx,
2149                                 struct i40e_asq_cmd_details *cmd_details)
2150 {
2151         struct i40e_aq_desc desc;
2152         struct i40e_aqc_add_get_update_vsi *cmd =
2153                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2154         struct i40e_aqc_add_get_update_vsi_completion *resp =
2155                 (struct i40e_aqc_add_get_update_vsi_completion *)
2156                 &desc.params.raw;
2157         enum i40e_status_code status;
2158
2159         i40e_fill_default_direct_cmd_desc(&desc,
2160                                           i40e_aqc_opc_add_vsi);
2161
2162         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2163         cmd->connection_type = vsi_ctx->connection_type;
2164         cmd->vf_id = vsi_ctx->vf_num;
2165         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2166
2167         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2168
2169         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2170                                     sizeof(vsi_ctx->info), cmd_details);
2171
2172         if (status != I40E_SUCCESS)
2173                 goto aq_add_vsi_exit;
2174
2175         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2176         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2177         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2178         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2179
2180 aq_add_vsi_exit:
2181         return status;
2182 }
2183
2184 /**
2185  * i40e_aq_set_default_vsi
2186  * @hw: pointer to the hw struct
2187  * @seid: vsi number
2188  * @cmd_details: pointer to command details structure or NULL
2189  **/
2190 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2191                                 u16 seid,
2192                                 struct i40e_asq_cmd_details *cmd_details)
2193 {
2194         struct i40e_aq_desc desc;
2195         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2196                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2197                 &desc.params.raw;
2198         enum i40e_status_code status;
2199
2200         i40e_fill_default_direct_cmd_desc(&desc,
2201                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2202
2203         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2204         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2205         cmd->seid = CPU_TO_LE16(seid);
2206
2207         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2208
2209         return status;
2210 }
2211
2212 /**
2213  * i40e_aq_set_vsi_unicast_promiscuous
2214  * @hw: pointer to the hw struct
2215  * @seid: vsi number
2216  * @set: set unicast promiscuous enable/disable
2217  * @cmd_details: pointer to command details structure or NULL
2218  **/
2219 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2220                                 u16 seid, bool set,
2221                                 struct i40e_asq_cmd_details *cmd_details)
2222 {
2223         struct i40e_aq_desc desc;
2224         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2225                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2226         enum i40e_status_code status;
2227         u16 flags = 0;
2228
2229         i40e_fill_default_direct_cmd_desc(&desc,
2230                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2231
2232         if (set) {
2233                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2234                 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2235                      (hw->aq.api_maj_ver > 1))
2236                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2237         }
2238
2239         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2240
2241         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2242         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2243              (hw->aq.api_maj_ver > 1))
2244                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2245
2246         cmd->seid = CPU_TO_LE16(seid);
2247         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2248
2249         return status;
2250 }
2251
2252 /**
2253  * i40e_aq_set_vsi_multicast_promiscuous
2254  * @hw: pointer to the hw struct
2255  * @seid: vsi number
2256  * @set: set multicast promiscuous enable/disable
2257  * @cmd_details: pointer to command details structure or NULL
2258  **/
2259 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2260                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2261 {
2262         struct i40e_aq_desc desc;
2263         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2264                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2265         enum i40e_status_code status;
2266         u16 flags = 0;
2267
2268         i40e_fill_default_direct_cmd_desc(&desc,
2269                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2270
2271         if (set)
2272                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2273
2274         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2275
2276         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2277
2278         cmd->seid = CPU_TO_LE16(seid);
2279         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2280
2281         return status;
2282 }
2283
2284 /**
2285  * i40e_aq_set_vsi_mc_promisc_on_vlan
2286  * @hw: pointer to the hw struct
2287  * @seid: vsi number
2288  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2289  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2290  * @cmd_details: pointer to command details structure or NULL
2291  **/
2292 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2293                                 u16 seid, bool enable, u16 vid,
2294                                 struct i40e_asq_cmd_details *cmd_details)
2295 {
2296         struct i40e_aq_desc desc;
2297         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2298                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2299         enum i40e_status_code status;
2300         u16 flags = 0;
2301
2302         i40e_fill_default_direct_cmd_desc(&desc,
2303                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2304
2305         if (enable)
2306                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2307
2308         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2309         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2310         cmd->seid = CPU_TO_LE16(seid);
2311         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2312
2313         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2314
2315         return status;
2316 }
2317
2318 /**
2319  * i40e_aq_set_vsi_uc_promisc_on_vlan
2320  * @hw: pointer to the hw struct
2321  * @seid: vsi number
2322  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2323  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2324  * @cmd_details: pointer to command details structure or NULL
2325  **/
2326 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2327                                 u16 seid, bool enable, u16 vid,
2328                                 struct i40e_asq_cmd_details *cmd_details)
2329 {
2330         struct i40e_aq_desc desc;
2331         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2332                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2333         enum i40e_status_code status;
2334         u16 flags = 0;
2335
2336         i40e_fill_default_direct_cmd_desc(&desc,
2337                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2338
2339         if (enable)
2340                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2341
2342         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2343         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2344         cmd->seid = CPU_TO_LE16(seid);
2345         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2346
2347         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2348
2349         return status;
2350 }
2351
2352 /**
2353  * i40e_aq_set_vsi_broadcast
2354  * @hw: pointer to the hw struct
2355  * @seid: vsi number
2356  * @set_filter: true to set filter, false to clear filter
2357  * @cmd_details: pointer to command details structure or NULL
2358  *
2359  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2360  **/
2361 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2362                                 u16 seid, bool set_filter,
2363                                 struct i40e_asq_cmd_details *cmd_details)
2364 {
2365         struct i40e_aq_desc desc;
2366         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2367                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2368         enum i40e_status_code status;
2369
2370         i40e_fill_default_direct_cmd_desc(&desc,
2371                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2372
2373         if (set_filter)
2374                 cmd->promiscuous_flags
2375                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2376         else
2377                 cmd->promiscuous_flags
2378                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2379
2380         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2381         cmd->seid = CPU_TO_LE16(seid);
2382         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2383
2384         return status;
2385 }
2386
2387 /**
2388  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2389  * @hw: pointer to the hw struct
2390  * @seid: vsi number
2391  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2392  * @cmd_details: pointer to command details structure or NULL
2393  **/
2394 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2395                                 u16 seid, bool enable,
2396                                 struct i40e_asq_cmd_details *cmd_details)
2397 {
2398         struct i40e_aq_desc desc;
2399         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2400                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2401         enum i40e_status_code status;
2402         u16 flags = 0;
2403
2404         i40e_fill_default_direct_cmd_desc(&desc,
2405                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2406         if (enable)
2407                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2408
2409         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2410         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2411         cmd->seid = CPU_TO_LE16(seid);
2412
2413         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2414
2415         return status;
2416 }
2417
2418 /**
2419  * i40e_get_vsi_params - get VSI configuration info
2420  * @hw: pointer to the hw struct
2421  * @vsi_ctx: pointer to a vsi context struct
2422  * @cmd_details: pointer to command details structure or NULL
2423  **/
2424 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2425                                 struct i40e_vsi_context *vsi_ctx,
2426                                 struct i40e_asq_cmd_details *cmd_details)
2427 {
2428         struct i40e_aq_desc desc;
2429         struct i40e_aqc_add_get_update_vsi *cmd =
2430                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2431         struct i40e_aqc_add_get_update_vsi_completion *resp =
2432                 (struct i40e_aqc_add_get_update_vsi_completion *)
2433                 &desc.params.raw;
2434         enum i40e_status_code status;
2435
2436         UNREFERENCED_1PARAMETER(cmd_details);
2437         i40e_fill_default_direct_cmd_desc(&desc,
2438                                           i40e_aqc_opc_get_vsi_parameters);
2439
2440         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2441
2442         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2443
2444         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2445                                     sizeof(vsi_ctx->info), NULL);
2446
2447         if (status != I40E_SUCCESS)
2448                 goto aq_get_vsi_params_exit;
2449
2450         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2451         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2452         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2453         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2454
2455 aq_get_vsi_params_exit:
2456         return status;
2457 }
2458
2459 /**
2460  * i40e_aq_update_vsi_params
2461  * @hw: pointer to the hw struct
2462  * @vsi_ctx: pointer to a vsi context struct
2463  * @cmd_details: pointer to command details structure or NULL
2464  *
2465  * Update a VSI context.
2466  **/
2467 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2468                                 struct i40e_vsi_context *vsi_ctx,
2469                                 struct i40e_asq_cmd_details *cmd_details)
2470 {
2471         struct i40e_aq_desc desc;
2472         struct i40e_aqc_add_get_update_vsi *cmd =
2473                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2474         struct i40e_aqc_add_get_update_vsi_completion *resp =
2475                 (struct i40e_aqc_add_get_update_vsi_completion *)
2476                 &desc.params.raw;
2477         enum i40e_status_code status;
2478
2479         i40e_fill_default_direct_cmd_desc(&desc,
2480                                           i40e_aqc_opc_update_vsi_parameters);
2481         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2482
2483         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2484
2485         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2486                                     sizeof(vsi_ctx->info), cmd_details);
2487
2488         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2489         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2490
2491         return status;
2492 }
2493
2494 /**
2495  * i40e_aq_get_switch_config
2496  * @hw: pointer to the hardware structure
2497  * @buf: pointer to the result buffer
2498  * @buf_size: length of input buffer
2499  * @start_seid: seid to start for the report, 0 == beginning
2500  * @cmd_details: pointer to command details structure or NULL
2501  *
2502  * Fill the buf with switch configuration returned from AdminQ command
2503  **/
2504 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2505                                 struct i40e_aqc_get_switch_config_resp *buf,
2506                                 u16 buf_size, u16 *start_seid,
2507                                 struct i40e_asq_cmd_details *cmd_details)
2508 {
2509         struct i40e_aq_desc desc;
2510         struct i40e_aqc_switch_seid *scfg =
2511                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2512         enum i40e_status_code status;
2513
2514         i40e_fill_default_direct_cmd_desc(&desc,
2515                                           i40e_aqc_opc_get_switch_config);
2516         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2517         if (buf_size > I40E_AQ_LARGE_BUF)
2518                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2519         scfg->seid = CPU_TO_LE16(*start_seid);
2520
2521         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2522         *start_seid = LE16_TO_CPU(scfg->seid);
2523
2524         return status;
2525 }
2526
2527 /**
2528  * i40e_aq_set_switch_config
2529  * @hw: pointer to the hardware structure
2530  * @flags: bit flag values to set
2531  * @valid_flags: which bit flags to set
2532  * @cmd_details: pointer to command details structure or NULL
2533  *
2534  * Set switch configuration bits
2535  **/
2536 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2537                                 u16 flags, u16 valid_flags,
2538                                 struct i40e_asq_cmd_details *cmd_details)
2539 {
2540         struct i40e_aq_desc desc;
2541         struct i40e_aqc_set_switch_config *scfg =
2542                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2543         enum i40e_status_code status;
2544
2545         i40e_fill_default_direct_cmd_desc(&desc,
2546                                           i40e_aqc_opc_set_switch_config);
2547         scfg->flags = CPU_TO_LE16(flags);
2548         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2549
2550         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2551
2552         return status;
2553 }
2554
2555 /**
2556  * i40e_aq_get_firmware_version
2557  * @hw: pointer to the hw struct
2558  * @fw_major_version: firmware major version
2559  * @fw_minor_version: firmware minor version
2560  * @fw_build: firmware build number
2561  * @api_major_version: major queue version
2562  * @api_minor_version: minor queue version
2563  * @cmd_details: pointer to command details structure or NULL
2564  *
2565  * Get the firmware version from the admin queue commands
2566  **/
2567 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2568                                 u16 *fw_major_version, u16 *fw_minor_version,
2569                                 u32 *fw_build,
2570                                 u16 *api_major_version, u16 *api_minor_version,
2571                                 struct i40e_asq_cmd_details *cmd_details)
2572 {
2573         struct i40e_aq_desc desc;
2574         struct i40e_aqc_get_version *resp =
2575                 (struct i40e_aqc_get_version *)&desc.params.raw;
2576         enum i40e_status_code status;
2577
2578         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2579
2580         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2581
2582         if (status == I40E_SUCCESS) {
2583                 if (fw_major_version != NULL)
2584                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2585                 if (fw_minor_version != NULL)
2586                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2587                 if (fw_build != NULL)
2588                         *fw_build = LE32_TO_CPU(resp->fw_build);
2589                 if (api_major_version != NULL)
2590                         *api_major_version = LE16_TO_CPU(resp->api_major);
2591                 if (api_minor_version != NULL)
2592                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2593
2594                 /* A workaround to fix the API version in SW */
2595                 if (api_major_version && api_minor_version &&
2596                     fw_major_version && fw_minor_version &&
2597                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2598                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2599                      (*fw_major_version > 4)))
2600                         *api_minor_version = 2;
2601         }
2602
2603         return status;
2604 }
2605
2606 /**
2607  * i40e_aq_send_driver_version
2608  * @hw: pointer to the hw struct
2609  * @dv: driver's major, minor version
2610  * @cmd_details: pointer to command details structure or NULL
2611  *
2612  * Send the driver version to the firmware
2613  **/
2614 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2615                                 struct i40e_driver_version *dv,
2616                                 struct i40e_asq_cmd_details *cmd_details)
2617 {
2618         struct i40e_aq_desc desc;
2619         struct i40e_aqc_driver_version *cmd =
2620                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2621         enum i40e_status_code status;
2622         u16 len;
2623
2624         if (dv == NULL)
2625                 return I40E_ERR_PARAM;
2626
2627         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2628
2629         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2630         cmd->driver_major_ver = dv->major_version;
2631         cmd->driver_minor_ver = dv->minor_version;
2632         cmd->driver_build_ver = dv->build_version;
2633         cmd->driver_subbuild_ver = dv->subbuild_version;
2634
2635         len = 0;
2636         while (len < sizeof(dv->driver_string) &&
2637                (dv->driver_string[len] < 0x80) &&
2638                dv->driver_string[len])
2639                 len++;
2640         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2641                                        len, cmd_details);
2642
2643         return status;
2644 }
2645
2646 /**
2647  * i40e_get_link_status - get status of the HW network link
2648  * @hw: pointer to the hw struct
2649  * @link_up: pointer to bool (true/false = linkup/linkdown)
2650  *
2651  * Variable link_up true if link is up, false if link is down.
2652  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2653  *
2654  * Side effect: LinkStatusEvent reporting becomes enabled
2655  **/
2656 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2657 {
2658         enum i40e_status_code status = I40E_SUCCESS;
2659
2660         if (hw->phy.get_link_info) {
2661                 status = i40e_update_link_info(hw);
2662
2663                 if (status != I40E_SUCCESS)
2664                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2665                                    status);
2666         }
2667
2668         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2669
2670         return status;
2671 }
2672
2673 /**
2674  * i40e_updatelink_status - update status of the HW network link
2675  * @hw: pointer to the hw struct
2676  **/
2677 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2678 {
2679         struct i40e_aq_get_phy_abilities_resp abilities;
2680         enum i40e_status_code status = I40E_SUCCESS;
2681
2682         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2683         if (status)
2684                 return status;
2685
2686         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2687                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2688                                                       &abilities, NULL);
2689                 if (status)
2690                         return status;
2691
2692                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2693                         sizeof(hw->phy.link_info.module_type));
2694         }
2695         return status;
2696 }
2697
2698
2699 /**
2700  * i40e_get_link_speed
2701  * @hw: pointer to the hw struct
2702  *
2703  * Returns the link speed of the adapter.
2704  **/
2705 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2706 {
2707         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2708         enum i40e_status_code status = I40E_SUCCESS;
2709
2710         if (hw->phy.get_link_info) {
2711                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2712
2713                 if (status != I40E_SUCCESS)
2714                         goto i40e_link_speed_exit;
2715         }
2716
2717         speed = hw->phy.link_info.link_speed;
2718
2719 i40e_link_speed_exit:
2720         return speed;
2721 }
2722
2723 /**
2724  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2725  * @hw: pointer to the hw struct
2726  * @uplink_seid: the MAC or other gizmo SEID
2727  * @downlink_seid: the VSI SEID
2728  * @enabled_tc: bitmap of TCs to be enabled
2729  * @default_port: true for default port VSI, false for control port
2730  * @veb_seid: pointer to where to put the resulting VEB SEID
2731  * @enable_stats: true to turn on VEB stats
2732  * @cmd_details: pointer to command details structure or NULL
2733  *
2734  * This asks the FW to add a VEB between the uplink and downlink
2735  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2736  **/
2737 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2738                                 u16 downlink_seid, u8 enabled_tc,
2739                                 bool default_port, u16 *veb_seid,
2740                                 bool enable_stats,
2741                                 struct i40e_asq_cmd_details *cmd_details)
2742 {
2743         struct i40e_aq_desc desc;
2744         struct i40e_aqc_add_veb *cmd =
2745                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2746         struct i40e_aqc_add_veb_completion *resp =
2747                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2748         enum i40e_status_code status;
2749         u16 veb_flags = 0;
2750
2751         /* SEIDs need to either both be set or both be 0 for floating VEB */
2752         if (!!uplink_seid != !!downlink_seid)
2753                 return I40E_ERR_PARAM;
2754
2755         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2756
2757         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2758         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2759         cmd->enable_tcs = enabled_tc;
2760         if (!uplink_seid)
2761                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2762         if (default_port)
2763                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2764         else
2765                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2766
2767         /* reverse logic here: set the bitflag to disable the stats */
2768         if (!enable_stats)
2769                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2770
2771         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2772
2773         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2774
2775         if (!status && veb_seid)
2776                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2777
2778         return status;
2779 }
2780
2781 /**
2782  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2783  * @hw: pointer to the hw struct
2784  * @veb_seid: the SEID of the VEB to query
2785  * @switch_id: the uplink switch id
2786  * @floating: set to true if the VEB is floating
2787  * @statistic_index: index of the stats counter block for this VEB
2788  * @vebs_used: number of VEB's used by function
2789  * @vebs_free: total VEB's not reserved by any function
2790  * @cmd_details: pointer to command details structure or NULL
2791  *
2792  * This retrieves the parameters for a particular VEB, specified by
2793  * uplink_seid, and returns them to the caller.
2794  **/
2795 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2796                                 u16 veb_seid, u16 *switch_id,
2797                                 bool *floating, u16 *statistic_index,
2798                                 u16 *vebs_used, u16 *vebs_free,
2799                                 struct i40e_asq_cmd_details *cmd_details)
2800 {
2801         struct i40e_aq_desc desc;
2802         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2803                 (struct i40e_aqc_get_veb_parameters_completion *)
2804                 &desc.params.raw;
2805         enum i40e_status_code status;
2806
2807         if (veb_seid == 0)
2808                 return I40E_ERR_PARAM;
2809
2810         i40e_fill_default_direct_cmd_desc(&desc,
2811                                           i40e_aqc_opc_get_veb_parameters);
2812         cmd_resp->seid = CPU_TO_LE16(veb_seid);
2813
2814         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2815         if (status)
2816                 goto get_veb_exit;
2817
2818         if (switch_id)
2819                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2820         if (statistic_index)
2821                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2822         if (vebs_used)
2823                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2824         if (vebs_free)
2825                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2826         if (floating) {
2827                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2828
2829                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2830                         *floating = true;
2831                 else
2832                         *floating = false;
2833         }
2834
2835 get_veb_exit:
2836         return status;
2837 }
2838
2839 /**
2840  * i40e_aq_add_macvlan
2841  * @hw: pointer to the hw struct
2842  * @seid: VSI for the mac address
2843  * @mv_list: list of macvlans to be added
2844  * @count: length of the list
2845  * @cmd_details: pointer to command details structure or NULL
2846  *
2847  * Add MAC/VLAN addresses to the HW filtering
2848  **/
2849 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2850                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2851                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2852 {
2853         struct i40e_aq_desc desc;
2854         struct i40e_aqc_macvlan *cmd =
2855                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2856         enum i40e_status_code status;
2857         u16 buf_size;
2858         int i;
2859
2860         if (count == 0 || !mv_list || !hw)
2861                 return I40E_ERR_PARAM;
2862
2863         buf_size = count * sizeof(*mv_list);
2864
2865         /* prep the rest of the request */
2866         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2867         cmd->num_addresses = CPU_TO_LE16(count);
2868         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2869         cmd->seid[1] = 0;
2870         cmd->seid[2] = 0;
2871
2872         for (i = 0; i < count; i++)
2873                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2874                         mv_list[i].flags |=
2875                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2876
2877         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2878         if (buf_size > I40E_AQ_LARGE_BUF)
2879                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2880
2881         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2882                                        cmd_details);
2883
2884         return status;
2885 }
2886
2887 /**
2888  * i40e_aq_remove_macvlan
2889  * @hw: pointer to the hw struct
2890  * @seid: VSI for the mac address
2891  * @mv_list: list of macvlans to be removed
2892  * @count: length of the list
2893  * @cmd_details: pointer to command details structure or NULL
2894  *
2895  * Remove MAC/VLAN addresses from the HW filtering
2896  **/
2897 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2898                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2899                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2900 {
2901         struct i40e_aq_desc desc;
2902         struct i40e_aqc_macvlan *cmd =
2903                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2904         enum i40e_status_code status;
2905         u16 buf_size;
2906
2907         if (count == 0 || !mv_list || !hw)
2908                 return I40E_ERR_PARAM;
2909
2910         buf_size = count * sizeof(*mv_list);
2911
2912         /* prep the rest of the request */
2913         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2914         cmd->num_addresses = CPU_TO_LE16(count);
2915         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2916         cmd->seid[1] = 0;
2917         cmd->seid[2] = 0;
2918
2919         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2920         if (buf_size > I40E_AQ_LARGE_BUF)
2921                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2922
2923         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2924                                        cmd_details);
2925
2926         return status;
2927 }
2928
2929 /**
2930  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2931  * @hw: pointer to the hw struct
2932  * @opcode: AQ opcode for add or delete mirror rule
2933  * @sw_seid: Switch SEID (to which rule refers)
2934  * @rule_type: Rule Type (ingress/egress/VLAN)
2935  * @id: Destination VSI SEID or Rule ID
2936  * @count: length of the list
2937  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2938  * @cmd_details: pointer to command details structure or NULL
2939  * @rule_id: Rule ID returned from FW
2940  * @rule_used: Number of rules used in internal switch
2941  * @rule_free: Number of rules free in internal switch
2942  *
2943  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2944  * VEBs/VEPA elements only
2945  **/
2946 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
2947                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2948                         u16 count, __le16 *mr_list,
2949                         struct i40e_asq_cmd_details *cmd_details,
2950                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2951 {
2952         struct i40e_aq_desc desc;
2953         struct i40e_aqc_add_delete_mirror_rule *cmd =
2954                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2955         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2956         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2957         enum i40e_status_code status;
2958         u16 buf_size;
2959
2960         buf_size = count * sizeof(*mr_list);
2961
2962         /* prep the rest of the request */
2963         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2964         cmd->seid = CPU_TO_LE16(sw_seid);
2965         cmd->rule_type = CPU_TO_LE16(rule_type &
2966                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2967         cmd->num_entries = CPU_TO_LE16(count);
2968         /* Dest VSI for add, rule_id for delete */
2969         cmd->destination = CPU_TO_LE16(id);
2970         if (mr_list) {
2971                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
2972                                                 I40E_AQ_FLAG_RD));
2973                 if (buf_size > I40E_AQ_LARGE_BUF)
2974                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2975         }
2976
2977         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2978                                        cmd_details);
2979         if (status == I40E_SUCCESS ||
2980             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2981                 if (rule_id)
2982                         *rule_id = LE16_TO_CPU(resp->rule_id);
2983                 if (rules_used)
2984                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
2985                 if (rules_free)
2986                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
2987         }
2988         return status;
2989 }
2990
2991 /**
2992  * i40e_aq_add_mirrorrule - add a mirror rule
2993  * @hw: pointer to the hw struct
2994  * @sw_seid: Switch SEID (to which rule refers)
2995  * @rule_type: Rule Type (ingress/egress/VLAN)
2996  * @dest_vsi: SEID of VSI to which packets will be mirrored
2997  * @count: length of the list
2998  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2999  * @cmd_details: pointer to command details structure or NULL
3000  * @rule_id: Rule ID returned from FW
3001  * @rule_used: Number of rules used in internal switch
3002  * @rule_free: Number of rules free in internal switch
3003  *
3004  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3005  **/
3006 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3007                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3008                         struct i40e_asq_cmd_details *cmd_details,
3009                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3010 {
3011         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3012             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3013                 if (count == 0 || !mr_list)
3014                         return I40E_ERR_PARAM;
3015         }
3016
3017         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3018                                   rule_type, dest_vsi, count, mr_list,
3019                                   cmd_details, rule_id, rules_used, rules_free);
3020 }
3021
3022 /**
3023  * i40e_aq_delete_mirrorrule - delete a mirror rule
3024  * @hw: pointer to the hw struct
3025  * @sw_seid: Switch SEID (to which rule refers)
3026  * @rule_type: Rule Type (ingress/egress/VLAN)
3027  * @count: length of the list
3028  * @rule_id: Rule ID that is returned in the receive desc as part of
3029  *              add_mirrorrule.
3030  * @mr_list: list of mirrored VLAN IDs to be removed
3031  * @cmd_details: pointer to command details structure or NULL
3032  * @rule_used: Number of rules used in internal switch
3033  * @rule_free: Number of rules free in internal switch
3034  *
3035  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3036  **/
3037 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3038                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3039                         struct i40e_asq_cmd_details *cmd_details,
3040                         u16 *rules_used, u16 *rules_free)
3041 {
3042         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3043         if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3044                 if (!rule_id)
3045                         return I40E_ERR_PARAM;
3046         } else {
3047                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3048                  * mirroring. For other rule_type, count and rule_type should
3049                  * not matter.
3050                  */
3051                 if (count == 0 || !mr_list)
3052                         return I40E_ERR_PARAM;
3053         }
3054
3055         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3056                                   rule_type, rule_id, count, mr_list,
3057                                   cmd_details, NULL, rules_used, rules_free);
3058 }
3059
3060 /**
3061  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3062  * @hw: pointer to the hw struct
3063  * @seid: VSI for the vlan filters
3064  * @v_list: list of vlan filters to be added
3065  * @count: length of the list
3066  * @cmd_details: pointer to command details structure or NULL
3067  **/
3068 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3069                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3070                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3071 {
3072         struct i40e_aq_desc desc;
3073         struct i40e_aqc_macvlan *cmd =
3074                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3075         enum i40e_status_code status;
3076         u16 buf_size;
3077
3078         if (count == 0 || !v_list || !hw)
3079                 return I40E_ERR_PARAM;
3080
3081         buf_size = count * sizeof(*v_list);
3082
3083         /* prep the rest of the request */
3084         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3085         cmd->num_addresses = CPU_TO_LE16(count);
3086         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3087         cmd->seid[1] = 0;
3088         cmd->seid[2] = 0;
3089
3090         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3091         if (buf_size > I40E_AQ_LARGE_BUF)
3092                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3093
3094         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3095                                        cmd_details);
3096
3097         return status;
3098 }
3099
3100 /**
3101  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3102  * @hw: pointer to the hw struct
3103  * @seid: VSI for the vlan filters
3104  * @v_list: list of macvlans to be removed
3105  * @count: length of the list
3106  * @cmd_details: pointer to command details structure or NULL
3107  **/
3108 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3109                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3110                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3111 {
3112         struct i40e_aq_desc desc;
3113         struct i40e_aqc_macvlan *cmd =
3114                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3115         enum i40e_status_code status;
3116         u16 buf_size;
3117
3118         if (count == 0 || !v_list || !hw)
3119                 return I40E_ERR_PARAM;
3120
3121         buf_size = count * sizeof(*v_list);
3122
3123         /* prep the rest of the request */
3124         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3125         cmd->num_addresses = CPU_TO_LE16(count);
3126         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3127         cmd->seid[1] = 0;
3128         cmd->seid[2] = 0;
3129
3130         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3131         if (buf_size > I40E_AQ_LARGE_BUF)
3132                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3133
3134         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3135                                        cmd_details);
3136
3137         return status;
3138 }
3139
3140 /**
3141  * i40e_aq_send_msg_to_vf
3142  * @hw: pointer to the hardware structure
3143  * @vfid: vf id to send msg
3144  * @v_opcode: opcodes for VF-PF communication
3145  * @v_retval: return error code
3146  * @msg: pointer to the msg buffer
3147  * @msglen: msg length
3148  * @cmd_details: pointer to command details
3149  *
3150  * send msg to vf
3151  **/
3152 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3153                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3154                                 struct i40e_asq_cmd_details *cmd_details)
3155 {
3156         struct i40e_aq_desc desc;
3157         struct i40e_aqc_pf_vf_message *cmd =
3158                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3159         enum i40e_status_code status;
3160
3161         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3162         cmd->id = CPU_TO_LE32(vfid);
3163         desc.cookie_high = CPU_TO_LE32(v_opcode);
3164         desc.cookie_low = CPU_TO_LE32(v_retval);
3165         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3166         if (msglen) {
3167                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3168                                                 I40E_AQ_FLAG_RD));
3169                 if (msglen > I40E_AQ_LARGE_BUF)
3170                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3171                 desc.datalen = CPU_TO_LE16(msglen);
3172         }
3173         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3174
3175         return status;
3176 }
3177
3178 /**
3179  * i40e_aq_debug_read_register
3180  * @hw: pointer to the hw struct
3181  * @reg_addr: register address
3182  * @reg_val: register value
3183  * @cmd_details: pointer to command details structure or NULL
3184  *
3185  * Read the register using the admin queue commands
3186  **/
3187 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3188                                 u32 reg_addr, u64 *reg_val,
3189                                 struct i40e_asq_cmd_details *cmd_details)
3190 {
3191         struct i40e_aq_desc desc;
3192         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3193                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3194         enum i40e_status_code status;
3195
3196         if (reg_val == NULL)
3197                 return I40E_ERR_PARAM;
3198
3199         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3200
3201         cmd_resp->address = CPU_TO_LE32(reg_addr);
3202
3203         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3204
3205         if (status == I40E_SUCCESS) {
3206                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3207                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3208         }
3209
3210         return status;
3211 }
3212
3213 /**
3214  * i40e_aq_debug_write_register
3215  * @hw: pointer to the hw struct
3216  * @reg_addr: register address
3217  * @reg_val: register value
3218  * @cmd_details: pointer to command details structure or NULL
3219  *
3220  * Write to a register using the admin queue commands
3221  **/
3222 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3223                                 u32 reg_addr, u64 reg_val,
3224                                 struct i40e_asq_cmd_details *cmd_details)
3225 {
3226         struct i40e_aq_desc desc;
3227         struct i40e_aqc_debug_reg_read_write *cmd =
3228                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3229         enum i40e_status_code status;
3230
3231         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3232
3233         cmd->address = CPU_TO_LE32(reg_addr);
3234         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3235         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3236
3237         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3238
3239         return status;
3240 }
3241
3242 /**
3243  * i40e_aq_get_hmc_resource_profile
3244  * @hw: pointer to the hw struct
3245  * @profile: type of profile the HMC is to be set as
3246  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3247  * @cmd_details: pointer to command details structure or NULL
3248  *
3249  * query the HMC profile of the device.
3250  **/
3251 enum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,
3252                                 enum i40e_aq_hmc_profile *profile,
3253                                 u8 *pe_vf_enabled_count,
3254                                 struct i40e_asq_cmd_details *cmd_details)
3255 {
3256         struct i40e_aq_desc desc;
3257         struct i40e_aq_get_set_hmc_resource_profile *resp =
3258                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3259         enum i40e_status_code status;
3260
3261         i40e_fill_default_direct_cmd_desc(&desc,
3262                                 i40e_aqc_opc_query_hmc_resource_profile);
3263         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3264
3265         *profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &
3266                    I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);
3267         *pe_vf_enabled_count = resp->pe_vf_enabled &
3268                                I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;
3269
3270         return status;
3271 }
3272
3273 /**
3274  * i40e_aq_set_hmc_resource_profile
3275  * @hw: pointer to the hw struct
3276  * @profile: type of profile the HMC is to be set as
3277  * @pe_vf_enabled_count: the number of PE enabled VFs the system has
3278  * @cmd_details: pointer to command details structure or NULL
3279  *
3280  * set the HMC profile of the device.
3281  **/
3282 enum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
3283                                 enum i40e_aq_hmc_profile profile,
3284                                 u8 pe_vf_enabled_count,
3285                                 struct i40e_asq_cmd_details *cmd_details)
3286 {
3287         struct i40e_aq_desc desc;
3288         struct i40e_aq_get_set_hmc_resource_profile *cmd =
3289                 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
3290         enum i40e_status_code status;
3291
3292         i40e_fill_default_direct_cmd_desc(&desc,
3293                                         i40e_aqc_opc_set_hmc_resource_profile);
3294
3295         cmd->pm_profile = (u8)profile;
3296         cmd->pe_vf_enabled = pe_vf_enabled_count;
3297
3298         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3299
3300         return status;
3301 }
3302
3303 /**
3304  * i40e_aq_request_resource
3305  * @hw: pointer to the hw struct
3306  * @resource: resource id
3307  * @access: access type
3308  * @sdp_number: resource number
3309  * @timeout: the maximum time in ms that the driver may hold the resource
3310  * @cmd_details: pointer to command details structure or NULL
3311  *
3312  * requests common resource using the admin queue commands
3313  **/
3314 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3315                                 enum i40e_aq_resources_ids resource,
3316                                 enum i40e_aq_resource_access_type access,
3317                                 u8 sdp_number, u64 *timeout,
3318                                 struct i40e_asq_cmd_details *cmd_details)
3319 {
3320         struct i40e_aq_desc desc;
3321         struct i40e_aqc_request_resource *cmd_resp =
3322                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3323         enum i40e_status_code status;
3324
3325         DEBUGFUNC("i40e_aq_request_resource");
3326
3327         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3328
3329         cmd_resp->resource_id = CPU_TO_LE16(resource);
3330         cmd_resp->access_type = CPU_TO_LE16(access);
3331         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3332
3333         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3334         /* The completion specifies the maximum time in ms that the driver
3335          * may hold the resource in the Timeout field.
3336          * If the resource is held by someone else, the command completes with
3337          * busy return value and the timeout field indicates the maximum time
3338          * the current owner of the resource has to free it.
3339          */
3340         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3341                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3342
3343         return status;
3344 }
3345
3346 /**
3347  * i40e_aq_release_resource
3348  * @hw: pointer to the hw struct
3349  * @resource: resource id
3350  * @sdp_number: resource number
3351  * @cmd_details: pointer to command details structure or NULL
3352  *
3353  * release common resource using the admin queue commands
3354  **/
3355 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3356                                 enum i40e_aq_resources_ids resource,
3357                                 u8 sdp_number,
3358                                 struct i40e_asq_cmd_details *cmd_details)
3359 {
3360         struct i40e_aq_desc desc;
3361         struct i40e_aqc_request_resource *cmd =
3362                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3363         enum i40e_status_code status;
3364
3365         DEBUGFUNC("i40e_aq_release_resource");
3366
3367         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3368
3369         cmd->resource_id = CPU_TO_LE16(resource);
3370         cmd->resource_number = CPU_TO_LE32(sdp_number);
3371
3372         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3373
3374         return status;
3375 }
3376
3377 /**
3378  * i40e_aq_read_nvm
3379  * @hw: pointer to the hw struct
3380  * @module_pointer: module pointer location in words from the NVM beginning
3381  * @offset: byte offset from the module beginning
3382  * @length: length of the section to be read (in bytes from the offset)
3383  * @data: command buffer (size [bytes] = length)
3384  * @last_command: tells if this is the last command in a series
3385  * @cmd_details: pointer to command details structure or NULL
3386  *
3387  * Read the NVM using the admin queue commands
3388  **/
3389 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3390                                 u32 offset, u16 length, void *data,
3391                                 bool last_command,
3392                                 struct i40e_asq_cmd_details *cmd_details)
3393 {
3394         struct i40e_aq_desc desc;
3395         struct i40e_aqc_nvm_update *cmd =
3396                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3397         enum i40e_status_code status;
3398
3399         DEBUGFUNC("i40e_aq_read_nvm");
3400
3401         /* In offset the highest byte must be zeroed. */
3402         if (offset & 0xFF000000) {
3403                 status = I40E_ERR_PARAM;
3404                 goto i40e_aq_read_nvm_exit;
3405         }
3406
3407         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3408
3409         /* If this is the last command in a series, set the proper flag. */
3410         if (last_command)
3411                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3412         cmd->module_pointer = module_pointer;
3413         cmd->offset = CPU_TO_LE32(offset);
3414         cmd->length = CPU_TO_LE16(length);
3415
3416         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3417         if (length > I40E_AQ_LARGE_BUF)
3418                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3419
3420         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3421
3422 i40e_aq_read_nvm_exit:
3423         return status;
3424 }
3425
3426 /**
3427  * i40e_aq_read_nvm_config - read an nvm config block
3428  * @hw: pointer to the hw struct
3429  * @cmd_flags: NVM access admin command bits
3430  * @field_id: field or feature id
3431  * @data: buffer for result
3432  * @buf_size: buffer size
3433  * @element_count: pointer to count of elements read by FW
3434  * @cmd_details: pointer to command details structure or NULL
3435  **/
3436 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3437                                 u8 cmd_flags, u32 field_id, void *data,
3438                                 u16 buf_size, u16 *element_count,
3439                                 struct i40e_asq_cmd_details *cmd_details)
3440 {
3441         struct i40e_aq_desc desc;
3442         struct i40e_aqc_nvm_config_read *cmd =
3443                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3444         enum i40e_status_code status;
3445
3446         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3447         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3448         if (buf_size > I40E_AQ_LARGE_BUF)
3449                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3450
3451         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3452         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3453         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3454                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3455         else
3456                 cmd->element_id_msw = 0;
3457
3458         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3459
3460         if (!status && element_count)
3461                 *element_count = LE16_TO_CPU(cmd->element_count);
3462
3463         return status;
3464 }
3465
3466 /**
3467  * i40e_aq_write_nvm_config - write an nvm config block
3468  * @hw: pointer to the hw struct
3469  * @cmd_flags: NVM access admin command bits
3470  * @data: buffer for result
3471  * @buf_size: buffer size
3472  * @element_count: count of elements to be written
3473  * @cmd_details: pointer to command details structure or NULL
3474  **/
3475 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3476                                 u8 cmd_flags, void *data, u16 buf_size,
3477                                 u16 element_count,
3478                                 struct i40e_asq_cmd_details *cmd_details)
3479 {
3480         struct i40e_aq_desc desc;
3481         struct i40e_aqc_nvm_config_write *cmd =
3482                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3483         enum i40e_status_code status;
3484
3485         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3486         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3487         if (buf_size > I40E_AQ_LARGE_BUF)
3488                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3489
3490         cmd->element_count = CPU_TO_LE16(element_count);
3491         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3492         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3493
3494         return status;
3495 }
3496
3497 /**
3498  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3499  * @hw: pointer to the hw struct
3500  * @cmd_details: pointer to command details structure or NULL
3501  **/
3502 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3503                                 void *buff, u16 buff_size,
3504                                 struct i40e_asq_cmd_details *cmd_details)
3505 {
3506         struct i40e_aq_desc desc;
3507         enum i40e_status_code status;
3508
3509         UNREFERENCED_2PARAMETER(buff, buff_size);
3510
3511         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3512         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3513         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3514                 status = I40E_ERR_NOT_IMPLEMENTED;
3515
3516         return status;
3517 }
3518
3519 /**
3520  * i40e_aq_erase_nvm
3521  * @hw: pointer to the hw struct
3522  * @module_pointer: module pointer location in words from the NVM beginning
3523  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3524  * @length: length of the section to be erased (expressed in 4 KB)
3525  * @last_command: tells if this is the last command in a series
3526  * @cmd_details: pointer to command details structure or NULL
3527  *
3528  * Erase the NVM sector using the admin queue commands
3529  **/
3530 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3531                                 u32 offset, u16 length, bool last_command,
3532                                 struct i40e_asq_cmd_details *cmd_details)
3533 {
3534         struct i40e_aq_desc desc;
3535         struct i40e_aqc_nvm_update *cmd =
3536                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3537         enum i40e_status_code status;
3538
3539         DEBUGFUNC("i40e_aq_erase_nvm");
3540
3541         /* In offset the highest byte must be zeroed. */
3542         if (offset & 0xFF000000) {
3543                 status = I40E_ERR_PARAM;
3544                 goto i40e_aq_erase_nvm_exit;
3545         }
3546
3547         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3548
3549         /* If this is the last command in a series, set the proper flag. */
3550         if (last_command)
3551                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3552         cmd->module_pointer = module_pointer;
3553         cmd->offset = CPU_TO_LE32(offset);
3554         cmd->length = CPU_TO_LE16(length);
3555
3556         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3557
3558 i40e_aq_erase_nvm_exit:
3559         return status;
3560 }
3561
3562 /**
3563  * i40e_parse_discover_capabilities
3564  * @hw: pointer to the hw struct
3565  * @buff: pointer to a buffer containing device/function capability records
3566  * @cap_count: number of capability records in the list
3567  * @list_type_opc: type of capabilities list to parse
3568  *
3569  * Parse the device/function capabilities list.
3570  **/
3571 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3572                                      u32 cap_count,
3573                                      enum i40e_admin_queue_opc list_type_opc)
3574 {
3575         struct i40e_aqc_list_capabilities_element_resp *cap;
3576         u32 valid_functions, num_functions;
3577         u32 number, logical_id, phys_id;
3578         struct i40e_hw_capabilities *p;
3579         u8 major_rev;
3580         u32 i = 0;
3581         u16 id;
3582
3583         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3584
3585         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3586                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3587         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3588                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3589         else
3590                 return;
3591
3592         for (i = 0; i < cap_count; i++, cap++) {
3593                 id = LE16_TO_CPU(cap->id);
3594                 number = LE32_TO_CPU(cap->number);
3595                 logical_id = LE32_TO_CPU(cap->logical_id);
3596                 phys_id = LE32_TO_CPU(cap->phys_id);
3597                 major_rev = cap->major_rev;
3598
3599                 switch (id) {
3600                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3601                         p->switch_mode = number;
3602                         i40e_debug(hw, I40E_DEBUG_INIT,
3603                                    "HW Capability: Switch mode = %d\n",
3604                                    p->switch_mode);
3605                         break;
3606                 case I40E_AQ_CAP_ID_MNG_MODE:
3607                         p->management_mode = number;
3608                         i40e_debug(hw, I40E_DEBUG_INIT,
3609                                    "HW Capability: Management Mode = %d\n",
3610                                    p->management_mode);
3611                         break;
3612                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3613                         p->npar_enable = number;
3614                         i40e_debug(hw, I40E_DEBUG_INIT,
3615                                    "HW Capability: NPAR enable = %d\n",
3616                                    p->npar_enable);
3617                         break;
3618                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3619                         p->os2bmc = number;
3620                         i40e_debug(hw, I40E_DEBUG_INIT,
3621                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3622                         break;
3623                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3624                         p->valid_functions = number;
3625                         i40e_debug(hw, I40E_DEBUG_INIT,
3626                                    "HW Capability: Valid Functions = %d\n",
3627                                    p->valid_functions);
3628                         break;
3629                 case I40E_AQ_CAP_ID_SRIOV:
3630                         if (number == 1)
3631                                 p->sr_iov_1_1 = true;
3632                         i40e_debug(hw, I40E_DEBUG_INIT,
3633                                    "HW Capability: SR-IOV = %d\n",
3634                                    p->sr_iov_1_1);
3635                         break;
3636                 case I40E_AQ_CAP_ID_VF:
3637                         p->num_vfs = number;
3638                         p->vf_base_id = logical_id;
3639                         i40e_debug(hw, I40E_DEBUG_INIT,
3640                                    "HW Capability: VF count = %d\n",
3641                                    p->num_vfs);
3642                         i40e_debug(hw, I40E_DEBUG_INIT,
3643                                    "HW Capability: VF base_id = %d\n",
3644                                    p->vf_base_id);
3645                         break;
3646                 case I40E_AQ_CAP_ID_VMDQ:
3647                         if (number == 1)
3648                                 p->vmdq = true;
3649                         i40e_debug(hw, I40E_DEBUG_INIT,
3650                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3651                         break;
3652                 case I40E_AQ_CAP_ID_8021QBG:
3653                         if (number == 1)
3654                                 p->evb_802_1_qbg = true;
3655                         i40e_debug(hw, I40E_DEBUG_INIT,
3656                                    "HW Capability: 802.1Qbg = %d\n", number);
3657                         break;
3658                 case I40E_AQ_CAP_ID_8021QBR:
3659                         if (number == 1)
3660                                 p->evb_802_1_qbh = true;
3661                         i40e_debug(hw, I40E_DEBUG_INIT,
3662                                    "HW Capability: 802.1Qbh = %d\n", number);
3663                         break;
3664                 case I40E_AQ_CAP_ID_VSI:
3665                         p->num_vsis = number;
3666                         i40e_debug(hw, I40E_DEBUG_INIT,
3667                                    "HW Capability: VSI count = %d\n",
3668                                    p->num_vsis);
3669                         break;
3670                 case I40E_AQ_CAP_ID_DCB:
3671                         if (number == 1) {
3672                                 p->dcb = true;
3673                                 p->enabled_tcmap = logical_id;
3674                                 p->maxtc = phys_id;
3675                         }
3676                         i40e_debug(hw, I40E_DEBUG_INIT,
3677                                    "HW Capability: DCB = %d\n", p->dcb);
3678                         i40e_debug(hw, I40E_DEBUG_INIT,
3679                                    "HW Capability: TC Mapping = %d\n",
3680                                    logical_id);
3681                         i40e_debug(hw, I40E_DEBUG_INIT,
3682                                    "HW Capability: TC Max = %d\n", p->maxtc);
3683                         break;
3684                 case I40E_AQ_CAP_ID_FCOE:
3685                         if (number == 1)
3686                                 p->fcoe = true;
3687                         i40e_debug(hw, I40E_DEBUG_INIT,
3688                                    "HW Capability: FCOE = %d\n", p->fcoe);
3689                         break;
3690                 case I40E_AQ_CAP_ID_ISCSI:
3691                         if (number == 1)
3692                                 p->iscsi = true;
3693                         i40e_debug(hw, I40E_DEBUG_INIT,
3694                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3695                         break;
3696                 case I40E_AQ_CAP_ID_RSS:
3697                         p->rss = true;
3698                         p->rss_table_size = number;
3699                         p->rss_table_entry_width = logical_id;
3700                         i40e_debug(hw, I40E_DEBUG_INIT,
3701                                    "HW Capability: RSS = %d\n", p->rss);
3702                         i40e_debug(hw, I40E_DEBUG_INIT,
3703                                    "HW Capability: RSS table size = %d\n",
3704                                    p->rss_table_size);
3705                         i40e_debug(hw, I40E_DEBUG_INIT,
3706                                    "HW Capability: RSS table width = %d\n",
3707                                    p->rss_table_entry_width);
3708                         break;
3709                 case I40E_AQ_CAP_ID_RXQ:
3710                         p->num_rx_qp = number;
3711                         p->base_queue = phys_id;
3712                         i40e_debug(hw, I40E_DEBUG_INIT,
3713                                    "HW Capability: Rx QP = %d\n", number);
3714                         i40e_debug(hw, I40E_DEBUG_INIT,
3715                                    "HW Capability: base_queue = %d\n",
3716                                    p->base_queue);
3717                         break;
3718                 case I40E_AQ_CAP_ID_TXQ:
3719                         p->num_tx_qp = number;
3720                         p->base_queue = phys_id;
3721                         i40e_debug(hw, I40E_DEBUG_INIT,
3722                                    "HW Capability: Tx QP = %d\n", number);
3723                         i40e_debug(hw, I40E_DEBUG_INIT,
3724                                    "HW Capability: base_queue = %d\n",
3725                                    p->base_queue);
3726                         break;
3727                 case I40E_AQ_CAP_ID_MSIX:
3728                         p->num_msix_vectors = number;
3729                         i40e_debug(hw, I40E_DEBUG_INIT,
3730                                    "HW Capability: MSIX vector count = %d\n",
3731                                    p->num_msix_vectors_vf);
3732                         break;
3733                 case I40E_AQ_CAP_ID_VF_MSIX:
3734                         p->num_msix_vectors_vf = number;
3735                         i40e_debug(hw, I40E_DEBUG_INIT,
3736                                    "HW Capability: MSIX VF vector count = %d\n",
3737                                    p->num_msix_vectors_vf);
3738                         break;
3739                 case I40E_AQ_CAP_ID_FLEX10:
3740                         if (major_rev == 1) {
3741                                 if (number == 1) {
3742                                         p->flex10_enable = true;
3743                                         p->flex10_capable = true;
3744                                 }
3745                         } else {
3746                                 /* Capability revision >= 2 */
3747                                 if (number & 1)
3748                                         p->flex10_enable = true;
3749                                 if (number & 2)
3750                                         p->flex10_capable = true;
3751                         }
3752                         p->flex10_mode = logical_id;
3753                         p->flex10_status = phys_id;
3754                         i40e_debug(hw, I40E_DEBUG_INIT,
3755                                    "HW Capability: Flex10 mode = %d\n",
3756                                    p->flex10_mode);
3757                         i40e_debug(hw, I40E_DEBUG_INIT,
3758                                    "HW Capability: Flex10 status = %d\n",
3759                                    p->flex10_status);
3760                         break;
3761                 case I40E_AQ_CAP_ID_CEM:
3762                         if (number == 1)
3763                                 p->mgmt_cem = true;
3764                         i40e_debug(hw, I40E_DEBUG_INIT,
3765                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3766                         break;
3767                 case I40E_AQ_CAP_ID_IWARP:
3768                         if (number == 1)
3769                                 p->iwarp = true;
3770                         i40e_debug(hw, I40E_DEBUG_INIT,
3771                                    "HW Capability: iWARP = %d\n", p->iwarp);
3772                         break;
3773                 case I40E_AQ_CAP_ID_LED:
3774                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3775                                 p->led[phys_id] = true;
3776                         i40e_debug(hw, I40E_DEBUG_INIT,
3777                                    "HW Capability: LED - PIN %d\n", phys_id);
3778                         break;
3779                 case I40E_AQ_CAP_ID_SDP:
3780                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3781                                 p->sdp[phys_id] = true;
3782                         i40e_debug(hw, I40E_DEBUG_INIT,
3783                                    "HW Capability: SDP - PIN %d\n", phys_id);
3784                         break;
3785                 case I40E_AQ_CAP_ID_MDIO:
3786                         if (number == 1) {
3787                                 p->mdio_port_num = phys_id;
3788                                 p->mdio_port_mode = logical_id;
3789                         }
3790                         i40e_debug(hw, I40E_DEBUG_INIT,
3791                                    "HW Capability: MDIO port number = %d\n",
3792                                    p->mdio_port_num);
3793                         i40e_debug(hw, I40E_DEBUG_INIT,
3794                                    "HW Capability: MDIO port mode = %d\n",
3795                                    p->mdio_port_mode);
3796                         break;
3797                 case I40E_AQ_CAP_ID_1588:
3798                         if (number == 1)
3799                                 p->ieee_1588 = true;
3800                         i40e_debug(hw, I40E_DEBUG_INIT,
3801                                    "HW Capability: IEEE 1588 = %d\n",
3802                                    p->ieee_1588);
3803                         break;
3804                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3805                         p->fd = true;
3806                         p->fd_filters_guaranteed = number;
3807                         p->fd_filters_best_effort = logical_id;
3808                         i40e_debug(hw, I40E_DEBUG_INIT,
3809                                    "HW Capability: Flow Director = 1\n");
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: Guaranteed FD filters = %d\n",
3812                                    p->fd_filters_guaranteed);
3813                         break;
3814                 case I40E_AQ_CAP_ID_WSR_PROT:
3815                         p->wr_csr_prot = (u64)number;
3816                         p->wr_csr_prot |= (u64)logical_id << 32;
3817                         i40e_debug(hw, I40E_DEBUG_INIT,
3818                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3819                                    (p->wr_csr_prot & 0xffff));
3820                         break;
3821 #ifdef X722_SUPPORT
3822                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3823                         hw->num_wol_proxy_filters = (u16)number;
3824                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3825                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3826                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3827                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3828                         else
3829                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3830                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3831                         p->proxy_support = p->proxy_support;
3832                         i40e_debug(hw, I40E_DEBUG_INIT,
3833                                    "HW Capability: WOL proxy filters = %d\n",
3834                                    hw->num_wol_proxy_filters);
3835                         break;
3836 #endif
3837                 default:
3838                         break;
3839                 }
3840         }
3841
3842         if (p->fcoe)
3843                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3844
3845 #ifdef I40E_FCOE_ENA
3846         /* Software override ensuring FCoE is disabled if npar or mfp
3847          * mode because it is not supported in these modes.
3848          */
3849         if (p->npar_enable || p->flex10_enable)
3850                 p->fcoe = false;
3851 #else
3852         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3853         p->fcoe = false;
3854 #endif
3855
3856         /* count the enabled ports (aka the "not disabled" ports) */
3857         hw->num_ports = 0;
3858         for (i = 0; i < 4; i++) {
3859                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3860                 u64 port_cfg = 0;
3861
3862                 /* use AQ read to get the physical register offset instead
3863                  * of the port relative offset
3864                  */
3865                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3866                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3867                         hw->num_ports++;
3868         }
3869
3870         valid_functions = p->valid_functions;
3871         num_functions = 0;
3872         while (valid_functions) {
3873                 if (valid_functions & 1)
3874                         num_functions++;
3875                 valid_functions >>= 1;
3876         }
3877
3878         /* partition id is 1-based, and functions are evenly spread
3879          * across the ports as partitions
3880          */
3881         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3882         hw->num_partitions = num_functions / hw->num_ports;
3883
3884         /* additional HW specific goodies that might
3885          * someday be HW version specific
3886          */
3887         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3888 }
3889
3890 /**
3891  * i40e_aq_discover_capabilities
3892  * @hw: pointer to the hw struct
3893  * @buff: a virtual buffer to hold the capabilities
3894  * @buff_size: Size of the virtual buffer
3895  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3896  * @list_type_opc: capabilities type to discover - pass in the command opcode
3897  * @cmd_details: pointer to command details structure or NULL
3898  *
3899  * Get the device capabilities descriptions from the firmware
3900  **/
3901 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
3902                                 void *buff, u16 buff_size, u16 *data_size,
3903                                 enum i40e_admin_queue_opc list_type_opc,
3904                                 struct i40e_asq_cmd_details *cmd_details)
3905 {
3906         struct i40e_aqc_list_capabilites *cmd;
3907         struct i40e_aq_desc desc;
3908         enum i40e_status_code status = I40E_SUCCESS;
3909
3910         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3911
3912         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3913                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3914                 status = I40E_ERR_PARAM;
3915                 goto exit;
3916         }
3917
3918         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3919
3920         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3921         if (buff_size > I40E_AQ_LARGE_BUF)
3922                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3923
3924         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3925         *data_size = LE16_TO_CPU(desc.datalen);
3926
3927         if (status)
3928                 goto exit;
3929
3930         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
3931                                          list_type_opc);
3932
3933 exit:
3934         return status;
3935 }
3936
3937 /**
3938  * i40e_aq_update_nvm
3939  * @hw: pointer to the hw struct
3940  * @module_pointer: module pointer location in words from the NVM beginning
3941  * @offset: byte offset from the module beginning
3942  * @length: length of the section to be written (in bytes from the offset)
3943  * @data: command buffer (size [bytes] = length)
3944  * @last_command: tells if this is the last command in a series
3945  * @cmd_details: pointer to command details structure or NULL
3946  *
3947  * Update the NVM using the admin queue commands
3948  **/
3949 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3950                                 u32 offset, u16 length, void *data,
3951                                 bool last_command,
3952                                 struct i40e_asq_cmd_details *cmd_details)
3953 {
3954         struct i40e_aq_desc desc;
3955         struct i40e_aqc_nvm_update *cmd =
3956                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3957         enum i40e_status_code status;
3958
3959         DEBUGFUNC("i40e_aq_update_nvm");
3960
3961         /* In offset the highest byte must be zeroed. */
3962         if (offset & 0xFF000000) {
3963                 status = I40E_ERR_PARAM;
3964                 goto i40e_aq_update_nvm_exit;
3965         }
3966
3967         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3968
3969         /* If this is the last command in a series, set the proper flag. */
3970         if (last_command)
3971                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3972         cmd->module_pointer = module_pointer;
3973         cmd->offset = CPU_TO_LE32(offset);
3974         cmd->length = CPU_TO_LE16(length);
3975
3976         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3977         if (length > I40E_AQ_LARGE_BUF)
3978                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3979
3980         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3981
3982 i40e_aq_update_nvm_exit:
3983         return status;
3984 }
3985
3986 /**
3987  * i40e_aq_get_lldp_mib
3988  * @hw: pointer to the hw struct
3989  * @bridge_type: type of bridge requested
3990  * @mib_type: Local, Remote or both Local and Remote MIBs
3991  * @buff: pointer to a user supplied buffer to store the MIB block
3992  * @buff_size: size of the buffer (in bytes)
3993  * @local_len : length of the returned Local LLDP MIB
3994  * @remote_len: length of the returned Remote LLDP MIB
3995  * @cmd_details: pointer to command details structure or NULL
3996  *
3997  * Requests the complete LLDP MIB (entire packet).
3998  **/
3999 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4000                                 u8 mib_type, void *buff, u16 buff_size,
4001                                 u16 *local_len, u16 *remote_len,
4002                                 struct i40e_asq_cmd_details *cmd_details)
4003 {
4004         struct i40e_aq_desc desc;
4005         struct i40e_aqc_lldp_get_mib *cmd =
4006                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4007         struct i40e_aqc_lldp_get_mib *resp =
4008                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4009         enum i40e_status_code status;
4010
4011         if (buff_size == 0 || !buff)
4012                 return I40E_ERR_PARAM;
4013
4014         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4015         /* Indirect Command */
4016         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4017
4018         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4019         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4020                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4021
4022         desc.datalen = CPU_TO_LE16(buff_size);
4023
4024         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4025         if (buff_size > I40E_AQ_LARGE_BUF)
4026                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4027
4028         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4029         if (!status) {
4030                 if (local_len != NULL)
4031                         *local_len = LE16_TO_CPU(resp->local_len);
4032                 if (remote_len != NULL)
4033                         *remote_len = LE16_TO_CPU(resp->remote_len);
4034         }
4035
4036         return status;
4037 }
4038
4039  /**
4040  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4041  * @hw: pointer to the hw struct
4042  * @mib_type: Local, Remote or both Local and Remote MIBs
4043  * @buff: pointer to a user supplied buffer to store the MIB block
4044  * @buff_size: size of the buffer (in bytes)
4045  * @cmd_details: pointer to command details structure or NULL
4046  *
4047  * Set the LLDP MIB.
4048  **/
4049 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4050                                 u8 mib_type, void *buff, u16 buff_size,
4051                                 struct i40e_asq_cmd_details *cmd_details)
4052 {
4053         struct i40e_aq_desc desc;
4054         struct i40e_aqc_lldp_set_local_mib *cmd =
4055                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4056         enum i40e_status_code status;
4057
4058         if (buff_size == 0 || !buff)
4059                 return I40E_ERR_PARAM;
4060
4061         i40e_fill_default_direct_cmd_desc(&desc,
4062                                 i40e_aqc_opc_lldp_set_local_mib);
4063         /* Indirect Command */
4064         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4065         if (buff_size > I40E_AQ_LARGE_BUF)
4066                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4067         desc.datalen = CPU_TO_LE16(buff_size);
4068
4069         cmd->type = mib_type;
4070         cmd->length = CPU_TO_LE16(buff_size);
4071         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4072         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4073
4074         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4075         return status;
4076 }
4077
4078 /**
4079  * i40e_aq_cfg_lldp_mib_change_event
4080  * @hw: pointer to the hw struct
4081  * @enable_update: Enable or Disable event posting
4082  * @cmd_details: pointer to command details structure or NULL
4083  *
4084  * Enable or Disable posting of an event on ARQ when LLDP MIB
4085  * associated with the interface changes
4086  **/
4087 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4088                                 bool enable_update,
4089                                 struct i40e_asq_cmd_details *cmd_details)
4090 {
4091         struct i40e_aq_desc desc;
4092         struct i40e_aqc_lldp_update_mib *cmd =
4093                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4094         enum i40e_status_code status;
4095
4096         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4097
4098         if (!enable_update)
4099                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4100
4101         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4102
4103         return status;
4104 }
4105
4106 /**
4107  * i40e_aq_add_lldp_tlv
4108  * @hw: pointer to the hw struct
4109  * @bridge_type: type of bridge
4110  * @buff: buffer with TLV to add
4111  * @buff_size: length of the buffer
4112  * @tlv_len: length of the TLV to be added
4113  * @mib_len: length of the LLDP MIB returned in response
4114  * @cmd_details: pointer to command details structure or NULL
4115  *
4116  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4117  * it is responsibility of the caller to make sure that the TLV is not
4118  * already present in the LLDPDU.
4119  * In return firmware will write the complete LLDP MIB with the newly
4120  * added TLV in the response buffer.
4121  **/
4122 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4123                                 void *buff, u16 buff_size, u16 tlv_len,
4124                                 u16 *mib_len,
4125                                 struct i40e_asq_cmd_details *cmd_details)
4126 {
4127         struct i40e_aq_desc desc;
4128         struct i40e_aqc_lldp_add_tlv *cmd =
4129                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4130         enum i40e_status_code status;
4131
4132         if (buff_size == 0 || !buff || tlv_len == 0)
4133                 return I40E_ERR_PARAM;
4134
4135         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4136
4137         /* Indirect Command */
4138         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4139         if (buff_size > I40E_AQ_LARGE_BUF)
4140                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4141         desc.datalen = CPU_TO_LE16(buff_size);
4142
4143         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4144                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4145         cmd->len = CPU_TO_LE16(tlv_len);
4146
4147         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4148         if (!status) {
4149                 if (mib_len != NULL)
4150                         *mib_len = LE16_TO_CPU(desc.datalen);
4151         }
4152
4153         return status;
4154 }
4155
4156 /**
4157  * i40e_aq_update_lldp_tlv
4158  * @hw: pointer to the hw struct
4159  * @bridge_type: type of bridge
4160  * @buff: buffer with TLV to update
4161  * @buff_size: size of the buffer holding original and updated TLVs
4162  * @old_len: Length of the Original TLV
4163  * @new_len: Length of the Updated TLV
4164  * @offset: offset of the updated TLV in the buff
4165  * @mib_len: length of the returned LLDP MIB
4166  * @cmd_details: pointer to command details structure or NULL
4167  *
4168  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4169  * Firmware will place the complete LLDP MIB in response buffer with the
4170  * updated TLV.
4171  **/
4172 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4173                                 u8 bridge_type, void *buff, u16 buff_size,
4174                                 u16 old_len, u16 new_len, u16 offset,
4175                                 u16 *mib_len,
4176                                 struct i40e_asq_cmd_details *cmd_details)
4177 {
4178         struct i40e_aq_desc desc;
4179         struct i40e_aqc_lldp_update_tlv *cmd =
4180                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4181         enum i40e_status_code status;
4182
4183         if (buff_size == 0 || !buff || offset == 0 ||
4184             old_len == 0 || new_len == 0)
4185                 return I40E_ERR_PARAM;
4186
4187         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4188
4189         /* Indirect Command */
4190         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4191         if (buff_size > I40E_AQ_LARGE_BUF)
4192                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4193         desc.datalen = CPU_TO_LE16(buff_size);
4194
4195         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4196                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4197         cmd->old_len = CPU_TO_LE16(old_len);
4198         cmd->new_offset = CPU_TO_LE16(offset);
4199         cmd->new_len = CPU_TO_LE16(new_len);
4200
4201         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4202         if (!status) {
4203                 if (mib_len != NULL)
4204                         *mib_len = LE16_TO_CPU(desc.datalen);
4205         }
4206
4207         return status;
4208 }
4209
4210 /**
4211  * i40e_aq_delete_lldp_tlv
4212  * @hw: pointer to the hw struct
4213  * @bridge_type: type of bridge
4214  * @buff: pointer to a user supplied buffer that has the TLV
4215  * @buff_size: length of the buffer
4216  * @tlv_len: length of the TLV to be deleted
4217  * @mib_len: length of the returned LLDP MIB
4218  * @cmd_details: pointer to command details structure or NULL
4219  *
4220  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4221  * The firmware places the entire LLDP MIB in the response buffer.
4222  **/
4223 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4224                                 u8 bridge_type, void *buff, u16 buff_size,
4225                                 u16 tlv_len, u16 *mib_len,
4226                                 struct i40e_asq_cmd_details *cmd_details)
4227 {
4228         struct i40e_aq_desc desc;
4229         struct i40e_aqc_lldp_add_tlv *cmd =
4230                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4231         enum i40e_status_code status;
4232
4233         if (buff_size == 0 || !buff)
4234                 return I40E_ERR_PARAM;
4235
4236         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4237
4238         /* Indirect Command */
4239         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4240         if (buff_size > I40E_AQ_LARGE_BUF)
4241                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4242         desc.datalen = CPU_TO_LE16(buff_size);
4243         cmd->len = CPU_TO_LE16(tlv_len);
4244         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4245                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4246
4247         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4248         if (!status) {
4249                 if (mib_len != NULL)
4250                         *mib_len = LE16_TO_CPU(desc.datalen);
4251         }
4252
4253         return status;
4254 }
4255
4256 /**
4257  * i40e_aq_stop_lldp
4258  * @hw: pointer to the hw struct
4259  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4260  * @cmd_details: pointer to command details structure or NULL
4261  *
4262  * Stop or Shutdown the embedded LLDP Agent
4263  **/
4264 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4265                                 struct i40e_asq_cmd_details *cmd_details)
4266 {
4267         struct i40e_aq_desc desc;
4268         struct i40e_aqc_lldp_stop *cmd =
4269                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4270         enum i40e_status_code status;
4271
4272         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4273
4274         if (shutdown_agent)
4275                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4276
4277         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4278
4279         return status;
4280 }
4281
4282 /**
4283  * i40e_aq_start_lldp
4284  * @hw: pointer to the hw struct
4285  * @cmd_details: pointer to command details structure or NULL
4286  *
4287  * Start the embedded LLDP Agent on all ports.
4288  **/
4289 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4290                                 struct i40e_asq_cmd_details *cmd_details)
4291 {
4292         struct i40e_aq_desc desc;
4293         struct i40e_aqc_lldp_start *cmd =
4294                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4295         enum i40e_status_code status;
4296
4297         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4298
4299         cmd->command = I40E_AQ_LLDP_AGENT_START;
4300
4301         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4302
4303         return status;
4304 }
4305
4306 /**
4307  * i40e_aq_get_cee_dcb_config
4308  * @hw: pointer to the hw struct
4309  * @buff: response buffer that stores CEE operational configuration
4310  * @buff_size: size of the buffer passed
4311  * @cmd_details: pointer to command details structure or NULL
4312  *
4313  * Get CEE DCBX mode operational configuration from firmware
4314  **/
4315 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4316                                 void *buff, u16 buff_size,
4317                                 struct i40e_asq_cmd_details *cmd_details)
4318 {
4319         struct i40e_aq_desc desc;
4320         enum i40e_status_code status;
4321
4322         if (buff_size == 0 || !buff)
4323                 return I40E_ERR_PARAM;
4324
4325         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4326
4327         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4328         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4329                                        cmd_details);
4330
4331         return status;
4332 }
4333
4334 /**
4335  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4336  * @hw: pointer to the hw struct
4337  * @start_agent: True if DCBx Agent needs to be Started
4338  *                              False if DCBx Agent needs to be Stopped
4339  * @cmd_details: pointer to command details structure or NULL
4340  *
4341  * Start/Stop the embedded dcbx Agent
4342  **/
4343 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4344                                 bool start_agent,
4345                                 struct i40e_asq_cmd_details *cmd_details)
4346 {
4347         struct i40e_aq_desc desc;
4348         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4349                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4350                                 &desc.params.raw;
4351         enum i40e_status_code status;
4352
4353         i40e_fill_default_direct_cmd_desc(&desc,
4354                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4355
4356         if (start_agent)
4357                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4358
4359         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4360
4361         return status;
4362 }
4363
4364 /**
4365  * i40e_aq_add_udp_tunnel
4366  * @hw: pointer to the hw struct
4367  * @udp_port: the UDP port to add
4368  * @header_len: length of the tunneling header length in DWords
4369  * @protocol_index: protocol index type
4370  * @filter_index: pointer to filter index
4371  * @cmd_details: pointer to command details structure or NULL
4372  **/
4373 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4374                                 u16 udp_port, u8 protocol_index,
4375                                 u8 *filter_index,
4376                                 struct i40e_asq_cmd_details *cmd_details)
4377 {
4378         struct i40e_aq_desc desc;
4379         struct i40e_aqc_add_udp_tunnel *cmd =
4380                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4381         struct i40e_aqc_del_udp_tunnel_completion *resp =
4382                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4383         enum i40e_status_code status;
4384
4385         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4386
4387         cmd->udp_port = CPU_TO_LE16(udp_port);
4388         cmd->protocol_type = protocol_index;
4389
4390         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4391
4392         if (!status && filter_index)
4393                 *filter_index = resp->index;
4394
4395         return status;
4396 }
4397
4398 /**
4399  * i40e_aq_del_udp_tunnel
4400  * @hw: pointer to the hw struct
4401  * @index: filter index
4402  * @cmd_details: pointer to command details structure or NULL
4403  **/
4404 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4405                                 struct i40e_asq_cmd_details *cmd_details)
4406 {
4407         struct i40e_aq_desc desc;
4408         struct i40e_aqc_remove_udp_tunnel *cmd =
4409                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4410         enum i40e_status_code status;
4411
4412         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4413
4414         cmd->index = index;
4415
4416         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4417
4418         return status;
4419 }
4420
4421 /**
4422  * i40e_aq_get_switch_resource_alloc (0x0204)
4423  * @hw: pointer to the hw struct
4424  * @num_entries: pointer to u8 to store the number of resource entries returned
4425  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4426  *        to store the resource information for all resource types.  Each
4427  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4428  * @count: size, in bytes, of the buffer provided
4429  * @cmd_details: pointer to command details structure or NULL
4430  *
4431  * Query the resources allocated to a function.
4432  **/
4433 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4434                         u8 *num_entries,
4435                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4436                         u16 count,
4437                         struct i40e_asq_cmd_details *cmd_details)
4438 {
4439         struct i40e_aq_desc desc;
4440         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4441                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4442         enum i40e_status_code status;
4443         u16 length = count * sizeof(*buf);
4444
4445         i40e_fill_default_direct_cmd_desc(&desc,
4446                                         i40e_aqc_opc_get_switch_resource_alloc);
4447
4448         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4449         if (length > I40E_AQ_LARGE_BUF)
4450                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4451
4452         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4453
4454         if (!status && num_entries)
4455                 *num_entries = cmd_resp->num_entries;
4456
4457         return status;
4458 }
4459
4460 /**
4461  * i40e_aq_delete_element - Delete switch element
4462  * @hw: pointer to the hw struct
4463  * @seid: the SEID to delete from the switch
4464  * @cmd_details: pointer to command details structure or NULL
4465  *
4466  * This deletes a switch element from the switch.
4467  **/
4468 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4469                                 struct i40e_asq_cmd_details *cmd_details)
4470 {
4471         struct i40e_aq_desc desc;
4472         struct i40e_aqc_switch_seid *cmd =
4473                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4474         enum i40e_status_code status;
4475
4476         if (seid == 0)
4477                 return I40E_ERR_PARAM;
4478
4479         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4480
4481         cmd->seid = CPU_TO_LE16(seid);
4482
4483         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4484
4485         return status;
4486 }
4487
4488 /**
4489  * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4490  * @hw: pointer to the hw struct
4491  * @flags: component flags
4492  * @mac_seid: uplink seid (MAC SEID)
4493  * @vsi_seid: connected vsi seid
4494  * @ret_seid: seid of create pv component
4495  *
4496  * This instantiates an i40e port virtualizer with specified flags.
4497  * Depending on specified flags the port virtualizer can act as a
4498  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4499  */
4500 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4501                                        u16 mac_seid, u16 vsi_seid,
4502                                        u16 *ret_seid)
4503 {
4504         struct i40e_aq_desc desc;
4505         struct i40e_aqc_add_update_pv *cmd =
4506                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4507         struct i40e_aqc_add_update_pv_completion *resp =
4508                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4509         enum i40e_status_code status;
4510
4511         if (vsi_seid == 0)
4512                 return I40E_ERR_PARAM;
4513
4514         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4515         cmd->command_flags = CPU_TO_LE16(flags);
4516         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4517         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4518
4519         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4520         if (!status && ret_seid)
4521                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4522
4523         return status;
4524 }
4525
4526 /**
4527  * i40e_aq_add_tag - Add an S/E-tag
4528  * @hw: pointer to the hw struct
4529  * @direct_to_queue: should s-tag direct flow to a specific queue
4530  * @vsi_seid: VSI SEID to use this tag
4531  * @tag: value of the tag
4532  * @queue_num: queue number, only valid is direct_to_queue is true
4533  * @tags_used: return value, number of tags in use by this PF
4534  * @tags_free: return value, number of unallocated tags
4535  * @cmd_details: pointer to command details structure or NULL
4536  *
4537  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4538  * the number of tags allocated by the PF, and the number of unallocated
4539  * tags available.
4540  **/
4541 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4542                                 u16 vsi_seid, u16 tag, u16 queue_num,
4543                                 u16 *tags_used, u16 *tags_free,
4544                                 struct i40e_asq_cmd_details *cmd_details)
4545 {
4546         struct i40e_aq_desc desc;
4547         struct i40e_aqc_add_tag *cmd =
4548                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4549         struct i40e_aqc_add_remove_tag_completion *resp =
4550                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4551         enum i40e_status_code status;
4552
4553         if (vsi_seid == 0)
4554                 return I40E_ERR_PARAM;
4555
4556         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4557
4558         cmd->seid = CPU_TO_LE16(vsi_seid);
4559         cmd->tag = CPU_TO_LE16(tag);
4560         if (direct_to_queue) {
4561                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4562                 cmd->queue_number = CPU_TO_LE16(queue_num);
4563         }
4564
4565         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4566
4567         if (!status) {
4568                 if (tags_used != NULL)
4569                         *tags_used = LE16_TO_CPU(resp->tags_used);
4570                 if (tags_free != NULL)
4571                         *tags_free = LE16_TO_CPU(resp->tags_free);
4572         }
4573
4574         return status;
4575 }
4576
4577 /**
4578  * i40e_aq_remove_tag - Remove an S- or E-tag
4579  * @hw: pointer to the hw struct
4580  * @vsi_seid: VSI SEID this tag is associated with
4581  * @tag: value of the S-tag to delete
4582  * @tags_used: return value, number of tags in use by this PF
4583  * @tags_free: return value, number of unallocated tags
4584  * @cmd_details: pointer to command details structure or NULL
4585  *
4586  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4587  * the number of tags allocated by the PF, and the number of unallocated
4588  * tags available.
4589  **/
4590 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4591                                 u16 tag, u16 *tags_used, u16 *tags_free,
4592                                 struct i40e_asq_cmd_details *cmd_details)
4593 {
4594         struct i40e_aq_desc desc;
4595         struct i40e_aqc_remove_tag *cmd =
4596                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4597         struct i40e_aqc_add_remove_tag_completion *resp =
4598                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4599         enum i40e_status_code status;
4600
4601         if (vsi_seid == 0)
4602                 return I40E_ERR_PARAM;
4603
4604         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4605
4606         cmd->seid = CPU_TO_LE16(vsi_seid);
4607         cmd->tag = CPU_TO_LE16(tag);
4608
4609         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4610
4611         if (!status) {
4612                 if (tags_used != NULL)
4613                         *tags_used = LE16_TO_CPU(resp->tags_used);
4614                 if (tags_free != NULL)
4615                         *tags_free = LE16_TO_CPU(resp->tags_free);
4616         }
4617
4618         return status;
4619 }
4620
4621 /**
4622  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4623  * @hw: pointer to the hw struct
4624  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4625  * @etag: value of E-tag to add
4626  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4627  * @buf: address of indirect buffer
4628  * @tags_used: return value, number of E-tags in use by this port
4629  * @tags_free: return value, number of unallocated M-tags
4630  * @cmd_details: pointer to command details structure or NULL
4631  *
4632  * This associates a multicast E-tag to a port virtualizer.  It will return
4633  * the number of tags allocated by the PF, and the number of unallocated
4634  * tags available.
4635  *
4636  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4637  * num_tags_in_buf long.
4638  **/
4639 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4640                                 u16 etag, u8 num_tags_in_buf, void *buf,
4641                                 u16 *tags_used, u16 *tags_free,
4642                                 struct i40e_asq_cmd_details *cmd_details)
4643 {
4644         struct i40e_aq_desc desc;
4645         struct i40e_aqc_add_remove_mcast_etag *cmd =
4646                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4647         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4648            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4649         enum i40e_status_code status;
4650         u16 length = sizeof(u16) * num_tags_in_buf;
4651
4652         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4653                 return I40E_ERR_PARAM;
4654
4655         i40e_fill_default_direct_cmd_desc(&desc,
4656                                           i40e_aqc_opc_add_multicast_etag);
4657
4658         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4659         cmd->etag = CPU_TO_LE16(etag);
4660         cmd->num_unicast_etags = num_tags_in_buf;
4661
4662         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4663         if (length > I40E_AQ_LARGE_BUF)
4664                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4665
4666         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4667
4668         if (!status) {
4669                 if (tags_used != NULL)
4670                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4671                 if (tags_free != NULL)
4672                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4673         }
4674
4675         return status;
4676 }
4677
4678 /**
4679  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4680  * @hw: pointer to the hw struct
4681  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4682  * @etag: value of the E-tag to remove
4683  * @tags_used: return value, number of tags in use by this port
4684  * @tags_free: return value, number of unallocated tags
4685  * @cmd_details: pointer to command details structure or NULL
4686  *
4687  * This deletes an E-tag from the port virtualizer.  It will return
4688  * the number of tags allocated by the port, and the number of unallocated
4689  * tags available.
4690  **/
4691 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4692                                 u16 etag, u16 *tags_used, u16 *tags_free,
4693                                 struct i40e_asq_cmd_details *cmd_details)
4694 {
4695         struct i40e_aq_desc desc;
4696         struct i40e_aqc_add_remove_mcast_etag *cmd =
4697                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4698         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4699            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4700         enum i40e_status_code status;
4701
4702
4703         if (pv_seid == 0)
4704                 return I40E_ERR_PARAM;
4705
4706         i40e_fill_default_direct_cmd_desc(&desc,
4707                                           i40e_aqc_opc_remove_multicast_etag);
4708
4709         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4710         cmd->etag = CPU_TO_LE16(etag);
4711
4712         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4713
4714         if (!status) {
4715                 if (tags_used != NULL)
4716                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4717                 if (tags_free != NULL)
4718                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4719         }
4720
4721         return status;
4722 }
4723
4724 /**
4725  * i40e_aq_update_tag - Update an S/E-tag
4726  * @hw: pointer to the hw struct
4727  * @vsi_seid: VSI SEID using this S-tag
4728  * @old_tag: old tag value
4729  * @new_tag: new tag value
4730  * @tags_used: return value, number of tags in use by this PF
4731  * @tags_free: return value, number of unallocated tags
4732  * @cmd_details: pointer to command details structure or NULL
4733  *
4734  * This updates the value of the tag currently attached to this VSI
4735  * in the switch complex.  It will return the number of tags allocated
4736  * by the PF, and the number of unallocated tags available.
4737  **/
4738 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
4739                                 u16 old_tag, u16 new_tag, u16 *tags_used,
4740                                 u16 *tags_free,
4741                                 struct i40e_asq_cmd_details *cmd_details)
4742 {
4743         struct i40e_aq_desc desc;
4744         struct i40e_aqc_update_tag *cmd =
4745                 (struct i40e_aqc_update_tag *)&desc.params.raw;
4746         struct i40e_aqc_update_tag_completion *resp =
4747                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
4748         enum i40e_status_code status;
4749
4750         if (vsi_seid == 0)
4751                 return I40E_ERR_PARAM;
4752
4753         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
4754
4755         cmd->seid = CPU_TO_LE16(vsi_seid);
4756         cmd->old_tag = CPU_TO_LE16(old_tag);
4757         cmd->new_tag = CPU_TO_LE16(new_tag);
4758
4759         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4760
4761         if (!status) {
4762                 if (tags_used != NULL)
4763                         *tags_used = LE16_TO_CPU(resp->tags_used);
4764                 if (tags_free != NULL)
4765                         *tags_free = LE16_TO_CPU(resp->tags_free);
4766         }
4767
4768         return status;
4769 }
4770
4771 /**
4772  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
4773  * @hw: pointer to the hw struct
4774  * @tcmap: TC map for request/release any ignore PFC condition
4775  * @request: request or release ignore PFC condition
4776  * @tcmap_ret: return TCs for which PFC is currently ignored
4777  * @cmd_details: pointer to command details structure or NULL
4778  *
4779  * This sends out request/release to ignore PFC condition for a TC.
4780  * It will return the TCs for which PFC is currently ignored.
4781  **/
4782 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
4783                                 bool request, u8 *tcmap_ret,
4784                                 struct i40e_asq_cmd_details *cmd_details)
4785 {
4786         struct i40e_aq_desc desc;
4787         struct i40e_aqc_pfc_ignore *cmd_resp =
4788                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
4789         enum i40e_status_code status;
4790
4791         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
4792
4793         if (request)
4794                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
4795
4796         cmd_resp->tc_bitmap = tcmap;
4797
4798         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4799
4800         if (!status) {
4801                 if (tcmap_ret != NULL)
4802                         *tcmap_ret = cmd_resp->tc_bitmap;
4803         }
4804
4805         return status;
4806 }
4807
4808 /**
4809  * i40e_aq_dcb_updated - DCB Updated Command
4810  * @hw: pointer to the hw struct
4811  * @cmd_details: pointer to command details structure or NULL
4812  *
4813  * When LLDP is handled in PF this command is used by the PF
4814  * to notify EMP that a DCB setting is modified.
4815  * When LLDP is handled in EMP this command is used by the PF
4816  * to notify EMP whenever one of the following parameters get
4817  * modified:
4818  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
4819  *   - PCIRTT in PRTDCB_GENC.PCIRTT
4820  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
4821  * EMP will return when the shared RPB settings have been
4822  * recomputed and modified. The retval field in the descriptor
4823  * will be set to 0 when RPB is modified.
4824  **/
4825 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
4826                                 struct i40e_asq_cmd_details *cmd_details)
4827 {
4828         struct i40e_aq_desc desc;
4829         enum i40e_status_code status;
4830
4831         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
4832
4833         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4834
4835         return status;
4836 }
4837
4838 /**
4839  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
4840  * @hw: pointer to the hw struct
4841  * @seid: defines the SEID of the switch for which the stats are requested
4842  * @vlan_id: the VLAN ID for which the statistics are requested
4843  * @stat_index: index of the statistics counters block assigned to this VLAN
4844  * @cmd_details: pointer to command details structure or NULL
4845  *
4846  * XL710 supports 128 smonVlanStats counters.This command is used to
4847  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
4848  * switch.
4849  **/
4850 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
4851                                 u16 vlan_id, u16 *stat_index,
4852                                 struct i40e_asq_cmd_details *cmd_details)
4853 {
4854         struct i40e_aq_desc desc;
4855         struct i40e_aqc_add_remove_statistics *cmd_resp =
4856                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4857         enum i40e_status_code status;
4858
4859         if ((seid == 0) || (stat_index == NULL))
4860                 return I40E_ERR_PARAM;
4861
4862         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
4863
4864         cmd_resp->seid = CPU_TO_LE16(seid);
4865         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
4866
4867         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4868
4869         if (!status && stat_index)
4870                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
4871
4872         return status;
4873 }
4874
4875 /**
4876  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
4877  * @hw: pointer to the hw struct
4878  * @seid: defines the SEID of the switch for which the stats are requested
4879  * @vlan_id: the VLAN ID for which the statistics are requested
4880  * @stat_index: index of the statistics counters block assigned to this VLAN
4881  * @cmd_details: pointer to command details structure or NULL
4882  *
4883  * XL710 supports 128 smonVlanStats counters.This command is used to
4884  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
4885  * switch.
4886  **/
4887 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
4888                                 u16 vlan_id, u16 stat_index,
4889                                 struct i40e_asq_cmd_details *cmd_details)
4890 {
4891         struct i40e_aq_desc desc;
4892         struct i40e_aqc_add_remove_statistics *cmd =
4893                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
4894         enum i40e_status_code status;
4895
4896         if (seid == 0)
4897                 return I40E_ERR_PARAM;
4898
4899         i40e_fill_default_direct_cmd_desc(&desc,
4900                                           i40e_aqc_opc_remove_statistics);
4901
4902         cmd->seid = CPU_TO_LE16(seid);
4903         cmd->vlan  = CPU_TO_LE16(vlan_id);
4904         cmd->stat_index = CPU_TO_LE16(stat_index);
4905
4906         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4907
4908         return status;
4909 }
4910
4911 /**
4912  * i40e_aq_set_port_parameters - set physical port parameters.
4913  * @hw: pointer to the hw struct
4914  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
4915  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
4916  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
4917  * @double_vlan: if set double VLAN is enabled
4918  * @cmd_details: pointer to command details structure or NULL
4919  **/
4920 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
4921                                 u16 bad_frame_vsi, bool save_bad_pac,
4922                                 bool pad_short_pac, bool double_vlan,
4923                                 struct i40e_asq_cmd_details *cmd_details)
4924 {
4925         struct i40e_aqc_set_port_parameters *cmd;
4926         enum i40e_status_code status;
4927         struct i40e_aq_desc desc;
4928         u16 command_flags = 0;
4929
4930         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
4931
4932         i40e_fill_default_direct_cmd_desc(&desc,
4933                                           i40e_aqc_opc_set_port_parameters);
4934
4935         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
4936         if (save_bad_pac)
4937                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
4938         if (pad_short_pac)
4939                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
4940         if (double_vlan)
4941                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
4942         cmd->command_flags = CPU_TO_LE16(command_flags);
4943
4944         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4945
4946         return status;
4947 }
4948
4949 /**
4950  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
4951  * @hw: pointer to the hw struct
4952  * @seid: seid for the physical port/switching component/vsi
4953  * @buff: Indirect buffer to hold data parameters and response
4954  * @buff_size: Indirect buffer size
4955  * @opcode: Tx scheduler AQ command opcode
4956  * @cmd_details: pointer to command details structure or NULL
4957  *
4958  * Generic command handler for Tx scheduler AQ commands
4959  **/
4960 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
4961                                 void *buff, u16 buff_size,
4962                                  enum i40e_admin_queue_opc opcode,
4963                                 struct i40e_asq_cmd_details *cmd_details)
4964 {
4965         struct i40e_aq_desc desc;
4966         struct i40e_aqc_tx_sched_ind *cmd =
4967                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4968         enum i40e_status_code status;
4969         bool cmd_param_flag = false;
4970
4971         switch (opcode) {
4972         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
4973         case i40e_aqc_opc_configure_vsi_tc_bw:
4974         case i40e_aqc_opc_enable_switching_comp_ets:
4975         case i40e_aqc_opc_modify_switching_comp_ets:
4976         case i40e_aqc_opc_disable_switching_comp_ets:
4977         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
4978         case i40e_aqc_opc_configure_switching_comp_bw_config:
4979                 cmd_param_flag = true;
4980                 break;
4981         case i40e_aqc_opc_query_vsi_bw_config:
4982         case i40e_aqc_opc_query_vsi_ets_sla_config:
4983         case i40e_aqc_opc_query_switching_comp_ets_config:
4984         case i40e_aqc_opc_query_port_ets_config:
4985         case i40e_aqc_opc_query_switching_comp_bw_config:
4986                 cmd_param_flag = false;
4987                 break;
4988         default:
4989                 return I40E_ERR_PARAM;
4990         }
4991
4992         i40e_fill_default_direct_cmd_desc(&desc, opcode);
4993
4994         /* Indirect command */
4995         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4996         if (cmd_param_flag)
4997                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
4998         if (buff_size > I40E_AQ_LARGE_BUF)
4999                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5000
5001         desc.datalen = CPU_TO_LE16(buff_size);
5002
5003         cmd->vsi_seid = CPU_TO_LE16(seid);
5004
5005         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5006
5007         return status;
5008 }
5009
5010 /**
5011  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5012  * @hw: pointer to the hw struct
5013  * @seid: VSI seid
5014  * @credit: BW limit credits (0 = disabled)
5015  * @max_credit: Max BW limit credits
5016  * @cmd_details: pointer to command details structure or NULL
5017  **/
5018 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5019                                 u16 seid, u16 credit, u8 max_credit,
5020                                 struct i40e_asq_cmd_details *cmd_details)
5021 {
5022         struct i40e_aq_desc desc;
5023         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5024                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5025         enum i40e_status_code status;
5026
5027         i40e_fill_default_direct_cmd_desc(&desc,
5028                                           i40e_aqc_opc_configure_vsi_bw_limit);
5029
5030         cmd->vsi_seid = CPU_TO_LE16(seid);
5031         cmd->credit = CPU_TO_LE16(credit);
5032         cmd->max_credit = max_credit;
5033
5034         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5035
5036         return status;
5037 }
5038
5039 /**
5040  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5041  * @hw: pointer to the hw struct
5042  * @seid: switching component seid
5043  * @credit: BW limit credits (0 = disabled)
5044  * @max_bw: Max BW limit credits
5045  * @cmd_details: pointer to command details structure or NULL
5046  **/
5047 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5048                                 u16 seid, u16 credit, u8 max_bw,
5049                                 struct i40e_asq_cmd_details *cmd_details)
5050 {
5051         struct i40e_aq_desc desc;
5052         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5053           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5054         enum i40e_status_code status;
5055
5056         i40e_fill_default_direct_cmd_desc(&desc,
5057                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5058
5059         cmd->seid = CPU_TO_LE16(seid);
5060         cmd->credit = CPU_TO_LE16(credit);
5061         cmd->max_bw = max_bw;
5062
5063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5064
5065         return status;
5066 }
5067
5068 /**
5069  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5070  * @hw: pointer to the hw struct
5071  * @seid: VSI seid
5072  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5073  * @cmd_details: pointer to command details structure or NULL
5074  **/
5075 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5076                         u16 seid,
5077                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5078                         struct i40e_asq_cmd_details *cmd_details)
5079 {
5080         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5081                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5082                                     cmd_details);
5083 }
5084
5085 /**
5086  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5087  * @hw: pointer to the hw struct
5088  * @seid: VSI seid
5089  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5090  * @cmd_details: pointer to command details structure or NULL
5091  **/
5092 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5093                         u16 seid,
5094                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5095                         struct i40e_asq_cmd_details *cmd_details)
5096 {
5097         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5098                                     i40e_aqc_opc_configure_vsi_tc_bw,
5099                                     cmd_details);
5100 }
5101
5102 /**
5103  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5104  * @hw: pointer to the hw struct
5105  * @seid: seid of the switching component connected to Physical Port
5106  * @ets_data: Buffer holding ETS parameters
5107  * @cmd_details: pointer to command details structure or NULL
5108  **/
5109 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5110                 u16 seid,
5111                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5112                 enum i40e_admin_queue_opc opcode,
5113                 struct i40e_asq_cmd_details *cmd_details)
5114 {
5115         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5116                                     sizeof(*ets_data), opcode, cmd_details);
5117 }
5118
5119 /**
5120  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5121  * @hw: pointer to the hw struct
5122  * @seid: seid of the switching component
5123  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5124  * @cmd_details: pointer to command details structure or NULL
5125  **/
5126 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5127         u16 seid,
5128         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5129         struct i40e_asq_cmd_details *cmd_details)
5130 {
5131         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5132                             i40e_aqc_opc_configure_switching_comp_bw_config,
5133                             cmd_details);
5134 }
5135
5136 /**
5137  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5138  * @hw: pointer to the hw struct
5139  * @seid: seid of the switching component
5140  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5141  * @cmd_details: pointer to command details structure or NULL
5142  **/
5143 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5144         struct i40e_hw *hw, u16 seid,
5145         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5146         struct i40e_asq_cmd_details *cmd_details)
5147 {
5148         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5149                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5150                             cmd_details);
5151 }
5152
5153 /**
5154  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5155  * @hw: pointer to the hw struct
5156  * @seid: seid of the VSI
5157  * @bw_data: Buffer to hold VSI BW configuration
5158  * @cmd_details: pointer to command details structure or NULL
5159  **/
5160 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5161                         u16 seid,
5162                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5163                         struct i40e_asq_cmd_details *cmd_details)
5164 {
5165         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5166                                     i40e_aqc_opc_query_vsi_bw_config,
5167                                     cmd_details);
5168 }
5169
5170 /**
5171  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5172  * @hw: pointer to the hw struct
5173  * @seid: seid of the VSI
5174  * @bw_data: Buffer to hold VSI BW configuration per TC
5175  * @cmd_details: pointer to command details structure or NULL
5176  **/
5177 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5178                         u16 seid,
5179                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5180                         struct i40e_asq_cmd_details *cmd_details)
5181 {
5182         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5183                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5184                                     cmd_details);
5185 }
5186
5187 /**
5188  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5189  * @hw: pointer to the hw struct
5190  * @seid: seid of the switching component
5191  * @bw_data: Buffer to hold switching component's per TC BW config
5192  * @cmd_details: pointer to command details structure or NULL
5193  **/
5194 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5195                 u16 seid,
5196                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5197                 struct i40e_asq_cmd_details *cmd_details)
5198 {
5199         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5200                                    i40e_aqc_opc_query_switching_comp_ets_config,
5201                                    cmd_details);
5202 }
5203
5204 /**
5205  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5206  * @hw: pointer to the hw struct
5207  * @seid: seid of the VSI or switching component connected to Physical Port
5208  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5209  * @cmd_details: pointer to command details structure or NULL
5210  **/
5211 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5212                         u16 seid,
5213                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5214                         struct i40e_asq_cmd_details *cmd_details)
5215 {
5216         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5217                                     i40e_aqc_opc_query_port_ets_config,
5218                                     cmd_details);
5219 }
5220
5221 /**
5222  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5223  * @hw: pointer to the hw struct
5224  * @seid: seid of the switching component
5225  * @bw_data: Buffer to hold switching component's BW configuration
5226  * @cmd_details: pointer to command details structure or NULL
5227  **/
5228 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5229                 u16 seid,
5230                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5231                 struct i40e_asq_cmd_details *cmd_details)
5232 {
5233         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5234                                     i40e_aqc_opc_query_switching_comp_bw_config,
5235                                     cmd_details);
5236 }
5237
5238 /**
5239  * i40e_validate_filter_settings
5240  * @hw: pointer to the hardware structure
5241  * @settings: Filter control settings
5242  *
5243  * Check and validate the filter control settings passed.
5244  * The function checks for the valid filter/context sizes being
5245  * passed for FCoE and PE.
5246  *
5247  * Returns I40E_SUCCESS if the values passed are valid and within
5248  * range else returns an error.
5249  **/
5250 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5251                                 struct i40e_filter_control_settings *settings)
5252 {
5253         u32 fcoe_cntx_size, fcoe_filt_size;
5254         u32 pe_cntx_size, pe_filt_size;
5255         u32 fcoe_fmax;
5256
5257         u32 val;
5258
5259         /* Validate FCoE settings passed */
5260         switch (settings->fcoe_filt_num) {
5261         case I40E_HASH_FILTER_SIZE_1K:
5262         case I40E_HASH_FILTER_SIZE_2K:
5263         case I40E_HASH_FILTER_SIZE_4K:
5264         case I40E_HASH_FILTER_SIZE_8K:
5265         case I40E_HASH_FILTER_SIZE_16K:
5266         case I40E_HASH_FILTER_SIZE_32K:
5267                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5268                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5269                 break;
5270         default:
5271                 return I40E_ERR_PARAM;
5272         }
5273
5274         switch (settings->fcoe_cntx_num) {
5275         case I40E_DMA_CNTX_SIZE_512:
5276         case I40E_DMA_CNTX_SIZE_1K:
5277         case I40E_DMA_CNTX_SIZE_2K:
5278         case I40E_DMA_CNTX_SIZE_4K:
5279                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5280                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5281                 break;
5282         default:
5283                 return I40E_ERR_PARAM;
5284         }
5285
5286         /* Validate PE settings passed */
5287         switch (settings->pe_filt_num) {
5288         case I40E_HASH_FILTER_SIZE_1K:
5289         case I40E_HASH_FILTER_SIZE_2K:
5290         case I40E_HASH_FILTER_SIZE_4K:
5291         case I40E_HASH_FILTER_SIZE_8K:
5292         case I40E_HASH_FILTER_SIZE_16K:
5293         case I40E_HASH_FILTER_SIZE_32K:
5294         case I40E_HASH_FILTER_SIZE_64K:
5295         case I40E_HASH_FILTER_SIZE_128K:
5296         case I40E_HASH_FILTER_SIZE_256K:
5297         case I40E_HASH_FILTER_SIZE_512K:
5298         case I40E_HASH_FILTER_SIZE_1M:
5299                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5300                 pe_filt_size <<= (u32)settings->pe_filt_num;
5301                 break;
5302         default:
5303                 return I40E_ERR_PARAM;
5304         }
5305
5306         switch (settings->pe_cntx_num) {
5307         case I40E_DMA_CNTX_SIZE_512:
5308         case I40E_DMA_CNTX_SIZE_1K:
5309         case I40E_DMA_CNTX_SIZE_2K:
5310         case I40E_DMA_CNTX_SIZE_4K:
5311         case I40E_DMA_CNTX_SIZE_8K:
5312         case I40E_DMA_CNTX_SIZE_16K:
5313         case I40E_DMA_CNTX_SIZE_32K:
5314         case I40E_DMA_CNTX_SIZE_64K:
5315         case I40E_DMA_CNTX_SIZE_128K:
5316         case I40E_DMA_CNTX_SIZE_256K:
5317                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5318                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5319                 break;
5320         default:
5321                 return I40E_ERR_PARAM;
5322         }
5323
5324         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5325         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5326         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5327                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5328         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5329                 return I40E_ERR_INVALID_SIZE;
5330
5331         return I40E_SUCCESS;
5332 }
5333
5334 /**
5335  * i40e_set_filter_control
5336  * @hw: pointer to the hardware structure
5337  * @settings: Filter control settings
5338  *
5339  * Set the Queue Filters for PE/FCoE and enable filters required
5340  * for a single PF. It is expected that these settings are programmed
5341  * at the driver initialization time.
5342  **/
5343 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5344                                 struct i40e_filter_control_settings *settings)
5345 {
5346         enum i40e_status_code ret = I40E_SUCCESS;
5347         u32 hash_lut_size = 0;
5348         u32 val;
5349
5350         if (!settings)
5351                 return I40E_ERR_PARAM;
5352
5353         /* Validate the input settings */
5354         ret = i40e_validate_filter_settings(hw, settings);
5355         if (ret)
5356                 return ret;
5357
5358         /* Read the PF Queue Filter control register */
5359         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5360
5361         /* Program required PE hash buckets for the PF */
5362         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5363         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5364                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5365         /* Program required PE contexts for the PF */
5366         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5367         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5368                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5369
5370         /* Program required FCoE hash buckets for the PF */
5371         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5372         val |= ((u32)settings->fcoe_filt_num <<
5373                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5374                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5375         /* Program required FCoE DDP contexts for the PF */
5376         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5377         val |= ((u32)settings->fcoe_cntx_num <<
5378                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5379                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5380
5381         /* Program Hash LUT size for the PF */
5382         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5383         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5384                 hash_lut_size = 1;
5385         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5386                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5387
5388         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5389         if (settings->enable_fdir)
5390                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5391         if (settings->enable_ethtype)
5392                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5393         if (settings->enable_macvlan)
5394                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5395
5396         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5397
5398         return I40E_SUCCESS;
5399 }
5400
5401 /**
5402  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5403  * @hw: pointer to the hw struct
5404  * @mac_addr: MAC address to use in the filter
5405  * @ethtype: Ethertype to use in the filter
5406  * @flags: Flags that needs to be applied to the filter
5407  * @vsi_seid: seid of the control VSI
5408  * @queue: VSI queue number to send the packet to
5409  * @is_add: Add control packet filter if True else remove
5410  * @stats: Structure to hold information on control filter counts
5411  * @cmd_details: pointer to command details structure or NULL
5412  *
5413  * This command will Add or Remove control packet filter for a control VSI.
5414  * In return it will update the total number of perfect filter count in
5415  * the stats member.
5416  **/
5417 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5418                                 u8 *mac_addr, u16 ethtype, u16 flags,
5419                                 u16 vsi_seid, u16 queue, bool is_add,
5420                                 struct i40e_control_filter_stats *stats,
5421                                 struct i40e_asq_cmd_details *cmd_details)
5422 {
5423         struct i40e_aq_desc desc;
5424         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5425                 (struct i40e_aqc_add_remove_control_packet_filter *)
5426                 &desc.params.raw;
5427         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5428                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5429                 &desc.params.raw;
5430         enum i40e_status_code status;
5431
5432         if (vsi_seid == 0)
5433                 return I40E_ERR_PARAM;
5434
5435         if (is_add) {
5436                 i40e_fill_default_direct_cmd_desc(&desc,
5437                                 i40e_aqc_opc_add_control_packet_filter);
5438                 cmd->queue = CPU_TO_LE16(queue);
5439         } else {
5440                 i40e_fill_default_direct_cmd_desc(&desc,
5441                                 i40e_aqc_opc_remove_control_packet_filter);
5442         }
5443
5444         if (mac_addr)
5445                 i40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,
5446                             I40E_NONDMA_TO_NONDMA);
5447
5448         cmd->etype = CPU_TO_LE16(ethtype);
5449         cmd->flags = CPU_TO_LE16(flags);
5450         cmd->seid = CPU_TO_LE16(vsi_seid);
5451
5452         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5453
5454         if (!status && stats) {
5455                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5456                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5457                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5458                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5459         }
5460
5461         return status;
5462 }
5463
5464 /**
5465  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5466  * @hw: pointer to the hw struct
5467  * @seid: VSI seid to add ethertype filter from
5468  **/
5469 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5470 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5471                                                     u16 seid)
5472 {
5473         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5474                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5475                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5476         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5477         enum i40e_status_code status;
5478
5479         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5480                                                        seid, 0, true, NULL,
5481                                                        NULL);
5482         if (status)
5483                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5484 }
5485
5486 /**
5487  * i40e_aq_add_cloud_filters
5488  * @hw: pointer to the hardware structure
5489  * @seid: VSI seid to add cloud filters from
5490  * @filters: Buffer which contains the filters to be added
5491  * @filter_count: number of filters contained in the buffer
5492  *
5493  * Set the cloud filters for a given VSI.  The contents of the
5494  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5495  * in by the caller of the function.
5496  *
5497  **/
5498 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5499         u16 seid,
5500         struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5501         u8 filter_count)
5502 {
5503         struct i40e_aq_desc desc;
5504         struct i40e_aqc_add_remove_cloud_filters *cmd =
5505         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5506         u16 buff_len;
5507         enum i40e_status_code status;
5508
5509         i40e_fill_default_direct_cmd_desc(&desc,
5510                                           i40e_aqc_opc_add_cloud_filters);
5511
5512         buff_len = filter_count * sizeof(*filters);
5513         desc.datalen = CPU_TO_LE16(buff_len);
5514         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5515         cmd->num_filters = filter_count;
5516         cmd->seid = CPU_TO_LE16(seid);
5517
5518         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5519
5520         return status;
5521 }
5522
5523 /**
5524  * i40e_aq_remove_cloud_filters
5525  * @hw: pointer to the hardware structure
5526  * @seid: VSI seid to remove cloud filters from
5527  * @filters: Buffer which contains the filters to be removed
5528  * @filter_count: number of filters contained in the buffer
5529  *
5530  * Remove the cloud filters for a given VSI.  The contents of the
5531  * i40e_aqc_add_remove_cloud_filters_element_data are filled
5532  * in by the caller of the function.
5533  *
5534  **/
5535 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
5536                 u16 seid,
5537                 struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
5538                 u8 filter_count)
5539 {
5540         struct i40e_aq_desc desc;
5541         struct i40e_aqc_add_remove_cloud_filters *cmd =
5542         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5543         enum i40e_status_code status;
5544         u16 buff_len;
5545
5546         i40e_fill_default_direct_cmd_desc(&desc,
5547                                           i40e_aqc_opc_remove_cloud_filters);
5548
5549         buff_len = filter_count * sizeof(*filters);
5550         desc.datalen = CPU_TO_LE16(buff_len);
5551         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5552         cmd->num_filters = filter_count;
5553         cmd->seid = CPU_TO_LE16(seid);
5554
5555         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5556
5557         return status;
5558 }
5559
5560 /**
5561  * i40e_aq_alternate_write
5562  * @hw: pointer to the hardware structure
5563  * @reg_addr0: address of first dword to be read
5564  * @reg_val0: value to be written under 'reg_addr0'
5565  * @reg_addr1: address of second dword to be read
5566  * @reg_val1: value to be written under 'reg_addr1'
5567  *
5568  * Write one or two dwords to alternate structure. Fields are indicated
5569  * by 'reg_addr0' and 'reg_addr1' register numbers.
5570  *
5571  **/
5572 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
5573                                 u32 reg_addr0, u32 reg_val0,
5574                                 u32 reg_addr1, u32 reg_val1)
5575 {
5576         struct i40e_aq_desc desc;
5577         struct i40e_aqc_alternate_write *cmd_resp =
5578                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5579         enum i40e_status_code status;
5580
5581         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
5582         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5583         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5584         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
5585         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
5586
5587         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5588
5589         return status;
5590 }
5591
5592 /**
5593  * i40e_aq_alternate_write_indirect
5594  * @hw: pointer to the hardware structure
5595  * @addr: address of a first register to be modified
5596  * @dw_count: number of alternate structure fields to write
5597  * @buffer: pointer to the command buffer
5598  *
5599  * Write 'dw_count' dwords from 'buffer' to alternate structure
5600  * starting at 'addr'.
5601  *
5602  **/
5603 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
5604                                 u32 addr, u32 dw_count, void *buffer)
5605 {
5606         struct i40e_aq_desc desc;
5607         struct i40e_aqc_alternate_ind_write *cmd_resp =
5608                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5609         enum i40e_status_code status;
5610
5611         if (buffer == NULL)
5612                 return I40E_ERR_PARAM;
5613
5614         /* Indirect command */
5615         i40e_fill_default_direct_cmd_desc(&desc,
5616                                          i40e_aqc_opc_alternate_write_indirect);
5617
5618         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5619         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5620         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5621                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5622
5623         cmd_resp->address = CPU_TO_LE32(addr);
5624         cmd_resp->length = CPU_TO_LE32(dw_count);
5625
5626         status = i40e_asq_send_command(hw, &desc, buffer,
5627                                        I40E_LO_DWORD(4*dw_count), NULL);
5628
5629         return status;
5630 }
5631
5632 /**
5633  * i40e_aq_alternate_read
5634  * @hw: pointer to the hardware structure
5635  * @reg_addr0: address of first dword to be read
5636  * @reg_val0: pointer for data read from 'reg_addr0'
5637  * @reg_addr1: address of second dword to be read
5638  * @reg_val1: pointer for data read from 'reg_addr1'
5639  *
5640  * Read one or two dwords from alternate structure. Fields are indicated
5641  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
5642  * is not passed then only register at 'reg_addr0' is read.
5643  *
5644  **/
5645 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
5646                                 u32 reg_addr0, u32 *reg_val0,
5647                                 u32 reg_addr1, u32 *reg_val1)
5648 {
5649         struct i40e_aq_desc desc;
5650         struct i40e_aqc_alternate_write *cmd_resp =
5651                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
5652         enum i40e_status_code status;
5653
5654         if (reg_val0 == NULL)
5655                 return I40E_ERR_PARAM;
5656
5657         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
5658         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
5659         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
5660
5661         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5662
5663         if (status == I40E_SUCCESS) {
5664                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
5665
5666                 if (reg_val1 != NULL)
5667                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
5668         }
5669
5670         return status;
5671 }
5672
5673 /**
5674  * i40e_aq_alternate_read_indirect
5675  * @hw: pointer to the hardware structure
5676  * @addr: address of the alternate structure field
5677  * @dw_count: number of alternate structure fields to read
5678  * @buffer: pointer to the command buffer
5679  *
5680  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
5681  * place them in 'buffer'. The buffer should be allocated by caller.
5682  *
5683  **/
5684 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
5685                                 u32 addr, u32 dw_count, void *buffer)
5686 {
5687         struct i40e_aq_desc desc;
5688         struct i40e_aqc_alternate_ind_write *cmd_resp =
5689                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
5690         enum i40e_status_code status;
5691
5692         if (buffer == NULL)
5693                 return I40E_ERR_PARAM;
5694
5695         /* Indirect command */
5696         i40e_fill_default_direct_cmd_desc(&desc,
5697                 i40e_aqc_opc_alternate_read_indirect);
5698
5699         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
5700         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
5701         if (dw_count > (I40E_AQ_LARGE_BUF/4))
5702                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5703
5704         cmd_resp->address = CPU_TO_LE32(addr);
5705         cmd_resp->length = CPU_TO_LE32(dw_count);
5706
5707         status = i40e_asq_send_command(hw, &desc, buffer,
5708                                        I40E_LO_DWORD(4*dw_count), NULL);
5709
5710         return status;
5711 }
5712
5713 /**
5714  *  i40e_aq_alternate_clear
5715  *  @hw: pointer to the HW structure.
5716  *
5717  *  Clear the alternate structures of the port from which the function
5718  *  is called.
5719  *
5720  **/
5721 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
5722 {
5723         struct i40e_aq_desc desc;
5724         enum i40e_status_code status;
5725
5726         i40e_fill_default_direct_cmd_desc(&desc,
5727                                           i40e_aqc_opc_alternate_clear_port);
5728
5729         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5730
5731         return status;
5732 }
5733
5734 /**
5735  *  i40e_aq_alternate_write_done
5736  *  @hw: pointer to the HW structure.
5737  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
5738  *  @reset_needed: indicates the SW should trigger GLOBAL reset
5739  *
5740  *  Indicates to the FW that alternate structures have been changed.
5741  *
5742  **/
5743 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
5744                 u8 bios_mode, bool *reset_needed)
5745 {
5746         struct i40e_aq_desc desc;
5747         struct i40e_aqc_alternate_write_done *cmd =
5748                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5749         enum i40e_status_code status;
5750
5751         if (reset_needed == NULL)
5752                 return I40E_ERR_PARAM;
5753
5754         i40e_fill_default_direct_cmd_desc(&desc,
5755                                           i40e_aqc_opc_alternate_write_done);
5756
5757         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
5758
5759         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5760         if (!status && reset_needed)
5761                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
5762                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
5763
5764         return status;
5765 }
5766
5767 /**
5768  *  i40e_aq_set_oem_mode
5769  *  @hw: pointer to the HW structure.
5770  *  @oem_mode: the OEM mode to be used
5771  *
5772  *  Sets the device to a specific operating mode. Currently the only supported
5773  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
5774  *
5775  **/
5776 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
5777                 u8 oem_mode)
5778 {
5779         struct i40e_aq_desc desc;
5780         struct i40e_aqc_alternate_write_done *cmd =
5781                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
5782         enum i40e_status_code status;
5783
5784         i40e_fill_default_direct_cmd_desc(&desc,
5785                                           i40e_aqc_opc_alternate_set_mode);
5786
5787         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
5788
5789         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
5790
5791         return status;
5792 }
5793
5794 /**
5795  * i40e_aq_resume_port_tx
5796  * @hw: pointer to the hardware structure
5797  * @cmd_details: pointer to command details structure or NULL
5798  *
5799  * Resume port's Tx traffic
5800  **/
5801 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
5802                                 struct i40e_asq_cmd_details *cmd_details)
5803 {
5804         struct i40e_aq_desc desc;
5805         enum i40e_status_code status;
5806
5807         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
5808
5809         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5810
5811         return status;
5812 }
5813
5814 /**
5815  * i40e_set_pci_config_data - store PCI bus info
5816  * @hw: pointer to hardware structure
5817  * @link_status: the link status word from PCI config space
5818  *
5819  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
5820  **/
5821 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
5822 {
5823         hw->bus.type = i40e_bus_type_pci_express;
5824
5825         switch (link_status & I40E_PCI_LINK_WIDTH) {
5826         case I40E_PCI_LINK_WIDTH_1:
5827                 hw->bus.width = i40e_bus_width_pcie_x1;
5828                 break;
5829         case I40E_PCI_LINK_WIDTH_2:
5830                 hw->bus.width = i40e_bus_width_pcie_x2;
5831                 break;
5832         case I40E_PCI_LINK_WIDTH_4:
5833                 hw->bus.width = i40e_bus_width_pcie_x4;
5834                 break;
5835         case I40E_PCI_LINK_WIDTH_8:
5836                 hw->bus.width = i40e_bus_width_pcie_x8;
5837                 break;
5838         default:
5839                 hw->bus.width = i40e_bus_width_unknown;
5840                 break;
5841         }
5842
5843         switch (link_status & I40E_PCI_LINK_SPEED) {
5844         case I40E_PCI_LINK_SPEED_2500:
5845                 hw->bus.speed = i40e_bus_speed_2500;
5846                 break;
5847         case I40E_PCI_LINK_SPEED_5000:
5848                 hw->bus.speed = i40e_bus_speed_5000;
5849                 break;
5850         case I40E_PCI_LINK_SPEED_8000:
5851                 hw->bus.speed = i40e_bus_speed_8000;
5852                 break;
5853         default:
5854                 hw->bus.speed = i40e_bus_speed_unknown;
5855                 break;
5856         }
5857 }
5858
5859 /**
5860  * i40e_aq_debug_dump
5861  * @hw: pointer to the hardware structure
5862  * @cluster_id: specific cluster to dump
5863  * @table_id: table id within cluster
5864  * @start_index: index of line in the block to read
5865  * @buff_size: dump buffer size
5866  * @buff: dump buffer
5867  * @ret_buff_size: actual buffer size returned
5868  * @ret_next_table: next block to read
5869  * @ret_next_index: next index to read
5870  *
5871  * Dump internal FW/HW data for debug purposes.
5872  *
5873  **/
5874 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
5875                                 u8 table_id, u32 start_index, u16 buff_size,
5876                                 void *buff, u16 *ret_buff_size,
5877                                 u8 *ret_next_table, u32 *ret_next_index,
5878                                 struct i40e_asq_cmd_details *cmd_details)
5879 {
5880         struct i40e_aq_desc desc;
5881         struct i40e_aqc_debug_dump_internals *cmd =
5882                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5883         struct i40e_aqc_debug_dump_internals *resp =
5884                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
5885         enum i40e_status_code status;
5886
5887         if (buff_size == 0 || !buff)
5888                 return I40E_ERR_PARAM;
5889
5890         i40e_fill_default_direct_cmd_desc(&desc,
5891                                           i40e_aqc_opc_debug_dump_internals);
5892         /* Indirect Command */
5893         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5894         if (buff_size > I40E_AQ_LARGE_BUF)
5895                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5896
5897         cmd->cluster_id = cluster_id;
5898         cmd->table_id = table_id;
5899         cmd->idx = CPU_TO_LE32(start_index);
5900
5901         desc.datalen = CPU_TO_LE16(buff_size);
5902
5903         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5904         if (!status) {
5905                 if (ret_buff_size != NULL)
5906                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
5907                 if (ret_next_table != NULL)
5908                         *ret_next_table = resp->table_id;
5909                 if (ret_next_index != NULL)
5910                         *ret_next_index = LE32_TO_CPU(resp->idx);
5911         }
5912
5913         return status;
5914 }
5915
5916 /**
5917  * i40e_read_bw_from_alt_ram
5918  * @hw: pointer to the hardware structure
5919  * @max_bw: pointer for max_bw read
5920  * @min_bw: pointer for min_bw read
5921  * @min_valid: pointer for bool that is true if min_bw is a valid value
5922  * @max_valid: pointer for bool that is true if max_bw is a valid value
5923  *
5924  * Read bw from the alternate ram for the given pf
5925  **/
5926 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
5927                                         u32 *max_bw, u32 *min_bw,
5928                                         bool *min_valid, bool *max_valid)
5929 {
5930         enum i40e_status_code status;
5931         u32 max_bw_addr, min_bw_addr;
5932
5933         /* Calculate the address of the min/max bw registers */
5934         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5935                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
5936                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5937         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
5938                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
5939                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
5940
5941         /* Read the bandwidths from alt ram */
5942         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
5943                                         min_bw_addr, min_bw);
5944
5945         if (*min_bw & I40E_ALT_BW_VALID_MASK)
5946                 *min_valid = true;
5947         else
5948                 *min_valid = false;
5949
5950         if (*max_bw & I40E_ALT_BW_VALID_MASK)
5951                 *max_valid = true;
5952         else
5953                 *max_valid = false;
5954
5955         return status;
5956 }
5957
5958 /**
5959  * i40e_aq_configure_partition_bw
5960  * @hw: pointer to the hardware structure
5961  * @bw_data: Buffer holding valid pfs and bw limits
5962  * @cmd_details: pointer to command details
5963  *
5964  * Configure partitions guaranteed/max bw
5965  **/
5966 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
5967                         struct i40e_aqc_configure_partition_bw_data *bw_data,
5968                         struct i40e_asq_cmd_details *cmd_details)
5969 {
5970         enum i40e_status_code status;
5971         struct i40e_aq_desc desc;
5972         u16 bwd_size = sizeof(*bw_data);
5973
5974         i40e_fill_default_direct_cmd_desc(&desc,
5975                                 i40e_aqc_opc_configure_partition_bw);
5976
5977         /* Indirect command */
5978         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5979         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5980
5981         if (bwd_size > I40E_AQ_LARGE_BUF)
5982                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5983
5984         desc.datalen = CPU_TO_LE16(bwd_size);
5985
5986         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
5987
5988         return status;
5989 }
5990
5991 /**
5992  * i40e_read_phy_register
5993  * @hw: pointer to the HW structure
5994  * @page: registers page number
5995  * @reg: register address in the page
5996  * @phy_adr: PHY address on MDIO interface
5997  * @value: PHY register value
5998  *
5999  * Reads specified PHY register value
6000  **/
6001 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6002                                              u8 page, u16 reg, u8 phy_addr,
6003                                              u16 *value)
6004 {
6005         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6006         u32 command  = 0;
6007         u16 retry = 1000;
6008         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6009
6010         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6011                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6012                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6013                   (I40E_MDIO_OPCODE_ADDRESS) |
6014                   (I40E_MDIO_STCODE) |
6015                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6016                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6017         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6018         do {
6019                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6020                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6021                         status = I40E_SUCCESS;
6022                         break;
6023                 }
6024                 i40e_usec_delay(10);
6025                 retry--;
6026         } while (retry);
6027
6028         if (status) {
6029                 i40e_debug(hw, I40E_DEBUG_PHY,
6030                            "PHY: Can't write command to external PHY.\n");
6031                 goto phy_read_end;
6032         }
6033
6034         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6035                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6036                   (I40E_MDIO_OPCODE_READ) |
6037                   (I40E_MDIO_STCODE) |
6038                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6039                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6040         status = I40E_ERR_TIMEOUT;
6041         retry = 1000;
6042         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6043         do {
6044                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6045                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6046                         status = I40E_SUCCESS;
6047                         break;
6048                 }
6049                 i40e_usec_delay(10);
6050                 retry--;
6051         } while (retry);
6052
6053         if (!status) {
6054                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6055                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6056                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6057         } else {
6058                 i40e_debug(hw, I40E_DEBUG_PHY,
6059                            "PHY: Can't read register value from external PHY.\n");
6060         }
6061
6062 phy_read_end:
6063         return status;
6064 }
6065
6066 /**
6067  * i40e_write_phy_register
6068  * @hw: pointer to the HW structure
6069  * @page: registers page number
6070  * @reg: register address in the page
6071  * @phy_adr: PHY address on MDIO interface
6072  * @value: PHY register value
6073  *
6074  * Writes value to specified PHY register
6075  **/
6076 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6077                                               u8 page, u16 reg, u8 phy_addr,
6078                                               u16 value)
6079 {
6080         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6081         u32 command  = 0;
6082         u16 retry = 1000;
6083         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6084
6085         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6086                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6087                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6088                   (I40E_MDIO_OPCODE_ADDRESS) |
6089                   (I40E_MDIO_STCODE) |
6090                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6091                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6092         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6093         do {
6094                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6095                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6096                         status = I40E_SUCCESS;
6097                         break;
6098                 }
6099                 i40e_usec_delay(10);
6100                 retry--;
6101         } while (retry);
6102         if (status) {
6103                 i40e_debug(hw, I40E_DEBUG_PHY,
6104                            "PHY: Can't write command to external PHY.\n");
6105                 goto phy_write_end;
6106         }
6107
6108         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6109         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6110
6111         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6112                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6113                   (I40E_MDIO_OPCODE_WRITE) |
6114                   (I40E_MDIO_STCODE) |
6115                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6116                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6117         status = I40E_ERR_TIMEOUT;
6118         retry = 1000;
6119         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6120         do {
6121                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6122                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6123                         status = I40E_SUCCESS;
6124                         break;
6125                 }
6126                 i40e_usec_delay(10);
6127                 retry--;
6128         } while (retry);
6129
6130 phy_write_end:
6131         return status;
6132 }
6133
6134 /**
6135  * i40e_get_phy_address
6136  * @hw: pointer to the HW structure
6137  * @dev_num: PHY port num that address we want
6138  * @phy_addr: Returned PHY address
6139  *
6140  * Gets PHY address for current port
6141  **/
6142 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6143 {
6144         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6145         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6146
6147         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6148 }
6149
6150 /**
6151  * i40e_blink_phy_led
6152  * @hw: pointer to the HW structure
6153  * @time: time how long led will blinks in secs
6154  * @interval: gap between LED on and off in msecs
6155  *
6156  * Blinks PHY link LED
6157  **/
6158 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6159                                               u32 time, u32 interval)
6160 {
6161         enum i40e_status_code status = I40E_SUCCESS;
6162         u32 i;
6163         u16 led_ctl = 0;
6164         u16 gpio_led_port;
6165         u16 led_reg;
6166         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6167         u8 phy_addr = 0;
6168         u8 port_num;
6169
6170         i = rd32(hw, I40E_PFGEN_PORTNUM);
6171         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6172         phy_addr = i40e_get_phy_address(hw, port_num);
6173
6174         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6175              led_addr++) {
6176                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6177                                                 led_addr, phy_addr, &led_reg);
6178                 if (status)
6179                         goto phy_blinking_end;
6180                 led_ctl = led_reg;
6181                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6182                         led_reg = 0;
6183                         status = i40e_write_phy_register(hw,
6184                                                          I40E_PHY_COM_REG_PAGE,
6185                                                          led_addr, phy_addr,
6186                                                          led_reg);
6187                         if (status)
6188                                 goto phy_blinking_end;
6189                         break;
6190                 }
6191         }
6192
6193         if (time > 0 && interval > 0) {
6194                 for (i = 0; i < time * 1000; i += interval) {
6195                         status = i40e_read_phy_register(hw,
6196                                                         I40E_PHY_COM_REG_PAGE,
6197                                                         led_addr, phy_addr,
6198                                                         &led_reg);
6199                         if (status)
6200                                 goto restore_config;
6201                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6202                                 led_reg = 0;
6203                         else
6204                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6205                         status = i40e_write_phy_register(hw,
6206                                                          I40E_PHY_COM_REG_PAGE,
6207                                                          led_addr, phy_addr,
6208                                                          led_reg);
6209                         if (status)
6210                                 goto restore_config;
6211                         i40e_msec_delay(interval);
6212                 }
6213         }
6214
6215 restore_config:
6216         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6217                                          phy_addr, led_ctl);
6218
6219 phy_blinking_end:
6220         return status;
6221 }
6222
6223 /**
6224  * i40e_led_get_phy - return current on/off mode
6225  * @hw: pointer to the hw struct
6226  * @led_addr: address of led register to use
6227  * @val: original value of register to use
6228  *
6229  **/
6230 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6231                                        u16 *val)
6232 {
6233         enum i40e_status_code status = I40E_SUCCESS;
6234         u16 gpio_led_port;
6235         u8 phy_addr = 0;
6236         u16 reg_val;
6237         u16 temp_addr;
6238         u8 port_num;
6239         u32 i;
6240
6241         temp_addr = I40E_PHY_LED_PROV_REG_1;
6242         i = rd32(hw, I40E_PFGEN_PORTNUM);
6243         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6244         phy_addr = i40e_get_phy_address(hw, port_num);
6245
6246         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6247              temp_addr++) {
6248                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6249                                                 temp_addr, phy_addr, &reg_val);
6250                 if (status)
6251                         return status;
6252                 *val = reg_val;
6253                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6254                         *led_addr = temp_addr;
6255                         break;
6256                 }
6257         }
6258         return status;
6259 }
6260
6261 /**
6262  * i40e_led_set_phy
6263  * @hw: pointer to the HW structure
6264  * @on: true or false
6265  * @mode: original val plus bit for set or ignore
6266  * Set led's on or off when controlled by the PHY
6267  *
6268  **/
6269 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6270                                        u16 led_addr, u32 mode)
6271 {
6272         enum i40e_status_code status = I40E_SUCCESS;
6273         u16 led_ctl = 0;
6274         u16 led_reg = 0;
6275         u8 phy_addr = 0;
6276         u8 port_num;
6277         u32 i;
6278
6279         i = rd32(hw, I40E_PFGEN_PORTNUM);
6280         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6281         phy_addr = i40e_get_phy_address(hw, port_num);
6282
6283         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6284                                         phy_addr, &led_reg);
6285         if (status)
6286                 return status;
6287         led_ctl = led_reg;
6288         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6289                 led_reg = 0;
6290                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6291                                                  led_addr, phy_addr, led_reg);
6292                 if (status)
6293                         return status;
6294         }
6295         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6296                                         led_addr, phy_addr, &led_reg);
6297         if (status)
6298                 goto restore_config;
6299         if (on)
6300                 led_reg = I40E_PHY_LED_MANUAL_ON;
6301         else
6302                 led_reg = 0;
6303         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
6304                                          led_addr, phy_addr, led_reg);
6305         if (status)
6306                 goto restore_config;
6307         if (mode & I40E_PHY_LED_MODE_ORIG) {
6308                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6309                 status = i40e_write_phy_register(hw,
6310                                                  I40E_PHY_COM_REG_PAGE,
6311                                                  led_addr, phy_addr, led_ctl);
6312         }
6313         return status;
6314 restore_config:
6315         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
6316                                          phy_addr, led_ctl);
6317         return status;
6318 }
6319 #endif /* PF_DRIVER */
6320
6321 /**
6322  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
6323  * @hw: pointer to the hw struct
6324  * @reg_addr: register address
6325  * @reg_val: ptr to register value
6326  * @cmd_details: pointer to command details structure or NULL
6327  *
6328  * Use the firmware to read the Rx control register,
6329  * especially useful if the Rx unit is under heavy pressure
6330  **/
6331 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
6332                                 u32 reg_addr, u32 *reg_val,
6333                                 struct i40e_asq_cmd_details *cmd_details)
6334 {
6335         struct i40e_aq_desc desc;
6336         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
6337                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6338         enum i40e_status_code status;
6339
6340         if (reg_val == NULL)
6341                 return I40E_ERR_PARAM;
6342
6343         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
6344
6345         cmd_resp->address = CPU_TO_LE32(reg_addr);
6346
6347         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6348
6349         if (status == I40E_SUCCESS)
6350                 *reg_val = LE32_TO_CPU(cmd_resp->value);
6351
6352         return status;
6353 }
6354
6355 /**
6356  * i40e_read_rx_ctl - read from an Rx control register
6357  * @hw: pointer to the hw struct
6358  * @reg_addr: register address
6359  **/
6360 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
6361 {
6362         enum i40e_status_code status = I40E_SUCCESS;
6363         bool use_register;
6364         int retry = 5;
6365         u32 val = 0;
6366
6367         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6368         if (!use_register) {
6369 do_retry:
6370                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
6371                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6372                         i40e_msec_delay(1);
6373                         retry--;
6374                         goto do_retry;
6375                 }
6376         }
6377
6378         /* if the AQ access failed, try the old-fashioned way */
6379         if (status || use_register)
6380                 val = rd32(hw, reg_addr);
6381
6382         return val;
6383 }
6384
6385 /**
6386  * i40e_aq_rx_ctl_write_register
6387  * @hw: pointer to the hw struct
6388  * @reg_addr: register address
6389  * @reg_val: register value
6390  * @cmd_details: pointer to command details structure or NULL
6391  *
6392  * Use the firmware to write to an Rx control register,
6393  * especially useful if the Rx unit is under heavy pressure
6394  **/
6395 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
6396                                 u32 reg_addr, u32 reg_val,
6397                                 struct i40e_asq_cmd_details *cmd_details)
6398 {
6399         struct i40e_aq_desc desc;
6400         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
6401                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
6402         enum i40e_status_code status;
6403
6404         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
6405
6406         cmd->address = CPU_TO_LE32(reg_addr);
6407         cmd->value = CPU_TO_LE32(reg_val);
6408
6409         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6410
6411         return status;
6412 }
6413
6414 /**
6415  * i40e_write_rx_ctl - write to an Rx control register
6416  * @hw: pointer to the hw struct
6417  * @reg_addr: register address
6418  * @reg_val: register value
6419  **/
6420 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
6421 {
6422         enum i40e_status_code status = I40E_SUCCESS;
6423         bool use_register;
6424         int retry = 5;
6425
6426         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
6427         if (!use_register) {
6428 do_retry:
6429                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
6430                                                        reg_val, NULL);
6431                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
6432                         i40e_msec_delay(1);
6433                         retry--;
6434                         goto do_retry;
6435                 }
6436         }
6437
6438         /* if the AQ access failed, try the old-fashioned way */
6439         if (status || use_register)
6440                 wr32(hw, reg_addr, reg_val);
6441 }
6442 #ifdef VF_DRIVER
6443
6444 /**
6445  * i40e_aq_send_msg_to_pf
6446  * @hw: pointer to the hardware structure
6447  * @v_opcode: opcodes for VF-PF communication
6448  * @v_retval: return error code
6449  * @msg: pointer to the msg buffer
6450  * @msglen: msg length
6451  * @cmd_details: pointer to command details
6452  *
6453  * Send message to PF driver using admin queue. By default, this message
6454  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
6455  * completion before returning.
6456  **/
6457 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
6458                                 enum i40e_virtchnl_ops v_opcode,
6459                                 enum i40e_status_code v_retval,
6460                                 u8 *msg, u16 msglen,
6461                                 struct i40e_asq_cmd_details *cmd_details)
6462 {
6463         struct i40e_aq_desc desc;
6464         struct i40e_asq_cmd_details details;
6465         enum i40e_status_code status;
6466
6467         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
6468         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
6469         desc.cookie_high = CPU_TO_LE32(v_opcode);
6470         desc.cookie_low = CPU_TO_LE32(v_retval);
6471         if (msglen) {
6472                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
6473                                                 | I40E_AQ_FLAG_RD));
6474                 if (msglen > I40E_AQ_LARGE_BUF)
6475                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6476                 desc.datalen = CPU_TO_LE16(msglen);
6477         }
6478         if (!cmd_details) {
6479                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
6480                 details.async = true;
6481                 cmd_details = &details;
6482         }
6483         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
6484                                        msglen, cmd_details);
6485         return status;
6486 }
6487
6488 /**
6489  * i40e_vf_parse_hw_config
6490  * @hw: pointer to the hardware structure
6491  * @msg: pointer to the virtual channel VF resource structure
6492  *
6493  * Given a VF resource message from the PF, populate the hw struct
6494  * with appropriate information.
6495  **/
6496 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
6497                              struct i40e_virtchnl_vf_resource *msg)
6498 {
6499         struct i40e_virtchnl_vsi_resource *vsi_res;
6500         int i;
6501
6502         vsi_res = &msg->vsi_res[0];
6503
6504         hw->dev_caps.num_vsis = msg->num_vsis;
6505         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
6506         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
6507         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
6508         hw->dev_caps.dcb = msg->vf_offload_flags &
6509                            I40E_VIRTCHNL_VF_OFFLOAD_L2;
6510         hw->dev_caps.fcoe = (msg->vf_offload_flags &
6511                              I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;
6512         hw->dev_caps.iwarp = (msg->vf_offload_flags &
6513                               I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
6514         for (i = 0; i < msg->num_vsis; i++) {
6515                 if (vsi_res->vsi_type == I40E_VSI_SRIOV) {
6516                         i40e_memcpy(hw->mac.perm_addr,
6517                                     vsi_res->default_mac_addr,
6518                                     I40E_ETH_LENGTH_OF_ADDRESS,
6519                                     I40E_NONDMA_TO_NONDMA);
6520                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
6521                                     I40E_ETH_LENGTH_OF_ADDRESS,
6522                                     I40E_NONDMA_TO_NONDMA);
6523                 }
6524                 vsi_res++;
6525         }
6526 }
6527
6528 /**
6529  * i40e_vf_reset
6530  * @hw: pointer to the hardware structure
6531  *
6532  * Send a VF_RESET message to the PF. Does not wait for response from PF
6533  * as none will be forthcoming. Immediately after calling this function,
6534  * the admin queue should be shut down and (optionally) reinitialized.
6535  **/
6536 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
6537 {
6538         return i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,
6539                                       I40E_SUCCESS, NULL, 0, NULL);
6540 }
6541 #endif /* VF_DRIVER */
6542 #ifdef X722_SUPPORT
6543
6544 /**
6545  * i40e_aq_set_arp_proxy_config
6546  * @hw: pointer to the HW structure
6547  * @proxy_config - pointer to proxy config command table struct
6548  * @cmd_details: pointer to command details
6549  *
6550  * Set ARP offload parameters from pre-populated
6551  * i40e_aqc_arp_proxy_data struct
6552  **/
6553 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
6554                                 struct i40e_aqc_arp_proxy_data *proxy_config,
6555                                 struct i40e_asq_cmd_details *cmd_details)
6556 {
6557         struct i40e_aq_desc desc;
6558         enum i40e_status_code status;
6559
6560         if (!proxy_config)
6561                 return I40E_ERR_PARAM;
6562
6563         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
6564
6565         desc.params.external.addr_high =
6566                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
6567         desc.params.external.addr_low =
6568                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
6569
6570         status = i40e_asq_send_command(hw, &desc, proxy_config,
6571                                        sizeof(struct i40e_aqc_arp_proxy_data),
6572                                        cmd_details);
6573
6574         return status;
6575 }
6576
6577 /**
6578  * i40e_aq_opc_set_ns_proxy_table_entry
6579  * @hw: pointer to the HW structure
6580  * @ns_proxy_table_entry: pointer to NS table entry command struct
6581  * @cmd_details: pointer to command details
6582  *
6583  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
6584  * from pre-populated i40e_aqc_ns_proxy_data struct
6585  **/
6586 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
6587                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
6588                         struct i40e_asq_cmd_details *cmd_details)
6589 {
6590         struct i40e_aq_desc desc;
6591         enum i40e_status_code status;
6592
6593         if (!ns_proxy_table_entry)
6594                 return I40E_ERR_PARAM;
6595
6596         i40e_fill_default_direct_cmd_desc(&desc,
6597                                 i40e_aqc_opc_set_ns_proxy_table_entry);
6598
6599         desc.params.external.addr_high =
6600                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
6601         desc.params.external.addr_low =
6602                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
6603
6604         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
6605                                        sizeof(struct i40e_aqc_ns_proxy_data),
6606                                        cmd_details);
6607
6608         return status;
6609 }
6610
6611 /**
6612  * i40e_aq_set_clear_wol_filter
6613  * @hw: pointer to the hw struct
6614  * @filter_index: index of filter to modify (0-7)
6615  * @filter: buffer containing filter to be set
6616  * @set_filter: true to set filter, false to clear filter
6617  * @no_wol_tco: if true, pass through packets cannot cause wake-up
6618  *              if false, pass through packets may cause wake-up
6619  * @filter_valid: true if filter action is valid
6620  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
6621  * @cmd_details: pointer to command details structure or NULL
6622  *
6623  * Set or clear WoL filter for port attached to the PF
6624  **/
6625 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
6626                                 u8 filter_index,
6627                                 struct i40e_aqc_set_wol_filter_data *filter,
6628                                 bool set_filter, bool no_wol_tco,
6629                                 bool filter_valid, bool no_wol_tco_valid,
6630                                 struct i40e_asq_cmd_details *cmd_details)
6631 {
6632         struct i40e_aq_desc desc;
6633         struct i40e_aqc_set_wol_filter *cmd =
6634                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
6635         enum i40e_status_code status;
6636         u16 cmd_flags = 0;
6637         u16 valid_flags = 0;
6638         u16 buff_len = 0;
6639
6640         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
6641
6642         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
6643                 return  I40E_ERR_PARAM;
6644         cmd->filter_index = CPU_TO_LE16(filter_index);
6645
6646         if (set_filter) {
6647                 if (!filter)
6648                         return  I40E_ERR_PARAM;
6649                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
6650                 buff_len = sizeof(*filter);
6651         }
6652         if (no_wol_tco)
6653                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
6654         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
6655
6656         if (filter_valid)
6657                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
6658         if (no_wol_tco_valid)
6659                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
6660         cmd->valid_flags = CPU_TO_LE16(valid_flags);
6661
6662         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
6663         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
6664
6665         status = i40e_asq_send_command(hw, &desc, filter,
6666                                        buff_len, cmd_details);
6667
6668         return status;
6669 }
6670
6671 /**
6672  * i40e_aq_get_wake_event_reason
6673  * @hw: pointer to the hw struct
6674  * @wake_reason: return value, index of matching filter
6675  * @cmd_details: pointer to command details structure or NULL
6676  *
6677  * Get information for the reason of a Wake Up event
6678  **/
6679 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
6680                                 u16 *wake_reason,
6681                                 struct i40e_asq_cmd_details *cmd_details)
6682 {
6683         struct i40e_aq_desc desc;
6684         struct i40e_aqc_get_wake_reason_completion *resp =
6685                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
6686         enum i40e_status_code status;
6687
6688         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
6689
6690         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6691
6692         if (status == I40E_SUCCESS)
6693                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
6694
6695         return status;
6696 }
6697
6698 #endif /* X722_SUPPORT */