drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 #define I40E_MDIO_STCODE                0
 161 #define I40E_MDIO_OPCODE_ADDRESS        0
 162 #define I40E_MDIO_OPCODE_WRITE          I40E_MASK(1, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_OPCODE_READ_INC_ADDR  I40E_MASK(2, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166 #define I40E_MDIO_OPCODE_READ           I40E_MASK(3, \
 167                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 168
 169 #define I40E_PHY_COM_REG_PAGE                   0x1E
 170 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 171 #define I40E_PHY_LED_MANUAL_ON                  0x100
 172 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 173 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 174 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 175
 176 /* Memory types */
 177 enum i40e_memset_type {
 178         I40E_NONDMA_MEM = 0,
 179         I40E_DMA_MEM
 180 };
 181
 182 /* Memcpy types */
 183 enum i40e_memcpy_type {
 184         I40E_NONDMA_TO_NONDMA = 0,
 185         I40E_NONDMA_TO_DMA,
 186         I40E_DMA_TO_DMA,
 187         I40E_DMA_TO_NONDMA
 188 };
 189
 190 #ifdef X722_SUPPORT
 191 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 192 #endif
 193 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 194
 195
 196 /* These are structs for managing the hardware information and the operations.
 197  * The structures of function pointers are filled out at init time when we
 198  * know for sure exactly which hardware we're working with.  This gives us the
 199  * flexibility of using the same main driver code but adapting to slightly
 200  * different hardware needs as new parts are developed.  For this architecture,
 201  * the Firmware and AdminQ are intended to insulate the driver from most of the
 202  * future changes, but these structures will also do part of the job.
 203  */
 204 enum i40e_mac_type {
 205         I40E_MAC_UNKNOWN = 0,
 206         I40E_MAC_X710,
 207         I40E_MAC_XL710,
 208         I40E_MAC_VF,
 209 #ifdef X722_SUPPORT
 210         I40E_MAC_X722,
 211         I40E_MAC_X722_VF,
 212 #endif
 213         I40E_MAC_GENERIC,
 214 };
 215
 216 enum i40e_media_type {
 217         I40E_MEDIA_TYPE_UNKNOWN = 0,
 218         I40E_MEDIA_TYPE_FIBER,
 219         I40E_MEDIA_TYPE_BASET,
 220         I40E_MEDIA_TYPE_BACKPLANE,
 221         I40E_MEDIA_TYPE_CX4,
 222         I40E_MEDIA_TYPE_DA,
 223         I40E_MEDIA_TYPE_VIRTUAL
 224 };
 225
 226 enum i40e_fc_mode {
 227         I40E_FC_NONE = 0,
 228         I40E_FC_RX_PAUSE,
 229         I40E_FC_TX_PAUSE,
 230         I40E_FC_FULL,
 231         I40E_FC_PFC,
 232         I40E_FC_DEFAULT
 233 };
 234
 235 enum i40e_set_fc_aq_failures {
 236         I40E_SET_FC_AQ_FAIL_NONE = 0,
 237         I40E_SET_FC_AQ_FAIL_GET = 1,
 238         I40E_SET_FC_AQ_FAIL_SET = 2,
 239         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 240         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 241 };
 242
 243 enum i40e_vsi_type {
 244         I40E_VSI_MAIN   = 0,
 245         I40E_VSI_VMDQ1  = 1,
 246         I40E_VSI_VMDQ2  = 2,
 247         I40E_VSI_CTRL   = 3,
 248         I40E_VSI_FCOE   = 4,
 249         I40E_VSI_MIRROR = 5,
 250         I40E_VSI_SRIOV  = 6,
 251         I40E_VSI_FDIR   = 7,
 252         I40E_VSI_TYPE_UNKNOWN
 253 };
 254
 255 enum i40e_queue_type {
 256         I40E_QUEUE_TYPE_RX = 0,
 257         I40E_QUEUE_TYPE_TX,
 258         I40E_QUEUE_TYPE_PE_CEQ,
 259         I40E_QUEUE_TYPE_UNKNOWN
 260 };
 261
 262 struct i40e_link_status {
 263         enum i40e_aq_phy_type phy_type;
 264         enum i40e_aq_link_speed link_speed;
 265         u8 link_info;
 266         u8 an_info;
 267         u8 ext_info;
 268         u8 loopback;
 269         /* is Link Status Event notification to SW enabled */
 270         bool lse_enable;
 271         u16 max_frame_size;
 272         bool crc_enable;
 273         u8 pacing;
 274         u8 requested_speeds;
 275         u8 module_type[3];
 276         /* 1st byte: module identifier */
 277 #define I40E_MODULE_TYPE_SFP            0x03
 278 #define I40E_MODULE_TYPE_QSFP           0x0D
 279         /* 2nd byte: ethernet compliance codes for 10/40G */
 280 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 281 #define I40E_MODULE_TYPE_40G_LR4        0x02
 282 #define I40E_MODULE_TYPE_40G_SR4        0x04
 283 #define I40E_MODULE_TYPE_40G_CR4        0x08
 284 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 285 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 286 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 287 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 288         /* 3rd byte: ethernet compliance codes for 1G */
 289 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 290 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 291 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 292 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 293 };
 294
 295 enum i40e_aq_capabilities_phy_type {
 296         I40E_CAP_PHY_TYPE_SGMII                 = BIT(I40E_PHY_TYPE_SGMII),
 297         I40E_CAP_PHY_TYPE_1000BASE_KX           = BIT(I40E_PHY_TYPE_1000BASE_KX),
 298         I40E_CAP_PHY_TYPE_10GBASE_KX4           = BIT(I40E_PHY_TYPE_10GBASE_KX4),
 299         I40E_CAP_PHY_TYPE_10GBASE_KR            = BIT(I40E_PHY_TYPE_10GBASE_KR),
 300         I40E_CAP_PHY_TYPE_40GBASE_KR4           = BIT(I40E_PHY_TYPE_40GBASE_KR4),
 301         I40E_CAP_PHY_TYPE_XAUI                  = BIT(I40E_PHY_TYPE_XAUI),
 302         I40E_CAP_PHY_TYPE_XFI                   = BIT(I40E_PHY_TYPE_XFI),
 303         I40E_CAP_PHY_TYPE_SFI                   = BIT(I40E_PHY_TYPE_SFI),
 304         I40E_CAP_PHY_TYPE_XLAUI                 = BIT(I40E_PHY_TYPE_XLAUI),
 305         I40E_CAP_PHY_TYPE_XLPPI                 = BIT(I40E_PHY_TYPE_XLPPI),
 306         I40E_CAP_PHY_TYPE_40GBASE_CR4_CU        = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
 307         I40E_CAP_PHY_TYPE_10GBASE_CR1_CU        = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
 308         I40E_CAP_PHY_TYPE_10GBASE_AOC           = BIT(I40E_PHY_TYPE_10GBASE_AOC),
 309         I40E_CAP_PHY_TYPE_40GBASE_AOC           = BIT(I40E_PHY_TYPE_40GBASE_AOC),
 310         I40E_CAP_PHY_TYPE_100BASE_TX            = BIT(I40E_PHY_TYPE_100BASE_TX),
 311         I40E_CAP_PHY_TYPE_1000BASE_T            = BIT(I40E_PHY_TYPE_1000BASE_T),
 312         I40E_CAP_PHY_TYPE_10GBASE_T             = BIT(I40E_PHY_TYPE_10GBASE_T),
 313         I40E_CAP_PHY_TYPE_10GBASE_SR            = BIT(I40E_PHY_TYPE_10GBASE_SR),
 314         I40E_CAP_PHY_TYPE_10GBASE_LR            = BIT(I40E_PHY_TYPE_10GBASE_LR),
 315         I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU       = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
 316         I40E_CAP_PHY_TYPE_10GBASE_CR1           = BIT(I40E_PHY_TYPE_10GBASE_CR1),
 317         I40E_CAP_PHY_TYPE_40GBASE_CR4           = BIT(I40E_PHY_TYPE_40GBASE_CR4),
 318         I40E_CAP_PHY_TYPE_40GBASE_SR4           = BIT(I40E_PHY_TYPE_40GBASE_SR4),
 319         I40E_CAP_PHY_TYPE_40GBASE_LR4           = BIT(I40E_PHY_TYPE_40GBASE_LR4),
 320         I40E_CAP_PHY_TYPE_1000BASE_SX           = BIT(I40E_PHY_TYPE_1000BASE_SX),
 321         I40E_CAP_PHY_TYPE_1000BASE_LX           = BIT(I40E_PHY_TYPE_1000BASE_LX),
 322         I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL    = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
 323         I40E_CAP_PHY_TYPE_20GBASE_KR2           = BIT(I40E_PHY_TYPE_20GBASE_KR2)
 324 };
 325
 326 struct i40e_phy_info {
 327         struct i40e_link_status link_info;
 328         struct i40e_link_status link_info_old;
 329         bool get_link_info;
 330         enum i40e_media_type media_type;
 331         /* all the phy types the NVM is capable of */
 332         u32 phy_types;
 333 };
 334
 335 #define I40E_HW_CAP_MAX_GPIO                    30
 336 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 337 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 338
 339 #ifdef X722_SUPPORT
 340 enum i40e_acpi_programming_method {
 341         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 342         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 343 };
 344
 345 #define I40E_WOL_SUPPORT_MASK                   1
 346 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       (1 << 1)
 347 #define I40E_PROXY_SUPPORT_MASK                 (1 << 2)
 348
 349 #endif
 350 /* Capabilities of a PF or a VF or the whole device */
 351 struct i40e_hw_capabilities {
 352         u32  switch_mode;
 353 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 354 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 355 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 356
 357         u32  management_mode;
 358         u32  npar_enable;
 359         u32  os2bmc;
 360         u32  valid_functions;
 361         bool sr_iov_1_1;
 362         bool vmdq;
 363         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 364         bool evb_802_1_qbh; /* Bridge Port Extension */
 365         bool dcb;
 366         bool fcoe;
 367         bool iscsi; /* Indicates iSCSI enabled */
 368         bool flex10_enable;
 369         bool flex10_capable;
 370         u32  flex10_mode;
 371 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 372 #define I40E_FLEX10_MODE_DCC            0x1
 373 #define I40E_FLEX10_MODE_DCI            0x2
 374
 375         u32 flex10_status;
 376 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 377 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 378
 379         bool sec_rev_disabled;
 380         bool update_disabled;
 381 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 382 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 383
 384         bool mgmt_cem;
 385         bool ieee_1588;
 386         bool iwarp;
 387         bool fd;
 388         u32 fd_filters_guaranteed;
 389         u32 fd_filters_best_effort;
 390         bool rss;
 391         u32 rss_table_size;
 392         u32 rss_table_entry_width;
 393         bool led[I40E_HW_CAP_MAX_GPIO];
 394         bool sdp[I40E_HW_CAP_MAX_GPIO];
 395         u32 nvm_image_type;
 396         u32 num_flow_director_filters;
 397         u32 num_vfs;
 398         u32 vf_base_id;
 399         u32 num_vsis;
 400         u32 num_rx_qp;
 401         u32 num_tx_qp;
 402         u32 base_queue;
 403         u32 num_msix_vectors;
 404         u32 num_msix_vectors_vf;
 405         u32 led_pin_num;
 406         u32 sdp_pin_num;
 407         u32 mdio_port_num;
 408         u32 mdio_port_mode;
 409         u8 rx_buf_chain_len;
 410         u32 enabled_tcmap;
 411         u32 maxtc;
 412         u64 wr_csr_prot;
 413 #ifdef X722_SUPPORT
 414         bool apm_wol_support;
 415         enum i40e_acpi_programming_method acpi_prog_method;
 416         bool proxy_support;
 417 #endif
 418 };
 419
 420 struct i40e_mac_info {
 421         enum i40e_mac_type type;
 422         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 423         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 424         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 425         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 426         u16 max_fcoeq;
 427 };
 428
 429 enum i40e_aq_resources_ids {
 430         I40E_NVM_RESOURCE_ID = 1
 431 };
 432
 433 enum i40e_aq_resource_access_type {
 434         I40E_RESOURCE_READ = 1,
 435         I40E_RESOURCE_WRITE
 436 };
 437
 438 struct i40e_nvm_info {
 439         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 440         u32 timeout;              /* [ms] */
 441         u16 sr_size;              /* Shadow RAM size in words */
 442         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 443         u16 version;              /* NVM package version */
 444         u32 eetrack;              /* NVM data version */
 445         u32 oem_ver;              /* OEM version info */
 446 };
 447
 448 /* definitions used in NVM update support */
 449
 450 enum i40e_nvmupd_cmd {
 451         I40E_NVMUPD_INVALID,
 452         I40E_NVMUPD_READ_CON,
 453         I40E_NVMUPD_READ_SNT,
 454         I40E_NVMUPD_READ_LCB,
 455         I40E_NVMUPD_READ_SA,
 456         I40E_NVMUPD_WRITE_ERA,
 457         I40E_NVMUPD_WRITE_CON,
 458         I40E_NVMUPD_WRITE_SNT,
 459         I40E_NVMUPD_WRITE_LCB,
 460         I40E_NVMUPD_WRITE_SA,
 461         I40E_NVMUPD_CSUM_CON,
 462         I40E_NVMUPD_CSUM_SA,
 463         I40E_NVMUPD_CSUM_LCB,
 464         I40E_NVMUPD_STATUS,
 465         I40E_NVMUPD_EXEC_AQ,
 466         I40E_NVMUPD_GET_AQ_RESULT,
 467 };
 468
 469 enum i40e_nvmupd_state {
 470         I40E_NVMUPD_STATE_INIT,
 471         I40E_NVMUPD_STATE_READING,
 472         I40E_NVMUPD_STATE_WRITING,
 473         I40E_NVMUPD_STATE_INIT_WAIT,
 474         I40E_NVMUPD_STATE_WRITE_WAIT,
 475 };
 476
 477 /* nvm_access definition and its masks/shifts need to be accessible to
 478  * application, core driver, and shared code.  Where is the right file?
 479  */
 480 #define I40E_NVM_READ   0xB
 481 #define I40E_NVM_WRITE  0xC
 482
 483 #define I40E_NVM_MOD_PNT_MASK 0xFF
 484
 485 #define I40E_NVM_TRANS_SHIFT    8
 486 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 487 #define I40E_NVM_CON            0x0
 488 #define I40E_NVM_SNT            0x1
 489 #define I40E_NVM_LCB            0x2
 490 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 491 #define I40E_NVM_ERA            0x4
 492 #define I40E_NVM_CSUM           0x8
 493 #define I40E_NVM_EXEC           0xf
 494
 495 #define I40E_NVM_ADAPT_SHIFT    16
 496 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 497
 498 #define I40E_NVMUPD_MAX_DATA    4096
 499 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 500
 501 struct i40e_nvm_access {
 502         u32 command;
 503         u32 config;
 504         u32 offset;     /* in bytes */
 505         u32 data_size;  /* in bytes */
 506         u8 data[1];
 507 };
 508
 509 /* PCI bus types */
 510 enum i40e_bus_type {
 511         i40e_bus_type_unknown = 0,
 512         i40e_bus_type_pci,
 513         i40e_bus_type_pcix,
 514         i40e_bus_type_pci_express,
 515         i40e_bus_type_reserved
 516 };
 517
 518 /* PCI bus speeds */
 519 enum i40e_bus_speed {
 520         i40e_bus_speed_unknown  = 0,
 521         i40e_bus_speed_33       = 33,
 522         i40e_bus_speed_66       = 66,
 523         i40e_bus_speed_100      = 100,
 524         i40e_bus_speed_120      = 120,
 525         i40e_bus_speed_133      = 133,
 526         i40e_bus_speed_2500     = 2500,
 527         i40e_bus_speed_5000     = 5000,
 528         i40e_bus_speed_8000     = 8000,
 529         i40e_bus_speed_reserved
 530 };
 531
 532 /* PCI bus widths */
 533 enum i40e_bus_width {
 534         i40e_bus_width_unknown  = 0,
 535         i40e_bus_width_pcie_x1  = 1,
 536         i40e_bus_width_pcie_x2  = 2,
 537         i40e_bus_width_pcie_x4  = 4,
 538         i40e_bus_width_pcie_x8  = 8,
 539         i40e_bus_width_32       = 32,
 540         i40e_bus_width_64       = 64,
 541         i40e_bus_width_reserved
 542 };
 543
 544 /* Bus parameters */
 545 struct i40e_bus_info {
 546         enum i40e_bus_speed speed;
 547         enum i40e_bus_width width;
 548         enum i40e_bus_type type;
 549
 550         u16 func;
 551         u16 device;
 552         u16 lan_id;
 553 };
 554
 555 /* Flow control (FC) parameters */
 556 struct i40e_fc_info {
 557         enum i40e_fc_mode current_mode; /* FC mode in effect */
 558         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 559 };
 560
 561 #define I40E_MAX_TRAFFIC_CLASS          8
 562 #define I40E_MAX_USER_PRIORITY          8
 563 #define I40E_DCBX_MAX_APPS              32
 564 #define I40E_LLDPDU_SIZE                1500
 565 #define I40E_TLV_STATUS_OPER            0x1
 566 #define I40E_TLV_STATUS_SYNC            0x2
 567 #define I40E_TLV_STATUS_ERR             0x4
 568 #define I40E_CEE_OPER_MAX_APPS          3
 569 #define I40E_APP_PROTOID_FCOE           0x8906
 570 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 571 #define I40E_APP_PROTOID_FIP            0x8914
 572 #define I40E_APP_SEL_ETHTYPE            0x1
 573 #define I40E_APP_SEL_TCPIP              0x2
 574 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 575 #define I40E_CEE_APP_SEL_TCPIP          0x1
 576
 577 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 578 struct i40e_dcb_ets_config {
 579         u8 willing;
 580         u8 cbs;
 581         u8 maxtcs;
 582         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 583         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 584         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 585 };
 586
 587 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 588 struct i40e_dcb_pfc_config {
 589         u8 willing;
 590         u8 mbc;
 591         u8 pfccap;
 592         u8 pfcenable;
 593 };
 594
 595 /* CEE or IEEE 802.1Qaz Application Priority data */
 596 struct i40e_dcb_app_priority_table {
 597         u8  priority;
 598         u8  selector;
 599         u16 protocolid;
 600 };
 601
 602 struct i40e_dcbx_config {
 603         u8  dcbx_mode;
 604 #define I40E_DCBX_MODE_CEE      0x1
 605 #define I40E_DCBX_MODE_IEEE     0x2
 606         u8  app_mode;
 607 #define I40E_DCBX_APPS_NON_WILLING      0x1
 608         u32 numapps;
 609         u32 tlv_status; /* CEE mode TLV status */
 610         struct i40e_dcb_ets_config etscfg;
 611         struct i40e_dcb_ets_config etsrec;
 612         struct i40e_dcb_pfc_config pfc;
 613         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 614 };
 615
 616 /* Port hardware description */
 617 struct i40e_hw {
 618         u8 *hw_addr;
 619         void *back;
 620
 621         /* subsystem structs */
 622         struct i40e_phy_info phy;
 623         struct i40e_mac_info mac;
 624         struct i40e_bus_info bus;
 625         struct i40e_nvm_info nvm;
 626         struct i40e_fc_info fc;
 627
 628         /* pci info */
 629         u16 device_id;
 630         u16 vendor_id;
 631         u16 subsystem_device_id;
 632         u16 subsystem_vendor_id;
 633         u8 revision_id;
 634         u8 port;
 635         bool adapter_stopped;
 636
 637         /* capabilities for entire device and PCI func */
 638         struct i40e_hw_capabilities dev_caps;
 639         struct i40e_hw_capabilities func_caps;
 640
 641         /* Flow Director shared filter space */
 642         u16 fdir_shared_filter_count;
 643
 644         /* device profile info */
 645         u8  pf_id;
 646         u16 main_vsi_seid;
 647
 648         /* for multi-function MACs */
 649         u16 partition_id;
 650         u16 num_partitions;
 651         u16 num_ports;
 652
 653         /* Closest numa node to the device */
 654         u16 numa_node;
 655
 656         /* Admin Queue info */
 657         struct i40e_adminq_info aq;
 658
 659         /* state of nvm update process */
 660         enum i40e_nvmupd_state nvmupd_state;
 661         struct i40e_aq_desc nvm_wb_desc;
 662         struct i40e_virt_mem nvm_buff;
 663         bool nvm_release_on_done;
 664         u16 nvm_wait_opcode;
 665
 666         /* HMC info */
 667         struct i40e_hmc_info hmc; /* HMC info struct */
 668
 669         /* LLDP/DCBX Status */
 670         u16 dcbx_status;
 671
 672         /* DCBX info */
 673         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 674         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 675         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 676
 677 #ifdef X722_SUPPORT
 678         /* WoL and proxy support */
 679         u16 num_wol_proxy_filters;
 680         u16 wol_proxy_vsi_seid;
 681
 682 #endif
 683 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 684         u64 flags;
 685
 686         /* debug mask */
 687         u32 debug_mask;
 688 #ifndef I40E_NDIS_SUPPORT
 689         char err_str[16];
 690 #endif /* I40E_NDIS_SUPPORT */
 691 };
 692
 693 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 694 {
 695 #ifdef X722_SUPPORT
 696         return (hw->mac.type == I40E_MAC_VF ||
 697                 hw->mac.type == I40E_MAC_X722_VF);
 698 #else
 699         return hw->mac.type == I40E_MAC_VF;
 700 #endif
 701 }
 702
 703 struct i40e_driver_version {
 704         u8 major_version;
 705         u8 minor_version;
 706         u8 build_version;
 707         u8 subbuild_version;
 708         u8 driver_string[32];
 709 };
 710
 711 /* RX Descriptors */
 712 union i40e_16byte_rx_desc {
 713         struct {
 714                 __le64 pkt_addr; /* Packet buffer address */
 715                 __le64 hdr_addr; /* Header buffer address */
 716         } read;
 717         struct {
 718                 struct {
 719                         struct {
 720                                 union {
 721                                         __le16 mirroring_status;
 722                                         __le16 fcoe_ctx_id;
 723                                 } mirr_fcoe;
 724                                 __le16 l2tag1;
 725                         } lo_dword;
 726                         union {
 727                                 __le32 rss; /* RSS Hash */
 728                                 __le32 fd_id; /* Flow director filter id */
 729                                 __le32 fcoe_param; /* FCoE DDP Context id */
 730                         } hi_dword;
 731                 } qword0;
 732                 struct {
 733                         /* ext status/error/pktype/length */
 734                         __le64 status_error_len;
 735                 } qword1;
 736         } wb;  /* writeback */
 737 };
 738
 739 union i40e_32byte_rx_desc {
 740         struct {
 741                 __le64  pkt_addr; /* Packet buffer address */
 742                 __le64  hdr_addr; /* Header buffer address */
 743                         /* bit 0 of hdr_buffer_addr is DD bit */
 744                 __le64  rsvd1;
 745                 __le64  rsvd2;
 746         } read;
 747         struct {
 748                 struct {
 749                         struct {
 750                                 union {
 751                                         __le16 mirroring_status;
 752                                         __le16 fcoe_ctx_id;
 753                                 } mirr_fcoe;
 754                                 __le16 l2tag1;
 755                         } lo_dword;
 756                         union {
 757                                 __le32 rss; /* RSS Hash */
 758                                 __le32 fcoe_param; /* FCoE DDP Context id */
 759                                 /* Flow director filter id in case of
 760                                  * Programming status desc WB
 761                                  */
 762                                 __le32 fd_id;
 763                         } hi_dword;
 764                 } qword0;
 765                 struct {
 766                         /* status/error/pktype/length */
 767                         __le64 status_error_len;
 768                 } qword1;
 769                 struct {
 770                         __le16 ext_status; /* extended status */
 771                         __le16 rsvd;
 772                         __le16 l2tag2_1;
 773                         __le16 l2tag2_2;
 774                 } qword2;
 775                 struct {
 776                         union {
 777                                 __le32 flex_bytes_lo;
 778                                 __le32 pe_status;
 779                         } lo_dword;
 780                         union {
 781                                 __le32 flex_bytes_hi;
 782                                 __le32 fd_id;
 783                         } hi_dword;
 784                 } qword3;
 785         } wb;  /* writeback */
 786 };
 787
 788 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 789 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 790                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 791 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 792 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 793                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 794
 795 enum i40e_rx_desc_status_bits {
 796         /* Note: These are predefined bit offsets */
 797         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 798         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 799         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 800         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 801         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 802         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 803         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 804 #ifdef X722_SUPPORT
 805         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 806 #else
 807         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 808 #endif
 809
 810         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 811         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 812         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 813         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 814         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 815         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 816 #ifdef X722_SUPPORT
 817         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 818 #else
 819         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 820 #endif
 821         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 822 };
 823
 824 #define I40E_RXD_QW1_STATUS_SHIFT       0
 825 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 826                                          I40E_RXD_QW1_STATUS_SHIFT)
 827
 828 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 829 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 830                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 831
 832 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 833 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 834
 835 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 836 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 837                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 838
 839 enum i40e_rx_desc_fltstat_values {
 840         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 841         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 842         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 843         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 844 };
 845
 846 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 847 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 848 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 849 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 850
 851 #define I40E_RXD_QW1_ERROR_SHIFT        19
 852 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 853
 854 enum i40e_rx_desc_error_bits {
 855         /* Note: These are predefined bit offsets */
 856         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 857         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 858         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 859         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 860         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 861         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 862         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 863         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 864         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 865 };
 866
 867 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 868         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 869         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 870         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 871         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 872         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 873 };
 874
 875 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 876 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 877
 878 /* Packet type non-ip values */
 879 enum i40e_rx_l2_ptype {
 880         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 881         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 882         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 883         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 884         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 885         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 886         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 887         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 888         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 889         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 890         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 891         I40E_RX_PTYPE_L2_ARP                            = 11,
 892         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 893         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 894         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 895         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 896         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 897         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 898         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 899         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 900         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 901         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 902         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 903         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 904         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 905         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 906 };
 907
 908 struct i40e_rx_ptype_decoded {
 909         u32 ptype:8;
 910         u32 known:1;
 911         u32 outer_ip:1;
 912         u32 outer_ip_ver:1;
 913         u32 outer_frag:1;
 914         u32 tunnel_type:3;
 915         u32 tunnel_end_prot:2;
 916         u32 tunnel_end_frag:1;
 917         u32 inner_prot:4;
 918         u32 payload_layer:3;
 919 };
 920
 921 enum i40e_rx_ptype_outer_ip {
 922         I40E_RX_PTYPE_OUTER_L2  = 0,
 923         I40E_RX_PTYPE_OUTER_IP  = 1
 924 };
 925
 926 enum i40e_rx_ptype_outer_ip_ver {
 927         I40E_RX_PTYPE_OUTER_NONE        = 0,
 928         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 929         I40E_RX_PTYPE_OUTER_IPV6        = 1
 930 };
 931
 932 enum i40e_rx_ptype_outer_fragmented {
 933         I40E_RX_PTYPE_NOT_FRAG  = 0,
 934         I40E_RX_PTYPE_FRAG      = 1
 935 };
 936
 937 enum i40e_rx_ptype_tunnel_type {
 938         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 939         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 940         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 941         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 942         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 943 };
 944
 945 enum i40e_rx_ptype_tunnel_end_prot {
 946         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 947         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 948         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 949 };
 950
 951 enum i40e_rx_ptype_inner_prot {
 952         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 953         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 954         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 955         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 956         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 957         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 958 };
 959
 960 enum i40e_rx_ptype_payload_layer {
 961         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 962         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 963         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 964         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 965 };
 966
 967 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 968 #define I40E_RX_PTYPE_SHIFT             56
 969
 970 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 971 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 972                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 973
 974 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 975 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 976                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 977
 978 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 979 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 980
 981 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 982 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 983
 984 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 985 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 986                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 987
 988 enum i40e_rx_desc_ext_status_bits {
 989         /* Note: These are predefined bit offsets */
 990         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 991         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 992         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 993         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 994         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 995         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 996         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 997 };
 998
 999 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1000 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1001
1002 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1003 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1004
1005 enum i40e_rx_desc_pe_status_bits {
1006         /* Note: These are predefined bit offsets */
1007         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1008         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1009         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1010         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1011         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1012         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1013         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1014         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1015         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1016 };
1017
1018 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1019 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1020
1021 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1022 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1023                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1024
1025 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1026 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1027                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1028
1029 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1030 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1031                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1032
1033 enum i40e_rx_prog_status_desc_status_bits {
1034         /* Note: These are predefined bit offsets */
1035         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1036         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1037 };
1038
1039 enum i40e_rx_prog_status_desc_prog_id_masks {
1040         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1041         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1042         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1043 };
1044
1045 enum i40e_rx_prog_status_desc_error_bits {
1046         /* Note: These are predefined bit offsets */
1047         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1048         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1049         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1050         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1051 };
1052
1053 #define I40E_TWO_BIT_MASK       0x3
1054 #define I40E_THREE_BIT_MASK     0x7
1055 #define I40E_FOUR_BIT_MASK      0xF
1056 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1057
1058 /* TX Descriptor */
1059 struct i40e_tx_desc {
1060         __le64 buffer_addr; /* Address of descriptor's data buf */
1061         __le64 cmd_type_offset_bsz;
1062 };
1063
1064 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1065 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1066
1067 enum i40e_tx_desc_dtype_value {
1068         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1069         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1070         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1071         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1072         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1073         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1074         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1075         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1076         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1077         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1078 };
1079
1080 #define I40E_TXD_QW1_CMD_SHIFT  4
1081 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1082
1083 enum i40e_tx_desc_cmd_bits {
1084         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1085         I40E_TX_DESC_CMD_RS                     = 0x0002,
1086         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1087         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1088         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1089         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1090         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1091         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1092         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1093         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1094         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1095         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1096         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1097         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1098         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1099         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1100         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1101         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1102 };
1103
1104 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1105 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1106                                          I40E_TXD_QW1_OFFSET_SHIFT)
1107
1108 enum i40e_tx_desc_length_fields {
1109         /* Note: These are predefined bit offsets */
1110         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1111         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1112         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1113 };
1114
1115 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1116 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1117 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1118 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1119
1120 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1121 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1122                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1123
1124 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1125 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1126
1127 /* Context descriptors */
1128 struct i40e_tx_context_desc {
1129         __le32 tunneling_params;
1130         __le16 l2tag2;
1131         __le16 rsvd;
1132         __le64 type_cmd_tso_mss;
1133 };
1134
1135 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1136 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1137
1138 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1139 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1140
1141 enum i40e_tx_ctx_desc_cmd_bits {
1142         I40E_TX_CTX_DESC_TSO            = 0x01,
1143         I40E_TX_CTX_DESC_TSYN           = 0x02,
1144         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1145         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1146         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1147         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1148         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1149         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1150         I40E_TX_CTX_DESC_SWPE           = 0x40
1151 };
1152
1153 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1154 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1155                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1156
1157 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1158 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1159                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1160
1161 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1162 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1163
1164 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1165 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1166                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1167
1168 enum i40e_tx_ctx_desc_eipt_offload {
1169         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1170         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1171         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1172         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1173 };
1174
1175 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1176 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1177                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1178
1179 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1180 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1181
1182 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1183 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1184
1185 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1186 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1187
1188 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1189
1190 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1191 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1192                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1193
1194 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1195 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1196                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1197
1198 #ifdef X722_SUPPORT
1199 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1200 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1201 #endif
1202 struct i40e_nop_desc {
1203         __le64 rsvd;
1204         __le64 dtype_cmd;
1205 };
1206
1207 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1208 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1209
1210 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1211 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1212
1213 enum i40e_tx_nop_desc_cmd_bits {
1214         /* Note: These are predefined bit offsets */
1215         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1216         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1217         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1218 };
1219
1220 struct i40e_filter_program_desc {
1221         __le32 qindex_flex_ptype_vsi;
1222         __le32 rsvd;
1223         __le32 dtype_cmd_cntindex;
1224         __le32 fd_id;
1225 };
1226 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1227 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1228                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1229 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1230 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1231                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1232 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1233 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1234                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1235
1236 /* Packet Classifier Types for filters */
1237 enum i40e_filter_pctype {
1238 #ifdef X722_SUPPORT
1239         /* Note: Values 0-28 are reserved for future use.
1240          * Value 29, 30, 32 are not supported on XL710 and X710.
1241          */
1242         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1243         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1244 #else
1245         /* Note: Values 0-30 are reserved for future use */
1246 #endif
1247         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1248 #ifdef X722_SUPPORT
1249         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1250 #else
1251         /* Note: Value 32 is reserved for future use */
1252 #endif
1253         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1254         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1255         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1256         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1257 #ifdef X722_SUPPORT
1258         /* Note: Values 37-38 are reserved for future use.
1259          * Value 39, 40, 42 are not supported on XL710 and X710.
1260          */
1261         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1262         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1263 #else
1264         /* Note: Values 37-40 are reserved for future use */
1265 #endif
1266         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1267 #ifdef X722_SUPPORT
1268         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1269 #endif
1270         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1271         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1272         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1273         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1274         /* Note: Value 47 is reserved for future use */
1275         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1276         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1277         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1278         /* Note: Values 51-62 are reserved for future use */
1279         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1280 };
1281
1282 enum i40e_filter_program_desc_dest {
1283         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1284         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1285         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1286 };
1287
1288 enum i40e_filter_program_desc_fd_status {
1289         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1290         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1291         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1292         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1293 };
1294
1295 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1296 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1297                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1298
1299 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1300 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1301
1302 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1303 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1304                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1305
1306 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1307 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1308
1309 enum i40e_filter_program_desc_pcmd {
1310         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1311         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1312 };
1313
1314 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1315 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1316
1317 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1318 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1319
1320 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1321                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1322 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1323                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1324 #ifdef X722_SUPPORT
1325
1326 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1327                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1328 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1329 #endif
1330
1331 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1332 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1333                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1334
1335 enum i40e_filter_type {
1336         I40E_FLOW_DIRECTOR_FLTR = 0,
1337         I40E_PE_QUAD_HASH_FLTR = 1,
1338         I40E_ETHERTYPE_FLTR,
1339         I40E_FCOE_CTX_FLTR,
1340         I40E_MAC_VLAN_FLTR,
1341         I40E_HASH_FLTR
1342 };
1343
1344 struct i40e_vsi_context {
1345         u16 seid;
1346         u16 uplink_seid;
1347         u16 vsi_number;
1348         u16 vsis_allocated;
1349         u16 vsis_unallocated;
1350         u16 flags;
1351         u8 pf_num;
1352         u8 vf_num;
1353         u8 connection_type;
1354         struct i40e_aqc_vsi_properties_data info;
1355 };
1356
1357 struct i40e_veb_context {
1358         u16 seid;
1359         u16 uplink_seid;
1360         u16 veb_number;
1361         u16 vebs_allocated;
1362         u16 vebs_unallocated;
1363         u16 flags;
1364         struct i40e_aqc_get_veb_parameters_completion info;
1365 };
1366
1367 /* Statistics collected by each port, VSI, VEB, and S-channel */
1368 struct i40e_eth_stats {
1369         u64 rx_bytes;                   /* gorc */
1370         u64 rx_unicast;                 /* uprc */
1371         u64 rx_multicast;               /* mprc */
1372         u64 rx_broadcast;               /* bprc */
1373         u64 rx_discards;                /* rdpc */
1374         u64 rx_unknown_protocol;        /* rupp */
1375         u64 tx_bytes;                   /* gotc */
1376         u64 tx_unicast;                 /* uptc */
1377         u64 tx_multicast;               /* mptc */
1378         u64 tx_broadcast;               /* bptc */
1379         u64 tx_discards;                /* tdpc */
1380         u64 tx_errors;                  /* tepc */
1381 };
1382
1383 /* Statistics collected per VEB per TC */
1384 struct i40e_veb_tc_stats {
1385         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1386         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1387         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1388         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1389 };
1390
1391 /* Statistics collected by the MAC */
1392 struct i40e_hw_port_stats {
1393         /* eth stats collected by the port */
1394         struct i40e_eth_stats eth;
1395
1396         /* additional port specific stats */
1397         u64 tx_dropped_link_down;       /* tdold */
1398         u64 crc_errors;                 /* crcerrs */
1399         u64 illegal_bytes;              /* illerrc */
1400         u64 error_bytes;                /* errbc */
1401         u64 mac_local_faults;           /* mlfc */
1402         u64 mac_remote_faults;          /* mrfc */
1403         u64 rx_length_errors;           /* rlec */
1404         u64 link_xon_rx;                /* lxonrxc */
1405         u64 link_xoff_rx;               /* lxoffrxc */
1406         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1407         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1408         u64 link_xon_tx;                /* lxontxc */
1409         u64 link_xoff_tx;               /* lxofftxc */
1410         u64 priority_xon_tx[8];         /* pxontxc[8] */
1411         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1412         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1413         u64 rx_size_64;                 /* prc64 */
1414         u64 rx_size_127;                /* prc127 */
1415         u64 rx_size_255;                /* prc255 */
1416         u64 rx_size_511;                /* prc511 */
1417         u64 rx_size_1023;               /* prc1023 */
1418         u64 rx_size_1522;               /* prc1522 */
1419         u64 rx_size_big;                /* prc9522 */
1420         u64 rx_undersize;               /* ruc */
1421         u64 rx_fragments;               /* rfc */
1422         u64 rx_oversize;                /* roc */
1423         u64 rx_jabber;                  /* rjc */
1424         u64 tx_size_64;                 /* ptc64 */
1425         u64 tx_size_127;                /* ptc127 */
1426         u64 tx_size_255;                /* ptc255 */
1427         u64 tx_size_511;                /* ptc511 */
1428         u64 tx_size_1023;               /* ptc1023 */
1429         u64 tx_size_1522;               /* ptc1522 */
1430         u64 tx_size_big;                /* ptc9522 */
1431         u64 mac_short_packet_dropped;   /* mspdc */
1432         u64 checksum_error;             /* xec */
1433         /* flow director stats */
1434         u64 fd_atr_match;
1435         u64 fd_sb_match;
1436         u64 fd_atr_tunnel_match;
1437         u32 fd_atr_status;
1438         u32 fd_sb_status;
1439         /* EEE LPI */
1440         u32 tx_lpi_status;
1441         u32 rx_lpi_status;
1442         u64 tx_lpi_count;               /* etlpic */
1443         u64 rx_lpi_count;               /* erlpic */
1444 };
1445
1446 /* Checksum and Shadow RAM pointers */
1447 #define I40E_SR_NVM_CONTROL_WORD                0x00
1448 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1449 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1450 #define I40E_SR_OPTION_ROM_PTR                  0x05
1451 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1452 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1453 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1454 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1455 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1456 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1457 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1458 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1459 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1460 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1461 #define I40E_SR_PBA_FLAGS                       0x15
1462 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1463 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1464 #define I40E_NVM_OEM_VER_OFF                    0x83
1465 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1466 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1467 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1468 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1469 #define I40E_SR_NVM_MAP_VERSION                 0x29
1470 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1471 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1472 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1473 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1474 #define I40E_SR_VPD_PTR                         0x2F
1475 #define I40E_SR_PXE_SETUP_PTR                   0x30
1476 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1477 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1478 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1479 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1480 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1481 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1482 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1483 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1484 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1485 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1486 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1487 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1488 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1489 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1490 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1491 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1492 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1493 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1494
1495 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1496 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1497 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1498 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1499 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1500
1501 /* Shadow RAM related */
1502 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1503 #define I40E_SR_BUF_ALIGNMENT           4096
1504 #define I40E_SR_WORDS_IN_1KB            512
1505 /* Checksum should be calculated such that after adding all the words,
1506  * including the checksum word itself, the sum should be 0xBABA.
1507  */
1508 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1509
1510 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1511
1512 enum i40e_switch_element_types {
1513         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1514         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1515         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1516         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1517         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1518         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1519         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1520         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1521         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1522 };
1523
1524 /* Supported EtherType filters */
1525 enum i40e_ether_type_index {
1526         I40E_ETHER_TYPE_1588            = 0,
1527         I40E_ETHER_TYPE_FIP             = 1,
1528         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1529         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1530         I40E_ETHER_TYPE_LLDP            = 4,
1531         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1532         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1533         I40E_ETHER_TYPE_QCN_CNM         = 7,
1534         I40E_ETHER_TYPE_8021X           = 8,
1535         I40E_ETHER_TYPE_ARP             = 9,
1536         I40E_ETHER_TYPE_RSV1            = 10,
1537         I40E_ETHER_TYPE_RSV2            = 11,
1538 };
1539
1540 /* Filter context base size is 1K */
1541 #define I40E_HASH_FILTER_BASE_SIZE      1024
1542 /* Supported Hash filter values */
1543 enum i40e_hash_filter_size {
1544         I40E_HASH_FILTER_SIZE_1K        = 0,
1545         I40E_HASH_FILTER_SIZE_2K        = 1,
1546         I40E_HASH_FILTER_SIZE_4K        = 2,
1547         I40E_HASH_FILTER_SIZE_8K        = 3,
1548         I40E_HASH_FILTER_SIZE_16K       = 4,
1549         I40E_HASH_FILTER_SIZE_32K       = 5,
1550         I40E_HASH_FILTER_SIZE_64K       = 6,
1551         I40E_HASH_FILTER_SIZE_128K      = 7,
1552         I40E_HASH_FILTER_SIZE_256K      = 8,
1553         I40E_HASH_FILTER_SIZE_512K      = 9,
1554         I40E_HASH_FILTER_SIZE_1M        = 10,
1555 };
1556
1557 /* DMA context base size is 0.5K */
1558 #define I40E_DMA_CNTX_BASE_SIZE         512
1559 /* Supported DMA context values */
1560 enum i40e_dma_cntx_size {
1561         I40E_DMA_CNTX_SIZE_512          = 0,
1562         I40E_DMA_CNTX_SIZE_1K           = 1,
1563         I40E_DMA_CNTX_SIZE_2K           = 2,
1564         I40E_DMA_CNTX_SIZE_4K           = 3,
1565         I40E_DMA_CNTX_SIZE_8K           = 4,
1566         I40E_DMA_CNTX_SIZE_16K          = 5,
1567         I40E_DMA_CNTX_SIZE_32K          = 6,
1568         I40E_DMA_CNTX_SIZE_64K          = 7,
1569         I40E_DMA_CNTX_SIZE_128K         = 8,
1570         I40E_DMA_CNTX_SIZE_256K         = 9,
1571 };
1572
1573 /* Supported Hash look up table (LUT) sizes */
1574 enum i40e_hash_lut_size {
1575         I40E_HASH_LUT_SIZE_128          = 0,
1576         I40E_HASH_LUT_SIZE_512          = 1,
1577 };
1578
1579 /* Structure to hold a per PF filter control settings */
1580 struct i40e_filter_control_settings {
1581         /* number of PE Quad Hash filter buckets */
1582         enum i40e_hash_filter_size pe_filt_num;
1583         /* number of PE Quad Hash contexts */
1584         enum i40e_dma_cntx_size pe_cntx_num;
1585         /* number of FCoE filter buckets */
1586         enum i40e_hash_filter_size fcoe_filt_num;
1587         /* number of FCoE DDP contexts */
1588         enum i40e_dma_cntx_size fcoe_cntx_num;
1589         /* size of the Hash LUT */
1590         enum i40e_hash_lut_size hash_lut_size;
1591         /* enable FDIR filters for PF and its VFs */
1592         bool enable_fdir;
1593         /* enable Ethertype filters for PF and its VFs */
1594         bool enable_ethtype;
1595         /* enable MAC/VLAN filters for PF and its VFs */
1596         bool enable_macvlan;
1597 };
1598
1599 /* Structure to hold device level control filter counts */
1600 struct i40e_control_filter_stats {
1601         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1602         u16 etype_used;       /* Used perfect EtherType filters */
1603         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1604         u16 etype_free;       /* Un-used perfect EtherType filters */
1605 };
1606
1607 enum i40e_reset_type {
1608         I40E_RESET_POR          = 0,
1609         I40E_RESET_CORER        = 1,
1610         I40E_RESET_GLOBR        = 2,
1611         I40E_RESET_EMPR         = 3,
1612 };
1613
1614 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1615 #define I40E_NVM_LLDP_CFG_PTR           0xD
1616 struct i40e_lldp_variables {
1617         u16 length;
1618         u16 adminstatus;
1619         u16 msgfasttx;
1620         u16 msgtxinterval;
1621         u16 txparams;
1622         u16 timers;
1623         u16 crc8;
1624 };
1625
1626 /* Offsets into Alternate Ram */
1627 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1628 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1629 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1630 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1631 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1632 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1633
1634 /* Alternate Ram Bandwidth Masks */
1635 #define I40E_ALT_BW_VALUE_MASK          0xFF
1636 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1637 #define I40E_ALT_BW_VALID_MASK          0x80000000
1638
1639 /* RSS Hash Table Size */
1640 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1641
1642 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1643 #define I40E_L3_SRC_SHIFT               47
1644 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1645 #define I40E_L3_V6_SRC_SHIFT            43
1646 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1647 #define I40E_L3_DST_SHIFT               35
1648 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1649 #define I40E_L3_V6_DST_SHIFT            35
1650 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1651 #define I40E_L4_SRC_SHIFT               34
1652 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1653 #define I40E_L4_DST_SHIFT               33
1654 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1655 #define I40E_VERIFY_TAG_SHIFT           31
1656 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1657
1658 #define I40E_FLEX_50_SHIFT              13
1659 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1660 #define I40E_FLEX_51_SHIFT              12
1661 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1662 #define I40E_FLEX_52_SHIFT              11
1663 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1664 #define I40E_FLEX_53_SHIFT              10
1665 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1666 #define I40E_FLEX_54_SHIFT              9
1667 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1668 #define I40E_FLEX_55_SHIFT              8
1669 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1670 #define I40E_FLEX_56_SHIFT              7
1671 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1672 #define I40E_FLEX_57_SHIFT              6
1673 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1674 #endif /* _I40E_TYPE_H_ */