drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 #define I40E_MDIO_STCODE                I40E_MASK(0, \
 161                                                   I40E_GLGEN_MSCA_STCODE_SHIFT)
 162 #define I40E_MDIO_OPCODE_ADDRESS        I40E_MASK(0, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_OPCODE_WRITE          I40E_MASK(1, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166 #define I40E_MDIO_OPCODE_READ_INC_ADDR  I40E_MASK(2, \
 167                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 168 #define I40E_MDIO_OPCODE_READ           I40E_MASK(3, \
 169                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 170
 171 #define I40E_PHY_COM_REG_PAGE                   0x1E
 172 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 173 #define I40E_PHY_LED_MANUAL_ON                  0x100
 174 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 175 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 176 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 177
 178 /* Memory types */
 179 enum i40e_memset_type {
 180         I40E_NONDMA_MEM = 0,
 181         I40E_DMA_MEM
 182 };
 183
 184 /* Memcpy types */
 185 enum i40e_memcpy_type {
 186         I40E_NONDMA_TO_NONDMA = 0,
 187         I40E_NONDMA_TO_DMA,
 188         I40E_DMA_TO_DMA,
 189         I40E_DMA_TO_NONDMA
 190 };
 191
 192 #ifdef X722_SUPPORT
 193 #define I40E_FW_API_VERSION_MINOR_X722  0x0005
 194 #endif
 195 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 196
 197
 198 /* These are structs for managing the hardware information and the operations.
 199  * The structures of function pointers are filled out at init time when we
 200  * know for sure exactly which hardware we're working with.  This gives us the
 201  * flexibility of using the same main driver code but adapting to slightly
 202  * different hardware needs as new parts are developed.  For this architecture,
 203  * the Firmware and AdminQ are intended to insulate the driver from most of the
 204  * future changes, but these structures will also do part of the job.
 205  */
 206 enum i40e_mac_type {
 207         I40E_MAC_UNKNOWN = 0,
 208         I40E_MAC_X710,
 209         I40E_MAC_XL710,
 210         I40E_MAC_VF,
 211 #ifdef X722_SUPPORT
 212         I40E_MAC_X722,
 213         I40E_MAC_X722_VF,
 214 #endif
 215         I40E_MAC_GENERIC,
 216 };
 217
 218 enum i40e_media_type {
 219         I40E_MEDIA_TYPE_UNKNOWN = 0,
 220         I40E_MEDIA_TYPE_FIBER,
 221         I40E_MEDIA_TYPE_BASET,
 222         I40E_MEDIA_TYPE_BACKPLANE,
 223         I40E_MEDIA_TYPE_CX4,
 224         I40E_MEDIA_TYPE_DA,
 225         I40E_MEDIA_TYPE_VIRTUAL
 226 };
 227
 228 enum i40e_fc_mode {
 229         I40E_FC_NONE = 0,
 230         I40E_FC_RX_PAUSE,
 231         I40E_FC_TX_PAUSE,
 232         I40E_FC_FULL,
 233         I40E_FC_PFC,
 234         I40E_FC_DEFAULT
 235 };
 236
 237 enum i40e_set_fc_aq_failures {
 238         I40E_SET_FC_AQ_FAIL_NONE = 0,
 239         I40E_SET_FC_AQ_FAIL_GET = 1,
 240         I40E_SET_FC_AQ_FAIL_SET = 2,
 241         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 242         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 243 };
 244
 245 enum i40e_vsi_type {
 246         I40E_VSI_MAIN   = 0,
 247         I40E_VSI_VMDQ1  = 1,
 248         I40E_VSI_VMDQ2  = 2,
 249         I40E_VSI_CTRL   = 3,
 250         I40E_VSI_FCOE   = 4,
 251         I40E_VSI_MIRROR = 5,
 252         I40E_VSI_SRIOV  = 6,
 253         I40E_VSI_FDIR   = 7,
 254         I40E_VSI_TYPE_UNKNOWN
 255 };
 256
 257 enum i40e_queue_type {
 258         I40E_QUEUE_TYPE_RX = 0,
 259         I40E_QUEUE_TYPE_TX,
 260         I40E_QUEUE_TYPE_PE_CEQ,
 261         I40E_QUEUE_TYPE_UNKNOWN
 262 };
 263
 264 struct i40e_link_status {
 265         enum i40e_aq_phy_type phy_type;
 266         enum i40e_aq_link_speed link_speed;
 267         u8 link_info;
 268         u8 an_info;
 269         u8 ext_info;
 270         u8 loopback;
 271         /* is Link Status Event notification to SW enabled */
 272         bool lse_enable;
 273         u16 max_frame_size;
 274         bool crc_enable;
 275         u8 pacing;
 276         u8 requested_speeds;
 277         u8 module_type[3];
 278         /* 1st byte: module identifier */
 279 #define I40E_MODULE_TYPE_SFP            0x03
 280 #define I40E_MODULE_TYPE_QSFP           0x0D
 281         /* 2nd byte: ethernet compliance codes for 10/40G */
 282 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 283 #define I40E_MODULE_TYPE_40G_LR4        0x02
 284 #define I40E_MODULE_TYPE_40G_SR4        0x04
 285 #define I40E_MODULE_TYPE_40G_CR4        0x08
 286 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 287 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 288 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 289 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 290         /* 3rd byte: ethernet compliance codes for 1G */
 291 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 292 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 293 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 294 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 295 };
 296
 297 struct i40e_phy_info {
 298         struct i40e_link_status link_info;
 299         struct i40e_link_status link_info_old;
 300         bool get_link_info;
 301         enum i40e_media_type media_type;
 302         /* all the phy types the NVM is capable of */
 303         u64 phy_types;
 304 };
 305
 306 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 307 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 308 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 309 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 310 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 311 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 312 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 313 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 314 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 315 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 316 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 317 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 318 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 319 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 320 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 321 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 322 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 323 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 324 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 325 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 326 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 327 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 328 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 329 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 330 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 331 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 332 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 333                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 334 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 335 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)
 336 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)
 337 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)
 338 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)
 339 #define I40E_HW_CAP_MAX_GPIO                    30
 340 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 341 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 342
 343 #ifdef X722_SUPPORT
 344 enum i40e_acpi_programming_method {
 345         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 346         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 347 };
 348
 349 #define I40E_WOL_SUPPORT_MASK                   1
 350 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       (1 << 1)
 351 #define I40E_PROXY_SUPPORT_MASK                 (1 << 2)
 352
 353 #endif
 354 /* Capabilities of a PF or a VF or the whole device */
 355 struct i40e_hw_capabilities {
 356         u32  switch_mode;
 357 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 358 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 359 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 360
 361         u32  management_mode;
 362         u32  npar_enable;
 363         u32  os2bmc;
 364         u32  valid_functions;
 365         bool sr_iov_1_1;
 366         bool vmdq;
 367         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 368         bool evb_802_1_qbh; /* Bridge Port Extension */
 369         bool dcb;
 370         bool fcoe;
 371         bool iscsi; /* Indicates iSCSI enabled */
 372         bool flex10_enable;
 373         bool flex10_capable;
 374         u32  flex10_mode;
 375 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 376 #define I40E_FLEX10_MODE_DCC            0x1
 377 #define I40E_FLEX10_MODE_DCI            0x2
 378
 379         u32 flex10_status;
 380 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 381 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 382
 383         bool sec_rev_disabled;
 384         bool update_disabled;
 385 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 386 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 387
 388         bool mgmt_cem;
 389         bool ieee_1588;
 390         bool iwarp;
 391         bool fd;
 392         u32 fd_filters_guaranteed;
 393         u32 fd_filters_best_effort;
 394         bool rss;
 395         u32 rss_table_size;
 396         u32 rss_table_entry_width;
 397         bool led[I40E_HW_CAP_MAX_GPIO];
 398         bool sdp[I40E_HW_CAP_MAX_GPIO];
 399         u32 nvm_image_type;
 400         u32 num_flow_director_filters;
 401         u32 num_vfs;
 402         u32 vf_base_id;
 403         u32 num_vsis;
 404         u32 num_rx_qp;
 405         u32 num_tx_qp;
 406         u32 base_queue;
 407         u32 num_msix_vectors;
 408         u32 num_msix_vectors_vf;
 409         u32 led_pin_num;
 410         u32 sdp_pin_num;
 411         u32 mdio_port_num;
 412         u32 mdio_port_mode;
 413         u8 rx_buf_chain_len;
 414         u32 enabled_tcmap;
 415         u32 maxtc;
 416         u64 wr_csr_prot;
 417 #ifdef X722_SUPPORT
 418         bool apm_wol_support;
 419         enum i40e_acpi_programming_method acpi_prog_method;
 420         bool proxy_support;
 421 #endif
 422 };
 423
 424 struct i40e_mac_info {
 425         enum i40e_mac_type type;
 426         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 427         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 428         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 429         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 430         u16 max_fcoeq;
 431 };
 432
 433 enum i40e_aq_resources_ids {
 434         I40E_NVM_RESOURCE_ID = 1
 435 };
 436
 437 enum i40e_aq_resource_access_type {
 438         I40E_RESOURCE_READ = 1,
 439         I40E_RESOURCE_WRITE
 440 };
 441
 442 struct i40e_nvm_info {
 443         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 444         u32 timeout;              /* [ms] */
 445         u16 sr_size;              /* Shadow RAM size in words */
 446         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 447         u16 version;              /* NVM package version */
 448         u32 eetrack;              /* NVM data version */
 449         u32 oem_ver;              /* OEM version info */
 450 };
 451
 452 /* definitions used in NVM update support */
 453
 454 enum i40e_nvmupd_cmd {
 455         I40E_NVMUPD_INVALID,
 456         I40E_NVMUPD_READ_CON,
 457         I40E_NVMUPD_READ_SNT,
 458         I40E_NVMUPD_READ_LCB,
 459         I40E_NVMUPD_READ_SA,
 460         I40E_NVMUPD_WRITE_ERA,
 461         I40E_NVMUPD_WRITE_CON,
 462         I40E_NVMUPD_WRITE_SNT,
 463         I40E_NVMUPD_WRITE_LCB,
 464         I40E_NVMUPD_WRITE_SA,
 465         I40E_NVMUPD_CSUM_CON,
 466         I40E_NVMUPD_CSUM_SA,
 467         I40E_NVMUPD_CSUM_LCB,
 468         I40E_NVMUPD_STATUS,
 469         I40E_NVMUPD_EXEC_AQ,
 470         I40E_NVMUPD_GET_AQ_RESULT,
 471 };
 472
 473 enum i40e_nvmupd_state {
 474         I40E_NVMUPD_STATE_INIT,
 475         I40E_NVMUPD_STATE_READING,
 476         I40E_NVMUPD_STATE_WRITING,
 477         I40E_NVMUPD_STATE_INIT_WAIT,
 478         I40E_NVMUPD_STATE_WRITE_WAIT,
 479 };
 480
 481 /* nvm_access definition and its masks/shifts need to be accessible to
 482  * application, core driver, and shared code.  Where is the right file?
 483  */
 484 #define I40E_NVM_READ   0xB
 485 #define I40E_NVM_WRITE  0xC
 486
 487 #define I40E_NVM_MOD_PNT_MASK 0xFF
 488
 489 #define I40E_NVM_TRANS_SHIFT    8
 490 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 491 #define I40E_NVM_CON            0x0
 492 #define I40E_NVM_SNT            0x1
 493 #define I40E_NVM_LCB            0x2
 494 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 495 #define I40E_NVM_ERA            0x4
 496 #define I40E_NVM_CSUM           0x8
 497 #define I40E_NVM_EXEC           0xf
 498
 499 #define I40E_NVM_ADAPT_SHIFT    16
 500 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 501
 502 #define I40E_NVMUPD_MAX_DATA    4096
 503 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 504
 505 struct i40e_nvm_access {
 506         u32 command;
 507         u32 config;
 508         u32 offset;     /* in bytes */
 509         u32 data_size;  /* in bytes */
 510         u8 data[1];
 511 };
 512
 513 /* PCI bus types */
 514 enum i40e_bus_type {
 515         i40e_bus_type_unknown = 0,
 516         i40e_bus_type_pci,
 517         i40e_bus_type_pcix,
 518         i40e_bus_type_pci_express,
 519         i40e_bus_type_reserved
 520 };
 521
 522 /* PCI bus speeds */
 523 enum i40e_bus_speed {
 524         i40e_bus_speed_unknown  = 0,
 525         i40e_bus_speed_33       = 33,
 526         i40e_bus_speed_66       = 66,
 527         i40e_bus_speed_100      = 100,
 528         i40e_bus_speed_120      = 120,
 529         i40e_bus_speed_133      = 133,
 530         i40e_bus_speed_2500     = 2500,
 531         i40e_bus_speed_5000     = 5000,
 532         i40e_bus_speed_8000     = 8000,
 533         i40e_bus_speed_reserved
 534 };
 535
 536 /* PCI bus widths */
 537 enum i40e_bus_width {
 538         i40e_bus_width_unknown  = 0,
 539         i40e_bus_width_pcie_x1  = 1,
 540         i40e_bus_width_pcie_x2  = 2,
 541         i40e_bus_width_pcie_x4  = 4,
 542         i40e_bus_width_pcie_x8  = 8,
 543         i40e_bus_width_32       = 32,
 544         i40e_bus_width_64       = 64,
 545         i40e_bus_width_reserved
 546 };
 547
 548 /* Bus parameters */
 549 struct i40e_bus_info {
 550         enum i40e_bus_speed speed;
 551         enum i40e_bus_width width;
 552         enum i40e_bus_type type;
 553
 554         u16 func;
 555         u16 device;
 556         u16 lan_id;
 557 };
 558
 559 /* Flow control (FC) parameters */
 560 struct i40e_fc_info {
 561         enum i40e_fc_mode current_mode; /* FC mode in effect */
 562         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 563 };
 564
 565 #define I40E_MAX_TRAFFIC_CLASS          8
 566 #define I40E_MAX_USER_PRIORITY          8
 567 #define I40E_DCBX_MAX_APPS              32
 568 #define I40E_LLDPDU_SIZE                1500
 569 #define I40E_TLV_STATUS_OPER            0x1
 570 #define I40E_TLV_STATUS_SYNC            0x2
 571 #define I40E_TLV_STATUS_ERR             0x4
 572 #define I40E_CEE_OPER_MAX_APPS          3
 573 #define I40E_APP_PROTOID_FCOE           0x8906
 574 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 575 #define I40E_APP_PROTOID_FIP            0x8914
 576 #define I40E_APP_SEL_ETHTYPE            0x1
 577 #define I40E_APP_SEL_TCPIP              0x2
 578 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 579 #define I40E_CEE_APP_SEL_TCPIP          0x1
 580
 581 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 582 struct i40e_dcb_ets_config {
 583         u8 willing;
 584         u8 cbs;
 585         u8 maxtcs;
 586         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 587         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 588         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 589 };
 590
 591 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 592 struct i40e_dcb_pfc_config {
 593         u8 willing;
 594         u8 mbc;
 595         u8 pfccap;
 596         u8 pfcenable;
 597 };
 598
 599 /* CEE or IEEE 802.1Qaz Application Priority data */
 600 struct i40e_dcb_app_priority_table {
 601         u8  priority;
 602         u8  selector;
 603         u16 protocolid;
 604 };
 605
 606 struct i40e_dcbx_config {
 607         u8  dcbx_mode;
 608 #define I40E_DCBX_MODE_CEE      0x1
 609 #define I40E_DCBX_MODE_IEEE     0x2
 610         u8  app_mode;
 611 #define I40E_DCBX_APPS_NON_WILLING      0x1
 612         u32 numapps;
 613         u32 tlv_status; /* CEE mode TLV status */
 614         struct i40e_dcb_ets_config etscfg;
 615         struct i40e_dcb_ets_config etsrec;
 616         struct i40e_dcb_pfc_config pfc;
 617         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 618 };
 619
 620 /* Port hardware description */
 621 struct i40e_hw {
 622         u8 *hw_addr;
 623         void *back;
 624
 625         /* subsystem structs */
 626         struct i40e_phy_info phy;
 627         struct i40e_mac_info mac;
 628         struct i40e_bus_info bus;
 629         struct i40e_nvm_info nvm;
 630         struct i40e_fc_info fc;
 631
 632         /* pci info */
 633         u16 device_id;
 634         u16 vendor_id;
 635         u16 subsystem_device_id;
 636         u16 subsystem_vendor_id;
 637         u8 revision_id;
 638         u8 port;
 639         bool adapter_stopped;
 640
 641         /* capabilities for entire device and PCI func */
 642         struct i40e_hw_capabilities dev_caps;
 643         struct i40e_hw_capabilities func_caps;
 644
 645         /* Flow Director shared filter space */
 646         u16 fdir_shared_filter_count;
 647
 648         /* device profile info */
 649         u8  pf_id;
 650         u16 main_vsi_seid;
 651
 652         /* for multi-function MACs */
 653         u16 partition_id;
 654         u16 num_partitions;
 655         u16 num_ports;
 656
 657         /* Closest numa node to the device */
 658         u16 numa_node;
 659
 660         /* Admin Queue info */
 661         struct i40e_adminq_info aq;
 662
 663         /* state of nvm update process */
 664         enum i40e_nvmupd_state nvmupd_state;
 665         struct i40e_aq_desc nvm_wb_desc;
 666         struct i40e_virt_mem nvm_buff;
 667         bool nvm_release_on_done;
 668         u16 nvm_wait_opcode;
 669
 670         /* HMC info */
 671         struct i40e_hmc_info hmc; /* HMC info struct */
 672
 673         /* LLDP/DCBX Status */
 674         u16 dcbx_status;
 675
 676         /* DCBX info */
 677         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 678         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 679         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 680
 681 #ifdef X722_SUPPORT
 682         /* WoL and proxy support */
 683         u16 num_wol_proxy_filters;
 684         u16 wol_proxy_vsi_seid;
 685
 686 #endif
 687 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 688         u64 flags;
 689
 690         /* debug mask */
 691         u32 debug_mask;
 692 #ifndef I40E_NDIS_SUPPORT
 693         char err_str[16];
 694 #endif /* I40E_NDIS_SUPPORT */
 695 };
 696
 697 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 698 {
 699 #ifdef X722_SUPPORT
 700         return (hw->mac.type == I40E_MAC_VF ||
 701                 hw->mac.type == I40E_MAC_X722_VF);
 702 #else
 703         return hw->mac.type == I40E_MAC_VF;
 704 #endif
 705 }
 706
 707 struct i40e_driver_version {
 708         u8 major_version;
 709         u8 minor_version;
 710         u8 build_version;
 711         u8 subbuild_version;
 712         u8 driver_string[32];
 713 };
 714
 715 /* RX Descriptors */
 716 union i40e_16byte_rx_desc {
 717         struct {
 718                 __le64 pkt_addr; /* Packet buffer address */
 719                 __le64 hdr_addr; /* Header buffer address */
 720         } read;
 721         struct {
 722                 struct {
 723                         struct {
 724                                 union {
 725                                         __le16 mirroring_status;
 726                                         __le16 fcoe_ctx_id;
 727                                 } mirr_fcoe;
 728                                 __le16 l2tag1;
 729                         } lo_dword;
 730                         union {
 731                                 __le32 rss; /* RSS Hash */
 732                                 __le32 fd_id; /* Flow director filter id */
 733                                 __le32 fcoe_param; /* FCoE DDP Context id */
 734                         } hi_dword;
 735                 } qword0;
 736                 struct {
 737                         /* ext status/error/pktype/length */
 738                         __le64 status_error_len;
 739                 } qword1;
 740         } wb;  /* writeback */
 741 };
 742
 743 union i40e_32byte_rx_desc {
 744         struct {
 745                 __le64  pkt_addr; /* Packet buffer address */
 746                 __le64  hdr_addr; /* Header buffer address */
 747                         /* bit 0 of hdr_buffer_addr is DD bit */
 748                 __le64  rsvd1;
 749                 __le64  rsvd2;
 750         } read;
 751         struct {
 752                 struct {
 753                         struct {
 754                                 union {
 755                                         __le16 mirroring_status;
 756                                         __le16 fcoe_ctx_id;
 757                                 } mirr_fcoe;
 758                                 __le16 l2tag1;
 759                         } lo_dword;
 760                         union {
 761                                 __le32 rss; /* RSS Hash */
 762                                 __le32 fcoe_param; /* FCoE DDP Context id */
 763                                 /* Flow director filter id in case of
 764                                  * Programming status desc WB
 765                                  */
 766                                 __le32 fd_id;
 767                         } hi_dword;
 768                 } qword0;
 769                 struct {
 770                         /* status/error/pktype/length */
 771                         __le64 status_error_len;
 772                 } qword1;
 773                 struct {
 774                         __le16 ext_status; /* extended status */
 775                         __le16 rsvd;
 776                         __le16 l2tag2_1;
 777                         __le16 l2tag2_2;
 778                 } qword2;
 779                 struct {
 780                         union {
 781                                 __le32 flex_bytes_lo;
 782                                 __le32 pe_status;
 783                         } lo_dword;
 784                         union {
 785                                 __le32 flex_bytes_hi;
 786                                 __le32 fd_id;
 787                         } hi_dword;
 788                 } qword3;
 789         } wb;  /* writeback */
 790 };
 791
 792 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 793 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 794                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 795 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 796 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 797                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 798
 799 enum i40e_rx_desc_status_bits {
 800         /* Note: These are predefined bit offsets */
 801         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 802         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 803         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 804         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 805         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 806         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 807         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 808 #ifdef X722_SUPPORT
 809         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 810 #else
 811         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 812 #endif
 813
 814         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 815         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 816         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 817         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 818         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 819         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 820 #ifdef X722_SUPPORT
 821         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 822 #else
 823         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 824 #endif
 825         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 826 };
 827
 828 #define I40E_RXD_QW1_STATUS_SHIFT       0
 829 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 830                                          I40E_RXD_QW1_STATUS_SHIFT)
 831
 832 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 833 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 834                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 835
 836 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 837 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 838
 839 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 840 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 841                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 842
 843 enum i40e_rx_desc_fltstat_values {
 844         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 845         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 846         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 847         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 848 };
 849
 850 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 851 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 852 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 853 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 854
 855 #define I40E_RXD_QW1_ERROR_SHIFT        19
 856 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 857
 858 enum i40e_rx_desc_error_bits {
 859         /* Note: These are predefined bit offsets */
 860         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 861         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 862         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 863         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 864         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 865         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 866         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 867         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 868         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 869 };
 870
 871 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 872         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 873         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 874         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 875         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 876         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 877 };
 878
 879 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 880 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 881
 882 /* Packet type non-ip values */
 883 enum i40e_rx_l2_ptype {
 884         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 885         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 886         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 887         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 888         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 889         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 890         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 891         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 892         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 893         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 894         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 895         I40E_RX_PTYPE_L2_ARP                            = 11,
 896         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 897         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 898         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 899         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 900         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 901         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 902         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 903         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 904         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 905         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 906         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 907         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 908         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 909         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 910 };
 911
 912 struct i40e_rx_ptype_decoded {
 913         u32 ptype:8;
 914         u32 known:1;
 915         u32 outer_ip:1;
 916         u32 outer_ip_ver:1;
 917         u32 outer_frag:1;
 918         u32 tunnel_type:3;
 919         u32 tunnel_end_prot:2;
 920         u32 tunnel_end_frag:1;
 921         u32 inner_prot:4;
 922         u32 payload_layer:3;
 923 };
 924
 925 enum i40e_rx_ptype_outer_ip {
 926         I40E_RX_PTYPE_OUTER_L2  = 0,
 927         I40E_RX_PTYPE_OUTER_IP  = 1
 928 };
 929
 930 enum i40e_rx_ptype_outer_ip_ver {
 931         I40E_RX_PTYPE_OUTER_NONE        = 0,
 932         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 933         I40E_RX_PTYPE_OUTER_IPV6        = 1
 934 };
 935
 936 enum i40e_rx_ptype_outer_fragmented {
 937         I40E_RX_PTYPE_NOT_FRAG  = 0,
 938         I40E_RX_PTYPE_FRAG      = 1
 939 };
 940
 941 enum i40e_rx_ptype_tunnel_type {
 942         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 943         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 944         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 945         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 946         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 947 };
 948
 949 enum i40e_rx_ptype_tunnel_end_prot {
 950         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 951         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 952         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 953 };
 954
 955 enum i40e_rx_ptype_inner_prot {
 956         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 957         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 958         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 959         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 960         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 961         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 962 };
 963
 964 enum i40e_rx_ptype_payload_layer {
 965         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 966         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 967         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 968         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 969 };
 970
 971 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 972 #define I40E_RX_PTYPE_SHIFT             56
 973
 974 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 975 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 976                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 977
 978 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 979 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 980                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 981
 982 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 983 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 984
 985 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 986 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 987
 988 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 989 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 990                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 991
 992 enum i40e_rx_desc_ext_status_bits {
 993         /* Note: These are predefined bit offsets */
 994         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 995         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 996         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 997         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 998         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 999         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1000         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1001 };
1002
1003 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
1004 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
1005
1006 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
1007 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
1008
1009 enum i40e_rx_desc_pe_status_bits {
1010         /* Note: These are predefined bit offsets */
1011         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1012         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1013         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1014         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1015         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1016         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1017         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1018         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1019         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1020 };
1021
1022 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1023 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1024
1025 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1026 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1027                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1028
1029 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1030 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1031                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1032
1033 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1034 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1035                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1036
1037 enum i40e_rx_prog_status_desc_status_bits {
1038         /* Note: These are predefined bit offsets */
1039         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1040         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1041 };
1042
1043 enum i40e_rx_prog_status_desc_prog_id_masks {
1044         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1045         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1046         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1047 };
1048
1049 enum i40e_rx_prog_status_desc_error_bits {
1050         /* Note: These are predefined bit offsets */
1051         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1052         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1053         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1054         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1055 };
1056
1057 #define I40E_TWO_BIT_MASK       0x3
1058 #define I40E_THREE_BIT_MASK     0x7
1059 #define I40E_FOUR_BIT_MASK      0xF
1060 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1061
1062 /* TX Descriptor */
1063 struct i40e_tx_desc {
1064         __le64 buffer_addr; /* Address of descriptor's data buf */
1065         __le64 cmd_type_offset_bsz;
1066 };
1067
1068 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1069 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1070
1071 enum i40e_tx_desc_dtype_value {
1072         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1073         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1074         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1075         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1076         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1077         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1078         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1079         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1080         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1081         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1082 };
1083
1084 #define I40E_TXD_QW1_CMD_SHIFT  4
1085 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1086
1087 enum i40e_tx_desc_cmd_bits {
1088         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1089         I40E_TX_DESC_CMD_RS                     = 0x0002,
1090         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1091         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1092         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1093         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1094         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1095         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1096         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1097         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1098         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1099         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1100         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1101         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1102         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1103         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1104         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1105         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1106 };
1107
1108 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1109 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1110                                          I40E_TXD_QW1_OFFSET_SHIFT)
1111
1112 enum i40e_tx_desc_length_fields {
1113         /* Note: These are predefined bit offsets */
1114         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1115         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1116         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1117 };
1118
1119 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1120 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1121 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1122 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1123
1124 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1125 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1126                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1127
1128 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1129 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1130
1131 /* Context descriptors */
1132 struct i40e_tx_context_desc {
1133         __le32 tunneling_params;
1134         __le16 l2tag2;
1135         __le16 rsvd;
1136         __le64 type_cmd_tso_mss;
1137 };
1138
1139 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1140 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1141
1142 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1143 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1144
1145 enum i40e_tx_ctx_desc_cmd_bits {
1146         I40E_TX_CTX_DESC_TSO            = 0x01,
1147         I40E_TX_CTX_DESC_TSYN           = 0x02,
1148         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1149         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1150         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1151         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1152         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1153         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1154         I40E_TX_CTX_DESC_SWPE           = 0x40
1155 };
1156
1157 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1158 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1159                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1160
1161 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1162 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1163                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1164
1165 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1166 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1167
1168 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1169 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1170                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1171
1172 enum i40e_tx_ctx_desc_eipt_offload {
1173         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1174         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1175         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1176         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1177 };
1178
1179 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1180 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1181                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1182
1183 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1184 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1185
1186 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1187 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1188
1189 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1190 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1191
1192 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1193
1194 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1195 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1196                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1197
1198 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1199 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1200                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1201
1202 #ifdef X722_SUPPORT
1203 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1204 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1205 #endif
1206 struct i40e_nop_desc {
1207         __le64 rsvd;
1208         __le64 dtype_cmd;
1209 };
1210
1211 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1212 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1213
1214 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1215 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1216
1217 enum i40e_tx_nop_desc_cmd_bits {
1218         /* Note: These are predefined bit offsets */
1219         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1220         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1221         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1222 };
1223
1224 struct i40e_filter_program_desc {
1225         __le32 qindex_flex_ptype_vsi;
1226         __le32 rsvd;
1227         __le32 dtype_cmd_cntindex;
1228         __le32 fd_id;
1229 };
1230 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1231 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1232                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1233 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1234 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1235                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1236 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1237 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1238                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1239
1240 /* Packet Classifier Types for filters */
1241 enum i40e_filter_pctype {
1242 #ifdef X722_SUPPORT
1243         /* Note: Values 0-28 are reserved for future use.
1244          * Value 29, 30, 32 are not supported on XL710 and X710.
1245          */
1246         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1247         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1248 #else
1249         /* Note: Values 0-30 are reserved for future use */
1250 #endif
1251         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1252 #ifdef X722_SUPPORT
1253         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1254 #else
1255         /* Note: Value 32 is reserved for future use */
1256 #endif
1257         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1258         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1259         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1260         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1261 #ifdef X722_SUPPORT
1262         /* Note: Values 37-38 are reserved for future use.
1263          * Value 39, 40, 42 are not supported on XL710 and X710.
1264          */
1265         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1266         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1267 #else
1268         /* Note: Values 37-40 are reserved for future use */
1269 #endif
1270         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1271 #ifdef X722_SUPPORT
1272         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1273 #endif
1274         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1275         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1276         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1277         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1278         /* Note: Value 47 is reserved for future use */
1279         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1280         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1281         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1282         /* Note: Values 51-62 are reserved for future use */
1283         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1284 };
1285
1286 enum i40e_filter_program_desc_dest {
1287         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1288         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1289         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1290 };
1291
1292 enum i40e_filter_program_desc_fd_status {
1293         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1294         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1295         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1296         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1297 };
1298
1299 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1300 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1301                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1302
1303 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1304 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1305
1306 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1307 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1308                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1309
1310 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1311 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1312
1313 enum i40e_filter_program_desc_pcmd {
1314         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1315         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1316 };
1317
1318 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1319 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1320
1321 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1322 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1323
1324 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1325                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1326 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1327                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1328 #ifdef X722_SUPPORT
1329
1330 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1331                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1332 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1333 #endif
1334
1335 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1336 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1337                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1338
1339 enum i40e_filter_type {
1340         I40E_FLOW_DIRECTOR_FLTR = 0,
1341         I40E_PE_QUAD_HASH_FLTR = 1,
1342         I40E_ETHERTYPE_FLTR,
1343         I40E_FCOE_CTX_FLTR,
1344         I40E_MAC_VLAN_FLTR,
1345         I40E_HASH_FLTR
1346 };
1347
1348 struct i40e_vsi_context {
1349         u16 seid;
1350         u16 uplink_seid;
1351         u16 vsi_number;
1352         u16 vsis_allocated;
1353         u16 vsis_unallocated;
1354         u16 flags;
1355         u8 pf_num;
1356         u8 vf_num;
1357         u8 connection_type;
1358         struct i40e_aqc_vsi_properties_data info;
1359 };
1360
1361 struct i40e_veb_context {
1362         u16 seid;
1363         u16 uplink_seid;
1364         u16 veb_number;
1365         u16 vebs_allocated;
1366         u16 vebs_unallocated;
1367         u16 flags;
1368         struct i40e_aqc_get_veb_parameters_completion info;
1369 };
1370
1371 /* Statistics collected by each port, VSI, VEB, and S-channel */
1372 struct i40e_eth_stats {
1373         u64 rx_bytes;                   /* gorc */
1374         u64 rx_unicast;                 /* uprc */
1375         u64 rx_multicast;               /* mprc */
1376         u64 rx_broadcast;               /* bprc */
1377         u64 rx_discards;                /* rdpc */
1378         u64 rx_unknown_protocol;        /* rupp */
1379         u64 tx_bytes;                   /* gotc */
1380         u64 tx_unicast;                 /* uptc */
1381         u64 tx_multicast;               /* mptc */
1382         u64 tx_broadcast;               /* bptc */
1383         u64 tx_discards;                /* tdpc */
1384         u64 tx_errors;                  /* tepc */
1385 };
1386
1387 /* Statistics collected per VEB per TC */
1388 struct i40e_veb_tc_stats {
1389         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1390         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1391         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1392         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1393 };
1394
1395 /* Statistics collected per function for FCoE */
1396 struct i40e_fcoe_stats {
1397         u64 rx_fcoe_packets;            /* fcoeprc */
1398         u64 rx_fcoe_dwords;             /* focedwrc */
1399         u64 rx_fcoe_dropped;            /* fcoerpdc */
1400         u64 tx_fcoe_packets;            /* fcoeptc */
1401         u64 tx_fcoe_dwords;             /* focedwtc */
1402         u64 fcoe_bad_fccrc;             /* fcoecrc */
1403         u64 fcoe_last_error;            /* fcoelast */
1404         u64 fcoe_ddp_count;             /* fcoeddpc */
1405 };
1406
1407 /* offset to per function FCoE statistics block */
1408 #define I40E_FCOE_VF_STAT_OFFSET        0
1409 #define I40E_FCOE_PF_STAT_OFFSET        128
1410 #define I40E_FCOE_STAT_MAX              (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1411
1412 /* Statistics collected by the MAC */
1413 struct i40e_hw_port_stats {
1414         /* eth stats collected by the port */
1415         struct i40e_eth_stats eth;
1416
1417         /* additional port specific stats */
1418         u64 tx_dropped_link_down;       /* tdold */
1419         u64 crc_errors;                 /* crcerrs */
1420         u64 illegal_bytes;              /* illerrc */
1421         u64 error_bytes;                /* errbc */
1422         u64 mac_local_faults;           /* mlfc */
1423         u64 mac_remote_faults;          /* mrfc */
1424         u64 rx_length_errors;           /* rlec */
1425         u64 link_xon_rx;                /* lxonrxc */
1426         u64 link_xoff_rx;               /* lxoffrxc */
1427         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1428         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1429         u64 link_xon_tx;                /* lxontxc */
1430         u64 link_xoff_tx;               /* lxofftxc */
1431         u64 priority_xon_tx[8];         /* pxontxc[8] */
1432         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1433         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1434         u64 rx_size_64;                 /* prc64 */
1435         u64 rx_size_127;                /* prc127 */
1436         u64 rx_size_255;                /* prc255 */
1437         u64 rx_size_511;                /* prc511 */
1438         u64 rx_size_1023;               /* prc1023 */
1439         u64 rx_size_1522;               /* prc1522 */
1440         u64 rx_size_big;                /* prc9522 */
1441         u64 rx_undersize;               /* ruc */
1442         u64 rx_fragments;               /* rfc */
1443         u64 rx_oversize;                /* roc */
1444         u64 rx_jabber;                  /* rjc */
1445         u64 tx_size_64;                 /* ptc64 */
1446         u64 tx_size_127;                /* ptc127 */
1447         u64 tx_size_255;                /* ptc255 */
1448         u64 tx_size_511;                /* ptc511 */
1449         u64 tx_size_1023;               /* ptc1023 */
1450         u64 tx_size_1522;               /* ptc1522 */
1451         u64 tx_size_big;                /* ptc9522 */
1452         u64 mac_short_packet_dropped;   /* mspdc */
1453         u64 checksum_error;             /* xec */
1454         /* flow director stats */
1455         u64 fd_atr_match;
1456         u64 fd_sb_match;
1457         u64 fd_atr_tunnel_match;
1458         u32 fd_atr_status;
1459         u32 fd_sb_status;
1460         /* EEE LPI */
1461         u32 tx_lpi_status;
1462         u32 rx_lpi_status;
1463         u64 tx_lpi_count;               /* etlpic */
1464         u64 rx_lpi_count;               /* erlpic */
1465 };
1466
1467 /* Checksum and Shadow RAM pointers */
1468 #define I40E_SR_NVM_CONTROL_WORD                0x00
1469 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1470 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1471 #define I40E_SR_OPTION_ROM_PTR                  0x05
1472 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1473 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1474 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1475 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1476 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1477 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1478 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1479 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1480 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1481 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1482 #define I40E_SR_PBA_FLAGS                       0x15
1483 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1484 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1485 #define I40E_NVM_OEM_VER_OFF                    0x83
1486 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1487 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1488 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1489 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1490 #define I40E_SR_NVM_MAP_VERSION                 0x29
1491 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1492 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1493 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1494 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1495 #define I40E_SR_VPD_PTR                         0x2F
1496 #define I40E_SR_PXE_SETUP_PTR                   0x30
1497 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1498 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1499 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1500 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1501 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1502 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1503 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1504 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1505 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1506 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1507 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1508 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1509 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1510 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1511 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1512 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1513 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1514 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1515
1516 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1517 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1518 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1519 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1520 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1521
1522 /* Shadow RAM related */
1523 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1524 #define I40E_SR_BUF_ALIGNMENT           4096
1525 #define I40E_SR_WORDS_IN_1KB            512
1526 /* Checksum should be calculated such that after adding all the words,
1527  * including the checksum word itself, the sum should be 0xBABA.
1528  */
1529 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1530
1531 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1532
1533 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1534
1535 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1536         I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1537         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1538         I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1539         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1540         I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1541         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1542         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1543         I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1544         I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1545         I40E_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1546         I40E_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1547         I40E_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1548         I40E_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1549 };
1550
1551 /* FCoE DIF/DIX Context descriptor */
1552 struct i40e_fcoe_difdix_context_desc {
1553         __le64 flags_buff0_buff1_ref;
1554         __le64 difapp_msk_bias;
1555 };
1556
1557 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1558 #define I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1559                                         I40E_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1560
1561 enum i40e_fcoe_difdix_ctx_desc_flags_bits {
1562         /* 2 BITS */
1563         I40E_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1564         /* 1 BIT  */
1565         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1566         /* 1 BIT  */
1567         I40E_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1568         /* 2 BITS */
1569         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1570         /* 2 BITS */
1571         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1572         /* 2 BITS */
1573         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1574         /* 2 BITS */
1575         I40E_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1576         /* 2 BITS */
1577         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1578         /* 2 BITS */
1579         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1580         /* 2 BITS */
1581         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1582         /* 2 BITS */
1583         I40E_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1584         /* 1 BIT  */
1585         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1586         /* 1 BIT  */
1587         I40E_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1588         /* 2 BITS */
1589         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1590         /* 2 BITS */
1591         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1592         /* 2 BITS */
1593         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1594         /* 2 BITS */
1595         I40E_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1596         /* 1 BIT  */
1597         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1598         /* 1 BIT  */
1599         I40E_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1600         /* 1 BIT */
1601         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1602         /* 1 BIT */
1603         I40E_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1604 };
1605
1606 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1607 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1608                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1609
1610 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1611 #define I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1612                                         I40E_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1613
1614 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1615 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1616                                         I40E_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1617
1618 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1619 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1620                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1621
1622 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1623 #define I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1624                                         I40E_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1625
1626 #define I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1627 #define I40E_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1628                                         I40E_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1629
1630 /* FCoE DIF/DIX Buffers descriptor */
1631 struct i40e_fcoe_difdix_buffers_desc {
1632         __le64 buff_addr0;
1633         __le64 buff_addr1;
1634 };
1635
1636 /* FCoE DDP Context descriptor */
1637 struct i40e_fcoe_ddp_context_desc {
1638         __le64 rsvd;
1639         __le64 type_cmd_foff_lsize;
1640 };
1641
1642 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1643 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1644                                         I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1645
1646 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1647 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1648                                          I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1649
1650 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1651         I40E_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1652         I40E_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1653         I40E_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1654         I40E_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1655         I40E_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1656         I40E_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1657 };
1658
1659 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1660 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1661                                          I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1662
1663 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1664 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1665                                         I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1666
1667 /* FCoE DDP/DWO Queue Context descriptor */
1668 struct i40e_fcoe_queue_context_desc {
1669         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1670         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1671 };
1672
1673 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1674 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1675                                         I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1676
1677 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1678 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1679                                         I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1680
1681 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1682 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1683                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1684
1685 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1686 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1687                                         I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1688
1689 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1690         I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1691         I40E_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1692 };
1693
1694 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1695 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1696                                         I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1697
1698 /* FCoE DDP/DWO Filter Context descriptor */
1699 struct i40e_fcoe_filter_context_desc {
1700         __le32 param;
1701         __le16 seqn;
1702
1703         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1704         __le16 rsvd_dmaindx;
1705
1706         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1707         __le64 flags_rsvd_lanq;
1708 };
1709
1710 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1711 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1712                                         I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1713
1714 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1715         I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1716         I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1717         I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1718         I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1719         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1720         I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1721 };
1722
1723 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1724 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1725                                         I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1726
1727 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1728 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1729                         I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1730
1731 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1732 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1733                         I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1734
1735 enum i40e_switch_element_types {
1736         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1737         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1738         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1739         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1740         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1741         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1742         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1743         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1744         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1745 };
1746
1747 /* Supported EtherType filters */
1748 enum i40e_ether_type_index {
1749         I40E_ETHER_TYPE_1588            = 0,
1750         I40E_ETHER_TYPE_FIP             = 1,
1751         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1752         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1753         I40E_ETHER_TYPE_LLDP            = 4,
1754         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1755         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1756         I40E_ETHER_TYPE_QCN_CNM         = 7,
1757         I40E_ETHER_TYPE_8021X           = 8,
1758         I40E_ETHER_TYPE_ARP             = 9,
1759         I40E_ETHER_TYPE_RSV1            = 10,
1760         I40E_ETHER_TYPE_RSV2            = 11,
1761 };
1762
1763 /* Filter context base size is 1K */
1764 #define I40E_HASH_FILTER_BASE_SIZE      1024
1765 /* Supported Hash filter values */
1766 enum i40e_hash_filter_size {
1767         I40E_HASH_FILTER_SIZE_1K        = 0,
1768         I40E_HASH_FILTER_SIZE_2K        = 1,
1769         I40E_HASH_FILTER_SIZE_4K        = 2,
1770         I40E_HASH_FILTER_SIZE_8K        = 3,
1771         I40E_HASH_FILTER_SIZE_16K       = 4,
1772         I40E_HASH_FILTER_SIZE_32K       = 5,
1773         I40E_HASH_FILTER_SIZE_64K       = 6,
1774         I40E_HASH_FILTER_SIZE_128K      = 7,
1775         I40E_HASH_FILTER_SIZE_256K      = 8,
1776         I40E_HASH_FILTER_SIZE_512K      = 9,
1777         I40E_HASH_FILTER_SIZE_1M        = 10,
1778 };
1779
1780 /* DMA context base size is 0.5K */
1781 #define I40E_DMA_CNTX_BASE_SIZE         512
1782 /* Supported DMA context values */
1783 enum i40e_dma_cntx_size {
1784         I40E_DMA_CNTX_SIZE_512          = 0,
1785         I40E_DMA_CNTX_SIZE_1K           = 1,
1786         I40E_DMA_CNTX_SIZE_2K           = 2,
1787         I40E_DMA_CNTX_SIZE_4K           = 3,
1788         I40E_DMA_CNTX_SIZE_8K           = 4,
1789         I40E_DMA_CNTX_SIZE_16K          = 5,
1790         I40E_DMA_CNTX_SIZE_32K          = 6,
1791         I40E_DMA_CNTX_SIZE_64K          = 7,
1792         I40E_DMA_CNTX_SIZE_128K         = 8,
1793         I40E_DMA_CNTX_SIZE_256K         = 9,
1794 };
1795
1796 /* Supported Hash look up table (LUT) sizes */
1797 enum i40e_hash_lut_size {
1798         I40E_HASH_LUT_SIZE_128          = 0,
1799         I40E_HASH_LUT_SIZE_512          = 1,
1800 };
1801
1802 /* Structure to hold a per PF filter control settings */
1803 struct i40e_filter_control_settings {
1804         /* number of PE Quad Hash filter buckets */
1805         enum i40e_hash_filter_size pe_filt_num;
1806         /* number of PE Quad Hash contexts */
1807         enum i40e_dma_cntx_size pe_cntx_num;
1808         /* number of FCoE filter buckets */
1809         enum i40e_hash_filter_size fcoe_filt_num;
1810         /* number of FCoE DDP contexts */
1811         enum i40e_dma_cntx_size fcoe_cntx_num;
1812         /* size of the Hash LUT */
1813         enum i40e_hash_lut_size hash_lut_size;
1814         /* enable FDIR filters for PF and its VFs */
1815         bool enable_fdir;
1816         /* enable Ethertype filters for PF and its VFs */
1817         bool enable_ethtype;
1818         /* enable MAC/VLAN filters for PF and its VFs */
1819         bool enable_macvlan;
1820 };
1821
1822 /* Structure to hold device level control filter counts */
1823 struct i40e_control_filter_stats {
1824         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1825         u16 etype_used;       /* Used perfect EtherType filters */
1826         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1827         u16 etype_free;       /* Un-used perfect EtherType filters */
1828 };
1829
1830 enum i40e_reset_type {
1831         I40E_RESET_POR          = 0,
1832         I40E_RESET_CORER        = 1,
1833         I40E_RESET_GLOBR        = 2,
1834         I40E_RESET_EMPR         = 3,
1835 };
1836
1837 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1838 #define I40E_NVM_LLDP_CFG_PTR           0xD
1839 struct i40e_lldp_variables {
1840         u16 length;
1841         u16 adminstatus;
1842         u16 msgfasttx;
1843         u16 msgtxinterval;
1844         u16 txparams;
1845         u16 timers;
1846         u16 crc8;
1847 };
1848
1849 /* Offsets into Alternate Ram */
1850 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1851 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1852 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1853 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1854 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1855 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1856
1857 /* Alternate Ram Bandwidth Masks */
1858 #define I40E_ALT_BW_VALUE_MASK          0xFF
1859 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1860 #define I40E_ALT_BW_VALID_MASK          0x80000000
1861
1862 /* RSS Hash Table Size */
1863 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1864
1865 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1866 #define I40E_L3_SRC_SHIFT               47
1867 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1868 #define I40E_L3_V6_SRC_SHIFT            43
1869 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1870 #define I40E_L3_DST_SHIFT               35
1871 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1872 #define I40E_L3_V6_DST_SHIFT            35
1873 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1874 #define I40E_L4_SRC_SHIFT               34
1875 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1876 #define I40E_L4_DST_SHIFT               33
1877 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1878 #define I40E_VERIFY_TAG_SHIFT           31
1879 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1880
1881 #define I40E_FLEX_50_SHIFT              13
1882 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1883 #define I40E_FLEX_51_SHIFT              12
1884 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1885 #define I40E_FLEX_52_SHIFT              11
1886 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1887 #define I40E_FLEX_53_SHIFT              10
1888 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1889 #define I40E_FLEX_54_SHIFT              9
1890 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1891 #define I40E_FLEX_55_SHIFT              8
1892 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1893 #define I40E_FLEX_56_SHIFT              7
1894 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1895 #define I40E_FLEX_57_SHIFT              6
1896 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1897 #endif /* _I40E_TYPE_H_ */