drivers/net/i40e/base/i40e_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _I40E_TYPE_H_
  35 #define _I40E_TYPE_H_
  36
  37 #include "i40e_status.h"
  38 #include "i40e_osdep.h"
  39 #include "i40e_register.h"
  40 #include "i40e_adminq.h"
  41 #include "i40e_hmc.h"
  42 #include "i40e_lan_hmc.h"
  43 #include "i40e_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef I40E_MASK
  62 /* I40E_MASK is a macro used on 32 bit registers */
  63 #define I40E_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define I40E_MAX_PF                     16
  67 #define I40E_MAX_PF_VSI                 64
  68 #define I40E_MAX_PF_QP                  128
  69 #define I40E_MAX_VSI_QP                 16
  70 #define I40E_MAX_VF_VSI                 3
  71 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  72 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define I40E_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define I40E_MAX_NVM_TIMEOUT            18000
  79
  80 /* Check whether address is multicast. */
  81 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  82
  83 /* Check whether an address is broadcast. */
  84 #define I40E_IS_BROADCAST(address)      \
  85         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  86         (((u8 *)(address))[1] == ((u8)0xff)))
  87
  88 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  89 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  90
  91 /* forward declaration */
  92 struct i40e_hw;
  93 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  94
  95 #define I40E_ETH_LENGTH_OF_ADDRESS      6
  96 /* Data type manipulation macros. */
  97 #define I40E_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  98 #define I40E_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  99
 100 #define I40E_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 101 #define I40E_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 102
 103 #define I40E_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 104 #define I40E_LO_BYTE(x)         ((u8)((x) & 0xFF))
 105
 106 /* Number of Transmit Descriptors must be a multiple of 8. */
 107 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8
 108 /* Number of Receive Descriptors must be a multiple of 32 if
 109  * the number of descriptors is greater than 32.
 110  */
 111 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32
 112
 113 #define I40E_DESC_UNUSED(R)     \
 114         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 115         (R)->next_to_clean - (R)->next_to_use - 1)
 116
 117 /* bitfields for Tx queue mapping in QTX_CTL */
 118 #define I40E_QTX_CTL_VF_QUEUE   0x0
 119 #define I40E_QTX_CTL_VM_QUEUE   0x1
 120 #define I40E_QTX_CTL_PF_QUEUE   0x2
 121
 122 /* debug masks - set these bits in hw->debug_mask to control output */
 123 enum i40e_debug_mask {
 124         I40E_DEBUG_INIT                 = 0x00000001,
 125         I40E_DEBUG_RELEASE              = 0x00000002,
 126
 127         I40E_DEBUG_LINK                 = 0x00000010,
 128         I40E_DEBUG_PHY                  = 0x00000020,
 129         I40E_DEBUG_HMC                  = 0x00000040,
 130         I40E_DEBUG_NVM                  = 0x00000080,
 131         I40E_DEBUG_LAN                  = 0x00000100,
 132         I40E_DEBUG_FLOW                 = 0x00000200,
 133         I40E_DEBUG_DCB                  = 0x00000400,
 134         I40E_DEBUG_DIAG                 = 0x00000800,
 135         I40E_DEBUG_FD                   = 0x00001000,
 136
 137         I40E_DEBUG_AQ_MESSAGE           = 0x01000000,
 138         I40E_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 139         I40E_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 140         I40E_DEBUG_AQ_COMMAND           = 0x06000000,
 141         I40E_DEBUG_AQ                   = 0x0F000000,
 142
 143         I40E_DEBUG_USER                 = 0xF0000000,
 144
 145         I40E_DEBUG_ALL                  = 0xFFFFFFFF
 146 };
 147
 148 /* PCI Bus Info */
 149 #define I40E_PCI_LINK_STATUS            0xB2
 150 #define I40E_PCI_LINK_WIDTH             0x3F0
 151 #define I40E_PCI_LINK_WIDTH_1           0x10
 152 #define I40E_PCI_LINK_WIDTH_2           0x20
 153 #define I40E_PCI_LINK_WIDTH_4           0x40
 154 #define I40E_PCI_LINK_WIDTH_8           0x80
 155 #define I40E_PCI_LINK_SPEED             0xF
 156 #define I40E_PCI_LINK_SPEED_2500        0x1
 157 #define I40E_PCI_LINK_SPEED_5000        0x2
 158 #define I40E_PCI_LINK_SPEED_8000        0x3
 159
 160 #define I40E_MDIO_STCODE                0
 161 #define I40E_MDIO_OPCODE_ADDRESS        0
 162 #define I40E_MDIO_OPCODE_WRITE          I40E_MASK(1, \
 163                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 164 #define I40E_MDIO_OPCODE_READ_INC_ADDR  I40E_MASK(2, \
 165                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 166 #define I40E_MDIO_OPCODE_READ           I40E_MASK(3, \
 167                                                   I40E_GLGEN_MSCA_OPCODE_SHIFT)
 168
 169 #define I40E_PHY_COM_REG_PAGE                   0x1E
 170 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
 171 #define I40E_PHY_LED_MANUAL_ON                  0x100
 172 #define I40E_PHY_LED_PROV_REG_1                 0xC430
 173 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
 174 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
 175
 176 /* Memory types */
 177 enum i40e_memset_type {
 178         I40E_NONDMA_MEM = 0,
 179         I40E_DMA_MEM
 180 };
 181
 182 /* Memcpy types */
 183 enum i40e_memcpy_type {
 184         I40E_NONDMA_TO_NONDMA = 0,
 185         I40E_NONDMA_TO_DMA,
 186         I40E_DMA_TO_DMA,
 187         I40E_DMA_TO_NONDMA
 188 };
 189
 190 #ifdef X722_SUPPORT
 191 #define I40E_FW_API_VERSION_MINOR_X722  0x0004
 192 #endif
 193 #define I40E_FW_API_VERSION_MINOR_X710  0x0005
 194
 195
 196 /* These are structs for managing the hardware information and the operations.
 197  * The structures of function pointers are filled out at init time when we
 198  * know for sure exactly which hardware we're working with.  This gives us the
 199  * flexibility of using the same main driver code but adapting to slightly
 200  * different hardware needs as new parts are developed.  For this architecture,
 201  * the Firmware and AdminQ are intended to insulate the driver from most of the
 202  * future changes, but these structures will also do part of the job.
 203  */
 204 enum i40e_mac_type {
 205         I40E_MAC_UNKNOWN = 0,
 206         I40E_MAC_X710,
 207         I40E_MAC_XL710,
 208         I40E_MAC_VF,
 209 #ifdef X722_SUPPORT
 210         I40E_MAC_X722,
 211         I40E_MAC_X722_VF,
 212 #endif
 213         I40E_MAC_GENERIC,
 214 };
 215
 216 enum i40e_media_type {
 217         I40E_MEDIA_TYPE_UNKNOWN = 0,
 218         I40E_MEDIA_TYPE_FIBER,
 219         I40E_MEDIA_TYPE_BASET,
 220         I40E_MEDIA_TYPE_BACKPLANE,
 221         I40E_MEDIA_TYPE_CX4,
 222         I40E_MEDIA_TYPE_DA,
 223         I40E_MEDIA_TYPE_VIRTUAL
 224 };
 225
 226 enum i40e_fc_mode {
 227         I40E_FC_NONE = 0,
 228         I40E_FC_RX_PAUSE,
 229         I40E_FC_TX_PAUSE,
 230         I40E_FC_FULL,
 231         I40E_FC_PFC,
 232         I40E_FC_DEFAULT
 233 };
 234
 235 enum i40e_set_fc_aq_failures {
 236         I40E_SET_FC_AQ_FAIL_NONE = 0,
 237         I40E_SET_FC_AQ_FAIL_GET = 1,
 238         I40E_SET_FC_AQ_FAIL_SET = 2,
 239         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
 240         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
 241 };
 242
 243 enum i40e_vsi_type {
 244         I40E_VSI_MAIN   = 0,
 245         I40E_VSI_VMDQ1  = 1,
 246         I40E_VSI_VMDQ2  = 2,
 247         I40E_VSI_CTRL   = 3,
 248         I40E_VSI_FCOE   = 4,
 249         I40E_VSI_MIRROR = 5,
 250         I40E_VSI_SRIOV  = 6,
 251         I40E_VSI_FDIR   = 7,
 252         I40E_VSI_TYPE_UNKNOWN
 253 };
 254
 255 enum i40e_queue_type {
 256         I40E_QUEUE_TYPE_RX = 0,
 257         I40E_QUEUE_TYPE_TX,
 258         I40E_QUEUE_TYPE_PE_CEQ,
 259         I40E_QUEUE_TYPE_UNKNOWN
 260 };
 261
 262 struct i40e_link_status {
 263         enum i40e_aq_phy_type phy_type;
 264         enum i40e_aq_link_speed link_speed;
 265         u8 link_info;
 266         u8 an_info;
 267         u8 ext_info;
 268         u8 loopback;
 269         /* is Link Status Event notification to SW enabled */
 270         bool lse_enable;
 271         u16 max_frame_size;
 272         bool crc_enable;
 273         u8 pacing;
 274         u8 requested_speeds;
 275         u8 module_type[3];
 276         /* 1st byte: module identifier */
 277 #define I40E_MODULE_TYPE_SFP            0x03
 278 #define I40E_MODULE_TYPE_QSFP           0x0D
 279         /* 2nd byte: ethernet compliance codes for 10/40G */
 280 #define I40E_MODULE_TYPE_40G_ACTIVE     0x01
 281 #define I40E_MODULE_TYPE_40G_LR4        0x02
 282 #define I40E_MODULE_TYPE_40G_SR4        0x04
 283 #define I40E_MODULE_TYPE_40G_CR4        0x08
 284 #define I40E_MODULE_TYPE_10G_BASE_SR    0x10
 285 #define I40E_MODULE_TYPE_10G_BASE_LR    0x20
 286 #define I40E_MODULE_TYPE_10G_BASE_LRM   0x40
 287 #define I40E_MODULE_TYPE_10G_BASE_ER    0x80
 288         /* 3rd byte: ethernet compliance codes for 1G */
 289 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 290 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 291 #define I40E_MODULE_TYPE_1000BASE_CX    0x04
 292 #define I40E_MODULE_TYPE_1000BASE_T     0x08
 293 };
 294
 295 enum i40e_aq_capabilities_phy_type {
 296         I40E_CAP_PHY_TYPE_SGMII                 = BIT(I40E_PHY_TYPE_SGMII),
 297         I40E_CAP_PHY_TYPE_1000BASE_KX           = BIT(I40E_PHY_TYPE_1000BASE_KX),
 298         I40E_CAP_PHY_TYPE_10GBASE_KX4           = BIT(I40E_PHY_TYPE_10GBASE_KX4),
 299         I40E_CAP_PHY_TYPE_10GBASE_KR            = BIT(I40E_PHY_TYPE_10GBASE_KR),
 300         I40E_CAP_PHY_TYPE_40GBASE_KR4           = BIT(I40E_PHY_TYPE_40GBASE_KR4),
 301         I40E_CAP_PHY_TYPE_XAUI                  = BIT(I40E_PHY_TYPE_XAUI),
 302         I40E_CAP_PHY_TYPE_XFI                   = BIT(I40E_PHY_TYPE_XFI),
 303         I40E_CAP_PHY_TYPE_SFI                   = BIT(I40E_PHY_TYPE_SFI),
 304         I40E_CAP_PHY_TYPE_XLAUI                 = BIT(I40E_PHY_TYPE_XLAUI),
 305         I40E_CAP_PHY_TYPE_XLPPI                 = BIT(I40E_PHY_TYPE_XLPPI),
 306         I40E_CAP_PHY_TYPE_40GBASE_CR4_CU        = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
 307         I40E_CAP_PHY_TYPE_10GBASE_CR1_CU        = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
 308         I40E_CAP_PHY_TYPE_10GBASE_AOC           = BIT(I40E_PHY_TYPE_10GBASE_AOC),
 309         I40E_CAP_PHY_TYPE_40GBASE_AOC           = BIT(I40E_PHY_TYPE_40GBASE_AOC),
 310         I40E_CAP_PHY_TYPE_100BASE_TX            = BIT(I40E_PHY_TYPE_100BASE_TX),
 311         I40E_CAP_PHY_TYPE_1000BASE_T            = BIT(I40E_PHY_TYPE_1000BASE_T),
 312         I40E_CAP_PHY_TYPE_10GBASE_T             = BIT(I40E_PHY_TYPE_10GBASE_T),
 313         I40E_CAP_PHY_TYPE_10GBASE_SR            = BIT(I40E_PHY_TYPE_10GBASE_SR),
 314         I40E_CAP_PHY_TYPE_10GBASE_LR            = BIT(I40E_PHY_TYPE_10GBASE_LR),
 315         I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU       = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
 316         I40E_CAP_PHY_TYPE_10GBASE_CR1           = BIT(I40E_PHY_TYPE_10GBASE_CR1),
 317         I40E_CAP_PHY_TYPE_40GBASE_CR4           = BIT(I40E_PHY_TYPE_40GBASE_CR4),
 318         I40E_CAP_PHY_TYPE_40GBASE_SR4           = BIT(I40E_PHY_TYPE_40GBASE_SR4),
 319         I40E_CAP_PHY_TYPE_40GBASE_LR4           = BIT(I40E_PHY_TYPE_40GBASE_LR4),
 320         I40E_CAP_PHY_TYPE_1000BASE_SX           = BIT(I40E_PHY_TYPE_1000BASE_SX),
 321         I40E_CAP_PHY_TYPE_1000BASE_LX           = BIT(I40E_PHY_TYPE_1000BASE_LX),
 322         I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL    = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
 323         I40E_CAP_PHY_TYPE_20GBASE_KR2           = BIT(I40E_PHY_TYPE_20GBASE_KR2)
 324 };
 325
 326 struct i40e_phy_info {
 327         struct i40e_link_status link_info;
 328         struct i40e_link_status link_info_old;
 329         bool get_link_info;
 330         enum i40e_media_type media_type;
 331         /* all the phy types the NVM is capable of */
 332         u32 phy_types;
 333 };
 334
 335 #define I40E_HW_CAP_MAX_GPIO                    30
 336 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO         0
 337 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C          1
 338
 339 #ifdef X722_SUPPORT
 340 enum i40e_acpi_programming_method {
 341         I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 342         I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 343 };
 344
 345 #define I40E_WOL_SUPPORT_MASK                   1
 346 #define I40E_ACPI_PROGRAMMING_METHOD_MASK       (1 << 1)
 347 #define I40E_PROXY_SUPPORT_MASK                 (1 << 2)
 348
 349 #endif
 350 /* Capabilities of a PF or a VF or the whole device */
 351 struct i40e_hw_capabilities {
 352         u32  switch_mode;
 353 #define I40E_NVM_IMAGE_TYPE_EVB         0x0
 354 #define I40E_NVM_IMAGE_TYPE_CLOUD       0x2
 355 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 356
 357         u32  management_mode;
 358         u32  npar_enable;
 359         u32  os2bmc;
 360         u32  valid_functions;
 361         bool sr_iov_1_1;
 362         bool vmdq;
 363         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 364         bool evb_802_1_qbh; /* Bridge Port Extension */
 365         bool dcb;
 366         bool fcoe;
 367         bool iscsi; /* Indicates iSCSI enabled */
 368         bool flex10_enable;
 369         bool flex10_capable;
 370         u32  flex10_mode;
 371 #define I40E_FLEX10_MODE_UNKNOWN        0x0
 372 #define I40E_FLEX10_MODE_DCC            0x1
 373 #define I40E_FLEX10_MODE_DCI            0x2
 374
 375         u32 flex10_status;
 376 #define I40E_FLEX10_STATUS_DCC_ERROR    0x1
 377 #define I40E_FLEX10_STATUS_VC_MODE      0x2
 378
 379         bool mgmt_cem;
 380         bool ieee_1588;
 381         bool iwarp;
 382         bool fd;
 383         u32 fd_filters_guaranteed;
 384         u32 fd_filters_best_effort;
 385         bool rss;
 386         u32 rss_table_size;
 387         u32 rss_table_entry_width;
 388         bool led[I40E_HW_CAP_MAX_GPIO];
 389         bool sdp[I40E_HW_CAP_MAX_GPIO];
 390         u32 nvm_image_type;
 391         u32 num_flow_director_filters;
 392         u32 num_vfs;
 393         u32 vf_base_id;
 394         u32 num_vsis;
 395         u32 num_rx_qp;
 396         u32 num_tx_qp;
 397         u32 base_queue;
 398         u32 num_msix_vectors;
 399         u32 num_msix_vectors_vf;
 400         u32 led_pin_num;
 401         u32 sdp_pin_num;
 402         u32 mdio_port_num;
 403         u32 mdio_port_mode;
 404         u8 rx_buf_chain_len;
 405         u32 enabled_tcmap;
 406         u32 maxtc;
 407         u64 wr_csr_prot;
 408 #ifdef X722_SUPPORT
 409         bool apm_wol_support;
 410         enum i40e_acpi_programming_method acpi_prog_method;
 411         bool proxy_support;
 412 #endif
 413 };
 414
 415 struct i40e_mac_info {
 416         enum i40e_mac_type type;
 417         u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
 418         u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 419         u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 420         u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];
 421         u16 max_fcoeq;
 422 };
 423
 424 enum i40e_aq_resources_ids {
 425         I40E_NVM_RESOURCE_ID = 1
 426 };
 427
 428 enum i40e_aq_resource_access_type {
 429         I40E_RESOURCE_READ = 1,
 430         I40E_RESOURCE_WRITE
 431 };
 432
 433 struct i40e_nvm_info {
 434         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 435         u32 timeout;              /* [ms] */
 436         u16 sr_size;              /* Shadow RAM size in words */
 437         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 438         u16 version;              /* NVM package version */
 439         u32 eetrack;              /* NVM data version */
 440         u32 oem_ver;              /* OEM version info */
 441 };
 442
 443 /* definitions used in NVM update support */
 444
 445 enum i40e_nvmupd_cmd {
 446         I40E_NVMUPD_INVALID,
 447         I40E_NVMUPD_READ_CON,
 448         I40E_NVMUPD_READ_SNT,
 449         I40E_NVMUPD_READ_LCB,
 450         I40E_NVMUPD_READ_SA,
 451         I40E_NVMUPD_WRITE_ERA,
 452         I40E_NVMUPD_WRITE_CON,
 453         I40E_NVMUPD_WRITE_SNT,
 454         I40E_NVMUPD_WRITE_LCB,
 455         I40E_NVMUPD_WRITE_SA,
 456         I40E_NVMUPD_CSUM_CON,
 457         I40E_NVMUPD_CSUM_SA,
 458         I40E_NVMUPD_CSUM_LCB,
 459         I40E_NVMUPD_STATUS,
 460         I40E_NVMUPD_EXEC_AQ,
 461         I40E_NVMUPD_GET_AQ_RESULT,
 462 };
 463
 464 enum i40e_nvmupd_state {
 465         I40E_NVMUPD_STATE_INIT,
 466         I40E_NVMUPD_STATE_READING,
 467         I40E_NVMUPD_STATE_WRITING,
 468         I40E_NVMUPD_STATE_INIT_WAIT,
 469         I40E_NVMUPD_STATE_WRITE_WAIT,
 470 };
 471
 472 /* nvm_access definition and its masks/shifts need to be accessible to
 473  * application, core driver, and shared code.  Where is the right file?
 474  */
 475 #define I40E_NVM_READ   0xB
 476 #define I40E_NVM_WRITE  0xC
 477
 478 #define I40E_NVM_MOD_PNT_MASK 0xFF
 479
 480 #define I40E_NVM_TRANS_SHIFT    8
 481 #define I40E_NVM_TRANS_MASK     (0xf << I40E_NVM_TRANS_SHIFT)
 482 #define I40E_NVM_CON            0x0
 483 #define I40E_NVM_SNT            0x1
 484 #define I40E_NVM_LCB            0x2
 485 #define I40E_NVM_SA             (I40E_NVM_SNT | I40E_NVM_LCB)
 486 #define I40E_NVM_ERA            0x4
 487 #define I40E_NVM_CSUM           0x8
 488 #define I40E_NVM_EXEC           0xf
 489
 490 #define I40E_NVM_ADAPT_SHIFT    16
 491 #define I40E_NVM_ADAPT_MASK     (0xffffULL << I40E_NVM_ADAPT_SHIFT)
 492
 493 #define I40E_NVMUPD_MAX_DATA    4096
 494 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 495
 496 struct i40e_nvm_access {
 497         u32 command;
 498         u32 config;
 499         u32 offset;     /* in bytes */
 500         u32 data_size;  /* in bytes */
 501         u8 data[1];
 502 };
 503
 504 /* PCI bus types */
 505 enum i40e_bus_type {
 506         i40e_bus_type_unknown = 0,
 507         i40e_bus_type_pci,
 508         i40e_bus_type_pcix,
 509         i40e_bus_type_pci_express,
 510         i40e_bus_type_reserved
 511 };
 512
 513 /* PCI bus speeds */
 514 enum i40e_bus_speed {
 515         i40e_bus_speed_unknown  = 0,
 516         i40e_bus_speed_33       = 33,
 517         i40e_bus_speed_66       = 66,
 518         i40e_bus_speed_100      = 100,
 519         i40e_bus_speed_120      = 120,
 520         i40e_bus_speed_133      = 133,
 521         i40e_bus_speed_2500     = 2500,
 522         i40e_bus_speed_5000     = 5000,
 523         i40e_bus_speed_8000     = 8000,
 524         i40e_bus_speed_reserved
 525 };
 526
 527 /* PCI bus widths */
 528 enum i40e_bus_width {
 529         i40e_bus_width_unknown  = 0,
 530         i40e_bus_width_pcie_x1  = 1,
 531         i40e_bus_width_pcie_x2  = 2,
 532         i40e_bus_width_pcie_x4  = 4,
 533         i40e_bus_width_pcie_x8  = 8,
 534         i40e_bus_width_32       = 32,
 535         i40e_bus_width_64       = 64,
 536         i40e_bus_width_reserved
 537 };
 538
 539 /* Bus parameters */
 540 struct i40e_bus_info {
 541         enum i40e_bus_speed speed;
 542         enum i40e_bus_width width;
 543         enum i40e_bus_type type;
 544
 545         u16 func;
 546         u16 device;
 547         u16 lan_id;
 548 };
 549
 550 /* Flow control (FC) parameters */
 551 struct i40e_fc_info {
 552         enum i40e_fc_mode current_mode; /* FC mode in effect */
 553         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 554 };
 555
 556 #define I40E_MAX_TRAFFIC_CLASS          8
 557 #define I40E_MAX_USER_PRIORITY          8
 558 #define I40E_DCBX_MAX_APPS              32
 559 #define I40E_LLDPDU_SIZE                1500
 560 #define I40E_TLV_STATUS_OPER            0x1
 561 #define I40E_TLV_STATUS_SYNC            0x2
 562 #define I40E_TLV_STATUS_ERR             0x4
 563 #define I40E_CEE_OPER_MAX_APPS          3
 564 #define I40E_APP_PROTOID_FCOE           0x8906
 565 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 566 #define I40E_APP_PROTOID_FIP            0x8914
 567 #define I40E_APP_SEL_ETHTYPE            0x1
 568 #define I40E_APP_SEL_TCPIP              0x2
 569 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 570 #define I40E_CEE_APP_SEL_TCPIP          0x1
 571
 572 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 573 struct i40e_dcb_ets_config {
 574         u8 willing;
 575         u8 cbs;
 576         u8 maxtcs;
 577         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 578         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 579         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 580 };
 581
 582 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 583 struct i40e_dcb_pfc_config {
 584         u8 willing;
 585         u8 mbc;
 586         u8 pfccap;
 587         u8 pfcenable;
 588 };
 589
 590 /* CEE or IEEE 802.1Qaz Application Priority data */
 591 struct i40e_dcb_app_priority_table {
 592         u8  priority;
 593         u8  selector;
 594         u16 protocolid;
 595 };
 596
 597 struct i40e_dcbx_config {
 598         u8  dcbx_mode;
 599 #define I40E_DCBX_MODE_CEE      0x1
 600 #define I40E_DCBX_MODE_IEEE     0x2
 601         u8  app_mode;
 602 #define I40E_DCBX_APPS_NON_WILLING      0x1
 603         u32 numapps;
 604         u32 tlv_status; /* CEE mode TLV status */
 605         struct i40e_dcb_ets_config etscfg;
 606         struct i40e_dcb_ets_config etsrec;
 607         struct i40e_dcb_pfc_config pfc;
 608         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 609 };
 610
 611 /* Port hardware description */
 612 struct i40e_hw {
 613         u8 *hw_addr;
 614         void *back;
 615
 616         /* subsystem structs */
 617         struct i40e_phy_info phy;
 618         struct i40e_mac_info mac;
 619         struct i40e_bus_info bus;
 620         struct i40e_nvm_info nvm;
 621         struct i40e_fc_info fc;
 622
 623         /* pci info */
 624         u16 device_id;
 625         u16 vendor_id;
 626         u16 subsystem_device_id;
 627         u16 subsystem_vendor_id;
 628         u8 revision_id;
 629         u8 port;
 630         bool adapter_stopped;
 631
 632         /* capabilities for entire device and PCI func */
 633         struct i40e_hw_capabilities dev_caps;
 634         struct i40e_hw_capabilities func_caps;
 635
 636         /* Flow Director shared filter space */
 637         u16 fdir_shared_filter_count;
 638
 639         /* device profile info */
 640         u8  pf_id;
 641         u16 main_vsi_seid;
 642
 643         /* for multi-function MACs */
 644         u16 partition_id;
 645         u16 num_partitions;
 646         u16 num_ports;
 647
 648         /* Closest numa node to the device */
 649         u16 numa_node;
 650
 651         /* Admin Queue info */
 652         struct i40e_adminq_info aq;
 653
 654         /* state of nvm update process */
 655         enum i40e_nvmupd_state nvmupd_state;
 656         struct i40e_aq_desc nvm_wb_desc;
 657         struct i40e_virt_mem nvm_buff;
 658
 659         /* HMC info */
 660         struct i40e_hmc_info hmc; /* HMC info struct */
 661
 662         /* LLDP/DCBX Status */
 663         u16 dcbx_status;
 664
 665         /* DCBX info */
 666         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 667         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 668         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 669
 670 #ifdef X722_SUPPORT
 671         /* WoL and proxy support */
 672         u16 num_wol_proxy_filters;
 673         u16 wol_proxy_vsi_seid;
 674
 675 #endif
 676 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 677         u64 flags;
 678
 679         /* debug mask */
 680         u32 debug_mask;
 681 #ifndef I40E_NDIS_SUPPORT
 682         char err_str[16];
 683 #endif /* I40E_NDIS_SUPPORT */
 684 };
 685
 686 STATIC INLINE bool i40e_is_vf(struct i40e_hw *hw)
 687 {
 688 #ifdef X722_SUPPORT
 689         return (hw->mac.type == I40E_MAC_VF ||
 690                 hw->mac.type == I40E_MAC_X722_VF);
 691 #else
 692         return hw->mac.type == I40E_MAC_VF;
 693 #endif
 694 }
 695
 696 struct i40e_driver_version {
 697         u8 major_version;
 698         u8 minor_version;
 699         u8 build_version;
 700         u8 subbuild_version;
 701         u8 driver_string[32];
 702 };
 703
 704 /* RX Descriptors */
 705 union i40e_16byte_rx_desc {
 706         struct {
 707                 __le64 pkt_addr; /* Packet buffer address */
 708                 __le64 hdr_addr; /* Header buffer address */
 709         } read;
 710         struct {
 711                 struct {
 712                         struct {
 713                                 union {
 714                                         __le16 mirroring_status;
 715                                         __le16 fcoe_ctx_id;
 716                                 } mirr_fcoe;
 717                                 __le16 l2tag1;
 718                         } lo_dword;
 719                         union {
 720                                 __le32 rss; /* RSS Hash */
 721                                 __le32 fd_id; /* Flow director filter id */
 722                                 __le32 fcoe_param; /* FCoE DDP Context id */
 723                         } hi_dword;
 724                 } qword0;
 725                 struct {
 726                         /* ext status/error/pktype/length */
 727                         __le64 status_error_len;
 728                 } qword1;
 729         } wb;  /* writeback */
 730 };
 731
 732 union i40e_32byte_rx_desc {
 733         struct {
 734                 __le64  pkt_addr; /* Packet buffer address */
 735                 __le64  hdr_addr; /* Header buffer address */
 736                         /* bit 0 of hdr_buffer_addr is DD bit */
 737                 __le64  rsvd1;
 738                 __le64  rsvd2;
 739         } read;
 740         struct {
 741                 struct {
 742                         struct {
 743                                 union {
 744                                         __le16 mirroring_status;
 745                                         __le16 fcoe_ctx_id;
 746                                 } mirr_fcoe;
 747                                 __le16 l2tag1;
 748                         } lo_dword;
 749                         union {
 750                                 __le32 rss; /* RSS Hash */
 751                                 __le32 fcoe_param; /* FCoE DDP Context id */
 752                                 /* Flow director filter id in case of
 753                                  * Programming status desc WB
 754                                  */
 755                                 __le32 fd_id;
 756                         } hi_dword;
 757                 } qword0;
 758                 struct {
 759                         /* status/error/pktype/length */
 760                         __le64 status_error_len;
 761                 } qword1;
 762                 struct {
 763                         __le16 ext_status; /* extended status */
 764                         __le16 rsvd;
 765                         __le16 l2tag2_1;
 766                         __le16 l2tag2_2;
 767                 } qword2;
 768                 struct {
 769                         union {
 770                                 __le32 flex_bytes_lo;
 771                                 __le32 pe_status;
 772                         } lo_dword;
 773                         union {
 774                                 __le32 flex_bytes_hi;
 775                                 __le32 fd_id;
 776                         } hi_dword;
 777                 } qword3;
 778         } wb;  /* writeback */
 779 };
 780
 781 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT        8
 782 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 783                                          I40E_RXD_QW0_MIRROR_STATUS_SHIFT)
 784 #define I40E_RXD_QW0_FCOEINDX_SHIFT     0
 785 #define I40E_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 786                                          I40E_RXD_QW0_FCOEINDX_SHIFT)
 787
 788 enum i40e_rx_desc_status_bits {
 789         /* Note: These are predefined bit offsets */
 790         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 791         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 792         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 793         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 794         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 795         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 796         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 797 #ifdef X722_SUPPORT
 798         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 799 #else
 800         I40E_RX_DESC_STATUS_RESERVED1_SHIFT     = 8,
 801 #endif
 802
 803         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 804         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 805         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 806         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 807         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 808         I40E_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 809 #ifdef X722_SUPPORT
 810         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 811 #else
 812         I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
 813 #endif
 814         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 815 };
 816
 817 #define I40E_RXD_QW1_STATUS_SHIFT       0
 818 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \
 819                                          I40E_RXD_QW1_STATUS_SHIFT)
 820
 821 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 822 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 823                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 824
 825 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 826 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 827
 828 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT       I40E_RX_DESC_STATUS_UMBCAST
 829 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 830                                          I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)
 831
 832 enum i40e_rx_desc_fltstat_values {
 833         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 834         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 835         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 836         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 837 };
 838
 839 #define I40E_RXD_PACKET_TYPE_UNICAST    0
 840 #define I40E_RXD_PACKET_TYPE_MULTICAST  1
 841 #define I40E_RXD_PACKET_TYPE_BROADCAST  2
 842 #define I40E_RXD_PACKET_TYPE_MIRRORED   3
 843
 844 #define I40E_RXD_QW1_ERROR_SHIFT        19
 845 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 846
 847 enum i40e_rx_desc_error_bits {
 848         /* Note: These are predefined bit offsets */
 849         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 850         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 851         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 852         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 853         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 854         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 855         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 856         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 857         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 858 };
 859
 860 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 861         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 862         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 863         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 864         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 865         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 866 };
 867
 868 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 869 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 870
 871 /* Packet type non-ip values */
 872 enum i40e_rx_l2_ptype {
 873         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 874         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 875         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 876         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 877         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 878         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 879         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 880         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 881         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 882         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 883         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 884         I40E_RX_PTYPE_L2_ARP                            = 11,
 885         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 886         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 887         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 888         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 889         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 890         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 891         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 892         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 893         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 894         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 895         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 896         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 897         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 898         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 899 };
 900
 901 struct i40e_rx_ptype_decoded {
 902         u32 ptype:8;
 903         u32 known:1;
 904         u32 outer_ip:1;
 905         u32 outer_ip_ver:1;
 906         u32 outer_frag:1;
 907         u32 tunnel_type:3;
 908         u32 tunnel_end_prot:2;
 909         u32 tunnel_end_frag:1;
 910         u32 inner_prot:4;
 911         u32 payload_layer:3;
 912 };
 913
 914 enum i40e_rx_ptype_outer_ip {
 915         I40E_RX_PTYPE_OUTER_L2  = 0,
 916         I40E_RX_PTYPE_OUTER_IP  = 1
 917 };
 918
 919 enum i40e_rx_ptype_outer_ip_ver {
 920         I40E_RX_PTYPE_OUTER_NONE        = 0,
 921         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 922         I40E_RX_PTYPE_OUTER_IPV6        = 1
 923 };
 924
 925 enum i40e_rx_ptype_outer_fragmented {
 926         I40E_RX_PTYPE_NOT_FRAG  = 0,
 927         I40E_RX_PTYPE_FRAG      = 1
 928 };
 929
 930 enum i40e_rx_ptype_tunnel_type {
 931         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 932         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 933         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 934         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 935         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 936 };
 937
 938 enum i40e_rx_ptype_tunnel_end_prot {
 939         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 940         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 941         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 942 };
 943
 944 enum i40e_rx_ptype_inner_prot {
 945         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 946         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 947         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 948         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 949         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 950         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 951 };
 952
 953 enum i40e_rx_ptype_payload_layer {
 954         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 955         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 956         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 957         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 958 };
 959
 960 #define I40E_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 961 #define I40E_RX_PTYPE_SHIFT             56
 962
 963 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 964 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 965                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 966
 967 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT  52
 968 #define I40E_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 969                                          I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
 970
 971 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 972 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 973
 974 #define I40E_RXD_QW1_NEXTP_SHIFT        38
 975 #define I40E_RXD_QW1_NEXTP_MASK         (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)
 976
 977 #define I40E_RXD_QW2_EXT_STATUS_SHIFT   0
 978 #define I40E_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 979                                          I40E_RXD_QW2_EXT_STATUS_SHIFT)
 980
 981 enum i40e_rx_desc_ext_status_bits {
 982         /* Note: These are predefined bit offsets */
 983         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 984         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 985         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 986         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 987         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 988         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 989         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 990 };
 991
 992 #define I40E_RXD_QW2_L2TAG2_SHIFT       0
 993 #define I40E_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)
 994
 995 #define I40E_RXD_QW2_L2TAG3_SHIFT       16
 996 #define I40E_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)
 997
 998 enum i40e_rx_desc_pe_status_bits {
 999         /* Note: These are predefined bit offsets */
1000         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1001         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1002         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1003         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1004         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1005         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1006         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1007         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1008         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1009 };
1010
1011 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1012 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1013
1014 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1015 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1016                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1017
1018 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1019 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1020                                 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1021
1022 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1023 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1024                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1025
1026 enum i40e_rx_prog_status_desc_status_bits {
1027         /* Note: These are predefined bit offsets */
1028         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1029         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1030 };
1031
1032 enum i40e_rx_prog_status_desc_prog_id_masks {
1033         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1034         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1035         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1036 };
1037
1038 enum i40e_rx_prog_status_desc_error_bits {
1039         /* Note: These are predefined bit offsets */
1040         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1041         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1042         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1043         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1044 };
1045
1046 #define I40E_TWO_BIT_MASK       0x3
1047 #define I40E_THREE_BIT_MASK     0x7
1048 #define I40E_FOUR_BIT_MASK      0xF
1049 #define I40E_EIGHTEEN_BIT_MASK  0x3FFFF
1050
1051 /* TX Descriptor */
1052 struct i40e_tx_desc {
1053         __le64 buffer_addr; /* Address of descriptor's data buf */
1054         __le64 cmd_type_offset_bsz;
1055 };
1056
1057 #define I40E_TXD_QW1_DTYPE_SHIFT        0
1058 #define I40E_TXD_QW1_DTYPE_MASK         (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
1059
1060 enum i40e_tx_desc_dtype_value {
1061         I40E_TX_DESC_DTYPE_DATA         = 0x0,
1062         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1063         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
1064         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1065         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1066         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1067         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1068         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1069         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1070         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
1071 };
1072
1073 #define I40E_TXD_QW1_CMD_SHIFT  4
1074 #define I40E_TXD_QW1_CMD_MASK   (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
1075
1076 enum i40e_tx_desc_cmd_bits {
1077         I40E_TX_DESC_CMD_EOP                    = 0x0001,
1078         I40E_TX_DESC_CMD_RS                     = 0x0002,
1079         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
1080         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
1081         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
1082         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1083         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1084         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1085         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1086         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
1087         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1088         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1089         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1090         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1091         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1092         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1093         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1094         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1095 };
1096
1097 #define I40E_TXD_QW1_OFFSET_SHIFT       16
1098 #define I40E_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1099                                          I40E_TXD_QW1_OFFSET_SHIFT)
1100
1101 enum i40e_tx_desc_length_fields {
1102         /* Note: These are predefined bit offsets */
1103         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1104         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1105         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1106 };
1107
1108 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)
1109 #define I40E_TXD_QW1_IPLEN_MASK  (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)
1110 #define I40E_TXD_QW1_L4LEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1111 #define I40E_TXD_QW1_FCLEN_MASK  (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1112
1113 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
1114 #define I40E_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1115                                          I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1116
1117 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
1118 #define I40E_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1119
1120 /* Context descriptors */
1121 struct i40e_tx_context_desc {
1122         __le32 tunneling_params;
1123         __le16 l2tag2;
1124         __le16 rsvd;
1125         __le64 type_cmd_tso_mss;
1126 };
1127
1128 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT    0
1129 #define I40E_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1130
1131 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
1132 #define I40E_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1133
1134 enum i40e_tx_ctx_desc_cmd_bits {
1135         I40E_TX_CTX_DESC_TSO            = 0x01,
1136         I40E_TX_CTX_DESC_TSYN           = 0x02,
1137         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
1138         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1139         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1140         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1141         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1142         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1143         I40E_TX_CTX_DESC_SWPE           = 0x40
1144 };
1145
1146 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1147 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1148                                          I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1149
1150 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
1151 #define I40E_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1152                                          I40E_TXD_CTX_QW1_MSS_SHIFT)
1153
1154 #define I40E_TXD_CTX_QW1_VSI_SHIFT      50
1155 #define I40E_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1156
1157 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT   0
1158 #define I40E_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1159                                          I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1160
1161 enum i40e_tx_ctx_desc_eipt_offload {
1162         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
1163         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
1164         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1165         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
1166 };
1167
1168 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1169 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1170                                          I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1171
1172 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
1173 #define I40E_TXD_CTX_QW0_NATT_MASK      (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1174
1175 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1176 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1177
1178 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1179 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1180
1181 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST       I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1182
1183 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1184 #define I40E_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1185                                          I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1186
1187 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT   19
1188 #define I40E_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1189                                          I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1190
1191 #ifdef X722_SUPPORT
1192 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1193 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1194 #endif
1195 struct i40e_nop_desc {
1196         __le64 rsvd;
1197         __le64 dtype_cmd;
1198 };
1199
1200 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT    0
1201 #define I40E_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)
1202
1203 #define I40E_TXD_NOP_QW1_CMD_SHIFT      4
1204 #define I40E_TXD_NOP_QW1_CMD_MASK       (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)
1205
1206 enum i40e_tx_nop_desc_cmd_bits {
1207         /* Note: These are predefined bit offsets */
1208         I40E_TX_NOP_DESC_EOP_SHIFT      = 0,
1209         I40E_TX_NOP_DESC_RS_SHIFT       = 1,
1210         I40E_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1211 };
1212
1213 struct i40e_filter_program_desc {
1214         __le32 qindex_flex_ptype_vsi;
1215         __le32 rsvd;
1216         __le32 dtype_cmd_cntindex;
1217         __le32 fd_id;
1218 };
1219 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1220 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1221                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1222 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1223 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1224                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1225 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1226 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1227                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1228
1229 /* Packet Classifier Types for filters */
1230 enum i40e_filter_pctype {
1231 #ifdef X722_SUPPORT
1232         /* Note: Values 0-28 are reserved for future use.
1233          * Value 29, 30, 32 are not supported on XL710 and X710.
1234          */
1235         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1236         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1237 #else
1238         /* Note: Values 0-30 are reserved for future use */
1239 #endif
1240         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1241 #ifdef X722_SUPPORT
1242         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1243 #else
1244         /* Note: Value 32 is reserved for future use */
1245 #endif
1246         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1247         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1248         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1249         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1250 #ifdef X722_SUPPORT
1251         /* Note: Values 37-38 are reserved for future use.
1252          * Value 39, 40, 42 are not supported on XL710 and X710.
1253          */
1254         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1255         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1256 #else
1257         /* Note: Values 37-40 are reserved for future use */
1258 #endif
1259         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1260 #ifdef X722_SUPPORT
1261         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1262 #endif
1263         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1264         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1265         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1266         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1267         /* Note: Value 47 is reserved for future use */
1268         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1269         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1270         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1271         /* Note: Values 51-62 are reserved for future use */
1272         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1273 };
1274
1275 enum i40e_filter_program_desc_dest {
1276         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1277         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1278         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1279 };
1280
1281 enum i40e_filter_program_desc_fd_status {
1282         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1283         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1284         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1285         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1286 };
1287
1288 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1289 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1290                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1291
1292 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT   0
1293 #define I40E_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)
1294
1295 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1296 #define I40E_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1297                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1298
1299 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1300 #define I40E_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1301
1302 enum i40e_filter_program_desc_pcmd {
1303         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1304         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1305 };
1306
1307 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1308 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1309
1310 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1311 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1312
1313 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1314                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1315 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1316                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1317 #ifdef X722_SUPPORT
1318
1319 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1320                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1321 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1322 #endif
1323
1324 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1325 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1326                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1327
1328 enum i40e_filter_type {
1329         I40E_FLOW_DIRECTOR_FLTR = 0,
1330         I40E_PE_QUAD_HASH_FLTR = 1,
1331         I40E_ETHERTYPE_FLTR,
1332         I40E_FCOE_CTX_FLTR,
1333         I40E_MAC_VLAN_FLTR,
1334         I40E_HASH_FLTR
1335 };
1336
1337 struct i40e_vsi_context {
1338         u16 seid;
1339         u16 uplink_seid;
1340         u16 vsi_number;
1341         u16 vsis_allocated;
1342         u16 vsis_unallocated;
1343         u16 flags;
1344         u8 pf_num;
1345         u8 vf_num;
1346         u8 connection_type;
1347         struct i40e_aqc_vsi_properties_data info;
1348 };
1349
1350 struct i40e_veb_context {
1351         u16 seid;
1352         u16 uplink_seid;
1353         u16 veb_number;
1354         u16 vebs_allocated;
1355         u16 vebs_unallocated;
1356         u16 flags;
1357         struct i40e_aqc_get_veb_parameters_completion info;
1358 };
1359
1360 /* Statistics collected by each port, VSI, VEB, and S-channel */
1361 struct i40e_eth_stats {
1362         u64 rx_bytes;                   /* gorc */
1363         u64 rx_unicast;                 /* uprc */
1364         u64 rx_multicast;               /* mprc */
1365         u64 rx_broadcast;               /* bprc */
1366         u64 rx_discards;                /* rdpc */
1367         u64 rx_unknown_protocol;        /* rupp */
1368         u64 tx_bytes;                   /* gotc */
1369         u64 tx_unicast;                 /* uptc */
1370         u64 tx_multicast;               /* mptc */
1371         u64 tx_broadcast;               /* bptc */
1372         u64 tx_discards;                /* tdpc */
1373         u64 tx_errors;                  /* tepc */
1374 };
1375
1376 /* Statistics collected per VEB per TC */
1377 struct i40e_veb_tc_stats {
1378         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1379         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1380         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1381         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1382 };
1383
1384 /* Statistics collected by the MAC */
1385 struct i40e_hw_port_stats {
1386         /* eth stats collected by the port */
1387         struct i40e_eth_stats eth;
1388
1389         /* additional port specific stats */
1390         u64 tx_dropped_link_down;       /* tdold */
1391         u64 crc_errors;                 /* crcerrs */
1392         u64 illegal_bytes;              /* illerrc */
1393         u64 error_bytes;                /* errbc */
1394         u64 mac_local_faults;           /* mlfc */
1395         u64 mac_remote_faults;          /* mrfc */
1396         u64 rx_length_errors;           /* rlec */
1397         u64 link_xon_rx;                /* lxonrxc */
1398         u64 link_xoff_rx;               /* lxoffrxc */
1399         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1400         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1401         u64 link_xon_tx;                /* lxontxc */
1402         u64 link_xoff_tx;               /* lxofftxc */
1403         u64 priority_xon_tx[8];         /* pxontxc[8] */
1404         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1405         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1406         u64 rx_size_64;                 /* prc64 */
1407         u64 rx_size_127;                /* prc127 */
1408         u64 rx_size_255;                /* prc255 */
1409         u64 rx_size_511;                /* prc511 */
1410         u64 rx_size_1023;               /* prc1023 */
1411         u64 rx_size_1522;               /* prc1522 */
1412         u64 rx_size_big;                /* prc9522 */
1413         u64 rx_undersize;               /* ruc */
1414         u64 rx_fragments;               /* rfc */
1415         u64 rx_oversize;                /* roc */
1416         u64 rx_jabber;                  /* rjc */
1417         u64 tx_size_64;                 /* ptc64 */
1418         u64 tx_size_127;                /* ptc127 */
1419         u64 tx_size_255;                /* ptc255 */
1420         u64 tx_size_511;                /* ptc511 */
1421         u64 tx_size_1023;               /* ptc1023 */
1422         u64 tx_size_1522;               /* ptc1522 */
1423         u64 tx_size_big;                /* ptc9522 */
1424         u64 mac_short_packet_dropped;   /* mspdc */
1425         u64 checksum_error;             /* xec */
1426         /* flow director stats */
1427         u64 fd_atr_match;
1428         u64 fd_sb_match;
1429         u64 fd_atr_tunnel_match;
1430         u32 fd_atr_status;
1431         u32 fd_sb_status;
1432         /* EEE LPI */
1433         u32 tx_lpi_status;
1434         u32 rx_lpi_status;
1435         u64 tx_lpi_count;               /* etlpic */
1436         u64 rx_lpi_count;               /* erlpic */
1437 };
1438
1439 /* Checksum and Shadow RAM pointers */
1440 #define I40E_SR_NVM_CONTROL_WORD                0x00
1441 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1442 #define I40E_SR_PHY_ANALOG_CONFIG_PTR           0x04
1443 #define I40E_SR_OPTION_ROM_PTR                  0x05
1444 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1445 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1446 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1447 #define I40E_SR_EMP_GLOBAL_MODULE_PTR           0x09
1448 #define I40E_SR_RO_PCIE_LCB_PTR                 0x0A
1449 #define I40E_SR_EMP_IMAGE_PTR                   0x0B
1450 #define I40E_SR_PE_IMAGE_PTR                    0x0C
1451 #define I40E_SR_CSR_PROTECTED_LIST_PTR          0x0D
1452 #define I40E_SR_MNG_CONFIG_PTR                  0x0E
1453 #define I40E_SR_EMP_MODULE_PTR                  0x0F
1454 #define I40E_SR_PBA_FLAGS                       0x15
1455 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1456 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1457 #define I40E_NVM_OEM_VER_OFF                    0x83
1458 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1459 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1460 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1461 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1462 #define I40E_SR_NVM_MAP_VERSION                 0x29
1463 #define I40E_SR_NVM_IMAGE_VERSION               0x2A
1464 #define I40E_SR_NVM_STRUCTURE_VERSION           0x2B
1465 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1466 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1467 #define I40E_SR_VPD_PTR                         0x2F
1468 #define I40E_SR_PXE_SETUP_PTR                   0x30
1469 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1470 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1471 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1472 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1473 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1474 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1475 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1476 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1477 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1478 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1479 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1480 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1481 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1482 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1483 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1484 #define I40E_SR_FEATURE_CONFIGURATION_PTR       0x49
1485 #define I40E_SR_CONFIGURATION_METADATA_PTR      0x4D
1486 #define I40E_SR_IMMEDIATE_VALUES_PTR            0x4E
1487
1488 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1489 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1490 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1491 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1492 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1493
1494 /* Shadow RAM related */
1495 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1496 #define I40E_SR_BUF_ALIGNMENT           4096
1497 #define I40E_SR_WORDS_IN_1KB            512
1498 /* Checksum should be calculated such that after adding all the words,
1499  * including the checksum word itself, the sum should be 0xBABA.
1500  */
1501 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1502
1503 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1504
1505 enum i40e_switch_element_types {
1506         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1507         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1508         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1509         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1510         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1511         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1512         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1513         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1514         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1515 };
1516
1517 /* Supported EtherType filters */
1518 enum i40e_ether_type_index {
1519         I40E_ETHER_TYPE_1588            = 0,
1520         I40E_ETHER_TYPE_FIP             = 1,
1521         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1522         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1523         I40E_ETHER_TYPE_LLDP            = 4,
1524         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1525         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1526         I40E_ETHER_TYPE_QCN_CNM         = 7,
1527         I40E_ETHER_TYPE_8021X           = 8,
1528         I40E_ETHER_TYPE_ARP             = 9,
1529         I40E_ETHER_TYPE_RSV1            = 10,
1530         I40E_ETHER_TYPE_RSV2            = 11,
1531 };
1532
1533 /* Filter context base size is 1K */
1534 #define I40E_HASH_FILTER_BASE_SIZE      1024
1535 /* Supported Hash filter values */
1536 enum i40e_hash_filter_size {
1537         I40E_HASH_FILTER_SIZE_1K        = 0,
1538         I40E_HASH_FILTER_SIZE_2K        = 1,
1539         I40E_HASH_FILTER_SIZE_4K        = 2,
1540         I40E_HASH_FILTER_SIZE_8K        = 3,
1541         I40E_HASH_FILTER_SIZE_16K       = 4,
1542         I40E_HASH_FILTER_SIZE_32K       = 5,
1543         I40E_HASH_FILTER_SIZE_64K       = 6,
1544         I40E_HASH_FILTER_SIZE_128K      = 7,
1545         I40E_HASH_FILTER_SIZE_256K      = 8,
1546         I40E_HASH_FILTER_SIZE_512K      = 9,
1547         I40E_HASH_FILTER_SIZE_1M        = 10,
1548 };
1549
1550 /* DMA context base size is 0.5K */
1551 #define I40E_DMA_CNTX_BASE_SIZE         512
1552 /* Supported DMA context values */
1553 enum i40e_dma_cntx_size {
1554         I40E_DMA_CNTX_SIZE_512          = 0,
1555         I40E_DMA_CNTX_SIZE_1K           = 1,
1556         I40E_DMA_CNTX_SIZE_2K           = 2,
1557         I40E_DMA_CNTX_SIZE_4K           = 3,
1558         I40E_DMA_CNTX_SIZE_8K           = 4,
1559         I40E_DMA_CNTX_SIZE_16K          = 5,
1560         I40E_DMA_CNTX_SIZE_32K          = 6,
1561         I40E_DMA_CNTX_SIZE_64K          = 7,
1562         I40E_DMA_CNTX_SIZE_128K         = 8,
1563         I40E_DMA_CNTX_SIZE_256K         = 9,
1564 };
1565
1566 /* Supported Hash look up table (LUT) sizes */
1567 enum i40e_hash_lut_size {
1568         I40E_HASH_LUT_SIZE_128          = 0,
1569         I40E_HASH_LUT_SIZE_512          = 1,
1570 };
1571
1572 /* Structure to hold a per PF filter control settings */
1573 struct i40e_filter_control_settings {
1574         /* number of PE Quad Hash filter buckets */
1575         enum i40e_hash_filter_size pe_filt_num;
1576         /* number of PE Quad Hash contexts */
1577         enum i40e_dma_cntx_size pe_cntx_num;
1578         /* number of FCoE filter buckets */
1579         enum i40e_hash_filter_size fcoe_filt_num;
1580         /* number of FCoE DDP contexts */
1581         enum i40e_dma_cntx_size fcoe_cntx_num;
1582         /* size of the Hash LUT */
1583         enum i40e_hash_lut_size hash_lut_size;
1584         /* enable FDIR filters for PF and its VFs */
1585         bool enable_fdir;
1586         /* enable Ethertype filters for PF and its VFs */
1587         bool enable_ethtype;
1588         /* enable MAC/VLAN filters for PF and its VFs */
1589         bool enable_macvlan;
1590 };
1591
1592 /* Structure to hold device level control filter counts */
1593 struct i40e_control_filter_stats {
1594         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1595         u16 etype_used;       /* Used perfect EtherType filters */
1596         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1597         u16 etype_free;       /* Un-used perfect EtherType filters */
1598 };
1599
1600 enum i40e_reset_type {
1601         I40E_RESET_POR          = 0,
1602         I40E_RESET_CORER        = 1,
1603         I40E_RESET_GLOBR        = 2,
1604         I40E_RESET_EMPR         = 3,
1605 };
1606
1607 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1608 #define I40E_NVM_LLDP_CFG_PTR           0xD
1609 struct i40e_lldp_variables {
1610         u16 length;
1611         u16 adminstatus;
1612         u16 msgfasttx;
1613         u16 msgtxinterval;
1614         u16 txparams;
1615         u16 timers;
1616         u16 crc8;
1617 };
1618
1619 /* Offsets into Alternate Ram */
1620 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1621 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1622 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1623 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1624 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1625 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1626
1627 /* Alternate Ram Bandwidth Masks */
1628 #define I40E_ALT_BW_VALUE_MASK          0xFF
1629 #define I40E_ALT_BW_RELATIVE_MASK       0x40000000
1630 #define I40E_ALT_BW_VALID_MASK          0x80000000
1631
1632 /* RSS Hash Table Size */
1633 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1634 #endif /* _I40E_TYPE_H_ */