drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control enable fwd bit */
  87 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  88
  89 /* Receive Packet Buffer size */
  90 #define I40E_RXPBSIZE (968 * 1024)
  91
  92 /* Kilobytes shift */
  93 #define I40E_KILOSHIFT 10
  94
  95 /* Flow control default high water */
  96 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  97
  98 /* Flow control default low water */
  99 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(
 377                 __rte_unused struct rte_intr_handle *handle, void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 426                                                      uint16_t seid,
 427                                                      uint16_t rule_type,
 428                                                      uint16_t *entries,
 429                                                      uint16_t count,
 430                                                      uint16_t rule_id);
 431 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 432                         struct rte_eth_mirror_conf *mirror_conf,
 433                         uint8_t sw_id, uint8_t on);
 434 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 435
 436 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 437 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 438 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 439                                            struct timespec *timestamp,
 440                                            uint32_t flags);
 441 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 442                                            struct timespec *timestamp);
 443 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 444
 445 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 446
 447 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 448                                    struct timespec *timestamp);
 449 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 450                                     const struct timespec *timestamp);
 451
 452 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 453                                          uint16_t queue_id);
 454 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 455                                           uint16_t queue_id);
 456
 457 static int i40e_get_regs(struct rte_eth_dev *dev,
 458                          struct rte_dev_reg_info *regs);
 459
 460 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 461
 462 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 463                            struct rte_dev_eeprom_info *eeprom);
 464
 465 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 466                                       struct ether_addr *mac_addr);
 467
 468 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 469 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 470
 471 static const struct rte_pci_id pci_id_i40e_map[] = {
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 486         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 487         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 488         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 489         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 490         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 491         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 492         { .vendor_id = 0, /* sentinel */ },
 493 };
 494
 495 static const struct eth_dev_ops i40e_eth_dev_ops = {
 496         .dev_configure                = i40e_dev_configure,
 497         .dev_start                    = i40e_dev_start,
 498         .dev_stop                     = i40e_dev_stop,
 499         .dev_close                    = i40e_dev_close,
 500         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 501         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 502         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 503         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 504         .dev_set_link_up              = i40e_dev_set_link_up,
 505         .dev_set_link_down            = i40e_dev_set_link_down,
 506         .link_update                  = i40e_dev_link_update,
 507         .stats_get                    = i40e_dev_stats_get,
 508         .xstats_get                   = i40e_dev_xstats_get,
 509         .xstats_get_names             = i40e_dev_xstats_get_names,
 510         .stats_reset                  = i40e_dev_stats_reset,
 511         .xstats_reset                 = i40e_dev_stats_reset,
 512         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 513         .dev_infos_get                = i40e_dev_info_get,
 514         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 515         .vlan_filter_set              = i40e_vlan_filter_set,
 516         .vlan_tpid_set                = i40e_vlan_tpid_set,
 517         .vlan_offload_set             = i40e_vlan_offload_set,
 518         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 519         .vlan_pvid_set                = i40e_vlan_pvid_set,
 520         .rx_queue_start               = i40e_dev_rx_queue_start,
 521         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 522         .tx_queue_start               = i40e_dev_tx_queue_start,
 523         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 524         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 525         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 526         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 527         .rx_queue_release             = i40e_dev_rx_queue_release,
 528         .rx_queue_count               = i40e_dev_rx_queue_count,
 529         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 530         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 531         .tx_queue_release             = i40e_dev_tx_queue_release,
 532         .dev_led_on                   = i40e_dev_led_on,
 533         .dev_led_off                  = i40e_dev_led_off,
 534         .flow_ctrl_get                = i40e_flow_ctrl_get,
 535         .flow_ctrl_set                = i40e_flow_ctrl_set,
 536         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 537         .mac_addr_add                 = i40e_macaddr_add,
 538         .mac_addr_remove              = i40e_macaddr_remove,
 539         .reta_update                  = i40e_dev_rss_reta_update,
 540         .reta_query                   = i40e_dev_rss_reta_query,
 541         .rss_hash_update              = i40e_dev_rss_hash_update,
 542         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 543         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 544         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 545         .filter_ctrl                  = i40e_dev_filter_ctrl,
 546         .rxq_info_get                 = i40e_rxq_info_get,
 547         .txq_info_get                 = i40e_txq_info_get,
 548         .mirror_rule_set              = i40e_mirror_rule_set,
 549         .mirror_rule_reset            = i40e_mirror_rule_reset,
 550         .timesync_enable              = i40e_timesync_enable,
 551         .timesync_disable             = i40e_timesync_disable,
 552         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 553         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 554         .get_dcb_info                 = i40e_dev_get_dcb_info,
 555         .timesync_adjust_time         = i40e_timesync_adjust_time,
 556         .timesync_read_time           = i40e_timesync_read_time,
 557         .timesync_write_time          = i40e_timesync_write_time,
 558         .get_reg                      = i40e_get_regs,
 559         .get_eeprom_length            = i40e_get_eeprom_length,
 560         .get_eeprom                   = i40e_get_eeprom,
 561         .mac_addr_set                 = i40e_set_default_mac_addr,
 562         .mtu_set                      = i40e_dev_mtu_set,
 563 };
 564
 565 /* store statistics names and its offset in stats structure */
 566 struct rte_i40e_xstats_name_off {
 567         char name[RTE_ETH_XSTATS_NAME_SIZE];
 568         unsigned offset;
 569 };
 570
 571 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 572         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 573         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 574         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 575         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 576         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 577                 rx_unknown_protocol)},
 578         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 579         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 580         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 581         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 582 };
 583
 584 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 585                 sizeof(rte_i40e_stats_strings[0]))
 586
 587 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 588         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 589                 tx_dropped_link_down)},
 590         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 591         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 592                 illegal_bytes)},
 593         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 594         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 595                 mac_local_faults)},
 596         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 597                 mac_remote_faults)},
 598         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 599                 rx_length_errors)},
 600         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 601         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 602         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 603         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 604         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 605         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 606                 rx_size_127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 608                 rx_size_255)},
 609         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 610                 rx_size_511)},
 611         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 612                 rx_size_1023)},
 613         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 614                 rx_size_1522)},
 615         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 616                 rx_size_big)},
 617         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 618                 rx_undersize)},
 619         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 620                 rx_oversize)},
 621         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 622                 mac_short_packet_dropped)},
 623         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 624                 rx_fragments)},
 625         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 626         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 627         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 628                 tx_size_127)},
 629         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 630                 tx_size_255)},
 631         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 632                 tx_size_511)},
 633         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 634                 tx_size_1023)},
 635         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 636                 tx_size_1522)},
 637         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 638                 tx_size_big)},
 639         {"rx_flow_director_atr_match_packets",
 640                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 641         {"rx_flow_director_sb_match_packets",
 642                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 643         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 644                 tx_lpi_status)},
 645         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 646                 rx_lpi_status)},
 647         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 648                 tx_lpi_count)},
 649         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 650                 rx_lpi_count)},
 651 };
 652
 653 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 654                 sizeof(rte_i40e_hw_port_strings[0]))
 655
 656 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 657         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_rx)},
 659         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 660                 priority_xoff_rx)},
 661 };
 662
 663 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 664                 sizeof(rte_i40e_rxq_prio_strings[0]))
 665
 666 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 667         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 668                 priority_xon_tx)},
 669         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 670                 priority_xoff_tx)},
 671         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 672                 priority_xon_2_xoff)},
 673 };
 674
 675 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 676                 sizeof(rte_i40e_txq_prio_strings[0]))
 677
 678 static struct eth_driver rte_i40e_pmd = {
 679         .pci_drv = {
 680                 .id_table = pci_id_i40e_map,
 681                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 682                         RTE_PCI_DRV_DETACHABLE,
 683                 .probe = rte_eth_dev_pci_probe,
 684                 .remove = rte_eth_dev_pci_remove,
 685         },
 686         .eth_dev_init = eth_i40e_dev_init,
 687         .eth_dev_uninit = eth_i40e_dev_uninit,
 688         .dev_private_size = sizeof(struct i40e_adapter),
 689 };
 690
 691 static inline int
 692 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 693                                      struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = link;
 696         struct rte_eth_link *src = &(dev->data->dev_link);
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 static inline int
 706 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 707                                       struct rte_eth_link *link)
 708 {
 709         struct rte_eth_link *dst = &(dev->data->dev_link);
 710         struct rte_eth_link *src = link;
 711
 712         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 713                                         *(uint64_t *)src) == 0)
 714                 return -1;
 715
 716         return 0;
 717 }
 718
 719 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 720 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 721
 722 #ifndef I40E_GLQF_ORT
 723 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 724 #endif
 725 #ifndef I40E_GLQF_PIT
 726 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 727 #endif
 728
 729 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 730 {
 731         /*
 732          * Force global configuration for flexible payload
 733          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 734          * This should be removed from code once proper
 735          * configuration API is added to avoid configuration conflicts
 736          * between ports of the same device.
 737          */
 738         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 739         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 740         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 741
 742         /*
 743          * Initialize registers for parsing packet type of QinQ
 744          * This should be removed from code once proper
 745          * configuration API is added to avoid configuration conflicts
 746          * between ports of the same device.
 747          */
 748         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 749         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 750 }
 751
 752 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 753
 754 /*
 755  * Add a ethertype filter to drop all flow control frames transmitted
 756  * from VSIs.
 757 */
 758 static void
 759 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 760 {
 761         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 762         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 763                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 764                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 765         int ret;
 766
 767         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 768                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 769                                 pf->main_vsi_seid, 0,
 770                                 TRUE, NULL, NULL);
 771         if (ret)
 772                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 773                                   " frames from VSIs.");
 774 }
 775
 776 static int
 777 floating_veb_list_handler(__rte_unused const char *key,
 778                           const char *floating_veb_value,
 779                           void *opaque)
 780 {
 781         int idx = 0;
 782         unsigned int count = 0;
 783         char *end = NULL;
 784         int min, max;
 785         bool *vf_floating_veb = opaque;
 786
 787         while (isblank(*floating_veb_value))
 788                 floating_veb_value++;
 789
 790         /* Reset floating VEB configuration for VFs */
 791         for (idx = 0; idx < I40E_MAX_VF; idx++)
 792                 vf_floating_veb[idx] = false;
 793
 794         min = I40E_MAX_VF;
 795         do {
 796                 while (isblank(*floating_veb_value))
 797                         floating_veb_value++;
 798                 if (*floating_veb_value == '\0')
 799                         return -1;
 800                 errno = 0;
 801                 idx = strtoul(floating_veb_value, &end, 10);
 802                 if (errno || end == NULL)
 803                         return -1;
 804                 while (isblank(*end))
 805                         end++;
 806                 if (*end == '-') {
 807                         min = idx;
 808                 } else if ((*end == ';') || (*end == '\0')) {
 809                         max = idx;
 810                         if (min == I40E_MAX_VF)
 811                                 min = idx;
 812                         if (max >= I40E_MAX_VF)
 813                                 max = I40E_MAX_VF - 1;
 814                         for (idx = min; idx <= max; idx++) {
 815                                 vf_floating_veb[idx] = true;
 816                                 count++;
 817                         }
 818                         min = I40E_MAX_VF;
 819                 } else {
 820                         return -1;
 821                 }
 822                 floating_veb_value = end + 1;
 823         } while (*end != '\0');
 824
 825         if (count == 0)
 826                 return -1;
 827
 828         return 0;
 829 }
 830
 831 static void
 832 config_vf_floating_veb(struct rte_devargs *devargs,
 833                        uint16_t floating_veb,
 834                        bool *vf_floating_veb)
 835 {
 836         struct rte_kvargs *kvlist;
 837         int i;
 838         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 839
 840         if (!floating_veb)
 841                 return;
 842         /* All the VFs attach to the floating VEB by default
 843          * when the floating VEB is enabled.
 844          */
 845         for (i = 0; i < I40E_MAX_VF; i++)
 846                 vf_floating_veb[i] = true;
 847
 848         if (devargs == NULL)
 849                 return;
 850
 851         kvlist = rte_kvargs_parse(devargs->args, NULL);
 852         if (kvlist == NULL)
 853                 return;
 854
 855         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 856                 rte_kvargs_free(kvlist);
 857                 return;
 858         }
 859         /* When the floating_veb_list parameter exists, all the VFs
 860          * will attach to the legacy VEB firstly, then configure VFs
 861          * to the floating VEB according to the floating_veb_list.
 862          */
 863         if (rte_kvargs_process(kvlist, floating_veb_list,
 864                                floating_veb_list_handler,
 865                                vf_floating_veb) < 0) {
 866                 rte_kvargs_free(kvlist);
 867                 return;
 868         }
 869         rte_kvargs_free(kvlist);
 870 }
 871
 872 static int
 873 i40e_check_floating_handler(__rte_unused const char *key,
 874                             const char *value,
 875                             __rte_unused void *opaque)
 876 {
 877         if (strcmp(value, "1"))
 878                 return -1;
 879
 880         return 0;
 881 }
 882
 883 static int
 884 is_floating_veb_supported(struct rte_devargs *devargs)
 885 {
 886         struct rte_kvargs *kvlist;
 887         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 888
 889         if (devargs == NULL)
 890                 return 0;
 891
 892         kvlist = rte_kvargs_parse(devargs->args, NULL);
 893         if (kvlist == NULL)
 894                 return 0;
 895
 896         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 897                 rte_kvargs_free(kvlist);
 898                 return 0;
 899         }
 900         /* Floating VEB is enabled when there's key-value:
 901          * enable_floating_veb=1
 902          */
 903         if (rte_kvargs_process(kvlist, floating_veb_key,
 904                                i40e_check_floating_handler, NULL) < 0) {
 905                 rte_kvargs_free(kvlist);
 906                 return 0;
 907         }
 908         rte_kvargs_free(kvlist);
 909
 910         return 1;
 911 }
 912
 913 static void
 914 config_floating_veb(struct rte_eth_dev *dev)
 915 {
 916         struct rte_pci_device *pci_dev = dev->pci_dev;
 917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919
 920         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 921
 922         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 923                 pf->floating_veb =
 924                         is_floating_veb_supported(pci_dev->device.devargs);
 925                 config_vf_floating_veb(pci_dev->device.devargs,
 926                                        pf->floating_veb,
 927                                        pf->floating_veb_list);
 928         } else {
 929                 pf->floating_veb = false;
 930         }
 931 }
 932
 933 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 934 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 935
 936 static int
 937 eth_i40e_dev_init(struct rte_eth_dev *dev)
 938 {
 939         struct rte_pci_device *pci_dev;
 940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 942         struct i40e_vsi *vsi;
 943         int ret;
 944         uint32_t len;
 945         uint8_t aq_fail = 0;
 946
 947         PMD_INIT_FUNC_TRACE();
 948
 949         dev->dev_ops = &i40e_eth_dev_ops;
 950         dev->rx_pkt_burst = i40e_recv_pkts;
 951         dev->tx_pkt_burst = i40e_xmit_pkts;
 952
 953         /* for secondary processes, we don't initialise any further as primary
 954          * has already done this work. Only check we don't need a different
 955          * RX function */
 956         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 957                 i40e_set_rx_function(dev);
 958                 i40e_set_tx_function(dev);
 959                 return 0;
 960         }
 961         pci_dev = dev->pci_dev;
 962
 963         rte_eth_copy_pci_info(dev, pci_dev);
 964
 965         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 966         pf->adapter->eth_dev = dev;
 967         pf->dev_data = dev->data;
 968
 969         hw->back = I40E_PF_TO_ADAPTER(pf);
 970         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 971         if (!hw->hw_addr) {
 972                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 973                              "as address is NULL");
 974                 return -ENODEV;
 975         }
 976
 977         hw->vendor_id = pci_dev->id.vendor_id;
 978         hw->device_id = pci_dev->id.device_id;
 979         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 980         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 981         hw->bus.device = pci_dev->addr.devid;
 982         hw->bus.func = pci_dev->addr.function;
 983         hw->adapter_stopped = 0;
 984
 985         /* Make sure all is clean before doing PF reset */
 986         i40e_clear_hw(hw);
 987
 988         /* Initialize the hardware */
 989         i40e_hw_init(dev);
 990
 991         /* Reset here to make sure all is clean for each PF */
 992         ret = i40e_pf_reset(hw);
 993         if (ret) {
 994                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 995                 return ret;
 996         }
 997
 998         /* Initialize the shared code (base driver) */
 999         ret = i40e_init_shared_code(hw);
1000         if (ret) {
1001                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1002                 return ret;
1003         }
1004
1005         /*
1006          * To work around the NVM issue, initialize registers
1007          * for flexible payload and packet type of QinQ by
1008          * software. It should be removed once issues are fixed
1009          * in NVM.
1010          */
1011         i40e_GLQF_reg_init(hw);
1012
1013         /* Initialize the input set for filters (hash and fd) to default value */
1014         i40e_filter_input_set_init(pf);
1015
1016         /* Initialize the parameters for adminq */
1017         i40e_init_adminq_parameter(hw);
1018         ret = i40e_init_adminq(hw);
1019         if (ret != I40E_SUCCESS) {
1020                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1021                 return -EIO;
1022         }
1023         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1024                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1025                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1026                      ((hw->nvm.version >> 12) & 0xf),
1027                      ((hw->nvm.version >> 4) & 0xff),
1028                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1029
1030         /* Need the special FW version to support floating VEB */
1031         config_floating_veb(dev);
1032         /* Clear PXE mode */
1033         i40e_clear_pxe_mode(hw);
1034         ret = i40e_dev_sync_phy_type(hw);
1035         if (ret) {
1036                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1037                 goto err_sync_phy_type;
1038         }
1039         /*
1040          * On X710, performance number is far from the expectation on recent
1041          * firmware versions. The fix for this issue may not be integrated in
1042          * the following firmware version. So the workaround in software driver
1043          * is needed. It needs to modify the initial values of 3 internal only
1044          * registers. Note that the workaround can be removed when it is fixed
1045          * in firmware in the future.
1046          */
1047         i40e_configure_registers(hw);
1048
1049         /* Get hw capabilities */
1050         ret = i40e_get_cap(hw);
1051         if (ret != I40E_SUCCESS) {
1052                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1053                 goto err_get_capabilities;
1054         }
1055
1056         /* Initialize parameters for PF */
1057         ret = i40e_pf_parameter_init(dev);
1058         if (ret != 0) {
1059                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1060                 goto err_parameter_init;
1061         }
1062
1063         /* Initialize the queue management */
1064         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1065         if (ret < 0) {
1066                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1067                 goto err_qp_pool_init;
1068         }
1069         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1070                                 hw->func_caps.num_msix_vectors - 1);
1071         if (ret < 0) {
1072                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1073                 goto err_msix_pool_init;
1074         }
1075
1076         /* Initialize lan hmc */
1077         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1078                                 hw->func_caps.num_rx_qp, 0, 0);
1079         if (ret != I40E_SUCCESS) {
1080                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1081                 goto err_init_lan_hmc;
1082         }
1083
1084         /* Configure lan hmc */
1085         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1086         if (ret != I40E_SUCCESS) {
1087                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1088                 goto err_configure_lan_hmc;
1089         }
1090
1091         /* Get and check the mac address */
1092         i40e_get_mac_addr(hw, hw->mac.addr);
1093         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1094                 PMD_INIT_LOG(ERR, "mac address is not valid");
1095                 ret = -EIO;
1096                 goto err_get_mac_addr;
1097         }
1098         /* Copy the permanent MAC address */
1099         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1100                         (struct ether_addr *) hw->mac.perm_addr);
1101
1102         /* Disable flow control */
1103         hw->fc.requested_mode = I40E_FC_NONE;
1104         i40e_set_fc(hw, &aq_fail, TRUE);
1105
1106         /* Set the global registers with default ether type value */
1107         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1108         if (ret != I40E_SUCCESS) {
1109                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1110                              "VLAN ether type");
1111                 goto err_setup_pf_switch;
1112         }
1113
1114         /* PF setup, which includes VSI setup */
1115         ret = i40e_pf_setup(pf);
1116         if (ret) {
1117                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1118                 goto err_setup_pf_switch;
1119         }
1120
1121         /* reset all stats of the device, including pf and main vsi */
1122         i40e_dev_stats_reset(dev);
1123
1124         vsi = pf->main_vsi;
1125
1126         /* Disable double vlan by default */
1127         i40e_vsi_config_double_vlan(vsi, FALSE);
1128
1129         /* Disable S-TAG identification when floating_veb is disabled */
1130         if (!pf->floating_veb) {
1131                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1132                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1133                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1134                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1135                 }
1136         }
1137
1138         if (!vsi->max_macaddrs)
1139                 len = ETHER_ADDR_LEN;
1140         else
1141                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1142
1143         /* Should be after VSI initialized */
1144         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1145         if (!dev->data->mac_addrs) {
1146                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1147                                         "for storing mac address");
1148                 goto err_mac_alloc;
1149         }
1150         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1151                                         &dev->data->mac_addrs[0]);
1152
1153         /* initialize pf host driver to setup SRIOV resource if applicable */
1154         i40e_pf_host_init(dev);
1155
1156         /* register callback func to eal lib */
1157         rte_intr_callback_register(&(pci_dev->intr_handle),
1158                 i40e_dev_interrupt_handler, (void *)dev);
1159
1160         /* configure and enable device interrupt */
1161         i40e_pf_config_irq0(hw, TRUE);
1162         i40e_pf_enable_irq0(hw);
1163
1164         /* enable uio intr after callback register */
1165         rte_intr_enable(&(pci_dev->intr_handle));
1166         /*
1167          * Add an ethertype filter to drop all flow control frames transmitted
1168          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1169          * frames to wire.
1170          */
1171         i40e_add_tx_flow_control_drop_filter(pf);
1172
1173         /* Set the max frame size to 0x2600 by default,
1174          * in case other drivers changed the default value.
1175          */
1176         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1177
1178         /* initialize mirror rule list */
1179         TAILQ_INIT(&pf->mirror_list);
1180
1181         /* Init dcb to sw mode by default */
1182         ret = i40e_dcb_init_configure(dev, TRUE);
1183         if (ret != I40E_SUCCESS) {
1184                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1185                 pf->flags &= ~I40E_FLAG_DCB;
1186         }
1187
1188         return 0;
1189
1190 err_mac_alloc:
1191         i40e_vsi_release(pf->main_vsi);
1192 err_setup_pf_switch:
1193 err_get_mac_addr:
1194 err_configure_lan_hmc:
1195         (void)i40e_shutdown_lan_hmc(hw);
1196 err_init_lan_hmc:
1197         i40e_res_pool_destroy(&pf->msix_pool);
1198 err_msix_pool_init:
1199         i40e_res_pool_destroy(&pf->qp_pool);
1200 err_qp_pool_init:
1201 err_parameter_init:
1202 err_get_capabilities:
1203 err_sync_phy_type:
1204         (void)i40e_shutdown_adminq(hw);
1205
1206         return ret;
1207 }
1208
1209 static int
1210 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1211 {
1212         struct rte_pci_device *pci_dev;
1213         struct i40e_hw *hw;
1214         struct i40e_filter_control_settings settings;
1215         int ret;
1216         uint8_t aq_fail = 0;
1217
1218         PMD_INIT_FUNC_TRACE();
1219
1220         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1221                 return 0;
1222
1223         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1224         pci_dev = dev->pci_dev;
1225
1226         if (hw->adapter_stopped == 0)
1227                 i40e_dev_close(dev);
1228
1229         dev->dev_ops = NULL;
1230         dev->rx_pkt_burst = NULL;
1231         dev->tx_pkt_burst = NULL;
1232
1233         /* Clear PXE mode */
1234         i40e_clear_pxe_mode(hw);
1235
1236         /* Unconfigure filter control */
1237         memset(&settings, 0, sizeof(settings));
1238         ret = i40e_set_filter_control(hw, &settings);
1239         if (ret)
1240                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1241                                         ret);
1242
1243         /* Disable flow control */
1244         hw->fc.requested_mode = I40E_FC_NONE;
1245         i40e_set_fc(hw, &aq_fail, TRUE);
1246
1247         /* uninitialize pf host driver */
1248         i40e_pf_host_uninit(dev);
1249
1250         rte_free(dev->data->mac_addrs);
1251         dev->data->mac_addrs = NULL;
1252
1253         /* disable uio intr before callback unregister */
1254         rte_intr_disable(&(pci_dev->intr_handle));
1255
1256         /* register callback func to eal lib */
1257         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1258                 i40e_dev_interrupt_handler, (void *)dev);
1259
1260         return 0;
1261 }
1262
1263 static int
1264 i40e_dev_configure(struct rte_eth_dev *dev)
1265 {
1266         struct i40e_adapter *ad =
1267                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1268         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1269         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1270         int i, ret;
1271
1272         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1273          * bulk allocation or vector Rx preconditions we will reset it.
1274          */
1275         ad->rx_bulk_alloc_allowed = true;
1276         ad->rx_vec_allowed = true;
1277         ad->tx_simple_allowed = true;
1278         ad->tx_vec_allowed = true;
1279
1280         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1281                 ret = i40e_fdir_setup(pf);
1282                 if (ret != I40E_SUCCESS) {
1283                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1284                         return -ENOTSUP;
1285                 }
1286                 ret = i40e_fdir_configure(dev);
1287                 if (ret < 0) {
1288                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1289                         goto err;
1290                 }
1291         } else
1292                 i40e_fdir_teardown(pf);
1293
1294         ret = i40e_dev_init_vlan(dev);
1295         if (ret < 0)
1296                 goto err;
1297
1298         /* VMDQ setup.
1299          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1300          *  RSS setting have different requirements.
1301          *  General PMD driver call sequence are NIC init, configure,
1302          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1303          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1304          *  applicable. So, VMDQ setting has to be done before
1305          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1306          *  For RSS setting, it will try to calculate actual configured RX queue
1307          *  number, which will be available after rx_queue_setup(). dev_start()
1308          *  function is good to place RSS setup.
1309          */
1310         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1311                 ret = i40e_vmdq_setup(dev);
1312                 if (ret)
1313                         goto err;
1314         }
1315
1316         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1317                 ret = i40e_dcb_setup(dev);
1318                 if (ret) {
1319                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1320                         goto err_dcb;
1321                 }
1322         }
1323
1324         return 0;
1325
1326 err_dcb:
1327         /* need to release vmdq resource if exists */
1328         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1329                 i40e_vsi_release(pf->vmdq[i].vsi);
1330                 pf->vmdq[i].vsi = NULL;
1331         }
1332         rte_free(pf->vmdq);
1333         pf->vmdq = NULL;
1334 err:
1335         /* need to release fdir resource if exists */
1336         i40e_fdir_teardown(pf);
1337         return ret;
1338 }
1339
1340 void
1341 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1342 {
1343         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1344         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1345         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1346         uint16_t msix_vect = vsi->msix_intr;
1347         uint16_t i;
1348
1349         for (i = 0; i < vsi->nb_qps; i++) {
1350                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1351                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1352                 rte_wmb();
1353         }
1354
1355         if (vsi->type != I40E_VSI_SRIOV) {
1356                 if (!rte_intr_allow_others(intr_handle)) {
1357                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1358                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1359                         I40E_WRITE_REG(hw,
1360                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1361                                        0);
1362                 } else {
1363                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1364                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1365                         I40E_WRITE_REG(hw,
1366                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1367                                                        msix_vect - 1), 0);
1368                 }
1369         } else {
1370                 uint32_t reg;
1371                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1372                         vsi->user_param + (msix_vect - 1);
1373
1374                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1375                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1376         }
1377         I40E_WRITE_FLUSH(hw);
1378 }
1379
1380 static void
1381 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1382                        int base_queue, int nb_queue)
1383 {
1384         int i;
1385         uint32_t val;
1386         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1387
1388         /* Bind all RX queues to allocated MSIX interrupt */
1389         for (i = 0; i < nb_queue; i++) {
1390                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1391                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1392                         ((base_queue + i + 1) <<
1393                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1394                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1395                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1396
1397                 if (i == nb_queue - 1)
1398                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1399                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1400         }
1401
1402         /* Write first RX queue to Link list register as the head element */
1403         if (vsi->type != I40E_VSI_SRIOV) {
1404                 uint16_t interval =
1405                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1406
1407                 if (msix_vect == I40E_MISC_VEC_ID) {
1408                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1409                                        (base_queue <<
1410                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1411                                        (0x0 <<
1412                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1413                         I40E_WRITE_REG(hw,
1414                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1415                                        interval);
1416                 } else {
1417                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1418                                        (base_queue <<
1419                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1420                                        (0x0 <<
1421                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1422                         I40E_WRITE_REG(hw,
1423                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1424                                                        msix_vect - 1),
1425                                        interval);
1426                 }
1427         } else {
1428                 uint32_t reg;
1429
1430                 if (msix_vect == I40E_MISC_VEC_ID) {
1431                         I40E_WRITE_REG(hw,
1432                                        I40E_VPINT_LNKLST0(vsi->user_param),
1433                                        (base_queue <<
1434                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1435                                        (0x0 <<
1436                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1437                 } else {
1438                         /* num_msix_vectors_vf needs to minus irq0 */
1439                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1440                                 vsi->user_param + (msix_vect - 1);
1441
1442                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1443                                        (base_queue <<
1444                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1445                                        (0x0 <<
1446                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1447                 }
1448         }
1449
1450         I40E_WRITE_FLUSH(hw);
1451 }
1452
1453 void
1454 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1455 {
1456         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1457         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1458         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1459         uint16_t msix_vect = vsi->msix_intr;
1460         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1461         uint16_t queue_idx = 0;
1462         int record = 0;
1463         uint32_t val;
1464         int i;
1465
1466         for (i = 0; i < vsi->nb_qps; i++) {
1467                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1468                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1469         }
1470
1471         /* INTENA flag is not auto-cleared for interrupt */
1472         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1473         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1474                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1475                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1476         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1477
1478         /* VF bind interrupt */
1479         if (vsi->type == I40E_VSI_SRIOV) {
1480                 __vsi_queues_bind_intr(vsi, msix_vect,
1481                                        vsi->base_queue, vsi->nb_qps);
1482                 return;
1483         }
1484
1485         /* PF & VMDq bind interrupt */
1486         if (rte_intr_dp_is_en(intr_handle)) {
1487                 if (vsi->type == I40E_VSI_MAIN) {
1488                         queue_idx = 0;
1489                         record = 1;
1490                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1491                         struct i40e_vsi *main_vsi =
1492                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1493                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1494                         record = 1;
1495                 }
1496         }
1497
1498         for (i = 0; i < vsi->nb_used_qps; i++) {
1499                 if (nb_msix <= 1) {
1500                         if (!rte_intr_allow_others(intr_handle))
1501                                 /* allow to share MISC_VEC_ID */
1502                                 msix_vect = I40E_MISC_VEC_ID;
1503
1504                         /* no enough msix_vect, map all to one */
1505                         __vsi_queues_bind_intr(vsi, msix_vect,
1506                                                vsi->base_queue + i,
1507                                                vsi->nb_used_qps - i);
1508                         for (; !!record && i < vsi->nb_used_qps; i++)
1509                                 intr_handle->intr_vec[queue_idx + i] =
1510                                         msix_vect;
1511                         break;
1512                 }
1513                 /* 1:1 queue/msix_vect mapping */
1514                 __vsi_queues_bind_intr(vsi, msix_vect,
1515                                        vsi->base_queue + i, 1);
1516                 if (!!record)
1517                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1518
1519                 msix_vect++;
1520                 nb_msix--;
1521         }
1522 }
1523
1524 static void
1525 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1526 {
1527         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1528         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1529         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1530         uint16_t interval = i40e_calc_itr_interval(\
1531                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1532         uint16_t msix_intr, i;
1533
1534         if (rte_intr_allow_others(intr_handle))
1535                 for (i = 0; i < vsi->nb_msix; i++) {
1536                         msix_intr = vsi->msix_intr + i;
1537                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1538                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1539                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1540                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1541                                 (interval <<
1542                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1543                 }
1544         else
1545                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1546                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1547                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1548                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1549                                (interval <<
1550                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1551
1552         I40E_WRITE_FLUSH(hw);
1553 }
1554
1555 static void
1556 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1557 {
1558         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1559         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1561         uint16_t msix_intr, i;
1562
1563         if (rte_intr_allow_others(intr_handle))
1564                 for (i = 0; i < vsi->nb_msix; i++) {
1565                         msix_intr = vsi->msix_intr + i;
1566                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1567                                        0);
1568                 }
1569         else
1570                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1571
1572         I40E_WRITE_FLUSH(hw);
1573 }
1574
1575 static inline uint8_t
1576 i40e_parse_link_speeds(uint16_t link_speeds)
1577 {
1578         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1579
1580         if (link_speeds & ETH_LINK_SPEED_40G)
1581                 link_speed |= I40E_LINK_SPEED_40GB;
1582         if (link_speeds & ETH_LINK_SPEED_25G)
1583                 link_speed |= I40E_LINK_SPEED_25GB;
1584         if (link_speeds & ETH_LINK_SPEED_20G)
1585                 link_speed |= I40E_LINK_SPEED_20GB;
1586         if (link_speeds & ETH_LINK_SPEED_10G)
1587                 link_speed |= I40E_LINK_SPEED_10GB;
1588         if (link_speeds & ETH_LINK_SPEED_1G)
1589                 link_speed |= I40E_LINK_SPEED_1GB;
1590         if (link_speeds & ETH_LINK_SPEED_100M)
1591                 link_speed |= I40E_LINK_SPEED_100MB;
1592
1593         return link_speed;
1594 }
1595
1596 static int
1597 i40e_phy_conf_link(struct i40e_hw *hw,
1598                    uint8_t abilities,
1599                    uint8_t force_speed,
1600                    bool is_up)
1601 {
1602         enum i40e_status_code status;
1603         struct i40e_aq_get_phy_abilities_resp phy_ab;
1604         struct i40e_aq_set_phy_config phy_conf;
1605         enum i40e_aq_phy_type cnt;
1606         uint32_t phy_type_mask = 0;
1607
1608         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1609                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1610                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1611                         I40E_AQ_PHY_FLAG_LOW_POWER;
1612         const uint8_t advt = I40E_LINK_SPEED_40GB |
1613                         I40E_LINK_SPEED_25GB |
1614                         I40E_LINK_SPEED_10GB |
1615                         I40E_LINK_SPEED_1GB |
1616                         I40E_LINK_SPEED_100MB;
1617         int ret = -ENOTSUP;
1618
1619
1620         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1621                                               NULL);
1622         if (status)
1623                 return ret;
1624
1625         /* If link already up, no need to set up again */
1626         if (is_up && phy_ab.phy_type != 0)
1627                 return I40E_SUCCESS;
1628
1629         memset(&phy_conf, 0, sizeof(phy_conf));
1630
1631         /* bits 0-2 use the values from get_phy_abilities_resp */
1632         abilities &= ~mask;
1633         abilities |= phy_ab.abilities & mask;
1634
1635         /* update ablities and speed */
1636         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1637                 phy_conf.link_speed = advt;
1638         else
1639                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1640
1641         phy_conf.abilities = abilities;
1642
1643
1644
1645         /* To enable link, phy_type mask needs to include each type */
1646         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1647                 phy_type_mask |= 1 << cnt;
1648
1649         /* use get_phy_abilities_resp value for the rest */
1650         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1651         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1652                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1653                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1654         phy_conf.fec_config = phy_ab.mod_type_ext;
1655         phy_conf.eee_capability = phy_ab.eee_capability;
1656         phy_conf.eeer = phy_ab.eeer_val;
1657         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1658
1659         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1660                     phy_ab.abilities, phy_ab.link_speed);
1661         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1662                     phy_conf.abilities, phy_conf.link_speed);
1663
1664         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1665         if (status)
1666                 return ret;
1667
1668         return I40E_SUCCESS;
1669 }
1670
1671 static int
1672 i40e_apply_link_speed(struct rte_eth_dev *dev)
1673 {
1674         uint8_t speed;
1675         uint8_t abilities = 0;
1676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         struct rte_eth_conf *conf = &dev->data->dev_conf;
1678
1679         speed = i40e_parse_link_speeds(conf->link_speeds);
1680         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1681         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1682                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1683         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1684
1685         return i40e_phy_conf_link(hw, abilities, speed, true);
1686 }
1687
1688 static int
1689 i40e_dev_start(struct rte_eth_dev *dev)
1690 {
1691         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693         struct i40e_vsi *main_vsi = pf->main_vsi;
1694         int ret, i;
1695         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1696         uint32_t intr_vector = 0;
1697
1698         hw->adapter_stopped = 0;
1699
1700         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1701                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1702                              dev->data->port_id);
1703                 return -EINVAL;
1704         }
1705
1706         rte_intr_disable(intr_handle);
1707
1708         if ((rte_intr_cap_multiple(intr_handle) ||
1709              !RTE_ETH_DEV_SRIOV(dev).active) &&
1710             dev->data->dev_conf.intr_conf.rxq != 0) {
1711                 intr_vector = dev->data->nb_rx_queues;
1712                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1713                         return -1;
1714         }
1715
1716         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1717                 intr_handle->intr_vec =
1718                         rte_zmalloc("intr_vec",
1719                                     dev->data->nb_rx_queues * sizeof(int),
1720                                     0);
1721                 if (!intr_handle->intr_vec) {
1722                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1723                                      " intr_vec\n", dev->data->nb_rx_queues);
1724                         return -ENOMEM;
1725                 }
1726         }
1727
1728         /* Initialize VSI */
1729         ret = i40e_dev_rxtx_init(pf);
1730         if (ret != I40E_SUCCESS) {
1731                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1732                 goto err_up;
1733         }
1734
1735         /* Map queues with MSIX interrupt */
1736         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1737                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1738         i40e_vsi_queues_bind_intr(main_vsi);
1739         i40e_vsi_enable_queues_intr(main_vsi);
1740
1741         /* Map VMDQ VSI queues with MSIX interrupt */
1742         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1743                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1744                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1745                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1746         }
1747
1748         /* enable FDIR MSIX interrupt */
1749         if (pf->fdir.fdir_vsi) {
1750                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1751                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1752         }
1753
1754         /* Enable all queues which have been configured */
1755         ret = i40e_dev_switch_queues(pf, TRUE);
1756         if (ret != I40E_SUCCESS) {
1757                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1758                 goto err_up;
1759         }
1760
1761         /* Enable receiving broadcast packets */
1762         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1763         if (ret != I40E_SUCCESS)
1764                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1765
1766         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1767                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1768                                                 true, NULL);
1769                 if (ret != I40E_SUCCESS)
1770                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1771         }
1772
1773         /* Apply link configure */
1774         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1775                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1776                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1777                                 ETH_LINK_SPEED_40G)) {
1778                 PMD_DRV_LOG(ERR, "Invalid link setting");
1779                 goto err_up;
1780         }
1781         ret = i40e_apply_link_speed(dev);
1782         if (I40E_SUCCESS != ret) {
1783                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1784                 goto err_up;
1785         }
1786
1787         if (!rte_intr_allow_others(intr_handle)) {
1788                 rte_intr_callback_unregister(intr_handle,
1789                                              i40e_dev_interrupt_handler,
1790                                              (void *)dev);
1791                 /* configure and enable device interrupt */
1792                 i40e_pf_config_irq0(hw, FALSE);
1793                 i40e_pf_enable_irq0(hw);
1794
1795                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1796                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1797                                      " no intr multiplex\n");
1798         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1799                 ret = i40e_aq_set_phy_int_mask(hw,
1800                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1801                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1802                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1803                 if (ret != I40E_SUCCESS)
1804                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1805
1806                 /* Call get_link_info aq commond to enable LSE */
1807                 i40e_dev_link_update(dev, 0);
1808         }
1809
1810         /* enable uio intr after callback register */
1811         rte_intr_enable(intr_handle);
1812
1813         return I40E_SUCCESS;
1814
1815 err_up:
1816         i40e_dev_switch_queues(pf, FALSE);
1817         i40e_dev_clear_queues(dev);
1818
1819         return ret;
1820 }
1821
1822 static void
1823 i40e_dev_stop(struct rte_eth_dev *dev)
1824 {
1825         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1826         struct i40e_vsi *main_vsi = pf->main_vsi;
1827         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1828         int i;
1829
1830         /* Disable all queues */
1831         i40e_dev_switch_queues(pf, FALSE);
1832
1833         /* un-map queues with interrupt registers */
1834         i40e_vsi_disable_queues_intr(main_vsi);
1835         i40e_vsi_queues_unbind_intr(main_vsi);
1836
1837         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1838                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1839                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1840         }
1841
1842         if (pf->fdir.fdir_vsi) {
1843                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1844                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1845         }
1846         /* Clear all queues and release memory */
1847         i40e_dev_clear_queues(dev);
1848
1849         /* Set link down */
1850         i40e_dev_set_link_down(dev);
1851
1852         if (!rte_intr_allow_others(intr_handle))
1853                 /* resume to the default handler */
1854                 rte_intr_callback_register(intr_handle,
1855                                            i40e_dev_interrupt_handler,
1856                                            (void *)dev);
1857
1858         /* Clean datapath event and queue/vec mapping */
1859         rte_intr_efd_disable(intr_handle);
1860         if (intr_handle->intr_vec) {
1861                 rte_free(intr_handle->intr_vec);
1862                 intr_handle->intr_vec = NULL;
1863         }
1864 }
1865
1866 static void
1867 i40e_dev_close(struct rte_eth_dev *dev)
1868 {
1869         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         struct i40e_mirror_rule *p_mirror;
1872         uint32_t reg;
1873         int i;
1874         int ret;
1875
1876         PMD_INIT_FUNC_TRACE();
1877
1878         i40e_dev_stop(dev);
1879         hw->adapter_stopped = 1;
1880
1881         /* Remove all mirror rules */
1882         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1883                 ret = i40e_aq_del_mirror_rule(hw,
1884                                               pf->main_vsi->veb->seid,
1885                                               p_mirror->rule_type,
1886                                               p_mirror->entries,
1887                                               p_mirror->num_entries,
1888                                               p_mirror->id);
1889                 if (ret < 0)
1890                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
1891                                     "status = %d, aq_err = %d.", ret,
1892                                     hw->aq.asq_last_status);
1893
1894                 /* remove mirror software resource anyway */
1895                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1896                 rte_free(p_mirror);
1897                 pf->nb_mirror_rule--;
1898         }
1899
1900         i40e_dev_free_queues(dev);
1901
1902         /* Disable interrupt */
1903         i40e_pf_disable_irq0(hw);
1904         rte_intr_disable(&(dev->pci_dev->intr_handle));
1905
1906         /* shutdown and destroy the HMC */
1907         i40e_shutdown_lan_hmc(hw);
1908
1909         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1910                 i40e_vsi_release(pf->vmdq[i].vsi);
1911                 pf->vmdq[i].vsi = NULL;
1912         }
1913         rte_free(pf->vmdq);
1914         pf->vmdq = NULL;
1915
1916         /* release all the existing VSIs and VEBs */
1917         i40e_fdir_teardown(pf);
1918         i40e_vsi_release(pf->main_vsi);
1919
1920         /* shutdown the adminq */
1921         i40e_aq_queue_shutdown(hw, true);
1922         i40e_shutdown_adminq(hw);
1923
1924         i40e_res_pool_destroy(&pf->qp_pool);
1925         i40e_res_pool_destroy(&pf->msix_pool);
1926
1927         /* force a PF reset to clean anything leftover */
1928         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1929         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1930                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1931         I40E_WRITE_FLUSH(hw);
1932 }
1933
1934 static void
1935 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1936 {
1937         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct i40e_vsi *vsi = pf->main_vsi;
1940         int status;
1941
1942         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1943                                                      true, NULL, true);
1944         if (status != I40E_SUCCESS)
1945                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1946
1947         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1948                                                         TRUE, NULL);
1949         if (status != I40E_SUCCESS)
1950                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1951
1952 }
1953
1954 static void
1955 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1956 {
1957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1958         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         struct i40e_vsi *vsi = pf->main_vsi;
1960         int status;
1961
1962         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1963                                                      false, NULL, true);
1964         if (status != I40E_SUCCESS)
1965                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1966
1967         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1968                                                         false, NULL);
1969         if (status != I40E_SUCCESS)
1970                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1971 }
1972
1973 static void
1974 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1975 {
1976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978         struct i40e_vsi *vsi = pf->main_vsi;
1979         int ret;
1980
1981         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1982         if (ret != I40E_SUCCESS)
1983                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1984 }
1985
1986 static void
1987 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1988 {
1989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         struct i40e_vsi *vsi = pf->main_vsi;
1992         int ret;
1993
1994         if (dev->data->promiscuous == 1)
1995                 return; /* must remain in all_multicast mode */
1996
1997         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1998                                 vsi->seid, FALSE, NULL);
1999         if (ret != I40E_SUCCESS)
2000                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2001 }
2002
2003 /*
2004  * Set device link up.
2005  */
2006 static int
2007 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2008 {
2009         /* re-apply link speed setting */
2010         return i40e_apply_link_speed(dev);
2011 }
2012
2013 /*
2014  * Set device link down.
2015  */
2016 static int
2017 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2018 {
2019         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2020         uint8_t abilities = 0;
2021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022
2023         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2024         return i40e_phy_conf_link(hw, abilities, speed, false);
2025 }
2026
2027 int
2028 i40e_dev_link_update(struct rte_eth_dev *dev,
2029                      int wait_to_complete)
2030 {
2031 #define CHECK_INTERVAL 100  /* 100ms */
2032 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2033         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2034         struct i40e_link_status link_status;
2035         struct rte_eth_link link, old;
2036         int status;
2037         unsigned rep_cnt = MAX_REPEAT_TIME;
2038         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2039
2040         memset(&link, 0, sizeof(link));
2041         memset(&old, 0, sizeof(old));
2042         memset(&link_status, 0, sizeof(link_status));
2043         rte_i40e_dev_atomic_read_link_status(dev, &old);
2044
2045         do {
2046                 /* Get link status information from hardware */
2047                 status = i40e_aq_get_link_info(hw, enable_lse,
2048                                                 &link_status, NULL);
2049                 if (status != I40E_SUCCESS) {
2050                         link.link_speed = ETH_SPEED_NUM_100M;
2051                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2052                         PMD_DRV_LOG(ERR, "Failed to get link info");
2053                         goto out;
2054                 }
2055
2056                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2057                 if (!wait_to_complete || link.link_status)
2058                         break;
2059
2060                 rte_delay_ms(CHECK_INTERVAL);
2061         } while (--rep_cnt);
2062
2063         if (!link.link_status)
2064                 goto out;
2065
2066         /* i40e uses full duplex only */
2067         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2068
2069         /* Parse the link status */
2070         switch (link_status.link_speed) {
2071         case I40E_LINK_SPEED_100MB:
2072                 link.link_speed = ETH_SPEED_NUM_100M;
2073                 break;
2074         case I40E_LINK_SPEED_1GB:
2075                 link.link_speed = ETH_SPEED_NUM_1G;
2076                 break;
2077         case I40E_LINK_SPEED_10GB:
2078                 link.link_speed = ETH_SPEED_NUM_10G;
2079                 break;
2080         case I40E_LINK_SPEED_20GB:
2081                 link.link_speed = ETH_SPEED_NUM_20G;
2082                 break;
2083         case I40E_LINK_SPEED_25GB:
2084                 link.link_speed = ETH_SPEED_NUM_25G;
2085                 break;
2086         case I40E_LINK_SPEED_40GB:
2087                 link.link_speed = ETH_SPEED_NUM_40G;
2088                 break;
2089         default:
2090                 link.link_speed = ETH_SPEED_NUM_100M;
2091                 break;
2092         }
2093
2094         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2095                         ETH_LINK_SPEED_FIXED);
2096
2097 out:
2098         rte_i40e_dev_atomic_write_link_status(dev, &link);
2099         if (link.link_status == old.link_status)
2100                 return -1;
2101
2102         i40e_notify_all_vfs_link_status(dev);
2103
2104         return 0;
2105 }
2106
2107 /* Get all the statistics of a VSI */
2108 void
2109 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2110 {
2111         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2112         struct i40e_eth_stats *nes = &vsi->eth_stats;
2113         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2114         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2115
2116         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2117                             vsi->offset_loaded, &oes->rx_bytes,
2118                             &nes->rx_bytes);
2119         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2120                             vsi->offset_loaded, &oes->rx_unicast,
2121                             &nes->rx_unicast);
2122         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2123                             vsi->offset_loaded, &oes->rx_multicast,
2124                             &nes->rx_multicast);
2125         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2126                             vsi->offset_loaded, &oes->rx_broadcast,
2127                             &nes->rx_broadcast);
2128         /* exclude CRC bytes */
2129         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2130                 nes->rx_broadcast) * ETHER_CRC_LEN;
2131
2132         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2133                             &oes->rx_discards, &nes->rx_discards);
2134         /* GLV_REPC not supported */
2135         /* GLV_RMPC not supported */
2136         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2137                             &oes->rx_unknown_protocol,
2138                             &nes->rx_unknown_protocol);
2139         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2140                             vsi->offset_loaded, &oes->tx_bytes,
2141                             &nes->tx_bytes);
2142         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2143                             vsi->offset_loaded, &oes->tx_unicast,
2144                             &nes->tx_unicast);
2145         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2146                             vsi->offset_loaded, &oes->tx_multicast,
2147                             &nes->tx_multicast);
2148         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2149                             vsi->offset_loaded,  &oes->tx_broadcast,
2150                             &nes->tx_broadcast);
2151         /* exclude CRC bytes */
2152         nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2153                 nes->tx_broadcast) * ETHER_CRC_LEN;
2154         /* GLV_TDPC not supported */
2155         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2156                             &oes->tx_errors, &nes->tx_errors);
2157         vsi->offset_loaded = true;
2158
2159         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2160                     vsi->vsi_id);
2161         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2162         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2163         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2164         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2165         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2166         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2167                     nes->rx_unknown_protocol);
2168         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2169         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2170         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2171         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2172         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2173         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2174         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2175                     vsi->vsi_id);
2176 }
2177
2178 static void
2179 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2180 {
2181         unsigned int i;
2182         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2183         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2184
2185         /* Get rx/tx bytes of internal transfer packets */
2186         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2187                         I40E_GLV_GORCL(hw->port),
2188                         pf->offset_loaded,
2189                         &pf->internal_rx_bytes_offset,
2190                         &pf->internal_rx_bytes);
2191
2192         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2193                         I40E_GLV_GOTCL(hw->port),
2194                         pf->offset_loaded,
2195                         &pf->internal_tx_bytes_offset,
2196                         &pf->internal_tx_bytes);
2197
2198         /* Get statistics of struct i40e_eth_stats */
2199         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2200                             I40E_GLPRT_GORCL(hw->port),
2201                             pf->offset_loaded, &os->eth.rx_bytes,
2202                             &ns->eth.rx_bytes);
2203         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2204                             I40E_GLPRT_UPRCL(hw->port),
2205                             pf->offset_loaded, &os->eth.rx_unicast,
2206                             &ns->eth.rx_unicast);
2207         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2208                             I40E_GLPRT_MPRCL(hw->port),
2209                             pf->offset_loaded, &os->eth.rx_multicast,
2210                             &ns->eth.rx_multicast);
2211         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2212                             I40E_GLPRT_BPRCL(hw->port),
2213                             pf->offset_loaded, &os->eth.rx_broadcast,
2214                             &ns->eth.rx_broadcast);
2215         /* Workaround: CRC size should not be included in byte statistics,
2216          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2217          */
2218         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2219                 ns->eth.rx_broadcast) * ETHER_CRC_LEN + pf->internal_rx_bytes;
2220
2221         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2222                             pf->offset_loaded, &os->eth.rx_discards,
2223                             &ns->eth.rx_discards);
2224         /* GLPRT_REPC not supported */
2225         /* GLPRT_RMPC not supported */
2226         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2227                             pf->offset_loaded,
2228                             &os->eth.rx_unknown_protocol,
2229                             &ns->eth.rx_unknown_protocol);
2230         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2231                             I40E_GLPRT_GOTCL(hw->port),
2232                             pf->offset_loaded, &os->eth.tx_bytes,
2233                             &ns->eth.tx_bytes);
2234         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2235                             I40E_GLPRT_UPTCL(hw->port),
2236                             pf->offset_loaded, &os->eth.tx_unicast,
2237                             &ns->eth.tx_unicast);
2238         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2239                             I40E_GLPRT_MPTCL(hw->port),
2240                             pf->offset_loaded, &os->eth.tx_multicast,
2241                             &ns->eth.tx_multicast);
2242         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2243                             I40E_GLPRT_BPTCL(hw->port),
2244                             pf->offset_loaded, &os->eth.tx_broadcast,
2245                             &ns->eth.tx_broadcast);
2246         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2247                 ns->eth.tx_broadcast) * ETHER_CRC_LEN + pf->internal_tx_bytes;
2248         /* GLPRT_TEPC not supported */
2249
2250         /* additional port specific stats */
2251         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2252                             pf->offset_loaded, &os->tx_dropped_link_down,
2253                             &ns->tx_dropped_link_down);
2254         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2255                             pf->offset_loaded, &os->crc_errors,
2256                             &ns->crc_errors);
2257         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2258                             pf->offset_loaded, &os->illegal_bytes,
2259                             &ns->illegal_bytes);
2260         /* GLPRT_ERRBC not supported */
2261         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2262                             pf->offset_loaded, &os->mac_local_faults,
2263                             &ns->mac_local_faults);
2264         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2265                             pf->offset_loaded, &os->mac_remote_faults,
2266                             &ns->mac_remote_faults);
2267         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2268                             pf->offset_loaded, &os->rx_length_errors,
2269                             &ns->rx_length_errors);
2270         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2271                             pf->offset_loaded, &os->link_xon_rx,
2272                             &ns->link_xon_rx);
2273         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2274                             pf->offset_loaded, &os->link_xoff_rx,
2275                             &ns->link_xoff_rx);
2276         for (i = 0; i < 8; i++) {
2277                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2278                                     pf->offset_loaded,
2279                                     &os->priority_xon_rx[i],
2280                                     &ns->priority_xon_rx[i]);
2281                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2282                                     pf->offset_loaded,
2283                                     &os->priority_xoff_rx[i],
2284                                     &ns->priority_xoff_rx[i]);
2285         }
2286         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2287                             pf->offset_loaded, &os->link_xon_tx,
2288                             &ns->link_xon_tx);
2289         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2290                             pf->offset_loaded, &os->link_xoff_tx,
2291                             &ns->link_xoff_tx);
2292         for (i = 0; i < 8; i++) {
2293                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2294                                     pf->offset_loaded,
2295                                     &os->priority_xon_tx[i],
2296                                     &ns->priority_xon_tx[i]);
2297                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2298                                     pf->offset_loaded,
2299                                     &os->priority_xoff_tx[i],
2300                                     &ns->priority_xoff_tx[i]);
2301                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2302                                     pf->offset_loaded,
2303                                     &os->priority_xon_2_xoff[i],
2304                                     &ns->priority_xon_2_xoff[i]);
2305         }
2306         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2307                             I40E_GLPRT_PRC64L(hw->port),
2308                             pf->offset_loaded, &os->rx_size_64,
2309                             &ns->rx_size_64);
2310         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2311                             I40E_GLPRT_PRC127L(hw->port),
2312                             pf->offset_loaded, &os->rx_size_127,
2313                             &ns->rx_size_127);
2314         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2315                             I40E_GLPRT_PRC255L(hw->port),
2316                             pf->offset_loaded, &os->rx_size_255,
2317                             &ns->rx_size_255);
2318         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2319                             I40E_GLPRT_PRC511L(hw->port),
2320                             pf->offset_loaded, &os->rx_size_511,
2321                             &ns->rx_size_511);
2322         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2323                             I40E_GLPRT_PRC1023L(hw->port),
2324                             pf->offset_loaded, &os->rx_size_1023,
2325                             &ns->rx_size_1023);
2326         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2327                             I40E_GLPRT_PRC1522L(hw->port),
2328                             pf->offset_loaded, &os->rx_size_1522,
2329                             &ns->rx_size_1522);
2330         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2331                             I40E_GLPRT_PRC9522L(hw->port),
2332                             pf->offset_loaded, &os->rx_size_big,
2333                             &ns->rx_size_big);
2334         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2335                             pf->offset_loaded, &os->rx_undersize,
2336                             &ns->rx_undersize);
2337         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2338                             pf->offset_loaded, &os->rx_fragments,
2339                             &ns->rx_fragments);
2340         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2341                             pf->offset_loaded, &os->rx_oversize,
2342                             &ns->rx_oversize);
2343         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2344                             pf->offset_loaded, &os->rx_jabber,
2345                             &ns->rx_jabber);
2346         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2347                             I40E_GLPRT_PTC64L(hw->port),
2348                             pf->offset_loaded, &os->tx_size_64,
2349                             &ns->tx_size_64);
2350         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2351                             I40E_GLPRT_PTC127L(hw->port),
2352                             pf->offset_loaded, &os->tx_size_127,
2353                             &ns->tx_size_127);
2354         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2355                             I40E_GLPRT_PTC255L(hw->port),
2356                             pf->offset_loaded, &os->tx_size_255,
2357                             &ns->tx_size_255);
2358         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2359                             I40E_GLPRT_PTC511L(hw->port),
2360                             pf->offset_loaded, &os->tx_size_511,
2361                             &ns->tx_size_511);
2362         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2363                             I40E_GLPRT_PTC1023L(hw->port),
2364                             pf->offset_loaded, &os->tx_size_1023,
2365                             &ns->tx_size_1023);
2366         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2367                             I40E_GLPRT_PTC1522L(hw->port),
2368                             pf->offset_loaded, &os->tx_size_1522,
2369                             &ns->tx_size_1522);
2370         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2371                             I40E_GLPRT_PTC9522L(hw->port),
2372                             pf->offset_loaded, &os->tx_size_big,
2373                             &ns->tx_size_big);
2374         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2375                            pf->offset_loaded,
2376                            &os->fd_sb_match, &ns->fd_sb_match);
2377         /* GLPRT_MSPDC not supported */
2378         /* GLPRT_XEC not supported */
2379
2380         pf->offset_loaded = true;
2381
2382         if (pf->main_vsi)
2383                 i40e_update_vsi_stats(pf->main_vsi);
2384 }
2385
2386 /* Get all statistics of a port */
2387 static void
2388 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2389 {
2390         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2393         unsigned i;
2394
2395         /* call read registers - updates values, now write them to struct */
2396         i40e_read_stats_registers(pf, hw);
2397
2398         stats->ipackets = ns->eth.rx_unicast +
2399                         ns->eth.rx_multicast +
2400                         ns->eth.rx_broadcast -
2401                         ns->eth.rx_discards -
2402                         pf->main_vsi->eth_stats.rx_discards;
2403         stats->opackets = ns->eth.tx_unicast +
2404                         ns->eth.tx_multicast +
2405                         ns->eth.tx_broadcast;
2406         stats->ibytes   = ns->eth.rx_bytes;
2407         stats->obytes   = ns->eth.tx_bytes;
2408         stats->oerrors  = ns->eth.tx_errors +
2409                         pf->main_vsi->eth_stats.tx_errors;
2410
2411         /* Rx Errors */
2412         stats->imissed  = ns->eth.rx_discards +
2413                         pf->main_vsi->eth_stats.rx_discards;
2414         stats->ierrors  = ns->crc_errors +
2415                         ns->rx_length_errors + ns->rx_undersize +
2416                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2417
2418         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2419         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2420         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2421         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2422         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2423         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2424         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2425                     ns->eth.rx_unknown_protocol);
2426         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2427         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2428         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2429         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2430         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2431         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2432
2433         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2434                     ns->tx_dropped_link_down);
2435         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2436         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2437                     ns->illegal_bytes);
2438         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2439         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2440                     ns->mac_local_faults);
2441         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2442                     ns->mac_remote_faults);
2443         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2444                     ns->rx_length_errors);
2445         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2446         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2447         for (i = 0; i < 8; i++) {
2448                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2449                                 i, ns->priority_xon_rx[i]);
2450                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2451                                 i, ns->priority_xoff_rx[i]);
2452         }
2453         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2454         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2455         for (i = 0; i < 8; i++) {
2456                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2457                                 i, ns->priority_xon_tx[i]);
2458                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2459                                 i, ns->priority_xoff_tx[i]);
2460                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2461                                 i, ns->priority_xon_2_xoff[i]);
2462         }
2463         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2464         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2465         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2466         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2467         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2468         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2469         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2470         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2471         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2472         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2473         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2474         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2475         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2476         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2477         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2478         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2479         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2480         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2481         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2482                         ns->mac_short_packet_dropped);
2483         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2484                     ns->checksum_error);
2485         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2486         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2487 }
2488
2489 /* Reset the statistics */
2490 static void
2491 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2492 {
2493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495
2496         /* Mark PF and VSI stats to update the offset, aka "reset" */
2497         pf->offset_loaded = false;
2498         if (pf->main_vsi)
2499                 pf->main_vsi->offset_loaded = false;
2500
2501         /* read the stats, reading current register values into offset */
2502         i40e_read_stats_registers(pf, hw);
2503 }
2504
2505 static uint32_t
2506 i40e_xstats_calc_num(void)
2507 {
2508         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2509                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2510                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2511 }
2512
2513 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2514                                      struct rte_eth_xstat_name *xstats_names,
2515                                      __rte_unused unsigned limit)
2516 {
2517         unsigned count = 0;
2518         unsigned i, prio;
2519
2520         if (xstats_names == NULL)
2521                 return i40e_xstats_calc_num();
2522
2523         /* Note: limit checked in rte_eth_xstats_names() */
2524
2525         /* Get stats from i40e_eth_stats struct */
2526         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2527                 snprintf(xstats_names[count].name,
2528                          sizeof(xstats_names[count].name),
2529                          "%s", rte_i40e_stats_strings[i].name);
2530                 count++;
2531         }
2532
2533         /* Get individiual stats from i40e_hw_port struct */
2534         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2535                 snprintf(xstats_names[count].name,
2536                         sizeof(xstats_names[count].name),
2537                          "%s", rte_i40e_hw_port_strings[i].name);
2538                 count++;
2539         }
2540
2541         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2542                 for (prio = 0; prio < 8; prio++) {
2543                         snprintf(xstats_names[count].name,
2544                                  sizeof(xstats_names[count].name),
2545                                  "rx_priority%u_%s", prio,
2546                                  rte_i40e_rxq_prio_strings[i].name);
2547                         count++;
2548                 }
2549         }
2550
2551         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2552                 for (prio = 0; prio < 8; prio++) {
2553                         snprintf(xstats_names[count].name,
2554                                  sizeof(xstats_names[count].name),
2555                                  "tx_priority%u_%s", prio,
2556                                  rte_i40e_txq_prio_strings[i].name);
2557                         count++;
2558                 }
2559         }
2560         return count;
2561 }
2562
2563 static int
2564 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2565                     unsigned n)
2566 {
2567         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2568         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569         unsigned i, count, prio;
2570         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2571
2572         count = i40e_xstats_calc_num();
2573         if (n < count)
2574                 return count;
2575
2576         i40e_read_stats_registers(pf, hw);
2577
2578         if (xstats == NULL)
2579                 return 0;
2580
2581         count = 0;
2582
2583         /* Get stats from i40e_eth_stats struct */
2584         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2585                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2586                         rte_i40e_stats_strings[i].offset);
2587                 xstats[count].id = count;
2588                 count++;
2589         }
2590
2591         /* Get individiual stats from i40e_hw_port struct */
2592         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2593                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2594                         rte_i40e_hw_port_strings[i].offset);
2595                 xstats[count].id = count;
2596                 count++;
2597         }
2598
2599         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2600                 for (prio = 0; prio < 8; prio++) {
2601                         xstats[count].value =
2602                                 *(uint64_t *)(((char *)hw_stats) +
2603                                 rte_i40e_rxq_prio_strings[i].offset +
2604                                 (sizeof(uint64_t) * prio));
2605                         xstats[count].id = count;
2606                         count++;
2607                 }
2608         }
2609
2610         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2611                 for (prio = 0; prio < 8; prio++) {
2612                         xstats[count].value =
2613                                 *(uint64_t *)(((char *)hw_stats) +
2614                                 rte_i40e_txq_prio_strings[i].offset +
2615                                 (sizeof(uint64_t) * prio));
2616                         xstats[count].id = count;
2617                         count++;
2618                 }
2619         }
2620
2621         return count;
2622 }
2623
2624 static int
2625 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2626                                  __rte_unused uint16_t queue_id,
2627                                  __rte_unused uint8_t stat_idx,
2628                                  __rte_unused uint8_t is_rx)
2629 {
2630         PMD_INIT_FUNC_TRACE();
2631
2632         return -ENOSYS;
2633 }
2634
2635 static void
2636 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2637 {
2638         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         struct i40e_vsi *vsi = pf->main_vsi;
2641
2642         dev_info->max_rx_queues = vsi->nb_qps;
2643         dev_info->max_tx_queues = vsi->nb_qps;
2644         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2645         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2646         dev_info->max_mac_addrs = vsi->max_macaddrs;
2647         dev_info->max_vfs = dev->pci_dev->max_vfs;
2648         dev_info->rx_offload_capa =
2649                 DEV_RX_OFFLOAD_VLAN_STRIP |
2650                 DEV_RX_OFFLOAD_QINQ_STRIP |
2651                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2652                 DEV_RX_OFFLOAD_UDP_CKSUM |
2653                 DEV_RX_OFFLOAD_TCP_CKSUM;
2654         dev_info->tx_offload_capa =
2655                 DEV_TX_OFFLOAD_VLAN_INSERT |
2656                 DEV_TX_OFFLOAD_QINQ_INSERT |
2657                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2658                 DEV_TX_OFFLOAD_UDP_CKSUM |
2659                 DEV_TX_OFFLOAD_TCP_CKSUM |
2660                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2661                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2662                 DEV_TX_OFFLOAD_TCP_TSO |
2663                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2664                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2665                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2666                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2667         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2668                                                 sizeof(uint32_t);
2669         dev_info->reta_size = pf->hash_lut_size;
2670         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2671
2672         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2673                 .rx_thresh = {
2674                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2675                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2676                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2677                 },
2678                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2679                 .rx_drop_en = 0,
2680         };
2681
2682         dev_info->default_txconf = (struct rte_eth_txconf) {
2683                 .tx_thresh = {
2684                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2685                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2686                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2687                 },
2688                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2689                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2690                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2691                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2692         };
2693
2694         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2695                 .nb_max = I40E_MAX_RING_DESC,
2696                 .nb_min = I40E_MIN_RING_DESC,
2697                 .nb_align = I40E_ALIGN_RING_DESC,
2698         };
2699
2700         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2701                 .nb_max = I40E_MAX_RING_DESC,
2702                 .nb_min = I40E_MIN_RING_DESC,
2703                 .nb_align = I40E_ALIGN_RING_DESC,
2704         };
2705
2706         if (pf->flags & I40E_FLAG_VMDQ) {
2707                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2708                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2709                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2710                                                 pf->max_nb_vmdq_vsi;
2711                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2712                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2713                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2714         }
2715
2716         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2717                 /* For XL710 */
2718                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2719         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2720                 /* For XXV710 */
2721                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2722         else
2723                 /* For X710 */
2724                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2725 }
2726
2727 static int
2728 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2729 {
2730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2731         struct i40e_vsi *vsi = pf->main_vsi;
2732         PMD_INIT_FUNC_TRACE();
2733
2734         if (on)
2735                 return i40e_vsi_add_vlan(vsi, vlan_id);
2736         else
2737                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2738 }
2739
2740 static int
2741 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2742                    enum rte_vlan_type vlan_type,
2743                    uint16_t tpid)
2744 {
2745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746         uint64_t reg_r = 0, reg_w = 0;
2747         uint16_t reg_id = 0;
2748         int ret = 0;
2749         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2750
2751         switch (vlan_type) {
2752         case ETH_VLAN_TYPE_OUTER:
2753                 if (qinq)
2754                         reg_id = 2;
2755                 else
2756                         reg_id = 3;
2757                 break;
2758         case ETH_VLAN_TYPE_INNER:
2759                 if (qinq)
2760                         reg_id = 3;
2761                 else {
2762                         ret = -EINVAL;
2763                         PMD_DRV_LOG(ERR,
2764                                 "Unsupported vlan type in single vlan.\n");
2765                         return ret;
2766                 }
2767                 break;
2768         default:
2769                 ret = -EINVAL;
2770                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2771                 return ret;
2772         }
2773         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2774                                           &reg_r, NULL);
2775         if (ret != I40E_SUCCESS) {
2776                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2777                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2778                 ret = -EIO;
2779                 return ret;
2780         }
2781         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2782                     "0x%08"PRIx64"", reg_id, reg_r);
2783
2784         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2785         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2786         if (reg_r == reg_w) {
2787                 ret = 0;
2788                 PMD_DRV_LOG(DEBUG, "No need to write");
2789                 return ret;
2790         }
2791
2792         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2793                                            reg_w, NULL);
2794         if (ret != I40E_SUCCESS) {
2795                 ret = -EIO;
2796                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2797                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2798                 return ret;
2799         }
2800         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2801                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2802
2803         return ret;
2804 }
2805
2806 static void
2807 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2808 {
2809         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2810         struct i40e_vsi *vsi = pf->main_vsi;
2811
2812         if (mask & ETH_VLAN_FILTER_MASK) {
2813                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2814                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2815                 else
2816                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2817         }
2818
2819         if (mask & ETH_VLAN_STRIP_MASK) {
2820                 /* Enable or disable VLAN stripping */
2821                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2822                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2823                 else
2824                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2825         }
2826
2827         if (mask & ETH_VLAN_EXTEND_MASK) {
2828                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2829                         i40e_vsi_config_double_vlan(vsi, TRUE);
2830                         /* Set global registers with default ether type value */
2831                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2832                                            ETHER_TYPE_VLAN);
2833                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2834                                            ETHER_TYPE_VLAN);
2835                 }
2836                 else
2837                         i40e_vsi_config_double_vlan(vsi, FALSE);
2838         }
2839 }
2840
2841 static void
2842 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2843                           __rte_unused uint16_t queue,
2844                           __rte_unused int on)
2845 {
2846         PMD_INIT_FUNC_TRACE();
2847 }
2848
2849 static int
2850 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2851 {
2852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2853         struct i40e_vsi *vsi = pf->main_vsi;
2854         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2855         struct i40e_vsi_vlan_pvid_info info;
2856
2857         memset(&info, 0, sizeof(info));
2858         info.on = on;
2859         if (info.on)
2860                 info.config.pvid = pvid;
2861         else {
2862                 info.config.reject.tagged =
2863                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2864                 info.config.reject.untagged =
2865                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2866         }
2867
2868         return i40e_vsi_vlan_pvid_set(vsi, &info);
2869 }
2870
2871 static int
2872 i40e_dev_led_on(struct rte_eth_dev *dev)
2873 {
2874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2875         uint32_t mode = i40e_led_get(hw);
2876
2877         if (mode == 0)
2878                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2879
2880         return 0;
2881 }
2882
2883 static int
2884 i40e_dev_led_off(struct rte_eth_dev *dev)
2885 {
2886         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2887         uint32_t mode = i40e_led_get(hw);
2888
2889         if (mode != 0)
2890                 i40e_led_set(hw, 0, false);
2891
2892         return 0;
2893 }
2894
2895 static int
2896 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2897 {
2898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2900
2901         fc_conf->pause_time = pf->fc_conf.pause_time;
2902
2903         /* read out from register, in case they are modified by other port */
2904         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
2905                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
2906         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
2907                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
2908
2909         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2910         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2911
2912          /* Return current mode according to actual setting*/
2913         switch (hw->fc.current_mode) {
2914         case I40E_FC_FULL:
2915                 fc_conf->mode = RTE_FC_FULL;
2916                 break;
2917         case I40E_FC_TX_PAUSE:
2918                 fc_conf->mode = RTE_FC_TX_PAUSE;
2919                 break;
2920         case I40E_FC_RX_PAUSE:
2921                 fc_conf->mode = RTE_FC_RX_PAUSE;
2922                 break;
2923         case I40E_FC_NONE:
2924         default:
2925                 fc_conf->mode = RTE_FC_NONE;
2926         };
2927
2928         return 0;
2929 }
2930
2931 static int
2932 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2933 {
2934         uint32_t mflcn_reg, fctrl_reg, reg;
2935         uint32_t max_high_water;
2936         uint8_t i, aq_failure;
2937         int err;
2938         struct i40e_hw *hw;
2939         struct i40e_pf *pf;
2940         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2941                 [RTE_FC_NONE] = I40E_FC_NONE,
2942                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2943                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2944                 [RTE_FC_FULL] = I40E_FC_FULL
2945         };
2946
2947         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2948
2949         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2950         if ((fc_conf->high_water > max_high_water) ||
2951                         (fc_conf->high_water < fc_conf->low_water)) {
2952                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2953                         "High_water must <= %d.", max_high_water);
2954                 return -EINVAL;
2955         }
2956
2957         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2958         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2959         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2960
2961         pf->fc_conf.pause_time = fc_conf->pause_time;
2962         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2963         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2964
2965         PMD_INIT_FUNC_TRACE();
2966
2967         /* All the link flow control related enable/disable register
2968          * configuration is handle by the F/W
2969          */
2970         err = i40e_set_fc(hw, &aq_failure, true);
2971         if (err < 0)
2972                 return -ENOSYS;
2973
2974         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2975                 /* Configure flow control refresh threshold,
2976                  * the value for stat_tx_pause_refresh_timer[8]
2977                  * is used for global pause operation.
2978                  */
2979
2980                 I40E_WRITE_REG(hw,
2981                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2982                                pf->fc_conf.pause_time);
2983
2984                 /* configure the timer value included in transmitted pause
2985                  * frame,
2986                  * the value for stat_tx_pause_quanta[8] is used for global
2987                  * pause operation
2988                  */
2989                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2990                                pf->fc_conf.pause_time);
2991
2992                 fctrl_reg = I40E_READ_REG(hw,
2993                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2994
2995                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2996                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2997                 else
2998                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2999
3000                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3001                                fctrl_reg);
3002         } else {
3003                 /* Configure pause time (2 TCs per register) */
3004                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3005                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3006                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3007
3008                 /* Configure flow control refresh threshold value */
3009                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3010                                pf->fc_conf.pause_time / 2);
3011
3012                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3013
3014                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3015                  *depending on configuration
3016                  */
3017                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3018                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3019                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3020                 } else {
3021                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3022                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3023                 }
3024
3025                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3026         }
3027
3028         /* config the water marker both based on the packets and bytes */
3029         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3030                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3031                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3032         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3033                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3034                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3035         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3036                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3037                        << I40E_KILOSHIFT);
3038         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3039                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3040                        << I40E_KILOSHIFT);
3041
3042         I40E_WRITE_FLUSH(hw);
3043
3044         return 0;
3045 }
3046
3047 static int
3048 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3049                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3050 {
3051         PMD_INIT_FUNC_TRACE();
3052
3053         return -ENOSYS;
3054 }
3055
3056 /* Add a MAC address, and update filters */
3057 static void
3058 i40e_macaddr_add(struct rte_eth_dev *dev,
3059                  struct ether_addr *mac_addr,
3060                  __rte_unused uint32_t index,
3061                  uint32_t pool)
3062 {
3063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3064         struct i40e_mac_filter_info mac_filter;
3065         struct i40e_vsi *vsi;
3066         int ret;
3067
3068         /* If VMDQ not enabled or configured, return */
3069         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3070                           !pf->nb_cfg_vmdq_vsi)) {
3071                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3072                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3073                         pool);
3074                 return;
3075         }
3076
3077         if (pool > pf->nb_cfg_vmdq_vsi) {
3078                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3079                                 pool, pf->nb_cfg_vmdq_vsi);
3080                 return;
3081         }
3082
3083         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3084         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3085                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3086         else
3087                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3088
3089         if (pool == 0)
3090                 vsi = pf->main_vsi;
3091         else
3092                 vsi = pf->vmdq[pool - 1].vsi;
3093
3094         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3095         if (ret != I40E_SUCCESS) {
3096                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3097                 return;
3098         }
3099 }
3100
3101 /* Remove a MAC address, and update filters */
3102 static void
3103 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3104 {
3105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3106         struct i40e_vsi *vsi;
3107         struct rte_eth_dev_data *data = dev->data;
3108         struct ether_addr *macaddr;
3109         int ret;
3110         uint32_t i;
3111         uint64_t pool_sel;
3112
3113         macaddr = &(data->mac_addrs[index]);
3114
3115         pool_sel = dev->data->mac_pool_sel[index];
3116
3117         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3118                 if (pool_sel & (1ULL << i)) {
3119                         if (i == 0)
3120                                 vsi = pf->main_vsi;
3121                         else {
3122                                 /* No VMDQ pool enabled or configured */
3123                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3124                                         (i > pf->nb_cfg_vmdq_vsi)) {
3125                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3126                                                         "/configured");
3127                                         return;
3128                                 }
3129                                 vsi = pf->vmdq[i - 1].vsi;
3130                         }
3131                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3132
3133                         if (ret) {
3134                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3135                                 return;
3136                         }
3137                 }
3138         }
3139 }
3140
3141 /* Set perfect match or hash match of MAC and VLAN for a VF */
3142 static int
3143 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3144                  struct rte_eth_mac_filter *filter,
3145                  bool add)
3146 {
3147         struct i40e_hw *hw;
3148         struct i40e_mac_filter_info mac_filter;
3149         struct ether_addr old_mac;
3150         struct ether_addr *new_mac;
3151         struct i40e_pf_vf *vf = NULL;
3152         uint16_t vf_id;
3153         int ret;
3154
3155         if (pf == NULL) {
3156                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3157                 return -EINVAL;
3158         }
3159         hw = I40E_PF_TO_HW(pf);
3160
3161         if (filter == NULL) {
3162                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3163                 return -EINVAL;
3164         }
3165
3166         new_mac = &filter->mac_addr;
3167
3168         if (is_zero_ether_addr(new_mac)) {
3169                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3170                 return -EINVAL;
3171         }
3172
3173         vf_id = filter->dst_id;
3174
3175         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3176                 PMD_DRV_LOG(ERR, "Invalid argument.");
3177                 return -EINVAL;
3178         }
3179         vf = &pf->vfs[vf_id];
3180
3181         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3182                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3183                 return -EINVAL;
3184         }
3185
3186         if (add) {
3187                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3188                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3189                                 ETHER_ADDR_LEN);
3190                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3191                                  ETHER_ADDR_LEN);
3192
3193                 mac_filter.filter_type = filter->filter_type;
3194                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3195                 if (ret != I40E_SUCCESS) {
3196                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3197                         return -1;
3198                 }
3199                 ether_addr_copy(new_mac, &pf->dev_addr);
3200         } else {
3201                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3202                                 ETHER_ADDR_LEN);
3203                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3204                 if (ret != I40E_SUCCESS) {
3205                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3206                         return -1;
3207                 }
3208
3209                 /* Clear device address as it has been removed */
3210                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3211                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3212         }
3213
3214         return 0;
3215 }
3216
3217 /* MAC filter handle */
3218 static int
3219 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3220                 void *arg)
3221 {
3222         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3223         struct rte_eth_mac_filter *filter;
3224         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3225         int ret = I40E_NOT_SUPPORTED;
3226
3227         filter = (struct rte_eth_mac_filter *)(arg);
3228
3229         switch (filter_op) {
3230         case RTE_ETH_FILTER_NOP:
3231                 ret = I40E_SUCCESS;
3232                 break;
3233         case RTE_ETH_FILTER_ADD:
3234                 i40e_pf_disable_irq0(hw);
3235                 if (filter->is_vf)
3236                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3237                 i40e_pf_enable_irq0(hw);
3238                 break;
3239         case RTE_ETH_FILTER_DELETE:
3240                 i40e_pf_disable_irq0(hw);
3241                 if (filter->is_vf)
3242                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3243                 i40e_pf_enable_irq0(hw);
3244                 break;
3245         default:
3246                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3247                 ret = I40E_ERR_PARAM;
3248                 break;
3249         }
3250
3251         return ret;
3252 }
3253
3254 static int
3255 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3256 {
3257         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3258         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3259         int ret;
3260
3261         if (!lut)
3262                 return -EINVAL;
3263
3264         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3265                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3266                                           lut, lut_size);
3267                 if (ret) {
3268                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3269                         return ret;
3270                 }
3271         } else {
3272                 uint32_t *lut_dw = (uint32_t *)lut;
3273                 uint16_t i, lut_size_dw = lut_size / 4;
3274
3275                 for (i = 0; i < lut_size_dw; i++)
3276                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3277         }
3278
3279         return 0;
3280 }
3281
3282 static int
3283 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3284 {
3285         struct i40e_pf *pf;
3286         struct i40e_hw *hw;
3287         int ret;
3288
3289         if (!vsi || !lut)
3290                 return -EINVAL;
3291
3292         pf = I40E_VSI_TO_PF(vsi);
3293         hw = I40E_VSI_TO_HW(vsi);
3294
3295         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3296                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3297                                           lut, lut_size);
3298                 if (ret) {
3299                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3300                         return ret;
3301                 }
3302         } else {
3303                 uint32_t *lut_dw = (uint32_t *)lut;
3304                 uint16_t i, lut_size_dw = lut_size / 4;
3305
3306                 for (i = 0; i < lut_size_dw; i++)
3307                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3308                 I40E_WRITE_FLUSH(hw);
3309         }
3310
3311         return 0;
3312 }
3313
3314 static int
3315 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3316                          struct rte_eth_rss_reta_entry64 *reta_conf,
3317                          uint16_t reta_size)
3318 {
3319         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320         uint16_t i, lut_size = pf->hash_lut_size;
3321         uint16_t idx, shift;
3322         uint8_t *lut;
3323         int ret;
3324
3325         if (reta_size != lut_size ||
3326                 reta_size > ETH_RSS_RETA_SIZE_512) {
3327                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3328                         "(%d) doesn't match the number hardware can supported "
3329                                         "(%d)\n", reta_size, lut_size);
3330                 return -EINVAL;
3331         }
3332
3333         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3334         if (!lut) {
3335                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3336                 return -ENOMEM;
3337         }
3338         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3339         if (ret)
3340                 goto out;
3341         for (i = 0; i < reta_size; i++) {
3342                 idx = i / RTE_RETA_GROUP_SIZE;
3343                 shift = i % RTE_RETA_GROUP_SIZE;
3344                 if (reta_conf[idx].mask & (1ULL << shift))
3345                         lut[i] = reta_conf[idx].reta[shift];
3346         }
3347         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3348
3349 out:
3350         rte_free(lut);
3351
3352         return ret;
3353 }
3354
3355 static int
3356 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3357                         struct rte_eth_rss_reta_entry64 *reta_conf,
3358                         uint16_t reta_size)
3359 {
3360         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3361         uint16_t i, lut_size = pf->hash_lut_size;
3362         uint16_t idx, shift;
3363         uint8_t *lut;
3364         int ret;
3365
3366         if (reta_size != lut_size ||
3367                 reta_size > ETH_RSS_RETA_SIZE_512) {
3368                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3369                         "(%d) doesn't match the number hardware can supported "
3370                                         "(%d)\n", reta_size, lut_size);
3371                 return -EINVAL;
3372         }
3373
3374         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3375         if (!lut) {
3376                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3377                 return -ENOMEM;
3378         }
3379
3380         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3381         if (ret)
3382                 goto out;
3383         for (i = 0; i < reta_size; i++) {
3384                 idx = i / RTE_RETA_GROUP_SIZE;
3385                 shift = i % RTE_RETA_GROUP_SIZE;
3386                 if (reta_conf[idx].mask & (1ULL << shift))
3387                         reta_conf[idx].reta[shift] = lut[i];
3388         }
3389
3390 out:
3391         rte_free(lut);
3392
3393         return ret;
3394 }
3395
3396 /**
3397  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3398  * @hw:   pointer to the HW structure
3399  * @mem:  pointer to mem struct to fill out
3400  * @size: size of memory requested
3401  * @alignment: what to align the allocation to
3402  **/
3403 enum i40e_status_code
3404 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3405                         struct i40e_dma_mem *mem,
3406                         u64 size,
3407                         u32 alignment)
3408 {
3409         const struct rte_memzone *mz = NULL;
3410         char z_name[RTE_MEMZONE_NAMESIZE];
3411
3412         if (!mem)
3413                 return I40E_ERR_PARAM;
3414
3415         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3416         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3417                                          alignment, RTE_PGSIZE_2M);
3418         if (!mz)
3419                 return I40E_ERR_NO_MEMORY;
3420
3421         mem->size = size;
3422         mem->va = mz->addr;
3423         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3424         mem->zone = (const void *)mz;
3425         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3426                     "%"PRIu64, mz->name, mem->pa);
3427
3428         return I40E_SUCCESS;
3429 }
3430
3431 /**
3432  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3433  * @hw:   pointer to the HW structure
3434  * @mem:  ptr to mem struct to free
3435  **/
3436 enum i40e_status_code
3437 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3438                     struct i40e_dma_mem *mem)
3439 {
3440         if (!mem)
3441                 return I40E_ERR_PARAM;
3442
3443         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3444                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3445                     mem->pa);
3446         rte_memzone_free((const struct rte_memzone *)mem->zone);
3447         mem->zone = NULL;
3448         mem->va = NULL;
3449         mem->pa = (u64)0;
3450
3451         return I40E_SUCCESS;
3452 }
3453
3454 /**
3455  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3456  * @hw:   pointer to the HW structure
3457  * @mem:  pointer to mem struct to fill out
3458  * @size: size of memory requested
3459  **/
3460 enum i40e_status_code
3461 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3462                          struct i40e_virt_mem *mem,
3463                          u32 size)
3464 {
3465         if (!mem)
3466                 return I40E_ERR_PARAM;
3467
3468         mem->size = size;
3469         mem->va = rte_zmalloc("i40e", size, 0);
3470
3471         if (mem->va)
3472                 return I40E_SUCCESS;
3473         else
3474                 return I40E_ERR_NO_MEMORY;
3475 }
3476
3477 /**
3478  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3479  * @hw:   pointer to the HW structure
3480  * @mem:  pointer to mem struct to free
3481  **/
3482 enum i40e_status_code
3483 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3484                      struct i40e_virt_mem *mem)
3485 {
3486         if (!mem)
3487                 return I40E_ERR_PARAM;
3488
3489         rte_free(mem->va);
3490         mem->va = NULL;
3491
3492         return I40E_SUCCESS;
3493 }
3494
3495 void
3496 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3497 {
3498         rte_spinlock_init(&sp->spinlock);
3499 }
3500
3501 void
3502 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3503 {
3504         rte_spinlock_lock(&sp->spinlock);
3505 }
3506
3507 void
3508 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3509 {
3510         rte_spinlock_unlock(&sp->spinlock);
3511 }
3512
3513 void
3514 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3515 {
3516         return;
3517 }
3518
3519 /**
3520  * Get the hardware capabilities, which will be parsed
3521  * and saved into struct i40e_hw.
3522  */
3523 static int
3524 i40e_get_cap(struct i40e_hw *hw)
3525 {
3526         struct i40e_aqc_list_capabilities_element_resp *buf;
3527         uint16_t len, size = 0;
3528         int ret;
3529
3530         /* Calculate a huge enough buff for saving response data temporarily */
3531         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3532                                                 I40E_MAX_CAP_ELE_NUM;
3533         buf = rte_zmalloc("i40e", len, 0);
3534         if (!buf) {
3535                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3536                 return I40E_ERR_NO_MEMORY;
3537         }
3538
3539         /* Get, parse the capabilities and save it to hw */
3540         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3541                         i40e_aqc_opc_list_func_capabilities, NULL);
3542         if (ret != I40E_SUCCESS)
3543                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3544
3545         /* Free the temporary buffer after being used */
3546         rte_free(buf);
3547
3548         return ret;
3549 }
3550
3551 static int
3552 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3553 {
3554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3555         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3556         uint16_t qp_count = 0, vsi_count = 0;
3557
3558         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3559                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3560                 return -EINVAL;
3561         }
3562         /* Add the parameter init for LFC */
3563         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3564         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3565         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3566
3567         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3568         pf->max_num_vsi = hw->func_caps.num_vsis;
3569         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3570         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3571         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3572
3573         /* FDir queue/VSI allocation */
3574         pf->fdir_qp_offset = 0;
3575         if (hw->func_caps.fd) {
3576                 pf->flags |= I40E_FLAG_FDIR;
3577                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3578         } else {
3579                 pf->fdir_nb_qps = 0;
3580         }
3581         qp_count += pf->fdir_nb_qps;
3582         vsi_count += 1;
3583
3584         /* LAN queue/VSI allocation */
3585         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3586         if (!hw->func_caps.rss) {
3587                 pf->lan_nb_qps = 1;
3588         } else {
3589                 pf->flags |= I40E_FLAG_RSS;
3590                 if (hw->mac.type == I40E_MAC_X722)
3591                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3592                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3593         }
3594         qp_count += pf->lan_nb_qps;
3595         vsi_count += 1;
3596
3597         /* VF queue/VSI allocation */
3598         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3599         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3600                 pf->flags |= I40E_FLAG_SRIOV;
3601                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3602                 pf->vf_num = dev->pci_dev->max_vfs;
3603                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3604                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3605                             pf->vf_nb_qps * pf->vf_num);
3606         } else {
3607                 pf->vf_nb_qps = 0;
3608                 pf->vf_num = 0;
3609         }
3610         qp_count += pf->vf_nb_qps * pf->vf_num;
3611         vsi_count += pf->vf_num;
3612
3613         /* VMDq queue/VSI allocation */
3614         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3615         pf->vmdq_nb_qps = 0;
3616         pf->max_nb_vmdq_vsi = 0;
3617         if (hw->func_caps.vmdq) {
3618                 if (qp_count < hw->func_caps.num_tx_qp &&
3619                         vsi_count < hw->func_caps.num_vsis) {
3620                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3621                                 qp_count) / pf->vmdq_nb_qp_max;
3622
3623                         /* Limit the maximum number of VMDq vsi to the maximum
3624                          * ethdev can support
3625                          */
3626                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3627                                 hw->func_caps.num_vsis - vsi_count);
3628                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3629                                 ETH_64_POOLS);
3630                         if (pf->max_nb_vmdq_vsi) {
3631                                 pf->flags |= I40E_FLAG_VMDQ;
3632                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3633                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3634                                             "per VMDQ VSI, in total %u queues",
3635                                             pf->max_nb_vmdq_vsi,
3636                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3637                                             pf->max_nb_vmdq_vsi);
3638                         } else {
3639                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3640                                             "VMDq");
3641                         }
3642                 } else {
3643                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3644                 }
3645         }
3646         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3647         vsi_count += pf->max_nb_vmdq_vsi;
3648
3649         if (hw->func_caps.dcb)
3650                 pf->flags |= I40E_FLAG_DCB;
3651
3652         if (qp_count > hw->func_caps.num_tx_qp) {
3653                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3654                             "the hardware maximum %u", qp_count,
3655                             hw->func_caps.num_tx_qp);
3656                 return -EINVAL;
3657         }
3658         if (vsi_count > hw->func_caps.num_vsis) {
3659                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3660                             "the hardware maximum %u", vsi_count,
3661                             hw->func_caps.num_vsis);
3662                 return -EINVAL;
3663         }
3664
3665         return 0;
3666 }
3667
3668 static int
3669 i40e_pf_get_switch_config(struct i40e_pf *pf)
3670 {
3671         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3672         struct i40e_aqc_get_switch_config_resp *switch_config;
3673         struct i40e_aqc_switch_config_element_resp *element;
3674         uint16_t start_seid = 0, num_reported;
3675         int ret;
3676
3677         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3678                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3679         if (!switch_config) {
3680                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3681                 return -ENOMEM;
3682         }
3683
3684         /* Get the switch configurations */
3685         ret = i40e_aq_get_switch_config(hw, switch_config,
3686                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3687         if (ret != I40E_SUCCESS) {
3688                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3689                 goto fail;
3690         }
3691         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3692         if (num_reported != 1) { /* The number should be 1 */
3693                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3694                 goto fail;
3695         }
3696
3697         /* Parse the switch configuration elements */
3698         element = &(switch_config->element[0]);
3699         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3700                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3701                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3702         } else
3703                 PMD_DRV_LOG(INFO, "Unknown element type");
3704
3705 fail:
3706         rte_free(switch_config);
3707
3708         return ret;
3709 }
3710
3711 static int
3712 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3713                         uint32_t num)
3714 {
3715         struct pool_entry *entry;
3716
3717         if (pool == NULL || num == 0)
3718                 return -EINVAL;
3719
3720         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3721         if (entry == NULL) {
3722                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3723                 return -ENOMEM;
3724         }
3725
3726         /* queue heap initialize */
3727         pool->num_free = num;
3728         pool->num_alloc = 0;
3729         pool->base = base;
3730         LIST_INIT(&pool->alloc_list);
3731         LIST_INIT(&pool->free_list);
3732
3733         /* Initialize element  */
3734         entry->base = 0;
3735         entry->len = num;
3736
3737         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3738         return 0;
3739 }
3740
3741 static void
3742 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3743 {
3744         struct pool_entry *entry, *next_entry;
3745
3746         if (pool == NULL)
3747                 return;
3748
3749         for (entry = LIST_FIRST(&pool->alloc_list);
3750                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3751                         entry = next_entry) {
3752                 LIST_REMOVE(entry, next);
3753                 rte_free(entry);
3754         }
3755
3756         for (entry = LIST_FIRST(&pool->free_list);
3757                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3758                         entry = next_entry) {
3759                 LIST_REMOVE(entry, next);
3760                 rte_free(entry);
3761         }
3762
3763         pool->num_free = 0;
3764         pool->num_alloc = 0;
3765         pool->base = 0;
3766         LIST_INIT(&pool->alloc_list);
3767         LIST_INIT(&pool->free_list);
3768 }
3769
3770 static int
3771 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3772                        uint32_t base)
3773 {
3774         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3775         uint32_t pool_offset;
3776         int insert;
3777
3778         if (pool == NULL) {
3779                 PMD_DRV_LOG(ERR, "Invalid parameter");
3780                 return -EINVAL;
3781         }
3782
3783         pool_offset = base - pool->base;
3784         /* Lookup in alloc list */
3785         LIST_FOREACH(entry, &pool->alloc_list, next) {
3786                 if (entry->base == pool_offset) {
3787                         valid_entry = entry;
3788                         LIST_REMOVE(entry, next);
3789                         break;
3790                 }
3791         }
3792
3793         /* Not find, return */
3794         if (valid_entry == NULL) {
3795                 PMD_DRV_LOG(ERR, "Failed to find entry");
3796                 return -EINVAL;
3797         }
3798
3799         /**
3800          * Found it, move it to free list  and try to merge.
3801          * In order to make merge easier, always sort it by qbase.
3802          * Find adjacent prev and last entries.
3803          */
3804         prev = next = NULL;
3805         LIST_FOREACH(entry, &pool->free_list, next) {
3806                 if (entry->base > valid_entry->base) {
3807                         next = entry;
3808                         break;
3809                 }
3810                 prev = entry;
3811         }
3812
3813         insert = 0;
3814         /* Try to merge with next one*/
3815         if (next != NULL) {
3816                 /* Merge with next one */
3817                 if (valid_entry->base + valid_entry->len == next->base) {
3818                         next->base = valid_entry->base;
3819                         next->len += valid_entry->len;
3820                         rte_free(valid_entry);
3821                         valid_entry = next;
3822                         insert = 1;
3823                 }
3824         }
3825
3826         if (prev != NULL) {
3827                 /* Merge with previous one */
3828                 if (prev->base + prev->len == valid_entry->base) {
3829                         prev->len += valid_entry->len;
3830                         /* If it merge with next one, remove next node */
3831                         if (insert == 1) {
3832                                 LIST_REMOVE(valid_entry, next);
3833                                 rte_free(valid_entry);
3834                         } else {
3835                                 rte_free(valid_entry);
3836                                 insert = 1;
3837                         }
3838                 }
3839         }
3840
3841         /* Not find any entry to merge, insert */
3842         if (insert == 0) {
3843                 if (prev != NULL)
3844                         LIST_INSERT_AFTER(prev, valid_entry, next);
3845                 else if (next != NULL)
3846                         LIST_INSERT_BEFORE(next, valid_entry, next);
3847                 else /* It's empty list, insert to head */
3848                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3849         }
3850
3851         pool->num_free += valid_entry->len;
3852         pool->num_alloc -= valid_entry->len;
3853
3854         return 0;
3855 }
3856
3857 static int
3858 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3859                        uint16_t num)
3860 {
3861         struct pool_entry *entry, *valid_entry;
3862
3863         if (pool == NULL || num == 0) {
3864                 PMD_DRV_LOG(ERR, "Invalid parameter");
3865                 return -EINVAL;
3866         }
3867
3868         if (pool->num_free < num) {
3869                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3870                             num, pool->num_free);
3871                 return -ENOMEM;
3872         }
3873
3874         valid_entry = NULL;
3875         /* Lookup  in free list and find most fit one */
3876         LIST_FOREACH(entry, &pool->free_list, next) {
3877                 if (entry->len >= num) {
3878                         /* Find best one */
3879                         if (entry->len == num) {
3880                                 valid_entry = entry;
3881                                 break;
3882                         }
3883                         if (valid_entry == NULL || valid_entry->len > entry->len)
3884                                 valid_entry = entry;
3885                 }
3886         }
3887
3888         /* Not find one to satisfy the request, return */
3889         if (valid_entry == NULL) {
3890                 PMD_DRV_LOG(ERR, "No valid entry found");
3891                 return -ENOMEM;
3892         }
3893         /**
3894          * The entry have equal queue number as requested,
3895          * remove it from alloc_list.
3896          */
3897         if (valid_entry->len == num) {
3898                 LIST_REMOVE(valid_entry, next);
3899         } else {
3900                 /**
3901                  * The entry have more numbers than requested,
3902                  * create a new entry for alloc_list and minus its
3903                  * queue base and number in free_list.
3904                  */
3905                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3906                 if (entry == NULL) {
3907                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3908                                     "resource pool");
3909                         return -ENOMEM;
3910                 }
3911                 entry->base = valid_entry->base;
3912                 entry->len = num;
3913                 valid_entry->base += num;
3914                 valid_entry->len -= num;
3915                 valid_entry = entry;
3916         }
3917
3918         /* Insert it into alloc list, not sorted */
3919         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3920
3921         pool->num_free -= valid_entry->len;
3922         pool->num_alloc += valid_entry->len;
3923
3924         return valid_entry->base + pool->base;
3925 }
3926
3927 /**
3928  * bitmap_is_subset - Check whether src2 is subset of src1
3929  **/
3930 static inline int
3931 bitmap_is_subset(uint8_t src1, uint8_t src2)
3932 {
3933         return !((src1 ^ src2) & src2);
3934 }
3935
3936 static enum i40e_status_code
3937 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3938 {
3939         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3940
3941         /* If DCB is not supported, only default TC is supported */
3942         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3943                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3944                 return I40E_NOT_SUPPORTED;
3945         }
3946
3947         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3948                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3949                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3950                             enabled_tcmap);
3951                 return I40E_NOT_SUPPORTED;
3952         }
3953         return I40E_SUCCESS;
3954 }
3955
3956 int
3957 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3958                                 struct i40e_vsi_vlan_pvid_info *info)
3959 {
3960         struct i40e_hw *hw;
3961         struct i40e_vsi_context ctxt;
3962         uint8_t vlan_flags = 0;
3963         int ret;
3964
3965         if (vsi == NULL || info == NULL) {
3966                 PMD_DRV_LOG(ERR, "invalid parameters");
3967                 return I40E_ERR_PARAM;
3968         }
3969
3970         if (info->on) {
3971                 vsi->info.pvid = info->config.pvid;
3972                 /**
3973                  * If insert pvid is enabled, only tagged pkts are
3974                  * allowed to be sent out.
3975                  */
3976                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3977                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3978         } else {
3979                 vsi->info.pvid = 0;
3980                 if (info->config.reject.tagged == 0)
3981                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3982
3983                 if (info->config.reject.untagged == 0)
3984                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3985         }
3986         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3987                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3988         vsi->info.port_vlan_flags |= vlan_flags;
3989         vsi->info.valid_sections =
3990                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3991         memset(&ctxt, 0, sizeof(ctxt));
3992         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3993         ctxt.seid = vsi->seid;
3994
3995         hw = I40E_VSI_TO_HW(vsi);
3996         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3997         if (ret != I40E_SUCCESS)
3998                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3999
4000         return ret;
4001 }
4002
4003 static int
4004 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4005 {
4006         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4007         int i, ret;
4008         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4009
4010         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4011         if (ret != I40E_SUCCESS)
4012                 return ret;
4013
4014         if (!vsi->seid) {
4015                 PMD_DRV_LOG(ERR, "seid not valid");
4016                 return -EINVAL;
4017         }
4018
4019         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4020         tc_bw_data.tc_valid_bits = enabled_tcmap;
4021         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4022                 tc_bw_data.tc_bw_credits[i] =
4023                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4024
4025         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4026         if (ret != I40E_SUCCESS) {
4027                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4028                 return ret;
4029         }
4030
4031         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4032                                         sizeof(vsi->info.qs_handle));
4033         return I40E_SUCCESS;
4034 }
4035
4036 static enum i40e_status_code
4037 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4038                                  struct i40e_aqc_vsi_properties_data *info,
4039                                  uint8_t enabled_tcmap)
4040 {
4041         enum i40e_status_code ret;
4042         int i, total_tc = 0;
4043         uint16_t qpnum_per_tc, bsf, qp_idx;
4044
4045         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4046         if (ret != I40E_SUCCESS)
4047                 return ret;
4048
4049         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4050                 if (enabled_tcmap & (1 << i))
4051                         total_tc++;
4052         if (total_tc == 0)
4053                 total_tc = 1;
4054         vsi->enabled_tc = enabled_tcmap;
4055
4056         /* Number of queues per enabled TC */
4057         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4058         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4059         bsf = rte_bsf32(qpnum_per_tc);
4060
4061         /* Adjust the queue number to actual queues that can be applied */
4062         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4063                 vsi->nb_qps = qpnum_per_tc * total_tc;
4064
4065         /**
4066          * Configure TC and queue mapping parameters, for enabled TC,
4067          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4068          * default queue will serve it.
4069          */
4070         qp_idx = 0;
4071         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4072                 if (vsi->enabled_tc & (1 << i)) {
4073                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4074                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4075                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4076                         qp_idx += qpnum_per_tc;
4077                 } else
4078                         info->tc_mapping[i] = 0;
4079         }
4080
4081         /* Associate queue number with VSI */
4082         if (vsi->type == I40E_VSI_SRIOV) {
4083                 info->mapping_flags |=
4084                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4085                 for (i = 0; i < vsi->nb_qps; i++)
4086                         info->queue_mapping[i] =
4087                                 rte_cpu_to_le_16(vsi->base_queue + i);
4088         } else {
4089                 info->mapping_flags |=
4090                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4091                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4092         }
4093         info->valid_sections |=
4094                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4095
4096         return I40E_SUCCESS;
4097 }
4098
4099 static int
4100 i40e_veb_release(struct i40e_veb *veb)
4101 {
4102         struct i40e_vsi *vsi;
4103         struct i40e_hw *hw;
4104
4105         if (veb == NULL)
4106                 return -EINVAL;
4107
4108         if (!TAILQ_EMPTY(&veb->head)) {
4109                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4110                 return -EACCES;
4111         }
4112         /* associate_vsi field is NULL for floating VEB */
4113         if (veb->associate_vsi != NULL) {
4114                 vsi = veb->associate_vsi;
4115                 hw = I40E_VSI_TO_HW(vsi);
4116
4117                 vsi->uplink_seid = veb->uplink_seid;
4118                 vsi->veb = NULL;
4119         } else {
4120                 veb->associate_pf->main_vsi->floating_veb = NULL;
4121                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4122         }
4123
4124         i40e_aq_delete_element(hw, veb->seid, NULL);
4125         rte_free(veb);
4126         return I40E_SUCCESS;
4127 }
4128
4129 /* Setup a veb */
4130 static struct i40e_veb *
4131 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4132 {
4133         struct i40e_veb *veb;
4134         int ret;
4135         struct i40e_hw *hw;
4136
4137         if (pf == NULL) {
4138                 PMD_DRV_LOG(ERR,
4139                             "veb setup failed, associated PF shouldn't null");
4140                 return NULL;
4141         }
4142         hw = I40E_PF_TO_HW(pf);
4143
4144         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4145         if (!veb) {
4146                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4147                 goto fail;
4148         }
4149
4150         veb->associate_vsi = vsi;
4151         veb->associate_pf = pf;
4152         TAILQ_INIT(&veb->head);
4153         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4154
4155         /* create floating veb if vsi is NULL */
4156         if (vsi != NULL) {
4157                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4158                                       I40E_DEFAULT_TCMAP, false,
4159                                       &veb->seid, false, NULL);
4160         } else {
4161                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4162                                       true, &veb->seid, false, NULL);
4163         }
4164
4165         if (ret != I40E_SUCCESS) {
4166                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4167                             hw->aq.asq_last_status);
4168                 goto fail;
4169         }
4170         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4171
4172         /* get statistics index */
4173         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4174                                 &veb->stats_idx, NULL, NULL, NULL);
4175         if (ret != I40E_SUCCESS) {
4176                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4177                             hw->aq.asq_last_status);
4178                 goto fail;
4179         }
4180         /* Get VEB bandwidth, to be implemented */
4181         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4182         if (vsi)
4183                 vsi->uplink_seid = veb->seid;
4184
4185         return veb;
4186 fail:
4187         rte_free(veb);
4188         return NULL;
4189 }
4190
4191 int
4192 i40e_vsi_release(struct i40e_vsi *vsi)
4193 {
4194         struct i40e_pf *pf;
4195         struct i40e_hw *hw;
4196         struct i40e_vsi_list *vsi_list;
4197         void *temp;
4198         int ret;
4199         struct i40e_mac_filter *f;
4200         uint16_t user_param;
4201
4202         if (!vsi)
4203                 return I40E_SUCCESS;
4204
4205         if (!vsi->adapter)
4206                 return -EFAULT;
4207
4208         user_param = vsi->user_param;
4209
4210         pf = I40E_VSI_TO_PF(vsi);
4211         hw = I40E_VSI_TO_HW(vsi);
4212
4213         /* VSI has child to attach, release child first */
4214         if (vsi->veb) {
4215                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4216                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4217                                 return -1;
4218                 }
4219                 i40e_veb_release(vsi->veb);
4220         }
4221
4222         if (vsi->floating_veb) {
4223                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4224                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4225                                 return -1;
4226                 }
4227         }
4228
4229         /* Remove all macvlan filters of the VSI */
4230         i40e_vsi_remove_all_macvlan_filter(vsi);
4231         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4232                 rte_free(f);
4233
4234         if (vsi->type != I40E_VSI_MAIN &&
4235             ((vsi->type != I40E_VSI_SRIOV) ||
4236             !pf->floating_veb_list[user_param])) {
4237                 /* Remove vsi from parent's sibling list */
4238                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4239                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4240                         return I40E_ERR_PARAM;
4241                 }
4242                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4243                                 &vsi->sib_vsi_list, list);
4244
4245                 /* Remove all switch element of the VSI */
4246                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4247                 if (ret != I40E_SUCCESS)
4248                         PMD_DRV_LOG(ERR, "Failed to delete element");
4249         }
4250
4251         if ((vsi->type == I40E_VSI_SRIOV) &&
4252             pf->floating_veb_list[user_param]) {
4253                 /* Remove vsi from parent's sibling list */
4254                 if (vsi->parent_vsi == NULL ||
4255                     vsi->parent_vsi->floating_veb == NULL) {
4256                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4257                         return I40E_ERR_PARAM;
4258                 }
4259                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4260                              &vsi->sib_vsi_list, list);
4261
4262                 /* Remove all switch element of the VSI */
4263                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4264                 if (ret != I40E_SUCCESS)
4265                         PMD_DRV_LOG(ERR, "Failed to delete element");
4266         }
4267
4268         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4269
4270         if (vsi->type != I40E_VSI_SRIOV)
4271                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4272         rte_free(vsi);
4273
4274         return I40E_SUCCESS;
4275 }
4276
4277 static int
4278 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4279 {
4280         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4281         struct i40e_aqc_remove_macvlan_element_data def_filter;
4282         struct i40e_mac_filter_info filter;
4283         int ret;
4284
4285         if (vsi->type != I40E_VSI_MAIN)
4286                 return I40E_ERR_CONFIG;
4287         memset(&def_filter, 0, sizeof(def_filter));
4288         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4289                                         ETH_ADDR_LEN);
4290         def_filter.vlan_tag = 0;
4291         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4292                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4293         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4294         if (ret != I40E_SUCCESS) {
4295                 struct i40e_mac_filter *f;
4296                 struct ether_addr *mac;
4297
4298                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4299                             "macvlan filter");
4300                 /* It needs to add the permanent mac into mac list */
4301                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4302                 if (f == NULL) {
4303                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4304                         return I40E_ERR_NO_MEMORY;
4305                 }
4306                 mac = &f->mac_info.mac_addr;
4307                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4308                                 ETH_ADDR_LEN);
4309                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4310                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4311                 vsi->mac_num++;
4312
4313                 return ret;
4314         }
4315         (void)rte_memcpy(&filter.mac_addr,
4316                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4317         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4318         return i40e_vsi_add_mac(vsi, &filter);
4319 }
4320
4321 /*
4322  * i40e_vsi_get_bw_config - Query VSI BW Information
4323  * @vsi: the VSI to be queried
4324  *
4325  * Returns 0 on success, negative value on failure
4326  */
4327 static enum i40e_status_code
4328 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4329 {
4330         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4331         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4332         struct i40e_hw *hw = &vsi->adapter->hw;
4333         i40e_status ret;
4334         int i;
4335         uint32_t bw_max;
4336
4337         memset(&bw_config, 0, sizeof(bw_config));
4338         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4339         if (ret != I40E_SUCCESS) {
4340                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4341                             hw->aq.asq_last_status);
4342                 return ret;
4343         }
4344
4345         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4346         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4347                                         &ets_sla_config, NULL);
4348         if (ret != I40E_SUCCESS) {
4349                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4350                             "configuration %u", hw->aq.asq_last_status);
4351                 return ret;
4352         }
4353
4354         /* store and print out BW info */
4355         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4356         vsi->bw_info.bw_max = bw_config.max_bw;
4357         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4358         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4359         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4360                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4361                      I40E_16_BIT_WIDTH);
4362         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4363                 vsi->bw_info.bw_ets_share_credits[i] =
4364                                 ets_sla_config.share_credits[i];
4365                 vsi->bw_info.bw_ets_credits[i] =
4366                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4367                 /* 4 bits per TC, 4th bit is reserved */
4368                 vsi->bw_info.bw_ets_max[i] =
4369                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4370                                   RTE_LEN2MASK(3, uint8_t));
4371                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4372                             vsi->bw_info.bw_ets_share_credits[i]);
4373                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4374                             vsi->bw_info.bw_ets_credits[i]);
4375                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4376                             vsi->bw_info.bw_ets_max[i]);
4377         }
4378
4379         return I40E_SUCCESS;
4380 }
4381
4382 /* i40e_enable_pf_lb
4383  * @pf: pointer to the pf structure
4384  *
4385  * allow loopback on pf
4386  */
4387 static inline void
4388 i40e_enable_pf_lb(struct i40e_pf *pf)
4389 {
4390         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4391         struct i40e_vsi_context ctxt;
4392         int ret;
4393
4394         /* Use the FW API if FW >= v5.0 */
4395         if (hw->aq.fw_maj_ver < 5) {
4396                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4397                 return;
4398         }
4399
4400         memset(&ctxt, 0, sizeof(ctxt));
4401         ctxt.seid = pf->main_vsi_seid;
4402         ctxt.pf_num = hw->pf_id;
4403         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4404         if (ret) {
4405                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4406                             ret, hw->aq.asq_last_status);
4407                 return;
4408         }
4409         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4410         ctxt.info.valid_sections =
4411                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4412         ctxt.info.switch_id |=
4413                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4414
4415         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4416         if (ret)
4417                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4418                             hw->aq.asq_last_status);
4419 }
4420
4421 /* Setup a VSI */
4422 struct i40e_vsi *
4423 i40e_vsi_setup(struct i40e_pf *pf,
4424                enum i40e_vsi_type type,
4425                struct i40e_vsi *uplink_vsi,
4426                uint16_t user_param)
4427 {
4428         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4429         struct i40e_vsi *vsi;
4430         struct i40e_mac_filter_info filter;
4431         int ret;
4432         struct i40e_vsi_context ctxt;
4433         struct ether_addr broadcast =
4434                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4435
4436         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4437             uplink_vsi == NULL) {
4438                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4439                             "VSI link shouldn't be NULL");
4440                 return NULL;
4441         }
4442
4443         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4444                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4445                             "uplink VSI should be NULL");
4446                 return NULL;
4447         }
4448
4449         /* two situations
4450          * 1.type is not MAIN and uplink vsi is not NULL
4451          * If uplink vsi didn't setup VEB, create one first under veb field
4452          * 2.type is SRIOV and the uplink is NULL
4453          * If floating VEB is NULL, create one veb under floating veb field
4454          */
4455
4456         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4457             uplink_vsi->veb == NULL) {
4458                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4459
4460                 if (uplink_vsi->veb == NULL) {
4461                         PMD_DRV_LOG(ERR, "VEB setup failed");
4462                         return NULL;
4463                 }
4464                 /* set ALLOWLOOPBACk on pf, when veb is created */
4465                 i40e_enable_pf_lb(pf);
4466         }
4467
4468         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4469             pf->main_vsi->floating_veb == NULL) {
4470                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4471
4472                 if (pf->main_vsi->floating_veb == NULL) {
4473                         PMD_DRV_LOG(ERR, "VEB setup failed");
4474                         return NULL;
4475                 }
4476         }
4477
4478         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4479         if (!vsi) {
4480                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4481                 return NULL;
4482         }
4483         TAILQ_INIT(&vsi->mac_list);
4484         vsi->type = type;
4485         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4486         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4487         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4488         vsi->user_param = user_param;
4489         /* Allocate queues */
4490         switch (vsi->type) {
4491         case I40E_VSI_MAIN  :
4492                 vsi->nb_qps = pf->lan_nb_qps;
4493                 break;
4494         case I40E_VSI_SRIOV :
4495                 vsi->nb_qps = pf->vf_nb_qps;
4496                 break;
4497         case I40E_VSI_VMDQ2:
4498                 vsi->nb_qps = pf->vmdq_nb_qps;
4499                 break;
4500         case I40E_VSI_FDIR:
4501                 vsi->nb_qps = pf->fdir_nb_qps;
4502                 break;
4503         default:
4504                 goto fail_mem;
4505         }
4506         /*
4507          * The filter status descriptor is reported in rx queue 0,
4508          * while the tx queue for fdir filter programming has no
4509          * such constraints, can be non-zero queues.
4510          * To simplify it, choose FDIR vsi use queue 0 pair.
4511          * To make sure it will use queue 0 pair, queue allocation
4512          * need be done before this function is called
4513          */
4514         if (type != I40E_VSI_FDIR) {
4515                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4516                         if (ret < 0) {
4517                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4518                                                 vsi->seid, ret);
4519                                 goto fail_mem;
4520                         }
4521                         vsi->base_queue = ret;
4522         } else
4523                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4524
4525         /* VF has MSIX interrupt in VF range, don't allocate here */
4526         if (type == I40E_VSI_MAIN) {
4527                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4528                                           RTE_MIN(vsi->nb_qps,
4529                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4530                 if (ret < 0) {
4531                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4532                                     vsi->seid, ret);
4533                         goto fail_queue_alloc;
4534                 }
4535                 vsi->msix_intr = ret;
4536                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4537         } else if (type != I40E_VSI_SRIOV) {
4538                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4539                 if (ret < 0) {
4540                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4541                         goto fail_queue_alloc;
4542                 }
4543                 vsi->msix_intr = ret;
4544                 vsi->nb_msix = 1;
4545         } else {
4546                 vsi->msix_intr = 0;
4547                 vsi->nb_msix = 0;
4548         }
4549
4550         /* Add VSI */
4551         if (type == I40E_VSI_MAIN) {
4552                 /* For main VSI, no need to add since it's default one */
4553                 vsi->uplink_seid = pf->mac_seid;
4554                 vsi->seid = pf->main_vsi_seid;
4555                 /* Bind queues with specific MSIX interrupt */
4556                 /**
4557                  * Needs 2 interrupt at least, one for misc cause which will
4558                  * enabled from OS side, Another for queues binding the
4559                  * interrupt from device side only.
4560                  */
4561
4562                 /* Get default VSI parameters from hardware */
4563                 memset(&ctxt, 0, sizeof(ctxt));
4564                 ctxt.seid = vsi->seid;
4565                 ctxt.pf_num = hw->pf_id;
4566                 ctxt.uplink_seid = vsi->uplink_seid;
4567                 ctxt.vf_num = 0;
4568                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4569                 if (ret != I40E_SUCCESS) {
4570                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4571                         goto fail_msix_alloc;
4572                 }
4573                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4574                         sizeof(struct i40e_aqc_vsi_properties_data));
4575                 vsi->vsi_id = ctxt.vsi_number;
4576                 vsi->info.valid_sections = 0;
4577
4578                 /* Configure tc, enabled TC0 only */
4579                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4580                         I40E_SUCCESS) {
4581                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4582                         goto fail_msix_alloc;
4583                 }
4584
4585                 /* TC, queue mapping */
4586                 memset(&ctxt, 0, sizeof(ctxt));
4587                 vsi->info.valid_sections |=
4588                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4589                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4590                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4591                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4592                         sizeof(struct i40e_aqc_vsi_properties_data));
4593                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4594                                                 I40E_DEFAULT_TCMAP);
4595                 if (ret != I40E_SUCCESS) {
4596                         PMD_DRV_LOG(ERR, "Failed to configure "
4597                                     "TC queue mapping");
4598                         goto fail_msix_alloc;
4599                 }
4600                 ctxt.seid = vsi->seid;
4601                 ctxt.pf_num = hw->pf_id;
4602                 ctxt.uplink_seid = vsi->uplink_seid;
4603                 ctxt.vf_num = 0;
4604
4605                 /* Update VSI parameters */
4606                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4607                 if (ret != I40E_SUCCESS) {
4608                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4609                         goto fail_msix_alloc;
4610                 }
4611
4612                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4613                                                 sizeof(vsi->info.tc_mapping));
4614                 (void)rte_memcpy(&vsi->info.queue_mapping,
4615                                 &ctxt.info.queue_mapping,
4616                         sizeof(vsi->info.queue_mapping));
4617                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4618                 vsi->info.valid_sections = 0;
4619
4620                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4621                                 ETH_ADDR_LEN);
4622
4623                 /**
4624                  * Updating default filter settings are necessary to prevent
4625                  * reception of tagged packets.
4626                  * Some old firmware configurations load a default macvlan
4627                  * filter which accepts both tagged and untagged packets.
4628                  * The updating is to use a normal filter instead if needed.
4629                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4630                  * The firmware with correct configurations load the default
4631                  * macvlan filter which is expected and cannot be removed.
4632                  */
4633                 i40e_update_default_filter_setting(vsi);
4634                 i40e_config_qinq(hw, vsi);
4635         } else if (type == I40E_VSI_SRIOV) {
4636                 memset(&ctxt, 0, sizeof(ctxt));
4637                 /**
4638                  * For other VSI, the uplink_seid equals to uplink VSI's
4639                  * uplink_seid since they share same VEB
4640                  */
4641                 if (uplink_vsi == NULL)
4642                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4643                 else
4644                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4645                 ctxt.pf_num = hw->pf_id;
4646                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4647                 ctxt.uplink_seid = vsi->uplink_seid;
4648                 ctxt.connection_type = 0x1;
4649                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4650
4651                 /* Use the VEB configuration if FW >= v5.0 */
4652                 if (hw->aq.fw_maj_ver >= 5) {
4653                         /* Configure switch ID */
4654                         ctxt.info.valid_sections |=
4655                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4656                         ctxt.info.switch_id =
4657                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4658                 }
4659
4660                 /* Configure port/vlan */
4661                 ctxt.info.valid_sections |=
4662                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4663                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4664                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4665                                                 I40E_DEFAULT_TCMAP);
4666                 if (ret != I40E_SUCCESS) {
4667                         PMD_DRV_LOG(ERR, "Failed to configure "
4668                                     "TC queue mapping");
4669                         goto fail_msix_alloc;
4670                 }
4671                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4672                 ctxt.info.valid_sections |=
4673                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4674                 /**
4675                  * Since VSI is not created yet, only configure parameter,
4676                  * will add vsi below.
4677                  */
4678
4679                 i40e_config_qinq(hw, vsi);
4680         } else if (type == I40E_VSI_VMDQ2) {
4681                 memset(&ctxt, 0, sizeof(ctxt));
4682                 /*
4683                  * For other VSI, the uplink_seid equals to uplink VSI's
4684                  * uplink_seid since they share same VEB
4685                  */
4686                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4687                 ctxt.pf_num = hw->pf_id;
4688                 ctxt.vf_num = 0;
4689                 ctxt.uplink_seid = vsi->uplink_seid;
4690                 ctxt.connection_type = 0x1;
4691                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4692
4693                 ctxt.info.valid_sections |=
4694                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4695                 /* user_param carries flag to enable loop back */
4696                 if (user_param) {
4697                         ctxt.info.switch_id =
4698                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4699                         ctxt.info.switch_id |=
4700                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4701                 }
4702
4703                 /* Configure port/vlan */
4704                 ctxt.info.valid_sections |=
4705                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4706                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4707                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4708                                                 I40E_DEFAULT_TCMAP);
4709                 if (ret != I40E_SUCCESS) {
4710                         PMD_DRV_LOG(ERR, "Failed to configure "
4711                                         "TC queue mapping");
4712                         goto fail_msix_alloc;
4713                 }
4714                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4715                 ctxt.info.valid_sections |=
4716                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4717         } else if (type == I40E_VSI_FDIR) {
4718                 memset(&ctxt, 0, sizeof(ctxt));
4719                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4720                 ctxt.pf_num = hw->pf_id;
4721                 ctxt.vf_num = 0;
4722                 ctxt.uplink_seid = vsi->uplink_seid;
4723                 ctxt.connection_type = 0x1;     /* regular data port */
4724                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4725                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4726                                                 I40E_DEFAULT_TCMAP);
4727                 if (ret != I40E_SUCCESS) {
4728                         PMD_DRV_LOG(ERR, "Failed to configure "
4729                                         "TC queue mapping.");
4730                         goto fail_msix_alloc;
4731                 }
4732                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4733                 ctxt.info.valid_sections |=
4734                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4735         } else {
4736                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4737                 goto fail_msix_alloc;
4738         }
4739
4740         if (vsi->type != I40E_VSI_MAIN) {
4741                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4742                 if (ret != I40E_SUCCESS) {
4743                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4744                                     hw->aq.asq_last_status);
4745                         goto fail_msix_alloc;
4746                 }
4747                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4748                 vsi->info.valid_sections = 0;
4749                 vsi->seid = ctxt.seid;
4750                 vsi->vsi_id = ctxt.vsi_number;
4751                 vsi->sib_vsi_list.vsi = vsi;
4752                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4753                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4754                                           &vsi->sib_vsi_list, list);
4755                 } else {
4756                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4757                                           &vsi->sib_vsi_list, list);
4758                 }
4759         }
4760
4761         /* MAC/VLAN configuration */
4762         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4763         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4764
4765         ret = i40e_vsi_add_mac(vsi, &filter);
4766         if (ret != I40E_SUCCESS) {
4767                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4768                 goto fail_msix_alloc;
4769         }
4770
4771         /* Get VSI BW information */
4772         i40e_vsi_get_bw_config(vsi);
4773         return vsi;
4774 fail_msix_alloc:
4775         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4776 fail_queue_alloc:
4777         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4778 fail_mem:
4779         rte_free(vsi);
4780         return NULL;
4781 }
4782
4783 /* Configure vlan filter on or off */
4784 int
4785 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4786 {
4787         int i, num;
4788         struct i40e_mac_filter *f;
4789         void *temp;
4790         struct i40e_mac_filter_info *mac_filter;
4791         enum rte_mac_filter_type desired_filter;
4792         int ret = I40E_SUCCESS;
4793
4794         if (on) {
4795                 /* Filter to match MAC and VLAN */
4796                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4797         } else {
4798                 /* Filter to match only MAC */
4799                 desired_filter = RTE_MAC_PERFECT_MATCH;
4800         }
4801
4802         num = vsi->mac_num;
4803
4804         mac_filter = rte_zmalloc("mac_filter_info_data",
4805                                  num * sizeof(*mac_filter), 0);
4806         if (mac_filter == NULL) {
4807                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4808                 return I40E_ERR_NO_MEMORY;
4809         }
4810
4811         i = 0;
4812
4813         /* Remove all existing mac */
4814         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4815                 mac_filter[i] = f->mac_info;
4816                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4817                 if (ret) {
4818                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4819                                     on ? "enable" : "disable");
4820                         goto DONE;
4821                 }
4822                 i++;
4823         }
4824
4825         /* Override with new filter */
4826         for (i = 0; i < num; i++) {
4827                 mac_filter[i].filter_type = desired_filter;
4828                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4829                 if (ret) {
4830                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4831                                     on ? "enable" : "disable");
4832                         goto DONE;
4833                 }
4834         }
4835
4836 DONE:
4837         rte_free(mac_filter);
4838         return ret;
4839 }
4840
4841 /* Configure vlan stripping on or off */
4842 int
4843 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4844 {
4845         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4846         struct i40e_vsi_context ctxt;
4847         uint8_t vlan_flags;
4848         int ret = I40E_SUCCESS;
4849
4850         /* Check if it has been already on or off */
4851         if (vsi->info.valid_sections &
4852                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4853                 if (on) {
4854                         if ((vsi->info.port_vlan_flags &
4855                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4856                                 return 0; /* already on */
4857                 } else {
4858                         if ((vsi->info.port_vlan_flags &
4859                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4860                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4861                                 return 0; /* already off */
4862                 }
4863         }
4864
4865         if (on)
4866                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4867         else
4868                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4869         vsi->info.valid_sections =
4870                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4871         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4872         vsi->info.port_vlan_flags |= vlan_flags;
4873         ctxt.seid = vsi->seid;
4874         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4875         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4876         if (ret)
4877                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4878                             on ? "enable" : "disable");
4879
4880         return ret;
4881 }
4882
4883 static int
4884 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4885 {
4886         struct rte_eth_dev_data *data = dev->data;
4887         int ret;
4888         int mask = 0;
4889
4890         /* Apply vlan offload setting */
4891         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4892         i40e_vlan_offload_set(dev, mask);
4893
4894         /* Apply double-vlan setting, not implemented yet */
4895
4896         /* Apply pvid setting */
4897         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4898                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4899         if (ret)
4900                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4901
4902         return ret;
4903 }
4904
4905 static int
4906 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4907 {
4908         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4909
4910         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4911 }
4912
4913 static int
4914 i40e_update_flow_control(struct i40e_hw *hw)
4915 {
4916 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4917         struct i40e_link_status link_status;
4918         uint32_t rxfc = 0, txfc = 0, reg;
4919         uint8_t an_info;
4920         int ret;
4921
4922         memset(&link_status, 0, sizeof(link_status));
4923         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4924         if (ret != I40E_SUCCESS) {
4925                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4926                 goto write_reg; /* Disable flow control */
4927         }
4928
4929         an_info = hw->phy.link_info.an_info;
4930         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4931                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4932                 ret = I40E_ERR_NOT_READY;
4933                 goto write_reg; /* Disable flow control */
4934         }
4935         /**
4936          * If link auto negotiation is enabled, flow control needs to
4937          * be configured according to it
4938          */
4939         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4940         case I40E_LINK_PAUSE_RXTX:
4941                 rxfc = 1;
4942                 txfc = 1;
4943                 hw->fc.current_mode = I40E_FC_FULL;
4944                 break;
4945         case I40E_AQ_LINK_PAUSE_RX:
4946                 rxfc = 1;
4947                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4948                 break;
4949         case I40E_AQ_LINK_PAUSE_TX:
4950                 txfc = 1;
4951                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4952                 break;
4953         default:
4954                 hw->fc.current_mode = I40E_FC_NONE;
4955                 break;
4956         }
4957
4958 write_reg:
4959         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4960                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4961         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4962         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4963         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4964         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4965
4966         return ret;
4967 }
4968
4969 /* PF setup */
4970 static int
4971 i40e_pf_setup(struct i40e_pf *pf)
4972 {
4973         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4974         struct i40e_filter_control_settings settings;
4975         struct i40e_vsi *vsi;
4976         int ret;
4977
4978         /* Clear all stats counters */
4979         pf->offset_loaded = FALSE;
4980         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4981         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4982         pf->internal_rx_bytes = 0;
4983         pf->internal_tx_bytes = 0;
4984         pf->internal_rx_bytes_offset = 0;
4985         pf->internal_tx_bytes_offset = 0;
4986
4987         ret = i40e_pf_get_switch_config(pf);
4988         if (ret != I40E_SUCCESS) {
4989                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4990                 return ret;
4991         }
4992         if (pf->flags & I40E_FLAG_FDIR) {
4993                 /* make queue allocated first, let FDIR use queue pair 0*/
4994                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4995                 if (ret != I40E_FDIR_QUEUE_ID) {
4996                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4997                                     " ret =%d", ret);
4998                         pf->flags &= ~I40E_FLAG_FDIR;
4999                 }
5000         }
5001         /*  main VSI setup */
5002         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5003         if (!vsi) {
5004                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5005                 return I40E_ERR_NOT_READY;
5006         }
5007         pf->main_vsi = vsi;
5008
5009         /* Configure filter control */
5010         memset(&settings, 0, sizeof(settings));
5011         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5012                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5013         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5014                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5015         else {
5016                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5017                                                 hw->func_caps.rss_table_size);
5018                 return I40E_ERR_PARAM;
5019         }
5020         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5021                         "size: %u\n", hw->func_caps.rss_table_size);
5022         pf->hash_lut_size = hw->func_caps.rss_table_size;
5023
5024         /* Enable ethtype and macvlan filters */
5025         settings.enable_ethtype = TRUE;
5026         settings.enable_macvlan = TRUE;
5027         ret = i40e_set_filter_control(hw, &settings);
5028         if (ret)
5029                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5030                                                                 ret);
5031
5032         /* Update flow control according to the auto negotiation */
5033         i40e_update_flow_control(hw);
5034
5035         return I40E_SUCCESS;
5036 }
5037
5038 int
5039 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5040 {
5041         uint32_t reg;
5042         uint16_t j;
5043
5044         /**
5045          * Set or clear TX Queue Disable flags,
5046          * which is required by hardware.
5047          */
5048         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5049         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5050
5051         /* Wait until the request is finished */
5052         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5053                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5054                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5055                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5056                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5057                                                         & 0x1))) {
5058                         break;
5059                 }
5060         }
5061         if (on) {
5062                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5063                         return I40E_SUCCESS; /* already on, skip next steps */
5064
5065                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5066                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5067         } else {
5068                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5069                         return I40E_SUCCESS; /* already off, skip next steps */
5070                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5071         }
5072         /* Write the register */
5073         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5074         /* Check the result */
5075         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5076                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5077                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5078                 if (on) {
5079                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5080                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5081                                 break;
5082                 } else {
5083                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5084                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5085                                 break;
5086                 }
5087         }
5088         /* Check if it is timeout */
5089         if (j >= I40E_CHK_Q_ENA_COUNT) {
5090                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5091                             (on ? "enable" : "disable"), q_idx);
5092                 return I40E_ERR_TIMEOUT;
5093         }
5094
5095         return I40E_SUCCESS;
5096 }
5097
5098 /* Swith on or off the tx queues */
5099 static int
5100 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5101 {
5102         struct rte_eth_dev_data *dev_data = pf->dev_data;
5103         struct i40e_tx_queue *txq;
5104         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5105         uint16_t i;
5106         int ret;
5107
5108         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5109                 txq = dev_data->tx_queues[i];
5110                 /* Don't operate the queue if not configured or
5111                  * if starting only per queue */
5112                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5113                         continue;
5114                 if (on)
5115                         ret = i40e_dev_tx_queue_start(dev, i);
5116                 else
5117                         ret = i40e_dev_tx_queue_stop(dev, i);
5118                 if ( ret != I40E_SUCCESS)
5119                         return ret;
5120         }
5121
5122         return I40E_SUCCESS;
5123 }
5124
5125 int
5126 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5127 {
5128         uint32_t reg;
5129         uint16_t j;
5130
5131         /* Wait until the request is finished */
5132         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5133                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5134                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5135                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5136                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5137                         break;
5138         }
5139
5140         if (on) {
5141                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5142                         return I40E_SUCCESS; /* Already on, skip next steps */
5143                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5144         } else {
5145                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5146                         return I40E_SUCCESS; /* Already off, skip next steps */
5147                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5148         }
5149
5150         /* Write the register */
5151         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5152         /* Check the result */
5153         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5154                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5155                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5156                 if (on) {
5157                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5158                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5159                                 break;
5160                 } else {
5161                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5162                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5163                                 break;
5164                 }
5165         }
5166
5167         /* Check if it is timeout */
5168         if (j >= I40E_CHK_Q_ENA_COUNT) {
5169                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5170                             (on ? "enable" : "disable"), q_idx);
5171                 return I40E_ERR_TIMEOUT;
5172         }
5173
5174         return I40E_SUCCESS;
5175 }
5176 /* Switch on or off the rx queues */
5177 static int
5178 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5179 {
5180         struct rte_eth_dev_data *dev_data = pf->dev_data;
5181         struct i40e_rx_queue *rxq;
5182         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5183         uint16_t i;
5184         int ret;
5185
5186         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5187                 rxq = dev_data->rx_queues[i];
5188                 /* Don't operate the queue if not configured or
5189                  * if starting only per queue */
5190                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5191                         continue;
5192                 if (on)
5193                         ret = i40e_dev_rx_queue_start(dev, i);
5194                 else
5195                         ret = i40e_dev_rx_queue_stop(dev, i);
5196                 if (ret != I40E_SUCCESS)
5197                         return ret;
5198         }
5199
5200         return I40E_SUCCESS;
5201 }
5202
5203 /* Switch on or off all the rx/tx queues */
5204 int
5205 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5206 {
5207         int ret;
5208
5209         if (on) {
5210                 /* enable rx queues before enabling tx queues */
5211                 ret = i40e_dev_switch_rx_queues(pf, on);
5212                 if (ret) {
5213                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5214                         return ret;
5215                 }
5216                 ret = i40e_dev_switch_tx_queues(pf, on);
5217         } else {
5218                 /* Stop tx queues before stopping rx queues */
5219                 ret = i40e_dev_switch_tx_queues(pf, on);
5220                 if (ret) {
5221                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5222                         return ret;
5223                 }
5224                 ret = i40e_dev_switch_rx_queues(pf, on);
5225         }
5226
5227         return ret;
5228 }
5229
5230 /* Initialize VSI for TX */
5231 static int
5232 i40e_dev_tx_init(struct i40e_pf *pf)
5233 {
5234         struct rte_eth_dev_data *data = pf->dev_data;
5235         uint16_t i;
5236         uint32_t ret = I40E_SUCCESS;
5237         struct i40e_tx_queue *txq;
5238
5239         for (i = 0; i < data->nb_tx_queues; i++) {
5240                 txq = data->tx_queues[i];
5241                 if (!txq || !txq->q_set)
5242                         continue;
5243                 ret = i40e_tx_queue_init(txq);
5244                 if (ret != I40E_SUCCESS)
5245                         break;
5246         }
5247         if (ret == I40E_SUCCESS)
5248                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5249                                      ->eth_dev);
5250
5251         return ret;
5252 }
5253
5254 /* Initialize VSI for RX */
5255 static int
5256 i40e_dev_rx_init(struct i40e_pf *pf)
5257 {
5258         struct rte_eth_dev_data *data = pf->dev_data;
5259         int ret = I40E_SUCCESS;
5260         uint16_t i;
5261         struct i40e_rx_queue *rxq;
5262
5263         i40e_pf_config_mq_rx(pf);
5264         for (i = 0; i < data->nb_rx_queues; i++) {
5265                 rxq = data->rx_queues[i];
5266                 if (!rxq || !rxq->q_set)
5267                         continue;
5268
5269                 ret = i40e_rx_queue_init(rxq);
5270                 if (ret != I40E_SUCCESS) {
5271                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5272                                     "initialization");
5273                         break;
5274                 }
5275         }
5276         if (ret == I40E_SUCCESS)
5277                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5278                                      ->eth_dev);
5279
5280         return ret;
5281 }
5282
5283 static int
5284 i40e_dev_rxtx_init(struct i40e_pf *pf)
5285 {
5286         int err;
5287
5288         err = i40e_dev_tx_init(pf);
5289         if (err) {
5290                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5291                 return err;
5292         }
5293         err = i40e_dev_rx_init(pf);
5294         if (err) {
5295                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5296                 return err;
5297         }
5298
5299         return err;
5300 }
5301
5302 static int
5303 i40e_vmdq_setup(struct rte_eth_dev *dev)
5304 {
5305         struct rte_eth_conf *conf = &dev->data->dev_conf;
5306         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5307         int i, err, conf_vsis, j, loop;
5308         struct i40e_vsi *vsi;
5309         struct i40e_vmdq_info *vmdq_info;
5310         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5311         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5312
5313         /*
5314          * Disable interrupt to avoid message from VF. Furthermore, it will
5315          * avoid race condition in VSI creation/destroy.
5316          */
5317         i40e_pf_disable_irq0(hw);
5318
5319         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5320                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5321                 return -ENOTSUP;
5322         }
5323
5324         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5325         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5326                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5327                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5328                         pf->max_nb_vmdq_vsi);
5329                 return -ENOTSUP;
5330         }
5331
5332         if (pf->vmdq != NULL) {
5333                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5334                 return 0;
5335         }
5336
5337         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5338                                 sizeof(*vmdq_info) * conf_vsis, 0);
5339
5340         if (pf->vmdq == NULL) {
5341                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5342                 return -ENOMEM;
5343         }
5344
5345         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5346
5347         /* Create VMDQ VSI */
5348         for (i = 0; i < conf_vsis; i++) {
5349                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5350                                 vmdq_conf->enable_loop_back);
5351                 if (vsi == NULL) {
5352                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5353                         err = -1;
5354                         goto err_vsi_setup;
5355                 }
5356                 vmdq_info = &pf->vmdq[i];
5357                 vmdq_info->pf = pf;
5358                 vmdq_info->vsi = vsi;
5359         }
5360         pf->nb_cfg_vmdq_vsi = conf_vsis;
5361
5362         /* Configure Vlan */
5363         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5364         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5365                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5366                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5367                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5368                                         vmdq_conf->pool_map[i].vlan_id, j);
5369
5370                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5371                                                 vmdq_conf->pool_map[i].vlan_id);
5372                                 if (err) {
5373                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5374                                         err = -1;
5375                                         goto err_vsi_setup;
5376                                 }
5377                         }
5378                 }
5379         }
5380
5381         i40e_pf_enable_irq0(hw);
5382
5383         return 0;
5384
5385 err_vsi_setup:
5386         for (i = 0; i < conf_vsis; i++)
5387                 if (pf->vmdq[i].vsi == NULL)
5388                         break;
5389                 else
5390                         i40e_vsi_release(pf->vmdq[i].vsi);
5391
5392         rte_free(pf->vmdq);
5393         pf->vmdq = NULL;
5394         i40e_pf_enable_irq0(hw);
5395         return err;
5396 }
5397
5398 static void
5399 i40e_stat_update_32(struct i40e_hw *hw,
5400                    uint32_t reg,
5401                    bool offset_loaded,
5402                    uint64_t *offset,
5403                    uint64_t *stat)
5404 {
5405         uint64_t new_data;
5406
5407         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5408         if (!offset_loaded)
5409                 *offset = new_data;
5410
5411         if (new_data >= *offset)
5412                 *stat = (uint64_t)(new_data - *offset);
5413         else
5414                 *stat = (uint64_t)((new_data +
5415                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5416 }
5417
5418 static void
5419 i40e_stat_update_48(struct i40e_hw *hw,
5420                    uint32_t hireg,
5421                    uint32_t loreg,
5422                    bool offset_loaded,
5423                    uint64_t *offset,
5424                    uint64_t *stat)
5425 {
5426         uint64_t new_data;
5427
5428         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5429         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5430                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5431
5432         if (!offset_loaded)
5433                 *offset = new_data;
5434
5435         if (new_data >= *offset)
5436                 *stat = new_data - *offset;
5437         else
5438                 *stat = (uint64_t)((new_data +
5439                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5440
5441         *stat &= I40E_48_BIT_MASK;
5442 }
5443
5444 /* Disable IRQ0 */
5445 void
5446 i40e_pf_disable_irq0(struct i40e_hw *hw)
5447 {
5448         /* Disable all interrupt types */
5449         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5450         I40E_WRITE_FLUSH(hw);
5451 }
5452
5453 /* Enable IRQ0 */
5454 void
5455 i40e_pf_enable_irq0(struct i40e_hw *hw)
5456 {
5457         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5458                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5459                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5460                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5461         I40E_WRITE_FLUSH(hw);
5462 }
5463
5464 static void
5465 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5466 {
5467         /* read pending request and disable first */
5468         i40e_pf_disable_irq0(hw);
5469         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5470         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5471                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5472
5473         if (no_queue)
5474                 /* Link no queues with irq0 */
5475                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5476                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5477 }
5478
5479 static void
5480 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5481 {
5482         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5483         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5484         int i;
5485         uint16_t abs_vf_id;
5486         uint32_t index, offset, val;
5487
5488         if (!pf->vfs)
5489                 return;
5490         /**
5491          * Try to find which VF trigger a reset, use absolute VF id to access
5492          * since the reg is global register.
5493          */
5494         for (i = 0; i < pf->vf_num; i++) {
5495                 abs_vf_id = hw->func_caps.vf_base_id + i;
5496                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5497                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5498                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5499                 /* VFR event occured */
5500                 if (val & (0x1 << offset)) {
5501                         int ret;
5502
5503                         /* Clear the event first */
5504                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5505                                                         (0x1 << offset));
5506                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5507                         /**
5508                          * Only notify a VF reset event occured,
5509                          * don't trigger another SW reset
5510                          */
5511                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5512                         if (ret != I40E_SUCCESS)
5513                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5514                 }
5515         }
5516 }
5517
5518 static void
5519 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5520 {
5521         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5522         struct i40e_virtchnl_pf_event event;
5523         int i;
5524
5525         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5526         event.event_data.link_event.link_status =
5527                 dev->data->dev_link.link_status;
5528         event.event_data.link_event.link_speed =
5529                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5530
5531         for (i = 0; i < pf->vf_num; i++)
5532                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5533                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5534 }
5535
5536 static void
5537 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5538 {
5539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5540         struct i40e_arq_event_info info;
5541         uint16_t pending, opcode;
5542         int ret;
5543
5544         info.buf_len = I40E_AQ_BUF_SZ;
5545         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5546         if (!info.msg_buf) {
5547                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5548                 return;
5549         }
5550
5551         pending = 1;
5552         while (pending) {
5553                 ret = i40e_clean_arq_element(hw, &info, &pending);
5554
5555                 if (ret != I40E_SUCCESS) {
5556                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5557                                     "aq_err: %u", hw->aq.asq_last_status);
5558                         break;
5559                 }
5560                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5561
5562                 switch (opcode) {
5563                 case i40e_aqc_opc_send_msg_to_pf:
5564                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5565                         i40e_pf_host_handle_vf_msg(dev,
5566                                         rte_le_to_cpu_16(info.desc.retval),
5567                                         rte_le_to_cpu_32(info.desc.cookie_high),
5568                                         rte_le_to_cpu_32(info.desc.cookie_low),
5569                                         info.msg_buf,
5570                                         info.msg_len);
5571                         break;
5572                 case i40e_aqc_opc_get_link_status:
5573                         ret = i40e_dev_link_update(dev, 0);
5574                         if (!ret)
5575                                 _rte_eth_dev_callback_process(dev,
5576                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5577                         break;
5578                 default:
5579                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5580                                     opcode);
5581                         break;
5582                 }
5583         }
5584         rte_free(info.msg_buf);
5585 }
5586
5587 /**
5588  * Interrupt handler triggered by NIC  for handling
5589  * specific interrupt.
5590  *
5591  * @param handle
5592  *  Pointer to interrupt handle.
5593  * @param param
5594  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5595  *
5596  * @return
5597  *  void
5598  */
5599 static void
5600 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5601                            void *param)
5602 {
5603         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5604         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5605         uint32_t icr0;
5606
5607         /* Disable interrupt */
5608         i40e_pf_disable_irq0(hw);
5609
5610         /* read out interrupt causes */
5611         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5612
5613         /* No interrupt event indicated */
5614         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5615                 PMD_DRV_LOG(INFO, "No interrupt event");
5616                 goto done;
5617         }
5618 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5619         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5620                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5621         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5622                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5623         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5624                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5625         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5626                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5627         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5628                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5629         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5630                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5631         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5632                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5633 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5634
5635         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5636                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5637                 i40e_dev_handle_vfr_event(dev);
5638         }
5639         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5640                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5641                 i40e_dev_handle_aq_msg(dev);
5642         }
5643
5644 done:
5645         /* Enable interrupt */
5646         i40e_pf_enable_irq0(hw);
5647         rte_intr_enable(&(dev->pci_dev->intr_handle));
5648 }
5649
5650 static int
5651 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5652                          struct i40e_macvlan_filter *filter,
5653                          int total)
5654 {
5655         int ele_num, ele_buff_size;
5656         int num, actual_num, i;
5657         uint16_t flags;
5658         int ret = I40E_SUCCESS;
5659         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5660         struct i40e_aqc_add_macvlan_element_data *req_list;
5661
5662         if (filter == NULL  || total == 0)
5663                 return I40E_ERR_PARAM;
5664         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5665         ele_buff_size = hw->aq.asq_buf_size;
5666
5667         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5668         if (req_list == NULL) {
5669                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5670                 return I40E_ERR_NO_MEMORY;
5671         }
5672
5673         num = 0;
5674         do {
5675                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5676                 memset(req_list, 0, ele_buff_size);
5677
5678                 for (i = 0; i < actual_num; i++) {
5679                         (void)rte_memcpy(req_list[i].mac_addr,
5680                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5681                         req_list[i].vlan_tag =
5682                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5683
5684                         switch (filter[num + i].filter_type) {
5685                         case RTE_MAC_PERFECT_MATCH:
5686                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5687                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5688                                 break;
5689                         case RTE_MACVLAN_PERFECT_MATCH:
5690                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5691                                 break;
5692                         case RTE_MAC_HASH_MATCH:
5693                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5694                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5695                                 break;
5696                         case RTE_MACVLAN_HASH_MATCH:
5697                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5698                                 break;
5699                         default:
5700                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5701                                 ret = I40E_ERR_PARAM;
5702                                 goto DONE;
5703                         }
5704
5705                         req_list[i].queue_number = 0;
5706
5707                         req_list[i].flags = rte_cpu_to_le_16(flags);
5708                 }
5709
5710                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5711                                                 actual_num, NULL);
5712                 if (ret != I40E_SUCCESS) {
5713                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5714                         goto DONE;
5715                 }
5716                 num += actual_num;
5717         } while (num < total);
5718
5719 DONE:
5720         rte_free(req_list);
5721         return ret;
5722 }
5723
5724 static int
5725 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5726                             struct i40e_macvlan_filter *filter,
5727                             int total)
5728 {
5729         int ele_num, ele_buff_size;
5730         int num, actual_num, i;
5731         uint16_t flags;
5732         int ret = I40E_SUCCESS;
5733         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5734         struct i40e_aqc_remove_macvlan_element_data *req_list;
5735
5736         if (filter == NULL  || total == 0)
5737                 return I40E_ERR_PARAM;
5738
5739         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5740         ele_buff_size = hw->aq.asq_buf_size;
5741
5742         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5743         if (req_list == NULL) {
5744                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5745                 return I40E_ERR_NO_MEMORY;
5746         }
5747
5748         num = 0;
5749         do {
5750                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5751                 memset(req_list, 0, ele_buff_size);
5752
5753                 for (i = 0; i < actual_num; i++) {
5754                         (void)rte_memcpy(req_list[i].mac_addr,
5755                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5756                         req_list[i].vlan_tag =
5757                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5758
5759                         switch (filter[num + i].filter_type) {
5760                         case RTE_MAC_PERFECT_MATCH:
5761                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5762                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5763                                 break;
5764                         case RTE_MACVLAN_PERFECT_MATCH:
5765                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5766                                 break;
5767                         case RTE_MAC_HASH_MATCH:
5768                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5769                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5770                                 break;
5771                         case RTE_MACVLAN_HASH_MATCH:
5772                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5773                                 break;
5774                         default:
5775                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5776                                 ret = I40E_ERR_PARAM;
5777                                 goto DONE;
5778                         }
5779                         req_list[i].flags = rte_cpu_to_le_16(flags);
5780                 }
5781
5782                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5783                                                 actual_num, NULL);
5784                 if (ret != I40E_SUCCESS) {
5785                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5786                         goto DONE;
5787                 }
5788                 num += actual_num;
5789         } while (num < total);
5790
5791 DONE:
5792         rte_free(req_list);
5793         return ret;
5794 }
5795
5796 /* Find out specific MAC filter */
5797 static struct i40e_mac_filter *
5798 i40e_find_mac_filter(struct i40e_vsi *vsi,
5799                          struct ether_addr *macaddr)
5800 {
5801         struct i40e_mac_filter *f;
5802
5803         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5804                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5805                         return f;
5806         }
5807
5808         return NULL;
5809 }
5810
5811 static bool
5812 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5813                          uint16_t vlan_id)
5814 {
5815         uint32_t vid_idx, vid_bit;
5816
5817         if (vlan_id > ETH_VLAN_ID_MAX)
5818                 return 0;
5819
5820         vid_idx = I40E_VFTA_IDX(vlan_id);
5821         vid_bit = I40E_VFTA_BIT(vlan_id);
5822
5823         if (vsi->vfta[vid_idx] & vid_bit)
5824                 return 1;
5825         else
5826                 return 0;
5827 }
5828
5829 static void
5830 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5831                          uint16_t vlan_id, bool on)
5832 {
5833         uint32_t vid_idx, vid_bit;
5834
5835         if (vlan_id > ETH_VLAN_ID_MAX)
5836                 return;
5837
5838         vid_idx = I40E_VFTA_IDX(vlan_id);
5839         vid_bit = I40E_VFTA_BIT(vlan_id);
5840
5841         if (on)
5842                 vsi->vfta[vid_idx] |= vid_bit;
5843         else
5844                 vsi->vfta[vid_idx] &= ~vid_bit;
5845 }
5846
5847 /**
5848  * Find all vlan options for specific mac addr,
5849  * return with actual vlan found.
5850  */
5851 static inline int
5852 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5853                            struct i40e_macvlan_filter *mv_f,
5854                            int num, struct ether_addr *addr)
5855 {
5856         int i;
5857         uint32_t j, k;
5858
5859         /**
5860          * Not to use i40e_find_vlan_filter to decrease the loop time,
5861          * although the code looks complex.
5862           */
5863         if (num < vsi->vlan_num)
5864                 return I40E_ERR_PARAM;
5865
5866         i = 0;
5867         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5868                 if (vsi->vfta[j]) {
5869                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5870                                 if (vsi->vfta[j] & (1 << k)) {
5871                                         if (i > num - 1) {
5872                                                 PMD_DRV_LOG(ERR, "vlan number "
5873                                                             "not match");
5874                                                 return I40E_ERR_PARAM;
5875                                         }
5876                                         (void)rte_memcpy(&mv_f[i].macaddr,
5877                                                         addr, ETH_ADDR_LEN);
5878                                         mv_f[i].vlan_id =
5879                                                 j * I40E_UINT32_BIT_SIZE + k;
5880                                         i++;
5881                                 }
5882                         }
5883                 }
5884         }
5885         return I40E_SUCCESS;
5886 }
5887
5888 static inline int
5889 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5890                            struct i40e_macvlan_filter *mv_f,
5891                            int num,
5892                            uint16_t vlan)
5893 {
5894         int i = 0;
5895         struct i40e_mac_filter *f;
5896
5897         if (num < vsi->mac_num)
5898                 return I40E_ERR_PARAM;
5899
5900         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5901                 if (i > num - 1) {
5902                         PMD_DRV_LOG(ERR, "buffer number not match");
5903                         return I40E_ERR_PARAM;
5904                 }
5905                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5906                                 ETH_ADDR_LEN);
5907                 mv_f[i].vlan_id = vlan;
5908                 mv_f[i].filter_type = f->mac_info.filter_type;
5909                 i++;
5910         }
5911
5912         return I40E_SUCCESS;
5913 }
5914
5915 static int
5916 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5917 {
5918         int i, j, num;
5919         struct i40e_mac_filter *f;
5920         struct i40e_macvlan_filter *mv_f;
5921         int ret = I40E_SUCCESS;
5922
5923         if (vsi == NULL || vsi->mac_num == 0)
5924                 return I40E_ERR_PARAM;
5925
5926         /* Case that no vlan is set */
5927         if (vsi->vlan_num == 0)
5928                 num = vsi->mac_num;
5929         else
5930                 num = vsi->mac_num * vsi->vlan_num;
5931
5932         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5933         if (mv_f == NULL) {
5934                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5935                 return I40E_ERR_NO_MEMORY;
5936         }
5937
5938         i = 0;
5939         if (vsi->vlan_num == 0) {
5940                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5941                         (void)rte_memcpy(&mv_f[i].macaddr,
5942                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5943                         mv_f[i].filter_type = f->mac_info.filter_type;
5944                         mv_f[i].vlan_id = 0;
5945                         i++;
5946                 }
5947         } else {
5948                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5949                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5950                                         vsi->vlan_num, &f->mac_info.mac_addr);
5951                         if (ret != I40E_SUCCESS)
5952                                 goto DONE;
5953                         for (j = i; j < i + vsi->vlan_num; j++)
5954                                 mv_f[j].filter_type = f->mac_info.filter_type;
5955                         i += vsi->vlan_num;
5956                 }
5957         }
5958
5959         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5960 DONE:
5961         rte_free(mv_f);
5962
5963         return ret;
5964 }
5965
5966 int
5967 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5968 {
5969         struct i40e_macvlan_filter *mv_f;
5970         int mac_num;
5971         int ret = I40E_SUCCESS;
5972
5973         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5974                 return I40E_ERR_PARAM;
5975
5976         /* If it's already set, just return */
5977         if (i40e_find_vlan_filter(vsi,vlan))
5978                 return I40E_SUCCESS;
5979
5980         mac_num = vsi->mac_num;
5981
5982         if (mac_num == 0) {
5983                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5984                 return I40E_ERR_PARAM;
5985         }
5986
5987         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5988
5989         if (mv_f == NULL) {
5990                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5991                 return I40E_ERR_NO_MEMORY;
5992         }
5993
5994         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5995
5996         if (ret != I40E_SUCCESS)
5997                 goto DONE;
5998
5999         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6000
6001         if (ret != I40E_SUCCESS)
6002                 goto DONE;
6003
6004         i40e_set_vlan_filter(vsi, vlan, 1);
6005
6006         vsi->vlan_num++;
6007         ret = I40E_SUCCESS;
6008 DONE:
6009         rte_free(mv_f);
6010         return ret;
6011 }
6012
6013 int
6014 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6015 {
6016         struct i40e_macvlan_filter *mv_f;
6017         int mac_num;
6018         int ret = I40E_SUCCESS;
6019
6020         /**
6021          * Vlan 0 is the generic filter for untagged packets
6022          * and can't be removed.
6023          */
6024         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6025                 return I40E_ERR_PARAM;
6026
6027         /* If can't find it, just return */
6028         if (!i40e_find_vlan_filter(vsi, vlan))
6029                 return I40E_ERR_PARAM;
6030
6031         mac_num = vsi->mac_num;
6032
6033         if (mac_num == 0) {
6034                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6035                 return I40E_ERR_PARAM;
6036         }
6037
6038         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6039
6040         if (mv_f == NULL) {
6041                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6042                 return I40E_ERR_NO_MEMORY;
6043         }
6044
6045         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6046
6047         if (ret != I40E_SUCCESS)
6048                 goto DONE;
6049
6050         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6051
6052         if (ret != I40E_SUCCESS)
6053                 goto DONE;
6054
6055         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6056         if (vsi->vlan_num == 1) {
6057                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6058                 if (ret != I40E_SUCCESS)
6059                         goto DONE;
6060
6061                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6062                 if (ret != I40E_SUCCESS)
6063                         goto DONE;
6064         }
6065
6066         i40e_set_vlan_filter(vsi, vlan, 0);
6067
6068         vsi->vlan_num--;
6069         ret = I40E_SUCCESS;
6070 DONE:
6071         rte_free(mv_f);
6072         return ret;
6073 }
6074
6075 int
6076 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6077 {
6078         struct i40e_mac_filter *f;
6079         struct i40e_macvlan_filter *mv_f;
6080         int i, vlan_num = 0;
6081         int ret = I40E_SUCCESS;
6082
6083         /* If it's add and we've config it, return */
6084         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6085         if (f != NULL)
6086                 return I40E_SUCCESS;
6087         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6088                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6089
6090                 /**
6091                  * If vlan_num is 0, that's the first time to add mac,
6092                  * set mask for vlan_id 0.
6093                  */
6094                 if (vsi->vlan_num == 0) {
6095                         i40e_set_vlan_filter(vsi, 0, 1);
6096                         vsi->vlan_num = 1;
6097                 }
6098                 vlan_num = vsi->vlan_num;
6099         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6100                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6101                 vlan_num = 1;
6102
6103         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6104         if (mv_f == NULL) {
6105                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6106                 return I40E_ERR_NO_MEMORY;
6107         }
6108
6109         for (i = 0; i < vlan_num; i++) {
6110                 mv_f[i].filter_type = mac_filter->filter_type;
6111                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6112                                 ETH_ADDR_LEN);
6113         }
6114
6115         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6116                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6117                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6118                                         &mac_filter->mac_addr);
6119                 if (ret != I40E_SUCCESS)
6120                         goto DONE;
6121         }
6122
6123         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6124         if (ret != I40E_SUCCESS)
6125                 goto DONE;
6126
6127         /* Add the mac addr into mac list */
6128         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6129         if (f == NULL) {
6130                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6131                 ret = I40E_ERR_NO_MEMORY;
6132                 goto DONE;
6133         }
6134         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6135                         ETH_ADDR_LEN);
6136         f->mac_info.filter_type = mac_filter->filter_type;
6137         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6138         vsi->mac_num++;
6139
6140         ret = I40E_SUCCESS;
6141 DONE:
6142         rte_free(mv_f);
6143
6144         return ret;
6145 }
6146
6147 int
6148 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6149 {
6150         struct i40e_mac_filter *f;
6151         struct i40e_macvlan_filter *mv_f;
6152         int i, vlan_num;
6153         enum rte_mac_filter_type filter_type;
6154         int ret = I40E_SUCCESS;
6155
6156         /* Can't find it, return an error */
6157         f = i40e_find_mac_filter(vsi, addr);
6158         if (f == NULL)
6159                 return I40E_ERR_PARAM;
6160
6161         vlan_num = vsi->vlan_num;
6162         filter_type = f->mac_info.filter_type;
6163         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6164                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6165                 if (vlan_num == 0) {
6166                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6167                         return I40E_ERR_PARAM;
6168                 }
6169         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6170                         filter_type == RTE_MAC_HASH_MATCH)
6171                 vlan_num = 1;
6172
6173         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6174         if (mv_f == NULL) {
6175                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6176                 return I40E_ERR_NO_MEMORY;
6177         }
6178
6179         for (i = 0; i < vlan_num; i++) {
6180                 mv_f[i].filter_type = filter_type;
6181                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6182                                 ETH_ADDR_LEN);
6183         }
6184         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6185                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6186                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6187                 if (ret != I40E_SUCCESS)
6188                         goto DONE;
6189         }
6190
6191         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6192         if (ret != I40E_SUCCESS)
6193                 goto DONE;
6194
6195         /* Remove the mac addr into mac list */
6196         TAILQ_REMOVE(&vsi->mac_list, f, next);
6197         rte_free(f);
6198         vsi->mac_num--;
6199
6200         ret = I40E_SUCCESS;
6201 DONE:
6202         rte_free(mv_f);
6203         return ret;
6204 }
6205
6206 /* Configure hash enable flags for RSS */
6207 uint64_t
6208 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6209 {
6210         uint64_t hena = 0;
6211
6212         if (!flags)
6213                 return hena;
6214
6215         if (flags & ETH_RSS_FRAG_IPV4)
6216                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6217         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6218                 if (type == I40E_MAC_X722) {
6219                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6220                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6221                 } else
6222                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6223         }
6224         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6225                 if (type == I40E_MAC_X722) {
6226                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6227                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6228                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6229                 } else
6230                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6231         }
6232         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6233                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6234         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6235                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6236         if (flags & ETH_RSS_FRAG_IPV6)
6237                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6238         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6239                 if (type == I40E_MAC_X722) {
6240                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6241                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6242                 } else
6243                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6244         }
6245         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6246                 if (type == I40E_MAC_X722) {
6247                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6248                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6249                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6250                 } else
6251                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6252         }
6253         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6254                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6255         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6256                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6257         if (flags & ETH_RSS_L2_PAYLOAD)
6258                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6259
6260         return hena;
6261 }
6262
6263 /* Parse the hash enable flags */
6264 uint64_t
6265 i40e_parse_hena(uint64_t flags)
6266 {
6267         uint64_t rss_hf = 0;
6268
6269         if (!flags)
6270                 return rss_hf;
6271         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6272                 rss_hf |= ETH_RSS_FRAG_IPV4;
6273         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6274                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6275 #ifdef X722_SUPPORT
6276         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6277                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6278 #endif
6279         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6280                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6281 #ifdef X722_SUPPORT
6282         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6283                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6284         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6285                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6286 #endif
6287         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6288                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6289         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6290                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6291         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6292                 rss_hf |= ETH_RSS_FRAG_IPV6;
6293         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6294                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6295 #ifdef X722_SUPPORT
6296         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6297                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6298 #endif
6299         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6300                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6301 #ifdef X722_SUPPORT
6302         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6303                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6304         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6305                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6306 #endif
6307         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6308                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6309         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6310                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6311         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6312                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6313
6314         return rss_hf;
6315 }
6316
6317 /* Disable RSS */
6318 static void
6319 i40e_pf_disable_rss(struct i40e_pf *pf)
6320 {
6321         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6322         uint64_t hena;
6323
6324         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6325         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6326         if (hw->mac.type == I40E_MAC_X722)
6327                 hena &= ~I40E_RSS_HENA_ALL_X722;
6328         else
6329                 hena &= ~I40E_RSS_HENA_ALL;
6330         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6331         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6332         I40E_WRITE_FLUSH(hw);
6333 }
6334
6335 static int
6336 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6337 {
6338         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6339         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6340         int ret = 0;
6341
6342         if (!key || key_len == 0) {
6343                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6344                 return 0;
6345         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6346                 sizeof(uint32_t)) {
6347                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6348                 return -EINVAL;
6349         }
6350
6351         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6352                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6353                         (struct i40e_aqc_get_set_rss_key_data *)key;
6354
6355                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6356                 if (ret)
6357                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6358                                      "via AQ");
6359         } else {
6360                 uint32_t *hash_key = (uint32_t *)key;
6361                 uint16_t i;
6362
6363                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6364                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6365                 I40E_WRITE_FLUSH(hw);
6366         }
6367
6368         return ret;
6369 }
6370
6371 static int
6372 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6373 {
6374         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6375         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6376         int ret;
6377
6378         if (!key || !key_len)
6379                 return -EINVAL;
6380
6381         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6382                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6383                         (struct i40e_aqc_get_set_rss_key_data *)key);
6384                 if (ret) {
6385                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6386                         return ret;
6387                 }
6388         } else {
6389                 uint32_t *key_dw = (uint32_t *)key;
6390                 uint16_t i;
6391
6392                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6393                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6394         }
6395         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6396
6397         return 0;
6398 }
6399
6400 static int
6401 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6402 {
6403         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6404         uint64_t rss_hf;
6405         uint64_t hena;
6406         int ret;
6407
6408         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6409                                rss_conf->rss_key_len);
6410         if (ret)
6411                 return ret;
6412
6413         rss_hf = rss_conf->rss_hf;
6414         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6415         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6416         if (hw->mac.type == I40E_MAC_X722)
6417                 hena &= ~I40E_RSS_HENA_ALL_X722;
6418         else
6419                 hena &= ~I40E_RSS_HENA_ALL;
6420         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6421         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6422         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6423         I40E_WRITE_FLUSH(hw);
6424
6425         return 0;
6426 }
6427
6428 static int
6429 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6430                          struct rte_eth_rss_conf *rss_conf)
6431 {
6432         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6433         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6434         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6435         uint64_t hena;
6436
6437         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6438         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6439         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6440                  ? I40E_RSS_HENA_ALL_X722
6441                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6442                 if (rss_hf != 0) /* Enable RSS */
6443                         return -EINVAL;
6444                 return 0; /* Nothing to do */
6445         }
6446         /* RSS enabled */
6447         if (rss_hf == 0) /* Disable RSS */
6448                 return -EINVAL;
6449
6450         return i40e_hw_rss_hash_set(pf, rss_conf);
6451 }
6452
6453 static int
6454 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6455                            struct rte_eth_rss_conf *rss_conf)
6456 {
6457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6458         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6459         uint64_t hena;
6460
6461         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6462                          &rss_conf->rss_key_len);
6463
6464         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6465         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6466         rss_conf->rss_hf = i40e_parse_hena(hena);
6467
6468         return 0;
6469 }
6470
6471 static int
6472 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6473 {
6474         switch (filter_type) {
6475         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6476                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6477                 break;
6478         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6479                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6480                 break;
6481         case RTE_TUNNEL_FILTER_IMAC_TENID:
6482                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6483                 break;
6484         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6485                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6486                 break;
6487         case ETH_TUNNEL_FILTER_IMAC:
6488                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6489                 break;
6490         case ETH_TUNNEL_FILTER_OIP:
6491                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6492                 break;
6493         case ETH_TUNNEL_FILTER_IIP:
6494                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6495                 break;
6496         default:
6497                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6498                 return -EINVAL;
6499         }
6500
6501         return 0;
6502 }
6503
6504 static int
6505 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6506                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6507                         uint8_t add)
6508 {
6509         uint16_t ip_type;
6510         uint32_t ipv4_addr;
6511         uint8_t i, tun_type = 0;
6512         /* internal varialbe to convert ipv6 byte order */
6513         uint32_t convert_ipv6[4];
6514         int val, ret = 0;
6515         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6516         struct i40e_vsi *vsi = pf->main_vsi;
6517         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6518         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6519
6520         cld_filter = rte_zmalloc("tunnel_filter",
6521                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6522                 0);
6523
6524         if (NULL == cld_filter) {
6525                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6526                 return -EINVAL;
6527         }
6528         pfilter = cld_filter;
6529
6530         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6531         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6532
6533         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6534         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6535                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6536                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6537                 rte_memcpy(&pfilter->ipaddr.v4.data,
6538                                 &rte_cpu_to_le_32(ipv4_addr),
6539                                 sizeof(pfilter->ipaddr.v4.data));
6540         } else {
6541                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6542                 for (i = 0; i < 4; i++) {
6543                         convert_ipv6[i] =
6544                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6545                 }
6546                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6547                                 sizeof(pfilter->ipaddr.v6.data));
6548         }
6549
6550         /* check tunneled type */
6551         switch (tunnel_filter->tunnel_type) {
6552         case RTE_TUNNEL_TYPE_VXLAN:
6553                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6554                 break;
6555         case RTE_TUNNEL_TYPE_NVGRE:
6556                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6557                 break;
6558         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6559                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6560                 break;
6561         default:
6562                 /* Other tunnel types is not supported. */
6563                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6564                 rte_free(cld_filter);
6565                 return -EINVAL;
6566         }
6567
6568         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6569                                                 &pfilter->flags);
6570         if (val < 0) {
6571                 rte_free(cld_filter);
6572                 return -EINVAL;
6573         }
6574
6575         pfilter->flags |= rte_cpu_to_le_16(
6576                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6577                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6578         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6579         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6580
6581         if (add)
6582                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6583         else
6584                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6585                                                 cld_filter, 1);
6586
6587         rte_free(cld_filter);
6588         return ret;
6589 }
6590
6591 static int
6592 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6593 {
6594         uint8_t i;
6595
6596         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6597                 if (pf->vxlan_ports[i] == port)
6598                         return i;
6599         }
6600
6601         return -1;
6602 }
6603
6604 static int
6605 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6606 {
6607         int  idx, ret;
6608         uint8_t filter_idx;
6609         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6610
6611         idx = i40e_get_vxlan_port_idx(pf, port);
6612
6613         /* Check if port already exists */
6614         if (idx >= 0) {
6615                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6616                 return -EINVAL;
6617         }
6618
6619         /* Now check if there is space to add the new port */
6620         idx = i40e_get_vxlan_port_idx(pf, 0);
6621         if (idx < 0) {
6622                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6623                         "not adding port %d", port);
6624                 return -ENOSPC;
6625         }
6626
6627         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6628                                         &filter_idx, NULL);
6629         if (ret < 0) {
6630                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6631                 return -1;
6632         }
6633
6634         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6635                          port,  filter_idx);
6636
6637         /* New port: add it and mark its index in the bitmap */
6638         pf->vxlan_ports[idx] = port;
6639         pf->vxlan_bitmap |= (1 << idx);
6640
6641         if (!(pf->flags & I40E_FLAG_VXLAN))
6642                 pf->flags |= I40E_FLAG_VXLAN;
6643
6644         return 0;
6645 }
6646
6647 static int
6648 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6649 {
6650         int idx;
6651         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6652
6653         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6654                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6655                 return -EINVAL;
6656         }
6657
6658         idx = i40e_get_vxlan_port_idx(pf, port);
6659
6660         if (idx < 0) {
6661                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6662                 return -EINVAL;
6663         }
6664
6665         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6666                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6667                 return -1;
6668         }
6669
6670         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6671                         port, idx);
6672
6673         pf->vxlan_ports[idx] = 0;
6674         pf->vxlan_bitmap &= ~(1 << idx);
6675
6676         if (!pf->vxlan_bitmap)
6677                 pf->flags &= ~I40E_FLAG_VXLAN;
6678
6679         return 0;
6680 }
6681
6682 /* Add UDP tunneling port */
6683 static int
6684 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6685                              struct rte_eth_udp_tunnel *udp_tunnel)
6686 {
6687         int ret = 0;
6688         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6689
6690         if (udp_tunnel == NULL)
6691                 return -EINVAL;
6692
6693         switch (udp_tunnel->prot_type) {
6694         case RTE_TUNNEL_TYPE_VXLAN:
6695                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6696                 break;
6697
6698         case RTE_TUNNEL_TYPE_GENEVE:
6699         case RTE_TUNNEL_TYPE_TEREDO:
6700                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6701                 ret = -1;
6702                 break;
6703
6704         default:
6705                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6706                 ret = -1;
6707                 break;
6708         }
6709
6710         return ret;
6711 }
6712
6713 /* Remove UDP tunneling port */
6714 static int
6715 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6716                              struct rte_eth_udp_tunnel *udp_tunnel)
6717 {
6718         int ret = 0;
6719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6720
6721         if (udp_tunnel == NULL)
6722                 return -EINVAL;
6723
6724         switch (udp_tunnel->prot_type) {
6725         case RTE_TUNNEL_TYPE_VXLAN:
6726                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6727                 break;
6728         case RTE_TUNNEL_TYPE_GENEVE:
6729         case RTE_TUNNEL_TYPE_TEREDO:
6730                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6731                 ret = -1;
6732                 break;
6733         default:
6734                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6735                 ret = -1;
6736                 break;
6737         }
6738
6739         return ret;
6740 }
6741
6742 /* Calculate the maximum number of contiguous PF queues that are configured */
6743 static int
6744 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6745 {
6746         struct rte_eth_dev_data *data = pf->dev_data;
6747         int i, num;
6748         struct i40e_rx_queue *rxq;
6749
6750         num = 0;
6751         for (i = 0; i < pf->lan_nb_qps; i++) {
6752                 rxq = data->rx_queues[i];
6753                 if (rxq && rxq->q_set)
6754                         num++;
6755                 else
6756                         break;
6757         }
6758
6759         return num;
6760 }
6761
6762 /* Configure RSS */
6763 static int
6764 i40e_pf_config_rss(struct i40e_pf *pf)
6765 {
6766         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6767         struct rte_eth_rss_conf rss_conf;
6768         uint32_t i, lut = 0;
6769         uint16_t j, num;
6770
6771         /*
6772          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6773          * It's necessary to calulate the actual PF queues that are configured.
6774          */
6775         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6776                 num = i40e_pf_calc_configured_queues_num(pf);
6777         else
6778                 num = pf->dev_data->nb_rx_queues;
6779
6780         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6781         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6782                         num);
6783
6784         if (num == 0) {
6785                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6786                 return -ENOTSUP;
6787         }
6788
6789         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6790                 if (j == num)
6791                         j = 0;
6792                 lut = (lut << 8) | (j & ((0x1 <<
6793                         hw->func_caps.rss_table_entry_width) - 1));
6794                 if ((i & 3) == 3)
6795                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6796         }
6797
6798         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6799         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6800                 i40e_pf_disable_rss(pf);
6801                 return 0;
6802         }
6803         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6804                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6805                 /* Random default keys */
6806                 static uint32_t rss_key_default[] = {0x6b793944,
6807                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6808                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6809                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6810
6811                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6812                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6813                                                         sizeof(uint32_t);
6814         }
6815
6816         return i40e_hw_rss_hash_set(pf, &rss_conf);
6817 }
6818
6819 static int
6820 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6821                                struct rte_eth_tunnel_filter_conf *filter)
6822 {
6823         if (pf == NULL || filter == NULL) {
6824                 PMD_DRV_LOG(ERR, "Invalid parameter");
6825                 return -EINVAL;
6826         }
6827
6828         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6829                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6830                 return -EINVAL;
6831         }
6832
6833         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6834                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6835                 return -EINVAL;
6836         }
6837
6838         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6839                 (is_zero_ether_addr(&filter->outer_mac))) {
6840                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6841                 return -EINVAL;
6842         }
6843
6844         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6845                 (is_zero_ether_addr(&filter->inner_mac))) {
6846                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6847                 return -EINVAL;
6848         }
6849
6850         return 0;
6851 }
6852
6853 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6854 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6855 static int
6856 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6857 {
6858         uint32_t val, reg;
6859         int ret = -EINVAL;
6860
6861         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6862         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6863
6864         if (len == 3) {
6865                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6866         } else if (len == 4) {
6867                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6868         } else {
6869                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6870                 return ret;
6871         }
6872
6873         if (reg != val) {
6874                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6875                                                    reg, NULL);
6876                 if (ret != 0)
6877                         return ret;
6878         } else {
6879                 ret = 0;
6880         }
6881         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6882                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6883
6884         return ret;
6885 }
6886
6887 static int
6888 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6889 {
6890         int ret = -EINVAL;
6891
6892         if (!hw || !cfg)
6893                 return -EINVAL;
6894
6895         switch (cfg->cfg_type) {
6896         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6897                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6898                 break;
6899         default:
6900                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6901                 break;
6902         }
6903
6904         return ret;
6905 }
6906
6907 static int
6908 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6909                                enum rte_filter_op filter_op,
6910                                void *arg)
6911 {
6912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6913         int ret = I40E_ERR_PARAM;
6914
6915         switch (filter_op) {
6916         case RTE_ETH_FILTER_SET:
6917                 ret = i40e_dev_global_config_set(hw,
6918                         (struct rte_eth_global_cfg *)arg);
6919                 break;
6920         default:
6921                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6922                 break;
6923         }
6924
6925         return ret;
6926 }
6927
6928 static int
6929 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6930                           enum rte_filter_op filter_op,
6931                           void *arg)
6932 {
6933         struct rte_eth_tunnel_filter_conf *filter;
6934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6935         int ret = I40E_SUCCESS;
6936
6937         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6938
6939         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6940                 return I40E_ERR_PARAM;
6941
6942         switch (filter_op) {
6943         case RTE_ETH_FILTER_NOP:
6944                 if (!(pf->flags & I40E_FLAG_VXLAN))
6945                         ret = I40E_NOT_SUPPORTED;
6946                 break;
6947         case RTE_ETH_FILTER_ADD:
6948                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6949                 break;
6950         case RTE_ETH_FILTER_DELETE:
6951                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6952                 break;
6953         default:
6954                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6955                 ret = I40E_ERR_PARAM;
6956                 break;
6957         }
6958
6959         return ret;
6960 }
6961
6962 static int
6963 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6964 {
6965         int ret = 0;
6966         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6967
6968         /* RSS setup */
6969         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6970                 ret = i40e_pf_config_rss(pf);
6971         else
6972                 i40e_pf_disable_rss(pf);
6973
6974         return ret;
6975 }
6976
6977 /* Get the symmetric hash enable configurations per port */
6978 static void
6979 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6980 {
6981         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6982
6983         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6984 }
6985
6986 /* Set the symmetric hash enable configurations per port */
6987 static void
6988 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6989 {
6990         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6991
6992         if (enable > 0) {
6993                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6994                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6995                                                         "been enabled");
6996                         return;
6997                 }
6998                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6999         } else {
7000                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7001                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7002                                                         "been disabled");
7003                         return;
7004                 }
7005                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7006         }
7007         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7008         I40E_WRITE_FLUSH(hw);
7009 }
7010
7011 /*
7012  * Get global configurations of hash function type and symmetric hash enable
7013  * per flow type (pctype). Note that global configuration means it affects all
7014  * the ports on the same NIC.
7015  */
7016 static int
7017 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7018                                    struct rte_eth_hash_global_conf *g_cfg)
7019 {
7020         uint32_t reg, mask = I40E_FLOW_TYPES;
7021         uint16_t i;
7022         enum i40e_filter_pctype pctype;
7023
7024         memset(g_cfg, 0, sizeof(*g_cfg));
7025         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7026         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7027                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7028         else
7029                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7030         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7031                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7032
7033         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7034                 if (!(mask & (1UL << i)))
7035                         continue;
7036                 mask &= ~(1UL << i);
7037                 /* Bit set indicats the coresponding flow type is supported */
7038                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7039                 /* if flowtype is invalid, continue */
7040                 if (!I40E_VALID_FLOW(i))
7041                         continue;
7042                 pctype = i40e_flowtype_to_pctype(i);
7043                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7044                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7045                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7046         }
7047
7048         return 0;
7049 }
7050
7051 static int
7052 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7053 {
7054         uint32_t i;
7055         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7056
7057         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7058                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7059                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7060                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7061                                                 g_cfg->hash_func);
7062                 return -EINVAL;
7063         }
7064
7065         /*
7066          * As i40e supports less than 32 flow types, only first 32 bits need to
7067          * be checked.
7068          */
7069         mask0 = g_cfg->valid_bit_mask[0];
7070         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7071                 if (i == 0) {
7072                         /* Check if any unsupported flow type configured */
7073                         if ((mask0 | i40e_mask) ^ i40e_mask)
7074                                 goto mask_err;
7075                 } else {
7076                         if (g_cfg->valid_bit_mask[i])
7077                                 goto mask_err;
7078                 }
7079         }
7080
7081         return 0;
7082
7083 mask_err:
7084         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7085
7086         return -EINVAL;
7087 }
7088
7089 /*
7090  * Set global configurations of hash function type and symmetric hash enable
7091  * per flow type (pctype). Note any modifying global configuration will affect
7092  * all the ports on the same NIC.
7093  */
7094 static int
7095 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7096                                    struct rte_eth_hash_global_conf *g_cfg)
7097 {
7098         int ret;
7099         uint16_t i;
7100         uint32_t reg;
7101         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7102         enum i40e_filter_pctype pctype;
7103
7104         /* Check the input parameters */
7105         ret = i40e_hash_global_config_check(g_cfg);
7106         if (ret < 0)
7107                 return ret;
7108
7109         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7110                 if (!(mask0 & (1UL << i)))
7111                         continue;
7112                 mask0 &= ~(1UL << i);
7113                 /* if flowtype is invalid, continue */
7114                 if (!I40E_VALID_FLOW(i))
7115                         continue;
7116                 pctype = i40e_flowtype_to_pctype(i);
7117                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7118                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7119                 if (hw->mac.type == I40E_MAC_X722) {
7120                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7121                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7122                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7123                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7124                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7125                                   reg);
7126                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7127                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7128                                   reg);
7129                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7130                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7131                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7132                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7133                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7134                                   reg);
7135                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7136                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7137                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7138                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7139                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7140                                   reg);
7141                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7142                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7143                                   reg);
7144                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7145                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7146                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7147                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7148                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7149                                   reg);
7150                         } else {
7151                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7152                                   reg);
7153                         }
7154                 } else {
7155                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7156                 }
7157         }
7158
7159         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7160         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7161                 /* Toeplitz */
7162                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7163                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7164                                                                 "Toeplitz");
7165                         goto out;
7166                 }
7167                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7168         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7169                 /* Simple XOR */
7170                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7171                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7172                                                         "Simple XOR");
7173                         goto out;
7174                 }
7175                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7176         } else
7177                 /* Use the default, and keep it as it is */
7178                 goto out;
7179
7180         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7181
7182 out:
7183         I40E_WRITE_FLUSH(hw);
7184
7185         return 0;
7186 }
7187
7188 /**
7189  * Valid input sets for hash and flow director filters per PCTYPE
7190  */
7191 static uint64_t
7192 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7193                 enum rte_filter_type filter)
7194 {
7195         uint64_t valid;
7196
7197         static const uint64_t valid_hash_inset_table[] = {
7198                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7199                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7200                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7201                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7202                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7203                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7204                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7205                         I40E_INSET_FLEX_PAYLOAD,
7206                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7207                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7208                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7209                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7210                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7211                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7212                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7213                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7214                         I40E_INSET_FLEX_PAYLOAD,
7215 #ifdef X722_SUPPORT
7216                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7217                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7218                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7219                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7220                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7221                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7222                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7223                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7224                         I40E_INSET_FLEX_PAYLOAD,
7225                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7226                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7227                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7228                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7229                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7230                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7231                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7232                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7233                         I40E_INSET_FLEX_PAYLOAD,
7234 #endif
7235                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7236                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7237                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7238                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7239                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7240                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7241                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7242                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7243                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7244 #ifdef X722_SUPPORT
7245                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7246                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7247                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7248                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7249                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7250                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7251                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7252                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7253                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7254 #endif
7255                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7256                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7257                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7258                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7259                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7260                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7261                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7262                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7263                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7264                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7265                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7266                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7267                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7268                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7269                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7270                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7271                         I40E_INSET_FLEX_PAYLOAD,
7272                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7273                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7274                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7275                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7276                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7277                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7278                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7279                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7280                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7281                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7282                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7283                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7284                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7285                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7286                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7287                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7288 #ifdef X722_SUPPORT
7289                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7290                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7291                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7292                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7293                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7294                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7295                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7296                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7297                         I40E_INSET_FLEX_PAYLOAD,
7298                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7299                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7300                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7301                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7302                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7303                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7304                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7305                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7306                         I40E_INSET_FLEX_PAYLOAD,
7307 #endif
7308                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7309                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7310                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7311                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7312                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7313                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7314                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7315                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7316                         I40E_INSET_FLEX_PAYLOAD,
7317 #ifdef X722_SUPPORT
7318                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7319                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7320                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7321                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7322                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7323                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7324                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7325                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7326                         I40E_INSET_FLEX_PAYLOAD,
7327 #endif
7328                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7329                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7330                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7331                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7332                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7333                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7334                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7335                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7336                         I40E_INSET_FLEX_PAYLOAD,
7337                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7338                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7339                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7340                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7341                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7342                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7343                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7344                         I40E_INSET_FLEX_PAYLOAD,
7345                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7346                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7347                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7348                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7349                         I40E_INSET_FLEX_PAYLOAD,
7350         };
7351
7352         /**
7353          * Flow director supports only fields defined in
7354          * union rte_eth_fdir_flow.
7355          */
7356         static const uint64_t valid_fdir_inset_table[] = {
7357                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7358                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7359                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7360                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7361                 I40E_INSET_IPV4_TTL,
7362                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7363                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7364                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7365                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7366                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7367 #ifdef X722_SUPPORT
7368                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7369                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7370                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7371                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7372                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7373                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7374                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7375                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7376                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7377                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7378 #endif
7379                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7380                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7381                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7382                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7383                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7384 #ifdef X722_SUPPORT
7385                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7386                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7387                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7388                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7389                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7390 #endif
7391                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7392                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7393                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7394                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7395                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7396                 I40E_INSET_SCTP_VT,
7397                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7398                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7399                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7400                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7401                 I40E_INSET_IPV4_TTL,
7402                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7403                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7404                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7405                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7406                 I40E_INSET_IPV6_HOP_LIMIT,
7407                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7408                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7409                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7410                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7411                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7412 #ifdef X722_SUPPORT
7413                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7414                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7415                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7416                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7417                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7418                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7419                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7420                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7421                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7422                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7423 #endif
7424                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7425                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7426                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7427                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7428                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7429 #ifdef X722_SUPPORT
7430                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7431                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7432                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7433                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7434                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7435 #endif
7436                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7437                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7438                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7439                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7440                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7441                 I40E_INSET_SCTP_VT,
7442                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7443                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7444                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7445                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7446                 I40E_INSET_IPV6_HOP_LIMIT,
7447                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7448                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7449                 I40E_INSET_LAST_ETHER_TYPE,
7450         };
7451
7452         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7453                 return 0;
7454         if (filter == RTE_ETH_FILTER_HASH)
7455                 valid = valid_hash_inset_table[pctype];
7456         else
7457                 valid = valid_fdir_inset_table[pctype];
7458
7459         return valid;
7460 }
7461
7462 /**
7463  * Validate if the input set is allowed for a specific PCTYPE
7464  */
7465 static int
7466 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7467                 enum rte_filter_type filter, uint64_t inset)
7468 {
7469         uint64_t valid;
7470
7471         valid = i40e_get_valid_input_set(pctype, filter);
7472         if (inset & (~valid))
7473                 return -EINVAL;
7474
7475         return 0;
7476 }
7477
7478 /* default input set fields combination per pctype */
7479 static uint64_t
7480 i40e_get_default_input_set(uint16_t pctype)
7481 {
7482         static const uint64_t default_inset_table[] = {
7483                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7484                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7485                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7486                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7487                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7488 #ifdef X722_SUPPORT
7489                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7490                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7491                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7492                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7493                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7494                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7495 #endif
7496                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7497                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7498                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7499 #ifdef X722_SUPPORT
7500                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7501                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7502                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7503 #endif
7504                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7505                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7506                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7507                         I40E_INSET_SCTP_VT,
7508                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7509                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7510                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7511                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7512                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7513                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7514                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7515 #ifdef X722_SUPPORT
7516                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7517                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7518                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7519                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7520                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7521                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7522 #endif
7523                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7524                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7525                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7526 #ifdef X722_SUPPORT
7527                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7528                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7529                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7530 #endif
7531                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7532                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7533                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7534                         I40E_INSET_SCTP_VT,
7535                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7536                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7537                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7538                         I40E_INSET_LAST_ETHER_TYPE,
7539         };
7540
7541         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7542                 return 0;
7543
7544         return default_inset_table[pctype];
7545 }
7546
7547 /**
7548  * Parse the input set from index to logical bit masks
7549  */
7550 static int
7551 i40e_parse_input_set(uint64_t *inset,
7552                      enum i40e_filter_pctype pctype,
7553                      enum rte_eth_input_set_field *field,
7554                      uint16_t size)
7555 {
7556         uint16_t i, j;
7557         int ret = -EINVAL;
7558
7559         static const struct {
7560                 enum rte_eth_input_set_field field;
7561                 uint64_t inset;
7562         } inset_convert_table[] = {
7563                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7564                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7565                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7566                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7567                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7568                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7569                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7570                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7571                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7572                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7573                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7574                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7575                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7576                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7577                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7578                         I40E_INSET_IPV6_NEXT_HDR},
7579                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7580                         I40E_INSET_IPV6_HOP_LIMIT},
7581                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7582                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7583                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7584                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7585                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7586                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7587                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7588                         I40E_INSET_SCTP_VT},
7589                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7590                         I40E_INSET_TUNNEL_DMAC},
7591                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7592                         I40E_INSET_VLAN_TUNNEL},
7593                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7594                         I40E_INSET_TUNNEL_ID},
7595                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7596                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7597                         I40E_INSET_FLEX_PAYLOAD_W1},
7598                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7599                         I40E_INSET_FLEX_PAYLOAD_W2},
7600                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7601                         I40E_INSET_FLEX_PAYLOAD_W3},
7602                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7603                         I40E_INSET_FLEX_PAYLOAD_W4},
7604                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7605                         I40E_INSET_FLEX_PAYLOAD_W5},
7606                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7607                         I40E_INSET_FLEX_PAYLOAD_W6},
7608                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7609                         I40E_INSET_FLEX_PAYLOAD_W7},
7610                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7611                         I40E_INSET_FLEX_PAYLOAD_W8},
7612         };
7613
7614         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7615                 return ret;
7616
7617         /* Only one item allowed for default or all */
7618         if (size == 1) {
7619                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7620                         *inset = i40e_get_default_input_set(pctype);
7621                         return 0;
7622                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7623                         *inset = I40E_INSET_NONE;
7624                         return 0;
7625                 }
7626         }
7627
7628         for (i = 0, *inset = 0; i < size; i++) {
7629                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7630                         if (field[i] == inset_convert_table[j].field) {
7631                                 *inset |= inset_convert_table[j].inset;
7632                                 break;
7633                         }
7634                 }
7635
7636                 /* It contains unsupported input set, return immediately */
7637                 if (j == RTE_DIM(inset_convert_table))
7638                         return ret;
7639         }
7640
7641         return 0;
7642 }
7643
7644 /**
7645  * Translate the input set from bit masks to register aware bit masks
7646  * and vice versa
7647  */
7648 static uint64_t
7649 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7650 {
7651         uint64_t val = 0;
7652         uint16_t i;
7653
7654         struct inset_map {
7655                 uint64_t inset;
7656                 uint64_t inset_reg;
7657         };
7658
7659         static const struct inset_map inset_map_common[] = {
7660                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7661                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7662                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7663                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7664                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7665                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7666                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7667                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7668                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7669                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7670                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7671                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7672                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7673                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7674                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7675                 {I40E_INSET_TUNNEL_DMAC,
7676                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7677                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7678                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7679                 {I40E_INSET_TUNNEL_SRC_PORT,
7680                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7681                 {I40E_INSET_TUNNEL_DST_PORT,
7682                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7683                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7684                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7685                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7686                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7687                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7688                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7689                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7690                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7691                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7692         };
7693
7694     /* some different registers map in x722*/
7695         static const struct inset_map inset_map_diff_x722[] = {
7696                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7697                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7698                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7699                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7700         };
7701
7702         static const struct inset_map inset_map_diff_not_x722[] = {
7703                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7704                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7705                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7706                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7707         };
7708
7709         if (input == 0)
7710                 return val;
7711
7712         /* Translate input set to register aware inset */
7713         if (type == I40E_MAC_X722) {
7714                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7715                         if (input & inset_map_diff_x722[i].inset)
7716                                 val |= inset_map_diff_x722[i].inset_reg;
7717                 }
7718         } else {
7719                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7720                         if (input & inset_map_diff_not_x722[i].inset)
7721                                 val |= inset_map_diff_not_x722[i].inset_reg;
7722                 }
7723         }
7724
7725         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7726                 if (input & inset_map_common[i].inset)
7727                         val |= inset_map_common[i].inset_reg;
7728         }
7729
7730         return val;
7731 }
7732
7733 static int
7734 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7735 {
7736         uint8_t i, idx = 0;
7737         uint64_t inset_need_mask = inset;
7738
7739         static const struct {
7740                 uint64_t inset;
7741                 uint32_t mask;
7742         } inset_mask_map[] = {
7743                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7744                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7745                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7746                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7747                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7748                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7749                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7750                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7751         };
7752
7753         if (!inset || !mask || !nb_elem)
7754                 return 0;
7755
7756         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7757                 /* Clear the inset bit, if no MASK is required,
7758                  * for example proto + ttl
7759                  */
7760                 if ((inset & inset_mask_map[i].inset) ==
7761                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7762                         inset_need_mask &= ~inset_mask_map[i].inset;
7763                 if (!inset_need_mask)
7764                         return 0;
7765         }
7766         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7767                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7768                     inset_mask_map[i].inset) {
7769                         if (idx >= nb_elem) {
7770                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7771                                 return -EINVAL;
7772                         }
7773                         mask[idx] = inset_mask_map[i].mask;
7774                         idx++;
7775                 }
7776         }
7777
7778         return idx;
7779 }
7780
7781 static void
7782 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7783 {
7784         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7785
7786         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7787         if (reg != val)
7788                 i40e_write_rx_ctl(hw, addr, val);
7789         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7790                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7791 }
7792
7793 static void
7794 i40e_filter_input_set_init(struct i40e_pf *pf)
7795 {
7796         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7797         enum i40e_filter_pctype pctype;
7798         uint64_t input_set, inset_reg;
7799         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7800         int num, i;
7801
7802         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7803              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7804                 if (hw->mac.type == I40E_MAC_X722) {
7805                         if (!I40E_VALID_PCTYPE_X722(pctype))
7806                                 continue;
7807                 } else {
7808                         if (!I40E_VALID_PCTYPE(pctype))
7809                                 continue;
7810                 }
7811
7812                 input_set = i40e_get_default_input_set(pctype);
7813
7814                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7815                                                    I40E_INSET_MASK_NUM_REG);
7816                 if (num < 0)
7817                         return;
7818                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7819                                         input_set);
7820
7821                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7822                                       (uint32_t)(inset_reg & UINT32_MAX));
7823                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7824                                      (uint32_t)((inset_reg >>
7825                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7826                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7827                                       (uint32_t)(inset_reg & UINT32_MAX));
7828                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7829                                      (uint32_t)((inset_reg >>
7830                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7831
7832                 for (i = 0; i < num; i++) {
7833                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7834                                              mask_reg[i]);
7835                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7836                                              mask_reg[i]);
7837                 }
7838                 /*clear unused mask registers of the pctype */
7839                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7840                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7841                                              0);
7842                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7843                                              0);
7844                 }
7845                 I40E_WRITE_FLUSH(hw);
7846
7847                 /* store the default input set */
7848                 pf->hash_input_set[pctype] = input_set;
7849                 pf->fdir.input_set[pctype] = input_set;
7850         }
7851 }
7852
7853 int
7854 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7855                          struct rte_eth_input_set_conf *conf)
7856 {
7857         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7858         enum i40e_filter_pctype pctype;
7859         uint64_t input_set, inset_reg = 0;
7860         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7861         int ret, i, num;
7862
7863         if (!conf) {
7864                 PMD_DRV_LOG(ERR, "Invalid pointer");
7865                 return -EFAULT;
7866         }
7867         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7868             conf->op != RTE_ETH_INPUT_SET_ADD) {
7869                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7870                 return -EINVAL;
7871         }
7872
7873         if (!I40E_VALID_FLOW(conf->flow_type)) {
7874                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7875                 return -EINVAL;
7876         }
7877
7878         if (hw->mac.type == I40E_MAC_X722) {
7879                 /* get translated pctype value in fd pctype register */
7880                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7881                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7882                         conf->flow_type)));
7883         } else
7884                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7885
7886         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7887                                    conf->inset_size);
7888         if (ret) {
7889                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7890                 return -EINVAL;
7891         }
7892         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7893                                     input_set) != 0) {
7894                 PMD_DRV_LOG(ERR, "Invalid input set");
7895                 return -EINVAL;
7896         }
7897         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7898                 /* get inset value in register */
7899                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7900                 inset_reg <<= I40E_32_BIT_WIDTH;
7901                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7902                 input_set |= pf->hash_input_set[pctype];
7903         }
7904         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7905                                            I40E_INSET_MASK_NUM_REG);
7906         if (num < 0)
7907                 return -EINVAL;
7908
7909         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7910
7911         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7912                               (uint32_t)(inset_reg & UINT32_MAX));
7913         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7914                              (uint32_t)((inset_reg >>
7915                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7916
7917         for (i = 0; i < num; i++)
7918                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7919                                      mask_reg[i]);
7920         /*clear unused mask registers of the pctype */
7921         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7922                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7923                                      0);
7924         I40E_WRITE_FLUSH(hw);
7925
7926         pf->hash_input_set[pctype] = input_set;
7927         return 0;
7928 }
7929
7930 int
7931 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7932                          struct rte_eth_input_set_conf *conf)
7933 {
7934         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7935         enum i40e_filter_pctype pctype;
7936         uint64_t input_set, inset_reg = 0;
7937         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7938         int ret, i, num;
7939
7940         if (!hw || !conf) {
7941                 PMD_DRV_LOG(ERR, "Invalid pointer");
7942                 return -EFAULT;
7943         }
7944         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7945             conf->op != RTE_ETH_INPUT_SET_ADD) {
7946                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7947                 return -EINVAL;
7948         }
7949
7950         if (!I40E_VALID_FLOW(conf->flow_type)) {
7951                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7952                 return -EINVAL;
7953         }
7954
7955         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7956
7957         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7958                                    conf->inset_size);
7959         if (ret) {
7960                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7961                 return -EINVAL;
7962         }
7963         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7964                                     input_set) != 0) {
7965                 PMD_DRV_LOG(ERR, "Invalid input set");
7966                 return -EINVAL;
7967         }
7968
7969         /* get inset value in register */
7970         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7971         inset_reg <<= I40E_32_BIT_WIDTH;
7972         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7973
7974         /* Can not change the inset reg for flex payload for fdir,
7975          * it is done by writing I40E_PRTQF_FD_FLXINSET
7976          * in i40e_set_flex_mask_on_pctype.
7977          */
7978         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7979                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7980         else
7981                 input_set |= pf->fdir.input_set[pctype];
7982         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7983                                            I40E_INSET_MASK_NUM_REG);
7984         if (num < 0)
7985                 return -EINVAL;
7986
7987         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7988
7989         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7990                               (uint32_t)(inset_reg & UINT32_MAX));
7991         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7992                              (uint32_t)((inset_reg >>
7993                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7994
7995         for (i = 0; i < num; i++)
7996                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7997                                      mask_reg[i]);
7998         /*clear unused mask registers of the pctype */
7999         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8000                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8001                                      0);
8002         I40E_WRITE_FLUSH(hw);
8003
8004         pf->fdir.input_set[pctype] = input_set;
8005         return 0;
8006 }
8007
8008 static int
8009 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8010 {
8011         int ret = 0;
8012
8013         if (!hw || !info) {
8014                 PMD_DRV_LOG(ERR, "Invalid pointer");
8015                 return -EFAULT;
8016         }
8017
8018         switch (info->info_type) {
8019         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8020                 i40e_get_symmetric_hash_enable_per_port(hw,
8021                                         &(info->info.enable));
8022                 break;
8023         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8024                 ret = i40e_get_hash_filter_global_config(hw,
8025                                 &(info->info.global_conf));
8026                 break;
8027         default:
8028                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8029                                                         info->info_type);
8030                 ret = -EINVAL;
8031                 break;
8032         }
8033
8034         return ret;
8035 }
8036
8037 static int
8038 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8039 {
8040         int ret = 0;
8041
8042         if (!hw || !info) {
8043                 PMD_DRV_LOG(ERR, "Invalid pointer");
8044                 return -EFAULT;
8045         }
8046
8047         switch (info->info_type) {
8048         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8049                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8050                 break;
8051         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8052                 ret = i40e_set_hash_filter_global_config(hw,
8053                                 &(info->info.global_conf));
8054                 break;
8055         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8056                 ret = i40e_hash_filter_inset_select(hw,
8057                                                &(info->info.input_set_conf));
8058                 break;
8059
8060         default:
8061                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8062                                                         info->info_type);
8063                 ret = -EINVAL;
8064                 break;
8065         }
8066
8067         return ret;
8068 }
8069
8070 /* Operations for hash function */
8071 static int
8072 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8073                       enum rte_filter_op filter_op,
8074                       void *arg)
8075 {
8076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8077         int ret = 0;
8078
8079         switch (filter_op) {
8080         case RTE_ETH_FILTER_NOP:
8081                 break;
8082         case RTE_ETH_FILTER_GET:
8083                 ret = i40e_hash_filter_get(hw,
8084                         (struct rte_eth_hash_filter_info *)arg);
8085                 break;
8086         case RTE_ETH_FILTER_SET:
8087                 ret = i40e_hash_filter_set(hw,
8088                         (struct rte_eth_hash_filter_info *)arg);
8089                 break;
8090         default:
8091                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8092                                                                 filter_op);
8093                 ret = -ENOTSUP;
8094                 break;
8095         }
8096
8097         return ret;
8098 }
8099
8100 /*
8101  * Configure ethertype filter, which can director packet by filtering
8102  * with mac address and ether_type or only ether_type
8103  */
8104 static int
8105 i40e_ethertype_filter_set(struct i40e_pf *pf,
8106                         struct rte_eth_ethertype_filter *filter,
8107                         bool add)
8108 {
8109         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8110         struct i40e_control_filter_stats stats;
8111         uint16_t flags = 0;
8112         int ret;
8113
8114         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8115                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8116                 return -EINVAL;
8117         }
8118         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8119                 filter->ether_type == ETHER_TYPE_IPv6) {
8120                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8121                         " control packet filter.", filter->ether_type);
8122                 return -EINVAL;
8123         }
8124         if (filter->ether_type == ETHER_TYPE_VLAN)
8125                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8126                         " not supported.");
8127
8128         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8129                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8130         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8131                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8132         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8133
8134         memset(&stats, 0, sizeof(stats));
8135         ret = i40e_aq_add_rem_control_packet_filter(hw,
8136                         filter->mac_addr.addr_bytes,
8137                         filter->ether_type, flags,
8138                         pf->main_vsi->seid,
8139                         filter->queue, add, &stats, NULL);
8140
8141         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8142                          " mac_etype_used = %u, etype_used = %u,"
8143                          " mac_etype_free = %u, etype_free = %u\n",
8144                          ret, stats.mac_etype_used, stats.etype_used,
8145                          stats.mac_etype_free, stats.etype_free);
8146         if (ret < 0)
8147                 return -ENOSYS;
8148         return 0;
8149 }
8150
8151 /*
8152  * Handle operations for ethertype filter.
8153  */
8154 static int
8155 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8156                                 enum rte_filter_op filter_op,
8157                                 void *arg)
8158 {
8159         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8160         int ret = 0;
8161
8162         if (filter_op == RTE_ETH_FILTER_NOP)
8163                 return ret;
8164
8165         if (arg == NULL) {
8166                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8167                             filter_op);
8168                 return -EINVAL;
8169         }
8170
8171         switch (filter_op) {
8172         case RTE_ETH_FILTER_ADD:
8173                 ret = i40e_ethertype_filter_set(pf,
8174                         (struct rte_eth_ethertype_filter *)arg,
8175                         TRUE);
8176                 break;
8177         case RTE_ETH_FILTER_DELETE:
8178                 ret = i40e_ethertype_filter_set(pf,
8179                         (struct rte_eth_ethertype_filter *)arg,
8180                         FALSE);
8181                 break;
8182         default:
8183                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8184                 ret = -ENOSYS;
8185                 break;
8186         }
8187         return ret;
8188 }
8189
8190 static int
8191 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8192                      enum rte_filter_type filter_type,
8193                      enum rte_filter_op filter_op,
8194                      void *arg)
8195 {
8196         int ret = 0;
8197
8198         if (dev == NULL)
8199                 return -EINVAL;
8200
8201         switch (filter_type) {
8202         case RTE_ETH_FILTER_NONE:
8203                 /* For global configuration */
8204                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8205                 break;
8206         case RTE_ETH_FILTER_HASH:
8207                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8208                 break;
8209         case RTE_ETH_FILTER_MACVLAN:
8210                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8211                 break;
8212         case RTE_ETH_FILTER_ETHERTYPE:
8213                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8214                 break;
8215         case RTE_ETH_FILTER_TUNNEL:
8216                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8217                 break;
8218         case RTE_ETH_FILTER_FDIR:
8219                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8220                 break;
8221         default:
8222                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8223                                                         filter_type);
8224                 ret = -EINVAL;
8225                 break;
8226         }
8227
8228         return ret;
8229 }
8230
8231 /*
8232  * Check and enable Extended Tag.
8233  * Enabling Extended Tag is important for 40G performance.
8234  */
8235 static void
8236 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8237 {
8238         uint32_t buf = 0;
8239         int ret;
8240
8241         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8242                                       PCI_DEV_CAP_REG);
8243         if (ret < 0) {
8244                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8245                             PCI_DEV_CAP_REG);
8246                 return;
8247         }
8248         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8249                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8250                 return;
8251         }
8252
8253         buf = 0;
8254         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8255                                       PCI_DEV_CTRL_REG);
8256         if (ret < 0) {
8257                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8258                             PCI_DEV_CTRL_REG);
8259                 return;
8260         }
8261         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8262                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8263                 return;
8264         }
8265         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8266         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8267                                        PCI_DEV_CTRL_REG);
8268         if (ret < 0) {
8269                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8270                             PCI_DEV_CTRL_REG);
8271                 return;
8272         }
8273 }
8274
8275 /*
8276  * As some registers wouldn't be reset unless a global hardware reset,
8277  * hardware initialization is needed to put those registers into an
8278  * expected initial state.
8279  */
8280 static void
8281 i40e_hw_init(struct rte_eth_dev *dev)
8282 {
8283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8284
8285         i40e_enable_extended_tag(dev);
8286
8287         /* clear the PF Queue Filter control register */
8288         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8289
8290         /* Disable symmetric hash per port */
8291         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8292 }
8293
8294 enum i40e_filter_pctype
8295 i40e_flowtype_to_pctype(uint16_t flow_type)
8296 {
8297         static const enum i40e_filter_pctype pctype_table[] = {
8298                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8299                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8300                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8301                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8302                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8303                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8304                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8305                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8306                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8307                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8308                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8309                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8310                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8311                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8312                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8313                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8314                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8315                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8316                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8317         };
8318
8319         return pctype_table[flow_type];
8320 }
8321
8322 uint16_t
8323 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8324 {
8325         static const uint16_t flowtype_table[] = {
8326                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8327                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8328                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8329 #ifdef X722_SUPPORT
8330                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8331                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8332                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8333                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8334 #endif
8335                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8336                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8337 #ifdef X722_SUPPORT
8338                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8339                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8340 #endif
8341                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8342                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8343                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8344                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8345                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8346                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8347                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8348 #ifdef X722_SUPPORT
8349                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8350                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8351                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8352                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8353 #endif
8354                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8355                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8356 #ifdef X722_SUPPORT
8357                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8358                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8359 #endif
8360                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8361                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8362                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8363                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8364                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8365         };
8366
8367         return flowtype_table[pctype];
8368 }
8369
8370 /*
8371  * On X710, performance number is far from the expectation on recent firmware
8372  * versions; on XL710, performance number is also far from the expectation on
8373  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8374  * mode is enabled and port MAC address is equal to the packet destination MAC
8375  * address. The fix for this issue may not be integrated in the following
8376  * firmware version. So the workaround in software driver is needed. It needs
8377  * to modify the initial values of 3 internal only registers for both X710 and
8378  * XL710. Note that the values for X710 or XL710 could be different, and the
8379  * workaround can be removed when it is fixed in firmware in the future.
8380  */
8381
8382 /* For both X710 and XL710 */
8383 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
8384 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
8385 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
8386
8387 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8388 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8389
8390 /* For X722 */
8391 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8392 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8393
8394 /* For X710 */
8395 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8396 /* For XL710 */
8397 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8398 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8399
8400 static int
8401 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8402 {
8403         enum i40e_status_code status;
8404         struct i40e_aq_get_phy_abilities_resp phy_ab;
8405         int ret = -ENOTSUP;
8406
8407         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8408                                               NULL);
8409
8410         if (status)
8411                 return ret;
8412
8413         return 0;
8414 }
8415
8416 static void
8417 i40e_configure_registers(struct i40e_hw *hw)
8418 {
8419         static struct {
8420                 uint32_t addr;
8421                 uint64_t val;
8422         } reg_table[] = {
8423                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8424                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8425                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8426         };
8427         uint64_t reg;
8428         uint32_t i;
8429         int ret;
8430
8431         for (i = 0; i < RTE_DIM(reg_table); i++) {
8432                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8433                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8434                                 reg_table[i].val =
8435                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8436                         else /* For X710/XL710/XXV710 */
8437                                 if (hw->aq.fw_maj_ver < 6)
8438                                         reg_table[i].val =
8439                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
8440                                 else
8441                                         reg_table[i].val =
8442                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
8443                 }
8444
8445                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8446                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8447                                 reg_table[i].val =
8448                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8449                         else /* For X710/XL710/XXV710 */
8450                                 reg_table[i].val =
8451                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8452                 }
8453
8454                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8455                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8456                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8457                                 reg_table[i].val =
8458                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8459                         else /* For X710 */
8460                                 reg_table[i].val =
8461                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8462                 }
8463
8464                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8465                                                         &reg, NULL);
8466                 if (ret < 0) {
8467                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8468                                                         reg_table[i].addr);
8469                         break;
8470                 }
8471                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8472                                                 reg_table[i].addr, reg);
8473                 if (reg == reg_table[i].val)
8474                         continue;
8475
8476                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8477                                                 reg_table[i].val, NULL);
8478                 if (ret < 0) {
8479                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8480                                 "address of 0x%"PRIx32, reg_table[i].val,
8481                                                         reg_table[i].addr);
8482                         break;
8483                 }
8484                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8485                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8486         }
8487 }
8488
8489 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8490 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8491 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8492 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8493 static int
8494 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8495 {
8496         uint32_t reg;
8497         int ret;
8498
8499         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8500                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8501                 return -EINVAL;
8502         }
8503
8504         /* Configure for double VLAN RX stripping */
8505         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8506         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8507                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8508                 ret = i40e_aq_debug_write_register(hw,
8509                                                    I40E_VSI_TSR(vsi->vsi_id),
8510                                                    reg, NULL);
8511                 if (ret < 0) {
8512                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8513                                     vsi->vsi_id);
8514                         return I40E_ERR_CONFIG;
8515                 }
8516         }
8517
8518         /* Configure for double VLAN TX insertion */
8519         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8520         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8521                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8522                 ret = i40e_aq_debug_write_register(hw,
8523                                                    I40E_VSI_L2TAGSTXVALID(
8524                                                    vsi->vsi_id), reg, NULL);
8525                 if (ret < 0) {
8526                         PMD_DRV_LOG(ERR, "Failed to update "
8527                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8528                         return I40E_ERR_CONFIG;
8529                 }
8530         }
8531
8532         return 0;
8533 }
8534
8535 /**
8536  * i40e_aq_add_mirror_rule
8537  * @hw: pointer to the hardware structure
8538  * @seid: VEB seid to add mirror rule to
8539  * @dst_id: destination vsi seid
8540  * @entries: Buffer which contains the entities to be mirrored
8541  * @count: number of entities contained in the buffer
8542  * @rule_id:the rule_id of the rule to be added
8543  *
8544  * Add a mirror rule for a given veb.
8545  *
8546  **/
8547 static enum i40e_status_code
8548 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8549                         uint16_t seid, uint16_t dst_id,
8550                         uint16_t rule_type, uint16_t *entries,
8551                         uint16_t count, uint16_t *rule_id)
8552 {
8553         struct i40e_aq_desc desc;
8554         struct i40e_aqc_add_delete_mirror_rule cmd;
8555         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8556                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8557                 &desc.params.raw;
8558         uint16_t buff_len;
8559         enum i40e_status_code status;
8560
8561         i40e_fill_default_direct_cmd_desc(&desc,
8562                                           i40e_aqc_opc_add_mirror_rule);
8563         memset(&cmd, 0, sizeof(cmd));
8564
8565         buff_len = sizeof(uint16_t) * count;
8566         desc.datalen = rte_cpu_to_le_16(buff_len);
8567         if (buff_len > 0)
8568                 desc.flags |= rte_cpu_to_le_16(
8569                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8570         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8571                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8572         cmd.num_entries = rte_cpu_to_le_16(count);
8573         cmd.seid = rte_cpu_to_le_16(seid);
8574         cmd.destination = rte_cpu_to_le_16(dst_id);
8575
8576         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8577         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8578         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8579                          "rule_id = %u"
8580                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8581                          hw->aq.asq_last_status, resp->rule_id,
8582                          resp->mirror_rules_used, resp->mirror_rules_free);
8583         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8584
8585         return status;
8586 }
8587
8588 /**
8589  * i40e_aq_del_mirror_rule
8590  * @hw: pointer to the hardware structure
8591  * @seid: VEB seid to add mirror rule to
8592  * @entries: Buffer which contains the entities to be mirrored
8593  * @count: number of entities contained in the buffer
8594  * @rule_id:the rule_id of the rule to be delete
8595  *
8596  * Delete a mirror rule for a given veb.
8597  *
8598  **/
8599 static enum i40e_status_code
8600 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8601                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8602                 uint16_t count, uint16_t rule_id)
8603 {
8604         struct i40e_aq_desc desc;
8605         struct i40e_aqc_add_delete_mirror_rule cmd;
8606         uint16_t buff_len = 0;
8607         enum i40e_status_code status;
8608         void *buff = NULL;
8609
8610         i40e_fill_default_direct_cmd_desc(&desc,
8611                                           i40e_aqc_opc_delete_mirror_rule);
8612         memset(&cmd, 0, sizeof(cmd));
8613         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8614                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8615                                                           I40E_AQ_FLAG_RD));
8616                 cmd.num_entries = count;
8617                 buff_len = sizeof(uint16_t) * count;
8618                 desc.datalen = rte_cpu_to_le_16(buff_len);
8619                 buff = (void *)entries;
8620         } else
8621                 /* rule id is filled in destination field for deleting mirror rule */
8622                 cmd.destination = rte_cpu_to_le_16(rule_id);
8623
8624         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8625                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8626         cmd.seid = rte_cpu_to_le_16(seid);
8627
8628         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8629         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8630
8631         return status;
8632 }
8633
8634 /**
8635  * i40e_mirror_rule_set
8636  * @dev: pointer to the hardware structure
8637  * @mirror_conf: mirror rule info
8638  * @sw_id: mirror rule's sw_id
8639  * @on: enable/disable
8640  *
8641  * set a mirror rule.
8642  *
8643  **/
8644 static int
8645 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8646                         struct rte_eth_mirror_conf *mirror_conf,
8647                         uint8_t sw_id, uint8_t on)
8648 {
8649         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8651         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8652         struct i40e_mirror_rule *parent = NULL;
8653         uint16_t seid, dst_seid, rule_id;
8654         uint16_t i, j = 0;
8655         int ret;
8656
8657         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8658
8659         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8660                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8661                         " without veb or vfs.");
8662                 return -ENOSYS;
8663         }
8664         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8665                 PMD_DRV_LOG(ERR, "mirror table is full.");
8666                 return -ENOSPC;
8667         }
8668         if (mirror_conf->dst_pool > pf->vf_num) {
8669                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8670                                  mirror_conf->dst_pool);
8671                 return -EINVAL;
8672         }
8673
8674         seid = pf->main_vsi->veb->seid;
8675
8676         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8677                 if (sw_id <= it->index) {
8678                         mirr_rule = it;
8679                         break;
8680                 }
8681                 parent = it;
8682         }
8683         if (mirr_rule && sw_id == mirr_rule->index) {
8684                 if (on) {
8685                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8686                         return -EEXIST;
8687                 } else {
8688                         ret = i40e_aq_del_mirror_rule(hw, seid,
8689                                         mirr_rule->rule_type,
8690                                         mirr_rule->entries,
8691                                         mirr_rule->num_entries, mirr_rule->id);
8692                         if (ret < 0) {
8693                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8694                                                    " ret = %d, aq_err = %d.",
8695                                                    ret, hw->aq.asq_last_status);
8696                                 return -ENOSYS;
8697                         }
8698                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8699                         rte_free(mirr_rule);
8700                         pf->nb_mirror_rule--;
8701                         return 0;
8702                 }
8703         } else if (!on) {
8704                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8705                 return -ENOENT;
8706         }
8707
8708         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8709                                 sizeof(struct i40e_mirror_rule) , 0);
8710         if (!mirr_rule) {
8711                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8712                 return I40E_ERR_NO_MEMORY;
8713         }
8714         switch (mirror_conf->rule_type) {
8715         case ETH_MIRROR_VLAN:
8716                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8717                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8718                                 mirr_rule->entries[j] =
8719                                         mirror_conf->vlan.vlan_id[i];
8720                                 j++;
8721                         }
8722                 }
8723                 if (j == 0) {
8724                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8725                         rte_free(mirr_rule);
8726                         return -EINVAL;
8727                 }
8728                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8729                 break;
8730         case ETH_MIRROR_VIRTUAL_POOL_UP:
8731         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8732                 /* check if the specified pool bit is out of range */
8733                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8734                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8735                         rte_free(mirr_rule);
8736                         return -EINVAL;
8737                 }
8738                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8739                         if (mirror_conf->pool_mask & (1ULL << i)) {
8740                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8741                                 j++;
8742                         }
8743                 }
8744                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8745                         /* add pf vsi to entries */
8746                         mirr_rule->entries[j] = pf->main_vsi_seid;
8747                         j++;
8748                 }
8749                 if (j == 0) {
8750                         PMD_DRV_LOG(ERR, "pool is not specified.");
8751                         rte_free(mirr_rule);
8752                         return -EINVAL;
8753                 }
8754                 /* egress and ingress in aq commands means from switch but not port */
8755                 mirr_rule->rule_type =
8756                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8757                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8758                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8759                 break;
8760         case ETH_MIRROR_UPLINK_PORT:
8761                 /* egress and ingress in aq commands means from switch but not port*/
8762                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8763                 break;
8764         case ETH_MIRROR_DOWNLINK_PORT:
8765                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8766                 break;
8767         default:
8768                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8769                         mirror_conf->rule_type);
8770                 rte_free(mirr_rule);
8771                 return -EINVAL;
8772         }
8773
8774         /* If the dst_pool is equal to vf_num, consider it as PF */
8775         if (mirror_conf->dst_pool == pf->vf_num)
8776                 dst_seid = pf->main_vsi_seid;
8777         else
8778                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8779
8780         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8781                                       mirr_rule->rule_type, mirr_rule->entries,
8782                                       j, &rule_id);
8783         if (ret < 0) {
8784                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8785                                    " ret = %d, aq_err = %d.",
8786                                    ret, hw->aq.asq_last_status);
8787                 rte_free(mirr_rule);
8788                 return -ENOSYS;
8789         }
8790
8791         mirr_rule->index = sw_id;
8792         mirr_rule->num_entries = j;
8793         mirr_rule->id = rule_id;
8794         mirr_rule->dst_vsi_seid = dst_seid;
8795
8796         if (parent)
8797                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8798         else
8799                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8800
8801         pf->nb_mirror_rule++;
8802         return 0;
8803 }
8804
8805 /**
8806  * i40e_mirror_rule_reset
8807  * @dev: pointer to the device
8808  * @sw_id: mirror rule's sw_id
8809  *
8810  * reset a mirror rule.
8811  *
8812  **/
8813 static int
8814 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8815 {
8816         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8818         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8819         uint16_t seid;
8820         int ret;
8821
8822         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8823
8824         seid = pf->main_vsi->veb->seid;
8825
8826         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8827                 if (sw_id == it->index) {
8828                         mirr_rule = it;
8829                         break;
8830                 }
8831         }
8832         if (mirr_rule) {
8833                 ret = i40e_aq_del_mirror_rule(hw, seid,
8834                                 mirr_rule->rule_type,
8835                                 mirr_rule->entries,
8836                                 mirr_rule->num_entries, mirr_rule->id);
8837                 if (ret < 0) {
8838                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8839                                            " status = %d, aq_err = %d.",
8840                                            ret, hw->aq.asq_last_status);
8841                         return -ENOSYS;
8842                 }
8843                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8844                 rte_free(mirr_rule);
8845                 pf->nb_mirror_rule--;
8846         } else {
8847                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8848                 return -ENOENT;
8849         }
8850         return 0;
8851 }
8852
8853 static uint64_t
8854 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8855 {
8856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8857         uint64_t systim_cycles;
8858
8859         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8860         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8861                         << 32;
8862
8863         return systim_cycles;
8864 }
8865
8866 static uint64_t
8867 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8868 {
8869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8870         uint64_t rx_tstamp;
8871
8872         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8873         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8874                         << 32;
8875
8876         return rx_tstamp;
8877 }
8878
8879 static uint64_t
8880 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8881 {
8882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8883         uint64_t tx_tstamp;
8884
8885         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8886         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8887                         << 32;
8888
8889         return tx_tstamp;
8890 }
8891
8892 static void
8893 i40e_start_timecounters(struct rte_eth_dev *dev)
8894 {
8895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8896         struct i40e_adapter *adapter =
8897                         (struct i40e_adapter *)dev->data->dev_private;
8898         struct rte_eth_link link;
8899         uint32_t tsync_inc_l;
8900         uint32_t tsync_inc_h;
8901
8902         /* Get current link speed. */
8903         memset(&link, 0, sizeof(link));
8904         i40e_dev_link_update(dev, 1);
8905         rte_i40e_dev_atomic_read_link_status(dev, &link);
8906
8907         switch (link.link_speed) {
8908         case ETH_SPEED_NUM_40G:
8909                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8910                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8911                 break;
8912         case ETH_SPEED_NUM_10G:
8913                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8914                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8915                 break;
8916         case ETH_SPEED_NUM_1G:
8917                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8918                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8919                 break;
8920         default:
8921                 tsync_inc_l = 0x0;
8922                 tsync_inc_h = 0x0;
8923         }
8924
8925         /* Set the timesync increment value. */
8926         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8927         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8928
8929         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8930         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8931         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8932
8933         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8934         adapter->systime_tc.cc_shift = 0;
8935         adapter->systime_tc.nsec_mask = 0;
8936
8937         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8938         adapter->rx_tstamp_tc.cc_shift = 0;
8939         adapter->rx_tstamp_tc.nsec_mask = 0;
8940
8941         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8942         adapter->tx_tstamp_tc.cc_shift = 0;
8943         adapter->tx_tstamp_tc.nsec_mask = 0;
8944 }
8945
8946 static int
8947 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8948 {
8949         struct i40e_adapter *adapter =
8950                         (struct i40e_adapter *)dev->data->dev_private;
8951
8952         adapter->systime_tc.nsec += delta;
8953         adapter->rx_tstamp_tc.nsec += delta;
8954         adapter->tx_tstamp_tc.nsec += delta;
8955
8956         return 0;
8957 }
8958
8959 static int
8960 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8961 {
8962         uint64_t ns;
8963         struct i40e_adapter *adapter =
8964                         (struct i40e_adapter *)dev->data->dev_private;
8965
8966         ns = rte_timespec_to_ns(ts);
8967
8968         /* Set the timecounters to a new value. */
8969         adapter->systime_tc.nsec = ns;
8970         adapter->rx_tstamp_tc.nsec = ns;
8971         adapter->tx_tstamp_tc.nsec = ns;
8972
8973         return 0;
8974 }
8975
8976 static int
8977 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8978 {
8979         uint64_t ns, systime_cycles;
8980         struct i40e_adapter *adapter =
8981                         (struct i40e_adapter *)dev->data->dev_private;
8982
8983         systime_cycles = i40e_read_systime_cyclecounter(dev);
8984         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8985         *ts = rte_ns_to_timespec(ns);
8986
8987         return 0;
8988 }
8989
8990 static int
8991 i40e_timesync_enable(struct rte_eth_dev *dev)
8992 {
8993         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8994         uint32_t tsync_ctl_l;
8995         uint32_t tsync_ctl_h;
8996
8997         /* Stop the timesync system time. */
8998         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8999         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9000         /* Reset the timesync system time value. */
9001         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9002         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9003
9004         i40e_start_timecounters(dev);
9005
9006         /* Clear timesync registers. */
9007         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9008         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9009         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9010         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9011         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9012         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9013
9014         /* Enable timestamping of PTP packets. */
9015         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9016         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9017
9018         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9019         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9020         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9021
9022         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9023         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9024
9025         return 0;
9026 }
9027
9028 static int
9029 i40e_timesync_disable(struct rte_eth_dev *dev)
9030 {
9031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9032         uint32_t tsync_ctl_l;
9033         uint32_t tsync_ctl_h;
9034
9035         /* Disable timestamping of transmitted PTP packets. */
9036         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9037         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9038
9039         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9040         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9041
9042         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9043         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9044
9045         /* Reset the timesync increment value. */
9046         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9047         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9048
9049         return 0;
9050 }
9051
9052 static int
9053 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9054                                 struct timespec *timestamp, uint32_t flags)
9055 {
9056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9057         struct i40e_adapter *adapter =
9058                 (struct i40e_adapter *)dev->data->dev_private;
9059
9060         uint32_t sync_status;
9061         uint32_t index = flags & 0x03;
9062         uint64_t rx_tstamp_cycles;
9063         uint64_t ns;
9064
9065         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9066         if ((sync_status & (1 << index)) == 0)
9067                 return -EINVAL;
9068
9069         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9070         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9071         *timestamp = rte_ns_to_timespec(ns);
9072
9073         return 0;
9074 }
9075
9076 static int
9077 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9078                                 struct timespec *timestamp)
9079 {
9080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9081         struct i40e_adapter *adapter =
9082                 (struct i40e_adapter *)dev->data->dev_private;
9083
9084         uint32_t sync_status;
9085         uint64_t tx_tstamp_cycles;
9086         uint64_t ns;
9087
9088         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9089         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9090                 return -EINVAL;
9091
9092         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9093         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9094         *timestamp = rte_ns_to_timespec(ns);
9095
9096         return 0;
9097 }
9098
9099 /*
9100  * i40e_parse_dcb_configure - parse dcb configure from user
9101  * @dev: the device being configured
9102  * @dcb_cfg: pointer of the result of parse
9103  * @*tc_map: bit map of enabled traffic classes
9104  *
9105  * Returns 0 on success, negative value on failure
9106  */
9107 static int
9108 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9109                          struct i40e_dcbx_config *dcb_cfg,
9110                          uint8_t *tc_map)
9111 {
9112         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9113         uint8_t i, tc_bw, bw_lf;
9114
9115         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9116
9117         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9118         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9119                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9120                 return -EINVAL;
9121         }
9122
9123         /* assume each tc has the same bw */
9124         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9125         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9126                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9127         /* to ensure the sum of tcbw is equal to 100 */
9128         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9129         for (i = 0; i < bw_lf; i++)
9130                 dcb_cfg->etscfg.tcbwtable[i]++;
9131
9132         /* assume each tc has the same Transmission Selection Algorithm */
9133         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9134                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9135
9136         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9137                 dcb_cfg->etscfg.prioritytable[i] =
9138                                 dcb_rx_conf->dcb_tc[i];
9139
9140         /* FW needs one App to configure HW */
9141         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9142         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9143         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9144         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9145
9146         if (dcb_rx_conf->nb_tcs == 0)
9147                 *tc_map = 1; /* tc0 only */
9148         else
9149                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9150
9151         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9152                 dcb_cfg->pfc.willing = 0;
9153                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9154                 dcb_cfg->pfc.pfcenable = *tc_map;
9155         }
9156         return 0;
9157 }
9158
9159
9160 static enum i40e_status_code
9161 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9162                               struct i40e_aqc_vsi_properties_data *info,
9163                               uint8_t enabled_tcmap)
9164 {
9165         enum i40e_status_code ret;
9166         int i, total_tc = 0;
9167         uint16_t qpnum_per_tc, bsf, qp_idx;
9168         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9169         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9170         uint16_t used_queues;
9171
9172         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9173         if (ret != I40E_SUCCESS)
9174                 return ret;
9175
9176         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9177                 if (enabled_tcmap & (1 << i))
9178                         total_tc++;
9179         }
9180         if (total_tc == 0)
9181                 total_tc = 1;
9182         vsi->enabled_tc = enabled_tcmap;
9183
9184         /* different VSI has different queues assigned */
9185         if (vsi->type == I40E_VSI_MAIN)
9186                 used_queues = dev_data->nb_rx_queues -
9187                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9188         else if (vsi->type == I40E_VSI_VMDQ2)
9189                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9190         else {
9191                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9192                 return I40E_ERR_NO_AVAILABLE_VSI;
9193         }
9194
9195         qpnum_per_tc = used_queues / total_tc;
9196         /* Number of queues per enabled TC */
9197         if (qpnum_per_tc == 0) {
9198                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9199                 return I40E_ERR_INVALID_QP_ID;
9200         }
9201         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9202                                 I40E_MAX_Q_PER_TC);
9203         bsf = rte_bsf32(qpnum_per_tc);
9204
9205         /**
9206          * Configure TC and queue mapping parameters, for enabled TC,
9207          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9208          * default queue will serve it.
9209          */
9210         qp_idx = 0;
9211         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9212                 if (vsi->enabled_tc & (1 << i)) {
9213                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9214                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9215                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9216                         qp_idx += qpnum_per_tc;
9217                 } else
9218                         info->tc_mapping[i] = 0;
9219         }
9220
9221         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9222         if (vsi->type == I40E_VSI_SRIOV) {
9223                 info->mapping_flags |=
9224                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9225                 for (i = 0; i < vsi->nb_qps; i++)
9226                         info->queue_mapping[i] =
9227                                 rte_cpu_to_le_16(vsi->base_queue + i);
9228         } else {
9229                 info->mapping_flags |=
9230                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9231                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9232         }
9233         info->valid_sections |=
9234                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9235
9236         return I40E_SUCCESS;
9237 }
9238
9239 /*
9240  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9241  * @veb: VEB to be configured
9242  * @tc_map: enabled TC bitmap
9243  *
9244  * Returns 0 on success, negative value on failure
9245  */
9246 static enum i40e_status_code
9247 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9248 {
9249         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9250         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9251         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9252         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9253         enum i40e_status_code ret = I40E_SUCCESS;
9254         int i;
9255         uint32_t bw_max;
9256
9257         /* Check if enabled_tc is same as existing or new TCs */
9258         if (veb->enabled_tc == tc_map)
9259                 return ret;
9260
9261         /* configure tc bandwidth */
9262         memset(&veb_bw, 0, sizeof(veb_bw));
9263         veb_bw.tc_valid_bits = tc_map;
9264         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9265         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9266                 if (tc_map & BIT_ULL(i))
9267                         veb_bw.tc_bw_share_credits[i] = 1;
9268         }
9269         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9270                                                    &veb_bw, NULL);
9271         if (ret) {
9272                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9273                                   " per TC failed = %d",
9274                                   hw->aq.asq_last_status);
9275                 return ret;
9276         }
9277
9278         memset(&ets_query, 0, sizeof(ets_query));
9279         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9280                                                    &ets_query, NULL);
9281         if (ret != I40E_SUCCESS) {
9282                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9283                                  " configuration %u", hw->aq.asq_last_status);
9284                 return ret;
9285         }
9286         memset(&bw_query, 0, sizeof(bw_query));
9287         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9288                                                   &bw_query, NULL);
9289         if (ret != I40E_SUCCESS) {
9290                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9291                                  " configuration %u", hw->aq.asq_last_status);
9292                 return ret;
9293         }
9294
9295         /* store and print out BW info */
9296         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9297         veb->bw_info.bw_max = ets_query.tc_bw_max;
9298         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9299         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9300         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9301                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9302                      I40E_16_BIT_WIDTH);
9303         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9304                 veb->bw_info.bw_ets_share_credits[i] =
9305                                 bw_query.tc_bw_share_credits[i];
9306                 veb->bw_info.bw_ets_credits[i] =
9307                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9308                 /* 4 bits per TC, 4th bit is reserved */
9309                 veb->bw_info.bw_ets_max[i] =
9310                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9311                                   RTE_LEN2MASK(3, uint8_t));
9312                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9313                             veb->bw_info.bw_ets_share_credits[i]);
9314                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9315                             veb->bw_info.bw_ets_credits[i]);
9316                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9317                             veb->bw_info.bw_ets_max[i]);
9318         }
9319
9320         veb->enabled_tc = tc_map;
9321
9322         return ret;
9323 }
9324
9325
9326 /*
9327  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9328  * @vsi: VSI to be configured
9329  * @tc_map: enabled TC bitmap
9330  *
9331  * Returns 0 on success, negative value on failure
9332  */
9333 static enum i40e_status_code
9334 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9335 {
9336         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9337         struct i40e_vsi_context ctxt;
9338         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9339         enum i40e_status_code ret = I40E_SUCCESS;
9340         int i;
9341
9342         /* Check if enabled_tc is same as existing or new TCs */
9343         if (vsi->enabled_tc == tc_map)
9344                 return ret;
9345
9346         /* configure tc bandwidth */
9347         memset(&bw_data, 0, sizeof(bw_data));
9348         bw_data.tc_valid_bits = tc_map;
9349         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9350         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9351                 if (tc_map & BIT_ULL(i))
9352                         bw_data.tc_bw_credits[i] = 1;
9353         }
9354         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9355         if (ret) {
9356                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9357                         " per TC failed = %d",
9358                         hw->aq.asq_last_status);
9359                 goto out;
9360         }
9361         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9362                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9363
9364         /* Update Queue Pairs Mapping for currently enabled UPs */
9365         ctxt.seid = vsi->seid;
9366         ctxt.pf_num = hw->pf_id;
9367         ctxt.vf_num = 0;
9368         ctxt.uplink_seid = vsi->uplink_seid;
9369         ctxt.info = vsi->info;
9370         i40e_get_cap(hw);
9371         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9372         if (ret)
9373                 goto out;
9374
9375         /* Update the VSI after updating the VSI queue-mapping information */
9376         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9377         if (ret) {
9378                 PMD_INIT_LOG(ERR, "Failed to configure "
9379                             "TC queue mapping = %d",
9380                             hw->aq.asq_last_status);
9381                 goto out;
9382         }
9383         /* update the local VSI info with updated queue map */
9384         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9385                                         sizeof(vsi->info.tc_mapping));
9386         (void)rte_memcpy(&vsi->info.queue_mapping,
9387                         &ctxt.info.queue_mapping,
9388                 sizeof(vsi->info.queue_mapping));
9389         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9390         vsi->info.valid_sections = 0;
9391
9392         /* query and update current VSI BW information */
9393         ret = i40e_vsi_get_bw_config(vsi);
9394         if (ret) {
9395                 PMD_INIT_LOG(ERR,
9396                          "Failed updating vsi bw info, err %s aq_err %s",
9397                          i40e_stat_str(hw, ret),
9398                          i40e_aq_str(hw, hw->aq.asq_last_status));
9399                 goto out;
9400         }
9401
9402         vsi->enabled_tc = tc_map;
9403
9404 out:
9405         return ret;
9406 }
9407
9408 /*
9409  * i40e_dcb_hw_configure - program the dcb setting to hw
9410  * @pf: pf the configuration is taken on
9411  * @new_cfg: new configuration
9412  * @tc_map: enabled TC bitmap
9413  *
9414  * Returns 0 on success, negative value on failure
9415  */
9416 static enum i40e_status_code
9417 i40e_dcb_hw_configure(struct i40e_pf *pf,
9418                       struct i40e_dcbx_config *new_cfg,
9419                       uint8_t tc_map)
9420 {
9421         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9422         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9423         struct i40e_vsi *main_vsi = pf->main_vsi;
9424         struct i40e_vsi_list *vsi_list;
9425         enum i40e_status_code ret;
9426         int i;
9427         uint32_t val;
9428
9429         /* Use the FW API if FW > v4.4*/
9430         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9431               (hw->aq.fw_maj_ver >= 5))) {
9432                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9433                                   " to configure DCB");
9434                 return I40E_ERR_FIRMWARE_API_VERSION;
9435         }
9436
9437         /* Check if need reconfiguration */
9438         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9439                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9440                 return I40E_SUCCESS;
9441         }
9442
9443         /* Copy the new config to the current config */
9444         *old_cfg = *new_cfg;
9445         old_cfg->etsrec = old_cfg->etscfg;
9446         ret = i40e_set_dcb_config(hw);
9447         if (ret) {
9448                 PMD_INIT_LOG(ERR,
9449                          "Set DCB Config failed, err %s aq_err %s\n",
9450                          i40e_stat_str(hw, ret),
9451                          i40e_aq_str(hw, hw->aq.asq_last_status));
9452                 return ret;
9453         }
9454         /* set receive Arbiter to RR mode and ETS scheme by default */
9455         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9456                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9457                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9458                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9459                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9460                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9461                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9462                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9463                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9464                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9465                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9466                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9467                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9468         }
9469         /* get local mib to check whether it is configured correctly */
9470         /* IEEE mode */
9471         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9472         /* Get Local DCB Config */
9473         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9474                                      &hw->local_dcbx_config);
9475
9476         /* if Veb is created, need to update TC of it at first */
9477         if (main_vsi->veb) {
9478                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9479                 if (ret)
9480                         PMD_INIT_LOG(WARNING,
9481                                  "Failed configuring TC for VEB seid=%d\n",
9482                                  main_vsi->veb->seid);
9483         }
9484         /* Update each VSI */
9485         i40e_vsi_config_tc(main_vsi, tc_map);
9486         if (main_vsi->veb) {
9487                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9488                         /* Beside main VSI and VMDQ VSIs, only enable default
9489                          * TC for other VSIs
9490                          */
9491                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9492                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9493                                                          tc_map);
9494                         else
9495                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9496                                                          I40E_DEFAULT_TCMAP);
9497                         if (ret)
9498                                 PMD_INIT_LOG(WARNING,
9499                                          "Failed configuring TC for VSI seid=%d\n",
9500                                          vsi_list->vsi->seid);
9501                         /* continue */
9502                 }
9503         }
9504         return I40E_SUCCESS;
9505 }
9506
9507 /*
9508  * i40e_dcb_init_configure - initial dcb config
9509  * @dev: device being configured
9510  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9511  *
9512  * Returns 0 on success, negative value on failure
9513  */
9514 static int
9515 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9516 {
9517         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9518         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9519         int ret = 0;
9520
9521         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9522                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9523                 return -ENOTSUP;
9524         }
9525
9526         /* DCB initialization:
9527          * Update DCB configuration from the Firmware and configure
9528          * LLDP MIB change event.
9529          */
9530         if (sw_dcb == TRUE) {
9531                 ret = i40e_init_dcb(hw);
9532                 /* If lldp agent is stopped, the return value from
9533                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9534                  * adminq status. Otherwise, it should return success.
9535                  */
9536                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9537                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9538                         memset(&hw->local_dcbx_config, 0,
9539                                 sizeof(struct i40e_dcbx_config));
9540                         /* set dcb default configuration */
9541                         hw->local_dcbx_config.etscfg.willing = 0;
9542                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9543                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9544                         hw->local_dcbx_config.etscfg.tsatable[0] =
9545                                                 I40E_IEEE_TSA_ETS;
9546                         hw->local_dcbx_config.etsrec =
9547                                 hw->local_dcbx_config.etscfg;
9548                         hw->local_dcbx_config.pfc.willing = 0;
9549                         hw->local_dcbx_config.pfc.pfccap =
9550                                                 I40E_MAX_TRAFFIC_CLASS;
9551                         /* FW needs one App to configure HW */
9552                         hw->local_dcbx_config.numapps = 1;
9553                         hw->local_dcbx_config.app[0].selector =
9554                                                 I40E_APP_SEL_ETHTYPE;
9555                         hw->local_dcbx_config.app[0].priority = 3;
9556                         hw->local_dcbx_config.app[0].protocolid =
9557                                                 I40E_APP_PROTOID_FCOE;
9558                         ret = i40e_set_dcb_config(hw);
9559                         if (ret) {
9560                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9561                                         " err = %d, aq_err = %d.", ret,
9562                                           hw->aq.asq_last_status);
9563                                 return -ENOSYS;
9564                         }
9565                 } else {
9566                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9567                                           " err = %d, aq_err = %d.", ret,
9568                                           hw->aq.asq_last_status);
9569                         return -ENOTSUP;
9570                 }
9571         } else {
9572                 ret = i40e_aq_start_lldp(hw, NULL);
9573                 if (ret != I40E_SUCCESS)
9574                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9575
9576                 ret = i40e_init_dcb(hw);
9577                 if (!ret) {
9578                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9579                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9580                                                   " DCBX offload.");
9581                                 return -ENOTSUP;
9582                         }
9583                 } else {
9584                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9585                                           " aq_err = %d.", ret,
9586                                           hw->aq.asq_last_status);
9587                         return -ENOTSUP;
9588                 }
9589         }
9590         return 0;
9591 }
9592
9593 /*
9594  * i40e_dcb_setup - setup dcb related config
9595  * @dev: device being configured
9596  *
9597  * Returns 0 on success, negative value on failure
9598  */
9599 static int
9600 i40e_dcb_setup(struct rte_eth_dev *dev)
9601 {
9602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9603         struct i40e_dcbx_config dcb_cfg;
9604         uint8_t tc_map = 0;
9605         int ret = 0;
9606
9607         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9608                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9609                 return -ENOTSUP;
9610         }
9611
9612         if (pf->vf_num != 0)
9613                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9614
9615         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9616         if (ret) {
9617                 PMD_INIT_LOG(ERR, "invalid dcb config");
9618                 return -EINVAL;
9619         }
9620         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9621         if (ret) {
9622                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9623                 return -ENOSYS;
9624         }
9625
9626         return 0;
9627 }
9628
9629 static int
9630 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9631                       struct rte_eth_dcb_info *dcb_info)
9632 {
9633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9635         struct i40e_vsi *vsi = pf->main_vsi;
9636         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9637         uint16_t bsf, tc_mapping;
9638         int i, j = 0;
9639
9640         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9641                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9642         else
9643                 dcb_info->nb_tcs = 1;
9644         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9645                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9646         for (i = 0; i < dcb_info->nb_tcs; i++)
9647                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9648
9649         /* get queue mapping if vmdq is disabled */
9650         if (!pf->nb_cfg_vmdq_vsi) {
9651                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9652                         if (!(vsi->enabled_tc & (1 << i)))
9653                                 continue;
9654                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9655                         dcb_info->tc_queue.tc_rxq[j][i].base =
9656                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9657                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9658                         dcb_info->tc_queue.tc_txq[j][i].base =
9659                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9660                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9661                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9662                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9663                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9664                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9665                 }
9666                 return 0;
9667         }
9668
9669         /* get queue mapping if vmdq is enabled */
9670         do {
9671                 vsi = pf->vmdq[j].vsi;
9672                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9673                         if (!(vsi->enabled_tc & (1 << i)))
9674                                 continue;
9675                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9676                         dcb_info->tc_queue.tc_rxq[j][i].base =
9677                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9678                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9679                         dcb_info->tc_queue.tc_txq[j][i].base =
9680                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9681                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9682                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9683                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9684                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9685                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9686                 }
9687                 j++;
9688         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9689         return 0;
9690 }
9691
9692 static int
9693 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9694 {
9695         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9696         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9697         uint16_t interval =
9698                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9699         uint16_t msix_intr;
9700
9701         msix_intr = intr_handle->intr_vec[queue_id];
9702         if (msix_intr == I40E_MISC_VEC_ID)
9703                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9704                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9705                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9706                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9707                                (interval <<
9708                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9709         else
9710                 I40E_WRITE_REG(hw,
9711                                I40E_PFINT_DYN_CTLN(msix_intr -
9712                                                    I40E_RX_VEC_START),
9713                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9714                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9715                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9716                                (interval <<
9717                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9718
9719         I40E_WRITE_FLUSH(hw);
9720         rte_intr_enable(&dev->pci_dev->intr_handle);
9721
9722         return 0;
9723 }
9724
9725 static int
9726 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9727 {
9728         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9729         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9730         uint16_t msix_intr;
9731
9732         msix_intr = intr_handle->intr_vec[queue_id];
9733         if (msix_intr == I40E_MISC_VEC_ID)
9734                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9735         else
9736                 I40E_WRITE_REG(hw,
9737                                I40E_PFINT_DYN_CTLN(msix_intr -
9738                                                    I40E_RX_VEC_START),
9739                                0);
9740         I40E_WRITE_FLUSH(hw);
9741
9742         return 0;
9743 }
9744
9745 static int i40e_get_regs(struct rte_eth_dev *dev,
9746                          struct rte_dev_reg_info *regs)
9747 {
9748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9749         uint32_t *ptr_data = regs->data;
9750         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9751         const struct i40e_reg_info *reg_info;
9752
9753         if (ptr_data == NULL) {
9754                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9755                 regs->width = sizeof(uint32_t);
9756                 return 0;
9757         }
9758
9759         /* The first few registers have to be read using AQ operations */
9760         reg_idx = 0;
9761         while (i40e_regs_adminq[reg_idx].name) {
9762                 reg_info = &i40e_regs_adminq[reg_idx++];
9763                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9764                         for (arr_idx2 = 0;
9765                                         arr_idx2 <= reg_info->count2;
9766                                         arr_idx2++) {
9767                                 reg_offset = arr_idx * reg_info->stride1 +
9768                                         arr_idx2 * reg_info->stride2;
9769                                 reg_offset += reg_info->base_addr;
9770                                 ptr_data[reg_offset >> 2] =
9771                                         i40e_read_rx_ctl(hw, reg_offset);
9772                         }
9773         }
9774
9775         /* The remaining registers can be read using primitives */
9776         reg_idx = 0;
9777         while (i40e_regs_others[reg_idx].name) {
9778                 reg_info = &i40e_regs_others[reg_idx++];
9779                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9780                         for (arr_idx2 = 0;
9781                                         arr_idx2 <= reg_info->count2;
9782                                         arr_idx2++) {
9783                                 reg_offset = arr_idx * reg_info->stride1 +
9784                                         arr_idx2 * reg_info->stride2;
9785                                 reg_offset += reg_info->base_addr;
9786                                 ptr_data[reg_offset >> 2] =
9787                                         I40E_READ_REG(hw, reg_offset);
9788                         }
9789         }
9790
9791         return 0;
9792 }
9793
9794 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9795 {
9796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9797
9798         /* Convert word count to byte count */
9799         return hw->nvm.sr_size << 1;
9800 }
9801
9802 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9803                            struct rte_dev_eeprom_info *eeprom)
9804 {
9805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9806         uint16_t *data = eeprom->data;
9807         uint16_t offset, length, cnt_words;
9808         int ret_code;
9809
9810         offset = eeprom->offset >> 1;
9811         length = eeprom->length >> 1;
9812         cnt_words = length;
9813
9814         if (offset > hw->nvm.sr_size ||
9815                 offset + length > hw->nvm.sr_size) {
9816                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9817                 return -EINVAL;
9818         }
9819
9820         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9821
9822         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9823         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9824                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9825                 return -EIO;
9826         }
9827
9828         return 0;
9829 }
9830
9831 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9832                                       struct ether_addr *mac_addr)
9833 {
9834         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9835
9836         if (!is_valid_assigned_ether_addr(mac_addr)) {
9837                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9838                 return;
9839         }
9840
9841         /* Flags: 0x3 updates port address */
9842         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9843 }
9844
9845 static int
9846 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9847 {
9848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9849         struct rte_eth_dev_data *dev_data = pf->dev_data;
9850         uint32_t frame_size = mtu + ETHER_HDR_LEN
9851                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9852         int ret = 0;
9853
9854         /* check if mtu is within the allowed range */
9855         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9856                 return -EINVAL;
9857
9858         /* mtu setting is forbidden if port is start */
9859         if (dev_data->dev_started) {
9860                 PMD_DRV_LOG(ERR,
9861                             "port %d must be stopped before configuration\n",
9862                             dev_data->port_id);
9863                 return -EBUSY;
9864         }
9865
9866         if (frame_size > ETHER_MAX_LEN)
9867                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9868         else
9869                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9870
9871         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9872
9873         return ret;
9874 }