drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control enable fwd bit */
  87 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  88
  89 /* Receive Packet Buffer size */
  90 #define I40E_RXPBSIZE (968 * 1024)
  91
  92 /* Kilobytes shift */
  93 #define I40E_KILOSHIFT 10
  94
  95 /* Flow control default high water */
  96 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  97
  98 /* Flow control default low water */
  99 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(
 377                 __rte_unused struct rte_intr_handle *handle, void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 426                                                      uint16_t seid,
 427                                                      uint16_t rule_type,
 428                                                      uint16_t *entries,
 429                                                      uint16_t count,
 430                                                      uint16_t rule_id);
 431 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 432                         struct rte_eth_mirror_conf *mirror_conf,
 433                         uint8_t sw_id, uint8_t on);
 434 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 435
 436 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 437 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 438 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 439                                            struct timespec *timestamp,
 440                                            uint32_t flags);
 441 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 442                                            struct timespec *timestamp);
 443 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 444
 445 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 446
 447 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 448                                    struct timespec *timestamp);
 449 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 450                                     const struct timespec *timestamp);
 451
 452 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 453                                          uint16_t queue_id);
 454 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 455                                           uint16_t queue_id);
 456
 457 static int i40e_get_regs(struct rte_eth_dev *dev,
 458                          struct rte_dev_reg_info *regs);
 459
 460 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 461
 462 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 463                            struct rte_dev_eeprom_info *eeprom);
 464
 465 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 466                                       struct ether_addr *mac_addr);
 467
 468 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 469 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 470
 471 static const struct rte_pci_id pci_id_i40e_map[] = {
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 486         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 487         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 488         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 489         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 490         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 491         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 492         { .vendor_id = 0, /* sentinel */ },
 493 };
 494
 495 static const struct eth_dev_ops i40e_eth_dev_ops = {
 496         .dev_configure                = i40e_dev_configure,
 497         .dev_start                    = i40e_dev_start,
 498         .dev_stop                     = i40e_dev_stop,
 499         .dev_close                    = i40e_dev_close,
 500         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 501         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 502         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 503         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 504         .dev_set_link_up              = i40e_dev_set_link_up,
 505         .dev_set_link_down            = i40e_dev_set_link_down,
 506         .link_update                  = i40e_dev_link_update,
 507         .stats_get                    = i40e_dev_stats_get,
 508         .xstats_get                   = i40e_dev_xstats_get,
 509         .xstats_get_names             = i40e_dev_xstats_get_names,
 510         .stats_reset                  = i40e_dev_stats_reset,
 511         .xstats_reset                 = i40e_dev_stats_reset,
 512         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 513         .dev_infos_get                = i40e_dev_info_get,
 514         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 515         .vlan_filter_set              = i40e_vlan_filter_set,
 516         .vlan_tpid_set                = i40e_vlan_tpid_set,
 517         .vlan_offload_set             = i40e_vlan_offload_set,
 518         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 519         .vlan_pvid_set                = i40e_vlan_pvid_set,
 520         .rx_queue_start               = i40e_dev_rx_queue_start,
 521         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 522         .tx_queue_start               = i40e_dev_tx_queue_start,
 523         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 524         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 525         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 526         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 527         .rx_queue_release             = i40e_dev_rx_queue_release,
 528         .rx_queue_count               = i40e_dev_rx_queue_count,
 529         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 530         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 531         .tx_queue_release             = i40e_dev_tx_queue_release,
 532         .dev_led_on                   = i40e_dev_led_on,
 533         .dev_led_off                  = i40e_dev_led_off,
 534         .flow_ctrl_get                = i40e_flow_ctrl_get,
 535         .flow_ctrl_set                = i40e_flow_ctrl_set,
 536         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 537         .mac_addr_add                 = i40e_macaddr_add,
 538         .mac_addr_remove              = i40e_macaddr_remove,
 539         .reta_update                  = i40e_dev_rss_reta_update,
 540         .reta_query                   = i40e_dev_rss_reta_query,
 541         .rss_hash_update              = i40e_dev_rss_hash_update,
 542         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 543         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 544         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 545         .filter_ctrl                  = i40e_dev_filter_ctrl,
 546         .rxq_info_get                 = i40e_rxq_info_get,
 547         .txq_info_get                 = i40e_txq_info_get,
 548         .mirror_rule_set              = i40e_mirror_rule_set,
 549         .mirror_rule_reset            = i40e_mirror_rule_reset,
 550         .timesync_enable              = i40e_timesync_enable,
 551         .timesync_disable             = i40e_timesync_disable,
 552         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 553         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 554         .get_dcb_info                 = i40e_dev_get_dcb_info,
 555         .timesync_adjust_time         = i40e_timesync_adjust_time,
 556         .timesync_read_time           = i40e_timesync_read_time,
 557         .timesync_write_time          = i40e_timesync_write_time,
 558         .get_reg                      = i40e_get_regs,
 559         .get_eeprom_length            = i40e_get_eeprom_length,
 560         .get_eeprom                   = i40e_get_eeprom,
 561         .mac_addr_set                 = i40e_set_default_mac_addr,
 562         .mtu_set                      = i40e_dev_mtu_set,
 563 };
 564
 565 /* store statistics names and its offset in stats structure */
 566 struct rte_i40e_xstats_name_off {
 567         char name[RTE_ETH_XSTATS_NAME_SIZE];
 568         unsigned offset;
 569 };
 570
 571 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 572         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 573         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 574         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 575         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 576         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 577                 rx_unknown_protocol)},
 578         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 579         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 580         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 581         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 582 };
 583
 584 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 585                 sizeof(rte_i40e_stats_strings[0]))
 586
 587 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 588         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 589                 tx_dropped_link_down)},
 590         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 591         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 592                 illegal_bytes)},
 593         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 594         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 595                 mac_local_faults)},
 596         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 597                 mac_remote_faults)},
 598         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 599                 rx_length_errors)},
 600         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 601         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 602         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 603         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 604         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 605         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 606                 rx_size_127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 608                 rx_size_255)},
 609         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 610                 rx_size_511)},
 611         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 612                 rx_size_1023)},
 613         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 614                 rx_size_1522)},
 615         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 616                 rx_size_big)},
 617         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 618                 rx_undersize)},
 619         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 620                 rx_oversize)},
 621         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 622                 mac_short_packet_dropped)},
 623         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 624                 rx_fragments)},
 625         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 626         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 627         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 628                 tx_size_127)},
 629         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 630                 tx_size_255)},
 631         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 632                 tx_size_511)},
 633         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 634                 tx_size_1023)},
 635         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 636                 tx_size_1522)},
 637         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 638                 tx_size_big)},
 639         {"rx_flow_director_atr_match_packets",
 640                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 641         {"rx_flow_director_sb_match_packets",
 642                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 643         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 644                 tx_lpi_status)},
 645         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 646                 rx_lpi_status)},
 647         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 648                 tx_lpi_count)},
 649         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 650                 rx_lpi_count)},
 651 };
 652
 653 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 654                 sizeof(rte_i40e_hw_port_strings[0]))
 655
 656 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 657         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_rx)},
 659         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 660                 priority_xoff_rx)},
 661 };
 662
 663 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 664                 sizeof(rte_i40e_rxq_prio_strings[0]))
 665
 666 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 667         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 668                 priority_xon_tx)},
 669         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 670                 priority_xoff_tx)},
 671         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 672                 priority_xon_2_xoff)},
 673 };
 674
 675 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 676                 sizeof(rte_i40e_txq_prio_strings[0]))
 677
 678 static struct eth_driver rte_i40e_pmd = {
 679         .pci_drv = {
 680                 .id_table = pci_id_i40e_map,
 681                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 682                         RTE_PCI_DRV_DETACHABLE,
 683                 .probe = rte_eth_dev_pci_probe,
 684                 .remove = rte_eth_dev_pci_remove,
 685         },
 686         .eth_dev_init = eth_i40e_dev_init,
 687         .eth_dev_uninit = eth_i40e_dev_uninit,
 688         .dev_private_size = sizeof(struct i40e_adapter),
 689 };
 690
 691 static inline int
 692 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 693                                      struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = link;
 696         struct rte_eth_link *src = &(dev->data->dev_link);
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 static inline int
 706 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 707                                       struct rte_eth_link *link)
 708 {
 709         struct rte_eth_link *dst = &(dev->data->dev_link);
 710         struct rte_eth_link *src = link;
 711
 712         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 713                                         *(uint64_t *)src) == 0)
 714                 return -1;
 715
 716         return 0;
 717 }
 718
 719 static inline void
 720 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 721 {
 722         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 723         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 724                     "with value 0x%08x",
 725                     reg_addr, reg_val);
 726 }
 727
 728 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 729 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 730
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737
 738 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 739 {
 740         /*
 741          * Force global configuration for flexible payload
 742          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 743          * This should be removed from code once proper
 744          * configuration API is added to avoid configuration conflicts
 745          * between ports of the same device.
 746          */
 747         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 750         i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
 751
 752         /*
 753          * Initialize registers for parsing packet type of QinQ
 754          * This should be removed from code once proper
 755          * configuration API is added to avoid configuration conflicts
 756          * between ports of the same device.
 757          */
 758         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 759         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 760         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 761 }
 762
 763 static inline void i40e_config_automask(struct i40e_pf *pf)
 764 {
 765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 766         uint32_t val;
 767
 768         /* INTENA flag is not auto-cleared for interrupt */
 769         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 770         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 771                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 772
 773         /* If support multi-driver, PF will use INT0. */
 774         if (!pf->support_multi_driver)
 775                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 776
 777         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 778 }
 779
 780 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 781
 782 /*
 783  * Add a ethertype filter to drop all flow control frames transmitted
 784  * from VSIs.
 785 */
 786 static void
 787 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 788 {
 789         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 790         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 791                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 792                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 793         int ret;
 794
 795         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 796                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 797                                 pf->main_vsi_seid, 0,
 798                                 TRUE, NULL, NULL);
 799         if (ret)
 800                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 801                                   " frames from VSIs.");
 802 }
 803
 804 static int
 805 floating_veb_list_handler(__rte_unused const char *key,
 806                           const char *floating_veb_value,
 807                           void *opaque)
 808 {
 809         int idx = 0;
 810         unsigned int count = 0;
 811         char *end = NULL;
 812         int min, max;
 813         bool *vf_floating_veb = opaque;
 814
 815         while (isblank(*floating_veb_value))
 816                 floating_veb_value++;
 817
 818         /* Reset floating VEB configuration for VFs */
 819         for (idx = 0; idx < I40E_MAX_VF; idx++)
 820                 vf_floating_veb[idx] = false;
 821
 822         min = I40E_MAX_VF;
 823         do {
 824                 while (isblank(*floating_veb_value))
 825                         floating_veb_value++;
 826                 if (*floating_veb_value == '\0')
 827                         return -1;
 828                 errno = 0;
 829                 idx = strtoul(floating_veb_value, &end, 10);
 830                 if (errno || end == NULL)
 831                         return -1;
 832                 while (isblank(*end))
 833                         end++;
 834                 if (*end == '-') {
 835                         min = idx;
 836                 } else if ((*end == ';') || (*end == '\0')) {
 837                         max = idx;
 838                         if (min == I40E_MAX_VF)
 839                                 min = idx;
 840                         if (max >= I40E_MAX_VF)
 841                                 max = I40E_MAX_VF - 1;
 842                         for (idx = min; idx <= max; idx++) {
 843                                 vf_floating_veb[idx] = true;
 844                                 count++;
 845                         }
 846                         min = I40E_MAX_VF;
 847                 } else {
 848                         return -1;
 849                 }
 850                 floating_veb_value = end + 1;
 851         } while (*end != '\0');
 852
 853         if (count == 0)
 854                 return -1;
 855
 856         return 0;
 857 }
 858
 859 static void
 860 config_vf_floating_veb(struct rte_devargs *devargs,
 861                        uint16_t floating_veb,
 862                        bool *vf_floating_veb)
 863 {
 864         struct rte_kvargs *kvlist;
 865         int i;
 866         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 867
 868         if (!floating_veb)
 869                 return;
 870         /* All the VFs attach to the floating VEB by default
 871          * when the floating VEB is enabled.
 872          */
 873         for (i = 0; i < I40E_MAX_VF; i++)
 874                 vf_floating_veb[i] = true;
 875
 876         if (devargs == NULL)
 877                 return;
 878
 879         kvlist = rte_kvargs_parse(devargs->args, NULL);
 880         if (kvlist == NULL)
 881                 return;
 882
 883         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 884                 rte_kvargs_free(kvlist);
 885                 return;
 886         }
 887         /* When the floating_veb_list parameter exists, all the VFs
 888          * will attach to the legacy VEB firstly, then configure VFs
 889          * to the floating VEB according to the floating_veb_list.
 890          */
 891         if (rte_kvargs_process(kvlist, floating_veb_list,
 892                                floating_veb_list_handler,
 893                                vf_floating_veb) < 0) {
 894                 rte_kvargs_free(kvlist);
 895                 return;
 896         }
 897         rte_kvargs_free(kvlist);
 898 }
 899
 900 static int
 901 i40e_check_floating_handler(__rte_unused const char *key,
 902                             const char *value,
 903                             __rte_unused void *opaque)
 904 {
 905         if (strcmp(value, "1"))
 906                 return -1;
 907
 908         return 0;
 909 }
 910
 911 static int
 912 is_floating_veb_supported(struct rte_devargs *devargs)
 913 {
 914         struct rte_kvargs *kvlist;
 915         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 916
 917         if (devargs == NULL)
 918                 return 0;
 919
 920         kvlist = rte_kvargs_parse(devargs->args, NULL);
 921         if (kvlist == NULL)
 922                 return 0;
 923
 924         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 925                 rte_kvargs_free(kvlist);
 926                 return 0;
 927         }
 928         /* Floating VEB is enabled when there's key-value:
 929          * enable_floating_veb=1
 930          */
 931         if (rte_kvargs_process(kvlist, floating_veb_key,
 932                                i40e_check_floating_handler, NULL) < 0) {
 933                 rte_kvargs_free(kvlist);
 934                 return 0;
 935         }
 936         rte_kvargs_free(kvlist);
 937
 938         return 1;
 939 }
 940
 941 static void
 942 config_floating_veb(struct rte_eth_dev *dev)
 943 {
 944         struct rte_pci_device *pci_dev = dev->pci_dev;
 945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 946         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947
 948         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 949
 950         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 951                 pf->floating_veb =
 952                         is_floating_veb_supported(pci_dev->device.devargs);
 953                 config_vf_floating_veb(pci_dev->device.devargs,
 954                                        pf->floating_veb,
 955                                        pf->floating_veb_list);
 956         } else {
 957                 pf->floating_veb = false;
 958         }
 959 }
 960
 961 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 962 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 963
 964 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
 965 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
 966                               ETH_I40E_SUPPORT_MULTI_DRIVER "=0|1");
 967
 968 static int
 969 i40e_parse_multi_drv_handler(__rte_unused const char *key,
 970                               const char *value,
 971                               void *opaque)
 972 {
 973         struct i40e_pf *pf;
 974         unsigned long support_multi_driver;
 975         char *end;
 976
 977         pf = (struct i40e_pf *)opaque;
 978
 979         errno = 0;
 980         support_multi_driver = strtoul(value, &end, 10);
 981         if (errno != 0 || end == value || *end != 0) {
 982                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
 983                 return -(EINVAL);
 984         }
 985
 986         if (support_multi_driver == 1 || support_multi_driver == 0)
 987                 pf->support_multi_driver = (bool)support_multi_driver;
 988         else
 989                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
 990                             "enable global configuration by default."
 991                             ETH_I40E_SUPPORT_MULTI_DRIVER);
 992         return 0;
 993 }
 994
 995 static int
 996 i40e_support_multi_driver(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct rte_pci_device *pci_dev = dev->pci_dev;
1000         static const char *valid_keys[] = {
1001                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1002         struct rte_kvargs *kvlist;
1003
1004         /* Enable global configuration by default */
1005         pf->support_multi_driver = false;
1006
1007         if (!pci_dev->device.devargs)
1008                 return 0;
1009
1010         kvlist = rte_kvargs_parse(pci_dev->device.devargs->args, valid_keys);
1011         if (!kvlist)
1012                 return -EINVAL;
1013
1014         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1015                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1016                             "the first invalid or last valid one is used !",
1017                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1018
1019         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1020                                i40e_parse_multi_drv_handler, pf) < 0) {
1021                 rte_kvargs_free(kvlist);
1022                 return -EINVAL;
1023         }
1024
1025         rte_kvargs_free(kvlist);
1026         return 0;
1027 }
1028
1029 static int
1030 eth_i40e_dev_init(struct rte_eth_dev *dev)
1031 {
1032         struct rte_pci_device *pci_dev;
1033         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1034         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1035         struct i40e_vsi *vsi;
1036         int ret;
1037         uint32_t len;
1038         uint8_t aq_fail = 0;
1039
1040         PMD_INIT_FUNC_TRACE();
1041
1042         dev->dev_ops = &i40e_eth_dev_ops;
1043         dev->rx_pkt_burst = i40e_recv_pkts;
1044         dev->tx_pkt_burst = i40e_xmit_pkts;
1045
1046         /* for secondary processes, we don't initialise any further as primary
1047          * has already done this work. Only check we don't need a different
1048          * RX function */
1049         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1050                 i40e_set_rx_function(dev);
1051                 i40e_set_tx_function(dev);
1052                 return 0;
1053         }
1054         pci_dev = dev->pci_dev;
1055
1056         rte_eth_copy_pci_info(dev, pci_dev);
1057
1058         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1059         pf->adapter->eth_dev = dev;
1060         pf->dev_data = dev->data;
1061
1062         hw->back = I40E_PF_TO_ADAPTER(pf);
1063         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1064         if (!hw->hw_addr) {
1065                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1066                              "as address is NULL");
1067                 return -ENODEV;
1068         }
1069
1070         hw->vendor_id = pci_dev->id.vendor_id;
1071         hw->device_id = pci_dev->id.device_id;
1072         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1073         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1074         hw->bus.device = pci_dev->addr.devid;
1075         hw->bus.func = pci_dev->addr.function;
1076         hw->adapter_stopped = 0;
1077
1078         /* Check if need to support multi-driver */
1079         i40e_support_multi_driver(dev);
1080
1081         /* Make sure all is clean before doing PF reset */
1082         i40e_clear_hw(hw);
1083
1084         /* Initialize the hardware */
1085         i40e_hw_init(dev);
1086
1087         /* Reset here to make sure all is clean for each PF */
1088         ret = i40e_pf_reset(hw);
1089         if (ret) {
1090                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1091                 return ret;
1092         }
1093
1094         /* Initialize the shared code (base driver) */
1095         ret = i40e_init_shared_code(hw);
1096         if (ret) {
1097                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1098                 return ret;
1099         }
1100
1101         i40e_config_automask(pf);
1102
1103         /*
1104          * To work around the NVM issue, initialize registers
1105          * for flexible payload and packet type of QinQ by
1106          * software. It should be removed once issues are fixed
1107          * in NVM.
1108          */
1109         if (!pf->support_multi_driver)
1110                 i40e_GLQF_reg_init(hw);
1111
1112         /* Initialize the input set for filters (hash and fd) to default value */
1113         i40e_filter_input_set_init(pf);
1114
1115         /* Initialize the parameters for adminq */
1116         i40e_init_adminq_parameter(hw);
1117         ret = i40e_init_adminq(hw);
1118         if (ret != I40E_SUCCESS) {
1119                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1120                 return -EIO;
1121         }
1122         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1123                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1124                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1125                      ((hw->nvm.version >> 12) & 0xf),
1126                      ((hw->nvm.version >> 4) & 0xff),
1127                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1128
1129         /* Need the special FW version to support floating VEB */
1130         config_floating_veb(dev);
1131         /* Clear PXE mode */
1132         i40e_clear_pxe_mode(hw);
1133         ret = i40e_dev_sync_phy_type(hw);
1134         if (ret) {
1135                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1136                 goto err_sync_phy_type;
1137         }
1138         /*
1139          * On X710, performance number is far from the expectation on recent
1140          * firmware versions. The fix for this issue may not be integrated in
1141          * the following firmware version. So the workaround in software driver
1142          * is needed. It needs to modify the initial values of 3 internal only
1143          * registers. Note that the workaround can be removed when it is fixed
1144          * in firmware in the future.
1145          */
1146         i40e_configure_registers(hw);
1147
1148         /* Get hw capabilities */
1149         ret = i40e_get_cap(hw);
1150         if (ret != I40E_SUCCESS) {
1151                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1152                 goto err_get_capabilities;
1153         }
1154
1155         /* Initialize parameters for PF */
1156         ret = i40e_pf_parameter_init(dev);
1157         if (ret != 0) {
1158                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1159                 goto err_parameter_init;
1160         }
1161
1162         /* Initialize the queue management */
1163         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1164         if (ret < 0) {
1165                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1166                 goto err_qp_pool_init;
1167         }
1168         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1169                                 hw->func_caps.num_msix_vectors - 1);
1170         if (ret < 0) {
1171                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1172                 goto err_msix_pool_init;
1173         }
1174
1175         /* Initialize lan hmc */
1176         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1177                                 hw->func_caps.num_rx_qp, 0, 0);
1178         if (ret != I40E_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1180                 goto err_init_lan_hmc;
1181         }
1182
1183         /* Configure lan hmc */
1184         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1185         if (ret != I40E_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1187                 goto err_configure_lan_hmc;
1188         }
1189
1190         /* Get and check the mac address */
1191         i40e_get_mac_addr(hw, hw->mac.addr);
1192         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1193                 PMD_INIT_LOG(ERR, "mac address is not valid");
1194                 ret = -EIO;
1195                 goto err_get_mac_addr;
1196         }
1197         /* Copy the permanent MAC address */
1198         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1199                         (struct ether_addr *) hw->mac.perm_addr);
1200
1201         /* Disable flow control */
1202         hw->fc.requested_mode = I40E_FC_NONE;
1203         i40e_set_fc(hw, &aq_fail, TRUE);
1204
1205         /* Set the global registers with default ether type value */
1206         if (!pf->support_multi_driver) {
1207                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1208                                          ETHER_TYPE_VLAN);
1209                 if (ret != I40E_SUCCESS) {
1210                         PMD_INIT_LOG(ERR, "Failed to set the default outer "
1211                                      "VLAN ether type");
1212                         goto err_setup_pf_switch;
1213                 }
1214         }
1215
1216         /* PF setup, which includes VSI setup */
1217         ret = i40e_pf_setup(pf);
1218         if (ret) {
1219                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* reset all stats of the device, including pf and main vsi */
1224         i40e_dev_stats_reset(dev);
1225
1226         vsi = pf->main_vsi;
1227
1228         /* Disable double vlan by default */
1229         i40e_vsi_config_double_vlan(vsi, FALSE);
1230
1231         /* Disable S-TAG identification when floating_veb is disabled */
1232         if (!pf->floating_veb) {
1233                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1234                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1235                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1236                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1237                 }
1238         }
1239
1240         if (!vsi->max_macaddrs)
1241                 len = ETHER_ADDR_LEN;
1242         else
1243                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1244
1245         /* Should be after VSI initialized */
1246         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1247         if (!dev->data->mac_addrs) {
1248                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1249                                         "for storing mac address");
1250                 goto err_mac_alloc;
1251         }
1252         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1253                                         &dev->data->mac_addrs[0]);
1254
1255         /* initialize pf host driver to setup SRIOV resource if applicable */
1256         i40e_pf_host_init(dev);
1257
1258         /* register callback func to eal lib */
1259         rte_intr_callback_register(&(pci_dev->intr_handle),
1260                 i40e_dev_interrupt_handler, (void *)dev);
1261
1262         /* configure and enable device interrupt */
1263         i40e_pf_config_irq0(hw, TRUE);
1264         i40e_pf_enable_irq0(hw);
1265
1266         /* enable uio intr after callback register */
1267         rte_intr_enable(&(pci_dev->intr_handle));
1268         /*
1269          * Add an ethertype filter to drop all flow control frames transmitted
1270          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1271          * frames to wire.
1272          */
1273         i40e_add_tx_flow_control_drop_filter(pf);
1274
1275         /* Set the max frame size to 0x2600 by default,
1276          * in case other drivers changed the default value.
1277          */
1278         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1279
1280         /* initialize mirror rule list */
1281         TAILQ_INIT(&pf->mirror_list);
1282
1283         /* Init dcb to sw mode by default */
1284         ret = i40e_dcb_init_configure(dev, TRUE);
1285         if (ret != I40E_SUCCESS) {
1286                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1287                 pf->flags &= ~I40E_FLAG_DCB;
1288         }
1289
1290         return 0;
1291
1292 err_mac_alloc:
1293         i40e_vsi_release(pf->main_vsi);
1294 err_setup_pf_switch:
1295 err_get_mac_addr:
1296 err_configure_lan_hmc:
1297         (void)i40e_shutdown_lan_hmc(hw);
1298 err_init_lan_hmc:
1299         i40e_res_pool_destroy(&pf->msix_pool);
1300 err_msix_pool_init:
1301         i40e_res_pool_destroy(&pf->qp_pool);
1302 err_qp_pool_init:
1303 err_parameter_init:
1304 err_get_capabilities:
1305 err_sync_phy_type:
1306         (void)i40e_shutdown_adminq(hw);
1307
1308         return ret;
1309 }
1310
1311 static int
1312 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1313 {
1314         struct rte_pci_device *pci_dev;
1315         struct i40e_hw *hw;
1316         struct i40e_filter_control_settings settings;
1317         int ret;
1318         uint8_t aq_fail = 0;
1319
1320         PMD_INIT_FUNC_TRACE();
1321
1322         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1323                 return 0;
1324
1325         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1326         pci_dev = dev->pci_dev;
1327
1328         if (hw->adapter_stopped == 0)
1329                 i40e_dev_close(dev);
1330
1331         dev->dev_ops = NULL;
1332         dev->rx_pkt_burst = NULL;
1333         dev->tx_pkt_burst = NULL;
1334
1335         /* Clear PXE mode */
1336         i40e_clear_pxe_mode(hw);
1337
1338         /* Unconfigure filter control */
1339         memset(&settings, 0, sizeof(settings));
1340         ret = i40e_set_filter_control(hw, &settings);
1341         if (ret)
1342                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1343                                         ret);
1344
1345         /* Disable flow control */
1346         hw->fc.requested_mode = I40E_FC_NONE;
1347         i40e_set_fc(hw, &aq_fail, TRUE);
1348
1349         /* uninitialize pf host driver */
1350         i40e_pf_host_uninit(dev);
1351
1352         rte_free(dev->data->mac_addrs);
1353         dev->data->mac_addrs = NULL;
1354
1355         /* disable uio intr before callback unregister */
1356         rte_intr_disable(&(pci_dev->intr_handle));
1357
1358         /* register callback func to eal lib */
1359         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1360                 i40e_dev_interrupt_handler, (void *)dev);
1361
1362         return 0;
1363 }
1364
1365 static int
1366 i40e_dev_configure(struct rte_eth_dev *dev)
1367 {
1368         struct i40e_adapter *ad =
1369                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1371         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1372         int i, ret;
1373
1374         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1375          * bulk allocation or vector Rx preconditions we will reset it.
1376          */
1377         ad->rx_bulk_alloc_allowed = true;
1378         ad->rx_vec_allowed = true;
1379         ad->tx_simple_allowed = true;
1380         ad->tx_vec_allowed = true;
1381
1382         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1383                 ret = i40e_fdir_setup(pf);
1384                 if (ret != I40E_SUCCESS) {
1385                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1386                         return -ENOTSUP;
1387                 }
1388                 ret = i40e_fdir_configure(dev);
1389                 if (ret < 0) {
1390                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1391                         goto err;
1392                 }
1393         } else
1394                 i40e_fdir_teardown(pf);
1395
1396         ret = i40e_dev_init_vlan(dev);
1397         if (ret < 0)
1398                 goto err;
1399
1400         /* VMDQ setup.
1401          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1402          *  RSS setting have different requirements.
1403          *  General PMD driver call sequence are NIC init, configure,
1404          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1405          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1406          *  applicable. So, VMDQ setting has to be done before
1407          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1408          *  For RSS setting, it will try to calculate actual configured RX queue
1409          *  number, which will be available after rx_queue_setup(). dev_start()
1410          *  function is good to place RSS setup.
1411          */
1412         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1413                 ret = i40e_vmdq_setup(dev);
1414                 if (ret)
1415                         goto err;
1416         }
1417
1418         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1419                 ret = i40e_dcb_setup(dev);
1420                 if (ret) {
1421                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1422                         goto err_dcb;
1423                 }
1424         }
1425
1426         return 0;
1427
1428 err_dcb:
1429         /* need to release vmdq resource if exists */
1430         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1431                 i40e_vsi_release(pf->vmdq[i].vsi);
1432                 pf->vmdq[i].vsi = NULL;
1433         }
1434         rte_free(pf->vmdq);
1435         pf->vmdq = NULL;
1436 err:
1437         /* need to release fdir resource if exists */
1438         i40e_fdir_teardown(pf);
1439         return ret;
1440 }
1441
1442 void
1443 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1444 {
1445         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1446         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1447         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1448         uint16_t msix_vect = vsi->msix_intr;
1449         uint16_t i;
1450
1451         for (i = 0; i < vsi->nb_qps; i++) {
1452                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1453                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1454                 rte_wmb();
1455         }
1456
1457         if (vsi->type != I40E_VSI_SRIOV) {
1458                 if (!rte_intr_allow_others(intr_handle)) {
1459                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1460                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1461                         I40E_WRITE_REG(hw,
1462                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1463                                        0);
1464                 } else {
1465                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1466                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1467                         I40E_WRITE_REG(hw,
1468                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1469                                                        msix_vect - 1), 0);
1470                 }
1471         } else {
1472                 uint32_t reg;
1473                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1474                         vsi->user_param + (msix_vect - 1);
1475
1476                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1477                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1478         }
1479         I40E_WRITE_FLUSH(hw);
1480 }
1481
1482 static void
1483 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1484                        int base_queue, int nb_queue)
1485 {
1486         int i;
1487         uint32_t val;
1488         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1489         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1490
1491         /* Bind all RX queues to allocated MSIX interrupt */
1492         for (i = 0; i < nb_queue; i++) {
1493                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1494                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1495                         ((base_queue + i + 1) <<
1496                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1497                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1498                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1499
1500                 if (i == nb_queue - 1)
1501                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1502                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1503         }
1504
1505         /* Write first RX queue to Link list register as the head element */
1506         if (vsi->type != I40E_VSI_SRIOV) {
1507                 uint16_t interval =
1508                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL,
1509                                                pf->support_multi_driver);
1510
1511                 if (msix_vect == I40E_MISC_VEC_ID) {
1512                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1513                                        (base_queue <<
1514                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1515                                        (0x0 <<
1516                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1517                         I40E_WRITE_REG(hw,
1518                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1519                                        interval);
1520                 } else {
1521                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1522                                        (base_queue <<
1523                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1524                                        (0x0 <<
1525                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1526                         I40E_WRITE_REG(hw,
1527                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1528                                                        msix_vect - 1),
1529                                        interval);
1530                 }
1531         } else {
1532                 uint32_t reg;
1533
1534                 if (msix_vect == I40E_MISC_VEC_ID) {
1535                         I40E_WRITE_REG(hw,
1536                                        I40E_VPINT_LNKLST0(vsi->user_param),
1537                                        (base_queue <<
1538                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1539                                        (0x0 <<
1540                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1541                 } else {
1542                         /* num_msix_vectors_vf needs to minus irq0 */
1543                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1544                                 vsi->user_param + (msix_vect - 1);
1545
1546                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1547                                        (base_queue <<
1548                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1549                                        (0x0 <<
1550                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1551                 }
1552         }
1553
1554         I40E_WRITE_FLUSH(hw);
1555 }
1556
1557 void
1558 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1559 {
1560         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1561         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1562         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1563         uint16_t msix_vect = vsi->msix_intr;
1564         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1565         uint16_t queue_idx = 0;
1566         int record = 0;
1567         int i;
1568
1569         for (i = 0; i < vsi->nb_qps; i++) {
1570                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1571                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1572         }
1573
1574         /* VF bind interrupt */
1575         if (vsi->type == I40E_VSI_SRIOV) {
1576                 __vsi_queues_bind_intr(vsi, msix_vect,
1577                                        vsi->base_queue, vsi->nb_qps);
1578                 return;
1579         }
1580
1581         /* PF & VMDq bind interrupt */
1582         if (rte_intr_dp_is_en(intr_handle)) {
1583                 if (vsi->type == I40E_VSI_MAIN) {
1584                         queue_idx = 0;
1585                         record = 1;
1586                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1587                         struct i40e_vsi *main_vsi =
1588                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1589                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1590                         record = 1;
1591                 }
1592         }
1593
1594         for (i = 0; i < vsi->nb_used_qps; i++) {
1595                 if (nb_msix <= 1) {
1596                         if (!rte_intr_allow_others(intr_handle))
1597                                 /* allow to share MISC_VEC_ID */
1598                                 msix_vect = I40E_MISC_VEC_ID;
1599
1600                         /* no enough msix_vect, map all to one */
1601                         __vsi_queues_bind_intr(vsi, msix_vect,
1602                                                vsi->base_queue + i,
1603                                                vsi->nb_used_qps - i);
1604                         for (; !!record && i < vsi->nb_used_qps; i++)
1605                                 intr_handle->intr_vec[queue_idx + i] =
1606                                         msix_vect;
1607                         break;
1608                 }
1609                 /* 1:1 queue/msix_vect mapping */
1610                 __vsi_queues_bind_intr(vsi, msix_vect,
1611                                        vsi->base_queue + i, 1);
1612                 if (!!record)
1613                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1614
1615                 msix_vect++;
1616                 nb_msix--;
1617         }
1618 }
1619
1620 static void
1621 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1622 {
1623         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1624         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1625         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1626         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1627         uint16_t msix_intr, i;
1628
1629         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1630                 for (i = 0; i < vsi->nb_msix; i++) {
1631                         msix_intr = vsi->msix_intr + i;
1632                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1633                                        I40E_PFINT_DYN_CTLN_INTENA_MASK |
1634                                        I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1635                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1636                 }
1637         else
1638                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1639                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1640                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1641                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1642
1643         I40E_WRITE_FLUSH(hw);
1644 }
1645
1646 static void
1647 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1648 {
1649         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1650         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1651         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1652         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1653         uint16_t msix_intr, i;
1654
1655         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1656                 for (i = 0; i < vsi->nb_msix; i++) {
1657                         msix_intr = vsi->msix_intr + i;
1658                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1659                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1660                 }
1661         else
1662                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1663                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1664
1665         I40E_WRITE_FLUSH(hw);
1666 }
1667
1668 static inline uint8_t
1669 i40e_parse_link_speeds(uint16_t link_speeds)
1670 {
1671         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1672
1673         if (link_speeds & ETH_LINK_SPEED_40G)
1674                 link_speed |= I40E_LINK_SPEED_40GB;
1675         if (link_speeds & ETH_LINK_SPEED_25G)
1676                 link_speed |= I40E_LINK_SPEED_25GB;
1677         if (link_speeds & ETH_LINK_SPEED_20G)
1678                 link_speed |= I40E_LINK_SPEED_20GB;
1679         if (link_speeds & ETH_LINK_SPEED_10G)
1680                 link_speed |= I40E_LINK_SPEED_10GB;
1681         if (link_speeds & ETH_LINK_SPEED_1G)
1682                 link_speed |= I40E_LINK_SPEED_1GB;
1683         if (link_speeds & ETH_LINK_SPEED_100M)
1684                 link_speed |= I40E_LINK_SPEED_100MB;
1685
1686         return link_speed;
1687 }
1688
1689 static int
1690 i40e_phy_conf_link(struct i40e_hw *hw,
1691                    uint8_t abilities,
1692                    uint8_t force_speed,
1693                    bool is_up)
1694 {
1695         enum i40e_status_code status;
1696         struct i40e_aq_get_phy_abilities_resp phy_ab;
1697         struct i40e_aq_set_phy_config phy_conf;
1698         enum i40e_aq_phy_type cnt;
1699         uint32_t phy_type_mask = 0;
1700
1701         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1702                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1703                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1704                         I40E_AQ_PHY_FLAG_LOW_POWER;
1705         const uint8_t advt = I40E_LINK_SPEED_40GB |
1706                         I40E_LINK_SPEED_25GB |
1707                         I40E_LINK_SPEED_10GB |
1708                         I40E_LINK_SPEED_1GB |
1709                         I40E_LINK_SPEED_100MB;
1710         int ret = -ENOTSUP;
1711
1712
1713         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1714                                               NULL);
1715         if (status)
1716                 return ret;
1717
1718         /* If link already up, no need to set up again */
1719         if (is_up && phy_ab.phy_type != 0)
1720                 return I40E_SUCCESS;
1721
1722         memset(&phy_conf, 0, sizeof(phy_conf));
1723
1724         /* bits 0-2 use the values from get_phy_abilities_resp */
1725         abilities &= ~mask;
1726         abilities |= phy_ab.abilities & mask;
1727
1728         /* update ablities and speed */
1729         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1730                 phy_conf.link_speed = advt;
1731         else
1732                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1733
1734         phy_conf.abilities = abilities;
1735
1736
1737
1738         /* To enable link, phy_type mask needs to include each type */
1739         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1740                 phy_type_mask |= 1 << cnt;
1741
1742         /* use get_phy_abilities_resp value for the rest */
1743         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1744         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1745                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1746                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1747         phy_conf.fec_config = phy_ab.mod_type_ext;
1748         phy_conf.eee_capability = phy_ab.eee_capability;
1749         phy_conf.eeer = phy_ab.eeer_val;
1750         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1751
1752         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1753                     phy_ab.abilities, phy_ab.link_speed);
1754         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1755                     phy_conf.abilities, phy_conf.link_speed);
1756
1757         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1758         if (status)
1759                 return ret;
1760
1761         return I40E_SUCCESS;
1762 }
1763
1764 static int
1765 i40e_apply_link_speed(struct rte_eth_dev *dev)
1766 {
1767         uint8_t speed;
1768         uint8_t abilities = 0;
1769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct rte_eth_conf *conf = &dev->data->dev_conf;
1771
1772         speed = i40e_parse_link_speeds(conf->link_speeds);
1773         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1774         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1775                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1776         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1777
1778         return i40e_phy_conf_link(hw, abilities, speed, true);
1779 }
1780
1781 static int
1782 i40e_dev_start(struct rte_eth_dev *dev)
1783 {
1784         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786         struct i40e_vsi *main_vsi = pf->main_vsi;
1787         int ret, i;
1788         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1789         uint32_t intr_vector = 0;
1790
1791         hw->adapter_stopped = 0;
1792
1793         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1794                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1795                              dev->data->port_id);
1796                 return -EINVAL;
1797         }
1798
1799         rte_intr_disable(intr_handle);
1800
1801         if ((rte_intr_cap_multiple(intr_handle) ||
1802              !RTE_ETH_DEV_SRIOV(dev).active) &&
1803             dev->data->dev_conf.intr_conf.rxq != 0) {
1804                 intr_vector = dev->data->nb_rx_queues;
1805                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1806                         return -1;
1807         }
1808
1809         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1810                 intr_handle->intr_vec =
1811                         rte_zmalloc("intr_vec",
1812                                     dev->data->nb_rx_queues * sizeof(int),
1813                                     0);
1814                 if (!intr_handle->intr_vec) {
1815                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1816                                      " intr_vec\n", dev->data->nb_rx_queues);
1817                         return -ENOMEM;
1818                 }
1819         }
1820
1821         /* Initialize VSI */
1822         ret = i40e_dev_rxtx_init(pf);
1823         if (ret != I40E_SUCCESS) {
1824                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1825                 goto err_up;
1826         }
1827
1828         /* Map queues with MSIX interrupt */
1829         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1830                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1831         i40e_vsi_queues_bind_intr(main_vsi);
1832         i40e_vsi_enable_queues_intr(main_vsi);
1833
1834         /* Map VMDQ VSI queues with MSIX interrupt */
1835         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1836                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1837                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1838                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1839         }
1840
1841         /* enable FDIR MSIX interrupt */
1842         if (pf->fdir.fdir_vsi) {
1843                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1844                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1845         }
1846
1847         /* Enable all queues which have been configured */
1848         ret = i40e_dev_switch_queues(pf, TRUE);
1849         if (ret != I40E_SUCCESS) {
1850                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1851                 goto err_up;
1852         }
1853
1854         /* Enable receiving broadcast packets */
1855         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1856         if (ret != I40E_SUCCESS)
1857                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1858
1859         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1860                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1861                                                 true, NULL);
1862                 if (ret != I40E_SUCCESS)
1863                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1864         }
1865
1866         /* Apply link configure */
1867         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1868                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1869                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1870                                 ETH_LINK_SPEED_40G)) {
1871                 PMD_DRV_LOG(ERR, "Invalid link setting");
1872                 goto err_up;
1873         }
1874         ret = i40e_apply_link_speed(dev);
1875         if (I40E_SUCCESS != ret) {
1876                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1877                 goto err_up;
1878         }
1879
1880         if (!rte_intr_allow_others(intr_handle)) {
1881                 rte_intr_callback_unregister(intr_handle,
1882                                              i40e_dev_interrupt_handler,
1883                                              (void *)dev);
1884                 /* configure and enable device interrupt */
1885                 i40e_pf_config_irq0(hw, FALSE);
1886                 i40e_pf_enable_irq0(hw);
1887
1888                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1889                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1890                                      " no intr multiplex\n");
1891         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1892                 ret = i40e_aq_set_phy_int_mask(hw,
1893                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1894                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1895                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1896                 if (ret != I40E_SUCCESS)
1897                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1898
1899                 /* Call get_link_info aq commond to enable LSE */
1900                 i40e_dev_link_update(dev, 0);
1901         }
1902
1903         /* enable uio intr after callback register */
1904         rte_intr_enable(intr_handle);
1905
1906         return I40E_SUCCESS;
1907
1908 err_up:
1909         i40e_dev_switch_queues(pf, FALSE);
1910         i40e_dev_clear_queues(dev);
1911
1912         return ret;
1913 }
1914
1915 static void
1916 i40e_dev_stop(struct rte_eth_dev *dev)
1917 {
1918         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1919         struct i40e_vsi *main_vsi = pf->main_vsi;
1920         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1921         int i;
1922
1923         /* Disable all queues */
1924         i40e_dev_switch_queues(pf, FALSE);
1925
1926         /* un-map queues with interrupt registers */
1927         i40e_vsi_disable_queues_intr(main_vsi);
1928         i40e_vsi_queues_unbind_intr(main_vsi);
1929
1930         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1931                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1932                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1933         }
1934
1935         if (pf->fdir.fdir_vsi) {
1936                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1937                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1938         }
1939         /* Clear all queues and release memory */
1940         i40e_dev_clear_queues(dev);
1941
1942         /* Set link down */
1943         i40e_dev_set_link_down(dev);
1944
1945         if (!rte_intr_allow_others(intr_handle))
1946                 /* resume to the default handler */
1947                 rte_intr_callback_register(intr_handle,
1948                                            i40e_dev_interrupt_handler,
1949                                            (void *)dev);
1950
1951         /* Clean datapath event and queue/vec mapping */
1952         rte_intr_efd_disable(intr_handle);
1953         if (intr_handle->intr_vec) {
1954                 rte_free(intr_handle->intr_vec);
1955                 intr_handle->intr_vec = NULL;
1956         }
1957 }
1958
1959 static void
1960 i40e_dev_close(struct rte_eth_dev *dev)
1961 {
1962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964         struct i40e_mirror_rule *p_mirror;
1965         uint32_t reg;
1966         int i;
1967         int ret;
1968
1969         PMD_INIT_FUNC_TRACE();
1970
1971         i40e_dev_stop(dev);
1972         hw->adapter_stopped = 1;
1973
1974         /* Remove all mirror rules */
1975         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1976                 ret = i40e_aq_del_mirror_rule(hw,
1977                                               pf->main_vsi->veb->seid,
1978                                               p_mirror->rule_type,
1979                                               p_mirror->entries,
1980                                               p_mirror->num_entries,
1981                                               p_mirror->id);
1982                 if (ret < 0)
1983                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
1984                                     "status = %d, aq_err = %d.", ret,
1985                                     hw->aq.asq_last_status);
1986
1987                 /* remove mirror software resource anyway */
1988                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1989                 rte_free(p_mirror);
1990                 pf->nb_mirror_rule--;
1991         }
1992
1993         i40e_dev_free_queues(dev);
1994
1995         /* Disable interrupt */
1996         i40e_pf_disable_irq0(hw);
1997         rte_intr_disable(&(dev->pci_dev->intr_handle));
1998
1999         /* shutdown and destroy the HMC */
2000         i40e_shutdown_lan_hmc(hw);
2001
2002         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2003                 i40e_vsi_release(pf->vmdq[i].vsi);
2004                 pf->vmdq[i].vsi = NULL;
2005         }
2006         rte_free(pf->vmdq);
2007         pf->vmdq = NULL;
2008
2009         /* release all the existing VSIs and VEBs */
2010         i40e_fdir_teardown(pf);
2011         i40e_vsi_release(pf->main_vsi);
2012
2013         /* shutdown the adminq */
2014         i40e_aq_queue_shutdown(hw, true);
2015         i40e_shutdown_adminq(hw);
2016
2017         i40e_res_pool_destroy(&pf->qp_pool);
2018         i40e_res_pool_destroy(&pf->msix_pool);
2019
2020         /* force a PF reset to clean anything leftover */
2021         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2022         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2023                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2024         I40E_WRITE_FLUSH(hw);
2025 }
2026
2027 static void
2028 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2029 {
2030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032         struct i40e_vsi *vsi = pf->main_vsi;
2033         int status;
2034
2035         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2036                                                      true, NULL, true);
2037         if (status != I40E_SUCCESS)
2038                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2039
2040         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2041                                                         TRUE, NULL);
2042         if (status != I40E_SUCCESS)
2043                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2044
2045 }
2046
2047 static void
2048 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2049 {
2050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2051         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         struct i40e_vsi *vsi = pf->main_vsi;
2053         int status;
2054
2055         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2056                                                      false, NULL, true);
2057         if (status != I40E_SUCCESS)
2058                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2059
2060         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2061                                                         false, NULL);
2062         if (status != I40E_SUCCESS)
2063                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2064 }
2065
2066 static void
2067 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2068 {
2069         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2070         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071         struct i40e_vsi *vsi = pf->main_vsi;
2072         int ret;
2073
2074         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2075         if (ret != I40E_SUCCESS)
2076                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2077 }
2078
2079 static void
2080 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2081 {
2082         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2083         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         struct i40e_vsi *vsi = pf->main_vsi;
2085         int ret;
2086
2087         if (dev->data->promiscuous == 1)
2088                 return; /* must remain in all_multicast mode */
2089
2090         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2091                                 vsi->seid, FALSE, NULL);
2092         if (ret != I40E_SUCCESS)
2093                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2094 }
2095
2096 /*
2097  * Set device link up.
2098  */
2099 static int
2100 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2101 {
2102         /* re-apply link speed setting */
2103         return i40e_apply_link_speed(dev);
2104 }
2105
2106 /*
2107  * Set device link down.
2108  */
2109 static int
2110 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2111 {
2112         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2113         uint8_t abilities = 0;
2114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115
2116         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2117         return i40e_phy_conf_link(hw, abilities, speed, false);
2118 }
2119
2120 int
2121 i40e_dev_link_update(struct rte_eth_dev *dev,
2122                      int wait_to_complete)
2123 {
2124 #define CHECK_INTERVAL 100  /* 100ms */
2125 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2126         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127         struct i40e_link_status link_status;
2128         struct rte_eth_link link, old;
2129         int status;
2130         unsigned rep_cnt = MAX_REPEAT_TIME;
2131         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2132
2133         memset(&link, 0, sizeof(link));
2134         memset(&old, 0, sizeof(old));
2135         memset(&link_status, 0, sizeof(link_status));
2136         rte_i40e_dev_atomic_read_link_status(dev, &old);
2137
2138         do {
2139                 /* Get link status information from hardware */
2140                 status = i40e_aq_get_link_info(hw, enable_lse,
2141                                                 &link_status, NULL);
2142                 if (status != I40E_SUCCESS) {
2143                         link.link_speed = ETH_SPEED_NUM_100M;
2144                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2145                         PMD_DRV_LOG(ERR, "Failed to get link info");
2146                         goto out;
2147                 }
2148
2149                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2150                 if (!wait_to_complete || link.link_status)
2151                         break;
2152
2153                 rte_delay_ms(CHECK_INTERVAL);
2154         } while (--rep_cnt);
2155
2156         if (!link.link_status)
2157                 goto out;
2158
2159         /* i40e uses full duplex only */
2160         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2161
2162         /* Parse the link status */
2163         switch (link_status.link_speed) {
2164         case I40E_LINK_SPEED_100MB:
2165                 link.link_speed = ETH_SPEED_NUM_100M;
2166                 break;
2167         case I40E_LINK_SPEED_1GB:
2168                 link.link_speed = ETH_SPEED_NUM_1G;
2169                 break;
2170         case I40E_LINK_SPEED_10GB:
2171                 link.link_speed = ETH_SPEED_NUM_10G;
2172                 break;
2173         case I40E_LINK_SPEED_20GB:
2174                 link.link_speed = ETH_SPEED_NUM_20G;
2175                 break;
2176         case I40E_LINK_SPEED_25GB:
2177                 link.link_speed = ETH_SPEED_NUM_25G;
2178                 break;
2179         case I40E_LINK_SPEED_40GB:
2180                 link.link_speed = ETH_SPEED_NUM_40G;
2181                 break;
2182         default:
2183                 link.link_speed = ETH_SPEED_NUM_100M;
2184                 break;
2185         }
2186
2187         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2188                         ETH_LINK_SPEED_FIXED);
2189
2190 out:
2191         rte_i40e_dev_atomic_write_link_status(dev, &link);
2192         if (link.link_status == old.link_status)
2193                 return -1;
2194
2195         i40e_notify_all_vfs_link_status(dev);
2196
2197         return 0;
2198 }
2199
2200 /* Get all the statistics of a VSI */
2201 void
2202 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2203 {
2204         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2205         struct i40e_eth_stats *nes = &vsi->eth_stats;
2206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2207         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2208
2209         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2210                             vsi->offset_loaded, &oes->rx_bytes,
2211                             &nes->rx_bytes);
2212         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2213                             vsi->offset_loaded, &oes->rx_unicast,
2214                             &nes->rx_unicast);
2215         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2216                             vsi->offset_loaded, &oes->rx_multicast,
2217                             &nes->rx_multicast);
2218         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2219                             vsi->offset_loaded, &oes->rx_broadcast,
2220                             &nes->rx_broadcast);
2221         /* exclude CRC bytes */
2222         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2223                 nes->rx_broadcast) * ETHER_CRC_LEN;
2224
2225         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2226                             &oes->rx_discards, &nes->rx_discards);
2227         /* GLV_REPC not supported */
2228         /* GLV_RMPC not supported */
2229         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2230                             &oes->rx_unknown_protocol,
2231                             &nes->rx_unknown_protocol);
2232         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2233                             vsi->offset_loaded, &oes->tx_bytes,
2234                             &nes->tx_bytes);
2235         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2236                             vsi->offset_loaded, &oes->tx_unicast,
2237                             &nes->tx_unicast);
2238         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2239                             vsi->offset_loaded, &oes->tx_multicast,
2240                             &nes->tx_multicast);
2241         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2242                             vsi->offset_loaded,  &oes->tx_broadcast,
2243                             &nes->tx_broadcast);
2244         /* exclude CRC bytes */
2245         nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2246                 nes->tx_broadcast) * ETHER_CRC_LEN;
2247         /* GLV_TDPC not supported */
2248         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2249                             &oes->tx_errors, &nes->tx_errors);
2250         vsi->offset_loaded = true;
2251
2252         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2253                     vsi->vsi_id);
2254         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2255         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2256         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2257         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2258         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2259         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2260                     nes->rx_unknown_protocol);
2261         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2262         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2263         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2264         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2265         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2266         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2267         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2268                     vsi->vsi_id);
2269 }
2270
2271 static void
2272 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2273 {
2274         unsigned int i;
2275         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2276         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2277
2278         /* Get rx/tx bytes of internal transfer packets */
2279         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2280                         I40E_GLV_GORCL(hw->port),
2281                         pf->offset_loaded,
2282                         &pf->internal_rx_bytes_offset,
2283                         &pf->internal_rx_bytes);
2284
2285         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2286                         I40E_GLV_GOTCL(hw->port),
2287                         pf->offset_loaded,
2288                         &pf->internal_tx_bytes_offset,
2289                         &pf->internal_tx_bytes);
2290
2291         /* Get statistics of struct i40e_eth_stats */
2292         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2293                             I40E_GLPRT_GORCL(hw->port),
2294                             pf->offset_loaded, &os->eth.rx_bytes,
2295                             &ns->eth.rx_bytes);
2296         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2297                             I40E_GLPRT_UPRCL(hw->port),
2298                             pf->offset_loaded, &os->eth.rx_unicast,
2299                             &ns->eth.rx_unicast);
2300         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2301                             I40E_GLPRT_MPRCL(hw->port),
2302                             pf->offset_loaded, &os->eth.rx_multicast,
2303                             &ns->eth.rx_multicast);
2304         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2305                             I40E_GLPRT_BPRCL(hw->port),
2306                             pf->offset_loaded, &os->eth.rx_broadcast,
2307                             &ns->eth.rx_broadcast);
2308         /* Workaround: CRC size should not be included in byte statistics,
2309          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2310          */
2311         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2312                 ns->eth.rx_broadcast) * ETHER_CRC_LEN + pf->internal_rx_bytes;
2313
2314         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2315                             pf->offset_loaded, &os->eth.rx_discards,
2316                             &ns->eth.rx_discards);
2317         /* GLPRT_REPC not supported */
2318         /* GLPRT_RMPC not supported */
2319         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2320                             pf->offset_loaded,
2321                             &os->eth.rx_unknown_protocol,
2322                             &ns->eth.rx_unknown_protocol);
2323         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2324                             I40E_GLPRT_GOTCL(hw->port),
2325                             pf->offset_loaded, &os->eth.tx_bytes,
2326                             &ns->eth.tx_bytes);
2327         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2328                             I40E_GLPRT_UPTCL(hw->port),
2329                             pf->offset_loaded, &os->eth.tx_unicast,
2330                             &ns->eth.tx_unicast);
2331         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2332                             I40E_GLPRT_MPTCL(hw->port),
2333                             pf->offset_loaded, &os->eth.tx_multicast,
2334                             &ns->eth.tx_multicast);
2335         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2336                             I40E_GLPRT_BPTCL(hw->port),
2337                             pf->offset_loaded, &os->eth.tx_broadcast,
2338                             &ns->eth.tx_broadcast);
2339         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2340                 ns->eth.tx_broadcast) * ETHER_CRC_LEN + pf->internal_tx_bytes;
2341         /* GLPRT_TEPC not supported */
2342
2343         /* additional port specific stats */
2344         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2345                             pf->offset_loaded, &os->tx_dropped_link_down,
2346                             &ns->tx_dropped_link_down);
2347         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2348                             pf->offset_loaded, &os->crc_errors,
2349                             &ns->crc_errors);
2350         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2351                             pf->offset_loaded, &os->illegal_bytes,
2352                             &ns->illegal_bytes);
2353         /* GLPRT_ERRBC not supported */
2354         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2355                             pf->offset_loaded, &os->mac_local_faults,
2356                             &ns->mac_local_faults);
2357         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2358                             pf->offset_loaded, &os->mac_remote_faults,
2359                             &ns->mac_remote_faults);
2360         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2361                             pf->offset_loaded, &os->rx_length_errors,
2362                             &ns->rx_length_errors);
2363         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2364                             pf->offset_loaded, &os->link_xon_rx,
2365                             &ns->link_xon_rx);
2366         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2367                             pf->offset_loaded, &os->link_xoff_rx,
2368                             &ns->link_xoff_rx);
2369         for (i = 0; i < 8; i++) {
2370                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2371                                     pf->offset_loaded,
2372                                     &os->priority_xon_rx[i],
2373                                     &ns->priority_xon_rx[i]);
2374                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2375                                     pf->offset_loaded,
2376                                     &os->priority_xoff_rx[i],
2377                                     &ns->priority_xoff_rx[i]);
2378         }
2379         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2380                             pf->offset_loaded, &os->link_xon_tx,
2381                             &ns->link_xon_tx);
2382         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2383                             pf->offset_loaded, &os->link_xoff_tx,
2384                             &ns->link_xoff_tx);
2385         for (i = 0; i < 8; i++) {
2386                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2387                                     pf->offset_loaded,
2388                                     &os->priority_xon_tx[i],
2389                                     &ns->priority_xon_tx[i]);
2390                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2391                                     pf->offset_loaded,
2392                                     &os->priority_xoff_tx[i],
2393                                     &ns->priority_xoff_tx[i]);
2394                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2395                                     pf->offset_loaded,
2396                                     &os->priority_xon_2_xoff[i],
2397                                     &ns->priority_xon_2_xoff[i]);
2398         }
2399         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2400                             I40E_GLPRT_PRC64L(hw->port),
2401                             pf->offset_loaded, &os->rx_size_64,
2402                             &ns->rx_size_64);
2403         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2404                             I40E_GLPRT_PRC127L(hw->port),
2405                             pf->offset_loaded, &os->rx_size_127,
2406                             &ns->rx_size_127);
2407         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2408                             I40E_GLPRT_PRC255L(hw->port),
2409                             pf->offset_loaded, &os->rx_size_255,
2410                             &ns->rx_size_255);
2411         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2412                             I40E_GLPRT_PRC511L(hw->port),
2413                             pf->offset_loaded, &os->rx_size_511,
2414                             &ns->rx_size_511);
2415         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2416                             I40E_GLPRT_PRC1023L(hw->port),
2417                             pf->offset_loaded, &os->rx_size_1023,
2418                             &ns->rx_size_1023);
2419         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2420                             I40E_GLPRT_PRC1522L(hw->port),
2421                             pf->offset_loaded, &os->rx_size_1522,
2422                             &ns->rx_size_1522);
2423         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2424                             I40E_GLPRT_PRC9522L(hw->port),
2425                             pf->offset_loaded, &os->rx_size_big,
2426                             &ns->rx_size_big);
2427         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2428                             pf->offset_loaded, &os->rx_undersize,
2429                             &ns->rx_undersize);
2430         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2431                             pf->offset_loaded, &os->rx_fragments,
2432                             &ns->rx_fragments);
2433         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2434                             pf->offset_loaded, &os->rx_oversize,
2435                             &ns->rx_oversize);
2436         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2437                             pf->offset_loaded, &os->rx_jabber,
2438                             &ns->rx_jabber);
2439         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2440                             I40E_GLPRT_PTC64L(hw->port),
2441                             pf->offset_loaded, &os->tx_size_64,
2442                             &ns->tx_size_64);
2443         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2444                             I40E_GLPRT_PTC127L(hw->port),
2445                             pf->offset_loaded, &os->tx_size_127,
2446                             &ns->tx_size_127);
2447         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2448                             I40E_GLPRT_PTC255L(hw->port),
2449                             pf->offset_loaded, &os->tx_size_255,
2450                             &ns->tx_size_255);
2451         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2452                             I40E_GLPRT_PTC511L(hw->port),
2453                             pf->offset_loaded, &os->tx_size_511,
2454                             &ns->tx_size_511);
2455         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2456                             I40E_GLPRT_PTC1023L(hw->port),
2457                             pf->offset_loaded, &os->tx_size_1023,
2458                             &ns->tx_size_1023);
2459         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2460                             I40E_GLPRT_PTC1522L(hw->port),
2461                             pf->offset_loaded, &os->tx_size_1522,
2462                             &ns->tx_size_1522);
2463         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2464                             I40E_GLPRT_PTC9522L(hw->port),
2465                             pf->offset_loaded, &os->tx_size_big,
2466                             &ns->tx_size_big);
2467         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2468                            pf->offset_loaded,
2469                            &os->fd_sb_match, &ns->fd_sb_match);
2470         /* GLPRT_MSPDC not supported */
2471         /* GLPRT_XEC not supported */
2472
2473         pf->offset_loaded = true;
2474
2475         if (pf->main_vsi)
2476                 i40e_update_vsi_stats(pf->main_vsi);
2477 }
2478
2479 /* Get all statistics of a port */
2480 static void
2481 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2482 {
2483         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2484         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2485         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2486         unsigned i;
2487
2488         /* call read registers - updates values, now write them to struct */
2489         i40e_read_stats_registers(pf, hw);
2490
2491         stats->ipackets = ns->eth.rx_unicast +
2492                         ns->eth.rx_multicast +
2493                         ns->eth.rx_broadcast -
2494                         ns->eth.rx_discards -
2495                         pf->main_vsi->eth_stats.rx_discards;
2496         stats->opackets = ns->eth.tx_unicast +
2497                         ns->eth.tx_multicast +
2498                         ns->eth.tx_broadcast;
2499         stats->ibytes   = ns->eth.rx_bytes;
2500         stats->obytes   = ns->eth.tx_bytes;
2501         stats->oerrors  = ns->eth.tx_errors +
2502                         pf->main_vsi->eth_stats.tx_errors;
2503
2504         /* Rx Errors */
2505         stats->imissed  = ns->eth.rx_discards +
2506                         pf->main_vsi->eth_stats.rx_discards;
2507         stats->ierrors  = ns->crc_errors +
2508                         ns->rx_length_errors + ns->rx_undersize +
2509                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2510
2511         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2512         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2513         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2514         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2515         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2516         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2517         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2518                     ns->eth.rx_unknown_protocol);
2519         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2520         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2521         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2522         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2523         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2524         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2525
2526         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2527                     ns->tx_dropped_link_down);
2528         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2529         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2530                     ns->illegal_bytes);
2531         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2532         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2533                     ns->mac_local_faults);
2534         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2535                     ns->mac_remote_faults);
2536         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2537                     ns->rx_length_errors);
2538         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2539         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2540         for (i = 0; i < 8; i++) {
2541                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2542                                 i, ns->priority_xon_rx[i]);
2543                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2544                                 i, ns->priority_xoff_rx[i]);
2545         }
2546         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2547         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2548         for (i = 0; i < 8; i++) {
2549                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2550                                 i, ns->priority_xon_tx[i]);
2551                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2552                                 i, ns->priority_xoff_tx[i]);
2553                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2554                                 i, ns->priority_xon_2_xoff[i]);
2555         }
2556         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2557         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2558         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2559         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2560         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2561         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2562         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2563         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2564         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2565         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2566         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2567         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2568         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2569         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2570         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2571         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2572         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2573         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2574         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2575                         ns->mac_short_packet_dropped);
2576         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2577                     ns->checksum_error);
2578         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2579         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2580 }
2581
2582 /* Reset the statistics */
2583 static void
2584 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2585 {
2586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2588
2589         /* Mark PF and VSI stats to update the offset, aka "reset" */
2590         pf->offset_loaded = false;
2591         if (pf->main_vsi)
2592                 pf->main_vsi->offset_loaded = false;
2593
2594         /* read the stats, reading current register values into offset */
2595         i40e_read_stats_registers(pf, hw);
2596 }
2597
2598 static uint32_t
2599 i40e_xstats_calc_num(void)
2600 {
2601         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2602                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2603                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2604 }
2605
2606 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2607                                      struct rte_eth_xstat_name *xstats_names,
2608                                      __rte_unused unsigned limit)
2609 {
2610         unsigned count = 0;
2611         unsigned i, prio;
2612
2613         if (xstats_names == NULL)
2614                 return i40e_xstats_calc_num();
2615
2616         /* Note: limit checked in rte_eth_xstats_names() */
2617
2618         /* Get stats from i40e_eth_stats struct */
2619         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2620                 snprintf(xstats_names[count].name,
2621                          sizeof(xstats_names[count].name),
2622                          "%s", rte_i40e_stats_strings[i].name);
2623                 count++;
2624         }
2625
2626         /* Get individiual stats from i40e_hw_port struct */
2627         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2628                 snprintf(xstats_names[count].name,
2629                         sizeof(xstats_names[count].name),
2630                          "%s", rte_i40e_hw_port_strings[i].name);
2631                 count++;
2632         }
2633
2634         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2635                 for (prio = 0; prio < 8; prio++) {
2636                         snprintf(xstats_names[count].name,
2637                                  sizeof(xstats_names[count].name),
2638                                  "rx_priority%u_%s", prio,
2639                                  rte_i40e_rxq_prio_strings[i].name);
2640                         count++;
2641                 }
2642         }
2643
2644         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2645                 for (prio = 0; prio < 8; prio++) {
2646                         snprintf(xstats_names[count].name,
2647                                  sizeof(xstats_names[count].name),
2648                                  "tx_priority%u_%s", prio,
2649                                  rte_i40e_txq_prio_strings[i].name);
2650                         count++;
2651                 }
2652         }
2653         return count;
2654 }
2655
2656 static int
2657 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2658                     unsigned n)
2659 {
2660         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662         unsigned i, count, prio;
2663         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2664
2665         count = i40e_xstats_calc_num();
2666         if (n < count)
2667                 return count;
2668
2669         i40e_read_stats_registers(pf, hw);
2670
2671         if (xstats == NULL)
2672                 return 0;
2673
2674         count = 0;
2675
2676         /* Get stats from i40e_eth_stats struct */
2677         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2678                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2679                         rte_i40e_stats_strings[i].offset);
2680                 xstats[count].id = count;
2681                 count++;
2682         }
2683
2684         /* Get individiual stats from i40e_hw_port struct */
2685         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2686                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2687                         rte_i40e_hw_port_strings[i].offset);
2688                 xstats[count].id = count;
2689                 count++;
2690         }
2691
2692         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2693                 for (prio = 0; prio < 8; prio++) {
2694                         xstats[count].value =
2695                                 *(uint64_t *)(((char *)hw_stats) +
2696                                 rte_i40e_rxq_prio_strings[i].offset +
2697                                 (sizeof(uint64_t) * prio));
2698                         xstats[count].id = count;
2699                         count++;
2700                 }
2701         }
2702
2703         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2704                 for (prio = 0; prio < 8; prio++) {
2705                         xstats[count].value =
2706                                 *(uint64_t *)(((char *)hw_stats) +
2707                                 rte_i40e_txq_prio_strings[i].offset +
2708                                 (sizeof(uint64_t) * prio));
2709                         xstats[count].id = count;
2710                         count++;
2711                 }
2712         }
2713
2714         return count;
2715 }
2716
2717 static int
2718 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2719                                  __rte_unused uint16_t queue_id,
2720                                  __rte_unused uint8_t stat_idx,
2721                                  __rte_unused uint8_t is_rx)
2722 {
2723         PMD_INIT_FUNC_TRACE();
2724
2725         return -ENOSYS;
2726 }
2727
2728 static void
2729 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2730 {
2731         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2732         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2733         struct i40e_vsi *vsi = pf->main_vsi;
2734
2735         dev_info->max_rx_queues = vsi->nb_qps;
2736         dev_info->max_tx_queues = vsi->nb_qps;
2737         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2738         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2739         dev_info->max_mac_addrs = vsi->max_macaddrs;
2740         dev_info->max_vfs = dev->pci_dev->max_vfs;
2741         dev_info->rx_offload_capa =
2742                 DEV_RX_OFFLOAD_VLAN_STRIP |
2743                 DEV_RX_OFFLOAD_QINQ_STRIP |
2744                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2745                 DEV_RX_OFFLOAD_UDP_CKSUM |
2746                 DEV_RX_OFFLOAD_TCP_CKSUM;
2747         dev_info->tx_offload_capa =
2748                 DEV_TX_OFFLOAD_VLAN_INSERT |
2749                 DEV_TX_OFFLOAD_QINQ_INSERT |
2750                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2751                 DEV_TX_OFFLOAD_UDP_CKSUM |
2752                 DEV_TX_OFFLOAD_TCP_CKSUM |
2753                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2754                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2755                 DEV_TX_OFFLOAD_TCP_TSO |
2756                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2757                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2758                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2759                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2760         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2761                                                 sizeof(uint32_t);
2762         dev_info->reta_size = pf->hash_lut_size;
2763         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2764
2765         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2766                 .rx_thresh = {
2767                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2768                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2769                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2770                 },
2771                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2772                 .rx_drop_en = 0,
2773         };
2774
2775         dev_info->default_txconf = (struct rte_eth_txconf) {
2776                 .tx_thresh = {
2777                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2778                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2779                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2780                 },
2781                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2782                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2783                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2784                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2785         };
2786
2787         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2788                 .nb_max = I40E_MAX_RING_DESC,
2789                 .nb_min = I40E_MIN_RING_DESC,
2790                 .nb_align = I40E_ALIGN_RING_DESC,
2791         };
2792
2793         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2794                 .nb_max = I40E_MAX_RING_DESC,
2795                 .nb_min = I40E_MIN_RING_DESC,
2796                 .nb_align = I40E_ALIGN_RING_DESC,
2797         };
2798
2799         if (pf->flags & I40E_FLAG_VMDQ) {
2800                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2801                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2802                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2803                                                 pf->max_nb_vmdq_vsi;
2804                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2805                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2806                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2807         }
2808
2809         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2810                 /* For XL710 */
2811                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2812         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2813                 /* For XXV710 */
2814                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2815         else
2816                 /* For X710 */
2817                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2818 }
2819
2820 static int
2821 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2822 {
2823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2824         struct i40e_vsi *vsi = pf->main_vsi;
2825         PMD_INIT_FUNC_TRACE();
2826
2827         if (on)
2828                 return i40e_vsi_add_vlan(vsi, vlan_id);
2829         else
2830                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2831 }
2832
2833 static int
2834 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2835                    enum rte_vlan_type vlan_type,
2836                    uint16_t tpid)
2837 {
2838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2840         uint64_t reg_r = 0, reg_w = 0;
2841         uint16_t reg_id = 0;
2842         int ret = 0;
2843         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2844
2845         if (pf->support_multi_driver) {
2846                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
2847                 return -ENOTSUP;
2848         }
2849
2850         switch (vlan_type) {
2851         case ETH_VLAN_TYPE_OUTER:
2852                 if (qinq)
2853                         reg_id = 2;
2854                 else
2855                         reg_id = 3;
2856                 break;
2857         case ETH_VLAN_TYPE_INNER:
2858                 if (qinq)
2859                         reg_id = 3;
2860                 else {
2861                         ret = -EINVAL;
2862                         PMD_DRV_LOG(ERR,
2863                                 "Unsupported vlan type in single vlan.\n");
2864                         return ret;
2865                 }
2866                 break;
2867         default:
2868                 ret = -EINVAL;
2869                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2870                 return ret;
2871         }
2872         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2873                                           &reg_r, NULL);
2874         if (ret != I40E_SUCCESS) {
2875                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2876                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2877                 ret = -EIO;
2878                 return ret;
2879         }
2880         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2881                     "0x%08"PRIx64"", reg_id, reg_r);
2882
2883         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2884         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2885         if (reg_r == reg_w) {
2886                 ret = 0;
2887                 PMD_DRV_LOG(DEBUG, "No need to write");
2888                 return ret;
2889         }
2890
2891         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2892                                            reg_w, NULL);
2893         if (ret != I40E_SUCCESS) {
2894                 ret = -EIO;
2895                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2896                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2897                 return ret;
2898         }
2899         PMD_DRV_LOG(DEBUG,
2900                     "Global register 0x%08x is changed with value 0x%08x",
2901                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
2902
2903         i40e_global_cfg_warning(I40E_WARNING_TPID);
2904
2905         return ret;
2906 }
2907
2908 static void
2909 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2910 {
2911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2912         struct i40e_vsi *vsi = pf->main_vsi;
2913
2914         if (mask & ETH_VLAN_FILTER_MASK) {
2915                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2916                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2917                 else
2918                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2919         }
2920
2921         if (mask & ETH_VLAN_STRIP_MASK) {
2922                 /* Enable or disable VLAN stripping */
2923                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2924                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2925                 else
2926                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2927         }
2928
2929         if (mask & ETH_VLAN_EXTEND_MASK) {
2930                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2931                         i40e_vsi_config_double_vlan(vsi, TRUE);
2932                         /* Set global registers with default ether type value */
2933                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2934                                            ETHER_TYPE_VLAN);
2935                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2936                                            ETHER_TYPE_VLAN);
2937                 }
2938                 else
2939                         i40e_vsi_config_double_vlan(vsi, FALSE);
2940         }
2941 }
2942
2943 static void
2944 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2945                           __rte_unused uint16_t queue,
2946                           __rte_unused int on)
2947 {
2948         PMD_INIT_FUNC_TRACE();
2949 }
2950
2951 static int
2952 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2953 {
2954         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2955         struct i40e_vsi *vsi = pf->main_vsi;
2956         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2957         struct i40e_vsi_vlan_pvid_info info;
2958
2959         memset(&info, 0, sizeof(info));
2960         info.on = on;
2961         if (info.on)
2962                 info.config.pvid = pvid;
2963         else {
2964                 info.config.reject.tagged =
2965                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2966                 info.config.reject.untagged =
2967                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2968         }
2969
2970         return i40e_vsi_vlan_pvid_set(vsi, &info);
2971 }
2972
2973 static int
2974 i40e_dev_led_on(struct rte_eth_dev *dev)
2975 {
2976         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2977         uint32_t mode = i40e_led_get(hw);
2978
2979         if (mode == 0)
2980                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2981
2982         return 0;
2983 }
2984
2985 static int
2986 i40e_dev_led_off(struct rte_eth_dev *dev)
2987 {
2988         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2989         uint32_t mode = i40e_led_get(hw);
2990
2991         if (mode != 0)
2992                 i40e_led_set(hw, 0, false);
2993
2994         return 0;
2995 }
2996
2997 static int
2998 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2999 {
3000         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3002
3003         fc_conf->pause_time = pf->fc_conf.pause_time;
3004
3005         /* read out from register, in case they are modified by other port */
3006         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3007                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3008         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3009                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3010
3011         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3012         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3013
3014          /* Return current mode according to actual setting*/
3015         switch (hw->fc.current_mode) {
3016         case I40E_FC_FULL:
3017                 fc_conf->mode = RTE_FC_FULL;
3018                 break;
3019         case I40E_FC_TX_PAUSE:
3020                 fc_conf->mode = RTE_FC_TX_PAUSE;
3021                 break;
3022         case I40E_FC_RX_PAUSE:
3023                 fc_conf->mode = RTE_FC_RX_PAUSE;
3024                 break;
3025         case I40E_FC_NONE:
3026         default:
3027                 fc_conf->mode = RTE_FC_NONE;
3028         };
3029
3030         return 0;
3031 }
3032
3033 static int
3034 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3035 {
3036         uint32_t mflcn_reg, fctrl_reg, reg;
3037         uint32_t max_high_water;
3038         uint8_t i, aq_failure;
3039         int err;
3040         struct i40e_hw *hw;
3041         struct i40e_pf *pf;
3042         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3043                 [RTE_FC_NONE] = I40E_FC_NONE,
3044                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3045                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3046                 [RTE_FC_FULL] = I40E_FC_FULL
3047         };
3048
3049         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3050
3051         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3052         if ((fc_conf->high_water > max_high_water) ||
3053                         (fc_conf->high_water < fc_conf->low_water)) {
3054                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3055                         "High_water must <= %d.", max_high_water);
3056                 return -EINVAL;
3057         }
3058
3059         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3061         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3062
3063         pf->fc_conf.pause_time = fc_conf->pause_time;
3064         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3065         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3066
3067         PMD_INIT_FUNC_TRACE();
3068
3069         /* All the link flow control related enable/disable register
3070          * configuration is handle by the F/W
3071          */
3072         err = i40e_set_fc(hw, &aq_failure, true);
3073         if (err < 0)
3074                 return -ENOSYS;
3075
3076         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3077                 /* Configure flow control refresh threshold,
3078                  * the value for stat_tx_pause_refresh_timer[8]
3079                  * is used for global pause operation.
3080                  */
3081
3082                 I40E_WRITE_REG(hw,
3083                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3084                                pf->fc_conf.pause_time);
3085
3086                 /* configure the timer value included in transmitted pause
3087                  * frame,
3088                  * the value for stat_tx_pause_quanta[8] is used for global
3089                  * pause operation
3090                  */
3091                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3092                                pf->fc_conf.pause_time);
3093
3094                 fctrl_reg = I40E_READ_REG(hw,
3095                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3096
3097                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3098                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3099                 else
3100                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3101
3102                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3103                                fctrl_reg);
3104         } else {
3105                 /* Configure pause time (2 TCs per register) */
3106                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3107                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3108                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3109
3110                 /* Configure flow control refresh threshold value */
3111                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3112                                pf->fc_conf.pause_time / 2);
3113
3114                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3115
3116                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3117                  *depending on configuration
3118                  */
3119                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3120                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3121                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3122                 } else {
3123                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3124                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3125                 }
3126
3127                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3128         }
3129
3130         if (!pf->support_multi_driver) {
3131                 /* config water marker both based on the packets and bytes */
3132                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3133                                 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3134                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3135                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3136                                 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3137                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3138                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3139                                  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3140                                  << I40E_KILOSHIFT);
3141                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3142                                   pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3143                                   << I40E_KILOSHIFT);
3144                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3145         } else {
3146                 PMD_DRV_LOG(ERR,
3147                             "Water marker configuration is not supported.");
3148         }
3149
3150         I40E_WRITE_FLUSH(hw);
3151
3152         return 0;
3153 }
3154
3155 static int
3156 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3157                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3158 {
3159         PMD_INIT_FUNC_TRACE();
3160
3161         return -ENOSYS;
3162 }
3163
3164 /* Add a MAC address, and update filters */
3165 static void
3166 i40e_macaddr_add(struct rte_eth_dev *dev,
3167                  struct ether_addr *mac_addr,
3168                  __rte_unused uint32_t index,
3169                  uint32_t pool)
3170 {
3171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3172         struct i40e_mac_filter_info mac_filter;
3173         struct i40e_vsi *vsi;
3174         int ret;
3175
3176         /* If VMDQ not enabled or configured, return */
3177         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3178                           !pf->nb_cfg_vmdq_vsi)) {
3179                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3180                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3181                         pool);
3182                 return;
3183         }
3184
3185         if (pool > pf->nb_cfg_vmdq_vsi) {
3186                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3187                                 pool, pf->nb_cfg_vmdq_vsi);
3188                 return;
3189         }
3190
3191         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3192         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3193                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3194         else
3195                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3196
3197         if (pool == 0)
3198                 vsi = pf->main_vsi;
3199         else
3200                 vsi = pf->vmdq[pool - 1].vsi;
3201
3202         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3203         if (ret != I40E_SUCCESS) {
3204                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3205                 return;
3206         }
3207 }
3208
3209 /* Remove a MAC address, and update filters */
3210 static void
3211 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3212 {
3213         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3214         struct i40e_vsi *vsi;
3215         struct rte_eth_dev_data *data = dev->data;
3216         struct ether_addr *macaddr;
3217         int ret;
3218         uint32_t i;
3219         uint64_t pool_sel;
3220
3221         macaddr = &(data->mac_addrs[index]);
3222
3223         pool_sel = dev->data->mac_pool_sel[index];
3224
3225         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3226                 if (pool_sel & (1ULL << i)) {
3227                         if (i == 0)
3228                                 vsi = pf->main_vsi;
3229                         else {
3230                                 /* No VMDQ pool enabled or configured */
3231                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3232                                         (i > pf->nb_cfg_vmdq_vsi)) {
3233                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3234                                                         "/configured");
3235                                         return;
3236                                 }
3237                                 vsi = pf->vmdq[i - 1].vsi;
3238                         }
3239                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3240
3241                         if (ret) {
3242                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3243                                 return;
3244                         }
3245                 }
3246         }
3247 }
3248
3249 /* Set perfect match or hash match of MAC and VLAN for a VF */
3250 static int
3251 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3252                  struct rte_eth_mac_filter *filter,
3253                  bool add)
3254 {
3255         struct i40e_hw *hw;
3256         struct i40e_mac_filter_info mac_filter;
3257         struct ether_addr old_mac;
3258         struct ether_addr *new_mac;
3259         struct i40e_pf_vf *vf = NULL;
3260         uint16_t vf_id;
3261         int ret;
3262
3263         if (pf == NULL) {
3264                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3265                 return -EINVAL;
3266         }
3267         hw = I40E_PF_TO_HW(pf);
3268
3269         if (filter == NULL) {
3270                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3271                 return -EINVAL;
3272         }
3273
3274         new_mac = &filter->mac_addr;
3275
3276         if (is_zero_ether_addr(new_mac)) {
3277                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3278                 return -EINVAL;
3279         }
3280
3281         vf_id = filter->dst_id;
3282
3283         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3284                 PMD_DRV_LOG(ERR, "Invalid argument.");
3285                 return -EINVAL;
3286         }
3287         vf = &pf->vfs[vf_id];
3288
3289         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3290                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3291                 return -EINVAL;
3292         }
3293
3294         if (add) {
3295                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3296                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3297                                 ETHER_ADDR_LEN);
3298                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3299                                  ETHER_ADDR_LEN);
3300
3301                 mac_filter.filter_type = filter->filter_type;
3302                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3303                 if (ret != I40E_SUCCESS) {
3304                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3305                         return -1;
3306                 }
3307                 ether_addr_copy(new_mac, &pf->dev_addr);
3308         } else {
3309                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3310                                 ETHER_ADDR_LEN);
3311                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3312                 if (ret != I40E_SUCCESS) {
3313                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3314                         return -1;
3315                 }
3316
3317                 /* Clear device address as it has been removed */
3318                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3319                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3320         }
3321
3322         return 0;
3323 }
3324
3325 /* MAC filter handle */
3326 static int
3327 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3328                 void *arg)
3329 {
3330         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3331         struct rte_eth_mac_filter *filter;
3332         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3333         int ret = I40E_NOT_SUPPORTED;
3334
3335         filter = (struct rte_eth_mac_filter *)(arg);
3336
3337         switch (filter_op) {
3338         case RTE_ETH_FILTER_NOP:
3339                 ret = I40E_SUCCESS;
3340                 break;
3341         case RTE_ETH_FILTER_ADD:
3342                 i40e_pf_disable_irq0(hw);
3343                 if (filter->is_vf)
3344                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3345                 i40e_pf_enable_irq0(hw);
3346                 break;
3347         case RTE_ETH_FILTER_DELETE:
3348                 i40e_pf_disable_irq0(hw);
3349                 if (filter->is_vf)
3350                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3351                 i40e_pf_enable_irq0(hw);
3352                 break;
3353         default:
3354                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3355                 ret = I40E_ERR_PARAM;
3356                 break;
3357         }
3358
3359         return ret;
3360 }
3361
3362 static int
3363 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3364 {
3365         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3366         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3367         int ret;
3368
3369         if (!lut)
3370                 return -EINVAL;
3371
3372         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3373                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3374                                           lut, lut_size);
3375                 if (ret) {
3376                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3377                         return ret;
3378                 }
3379         } else {
3380                 uint32_t *lut_dw = (uint32_t *)lut;
3381                 uint16_t i, lut_size_dw = lut_size / 4;
3382
3383                 for (i = 0; i < lut_size_dw; i++)
3384                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3385         }
3386
3387         return 0;
3388 }
3389
3390 static int
3391 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3392 {
3393         struct i40e_pf *pf;
3394         struct i40e_hw *hw;
3395         int ret;
3396
3397         if (!vsi || !lut)
3398                 return -EINVAL;
3399
3400         pf = I40E_VSI_TO_PF(vsi);
3401         hw = I40E_VSI_TO_HW(vsi);
3402
3403         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3404                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3405                                           lut, lut_size);
3406                 if (ret) {
3407                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3408                         return ret;
3409                 }
3410         } else {
3411                 uint32_t *lut_dw = (uint32_t *)lut;
3412                 uint16_t i, lut_size_dw = lut_size / 4;
3413
3414                 for (i = 0; i < lut_size_dw; i++)
3415                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3416                 I40E_WRITE_FLUSH(hw);
3417         }
3418
3419         return 0;
3420 }
3421
3422 static int
3423 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3424                          struct rte_eth_rss_reta_entry64 *reta_conf,
3425                          uint16_t reta_size)
3426 {
3427         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3428         uint16_t i, lut_size = pf->hash_lut_size;
3429         uint16_t idx, shift;
3430         uint8_t *lut;
3431         int ret;
3432
3433         if (reta_size != lut_size ||
3434                 reta_size > ETH_RSS_RETA_SIZE_512) {
3435                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3436                         "(%d) doesn't match the number hardware can supported "
3437                                         "(%d)\n", reta_size, lut_size);
3438                 return -EINVAL;
3439         }
3440
3441         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3442         if (!lut) {
3443                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3444                 return -ENOMEM;
3445         }
3446         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3447         if (ret)
3448                 goto out;
3449         for (i = 0; i < reta_size; i++) {
3450                 idx = i / RTE_RETA_GROUP_SIZE;
3451                 shift = i % RTE_RETA_GROUP_SIZE;
3452                 if (reta_conf[idx].mask & (1ULL << shift))
3453                         lut[i] = reta_conf[idx].reta[shift];
3454         }
3455         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3456
3457 out:
3458         rte_free(lut);
3459
3460         return ret;
3461 }
3462
3463 static int
3464 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3465                         struct rte_eth_rss_reta_entry64 *reta_conf,
3466                         uint16_t reta_size)
3467 {
3468         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3469         uint16_t i, lut_size = pf->hash_lut_size;
3470         uint16_t idx, shift;
3471         uint8_t *lut;
3472         int ret;
3473
3474         if (reta_size != lut_size ||
3475                 reta_size > ETH_RSS_RETA_SIZE_512) {
3476                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3477                         "(%d) doesn't match the number hardware can supported "
3478                                         "(%d)\n", reta_size, lut_size);
3479                 return -EINVAL;
3480         }
3481
3482         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3483         if (!lut) {
3484                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3485                 return -ENOMEM;
3486         }
3487
3488         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3489         if (ret)
3490                 goto out;
3491         for (i = 0; i < reta_size; i++) {
3492                 idx = i / RTE_RETA_GROUP_SIZE;
3493                 shift = i % RTE_RETA_GROUP_SIZE;
3494                 if (reta_conf[idx].mask & (1ULL << shift))
3495                         reta_conf[idx].reta[shift] = lut[i];
3496         }
3497
3498 out:
3499         rte_free(lut);
3500
3501         return ret;
3502 }
3503
3504 /**
3505  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3506  * @hw:   pointer to the HW structure
3507  * @mem:  pointer to mem struct to fill out
3508  * @size: size of memory requested
3509  * @alignment: what to align the allocation to
3510  **/
3511 enum i40e_status_code
3512 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3513                         struct i40e_dma_mem *mem,
3514                         u64 size,
3515                         u32 alignment)
3516 {
3517         const struct rte_memzone *mz = NULL;
3518         char z_name[RTE_MEMZONE_NAMESIZE];
3519
3520         if (!mem)
3521                 return I40E_ERR_PARAM;
3522
3523         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3524         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3525                                          alignment, RTE_PGSIZE_2M);
3526         if (!mz)
3527                 return I40E_ERR_NO_MEMORY;
3528
3529         mem->size = size;
3530         mem->va = mz->addr;
3531         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3532         mem->zone = (const void *)mz;
3533         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3534                     "%"PRIu64, mz->name, mem->pa);
3535
3536         return I40E_SUCCESS;
3537 }
3538
3539 /**
3540  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3541  * @hw:   pointer to the HW structure
3542  * @mem:  ptr to mem struct to free
3543  **/
3544 enum i40e_status_code
3545 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3546                     struct i40e_dma_mem *mem)
3547 {
3548         if (!mem)
3549                 return I40E_ERR_PARAM;
3550
3551         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3552                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3553                     mem->pa);
3554         rte_memzone_free((const struct rte_memzone *)mem->zone);
3555         mem->zone = NULL;
3556         mem->va = NULL;
3557         mem->pa = (u64)0;
3558
3559         return I40E_SUCCESS;
3560 }
3561
3562 /**
3563  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3564  * @hw:   pointer to the HW structure
3565  * @mem:  pointer to mem struct to fill out
3566  * @size: size of memory requested
3567  **/
3568 enum i40e_status_code
3569 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3570                          struct i40e_virt_mem *mem,
3571                          u32 size)
3572 {
3573         if (!mem)
3574                 return I40E_ERR_PARAM;
3575
3576         mem->size = size;
3577         mem->va = rte_zmalloc("i40e", size, 0);
3578
3579         if (mem->va)
3580                 return I40E_SUCCESS;
3581         else
3582                 return I40E_ERR_NO_MEMORY;
3583 }
3584
3585 /**
3586  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3587  * @hw:   pointer to the HW structure
3588  * @mem:  pointer to mem struct to free
3589  **/
3590 enum i40e_status_code
3591 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3592                      struct i40e_virt_mem *mem)
3593 {
3594         if (!mem)
3595                 return I40E_ERR_PARAM;
3596
3597         rte_free(mem->va);
3598         mem->va = NULL;
3599
3600         return I40E_SUCCESS;
3601 }
3602
3603 void
3604 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3605 {
3606         rte_spinlock_init(&sp->spinlock);
3607 }
3608
3609 void
3610 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3611 {
3612         rte_spinlock_lock(&sp->spinlock);
3613 }
3614
3615 void
3616 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3617 {
3618         rte_spinlock_unlock(&sp->spinlock);
3619 }
3620
3621 void
3622 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3623 {
3624         return;
3625 }
3626
3627 /**
3628  * Get the hardware capabilities, which will be parsed
3629  * and saved into struct i40e_hw.
3630  */
3631 static int
3632 i40e_get_cap(struct i40e_hw *hw)
3633 {
3634         struct i40e_aqc_list_capabilities_element_resp *buf;
3635         uint16_t len, size = 0;
3636         int ret;
3637
3638         /* Calculate a huge enough buff for saving response data temporarily */
3639         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3640                                                 I40E_MAX_CAP_ELE_NUM;
3641         buf = rte_zmalloc("i40e", len, 0);
3642         if (!buf) {
3643                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3644                 return I40E_ERR_NO_MEMORY;
3645         }
3646
3647         /* Get, parse the capabilities and save it to hw */
3648         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3649                         i40e_aqc_opc_list_func_capabilities, NULL);
3650         if (ret != I40E_SUCCESS)
3651                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3652
3653         /* Free the temporary buffer after being used */
3654         rte_free(buf);
3655
3656         return ret;
3657 }
3658
3659 static int
3660 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3661 {
3662         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3663         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3664         uint16_t qp_count = 0, vsi_count = 0;
3665
3666         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3667                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3668                 return -EINVAL;
3669         }
3670         /* Add the parameter init for LFC */
3671         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3672         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3673         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3674
3675         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3676         pf->max_num_vsi = hw->func_caps.num_vsis;
3677         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3678         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3679         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3680
3681         /* FDir queue/VSI allocation */
3682         pf->fdir_qp_offset = 0;
3683         if (hw->func_caps.fd) {
3684                 pf->flags |= I40E_FLAG_FDIR;
3685                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3686         } else {
3687                 pf->fdir_nb_qps = 0;
3688         }
3689         qp_count += pf->fdir_nb_qps;
3690         vsi_count += 1;
3691
3692         /* LAN queue/VSI allocation */
3693         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3694         if (!hw->func_caps.rss) {
3695                 pf->lan_nb_qps = 1;
3696         } else {
3697                 pf->flags |= I40E_FLAG_RSS;
3698                 if (hw->mac.type == I40E_MAC_X722)
3699                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3700                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3701         }
3702         qp_count += pf->lan_nb_qps;
3703         vsi_count += 1;
3704
3705         /* VF queue/VSI allocation */
3706         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3707         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3708                 pf->flags |= I40E_FLAG_SRIOV;
3709                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3710                 pf->vf_num = dev->pci_dev->max_vfs;
3711                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3712                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3713                             pf->vf_nb_qps * pf->vf_num);
3714         } else {
3715                 pf->vf_nb_qps = 0;
3716                 pf->vf_num = 0;
3717         }
3718         qp_count += pf->vf_nb_qps * pf->vf_num;
3719         vsi_count += pf->vf_num;
3720
3721         /* VMDq queue/VSI allocation */
3722         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3723         pf->vmdq_nb_qps = 0;
3724         pf->max_nb_vmdq_vsi = 0;
3725         if (hw->func_caps.vmdq) {
3726                 if (qp_count < hw->func_caps.num_tx_qp &&
3727                         vsi_count < hw->func_caps.num_vsis) {
3728                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3729                                 qp_count) / pf->vmdq_nb_qp_max;
3730
3731                         /* Limit the maximum number of VMDq vsi to the maximum
3732                          * ethdev can support
3733                          */
3734                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3735                                 hw->func_caps.num_vsis - vsi_count);
3736                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3737                                 ETH_64_POOLS);
3738                         if (pf->max_nb_vmdq_vsi) {
3739                                 pf->flags |= I40E_FLAG_VMDQ;
3740                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3741                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3742                                             "per VMDQ VSI, in total %u queues",
3743                                             pf->max_nb_vmdq_vsi,
3744                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3745                                             pf->max_nb_vmdq_vsi);
3746                         } else {
3747                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3748                                             "VMDq");
3749                         }
3750                 } else {
3751                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3752                 }
3753         }
3754         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3755         vsi_count += pf->max_nb_vmdq_vsi;
3756
3757         if (hw->func_caps.dcb)
3758                 pf->flags |= I40E_FLAG_DCB;
3759
3760         if (qp_count > hw->func_caps.num_tx_qp) {
3761                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3762                             "the hardware maximum %u", qp_count,
3763                             hw->func_caps.num_tx_qp);
3764                 return -EINVAL;
3765         }
3766         if (vsi_count > hw->func_caps.num_vsis) {
3767                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3768                             "the hardware maximum %u", vsi_count,
3769                             hw->func_caps.num_vsis);
3770                 return -EINVAL;
3771         }
3772
3773         return 0;
3774 }
3775
3776 static int
3777 i40e_pf_get_switch_config(struct i40e_pf *pf)
3778 {
3779         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3780         struct i40e_aqc_get_switch_config_resp *switch_config;
3781         struct i40e_aqc_switch_config_element_resp *element;
3782         uint16_t start_seid = 0, num_reported;
3783         int ret;
3784
3785         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3786                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3787         if (!switch_config) {
3788                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3789                 return -ENOMEM;
3790         }
3791
3792         /* Get the switch configurations */
3793         ret = i40e_aq_get_switch_config(hw, switch_config,
3794                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3795         if (ret != I40E_SUCCESS) {
3796                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3797                 goto fail;
3798         }
3799         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3800         if (num_reported != 1) { /* The number should be 1 */
3801                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3802                 goto fail;
3803         }
3804
3805         /* Parse the switch configuration elements */
3806         element = &(switch_config->element[0]);
3807         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3808                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3809                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3810         } else
3811                 PMD_DRV_LOG(INFO, "Unknown element type");
3812
3813 fail:
3814         rte_free(switch_config);
3815
3816         return ret;
3817 }
3818
3819 static int
3820 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3821                         uint32_t num)
3822 {
3823         struct pool_entry *entry;
3824
3825         if (pool == NULL || num == 0)
3826                 return -EINVAL;
3827
3828         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3829         if (entry == NULL) {
3830                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3831                 return -ENOMEM;
3832         }
3833
3834         /* queue heap initialize */
3835         pool->num_free = num;
3836         pool->num_alloc = 0;
3837         pool->base = base;
3838         LIST_INIT(&pool->alloc_list);
3839         LIST_INIT(&pool->free_list);
3840
3841         /* Initialize element  */
3842         entry->base = 0;
3843         entry->len = num;
3844
3845         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3846         return 0;
3847 }
3848
3849 static void
3850 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3851 {
3852         struct pool_entry *entry, *next_entry;
3853
3854         if (pool == NULL)
3855                 return;
3856
3857         for (entry = LIST_FIRST(&pool->alloc_list);
3858                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3859                         entry = next_entry) {
3860                 LIST_REMOVE(entry, next);
3861                 rte_free(entry);
3862         }
3863
3864         for (entry = LIST_FIRST(&pool->free_list);
3865                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3866                         entry = next_entry) {
3867                 LIST_REMOVE(entry, next);
3868                 rte_free(entry);
3869         }
3870
3871         pool->num_free = 0;
3872         pool->num_alloc = 0;
3873         pool->base = 0;
3874         LIST_INIT(&pool->alloc_list);
3875         LIST_INIT(&pool->free_list);
3876 }
3877
3878 static int
3879 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3880                        uint32_t base)
3881 {
3882         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3883         uint32_t pool_offset;
3884         int insert;
3885
3886         if (pool == NULL) {
3887                 PMD_DRV_LOG(ERR, "Invalid parameter");
3888                 return -EINVAL;
3889         }
3890
3891         pool_offset = base - pool->base;
3892         /* Lookup in alloc list */
3893         LIST_FOREACH(entry, &pool->alloc_list, next) {
3894                 if (entry->base == pool_offset) {
3895                         valid_entry = entry;
3896                         LIST_REMOVE(entry, next);
3897                         break;
3898                 }
3899         }
3900
3901         /* Not find, return */
3902         if (valid_entry == NULL) {
3903                 PMD_DRV_LOG(ERR, "Failed to find entry");
3904                 return -EINVAL;
3905         }
3906
3907         /**
3908          * Found it, move it to free list  and try to merge.
3909          * In order to make merge easier, always sort it by qbase.
3910          * Find adjacent prev and last entries.
3911          */
3912         prev = next = NULL;
3913         LIST_FOREACH(entry, &pool->free_list, next) {
3914                 if (entry->base > valid_entry->base) {
3915                         next = entry;
3916                         break;
3917                 }
3918                 prev = entry;
3919         }
3920
3921         insert = 0;
3922         /* Try to merge with next one*/
3923         if (next != NULL) {
3924                 /* Merge with next one */
3925                 if (valid_entry->base + valid_entry->len == next->base) {
3926                         next->base = valid_entry->base;
3927                         next->len += valid_entry->len;
3928                         rte_free(valid_entry);
3929                         valid_entry = next;
3930                         insert = 1;
3931                 }
3932         }
3933
3934         if (prev != NULL) {
3935                 /* Merge with previous one */
3936                 if (prev->base + prev->len == valid_entry->base) {
3937                         prev->len += valid_entry->len;
3938                         /* If it merge with next one, remove next node */
3939                         if (insert == 1) {
3940                                 LIST_REMOVE(valid_entry, next);
3941                                 rte_free(valid_entry);
3942                         } else {
3943                                 rte_free(valid_entry);
3944                                 insert = 1;
3945                         }
3946                 }
3947         }
3948
3949         /* Not find any entry to merge, insert */
3950         if (insert == 0) {
3951                 if (prev != NULL)
3952                         LIST_INSERT_AFTER(prev, valid_entry, next);
3953                 else if (next != NULL)
3954                         LIST_INSERT_BEFORE(next, valid_entry, next);
3955                 else /* It's empty list, insert to head */
3956                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3957         }
3958
3959         pool->num_free += valid_entry->len;
3960         pool->num_alloc -= valid_entry->len;
3961
3962         return 0;
3963 }
3964
3965 static int
3966 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3967                        uint16_t num)
3968 {
3969         struct pool_entry *entry, *valid_entry;
3970
3971         if (pool == NULL || num == 0) {
3972                 PMD_DRV_LOG(ERR, "Invalid parameter");
3973                 return -EINVAL;
3974         }
3975
3976         if (pool->num_free < num) {
3977                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3978                             num, pool->num_free);
3979                 return -ENOMEM;
3980         }
3981
3982         valid_entry = NULL;
3983         /* Lookup  in free list and find most fit one */
3984         LIST_FOREACH(entry, &pool->free_list, next) {
3985                 if (entry->len >= num) {
3986                         /* Find best one */
3987                         if (entry->len == num) {
3988                                 valid_entry = entry;
3989                                 break;
3990                         }
3991                         if (valid_entry == NULL || valid_entry->len > entry->len)
3992                                 valid_entry = entry;
3993                 }
3994         }
3995
3996         /* Not find one to satisfy the request, return */
3997         if (valid_entry == NULL) {
3998                 PMD_DRV_LOG(ERR, "No valid entry found");
3999                 return -ENOMEM;
4000         }
4001         /**
4002          * The entry have equal queue number as requested,
4003          * remove it from alloc_list.
4004          */
4005         if (valid_entry->len == num) {
4006                 LIST_REMOVE(valid_entry, next);
4007         } else {
4008                 /**
4009                  * The entry have more numbers than requested,
4010                  * create a new entry for alloc_list and minus its
4011                  * queue base and number in free_list.
4012                  */
4013                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4014                 if (entry == NULL) {
4015                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4016                                     "resource pool");
4017                         return -ENOMEM;
4018                 }
4019                 entry->base = valid_entry->base;
4020                 entry->len = num;
4021                 valid_entry->base += num;
4022                 valid_entry->len -= num;
4023                 valid_entry = entry;
4024         }
4025
4026         /* Insert it into alloc list, not sorted */
4027         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4028
4029         pool->num_free -= valid_entry->len;
4030         pool->num_alloc += valid_entry->len;
4031
4032         return valid_entry->base + pool->base;
4033 }
4034
4035 /**
4036  * bitmap_is_subset - Check whether src2 is subset of src1
4037  **/
4038 static inline int
4039 bitmap_is_subset(uint8_t src1, uint8_t src2)
4040 {
4041         return !((src1 ^ src2) & src2);
4042 }
4043
4044 static enum i40e_status_code
4045 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4046 {
4047         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4048
4049         /* If DCB is not supported, only default TC is supported */
4050         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4051                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4052                 return I40E_NOT_SUPPORTED;
4053         }
4054
4055         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4056                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4057                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4058                             enabled_tcmap);
4059                 return I40E_NOT_SUPPORTED;
4060         }
4061         return I40E_SUCCESS;
4062 }
4063
4064 int
4065 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4066                                 struct i40e_vsi_vlan_pvid_info *info)
4067 {
4068         struct i40e_hw *hw;
4069         struct i40e_vsi_context ctxt;
4070         uint8_t vlan_flags = 0;
4071         int ret;
4072
4073         if (vsi == NULL || info == NULL) {
4074                 PMD_DRV_LOG(ERR, "invalid parameters");
4075                 return I40E_ERR_PARAM;
4076         }
4077
4078         if (info->on) {
4079                 vsi->info.pvid = info->config.pvid;
4080                 /**
4081                  * If insert pvid is enabled, only tagged pkts are
4082                  * allowed to be sent out.
4083                  */
4084                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4085                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4086         } else {
4087                 vsi->info.pvid = 0;
4088                 if (info->config.reject.tagged == 0)
4089                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4090
4091                 if (info->config.reject.untagged == 0)
4092                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4093         }
4094         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4095                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4096         vsi->info.port_vlan_flags |= vlan_flags;
4097         vsi->info.valid_sections =
4098                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4099         memset(&ctxt, 0, sizeof(ctxt));
4100         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4101         ctxt.seid = vsi->seid;
4102
4103         hw = I40E_VSI_TO_HW(vsi);
4104         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4105         if (ret != I40E_SUCCESS)
4106                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4107
4108         return ret;
4109 }
4110
4111 static int
4112 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4113 {
4114         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4115         int i, ret;
4116         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4117
4118         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4119         if (ret != I40E_SUCCESS)
4120                 return ret;
4121
4122         if (!vsi->seid) {
4123                 PMD_DRV_LOG(ERR, "seid not valid");
4124                 return -EINVAL;
4125         }
4126
4127         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4128         tc_bw_data.tc_valid_bits = enabled_tcmap;
4129         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4130                 tc_bw_data.tc_bw_credits[i] =
4131                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4132
4133         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4134         if (ret != I40E_SUCCESS) {
4135                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4136                 return ret;
4137         }
4138
4139         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4140                                         sizeof(vsi->info.qs_handle));
4141         return I40E_SUCCESS;
4142 }
4143
4144 static enum i40e_status_code
4145 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4146                                  struct i40e_aqc_vsi_properties_data *info,
4147                                  uint8_t enabled_tcmap)
4148 {
4149         enum i40e_status_code ret;
4150         int i, total_tc = 0;
4151         uint16_t qpnum_per_tc, bsf, qp_idx;
4152
4153         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4154         if (ret != I40E_SUCCESS)
4155                 return ret;
4156
4157         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4158                 if (enabled_tcmap & (1 << i))
4159                         total_tc++;
4160         if (total_tc == 0)
4161                 total_tc = 1;
4162         vsi->enabled_tc = enabled_tcmap;
4163
4164         /* Number of queues per enabled TC */
4165         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4166         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4167         bsf = rte_bsf32(qpnum_per_tc);
4168
4169         /* Adjust the queue number to actual queues that can be applied */
4170         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4171                 vsi->nb_qps = qpnum_per_tc * total_tc;
4172
4173         /**
4174          * Configure TC and queue mapping parameters, for enabled TC,
4175          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4176          * default queue will serve it.
4177          */
4178         qp_idx = 0;
4179         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4180                 if (vsi->enabled_tc & (1 << i)) {
4181                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4182                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4183                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4184                         qp_idx += qpnum_per_tc;
4185                 } else
4186                         info->tc_mapping[i] = 0;
4187         }
4188
4189         /* Associate queue number with VSI */
4190         if (vsi->type == I40E_VSI_SRIOV) {
4191                 info->mapping_flags |=
4192                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4193                 for (i = 0; i < vsi->nb_qps; i++)
4194                         info->queue_mapping[i] =
4195                                 rte_cpu_to_le_16(vsi->base_queue + i);
4196         } else {
4197                 info->mapping_flags |=
4198                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4199                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4200         }
4201         info->valid_sections |=
4202                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4203
4204         return I40E_SUCCESS;
4205 }
4206
4207 static int
4208 i40e_veb_release(struct i40e_veb *veb)
4209 {
4210         struct i40e_vsi *vsi;
4211         struct i40e_hw *hw;
4212
4213         if (veb == NULL)
4214                 return -EINVAL;
4215
4216         if (!TAILQ_EMPTY(&veb->head)) {
4217                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4218                 return -EACCES;
4219         }
4220         /* associate_vsi field is NULL for floating VEB */
4221         if (veb->associate_vsi != NULL) {
4222                 vsi = veb->associate_vsi;
4223                 hw = I40E_VSI_TO_HW(vsi);
4224
4225                 vsi->uplink_seid = veb->uplink_seid;
4226                 vsi->veb = NULL;
4227         } else {
4228                 veb->associate_pf->main_vsi->floating_veb = NULL;
4229                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4230         }
4231
4232         i40e_aq_delete_element(hw, veb->seid, NULL);
4233         rte_free(veb);
4234         return I40E_SUCCESS;
4235 }
4236
4237 /* Setup a veb */
4238 static struct i40e_veb *
4239 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4240 {
4241         struct i40e_veb *veb;
4242         int ret;
4243         struct i40e_hw *hw;
4244
4245         if (pf == NULL) {
4246                 PMD_DRV_LOG(ERR,
4247                             "veb setup failed, associated PF shouldn't null");
4248                 return NULL;
4249         }
4250         hw = I40E_PF_TO_HW(pf);
4251
4252         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4253         if (!veb) {
4254                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4255                 goto fail;
4256         }
4257
4258         veb->associate_vsi = vsi;
4259         veb->associate_pf = pf;
4260         TAILQ_INIT(&veb->head);
4261         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4262
4263         /* create floating veb if vsi is NULL */
4264         if (vsi != NULL) {
4265                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4266                                       I40E_DEFAULT_TCMAP, false,
4267                                       &veb->seid, false, NULL);
4268         } else {
4269                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4270                                       true, &veb->seid, false, NULL);
4271         }
4272
4273         if (ret != I40E_SUCCESS) {
4274                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4275                             hw->aq.asq_last_status);
4276                 goto fail;
4277         }
4278         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4279
4280         /* get statistics index */
4281         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4282                                 &veb->stats_idx, NULL, NULL, NULL);
4283         if (ret != I40E_SUCCESS) {
4284                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4285                             hw->aq.asq_last_status);
4286                 goto fail;
4287         }
4288         /* Get VEB bandwidth, to be implemented */
4289         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4290         if (vsi)
4291                 vsi->uplink_seid = veb->seid;
4292
4293         return veb;
4294 fail:
4295         rte_free(veb);
4296         return NULL;
4297 }
4298
4299 int
4300 i40e_vsi_release(struct i40e_vsi *vsi)
4301 {
4302         struct i40e_pf *pf;
4303         struct i40e_hw *hw;
4304         struct i40e_vsi_list *vsi_list;
4305         void *temp;
4306         int ret;
4307         struct i40e_mac_filter *f;
4308         uint16_t user_param;
4309
4310         if (!vsi)
4311                 return I40E_SUCCESS;
4312
4313         if (!vsi->adapter)
4314                 return -EFAULT;
4315
4316         user_param = vsi->user_param;
4317
4318         pf = I40E_VSI_TO_PF(vsi);
4319         hw = I40E_VSI_TO_HW(vsi);
4320
4321         /* VSI has child to attach, release child first */
4322         if (vsi->veb) {
4323                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4324                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4325                                 return -1;
4326                 }
4327                 i40e_veb_release(vsi->veb);
4328         }
4329
4330         if (vsi->floating_veb) {
4331                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4332                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4333                                 return -1;
4334                 }
4335         }
4336
4337         /* Remove all macvlan filters of the VSI */
4338         i40e_vsi_remove_all_macvlan_filter(vsi);
4339         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4340                 rte_free(f);
4341
4342         if (vsi->type != I40E_VSI_MAIN &&
4343             ((vsi->type != I40E_VSI_SRIOV) ||
4344             !pf->floating_veb_list[user_param])) {
4345                 /* Remove vsi from parent's sibling list */
4346                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4347                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4348                         return I40E_ERR_PARAM;
4349                 }
4350                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4351                                 &vsi->sib_vsi_list, list);
4352
4353                 /* Remove all switch element of the VSI */
4354                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4355                 if (ret != I40E_SUCCESS)
4356                         PMD_DRV_LOG(ERR, "Failed to delete element");
4357         }
4358
4359         if ((vsi->type == I40E_VSI_SRIOV) &&
4360             pf->floating_veb_list[user_param]) {
4361                 /* Remove vsi from parent's sibling list */
4362                 if (vsi->parent_vsi == NULL ||
4363                     vsi->parent_vsi->floating_veb == NULL) {
4364                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4365                         return I40E_ERR_PARAM;
4366                 }
4367                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4368                              &vsi->sib_vsi_list, list);
4369
4370                 /* Remove all switch element of the VSI */
4371                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4372                 if (ret != I40E_SUCCESS)
4373                         PMD_DRV_LOG(ERR, "Failed to delete element");
4374         }
4375
4376         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4377
4378         if (vsi->type != I40E_VSI_SRIOV)
4379                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4380         rte_free(vsi);
4381
4382         return I40E_SUCCESS;
4383 }
4384
4385 static int
4386 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4387 {
4388         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4389         struct i40e_aqc_remove_macvlan_element_data def_filter;
4390         struct i40e_mac_filter_info filter;
4391         int ret;
4392
4393         if (vsi->type != I40E_VSI_MAIN)
4394                 return I40E_ERR_CONFIG;
4395         memset(&def_filter, 0, sizeof(def_filter));
4396         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4397                                         ETH_ADDR_LEN);
4398         def_filter.vlan_tag = 0;
4399         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4400                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4401         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4402         if (ret != I40E_SUCCESS) {
4403                 struct i40e_mac_filter *f;
4404                 struct ether_addr *mac;
4405
4406                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4407                             "macvlan filter");
4408                 /* It needs to add the permanent mac into mac list */
4409                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4410                 if (f == NULL) {
4411                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4412                         return I40E_ERR_NO_MEMORY;
4413                 }
4414                 mac = &f->mac_info.mac_addr;
4415                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4416                                 ETH_ADDR_LEN);
4417                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4418                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4419                 vsi->mac_num++;
4420
4421                 return ret;
4422         }
4423         (void)rte_memcpy(&filter.mac_addr,
4424                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4425         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4426         return i40e_vsi_add_mac(vsi, &filter);
4427 }
4428
4429 /*
4430  * i40e_vsi_get_bw_config - Query VSI BW Information
4431  * @vsi: the VSI to be queried
4432  *
4433  * Returns 0 on success, negative value on failure
4434  */
4435 static enum i40e_status_code
4436 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4437 {
4438         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4439         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4440         struct i40e_hw *hw = &vsi->adapter->hw;
4441         i40e_status ret;
4442         int i;
4443         uint32_t bw_max;
4444
4445         memset(&bw_config, 0, sizeof(bw_config));
4446         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4447         if (ret != I40E_SUCCESS) {
4448                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4449                             hw->aq.asq_last_status);
4450                 return ret;
4451         }
4452
4453         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4454         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4455                                         &ets_sla_config, NULL);
4456         if (ret != I40E_SUCCESS) {
4457                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4458                             "configuration %u", hw->aq.asq_last_status);
4459                 return ret;
4460         }
4461
4462         /* store and print out BW info */
4463         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4464         vsi->bw_info.bw_max = bw_config.max_bw;
4465         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4466         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4467         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4468                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4469                      I40E_16_BIT_WIDTH);
4470         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4471                 vsi->bw_info.bw_ets_share_credits[i] =
4472                                 ets_sla_config.share_credits[i];
4473                 vsi->bw_info.bw_ets_credits[i] =
4474                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4475                 /* 4 bits per TC, 4th bit is reserved */
4476                 vsi->bw_info.bw_ets_max[i] =
4477                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4478                                   RTE_LEN2MASK(3, uint8_t));
4479                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4480                             vsi->bw_info.bw_ets_share_credits[i]);
4481                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4482                             vsi->bw_info.bw_ets_credits[i]);
4483                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4484                             vsi->bw_info.bw_ets_max[i]);
4485         }
4486
4487         return I40E_SUCCESS;
4488 }
4489
4490 /* i40e_enable_pf_lb
4491  * @pf: pointer to the pf structure
4492  *
4493  * allow loopback on pf
4494  */
4495 static inline void
4496 i40e_enable_pf_lb(struct i40e_pf *pf)
4497 {
4498         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4499         struct i40e_vsi_context ctxt;
4500         int ret;
4501
4502         /* Use the FW API if FW >= v5.0 */
4503         if (hw->aq.fw_maj_ver < 5) {
4504                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4505                 return;
4506         }
4507
4508         memset(&ctxt, 0, sizeof(ctxt));
4509         ctxt.seid = pf->main_vsi_seid;
4510         ctxt.pf_num = hw->pf_id;
4511         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4512         if (ret) {
4513                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4514                             ret, hw->aq.asq_last_status);
4515                 return;
4516         }
4517         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4518         ctxt.info.valid_sections =
4519                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4520         ctxt.info.switch_id |=
4521                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4522
4523         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4524         if (ret)
4525                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4526                             hw->aq.asq_last_status);
4527 }
4528
4529 /* Setup a VSI */
4530 struct i40e_vsi *
4531 i40e_vsi_setup(struct i40e_pf *pf,
4532                enum i40e_vsi_type type,
4533                struct i40e_vsi *uplink_vsi,
4534                uint16_t user_param)
4535 {
4536         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4537         struct i40e_vsi *vsi;
4538         struct i40e_mac_filter_info filter;
4539         int ret;
4540         struct i40e_vsi_context ctxt;
4541         struct ether_addr broadcast =
4542                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4543
4544         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4545             uplink_vsi == NULL) {
4546                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4547                             "VSI link shouldn't be NULL");
4548                 return NULL;
4549         }
4550
4551         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4552                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4553                             "uplink VSI should be NULL");
4554                 return NULL;
4555         }
4556
4557         /* two situations
4558          * 1.type is not MAIN and uplink vsi is not NULL
4559          * If uplink vsi didn't setup VEB, create one first under veb field
4560          * 2.type is SRIOV and the uplink is NULL
4561          * If floating VEB is NULL, create one veb under floating veb field
4562          */
4563
4564         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4565             uplink_vsi->veb == NULL) {
4566                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4567
4568                 if (uplink_vsi->veb == NULL) {
4569                         PMD_DRV_LOG(ERR, "VEB setup failed");
4570                         return NULL;
4571                 }
4572                 /* set ALLOWLOOPBACk on pf, when veb is created */
4573                 i40e_enable_pf_lb(pf);
4574         }
4575
4576         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4577             pf->main_vsi->floating_veb == NULL) {
4578                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4579
4580                 if (pf->main_vsi->floating_veb == NULL) {
4581                         PMD_DRV_LOG(ERR, "VEB setup failed");
4582                         return NULL;
4583                 }
4584         }
4585
4586         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4587         if (!vsi) {
4588                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4589                 return NULL;
4590         }
4591         TAILQ_INIT(&vsi->mac_list);
4592         vsi->type = type;
4593         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4594         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4595         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4596         vsi->user_param = user_param;
4597         /* Allocate queues */
4598         switch (vsi->type) {
4599         case I40E_VSI_MAIN  :
4600                 vsi->nb_qps = pf->lan_nb_qps;
4601                 break;
4602         case I40E_VSI_SRIOV :
4603                 vsi->nb_qps = pf->vf_nb_qps;
4604                 break;
4605         case I40E_VSI_VMDQ2:
4606                 vsi->nb_qps = pf->vmdq_nb_qps;
4607                 break;
4608         case I40E_VSI_FDIR:
4609                 vsi->nb_qps = pf->fdir_nb_qps;
4610                 break;
4611         default:
4612                 goto fail_mem;
4613         }
4614         /*
4615          * The filter status descriptor is reported in rx queue 0,
4616          * while the tx queue for fdir filter programming has no
4617          * such constraints, can be non-zero queues.
4618          * To simplify it, choose FDIR vsi use queue 0 pair.
4619          * To make sure it will use queue 0 pair, queue allocation
4620          * need be done before this function is called
4621          */
4622         if (type != I40E_VSI_FDIR) {
4623                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4624                         if (ret < 0) {
4625                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4626                                                 vsi->seid, ret);
4627                                 goto fail_mem;
4628                         }
4629                         vsi->base_queue = ret;
4630         } else
4631                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4632
4633         /* VF has MSIX interrupt in VF range, don't allocate here */
4634         if (type == I40E_VSI_MAIN) {
4635                 if (pf->support_multi_driver) {
4636                         /* If support multi-driver, need to use INT0 instead of
4637                          * allocating from msix pool. The Msix pool is init from
4638                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
4639                          * to 1 without calling i40e_res_pool_alloc.
4640                          */
4641                         vsi->msix_intr = 0;
4642                         vsi->nb_msix = 1;
4643                 } else {
4644                         ret = i40e_res_pool_alloc(&pf->msix_pool,
4645                                                   RTE_MIN(vsi->nb_qps,
4646                                                      RTE_MAX_RXTX_INTR_VEC_ID));
4647                         if (ret < 0) {
4648                                 PMD_DRV_LOG(ERR,
4649                                             "VSI MAIN %d get heap failed %d",
4650                                             vsi->seid, ret);
4651                                 goto fail_queue_alloc;
4652                         }
4653                         vsi->msix_intr = ret;
4654                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
4655                                                RTE_MAX_RXTX_INTR_VEC_ID);
4656                 }
4657         } else if (type != I40E_VSI_SRIOV) {
4658                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4659                 if (ret < 0) {
4660                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4661                         goto fail_queue_alloc;
4662                 }
4663                 vsi->msix_intr = ret;
4664                 vsi->nb_msix = 1;
4665         } else {
4666                 vsi->msix_intr = 0;
4667                 vsi->nb_msix = 0;
4668         }
4669
4670         /* Add VSI */
4671         if (type == I40E_VSI_MAIN) {
4672                 /* For main VSI, no need to add since it's default one */
4673                 vsi->uplink_seid = pf->mac_seid;
4674                 vsi->seid = pf->main_vsi_seid;
4675                 /* Bind queues with specific MSIX interrupt */
4676                 /**
4677                  * Needs 2 interrupt at least, one for misc cause which will
4678                  * enabled from OS side, Another for queues binding the
4679                  * interrupt from device side only.
4680                  */
4681
4682                 /* Get default VSI parameters from hardware */
4683                 memset(&ctxt, 0, sizeof(ctxt));
4684                 ctxt.seid = vsi->seid;
4685                 ctxt.pf_num = hw->pf_id;
4686                 ctxt.uplink_seid = vsi->uplink_seid;
4687                 ctxt.vf_num = 0;
4688                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4689                 if (ret != I40E_SUCCESS) {
4690                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4691                         goto fail_msix_alloc;
4692                 }
4693                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4694                         sizeof(struct i40e_aqc_vsi_properties_data));
4695                 vsi->vsi_id = ctxt.vsi_number;
4696                 vsi->info.valid_sections = 0;
4697
4698                 /* Configure tc, enabled TC0 only */
4699                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4700                         I40E_SUCCESS) {
4701                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4702                         goto fail_msix_alloc;
4703                 }
4704
4705                 /* TC, queue mapping */
4706                 memset(&ctxt, 0, sizeof(ctxt));
4707                 vsi->info.valid_sections |=
4708                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4709                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4710                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4711                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4712                         sizeof(struct i40e_aqc_vsi_properties_data));
4713                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4714                                                 I40E_DEFAULT_TCMAP);
4715                 if (ret != I40E_SUCCESS) {
4716                         PMD_DRV_LOG(ERR, "Failed to configure "
4717                                     "TC queue mapping");
4718                         goto fail_msix_alloc;
4719                 }
4720                 ctxt.seid = vsi->seid;
4721                 ctxt.pf_num = hw->pf_id;
4722                 ctxt.uplink_seid = vsi->uplink_seid;
4723                 ctxt.vf_num = 0;
4724
4725                 /* Update VSI parameters */
4726                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4727                 if (ret != I40E_SUCCESS) {
4728                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4729                         goto fail_msix_alloc;
4730                 }
4731
4732                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4733                                                 sizeof(vsi->info.tc_mapping));
4734                 (void)rte_memcpy(&vsi->info.queue_mapping,
4735                                 &ctxt.info.queue_mapping,
4736                         sizeof(vsi->info.queue_mapping));
4737                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4738                 vsi->info.valid_sections = 0;
4739
4740                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4741                                 ETH_ADDR_LEN);
4742
4743                 /**
4744                  * Updating default filter settings are necessary to prevent
4745                  * reception of tagged packets.
4746                  * Some old firmware configurations load a default macvlan
4747                  * filter which accepts both tagged and untagged packets.
4748                  * The updating is to use a normal filter instead if needed.
4749                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4750                  * The firmware with correct configurations load the default
4751                  * macvlan filter which is expected and cannot be removed.
4752                  */
4753                 i40e_update_default_filter_setting(vsi);
4754                 i40e_config_qinq(hw, vsi);
4755         } else if (type == I40E_VSI_SRIOV) {
4756                 memset(&ctxt, 0, sizeof(ctxt));
4757                 /**
4758                  * For other VSI, the uplink_seid equals to uplink VSI's
4759                  * uplink_seid since they share same VEB
4760                  */
4761                 if (uplink_vsi == NULL)
4762                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4763                 else
4764                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4765                 ctxt.pf_num = hw->pf_id;
4766                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4767                 ctxt.uplink_seid = vsi->uplink_seid;
4768                 ctxt.connection_type = 0x1;
4769                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4770
4771                 /* Use the VEB configuration if FW >= v5.0 */
4772                 if (hw->aq.fw_maj_ver >= 5) {
4773                         /* Configure switch ID */
4774                         ctxt.info.valid_sections |=
4775                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4776                         ctxt.info.switch_id =
4777                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4778                 }
4779
4780                 /* Configure port/vlan */
4781                 ctxt.info.valid_sections |=
4782                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4783                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4784                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4785                                                 I40E_DEFAULT_TCMAP);
4786                 if (ret != I40E_SUCCESS) {
4787                         PMD_DRV_LOG(ERR, "Failed to configure "
4788                                     "TC queue mapping");
4789                         goto fail_msix_alloc;
4790                 }
4791                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4792                 ctxt.info.valid_sections |=
4793                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4794                 /**
4795                  * Since VSI is not created yet, only configure parameter,
4796                  * will add vsi below.
4797                  */
4798
4799                 i40e_config_qinq(hw, vsi);
4800         } else if (type == I40E_VSI_VMDQ2) {
4801                 memset(&ctxt, 0, sizeof(ctxt));
4802                 /*
4803                  * For other VSI, the uplink_seid equals to uplink VSI's
4804                  * uplink_seid since they share same VEB
4805                  */
4806                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4807                 ctxt.pf_num = hw->pf_id;
4808                 ctxt.vf_num = 0;
4809                 ctxt.uplink_seid = vsi->uplink_seid;
4810                 ctxt.connection_type = 0x1;
4811                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4812
4813                 ctxt.info.valid_sections |=
4814                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4815                 /* user_param carries flag to enable loop back */
4816                 if (user_param) {
4817                         ctxt.info.switch_id =
4818                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4819                         ctxt.info.switch_id |=
4820                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4821                 }
4822
4823                 /* Configure port/vlan */
4824                 ctxt.info.valid_sections |=
4825                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4826                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4827                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4828                                                 I40E_DEFAULT_TCMAP);
4829                 if (ret != I40E_SUCCESS) {
4830                         PMD_DRV_LOG(ERR, "Failed to configure "
4831                                         "TC queue mapping");
4832                         goto fail_msix_alloc;
4833                 }
4834                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4835                 ctxt.info.valid_sections |=
4836                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4837         } else if (type == I40E_VSI_FDIR) {
4838                 memset(&ctxt, 0, sizeof(ctxt));
4839                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4840                 ctxt.pf_num = hw->pf_id;
4841                 ctxt.vf_num = 0;
4842                 ctxt.uplink_seid = vsi->uplink_seid;
4843                 ctxt.connection_type = 0x1;     /* regular data port */
4844                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4845                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4846                                                 I40E_DEFAULT_TCMAP);
4847                 if (ret != I40E_SUCCESS) {
4848                         PMD_DRV_LOG(ERR, "Failed to configure "
4849                                         "TC queue mapping.");
4850                         goto fail_msix_alloc;
4851                 }
4852                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4853                 ctxt.info.valid_sections |=
4854                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4855         } else {
4856                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4857                 goto fail_msix_alloc;
4858         }
4859
4860         if (vsi->type != I40E_VSI_MAIN) {
4861                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4862                 if (ret != I40E_SUCCESS) {
4863                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4864                                     hw->aq.asq_last_status);
4865                         goto fail_msix_alloc;
4866                 }
4867                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4868                 vsi->info.valid_sections = 0;
4869                 vsi->seid = ctxt.seid;
4870                 vsi->vsi_id = ctxt.vsi_number;
4871                 vsi->sib_vsi_list.vsi = vsi;
4872                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4873                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4874                                           &vsi->sib_vsi_list, list);
4875                 } else {
4876                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4877                                           &vsi->sib_vsi_list, list);
4878                 }
4879         }
4880
4881         /* MAC/VLAN configuration */
4882         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4883         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4884
4885         ret = i40e_vsi_add_mac(vsi, &filter);
4886         if (ret != I40E_SUCCESS) {
4887                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4888                 goto fail_msix_alloc;
4889         }
4890
4891         /* Get VSI BW information */
4892         i40e_vsi_get_bw_config(vsi);
4893         return vsi;
4894 fail_msix_alloc:
4895         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4896 fail_queue_alloc:
4897         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4898 fail_mem:
4899         rte_free(vsi);
4900         return NULL;
4901 }
4902
4903 /* Configure vlan filter on or off */
4904 int
4905 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4906 {
4907         int i, num;
4908         struct i40e_mac_filter *f;
4909         void *temp;
4910         struct i40e_mac_filter_info *mac_filter;
4911         enum rte_mac_filter_type desired_filter;
4912         int ret = I40E_SUCCESS;
4913
4914         if (on) {
4915                 /* Filter to match MAC and VLAN */
4916                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4917         } else {
4918                 /* Filter to match only MAC */
4919                 desired_filter = RTE_MAC_PERFECT_MATCH;
4920         }
4921
4922         num = vsi->mac_num;
4923
4924         mac_filter = rte_zmalloc("mac_filter_info_data",
4925                                  num * sizeof(*mac_filter), 0);
4926         if (mac_filter == NULL) {
4927                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4928                 return I40E_ERR_NO_MEMORY;
4929         }
4930
4931         i = 0;
4932
4933         /* Remove all existing mac */
4934         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4935                 mac_filter[i] = f->mac_info;
4936                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4937                 if (ret) {
4938                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4939                                     on ? "enable" : "disable");
4940                         goto DONE;
4941                 }
4942                 i++;
4943         }
4944
4945         /* Override with new filter */
4946         for (i = 0; i < num; i++) {
4947                 mac_filter[i].filter_type = desired_filter;
4948                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4949                 if (ret) {
4950                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4951                                     on ? "enable" : "disable");
4952                         goto DONE;
4953                 }
4954         }
4955
4956 DONE:
4957         rte_free(mac_filter);
4958         return ret;
4959 }
4960
4961 /* Configure vlan stripping on or off */
4962 int
4963 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4964 {
4965         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4966         struct i40e_vsi_context ctxt;
4967         uint8_t vlan_flags;
4968         int ret = I40E_SUCCESS;
4969
4970         /* Check if it has been already on or off */
4971         if (vsi->info.valid_sections &
4972                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4973                 if (on) {
4974                         if ((vsi->info.port_vlan_flags &
4975                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4976                                 return 0; /* already on */
4977                 } else {
4978                         if ((vsi->info.port_vlan_flags &
4979                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4980                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4981                                 return 0; /* already off */
4982                 }
4983         }
4984
4985         if (on)
4986                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4987         else
4988                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4989         vsi->info.valid_sections =
4990                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4991         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4992         vsi->info.port_vlan_flags |= vlan_flags;
4993         ctxt.seid = vsi->seid;
4994         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4995         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4996         if (ret)
4997                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4998                             on ? "enable" : "disable");
4999
5000         return ret;
5001 }
5002
5003 static int
5004 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5005 {
5006         struct rte_eth_dev_data *data = dev->data;
5007         int ret;
5008         int mask = 0;
5009
5010         /* Apply vlan offload setting */
5011         mask = ETH_VLAN_STRIP_MASK |
5012                ETH_VLAN_FILTER_MASK |
5013                ETH_VLAN_EXTEND_MASK;
5014         i40e_vlan_offload_set(dev, mask);
5015
5016         /* Apply pvid setting */
5017         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5018                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5019         if (ret)
5020                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5021
5022         return ret;
5023 }
5024
5025 static int
5026 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5027 {
5028         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5029
5030         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5031 }
5032
5033 static int
5034 i40e_update_flow_control(struct i40e_hw *hw)
5035 {
5036 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5037         struct i40e_link_status link_status;
5038         uint32_t rxfc = 0, txfc = 0, reg;
5039         uint8_t an_info;
5040         int ret;
5041
5042         memset(&link_status, 0, sizeof(link_status));
5043         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5044         if (ret != I40E_SUCCESS) {
5045                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5046                 goto write_reg; /* Disable flow control */
5047         }
5048
5049         an_info = hw->phy.link_info.an_info;
5050         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5051                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5052                 ret = I40E_ERR_NOT_READY;
5053                 goto write_reg; /* Disable flow control */
5054         }
5055         /**
5056          * If link auto negotiation is enabled, flow control needs to
5057          * be configured according to it
5058          */
5059         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5060         case I40E_LINK_PAUSE_RXTX:
5061                 rxfc = 1;
5062                 txfc = 1;
5063                 hw->fc.current_mode = I40E_FC_FULL;
5064                 break;
5065         case I40E_AQ_LINK_PAUSE_RX:
5066                 rxfc = 1;
5067                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5068                 break;
5069         case I40E_AQ_LINK_PAUSE_TX:
5070                 txfc = 1;
5071                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5072                 break;
5073         default:
5074                 hw->fc.current_mode = I40E_FC_NONE;
5075                 break;
5076         }
5077
5078 write_reg:
5079         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5080                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5081         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5082         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5083         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5084         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5085
5086         return ret;
5087 }
5088
5089 /* PF setup */
5090 static int
5091 i40e_pf_setup(struct i40e_pf *pf)
5092 {
5093         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5094         struct i40e_filter_control_settings settings;
5095         struct i40e_vsi *vsi;
5096         int ret;
5097
5098         /* Clear all stats counters */
5099         pf->offset_loaded = FALSE;
5100         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5101         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5102         pf->internal_rx_bytes = 0;
5103         pf->internal_tx_bytes = 0;
5104         pf->internal_rx_bytes_offset = 0;
5105         pf->internal_tx_bytes_offset = 0;
5106
5107         ret = i40e_pf_get_switch_config(pf);
5108         if (ret != I40E_SUCCESS) {
5109                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5110                 return ret;
5111         }
5112         if (pf->flags & I40E_FLAG_FDIR) {
5113                 /* make queue allocated first, let FDIR use queue pair 0*/
5114                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5115                 if (ret != I40E_FDIR_QUEUE_ID) {
5116                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5117                                     " ret =%d", ret);
5118                         pf->flags &= ~I40E_FLAG_FDIR;
5119                 }
5120         }
5121         /*  main VSI setup */
5122         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5123         if (!vsi) {
5124                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5125                 return I40E_ERR_NOT_READY;
5126         }
5127         pf->main_vsi = vsi;
5128
5129         /* Configure filter control */
5130         memset(&settings, 0, sizeof(settings));
5131         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5132                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5133         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5134                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5135         else {
5136                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5137                                                 hw->func_caps.rss_table_size);
5138                 return I40E_ERR_PARAM;
5139         }
5140         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5141                         "size: %u\n", hw->func_caps.rss_table_size);
5142         pf->hash_lut_size = hw->func_caps.rss_table_size;
5143
5144         /* Enable ethtype and macvlan filters */
5145         settings.enable_ethtype = TRUE;
5146         settings.enable_macvlan = TRUE;
5147         ret = i40e_set_filter_control(hw, &settings);
5148         if (ret)
5149                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5150                                                                 ret);
5151
5152         /* Update flow control according to the auto negotiation */
5153         i40e_update_flow_control(hw);
5154
5155         return I40E_SUCCESS;
5156 }
5157
5158 int
5159 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5160 {
5161         uint32_t reg;
5162         uint16_t j;
5163
5164         /**
5165          * Set or clear TX Queue Disable flags,
5166          * which is required by hardware.
5167          */
5168         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5169         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5170
5171         /* Wait until the request is finished */
5172         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5173                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5174                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5175                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5176                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5177                                                         & 0x1))) {
5178                         break;
5179                 }
5180         }
5181         if (on) {
5182                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5183                         return I40E_SUCCESS; /* already on, skip next steps */
5184
5185                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5186                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5187         } else {
5188                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5189                         return I40E_SUCCESS; /* already off, skip next steps */
5190                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5191         }
5192         /* Write the register */
5193         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5194         /* Check the result */
5195         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5196                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5197                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5198                 if (on) {
5199                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5200                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5201                                 break;
5202                 } else {
5203                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5204                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5205                                 break;
5206                 }
5207         }
5208         /* Check if it is timeout */
5209         if (j >= I40E_CHK_Q_ENA_COUNT) {
5210                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5211                             (on ? "enable" : "disable"), q_idx);
5212                 return I40E_ERR_TIMEOUT;
5213         }
5214
5215         return I40E_SUCCESS;
5216 }
5217
5218 /* Swith on or off the tx queues */
5219 static int
5220 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5221 {
5222         struct rte_eth_dev_data *dev_data = pf->dev_data;
5223         struct i40e_tx_queue *txq;
5224         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5225         uint16_t i;
5226         int ret;
5227
5228         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5229                 txq = dev_data->tx_queues[i];
5230                 /* Don't operate the queue if not configured or
5231                  * if starting only per queue */
5232                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5233                         continue;
5234                 if (on)
5235                         ret = i40e_dev_tx_queue_start(dev, i);
5236                 else
5237                         ret = i40e_dev_tx_queue_stop(dev, i);
5238                 if ( ret != I40E_SUCCESS)
5239                         return ret;
5240         }
5241
5242         return I40E_SUCCESS;
5243 }
5244
5245 int
5246 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5247 {
5248         uint32_t reg;
5249         uint16_t j;
5250
5251         /* Wait until the request is finished */
5252         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5253                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5254                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5255                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5256                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5257                         break;
5258         }
5259
5260         if (on) {
5261                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5262                         return I40E_SUCCESS; /* Already on, skip next steps */
5263                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5264         } else {
5265                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5266                         return I40E_SUCCESS; /* Already off, skip next steps */
5267                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5268         }
5269
5270         /* Write the register */
5271         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5272         /* Check the result */
5273         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5274                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5275                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5276                 if (on) {
5277                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5278                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5279                                 break;
5280                 } else {
5281                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5282                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5283                                 break;
5284                 }
5285         }
5286
5287         /* Check if it is timeout */
5288         if (j >= I40E_CHK_Q_ENA_COUNT) {
5289                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5290                             (on ? "enable" : "disable"), q_idx);
5291                 return I40E_ERR_TIMEOUT;
5292         }
5293
5294         return I40E_SUCCESS;
5295 }
5296 /* Switch on or off the rx queues */
5297 static int
5298 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5299 {
5300         struct rte_eth_dev_data *dev_data = pf->dev_data;
5301         struct i40e_rx_queue *rxq;
5302         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5303         uint16_t i;
5304         int ret;
5305
5306         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5307                 rxq = dev_data->rx_queues[i];
5308                 /* Don't operate the queue if not configured or
5309                  * if starting only per queue */
5310                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5311                         continue;
5312                 if (on)
5313                         ret = i40e_dev_rx_queue_start(dev, i);
5314                 else
5315                         ret = i40e_dev_rx_queue_stop(dev, i);
5316                 if (ret != I40E_SUCCESS)
5317                         return ret;
5318         }
5319
5320         return I40E_SUCCESS;
5321 }
5322
5323 /* Switch on or off all the rx/tx queues */
5324 int
5325 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5326 {
5327         int ret;
5328
5329         if (on) {
5330                 /* enable rx queues before enabling tx queues */
5331                 ret = i40e_dev_switch_rx_queues(pf, on);
5332                 if (ret) {
5333                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5334                         return ret;
5335                 }
5336                 ret = i40e_dev_switch_tx_queues(pf, on);
5337         } else {
5338                 /* Stop tx queues before stopping rx queues */
5339                 ret = i40e_dev_switch_tx_queues(pf, on);
5340                 if (ret) {
5341                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5342                         return ret;
5343                 }
5344                 ret = i40e_dev_switch_rx_queues(pf, on);
5345         }
5346
5347         return ret;
5348 }
5349
5350 /* Initialize VSI for TX */
5351 static int
5352 i40e_dev_tx_init(struct i40e_pf *pf)
5353 {
5354         struct rte_eth_dev_data *data = pf->dev_data;
5355         uint16_t i;
5356         uint32_t ret = I40E_SUCCESS;
5357         struct i40e_tx_queue *txq;
5358
5359         for (i = 0; i < data->nb_tx_queues; i++) {
5360                 txq = data->tx_queues[i];
5361                 if (!txq || !txq->q_set)
5362                         continue;
5363                 ret = i40e_tx_queue_init(txq);
5364                 if (ret != I40E_SUCCESS)
5365                         break;
5366         }
5367         if (ret == I40E_SUCCESS)
5368                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5369                                      ->eth_dev);
5370
5371         return ret;
5372 }
5373
5374 /* Initialize VSI for RX */
5375 static int
5376 i40e_dev_rx_init(struct i40e_pf *pf)
5377 {
5378         struct rte_eth_dev_data *data = pf->dev_data;
5379         int ret = I40E_SUCCESS;
5380         uint16_t i;
5381         struct i40e_rx_queue *rxq;
5382
5383         i40e_pf_config_mq_rx(pf);
5384         for (i = 0; i < data->nb_rx_queues; i++) {
5385                 rxq = data->rx_queues[i];
5386                 if (!rxq || !rxq->q_set)
5387                         continue;
5388
5389                 ret = i40e_rx_queue_init(rxq);
5390                 if (ret != I40E_SUCCESS) {
5391                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5392                                     "initialization");
5393                         break;
5394                 }
5395         }
5396         if (ret == I40E_SUCCESS)
5397                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5398                                      ->eth_dev);
5399
5400         return ret;
5401 }
5402
5403 static int
5404 i40e_dev_rxtx_init(struct i40e_pf *pf)
5405 {
5406         int err;
5407
5408         err = i40e_dev_tx_init(pf);
5409         if (err) {
5410                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5411                 return err;
5412         }
5413         err = i40e_dev_rx_init(pf);
5414         if (err) {
5415                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5416                 return err;
5417         }
5418
5419         return err;
5420 }
5421
5422 static int
5423 i40e_vmdq_setup(struct rte_eth_dev *dev)
5424 {
5425         struct rte_eth_conf *conf = &dev->data->dev_conf;
5426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5427         int i, err, conf_vsis, j, loop;
5428         struct i40e_vsi *vsi;
5429         struct i40e_vmdq_info *vmdq_info;
5430         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5431         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5432
5433         /*
5434          * Disable interrupt to avoid message from VF. Furthermore, it will
5435          * avoid race condition in VSI creation/destroy.
5436          */
5437         i40e_pf_disable_irq0(hw);
5438
5439         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5440                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5441                 return -ENOTSUP;
5442         }
5443
5444         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5445         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5446                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5447                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5448                         pf->max_nb_vmdq_vsi);
5449                 return -ENOTSUP;
5450         }
5451
5452         if (pf->vmdq != NULL) {
5453                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5454                 return 0;
5455         }
5456
5457         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5458                                 sizeof(*vmdq_info) * conf_vsis, 0);
5459
5460         if (pf->vmdq == NULL) {
5461                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5462                 return -ENOMEM;
5463         }
5464
5465         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5466
5467         /* Create VMDQ VSI */
5468         for (i = 0; i < conf_vsis; i++) {
5469                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5470                                 vmdq_conf->enable_loop_back);
5471                 if (vsi == NULL) {
5472                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5473                         err = -1;
5474                         goto err_vsi_setup;
5475                 }
5476                 vmdq_info = &pf->vmdq[i];
5477                 vmdq_info->pf = pf;
5478                 vmdq_info->vsi = vsi;
5479         }
5480         pf->nb_cfg_vmdq_vsi = conf_vsis;
5481
5482         /* Configure Vlan */
5483         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5484         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5485                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5486                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5487                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5488                                         vmdq_conf->pool_map[i].vlan_id, j);
5489
5490                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5491                                                 vmdq_conf->pool_map[i].vlan_id);
5492                                 if (err) {
5493                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5494                                         err = -1;
5495                                         goto err_vsi_setup;
5496                                 }
5497                         }
5498                 }
5499         }
5500
5501         i40e_pf_enable_irq0(hw);
5502
5503         return 0;
5504
5505 err_vsi_setup:
5506         for (i = 0; i < conf_vsis; i++)
5507                 if (pf->vmdq[i].vsi == NULL)
5508                         break;
5509                 else
5510                         i40e_vsi_release(pf->vmdq[i].vsi);
5511
5512         rte_free(pf->vmdq);
5513         pf->vmdq = NULL;
5514         i40e_pf_enable_irq0(hw);
5515         return err;
5516 }
5517
5518 static void
5519 i40e_stat_update_32(struct i40e_hw *hw,
5520                    uint32_t reg,
5521                    bool offset_loaded,
5522                    uint64_t *offset,
5523                    uint64_t *stat)
5524 {
5525         uint64_t new_data;
5526
5527         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5528         if (!offset_loaded)
5529                 *offset = new_data;
5530
5531         if (new_data >= *offset)
5532                 *stat = (uint64_t)(new_data - *offset);
5533         else
5534                 *stat = (uint64_t)((new_data +
5535                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5536 }
5537
5538 static void
5539 i40e_stat_update_48(struct i40e_hw *hw,
5540                    uint32_t hireg,
5541                    uint32_t loreg,
5542                    bool offset_loaded,
5543                    uint64_t *offset,
5544                    uint64_t *stat)
5545 {
5546         uint64_t new_data;
5547
5548         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5549         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5550                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5551
5552         if (!offset_loaded)
5553                 *offset = new_data;
5554
5555         if (new_data >= *offset)
5556                 *stat = new_data - *offset;
5557         else
5558                 *stat = (uint64_t)((new_data +
5559                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5560
5561         *stat &= I40E_48_BIT_MASK;
5562 }
5563
5564 /* Disable IRQ0 */
5565 void
5566 i40e_pf_disable_irq0(struct i40e_hw *hw)
5567 {
5568         /* Disable all interrupt types */
5569         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5570                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5571         I40E_WRITE_FLUSH(hw);
5572 }
5573
5574 /* Enable IRQ0 */
5575 void
5576 i40e_pf_enable_irq0(struct i40e_hw *hw)
5577 {
5578         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5579                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5580                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5581                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5582         I40E_WRITE_FLUSH(hw);
5583 }
5584
5585 static void
5586 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5587 {
5588         /* read pending request and disable first */
5589         i40e_pf_disable_irq0(hw);
5590         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5591         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5592                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5593
5594         if (no_queue)
5595                 /* Link no queues with irq0 */
5596                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5597                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5598 }
5599
5600 static void
5601 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5602 {
5603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5605         int i;
5606         uint16_t abs_vf_id;
5607         uint32_t index, offset, val;
5608
5609         if (!pf->vfs)
5610                 return;
5611         /**
5612          * Try to find which VF trigger a reset, use absolute VF id to access
5613          * since the reg is global register.
5614          */
5615         for (i = 0; i < pf->vf_num; i++) {
5616                 abs_vf_id = hw->func_caps.vf_base_id + i;
5617                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5618                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5619                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5620                 /* VFR event occured */
5621                 if (val & (0x1 << offset)) {
5622                         int ret;
5623
5624                         /* Clear the event first */
5625                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5626                                                         (0x1 << offset));
5627                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5628                         /**
5629                          * Only notify a VF reset event occured,
5630                          * don't trigger another SW reset
5631                          */
5632                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5633                         if (ret != I40E_SUCCESS)
5634                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5635                 }
5636         }
5637 }
5638
5639 static void
5640 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5641 {
5642         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5643         struct i40e_virtchnl_pf_event event;
5644         int i;
5645
5646         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5647         event.event_data.link_event.link_status =
5648                 dev->data->dev_link.link_status;
5649         event.event_data.link_event.link_speed =
5650                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5651
5652         for (i = 0; i < pf->vf_num; i++)
5653                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5654                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5655 }
5656
5657 static void
5658 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5659 {
5660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5661         struct i40e_arq_event_info info;
5662         uint16_t pending, opcode;
5663         int ret;
5664
5665         info.buf_len = I40E_AQ_BUF_SZ;
5666         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5667         if (!info.msg_buf) {
5668                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5669                 return;
5670         }
5671
5672         pending = 1;
5673         while (pending) {
5674                 ret = i40e_clean_arq_element(hw, &info, &pending);
5675
5676                 if (ret != I40E_SUCCESS) {
5677                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5678                                     "aq_err: %u", hw->aq.asq_last_status);
5679                         break;
5680                 }
5681                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5682
5683                 switch (opcode) {
5684                 case i40e_aqc_opc_send_msg_to_pf:
5685                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5686                         i40e_pf_host_handle_vf_msg(dev,
5687                                         rte_le_to_cpu_16(info.desc.retval),
5688                                         rte_le_to_cpu_32(info.desc.cookie_high),
5689                                         rte_le_to_cpu_32(info.desc.cookie_low),
5690                                         info.msg_buf,
5691                                         info.msg_len);
5692                         break;
5693                 case i40e_aqc_opc_get_link_status:
5694                         ret = i40e_dev_link_update(dev, 0);
5695                         if (!ret)
5696                                 _rte_eth_dev_callback_process(dev,
5697                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5698                         break;
5699                 default:
5700                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5701                                     opcode);
5702                         break;
5703                 }
5704         }
5705         rte_free(info.msg_buf);
5706 }
5707
5708 /**
5709  * Interrupt handler triggered by NIC  for handling
5710  * specific interrupt.
5711  *
5712  * @param handle
5713  *  Pointer to interrupt handle.
5714  * @param param
5715  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5716  *
5717  * @return
5718  *  void
5719  */
5720 static void
5721 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5722                            void *param)
5723 {
5724         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5726         uint32_t icr0;
5727
5728         /* Disable interrupt */
5729         i40e_pf_disable_irq0(hw);
5730
5731         /* read out interrupt causes */
5732         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5733
5734         /* No interrupt event indicated */
5735         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5736                 PMD_DRV_LOG(INFO, "No interrupt event");
5737                 goto done;
5738         }
5739 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5740         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5741                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5742         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5743                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5744         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5745                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5746         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5747                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5748         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5749                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5750         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5751                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5752         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5753                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5754 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5755
5756         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5757                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5758                 i40e_dev_handle_vfr_event(dev);
5759         }
5760         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5761                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5762                 i40e_dev_handle_aq_msg(dev);
5763         }
5764
5765 done:
5766         /* Enable interrupt */
5767         i40e_pf_enable_irq0(hw);
5768         rte_intr_enable(&(dev->pci_dev->intr_handle));
5769 }
5770
5771 static int
5772 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5773                          struct i40e_macvlan_filter *filter,
5774                          int total)
5775 {
5776         int ele_num, ele_buff_size;
5777         int num, actual_num, i;
5778         uint16_t flags;
5779         int ret = I40E_SUCCESS;
5780         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5781         struct i40e_aqc_add_macvlan_element_data *req_list;
5782
5783         if (filter == NULL  || total == 0)
5784                 return I40E_ERR_PARAM;
5785         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5786         ele_buff_size = hw->aq.asq_buf_size;
5787
5788         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5789         if (req_list == NULL) {
5790                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5791                 return I40E_ERR_NO_MEMORY;
5792         }
5793
5794         num = 0;
5795         do {
5796                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5797                 memset(req_list, 0, ele_buff_size);
5798
5799                 for (i = 0; i < actual_num; i++) {
5800                         (void)rte_memcpy(req_list[i].mac_addr,
5801                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5802                         req_list[i].vlan_tag =
5803                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5804
5805                         switch (filter[num + i].filter_type) {
5806                         case RTE_MAC_PERFECT_MATCH:
5807                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5808                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5809                                 break;
5810                         case RTE_MACVLAN_PERFECT_MATCH:
5811                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5812                                 break;
5813                         case RTE_MAC_HASH_MATCH:
5814                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5815                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5816                                 break;
5817                         case RTE_MACVLAN_HASH_MATCH:
5818                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5819                                 break;
5820                         default:
5821                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5822                                 ret = I40E_ERR_PARAM;
5823                                 goto DONE;
5824                         }
5825
5826                         req_list[i].queue_number = 0;
5827
5828                         req_list[i].flags = rte_cpu_to_le_16(flags);
5829                 }
5830
5831                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5832                                                 actual_num, NULL);
5833                 if (ret != I40E_SUCCESS) {
5834                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5835                         goto DONE;
5836                 }
5837                 num += actual_num;
5838         } while (num < total);
5839
5840 DONE:
5841         rte_free(req_list);
5842         return ret;
5843 }
5844
5845 static int
5846 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5847                             struct i40e_macvlan_filter *filter,
5848                             int total)
5849 {
5850         int ele_num, ele_buff_size;
5851         int num, actual_num, i;
5852         uint16_t flags;
5853         int ret = I40E_SUCCESS;
5854         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5855         struct i40e_aqc_remove_macvlan_element_data *req_list;
5856
5857         if (filter == NULL  || total == 0)
5858                 return I40E_ERR_PARAM;
5859
5860         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5861         ele_buff_size = hw->aq.asq_buf_size;
5862
5863         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5864         if (req_list == NULL) {
5865                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5866                 return I40E_ERR_NO_MEMORY;
5867         }
5868
5869         num = 0;
5870         do {
5871                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5872                 memset(req_list, 0, ele_buff_size);
5873
5874                 for (i = 0; i < actual_num; i++) {
5875                         (void)rte_memcpy(req_list[i].mac_addr,
5876                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5877                         req_list[i].vlan_tag =
5878                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5879
5880                         switch (filter[num + i].filter_type) {
5881                         case RTE_MAC_PERFECT_MATCH:
5882                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5883                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5884                                 break;
5885                         case RTE_MACVLAN_PERFECT_MATCH:
5886                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5887                                 break;
5888                         case RTE_MAC_HASH_MATCH:
5889                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5890                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5891                                 break;
5892                         case RTE_MACVLAN_HASH_MATCH:
5893                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5894                                 break;
5895                         default:
5896                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5897                                 ret = I40E_ERR_PARAM;
5898                                 goto DONE;
5899                         }
5900                         req_list[i].flags = rte_cpu_to_le_16(flags);
5901                 }
5902
5903                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5904                                                 actual_num, NULL);
5905                 if (ret != I40E_SUCCESS) {
5906                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5907                         goto DONE;
5908                 }
5909                 num += actual_num;
5910         } while (num < total);
5911
5912 DONE:
5913         rte_free(req_list);
5914         return ret;
5915 }
5916
5917 /* Find out specific MAC filter */
5918 static struct i40e_mac_filter *
5919 i40e_find_mac_filter(struct i40e_vsi *vsi,
5920                          struct ether_addr *macaddr)
5921 {
5922         struct i40e_mac_filter *f;
5923
5924         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5925                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5926                         return f;
5927         }
5928
5929         return NULL;
5930 }
5931
5932 static bool
5933 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5934                          uint16_t vlan_id)
5935 {
5936         uint32_t vid_idx, vid_bit;
5937
5938         if (vlan_id > ETH_VLAN_ID_MAX)
5939                 return 0;
5940
5941         vid_idx = I40E_VFTA_IDX(vlan_id);
5942         vid_bit = I40E_VFTA_BIT(vlan_id);
5943
5944         if (vsi->vfta[vid_idx] & vid_bit)
5945                 return 1;
5946         else
5947                 return 0;
5948 }
5949
5950 static void
5951 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5952                          uint16_t vlan_id, bool on)
5953 {
5954         uint32_t vid_idx, vid_bit;
5955
5956         if (vlan_id > ETH_VLAN_ID_MAX)
5957                 return;
5958
5959         vid_idx = I40E_VFTA_IDX(vlan_id);
5960         vid_bit = I40E_VFTA_BIT(vlan_id);
5961
5962         if (on)
5963                 vsi->vfta[vid_idx] |= vid_bit;
5964         else
5965                 vsi->vfta[vid_idx] &= ~vid_bit;
5966 }
5967
5968 /**
5969  * Find all vlan options for specific mac addr,
5970  * return with actual vlan found.
5971  */
5972 static inline int
5973 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5974                            struct i40e_macvlan_filter *mv_f,
5975                            int num, struct ether_addr *addr)
5976 {
5977         int i;
5978         uint32_t j, k;
5979
5980         /**
5981          * Not to use i40e_find_vlan_filter to decrease the loop time,
5982          * although the code looks complex.
5983           */
5984         if (num < vsi->vlan_num)
5985                 return I40E_ERR_PARAM;
5986
5987         i = 0;
5988         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5989                 if (vsi->vfta[j]) {
5990                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5991                                 if (vsi->vfta[j] & (1 << k)) {
5992                                         if (i > num - 1) {
5993                                                 PMD_DRV_LOG(ERR, "vlan number "
5994                                                             "not match");
5995                                                 return I40E_ERR_PARAM;
5996                                         }
5997                                         (void)rte_memcpy(&mv_f[i].macaddr,
5998                                                         addr, ETH_ADDR_LEN);
5999                                         mv_f[i].vlan_id =
6000                                                 j * I40E_UINT32_BIT_SIZE + k;
6001                                         i++;
6002                                 }
6003                         }
6004                 }
6005         }
6006         return I40E_SUCCESS;
6007 }
6008
6009 static inline int
6010 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6011                            struct i40e_macvlan_filter *mv_f,
6012                            int num,
6013                            uint16_t vlan)
6014 {
6015         int i = 0;
6016         struct i40e_mac_filter *f;
6017
6018         if (num < vsi->mac_num)
6019                 return I40E_ERR_PARAM;
6020
6021         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6022                 if (i > num - 1) {
6023                         PMD_DRV_LOG(ERR, "buffer number not match");
6024                         return I40E_ERR_PARAM;
6025                 }
6026                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6027                                 ETH_ADDR_LEN);
6028                 mv_f[i].vlan_id = vlan;
6029                 mv_f[i].filter_type = f->mac_info.filter_type;
6030                 i++;
6031         }
6032
6033         return I40E_SUCCESS;
6034 }
6035
6036 static int
6037 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6038 {
6039         int i, j, num;
6040         struct i40e_mac_filter *f;
6041         struct i40e_macvlan_filter *mv_f;
6042         int ret = I40E_SUCCESS;
6043
6044         if (vsi == NULL || vsi->mac_num == 0)
6045                 return I40E_ERR_PARAM;
6046
6047         /* Case that no vlan is set */
6048         if (vsi->vlan_num == 0)
6049                 num = vsi->mac_num;
6050         else
6051                 num = vsi->mac_num * vsi->vlan_num;
6052
6053         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6054         if (mv_f == NULL) {
6055                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6056                 return I40E_ERR_NO_MEMORY;
6057         }
6058
6059         i = 0;
6060         if (vsi->vlan_num == 0) {
6061                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6062                         (void)rte_memcpy(&mv_f[i].macaddr,
6063                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6064                         mv_f[i].filter_type = f->mac_info.filter_type;
6065                         mv_f[i].vlan_id = 0;
6066                         i++;
6067                 }
6068         } else {
6069                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6070                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6071                                         vsi->vlan_num, &f->mac_info.mac_addr);
6072                         if (ret != I40E_SUCCESS)
6073                                 goto DONE;
6074                         for (j = i; j < i + vsi->vlan_num; j++)
6075                                 mv_f[j].filter_type = f->mac_info.filter_type;
6076                         i += vsi->vlan_num;
6077                 }
6078         }
6079
6080         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6081 DONE:
6082         rte_free(mv_f);
6083
6084         return ret;
6085 }
6086
6087 int
6088 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6089 {
6090         struct i40e_macvlan_filter *mv_f;
6091         int mac_num;
6092         int ret = I40E_SUCCESS;
6093
6094         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6095                 return I40E_ERR_PARAM;
6096
6097         /* If it's already set, just return */
6098         if (i40e_find_vlan_filter(vsi,vlan))
6099                 return I40E_SUCCESS;
6100
6101         mac_num = vsi->mac_num;
6102
6103         if (mac_num == 0) {
6104                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6105                 return I40E_ERR_PARAM;
6106         }
6107
6108         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6109
6110         if (mv_f == NULL) {
6111                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6112                 return I40E_ERR_NO_MEMORY;
6113         }
6114
6115         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6116
6117         if (ret != I40E_SUCCESS)
6118                 goto DONE;
6119
6120         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6121
6122         if (ret != I40E_SUCCESS)
6123                 goto DONE;
6124
6125         i40e_set_vlan_filter(vsi, vlan, 1);
6126
6127         vsi->vlan_num++;
6128         ret = I40E_SUCCESS;
6129 DONE:
6130         rte_free(mv_f);
6131         return ret;
6132 }
6133
6134 int
6135 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6136 {
6137         struct i40e_macvlan_filter *mv_f;
6138         int mac_num;
6139         int ret = I40E_SUCCESS;
6140
6141         /**
6142          * Vlan 0 is the generic filter for untagged packets
6143          * and can't be removed.
6144          */
6145         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6146                 return I40E_ERR_PARAM;
6147
6148         /* If can't find it, just return */
6149         if (!i40e_find_vlan_filter(vsi, vlan))
6150                 return I40E_ERR_PARAM;
6151
6152         mac_num = vsi->mac_num;
6153
6154         if (mac_num == 0) {
6155                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6156                 return I40E_ERR_PARAM;
6157         }
6158
6159         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6160
6161         if (mv_f == NULL) {
6162                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6163                 return I40E_ERR_NO_MEMORY;
6164         }
6165
6166         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6167
6168         if (ret != I40E_SUCCESS)
6169                 goto DONE;
6170
6171         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6172
6173         if (ret != I40E_SUCCESS)
6174                 goto DONE;
6175
6176         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6177         if (vsi->vlan_num == 1) {
6178                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6179                 if (ret != I40E_SUCCESS)
6180                         goto DONE;
6181
6182                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6183                 if (ret != I40E_SUCCESS)
6184                         goto DONE;
6185         }
6186
6187         i40e_set_vlan_filter(vsi, vlan, 0);
6188
6189         vsi->vlan_num--;
6190         ret = I40E_SUCCESS;
6191 DONE:
6192         rte_free(mv_f);
6193         return ret;
6194 }
6195
6196 int
6197 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6198 {
6199         struct i40e_mac_filter *f;
6200         struct i40e_macvlan_filter *mv_f;
6201         int i, vlan_num = 0;
6202         int ret = I40E_SUCCESS;
6203
6204         /* If it's add and we've config it, return */
6205         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6206         if (f != NULL)
6207                 return I40E_SUCCESS;
6208         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6209                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6210
6211                 /**
6212                  * If vlan_num is 0, that's the first time to add mac,
6213                  * set mask for vlan_id 0.
6214                  */
6215                 if (vsi->vlan_num == 0) {
6216                         i40e_set_vlan_filter(vsi, 0, 1);
6217                         vsi->vlan_num = 1;
6218                 }
6219                 vlan_num = vsi->vlan_num;
6220         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6221                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6222                 vlan_num = 1;
6223
6224         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6225         if (mv_f == NULL) {
6226                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6227                 return I40E_ERR_NO_MEMORY;
6228         }
6229
6230         for (i = 0; i < vlan_num; i++) {
6231                 mv_f[i].filter_type = mac_filter->filter_type;
6232                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6233                                 ETH_ADDR_LEN);
6234         }
6235
6236         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6237                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6238                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6239                                         &mac_filter->mac_addr);
6240                 if (ret != I40E_SUCCESS)
6241                         goto DONE;
6242         }
6243
6244         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6245         if (ret != I40E_SUCCESS)
6246                 goto DONE;
6247
6248         /* Add the mac addr into mac list */
6249         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6250         if (f == NULL) {
6251                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6252                 ret = I40E_ERR_NO_MEMORY;
6253                 goto DONE;
6254         }
6255         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6256                         ETH_ADDR_LEN);
6257         f->mac_info.filter_type = mac_filter->filter_type;
6258         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6259         vsi->mac_num++;
6260
6261         ret = I40E_SUCCESS;
6262 DONE:
6263         rte_free(mv_f);
6264
6265         return ret;
6266 }
6267
6268 int
6269 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6270 {
6271         struct i40e_mac_filter *f;
6272         struct i40e_macvlan_filter *mv_f;
6273         int i, vlan_num;
6274         enum rte_mac_filter_type filter_type;
6275         int ret = I40E_SUCCESS;
6276
6277         /* Can't find it, return an error */
6278         f = i40e_find_mac_filter(vsi, addr);
6279         if (f == NULL)
6280                 return I40E_ERR_PARAM;
6281
6282         vlan_num = vsi->vlan_num;
6283         filter_type = f->mac_info.filter_type;
6284         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6285                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6286                 if (vlan_num == 0) {
6287                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6288                         return I40E_ERR_PARAM;
6289                 }
6290         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6291                         filter_type == RTE_MAC_HASH_MATCH)
6292                 vlan_num = 1;
6293
6294         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6295         if (mv_f == NULL) {
6296                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6297                 return I40E_ERR_NO_MEMORY;
6298         }
6299
6300         for (i = 0; i < vlan_num; i++) {
6301                 mv_f[i].filter_type = filter_type;
6302                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6303                                 ETH_ADDR_LEN);
6304         }
6305         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6306                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6307                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6308                 if (ret != I40E_SUCCESS)
6309                         goto DONE;
6310         }
6311
6312         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6313         if (ret != I40E_SUCCESS)
6314                 goto DONE;
6315
6316         /* Remove the mac addr into mac list */
6317         TAILQ_REMOVE(&vsi->mac_list, f, next);
6318         rte_free(f);
6319         vsi->mac_num--;
6320
6321         ret = I40E_SUCCESS;
6322 DONE:
6323         rte_free(mv_f);
6324         return ret;
6325 }
6326
6327 /* Configure hash enable flags for RSS */
6328 uint64_t
6329 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6330 {
6331         uint64_t hena = 0;
6332
6333         if (!flags)
6334                 return hena;
6335
6336         if (flags & ETH_RSS_FRAG_IPV4)
6337                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6338         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6339                 if (type == I40E_MAC_X722) {
6340                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6341                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6342                 } else
6343                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6344         }
6345         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6346                 if (type == I40E_MAC_X722) {
6347                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6348                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6349                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6350                 } else
6351                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6352         }
6353         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6354                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6355         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6356                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6357         if (flags & ETH_RSS_FRAG_IPV6)
6358                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6359         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6360                 if (type == I40E_MAC_X722) {
6361                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6362                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6363                 } else
6364                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6365         }
6366         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6367                 if (type == I40E_MAC_X722) {
6368                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6369                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6370                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6371                 } else
6372                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6373         }
6374         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6375                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6376         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6377                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6378         if (flags & ETH_RSS_L2_PAYLOAD)
6379                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6380
6381         return hena;
6382 }
6383
6384 /* Parse the hash enable flags */
6385 uint64_t
6386 i40e_parse_hena(uint64_t flags)
6387 {
6388         uint64_t rss_hf = 0;
6389
6390         if (!flags)
6391                 return rss_hf;
6392         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6393                 rss_hf |= ETH_RSS_FRAG_IPV4;
6394         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6395                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6396 #ifdef X722_SUPPORT
6397         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6398                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6399 #endif
6400         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6401                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6402 #ifdef X722_SUPPORT
6403         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6404                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6405         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6406                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6407 #endif
6408         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6409                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6410         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6411                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6412         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6413                 rss_hf |= ETH_RSS_FRAG_IPV6;
6414         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6415                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6416 #ifdef X722_SUPPORT
6417         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6418                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6419 #endif
6420         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6421                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6422 #ifdef X722_SUPPORT
6423         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6424                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6425         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6426                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6427 #endif
6428         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6429                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6430         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6431                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6432         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6433                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6434
6435         return rss_hf;
6436 }
6437
6438 /* Disable RSS */
6439 static void
6440 i40e_pf_disable_rss(struct i40e_pf *pf)
6441 {
6442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6443         uint64_t hena;
6444
6445         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6446         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6447         if (hw->mac.type == I40E_MAC_X722)
6448                 hena &= ~I40E_RSS_HENA_ALL_X722;
6449         else
6450                 hena &= ~I40E_RSS_HENA_ALL;
6451         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6452         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6453         I40E_WRITE_FLUSH(hw);
6454 }
6455
6456 static int
6457 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6458 {
6459         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6460         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6461         int ret = 0;
6462
6463         if (!key || key_len == 0) {
6464                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6465                 return 0;
6466         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6467                 sizeof(uint32_t)) {
6468                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6469                 return -EINVAL;
6470         }
6471
6472         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6473                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6474                         (struct i40e_aqc_get_set_rss_key_data *)key;
6475
6476                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6477                 if (ret)
6478                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6479                                      "via AQ");
6480         } else {
6481                 uint32_t *hash_key = (uint32_t *)key;
6482                 uint16_t i;
6483
6484                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6485                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6486                 I40E_WRITE_FLUSH(hw);
6487         }
6488
6489         return ret;
6490 }
6491
6492 static int
6493 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6494 {
6495         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6496         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6497         int ret;
6498
6499         if (!key || !key_len)
6500                 return -EINVAL;
6501
6502         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6503                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6504                         (struct i40e_aqc_get_set_rss_key_data *)key);
6505                 if (ret) {
6506                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6507                         return ret;
6508                 }
6509         } else {
6510                 uint32_t *key_dw = (uint32_t *)key;
6511                 uint16_t i;
6512
6513                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6514                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6515         }
6516         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6517
6518         return 0;
6519 }
6520
6521 static int
6522 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6523 {
6524         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6525         uint64_t rss_hf;
6526         uint64_t hena;
6527         int ret;
6528
6529         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6530                                rss_conf->rss_key_len);
6531         if (ret)
6532                 return ret;
6533
6534         rss_hf = rss_conf->rss_hf;
6535         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6536         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6537         if (hw->mac.type == I40E_MAC_X722)
6538                 hena &= ~I40E_RSS_HENA_ALL_X722;
6539         else
6540                 hena &= ~I40E_RSS_HENA_ALL;
6541         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6542         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6543         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6544         I40E_WRITE_FLUSH(hw);
6545
6546         return 0;
6547 }
6548
6549 static int
6550 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6551                          struct rte_eth_rss_conf *rss_conf)
6552 {
6553         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6555         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6556         uint64_t hena;
6557
6558         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6559         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6560         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6561                  ? I40E_RSS_HENA_ALL_X722
6562                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6563                 if (rss_hf != 0) /* Enable RSS */
6564                         return -EINVAL;
6565                 return 0; /* Nothing to do */
6566         }
6567         /* RSS enabled */
6568         if (rss_hf == 0) /* Disable RSS */
6569                 return -EINVAL;
6570
6571         return i40e_hw_rss_hash_set(pf, rss_conf);
6572 }
6573
6574 static int
6575 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6576                            struct rte_eth_rss_conf *rss_conf)
6577 {
6578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6579         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6580         uint64_t hena;
6581
6582         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6583                          &rss_conf->rss_key_len);
6584
6585         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6586         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6587         rss_conf->rss_hf = i40e_parse_hena(hena);
6588
6589         return 0;
6590 }
6591
6592 static int
6593 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6594 {
6595         switch (filter_type) {
6596         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6597                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6598                 break;
6599         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6600                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6601                 break;
6602         case RTE_TUNNEL_FILTER_IMAC_TENID:
6603                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6604                 break;
6605         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6606                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6607                 break;
6608         case ETH_TUNNEL_FILTER_IMAC:
6609                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6610                 break;
6611         case ETH_TUNNEL_FILTER_OIP:
6612                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6613                 break;
6614         case ETH_TUNNEL_FILTER_IIP:
6615                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6616                 break;
6617         default:
6618                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6619                 return -EINVAL;
6620         }
6621
6622         return 0;
6623 }
6624
6625 static int
6626 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6627                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6628                         uint8_t add)
6629 {
6630         uint16_t ip_type;
6631         uint32_t ipv4_addr, ipv4_addr_le;
6632         uint8_t i, tun_type = 0;
6633         /* internal varialbe to convert ipv6 byte order */
6634         uint32_t convert_ipv6[4];
6635         int val, ret = 0;
6636         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6637         struct i40e_vsi *vsi = pf->main_vsi;
6638         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6639         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6640
6641         cld_filter = rte_zmalloc("tunnel_filter",
6642                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6643                 0);
6644
6645         if (NULL == cld_filter) {
6646                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6647                 return -EINVAL;
6648         }
6649         pfilter = cld_filter;
6650
6651         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6652         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6653
6654         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6655         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6656                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6657                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6658                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
6659                 rte_memcpy(&pfilter->ipaddr.v4.data,
6660                                 &ipv4_addr_le,
6661                                 sizeof(pfilter->ipaddr.v4.data));
6662         } else {
6663                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6664                 for (i = 0; i < 4; i++) {
6665                         convert_ipv6[i] =
6666                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6667                 }
6668                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6669                                 sizeof(pfilter->ipaddr.v6.data));
6670         }
6671
6672         /* check tunneled type */
6673         switch (tunnel_filter->tunnel_type) {
6674         case RTE_TUNNEL_TYPE_VXLAN:
6675                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6676                 break;
6677         case RTE_TUNNEL_TYPE_NVGRE:
6678                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6679                 break;
6680         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6681                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6682                 break;
6683         default:
6684                 /* Other tunnel types is not supported. */
6685                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6686                 rte_free(cld_filter);
6687                 return -EINVAL;
6688         }
6689
6690         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6691                                                 &pfilter->flags);
6692         if (val < 0) {
6693                 rte_free(cld_filter);
6694                 return -EINVAL;
6695         }
6696
6697         pfilter->flags |= rte_cpu_to_le_16(
6698                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6699                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6700         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6701         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6702
6703         if (add)
6704                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6705         else
6706                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6707                                                 cld_filter, 1);
6708
6709         rte_free(cld_filter);
6710         return ret;
6711 }
6712
6713 static int
6714 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6715 {
6716         uint8_t i;
6717
6718         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6719                 if (pf->vxlan_ports[i] == port)
6720                         return i;
6721         }
6722
6723         return -1;
6724 }
6725
6726 static int
6727 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6728 {
6729         int  idx, ret;
6730         uint8_t filter_idx;
6731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6732
6733         idx = i40e_get_vxlan_port_idx(pf, port);
6734
6735         /* Check if port already exists */
6736         if (idx >= 0) {
6737                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6738                 return -EINVAL;
6739         }
6740
6741         /* Now check if there is space to add the new port */
6742         idx = i40e_get_vxlan_port_idx(pf, 0);
6743         if (idx < 0) {
6744                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6745                         "not adding port %d", port);
6746                 return -ENOSPC;
6747         }
6748
6749         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6750                                         &filter_idx, NULL);
6751         if (ret < 0) {
6752                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6753                 return -1;
6754         }
6755
6756         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6757                          port,  filter_idx);
6758
6759         /* New port: add it and mark its index in the bitmap */
6760         pf->vxlan_ports[idx] = port;
6761         pf->vxlan_bitmap |= (1 << idx);
6762
6763         if (!(pf->flags & I40E_FLAG_VXLAN))
6764                 pf->flags |= I40E_FLAG_VXLAN;
6765
6766         return 0;
6767 }
6768
6769 static int
6770 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6771 {
6772         int idx;
6773         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6774
6775         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6776                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6777                 return -EINVAL;
6778         }
6779
6780         idx = i40e_get_vxlan_port_idx(pf, port);
6781
6782         if (idx < 0) {
6783                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6784                 return -EINVAL;
6785         }
6786
6787         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6788                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6789                 return -1;
6790         }
6791
6792         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6793                         port, idx);
6794
6795         pf->vxlan_ports[idx] = 0;
6796         pf->vxlan_bitmap &= ~(1 << idx);
6797
6798         if (!pf->vxlan_bitmap)
6799                 pf->flags &= ~I40E_FLAG_VXLAN;
6800
6801         return 0;
6802 }
6803
6804 /* Add UDP tunneling port */
6805 static int
6806 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6807                              struct rte_eth_udp_tunnel *udp_tunnel)
6808 {
6809         int ret = 0;
6810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6811
6812         if (udp_tunnel == NULL)
6813                 return -EINVAL;
6814
6815         switch (udp_tunnel->prot_type) {
6816         case RTE_TUNNEL_TYPE_VXLAN:
6817                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6818                 break;
6819
6820         case RTE_TUNNEL_TYPE_GENEVE:
6821         case RTE_TUNNEL_TYPE_TEREDO:
6822                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6823                 ret = -1;
6824                 break;
6825
6826         default:
6827                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6828                 ret = -1;
6829                 break;
6830         }
6831
6832         return ret;
6833 }
6834
6835 /* Remove UDP tunneling port */
6836 static int
6837 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6838                              struct rte_eth_udp_tunnel *udp_tunnel)
6839 {
6840         int ret = 0;
6841         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6842
6843         if (udp_tunnel == NULL)
6844                 return -EINVAL;
6845
6846         switch (udp_tunnel->prot_type) {
6847         case RTE_TUNNEL_TYPE_VXLAN:
6848                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6849                 break;
6850         case RTE_TUNNEL_TYPE_GENEVE:
6851         case RTE_TUNNEL_TYPE_TEREDO:
6852                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6853                 ret = -1;
6854                 break;
6855         default:
6856                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6857                 ret = -1;
6858                 break;
6859         }
6860
6861         return ret;
6862 }
6863
6864 /* Calculate the maximum number of contiguous PF queues that are configured */
6865 static int
6866 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6867 {
6868         struct rte_eth_dev_data *data = pf->dev_data;
6869         int i, num;
6870         struct i40e_rx_queue *rxq;
6871
6872         num = 0;
6873         for (i = 0; i < pf->lan_nb_qps; i++) {
6874                 rxq = data->rx_queues[i];
6875                 if (rxq && rxq->q_set)
6876                         num++;
6877                 else
6878                         break;
6879         }
6880
6881         return num;
6882 }
6883
6884 /* Configure RSS */
6885 static int
6886 i40e_pf_config_rss(struct i40e_pf *pf)
6887 {
6888         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6889         struct rte_eth_rss_conf rss_conf;
6890         uint32_t i, lut = 0;
6891         uint16_t j, num;
6892
6893         /*
6894          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6895          * It's necessary to calulate the actual PF queues that are configured.
6896          */
6897         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6898                 num = i40e_pf_calc_configured_queues_num(pf);
6899         else
6900                 num = pf->dev_data->nb_rx_queues;
6901
6902         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6903         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6904                         num);
6905
6906         if (num == 0) {
6907                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6908                 return -ENOTSUP;
6909         }
6910
6911         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6912                 if (j == num)
6913                         j = 0;
6914                 lut = (lut << 8) | (j & ((0x1 <<
6915                         hw->func_caps.rss_table_entry_width) - 1));
6916                 if ((i & 3) == 3)
6917                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6918         }
6919
6920         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6921         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6922                 i40e_pf_disable_rss(pf);
6923                 return 0;
6924         }
6925         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6926                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6927                 /* Random default keys */
6928                 static uint32_t rss_key_default[] = {0x6b793944,
6929                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6930                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6931                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6932
6933                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6934                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6935                                                         sizeof(uint32_t);
6936         }
6937
6938         return i40e_hw_rss_hash_set(pf, &rss_conf);
6939 }
6940
6941 static int
6942 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6943                                struct rte_eth_tunnel_filter_conf *filter)
6944 {
6945         if (pf == NULL || filter == NULL) {
6946                 PMD_DRV_LOG(ERR, "Invalid parameter");
6947                 return -EINVAL;
6948         }
6949
6950         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6951                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6952                 return -EINVAL;
6953         }
6954
6955         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6956                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6957                 return -EINVAL;
6958         }
6959
6960         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6961                 (is_zero_ether_addr(&filter->outer_mac))) {
6962                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6963                 return -EINVAL;
6964         }
6965
6966         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6967                 (is_zero_ether_addr(&filter->inner_mac))) {
6968                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6969                 return -EINVAL;
6970         }
6971
6972         return 0;
6973 }
6974
6975 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6976 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6977 static int
6978 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6979 {
6980         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
6981         uint32_t val, reg;
6982         int ret = -EINVAL;
6983
6984         if (pf->support_multi_driver) {
6985                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
6986                 return -ENOTSUP;
6987         }
6988
6989         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6990         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6991
6992         if (len == 3) {
6993                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6994         } else if (len == 4) {
6995                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6996         } else {
6997                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6998                 return ret;
6999         }
7000
7001         if (reg != val) {
7002                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7003                                                    reg, NULL);
7004                 if (ret != 0)
7005                         return ret;
7006                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
7007                             "with value 0x%08x",
7008                             I40E_GL_PRS_FVBM(2), reg);
7009                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
7010         } else {
7011                 ret = 0;
7012         }
7013         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7014                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7015
7016         return ret;
7017 }
7018
7019 static int
7020 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7021 {
7022         int ret = -EINVAL;
7023
7024         if (!hw || !cfg)
7025                 return -EINVAL;
7026
7027         switch (cfg->cfg_type) {
7028         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7029                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7030                 break;
7031         default:
7032                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7033                 break;
7034         }
7035
7036         return ret;
7037 }
7038
7039 static int
7040 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7041                                enum rte_filter_op filter_op,
7042                                void *arg)
7043 {
7044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7045         int ret = I40E_ERR_PARAM;
7046
7047         switch (filter_op) {
7048         case RTE_ETH_FILTER_SET:
7049                 ret = i40e_dev_global_config_set(hw,
7050                         (struct rte_eth_global_cfg *)arg);
7051                 break;
7052         default:
7053                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7054                 break;
7055         }
7056
7057         return ret;
7058 }
7059
7060 static int
7061 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7062                           enum rte_filter_op filter_op,
7063                           void *arg)
7064 {
7065         struct rte_eth_tunnel_filter_conf *filter;
7066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7067         int ret = I40E_SUCCESS;
7068
7069         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7070
7071         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7072                 return I40E_ERR_PARAM;
7073
7074         switch (filter_op) {
7075         case RTE_ETH_FILTER_NOP:
7076                 if (!(pf->flags & I40E_FLAG_VXLAN))
7077                         ret = I40E_NOT_SUPPORTED;
7078                 break;
7079         case RTE_ETH_FILTER_ADD:
7080                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7081                 break;
7082         case RTE_ETH_FILTER_DELETE:
7083                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7084                 break;
7085         default:
7086                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7087                 ret = I40E_ERR_PARAM;
7088                 break;
7089         }
7090
7091         return ret;
7092 }
7093
7094 static int
7095 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7096 {
7097         int ret = 0;
7098         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7099
7100         /* RSS setup */
7101         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7102                 ret = i40e_pf_config_rss(pf);
7103         else
7104                 i40e_pf_disable_rss(pf);
7105
7106         return ret;
7107 }
7108
7109 /* Get the symmetric hash enable configurations per port */
7110 static void
7111 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7112 {
7113         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7114
7115         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7116 }
7117
7118 /* Set the symmetric hash enable configurations per port */
7119 static void
7120 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7121 {
7122         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7123
7124         if (enable > 0) {
7125                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7126                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7127                                                         "been enabled");
7128                         return;
7129                 }
7130                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7131         } else {
7132                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7133                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7134                                                         "been disabled");
7135                         return;
7136                 }
7137                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7138         }
7139         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7140         I40E_WRITE_FLUSH(hw);
7141 }
7142
7143 /*
7144  * Get global configurations of hash function type and symmetric hash enable
7145  * per flow type (pctype). Note that global configuration means it affects all
7146  * the ports on the same NIC.
7147  */
7148 static int
7149 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7150                                    struct rte_eth_hash_global_conf *g_cfg)
7151 {
7152         uint32_t reg, mask = I40E_FLOW_TYPES;
7153         uint16_t i;
7154         enum i40e_filter_pctype pctype;
7155
7156         memset(g_cfg, 0, sizeof(*g_cfg));
7157         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7158         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7159                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7160         else
7161                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7162         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7163                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7164
7165         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7166                 if (!(mask & (1UL << i)))
7167                         continue;
7168                 mask &= ~(1UL << i);
7169                 /* Bit set indicats the coresponding flow type is supported */
7170                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7171                 /* if flowtype is invalid, continue */
7172                 if (!I40E_VALID_FLOW(i))
7173                         continue;
7174                 pctype = i40e_flowtype_to_pctype(i);
7175                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7176                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7177                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7178         }
7179
7180         return 0;
7181 }
7182
7183 static int
7184 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7185 {
7186         uint32_t i;
7187         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7188
7189         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7190                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7191                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7192                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7193                                                 g_cfg->hash_func);
7194                 return -EINVAL;
7195         }
7196
7197         /*
7198          * As i40e supports less than 32 flow types, only first 32 bits need to
7199          * be checked.
7200          */
7201         mask0 = g_cfg->valid_bit_mask[0];
7202         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7203                 if (i == 0) {
7204                         /* Check if any unsupported flow type configured */
7205                         if ((mask0 | i40e_mask) ^ i40e_mask)
7206                                 goto mask_err;
7207                 } else {
7208                         if (g_cfg->valid_bit_mask[i])
7209                                 goto mask_err;
7210                 }
7211         }
7212
7213         return 0;
7214
7215 mask_err:
7216         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7217
7218         return -EINVAL;
7219 }
7220
7221 /*
7222  * Set global configurations of hash function type and symmetric hash enable
7223  * per flow type (pctype). Note any modifying global configuration will affect
7224  * all the ports on the same NIC.
7225  */
7226 static int
7227 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7228                                    struct rte_eth_hash_global_conf *g_cfg)
7229 {
7230         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7231         int ret;
7232         uint16_t i;
7233         uint32_t reg;
7234         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7235         enum i40e_filter_pctype pctype;
7236
7237         if (pf->support_multi_driver) {
7238                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
7239                 return -ENOTSUP;
7240         }
7241
7242         /* Check the input parameters */
7243         ret = i40e_hash_global_config_check(g_cfg);
7244         if (ret < 0)
7245                 return ret;
7246
7247         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7248                 if (!(mask0 & (1UL << i)))
7249                         continue;
7250                 mask0 &= ~(1UL << i);
7251                 /* if flowtype is invalid, continue */
7252                 if (!I40E_VALID_FLOW(i))
7253                         continue;
7254                 pctype = i40e_flowtype_to_pctype(i);
7255                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7256                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7257                 if (hw->mac.type == I40E_MAC_X722) {
7258                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7259                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7260                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7261                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7262                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7263                                   reg);
7264                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7265                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7266                                   reg);
7267                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7268                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7269                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7270                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7271                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7272                                   reg);
7273                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7274                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7275                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7276                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7277                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7278                                   reg);
7279                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7280                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7281                                   reg);
7282                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7283                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7284                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7285                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7286                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7287                                   reg);
7288                         } else {
7289                                 i40e_write_global_rx_ctl(hw,
7290                                                          I40E_GLQF_HSYM(pctype),
7291                                                          reg);
7292                         }
7293                 } else {
7294                         i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7295                                                  reg);
7296                 }
7297                 i40e_global_cfg_warning(I40E_WARNING_HSYM);
7298         }
7299
7300         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7301         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7302                 /* Toeplitz */
7303                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7304                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7305                                                                 "Toeplitz");
7306                         goto out;
7307                 }
7308                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7309         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7310                 /* Simple XOR */
7311                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7312                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7313                                                         "Simple XOR");
7314                         goto out;
7315                 }
7316                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7317         } else
7318                 /* Use the default, and keep it as it is */
7319                 goto out;
7320
7321         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
7322         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
7323
7324 out:
7325         I40E_WRITE_FLUSH(hw);
7326
7327         return 0;
7328 }
7329
7330 /**
7331  * Valid input sets for hash and flow director filters per PCTYPE
7332  */
7333 static uint64_t
7334 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7335                 enum rte_filter_type filter)
7336 {
7337         uint64_t valid;
7338
7339         static const uint64_t valid_hash_inset_table[] = {
7340                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7341                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7342                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7343                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7344                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7345                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7346                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7347                         I40E_INSET_FLEX_PAYLOAD,
7348                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7349                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7350                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7351                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7352                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7353                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7354                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7355                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7356                         I40E_INSET_FLEX_PAYLOAD,
7357 #ifdef X722_SUPPORT
7358                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7359                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7360                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7361                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7362                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7363                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7364                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7365                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7366                         I40E_INSET_FLEX_PAYLOAD,
7367                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7368                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7369                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7370                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7371                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7372                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7373                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7374                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7375                         I40E_INSET_FLEX_PAYLOAD,
7376 #endif
7377                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7378                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7379                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7380                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7381                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7382                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7383                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7384                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7385                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7386 #ifdef X722_SUPPORT
7387                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7388                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7389                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7390                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7391                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7392                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7393                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7394                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7395                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7396 #endif
7397                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7398                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7399                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7400                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7401                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7402                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7403                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7404                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7405                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7406                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7407                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7408                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7409                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7410                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7411                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7412                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7413                         I40E_INSET_FLEX_PAYLOAD,
7414                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7415                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7416                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7417                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7418                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7419                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7420                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7421                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7422                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7423                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7424                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7425                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7426                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7427                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7428                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7429                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7430 #ifdef X722_SUPPORT
7431                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7432                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7433                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7434                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7435                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7436                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7437                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7438                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7439                         I40E_INSET_FLEX_PAYLOAD,
7440                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7441                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7442                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7443                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7444                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7445                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7446                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7447                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7448                         I40E_INSET_FLEX_PAYLOAD,
7449 #endif
7450                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7451                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7452                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7453                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7454                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7455                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7456                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7457                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7458                         I40E_INSET_FLEX_PAYLOAD,
7459 #ifdef X722_SUPPORT
7460                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7461                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7462                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7463                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7464                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7465                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7466                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7467                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7468                         I40E_INSET_FLEX_PAYLOAD,
7469 #endif
7470                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7471                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7472                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7473                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7474                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7475                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7476                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7477                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7478                         I40E_INSET_FLEX_PAYLOAD,
7479                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7480                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7481                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7482                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7483                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7484                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7485                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7486                         I40E_INSET_FLEX_PAYLOAD,
7487                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7488                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7489                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7490                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7491                         I40E_INSET_FLEX_PAYLOAD,
7492         };
7493
7494         /**
7495          * Flow director supports only fields defined in
7496          * union rte_eth_fdir_flow.
7497          */
7498         static const uint64_t valid_fdir_inset_table[] = {
7499                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7500                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7501                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7502                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7503                 I40E_INSET_IPV4_TTL,
7504                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7505                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7506                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7507                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7508                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7509 #ifdef X722_SUPPORT
7510                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7511                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7512                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7513                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7514                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7515                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7516                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7517                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7518                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7519                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7520 #endif
7521                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7522                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7523                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7524                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7525                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7526 #ifdef X722_SUPPORT
7527                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7528                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7529                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7530                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7531                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7532 #endif
7533                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7534                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7535                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7536                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7537                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7538                 I40E_INSET_SCTP_VT,
7539                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7540                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7541                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7542                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7543                 I40E_INSET_IPV4_TTL,
7544                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7545                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7546                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7547                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7548                 I40E_INSET_IPV6_HOP_LIMIT,
7549                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7550                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7551                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7552                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7553                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7554 #ifdef X722_SUPPORT
7555                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7556                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7557                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7558                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7559                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7560                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7561                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7562                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7563                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7564                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7565 #endif
7566                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7567                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7568                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7569                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7570                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7571 #ifdef X722_SUPPORT
7572                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7573                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7574                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7575                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7576                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7577 #endif
7578                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7579                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7580                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7581                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7582                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7583                 I40E_INSET_SCTP_VT,
7584                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7585                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7586                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7587                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7588                 I40E_INSET_IPV6_HOP_LIMIT,
7589                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7590                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7591                 I40E_INSET_LAST_ETHER_TYPE,
7592         };
7593
7594         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7595                 return 0;
7596         if (filter == RTE_ETH_FILTER_HASH)
7597                 valid = valid_hash_inset_table[pctype];
7598         else
7599                 valid = valid_fdir_inset_table[pctype];
7600
7601         return valid;
7602 }
7603
7604 /**
7605  * Validate if the input set is allowed for a specific PCTYPE
7606  */
7607 static int
7608 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7609                 enum rte_filter_type filter, uint64_t inset)
7610 {
7611         uint64_t valid;
7612
7613         valid = i40e_get_valid_input_set(pctype, filter);
7614         if (inset & (~valid))
7615                 return -EINVAL;
7616
7617         return 0;
7618 }
7619
7620 /* default input set fields combination per pctype */
7621 static uint64_t
7622 i40e_get_default_input_set(uint16_t pctype)
7623 {
7624         static const uint64_t default_inset_table[] = {
7625                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7626                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7627                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7628                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7629                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7630 #ifdef X722_SUPPORT
7631                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7632                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7633                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7634                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7635                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7636                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7637 #endif
7638                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7639                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7640                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7641 #ifdef X722_SUPPORT
7642                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7643                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7644                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7645 #endif
7646                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7647                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7648                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7649                         I40E_INSET_SCTP_VT,
7650                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7651                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7652                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7653                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7654                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7655                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7656                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7657 #ifdef X722_SUPPORT
7658                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7659                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7660                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7661                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7662                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7663                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7664 #endif
7665                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7666                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7667                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7668 #ifdef X722_SUPPORT
7669                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7670                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7671                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7672 #endif
7673                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7674                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7675                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7676                         I40E_INSET_SCTP_VT,
7677                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7678                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7679                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7680                         I40E_INSET_LAST_ETHER_TYPE,
7681         };
7682
7683         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7684                 return 0;
7685
7686         return default_inset_table[pctype];
7687 }
7688
7689 /**
7690  * Parse the input set from index to logical bit masks
7691  */
7692 static int
7693 i40e_parse_input_set(uint64_t *inset,
7694                      enum i40e_filter_pctype pctype,
7695                      enum rte_eth_input_set_field *field,
7696                      uint16_t size)
7697 {
7698         uint16_t i, j;
7699         int ret = -EINVAL;
7700
7701         static const struct {
7702                 enum rte_eth_input_set_field field;
7703                 uint64_t inset;
7704         } inset_convert_table[] = {
7705                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7706                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7707                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7708                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7709                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7710                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7711                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7712                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7713                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7714                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7715                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7716                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7717                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7718                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7719                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7720                         I40E_INSET_IPV6_NEXT_HDR},
7721                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7722                         I40E_INSET_IPV6_HOP_LIMIT},
7723                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7724                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7725                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7726                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7727                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7728                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7729                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7730                         I40E_INSET_SCTP_VT},
7731                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7732                         I40E_INSET_TUNNEL_DMAC},
7733                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7734                         I40E_INSET_VLAN_TUNNEL},
7735                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7736                         I40E_INSET_TUNNEL_ID},
7737                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7738                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7739                         I40E_INSET_FLEX_PAYLOAD_W1},
7740                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7741                         I40E_INSET_FLEX_PAYLOAD_W2},
7742                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7743                         I40E_INSET_FLEX_PAYLOAD_W3},
7744                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7745                         I40E_INSET_FLEX_PAYLOAD_W4},
7746                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7747                         I40E_INSET_FLEX_PAYLOAD_W5},
7748                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7749                         I40E_INSET_FLEX_PAYLOAD_W6},
7750                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7751                         I40E_INSET_FLEX_PAYLOAD_W7},
7752                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7753                         I40E_INSET_FLEX_PAYLOAD_W8},
7754         };
7755
7756         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7757                 return ret;
7758
7759         /* Only one item allowed for default or all */
7760         if (size == 1) {
7761                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7762                         *inset = i40e_get_default_input_set(pctype);
7763                         return 0;
7764                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7765                         *inset = I40E_INSET_NONE;
7766                         return 0;
7767                 }
7768         }
7769
7770         for (i = 0, *inset = 0; i < size; i++) {
7771                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7772                         if (field[i] == inset_convert_table[j].field) {
7773                                 *inset |= inset_convert_table[j].inset;
7774                                 break;
7775                         }
7776                 }
7777
7778                 /* It contains unsupported input set, return immediately */
7779                 if (j == RTE_DIM(inset_convert_table))
7780                         return ret;
7781         }
7782
7783         return 0;
7784 }
7785
7786 /**
7787  * Translate the input set from bit masks to register aware bit masks
7788  * and vice versa
7789  */
7790 static uint64_t
7791 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7792 {
7793         uint64_t val = 0;
7794         uint16_t i;
7795
7796         struct inset_map {
7797                 uint64_t inset;
7798                 uint64_t inset_reg;
7799         };
7800
7801         static const struct inset_map inset_map_common[] = {
7802                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7803                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7804                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7805                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7806                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7807                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7808                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7809                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7810                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7811                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7812                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7813                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7814                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7815                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7816                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7817                 {I40E_INSET_TUNNEL_DMAC,
7818                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7819                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7820                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7821                 {I40E_INSET_TUNNEL_SRC_PORT,
7822                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7823                 {I40E_INSET_TUNNEL_DST_PORT,
7824                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7825                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7826                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7827                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7828                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7829                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7830                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7831                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7832                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7833                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7834         };
7835
7836     /* some different registers map in x722*/
7837         static const struct inset_map inset_map_diff_x722[] = {
7838                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7839                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7840                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7841                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7842         };
7843
7844         static const struct inset_map inset_map_diff_not_x722[] = {
7845                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7846                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7847                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7848                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7849         };
7850
7851         if (input == 0)
7852                 return val;
7853
7854         /* Translate input set to register aware inset */
7855         if (type == I40E_MAC_X722) {
7856                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7857                         if (input & inset_map_diff_x722[i].inset)
7858                                 val |= inset_map_diff_x722[i].inset_reg;
7859                 }
7860         } else {
7861                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7862                         if (input & inset_map_diff_not_x722[i].inset)
7863                                 val |= inset_map_diff_not_x722[i].inset_reg;
7864                 }
7865         }
7866
7867         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7868                 if (input & inset_map_common[i].inset)
7869                         val |= inset_map_common[i].inset_reg;
7870         }
7871
7872         return val;
7873 }
7874
7875 static int
7876 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7877 {
7878         uint8_t i, idx = 0;
7879         uint64_t inset_need_mask = inset;
7880
7881         static const struct {
7882                 uint64_t inset;
7883                 uint32_t mask;
7884         } inset_mask_map[] = {
7885                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7886                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7887                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7888                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7889                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7890                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7891                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7892                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7893         };
7894
7895         if (!inset || !mask || !nb_elem)
7896                 return 0;
7897
7898         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7899                 /* Clear the inset bit, if no MASK is required,
7900                  * for example proto + ttl
7901                  */
7902                 if ((inset & inset_mask_map[i].inset) ==
7903                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7904                         inset_need_mask &= ~inset_mask_map[i].inset;
7905                 if (!inset_need_mask)
7906                         return 0;
7907         }
7908         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7909                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7910                     inset_mask_map[i].inset) {
7911                         if (idx >= nb_elem) {
7912                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7913                                 return -EINVAL;
7914                         }
7915                         mask[idx] = inset_mask_map[i].mask;
7916                         idx++;
7917                 }
7918         }
7919
7920         return idx;
7921 }
7922
7923 static void
7924 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7925 {
7926         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7927
7928         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7929         if (reg != val)
7930                 i40e_write_rx_ctl(hw, addr, val);
7931         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7932                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7933 }
7934
7935 static void
7936 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7937 {
7938         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7939
7940         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
7941         if (reg != val)
7942                 i40e_write_global_rx_ctl(hw, addr, val);
7943         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
7944                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7945 }
7946
7947 static void
7948 i40e_filter_input_set_init(struct i40e_pf *pf)
7949 {
7950         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7951         enum i40e_filter_pctype pctype;
7952         uint64_t input_set, inset_reg;
7953         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7954         int num, i;
7955
7956         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7957              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7958                 if (hw->mac.type == I40E_MAC_X722) {
7959                         if (!I40E_VALID_PCTYPE_X722(pctype))
7960                                 continue;
7961                 } else {
7962                         if (!I40E_VALID_PCTYPE(pctype))
7963                                 continue;
7964                 }
7965
7966                 input_set = i40e_get_default_input_set(pctype);
7967
7968                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7969                                                    I40E_INSET_MASK_NUM_REG);
7970                 if (num < 0)
7971                         return;
7972
7973                 if (pf->support_multi_driver && num > 0) {
7974                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
7975                         return;
7976                 }
7977
7978                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7979                                         input_set);
7980
7981                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7982                                       (uint32_t)(inset_reg & UINT32_MAX));
7983                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7984                                      (uint32_t)((inset_reg >>
7985                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7986                 if (!pf->support_multi_driver) {
7987                         i40e_check_write_global_reg(hw,
7988                                             I40E_GLQF_HASH_INSET(0, pctype),
7989                                             (uint32_t)(inset_reg & UINT32_MAX));
7990                         i40e_check_write_global_reg(hw,
7991                                             I40E_GLQF_HASH_INSET(1, pctype),
7992                                             (uint32_t)((inset_reg >>
7993                                             I40E_32_BIT_WIDTH) & UINT32_MAX));
7994
7995                         for (i = 0; i < num; i++) {
7996                                 i40e_check_write_global_reg(hw,
7997                                                     I40E_GLQF_FD_MSK(i, pctype),
7998                                                     mask_reg[i]);
7999                                 i40e_check_write_global_reg(hw,
8000                                                   I40E_GLQF_HASH_MSK(i, pctype),
8001                                                   mask_reg[i]);
8002                         }
8003                         /*clear unused mask registers of the pctype */
8004                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8005                                 i40e_check_write_global_reg(hw,
8006                                                     I40E_GLQF_FD_MSK(i, pctype),
8007                                                     0);
8008                                 i40e_check_write_global_reg(hw,
8009                                                   I40E_GLQF_HASH_MSK(i, pctype),
8010                                                     0);
8011                         }
8012                 } else {
8013                         PMD_DRV_LOG(ERR,
8014                                     "Input set setting is not supported.");
8015                 }
8016                 I40E_WRITE_FLUSH(hw);
8017
8018                 /* store the default input set */
8019                 if (!pf->support_multi_driver)
8020                         pf->hash_input_set[pctype] = input_set;
8021                 pf->fdir.input_set[pctype] = input_set;
8022         }
8023
8024         if (!pf->support_multi_driver) {
8025                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
8026                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
8027                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
8028         }
8029 }
8030
8031 int
8032 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8033                          struct rte_eth_input_set_conf *conf)
8034 {
8035         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8036         enum i40e_filter_pctype pctype;
8037         uint64_t input_set, inset_reg = 0;
8038         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8039         int ret, i, num;
8040
8041         if (pf->support_multi_driver) {
8042                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
8043                 return -ENOTSUP;
8044         }
8045
8046         if (!conf) {
8047                 PMD_DRV_LOG(ERR, "Invalid pointer");
8048                 return -EFAULT;
8049         }
8050         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8051             conf->op != RTE_ETH_INPUT_SET_ADD) {
8052                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8053                 return -EINVAL;
8054         }
8055
8056         if (!I40E_VALID_FLOW(conf->flow_type)) {
8057                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8058                 return -EINVAL;
8059         }
8060
8061         if (hw->mac.type == I40E_MAC_X722) {
8062                 /* get translated pctype value in fd pctype register */
8063                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8064                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8065                         conf->flow_type)));
8066         } else
8067                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8068
8069         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8070                                    conf->inset_size);
8071         if (ret) {
8072                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8073                 return -EINVAL;
8074         }
8075         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8076                                     input_set) != 0) {
8077                 PMD_DRV_LOG(ERR, "Invalid input set");
8078                 return -EINVAL;
8079         }
8080         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8081                 /* get inset value in register */
8082                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8083                 inset_reg <<= I40E_32_BIT_WIDTH;
8084                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8085                 input_set |= pf->hash_input_set[pctype];
8086         }
8087         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8088                                            I40E_INSET_MASK_NUM_REG);
8089         if (num < 0)
8090                 return -EINVAL;
8091
8092         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8093
8094         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8095                                     (uint32_t)(inset_reg & UINT32_MAX));
8096         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8097                                     (uint32_t)((inset_reg >>
8098                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
8099         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
8100
8101         for (i = 0; i < num; i++)
8102                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8103                                             mask_reg[i]);
8104         /*clear unused mask registers of the pctype */
8105         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8106                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8107                                             0);
8108         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
8109         I40E_WRITE_FLUSH(hw);
8110
8111         pf->hash_input_set[pctype] = input_set;
8112         return 0;
8113 }
8114
8115 int
8116 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8117                          struct rte_eth_input_set_conf *conf)
8118 {
8119         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8120         enum i40e_filter_pctype pctype;
8121         uint64_t input_set, inset_reg = 0;
8122         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8123         int ret, i, num;
8124
8125         if (!hw || !conf) {
8126                 PMD_DRV_LOG(ERR, "Invalid pointer");
8127                 return -EFAULT;
8128         }
8129         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8130             conf->op != RTE_ETH_INPUT_SET_ADD) {
8131                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8132                 return -EINVAL;
8133         }
8134
8135         if (!I40E_VALID_FLOW(conf->flow_type)) {
8136                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8137                 return -EINVAL;
8138         }
8139
8140         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8141
8142         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8143                                    conf->inset_size);
8144         if (ret) {
8145                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8146                 return -EINVAL;
8147         }
8148         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8149                                     input_set) != 0) {
8150                 PMD_DRV_LOG(ERR, "Invalid input set");
8151                 return -EINVAL;
8152         }
8153
8154         /* get inset value in register */
8155         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8156         inset_reg <<= I40E_32_BIT_WIDTH;
8157         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8158
8159         /* Can not change the inset reg for flex payload for fdir,
8160          * it is done by writing I40E_PRTQF_FD_FLXINSET
8161          * in i40e_set_flex_mask_on_pctype.
8162          */
8163         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8164                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8165         else
8166                 input_set |= pf->fdir.input_set[pctype];
8167         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8168                                            I40E_INSET_MASK_NUM_REG);
8169         if (num < 0)
8170                 return -EINVAL;
8171
8172         if (pf->support_multi_driver && num > 0) {
8173                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
8174                 return -ENOTSUP;
8175         }
8176
8177         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8178
8179         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8180                               (uint32_t)(inset_reg & UINT32_MAX));
8181         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8182                              (uint32_t)((inset_reg >>
8183                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8184
8185         if (!pf->support_multi_driver) {
8186                 for (i = 0; i < num; i++)
8187                         i40e_check_write_global_reg(hw,
8188                                                     I40E_GLQF_FD_MSK(i, pctype),
8189                                                     mask_reg[i]);
8190                 /*clear unused mask registers of the pctype */
8191                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8192                         i40e_check_write_global_reg(hw,
8193                                                     I40E_GLQF_FD_MSK(i, pctype),
8194                                                     0);
8195                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
8196         } else {
8197                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
8198         }
8199         I40E_WRITE_FLUSH(hw);
8200
8201         pf->fdir.input_set[pctype] = input_set;
8202         return 0;
8203 }
8204
8205 static int
8206 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8207 {
8208         int ret = 0;
8209
8210         if (!hw || !info) {
8211                 PMD_DRV_LOG(ERR, "Invalid pointer");
8212                 return -EFAULT;
8213         }
8214
8215         switch (info->info_type) {
8216         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8217                 i40e_get_symmetric_hash_enable_per_port(hw,
8218                                         &(info->info.enable));
8219                 break;
8220         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8221                 ret = i40e_get_hash_filter_global_config(hw,
8222                                 &(info->info.global_conf));
8223                 break;
8224         default:
8225                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8226                                                         info->info_type);
8227                 ret = -EINVAL;
8228                 break;
8229         }
8230
8231         return ret;
8232 }
8233
8234 static int
8235 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8236 {
8237         int ret = 0;
8238
8239         if (!hw || !info) {
8240                 PMD_DRV_LOG(ERR, "Invalid pointer");
8241                 return -EFAULT;
8242         }
8243
8244         switch (info->info_type) {
8245         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8246                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8247                 break;
8248         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8249                 ret = i40e_set_hash_filter_global_config(hw,
8250                                 &(info->info.global_conf));
8251                 break;
8252         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8253                 ret = i40e_hash_filter_inset_select(hw,
8254                                                &(info->info.input_set_conf));
8255                 break;
8256
8257         default:
8258                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8259                                                         info->info_type);
8260                 ret = -EINVAL;
8261                 break;
8262         }
8263
8264         return ret;
8265 }
8266
8267 /* Operations for hash function */
8268 static int
8269 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8270                       enum rte_filter_op filter_op,
8271                       void *arg)
8272 {
8273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8274         int ret = 0;
8275
8276         switch (filter_op) {
8277         case RTE_ETH_FILTER_NOP:
8278                 break;
8279         case RTE_ETH_FILTER_GET:
8280                 ret = i40e_hash_filter_get(hw,
8281                         (struct rte_eth_hash_filter_info *)arg);
8282                 break;
8283         case RTE_ETH_FILTER_SET:
8284                 ret = i40e_hash_filter_set(hw,
8285                         (struct rte_eth_hash_filter_info *)arg);
8286                 break;
8287         default:
8288                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8289                                                                 filter_op);
8290                 ret = -ENOTSUP;
8291                 break;
8292         }
8293
8294         return ret;
8295 }
8296
8297 /*
8298  * Configure ethertype filter, which can director packet by filtering
8299  * with mac address and ether_type or only ether_type
8300  */
8301 static int
8302 i40e_ethertype_filter_set(struct i40e_pf *pf,
8303                         struct rte_eth_ethertype_filter *filter,
8304                         bool add)
8305 {
8306         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8307         struct i40e_control_filter_stats stats;
8308         uint16_t flags = 0;
8309         int ret;
8310
8311         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8312                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8313                 return -EINVAL;
8314         }
8315         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8316                 filter->ether_type == ETHER_TYPE_IPv6) {
8317                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8318                         " control packet filter.", filter->ether_type);
8319                 return -EINVAL;
8320         }
8321         if (filter->ether_type == ETHER_TYPE_VLAN)
8322                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8323                         " not supported.");
8324
8325         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8326                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8327         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8328                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8329         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8330
8331         memset(&stats, 0, sizeof(stats));
8332         ret = i40e_aq_add_rem_control_packet_filter(hw,
8333                         filter->mac_addr.addr_bytes,
8334                         filter->ether_type, flags,
8335                         pf->main_vsi->seid,
8336                         filter->queue, add, &stats, NULL);
8337
8338         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8339                          " mac_etype_used = %u, etype_used = %u,"
8340                          " mac_etype_free = %u, etype_free = %u\n",
8341                          ret, stats.mac_etype_used, stats.etype_used,
8342                          stats.mac_etype_free, stats.etype_free);
8343         if (ret < 0)
8344                 return -ENOSYS;
8345         return 0;
8346 }
8347
8348 /*
8349  * Handle operations for ethertype filter.
8350  */
8351 static int
8352 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8353                                 enum rte_filter_op filter_op,
8354                                 void *arg)
8355 {
8356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8357         int ret = 0;
8358
8359         if (filter_op == RTE_ETH_FILTER_NOP)
8360                 return ret;
8361
8362         if (arg == NULL) {
8363                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8364                             filter_op);
8365                 return -EINVAL;
8366         }
8367
8368         switch (filter_op) {
8369         case RTE_ETH_FILTER_ADD:
8370                 ret = i40e_ethertype_filter_set(pf,
8371                         (struct rte_eth_ethertype_filter *)arg,
8372                         TRUE);
8373                 break;
8374         case RTE_ETH_FILTER_DELETE:
8375                 ret = i40e_ethertype_filter_set(pf,
8376                         (struct rte_eth_ethertype_filter *)arg,
8377                         FALSE);
8378                 break;
8379         default:
8380                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8381                 ret = -ENOSYS;
8382                 break;
8383         }
8384         return ret;
8385 }
8386
8387 static int
8388 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8389                      enum rte_filter_type filter_type,
8390                      enum rte_filter_op filter_op,
8391                      void *arg)
8392 {
8393         int ret = 0;
8394
8395         if (dev == NULL)
8396                 return -EINVAL;
8397
8398         switch (filter_type) {
8399         case RTE_ETH_FILTER_NONE:
8400                 /* For global configuration */
8401                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8402                 break;
8403         case RTE_ETH_FILTER_HASH:
8404                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8405                 break;
8406         case RTE_ETH_FILTER_MACVLAN:
8407                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8408                 break;
8409         case RTE_ETH_FILTER_ETHERTYPE:
8410                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8411                 break;
8412         case RTE_ETH_FILTER_TUNNEL:
8413                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8414                 break;
8415         case RTE_ETH_FILTER_FDIR:
8416                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8417                 break;
8418         default:
8419                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8420                                                         filter_type);
8421                 ret = -EINVAL;
8422                 break;
8423         }
8424
8425         return ret;
8426 }
8427
8428 /*
8429  * Check and enable Extended Tag.
8430  * Enabling Extended Tag is important for 40G performance.
8431  */
8432 static void
8433 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8434 {
8435         uint32_t buf = 0;
8436         int ret;
8437
8438         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8439                                       PCI_DEV_CAP_REG);
8440         if (ret < 0) {
8441                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8442                             PCI_DEV_CAP_REG);
8443                 return;
8444         }
8445         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8446                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8447                 return;
8448         }
8449
8450         buf = 0;
8451         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8452                                       PCI_DEV_CTRL_REG);
8453         if (ret < 0) {
8454                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8455                             PCI_DEV_CTRL_REG);
8456                 return;
8457         }
8458         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8459                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8460                 return;
8461         }
8462         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8463         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8464                                        PCI_DEV_CTRL_REG);
8465         if (ret < 0) {
8466                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8467                             PCI_DEV_CTRL_REG);
8468                 return;
8469         }
8470 }
8471
8472 /*
8473  * As some registers wouldn't be reset unless a global hardware reset,
8474  * hardware initialization is needed to put those registers into an
8475  * expected initial state.
8476  */
8477 static void
8478 i40e_hw_init(struct rte_eth_dev *dev)
8479 {
8480         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8481
8482         i40e_enable_extended_tag(dev);
8483
8484         /* clear the PF Queue Filter control register */
8485         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8486
8487         /* Disable symmetric hash per port */
8488         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8489 }
8490
8491 enum i40e_filter_pctype
8492 i40e_flowtype_to_pctype(uint16_t flow_type)
8493 {
8494         static const enum i40e_filter_pctype pctype_table[] = {
8495                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8496                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8497                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8498                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8499                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8500                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8501                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8502                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8503                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8504                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8505                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8506                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8507                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8508                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8509                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8510                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8511                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8512                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8513                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8514         };
8515
8516         return pctype_table[flow_type];
8517 }
8518
8519 uint16_t
8520 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8521 {
8522         static const uint16_t flowtype_table[] = {
8523                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8524                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8525                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8526 #ifdef X722_SUPPORT
8527                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8528                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8529                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8530                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8531 #endif
8532                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8533                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8534 #ifdef X722_SUPPORT
8535                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8536                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8537 #endif
8538                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8539                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8540                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8541                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8542                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8543                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8544                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8545 #ifdef X722_SUPPORT
8546                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8547                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8548                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8549                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8550 #endif
8551                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8552                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8553 #ifdef X722_SUPPORT
8554                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8555                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8556 #endif
8557                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8558                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8559                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8560                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8561                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8562         };
8563
8564         return flowtype_table[pctype];
8565 }
8566
8567 /*
8568  * On X710, performance number is far from the expectation on recent firmware
8569  * versions; on XL710, performance number is also far from the expectation on
8570  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8571  * mode is enabled and port MAC address is equal to the packet destination MAC
8572  * address. The fix for this issue may not be integrated in the following
8573  * firmware version. So the workaround in software driver is needed. It needs
8574  * to modify the initial values of 3 internal only registers for both X710 and
8575  * XL710. Note that the values for X710 or XL710 could be different, and the
8576  * workaround can be removed when it is fixed in firmware in the future.
8577  */
8578
8579 /* For both X710 and XL710 */
8580 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
8581 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
8582 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
8583
8584 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8585 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8586
8587 /* For X722 */
8588 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8589 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8590
8591 /* For X710 */
8592 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8593 /* For XL710 */
8594 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8595 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8596
8597 static int
8598 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8599 {
8600         enum i40e_status_code status;
8601         struct i40e_aq_get_phy_abilities_resp phy_ab;
8602         int ret = -ENOTSUP;
8603
8604         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8605                                               NULL);
8606
8607         if (status)
8608                 return ret;
8609
8610         return 0;
8611 }
8612
8613 static void
8614 i40e_configure_registers(struct i40e_hw *hw)
8615 {
8616         static struct {
8617                 uint32_t addr;
8618                 uint64_t val;
8619         } reg_table[] = {
8620                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8621                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8622                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8623         };
8624         uint64_t reg;
8625         uint32_t i;
8626         int ret;
8627
8628         for (i = 0; i < RTE_DIM(reg_table); i++) {
8629                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8630                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8631                                 reg_table[i].val =
8632                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8633                         else /* For X710/XL710/XXV710 */
8634                                 if (hw->aq.fw_maj_ver < 6)
8635                                         reg_table[i].val =
8636                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
8637                                 else
8638                                         reg_table[i].val =
8639                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
8640                 }
8641
8642                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8643                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8644                                 reg_table[i].val =
8645                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8646                         else /* For X710/XL710/XXV710 */
8647                                 reg_table[i].val =
8648                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8649                 }
8650
8651                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8652                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8653                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8654                                 reg_table[i].val =
8655                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8656                         else /* For X710 */
8657                                 reg_table[i].val =
8658                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8659                 }
8660
8661                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8662                                                         &reg, NULL);
8663                 if (ret < 0) {
8664                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8665                                                         reg_table[i].addr);
8666                         break;
8667                 }
8668                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8669                                                 reg_table[i].addr, reg);
8670                 if (reg == reg_table[i].val)
8671                         continue;
8672
8673                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8674                                                 reg_table[i].val, NULL);
8675                 if (ret < 0) {
8676                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8677                                 "address of 0x%"PRIx32, reg_table[i].val,
8678                                                         reg_table[i].addr);
8679                         break;
8680                 }
8681                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8682                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8683         }
8684 }
8685
8686 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8687 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8688 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8689 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8690 static int
8691 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8692 {
8693         uint32_t reg;
8694         int ret;
8695
8696         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8697                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8698                 return -EINVAL;
8699         }
8700
8701         /* Configure for double VLAN RX stripping */
8702         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8703         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8704                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8705                 ret = i40e_aq_debug_write_register(hw,
8706                                                    I40E_VSI_TSR(vsi->vsi_id),
8707                                                    reg, NULL);
8708                 if (ret < 0) {
8709                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8710                                     vsi->vsi_id);
8711                         return I40E_ERR_CONFIG;
8712                 }
8713         }
8714
8715         /* Configure for double VLAN TX insertion */
8716         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8717         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8718                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8719                 ret = i40e_aq_debug_write_register(hw,
8720                                                    I40E_VSI_L2TAGSTXVALID(
8721                                                    vsi->vsi_id), reg, NULL);
8722                 if (ret < 0) {
8723                         PMD_DRV_LOG(ERR, "Failed to update "
8724                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8725                         return I40E_ERR_CONFIG;
8726                 }
8727         }
8728
8729         return 0;
8730 }
8731
8732 /**
8733  * i40e_aq_add_mirror_rule
8734  * @hw: pointer to the hardware structure
8735  * @seid: VEB seid to add mirror rule to
8736  * @dst_id: destination vsi seid
8737  * @entries: Buffer which contains the entities to be mirrored
8738  * @count: number of entities contained in the buffer
8739  * @rule_id:the rule_id of the rule to be added
8740  *
8741  * Add a mirror rule for a given veb.
8742  *
8743  **/
8744 static enum i40e_status_code
8745 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8746                         uint16_t seid, uint16_t dst_id,
8747                         uint16_t rule_type, uint16_t *entries,
8748                         uint16_t count, uint16_t *rule_id)
8749 {
8750         struct i40e_aq_desc desc;
8751         struct i40e_aqc_add_delete_mirror_rule cmd;
8752         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8753                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8754                 &desc.params.raw;
8755         uint16_t buff_len;
8756         enum i40e_status_code status;
8757
8758         i40e_fill_default_direct_cmd_desc(&desc,
8759                                           i40e_aqc_opc_add_mirror_rule);
8760         memset(&cmd, 0, sizeof(cmd));
8761
8762         buff_len = sizeof(uint16_t) * count;
8763         desc.datalen = rte_cpu_to_le_16(buff_len);
8764         if (buff_len > 0)
8765                 desc.flags |= rte_cpu_to_le_16(
8766                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8767         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8768                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8769         cmd.num_entries = rte_cpu_to_le_16(count);
8770         cmd.seid = rte_cpu_to_le_16(seid);
8771         cmd.destination = rte_cpu_to_le_16(dst_id);
8772
8773         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8774         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8775         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8776                          "rule_id = %u"
8777                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8778                          hw->aq.asq_last_status, resp->rule_id,
8779                          resp->mirror_rules_used, resp->mirror_rules_free);
8780         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8781
8782         return status;
8783 }
8784
8785 /**
8786  * i40e_aq_del_mirror_rule
8787  * @hw: pointer to the hardware structure
8788  * @seid: VEB seid to add mirror rule to
8789  * @entries: Buffer which contains the entities to be mirrored
8790  * @count: number of entities contained in the buffer
8791  * @rule_id:the rule_id of the rule to be delete
8792  *
8793  * Delete a mirror rule for a given veb.
8794  *
8795  **/
8796 static enum i40e_status_code
8797 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8798                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8799                 uint16_t count, uint16_t rule_id)
8800 {
8801         struct i40e_aq_desc desc;
8802         struct i40e_aqc_add_delete_mirror_rule cmd;
8803         uint16_t buff_len = 0;
8804         enum i40e_status_code status;
8805         void *buff = NULL;
8806
8807         i40e_fill_default_direct_cmd_desc(&desc,
8808                                           i40e_aqc_opc_delete_mirror_rule);
8809         memset(&cmd, 0, sizeof(cmd));
8810         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8811                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8812                                                           I40E_AQ_FLAG_RD));
8813                 cmd.num_entries = count;
8814                 buff_len = sizeof(uint16_t) * count;
8815                 desc.datalen = rte_cpu_to_le_16(buff_len);
8816                 buff = (void *)entries;
8817         } else
8818                 /* rule id is filled in destination field for deleting mirror rule */
8819                 cmd.destination = rte_cpu_to_le_16(rule_id);
8820
8821         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8822                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8823         cmd.seid = rte_cpu_to_le_16(seid);
8824
8825         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8826         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8827
8828         return status;
8829 }
8830
8831 /**
8832  * i40e_mirror_rule_set
8833  * @dev: pointer to the hardware structure
8834  * @mirror_conf: mirror rule info
8835  * @sw_id: mirror rule's sw_id
8836  * @on: enable/disable
8837  *
8838  * set a mirror rule.
8839  *
8840  **/
8841 static int
8842 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8843                         struct rte_eth_mirror_conf *mirror_conf,
8844                         uint8_t sw_id, uint8_t on)
8845 {
8846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8848         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8849         struct i40e_mirror_rule *parent = NULL;
8850         uint16_t seid, dst_seid, rule_id;
8851         uint16_t i, j = 0;
8852         int ret;
8853
8854         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8855
8856         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8857                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8858                         " without veb or vfs.");
8859                 return -ENOSYS;
8860         }
8861         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8862                 PMD_DRV_LOG(ERR, "mirror table is full.");
8863                 return -ENOSPC;
8864         }
8865         if (mirror_conf->dst_pool > pf->vf_num) {
8866                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8867                                  mirror_conf->dst_pool);
8868                 return -EINVAL;
8869         }
8870
8871         seid = pf->main_vsi->veb->seid;
8872
8873         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8874                 if (sw_id <= it->index) {
8875                         mirr_rule = it;
8876                         break;
8877                 }
8878                 parent = it;
8879         }
8880         if (mirr_rule && sw_id == mirr_rule->index) {
8881                 if (on) {
8882                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8883                         return -EEXIST;
8884                 } else {
8885                         ret = i40e_aq_del_mirror_rule(hw, seid,
8886                                         mirr_rule->rule_type,
8887                                         mirr_rule->entries,
8888                                         mirr_rule->num_entries, mirr_rule->id);
8889                         if (ret < 0) {
8890                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8891                                                    " ret = %d, aq_err = %d.",
8892                                                    ret, hw->aq.asq_last_status);
8893                                 return -ENOSYS;
8894                         }
8895                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8896                         rte_free(mirr_rule);
8897                         pf->nb_mirror_rule--;
8898                         return 0;
8899                 }
8900         } else if (!on) {
8901                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8902                 return -ENOENT;
8903         }
8904
8905         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8906                                 sizeof(struct i40e_mirror_rule) , 0);
8907         if (!mirr_rule) {
8908                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8909                 return I40E_ERR_NO_MEMORY;
8910         }
8911         switch (mirror_conf->rule_type) {
8912         case ETH_MIRROR_VLAN:
8913                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8914                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8915                                 mirr_rule->entries[j] =
8916                                         mirror_conf->vlan.vlan_id[i];
8917                                 j++;
8918                         }
8919                 }
8920                 if (j == 0) {
8921                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8922                         rte_free(mirr_rule);
8923                         return -EINVAL;
8924                 }
8925                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8926                 break;
8927         case ETH_MIRROR_VIRTUAL_POOL_UP:
8928         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8929                 /* check if the specified pool bit is out of range */
8930                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8931                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8932                         rte_free(mirr_rule);
8933                         return -EINVAL;
8934                 }
8935                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8936                         if (mirror_conf->pool_mask & (1ULL << i)) {
8937                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8938                                 j++;
8939                         }
8940                 }
8941                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8942                         /* add pf vsi to entries */
8943                         mirr_rule->entries[j] = pf->main_vsi_seid;
8944                         j++;
8945                 }
8946                 if (j == 0) {
8947                         PMD_DRV_LOG(ERR, "pool is not specified.");
8948                         rte_free(mirr_rule);
8949                         return -EINVAL;
8950                 }
8951                 /* egress and ingress in aq commands means from switch but not port */
8952                 mirr_rule->rule_type =
8953                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8954                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8955                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8956                 break;
8957         case ETH_MIRROR_UPLINK_PORT:
8958                 /* egress and ingress in aq commands means from switch but not port*/
8959                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8960                 break;
8961         case ETH_MIRROR_DOWNLINK_PORT:
8962                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8963                 break;
8964         default:
8965                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8966                         mirror_conf->rule_type);
8967                 rte_free(mirr_rule);
8968                 return -EINVAL;
8969         }
8970
8971         /* If the dst_pool is equal to vf_num, consider it as PF */
8972         if (mirror_conf->dst_pool == pf->vf_num)
8973                 dst_seid = pf->main_vsi_seid;
8974         else
8975                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8976
8977         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8978                                       mirr_rule->rule_type, mirr_rule->entries,
8979                                       j, &rule_id);
8980         if (ret < 0) {
8981                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8982                                    " ret = %d, aq_err = %d.",
8983                                    ret, hw->aq.asq_last_status);
8984                 rte_free(mirr_rule);
8985                 return -ENOSYS;
8986         }
8987
8988         mirr_rule->index = sw_id;
8989         mirr_rule->num_entries = j;
8990         mirr_rule->id = rule_id;
8991         mirr_rule->dst_vsi_seid = dst_seid;
8992
8993         if (parent)
8994                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8995         else
8996                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8997
8998         pf->nb_mirror_rule++;
8999         return 0;
9000 }
9001
9002 /**
9003  * i40e_mirror_rule_reset
9004  * @dev: pointer to the device
9005  * @sw_id: mirror rule's sw_id
9006  *
9007  * reset a mirror rule.
9008  *
9009  **/
9010 static int
9011 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9012 {
9013         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9015         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9016         uint16_t seid;
9017         int ret;
9018
9019         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9020
9021         seid = pf->main_vsi->veb->seid;
9022
9023         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9024                 if (sw_id == it->index) {
9025                         mirr_rule = it;
9026                         break;
9027                 }
9028         }
9029         if (mirr_rule) {
9030                 ret = i40e_aq_del_mirror_rule(hw, seid,
9031                                 mirr_rule->rule_type,
9032                                 mirr_rule->entries,
9033                                 mirr_rule->num_entries, mirr_rule->id);
9034                 if (ret < 0) {
9035                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9036                                            " status = %d, aq_err = %d.",
9037                                            ret, hw->aq.asq_last_status);
9038                         return -ENOSYS;
9039                 }
9040                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9041                 rte_free(mirr_rule);
9042                 pf->nb_mirror_rule--;
9043         } else {
9044                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9045                 return -ENOENT;
9046         }
9047         return 0;
9048 }
9049
9050 static uint64_t
9051 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9052 {
9053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9054         uint64_t systim_cycles;
9055
9056         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9057         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9058                         << 32;
9059
9060         return systim_cycles;
9061 }
9062
9063 static uint64_t
9064 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9065 {
9066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9067         uint64_t rx_tstamp;
9068
9069         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9070         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9071                         << 32;
9072
9073         return rx_tstamp;
9074 }
9075
9076 static uint64_t
9077 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9078 {
9079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9080         uint64_t tx_tstamp;
9081
9082         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9083         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9084                         << 32;
9085
9086         return tx_tstamp;
9087 }
9088
9089 static void
9090 i40e_start_timecounters(struct rte_eth_dev *dev)
9091 {
9092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9093         struct i40e_adapter *adapter =
9094                         (struct i40e_adapter *)dev->data->dev_private;
9095         struct rte_eth_link link;
9096         uint32_t tsync_inc_l;
9097         uint32_t tsync_inc_h;
9098
9099         /* Get current link speed. */
9100         memset(&link, 0, sizeof(link));
9101         i40e_dev_link_update(dev, 1);
9102         rte_i40e_dev_atomic_read_link_status(dev, &link);
9103
9104         switch (link.link_speed) {
9105         case ETH_SPEED_NUM_40G:
9106                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9107                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9108                 break;
9109         case ETH_SPEED_NUM_10G:
9110                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9111                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9112                 break;
9113         case ETH_SPEED_NUM_1G:
9114                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9115                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9116                 break;
9117         default:
9118                 tsync_inc_l = 0x0;
9119                 tsync_inc_h = 0x0;
9120         }
9121
9122         /* Set the timesync increment value. */
9123         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9124         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9125
9126         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9127         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9128         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9129
9130         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9131         adapter->systime_tc.cc_shift = 0;
9132         adapter->systime_tc.nsec_mask = 0;
9133
9134         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9135         adapter->rx_tstamp_tc.cc_shift = 0;
9136         adapter->rx_tstamp_tc.nsec_mask = 0;
9137
9138         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9139         adapter->tx_tstamp_tc.cc_shift = 0;
9140         adapter->tx_tstamp_tc.nsec_mask = 0;
9141 }
9142
9143 static int
9144 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9145 {
9146         struct i40e_adapter *adapter =
9147                         (struct i40e_adapter *)dev->data->dev_private;
9148
9149         adapter->systime_tc.nsec += delta;
9150         adapter->rx_tstamp_tc.nsec += delta;
9151         adapter->tx_tstamp_tc.nsec += delta;
9152
9153         return 0;
9154 }
9155
9156 static int
9157 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9158 {
9159         uint64_t ns;
9160         struct i40e_adapter *adapter =
9161                         (struct i40e_adapter *)dev->data->dev_private;
9162
9163         ns = rte_timespec_to_ns(ts);
9164
9165         /* Set the timecounters to a new value. */
9166         adapter->systime_tc.nsec = ns;
9167         adapter->rx_tstamp_tc.nsec = ns;
9168         adapter->tx_tstamp_tc.nsec = ns;
9169
9170         return 0;
9171 }
9172
9173 static int
9174 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9175 {
9176         uint64_t ns, systime_cycles;
9177         struct i40e_adapter *adapter =
9178                         (struct i40e_adapter *)dev->data->dev_private;
9179
9180         systime_cycles = i40e_read_systime_cyclecounter(dev);
9181         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9182         *ts = rte_ns_to_timespec(ns);
9183
9184         return 0;
9185 }
9186
9187 static int
9188 i40e_timesync_enable(struct rte_eth_dev *dev)
9189 {
9190         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9191         uint32_t tsync_ctl_l;
9192         uint32_t tsync_ctl_h;
9193
9194         /* Stop the timesync system time. */
9195         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9196         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9197         /* Reset the timesync system time value. */
9198         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9199         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9200
9201         i40e_start_timecounters(dev);
9202
9203         /* Clear timesync registers. */
9204         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9205         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9206         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9207         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9208         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9209         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9210
9211         /* Enable timestamping of PTP packets. */
9212         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9213         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9214
9215         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9216         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9217         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9218
9219         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9220         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9221
9222         return 0;
9223 }
9224
9225 static int
9226 i40e_timesync_disable(struct rte_eth_dev *dev)
9227 {
9228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9229         uint32_t tsync_ctl_l;
9230         uint32_t tsync_ctl_h;
9231
9232         /* Disable timestamping of transmitted PTP packets. */
9233         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9234         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9235
9236         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9237         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9238
9239         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9240         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9241
9242         /* Reset the timesync increment value. */
9243         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9244         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9245
9246         return 0;
9247 }
9248
9249 static int
9250 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9251                                 struct timespec *timestamp, uint32_t flags)
9252 {
9253         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9254         struct i40e_adapter *adapter =
9255                 (struct i40e_adapter *)dev->data->dev_private;
9256
9257         uint32_t sync_status;
9258         uint32_t index = flags & 0x03;
9259         uint64_t rx_tstamp_cycles;
9260         uint64_t ns;
9261
9262         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9263         if ((sync_status & (1 << index)) == 0)
9264                 return -EINVAL;
9265
9266         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9267         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9268         *timestamp = rte_ns_to_timespec(ns);
9269
9270         return 0;
9271 }
9272
9273 static int
9274 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9275                                 struct timespec *timestamp)
9276 {
9277         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9278         struct i40e_adapter *adapter =
9279                 (struct i40e_adapter *)dev->data->dev_private;
9280
9281         uint32_t sync_status;
9282         uint64_t tx_tstamp_cycles;
9283         uint64_t ns;
9284
9285         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9286         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9287                 return -EINVAL;
9288
9289         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9290         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9291         *timestamp = rte_ns_to_timespec(ns);
9292
9293         return 0;
9294 }
9295
9296 /*
9297  * i40e_parse_dcb_configure - parse dcb configure from user
9298  * @dev: the device being configured
9299  * @dcb_cfg: pointer of the result of parse
9300  * @*tc_map: bit map of enabled traffic classes
9301  *
9302  * Returns 0 on success, negative value on failure
9303  */
9304 static int
9305 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9306                          struct i40e_dcbx_config *dcb_cfg,
9307                          uint8_t *tc_map)
9308 {
9309         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9310         uint8_t i, tc_bw, bw_lf;
9311
9312         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9313
9314         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9315         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9316                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9317                 return -EINVAL;
9318         }
9319
9320         /* assume each tc has the same bw */
9321         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9322         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9323                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9324         /* to ensure the sum of tcbw is equal to 100 */
9325         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9326         for (i = 0; i < bw_lf; i++)
9327                 dcb_cfg->etscfg.tcbwtable[i]++;
9328
9329         /* assume each tc has the same Transmission Selection Algorithm */
9330         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9331                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9332
9333         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9334                 dcb_cfg->etscfg.prioritytable[i] =
9335                                 dcb_rx_conf->dcb_tc[i];
9336
9337         /* FW needs one App to configure HW */
9338         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9339         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9340         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9341         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9342
9343         if (dcb_rx_conf->nb_tcs == 0)
9344                 *tc_map = 1; /* tc0 only */
9345         else
9346                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9347
9348         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9349                 dcb_cfg->pfc.willing = 0;
9350                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9351                 dcb_cfg->pfc.pfcenable = *tc_map;
9352         }
9353         return 0;
9354 }
9355
9356
9357 static enum i40e_status_code
9358 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9359                               struct i40e_aqc_vsi_properties_data *info,
9360                               uint8_t enabled_tcmap)
9361 {
9362         enum i40e_status_code ret;
9363         int i, total_tc = 0;
9364         uint16_t qpnum_per_tc, bsf, qp_idx;
9365         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9366         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9367         uint16_t used_queues;
9368
9369         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9370         if (ret != I40E_SUCCESS)
9371                 return ret;
9372
9373         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9374                 if (enabled_tcmap & (1 << i))
9375                         total_tc++;
9376         }
9377         if (total_tc == 0)
9378                 total_tc = 1;
9379         vsi->enabled_tc = enabled_tcmap;
9380
9381         /* different VSI has different queues assigned */
9382         if (vsi->type == I40E_VSI_MAIN)
9383                 used_queues = dev_data->nb_rx_queues -
9384                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9385         else if (vsi->type == I40E_VSI_VMDQ2)
9386                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9387         else {
9388                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9389                 return I40E_ERR_NO_AVAILABLE_VSI;
9390         }
9391
9392         qpnum_per_tc = used_queues / total_tc;
9393         /* Number of queues per enabled TC */
9394         if (qpnum_per_tc == 0) {
9395                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9396                 return I40E_ERR_INVALID_QP_ID;
9397         }
9398         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9399                                 I40E_MAX_Q_PER_TC);
9400         bsf = rte_bsf32(qpnum_per_tc);
9401
9402         /**
9403          * Configure TC and queue mapping parameters, for enabled TC,
9404          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9405          * default queue will serve it.
9406          */
9407         qp_idx = 0;
9408         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9409                 if (vsi->enabled_tc & (1 << i)) {
9410                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9411                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9412                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9413                         qp_idx += qpnum_per_tc;
9414                 } else
9415                         info->tc_mapping[i] = 0;
9416         }
9417
9418         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9419         if (vsi->type == I40E_VSI_SRIOV) {
9420                 info->mapping_flags |=
9421                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9422                 for (i = 0; i < vsi->nb_qps; i++)
9423                         info->queue_mapping[i] =
9424                                 rte_cpu_to_le_16(vsi->base_queue + i);
9425         } else {
9426                 info->mapping_flags |=
9427                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9428                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9429         }
9430         info->valid_sections |=
9431                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9432
9433         return I40E_SUCCESS;
9434 }
9435
9436 /*
9437  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9438  * @veb: VEB to be configured
9439  * @tc_map: enabled TC bitmap
9440  *
9441  * Returns 0 on success, negative value on failure
9442  */
9443 static enum i40e_status_code
9444 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9445 {
9446         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9447         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9448         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9449         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9450         enum i40e_status_code ret = I40E_SUCCESS;
9451         int i;
9452         uint32_t bw_max;
9453
9454         /* Check if enabled_tc is same as existing or new TCs */
9455         if (veb->enabled_tc == tc_map)
9456                 return ret;
9457
9458         /* configure tc bandwidth */
9459         memset(&veb_bw, 0, sizeof(veb_bw));
9460         veb_bw.tc_valid_bits = tc_map;
9461         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9462         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9463                 if (tc_map & BIT_ULL(i))
9464                         veb_bw.tc_bw_share_credits[i] = 1;
9465         }
9466         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9467                                                    &veb_bw, NULL);
9468         if (ret) {
9469                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9470                                   " per TC failed = %d",
9471                                   hw->aq.asq_last_status);
9472                 return ret;
9473         }
9474
9475         memset(&ets_query, 0, sizeof(ets_query));
9476         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9477                                                    &ets_query, NULL);
9478         if (ret != I40E_SUCCESS) {
9479                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9480                                  " configuration %u", hw->aq.asq_last_status);
9481                 return ret;
9482         }
9483         memset(&bw_query, 0, sizeof(bw_query));
9484         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9485                                                   &bw_query, NULL);
9486         if (ret != I40E_SUCCESS) {
9487                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9488                                  " configuration %u", hw->aq.asq_last_status);
9489                 return ret;
9490         }
9491
9492         /* store and print out BW info */
9493         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9494         veb->bw_info.bw_max = ets_query.tc_bw_max;
9495         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9496         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9497         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9498                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9499                      I40E_16_BIT_WIDTH);
9500         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9501                 veb->bw_info.bw_ets_share_credits[i] =
9502                                 bw_query.tc_bw_share_credits[i];
9503                 veb->bw_info.bw_ets_credits[i] =
9504                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9505                 /* 4 bits per TC, 4th bit is reserved */
9506                 veb->bw_info.bw_ets_max[i] =
9507                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9508                                   RTE_LEN2MASK(3, uint8_t));
9509                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9510                             veb->bw_info.bw_ets_share_credits[i]);
9511                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9512                             veb->bw_info.bw_ets_credits[i]);
9513                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9514                             veb->bw_info.bw_ets_max[i]);
9515         }
9516
9517         veb->enabled_tc = tc_map;
9518
9519         return ret;
9520 }
9521
9522
9523 /*
9524  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9525  * @vsi: VSI to be configured
9526  * @tc_map: enabled TC bitmap
9527  *
9528  * Returns 0 on success, negative value on failure
9529  */
9530 static enum i40e_status_code
9531 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9532 {
9533         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9534         struct i40e_vsi_context ctxt;
9535         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9536         enum i40e_status_code ret = I40E_SUCCESS;
9537         int i;
9538
9539         /* Check if enabled_tc is same as existing or new TCs */
9540         if (vsi->enabled_tc == tc_map)
9541                 return ret;
9542
9543         /* configure tc bandwidth */
9544         memset(&bw_data, 0, sizeof(bw_data));
9545         bw_data.tc_valid_bits = tc_map;
9546         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9547         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9548                 if (tc_map & BIT_ULL(i))
9549                         bw_data.tc_bw_credits[i] = 1;
9550         }
9551         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9552         if (ret) {
9553                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9554                         " per TC failed = %d",
9555                         hw->aq.asq_last_status);
9556                 goto out;
9557         }
9558         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9559                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9560
9561         /* Update Queue Pairs Mapping for currently enabled UPs */
9562         ctxt.seid = vsi->seid;
9563         ctxt.pf_num = hw->pf_id;
9564         ctxt.vf_num = 0;
9565         ctxt.uplink_seid = vsi->uplink_seid;
9566         ctxt.info = vsi->info;
9567         i40e_get_cap(hw);
9568         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9569         if (ret)
9570                 goto out;
9571
9572         /* Update the VSI after updating the VSI queue-mapping information */
9573         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9574         if (ret) {
9575                 PMD_INIT_LOG(ERR, "Failed to configure "
9576                             "TC queue mapping = %d",
9577                             hw->aq.asq_last_status);
9578                 goto out;
9579         }
9580         /* update the local VSI info with updated queue map */
9581         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9582                                         sizeof(vsi->info.tc_mapping));
9583         (void)rte_memcpy(&vsi->info.queue_mapping,
9584                         &ctxt.info.queue_mapping,
9585                 sizeof(vsi->info.queue_mapping));
9586         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9587         vsi->info.valid_sections = 0;
9588
9589         /* query and update current VSI BW information */
9590         ret = i40e_vsi_get_bw_config(vsi);
9591         if (ret) {
9592                 PMD_INIT_LOG(ERR,
9593                          "Failed updating vsi bw info, err %s aq_err %s",
9594                          i40e_stat_str(hw, ret),
9595                          i40e_aq_str(hw, hw->aq.asq_last_status));
9596                 goto out;
9597         }
9598
9599         vsi->enabled_tc = tc_map;
9600
9601 out:
9602         return ret;
9603 }
9604
9605 /*
9606  * i40e_dcb_hw_configure - program the dcb setting to hw
9607  * @pf: pf the configuration is taken on
9608  * @new_cfg: new configuration
9609  * @tc_map: enabled TC bitmap
9610  *
9611  * Returns 0 on success, negative value on failure
9612  */
9613 static enum i40e_status_code
9614 i40e_dcb_hw_configure(struct i40e_pf *pf,
9615                       struct i40e_dcbx_config *new_cfg,
9616                       uint8_t tc_map)
9617 {
9618         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9619         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9620         struct i40e_vsi *main_vsi = pf->main_vsi;
9621         struct i40e_vsi_list *vsi_list;
9622         enum i40e_status_code ret;
9623         int i;
9624         uint32_t val;
9625
9626         /* Use the FW API if FW > v4.4*/
9627         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9628               (hw->aq.fw_maj_ver >= 5))) {
9629                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9630                                   " to configure DCB");
9631                 return I40E_ERR_FIRMWARE_API_VERSION;
9632         }
9633
9634         /* Check if need reconfiguration */
9635         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9636                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9637                 return I40E_SUCCESS;
9638         }
9639
9640         /* Copy the new config to the current config */
9641         *old_cfg = *new_cfg;
9642         old_cfg->etsrec = old_cfg->etscfg;
9643         ret = i40e_set_dcb_config(hw);
9644         if (ret) {
9645                 PMD_INIT_LOG(ERR,
9646                          "Set DCB Config failed, err %s aq_err %s\n",
9647                          i40e_stat_str(hw, ret),
9648                          i40e_aq_str(hw, hw->aq.asq_last_status));
9649                 return ret;
9650         }
9651         /* set receive Arbiter to RR mode and ETS scheme by default */
9652         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9653                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9654                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9655                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9656                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9657                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9658                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9659                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9660                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9661                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9662                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9663                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9664                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9665         }
9666         /* get local mib to check whether it is configured correctly */
9667         /* IEEE mode */
9668         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9669         /* Get Local DCB Config */
9670         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9671                                      &hw->local_dcbx_config);
9672
9673         /* if Veb is created, need to update TC of it at first */
9674         if (main_vsi->veb) {
9675                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9676                 if (ret)
9677                         PMD_INIT_LOG(WARNING,
9678                                  "Failed configuring TC for VEB seid=%d\n",
9679                                  main_vsi->veb->seid);
9680         }
9681         /* Update each VSI */
9682         i40e_vsi_config_tc(main_vsi, tc_map);
9683         if (main_vsi->veb) {
9684                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9685                         /* Beside main VSI and VMDQ VSIs, only enable default
9686                          * TC for other VSIs
9687                          */
9688                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9689                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9690                                                          tc_map);
9691                         else
9692                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9693                                                          I40E_DEFAULT_TCMAP);
9694                         if (ret)
9695                                 PMD_INIT_LOG(WARNING,
9696                                          "Failed configuring TC for VSI seid=%d\n",
9697                                          vsi_list->vsi->seid);
9698                         /* continue */
9699                 }
9700         }
9701         return I40E_SUCCESS;
9702 }
9703
9704 /*
9705  * i40e_dcb_init_configure - initial dcb config
9706  * @dev: device being configured
9707  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9708  *
9709  * Returns 0 on success, negative value on failure
9710  */
9711 static int
9712 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9713 {
9714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9716         int ret = 0;
9717
9718         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9719                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9720                 return -ENOTSUP;
9721         }
9722
9723         /* DCB initialization:
9724          * Update DCB configuration from the Firmware and configure
9725          * LLDP MIB change event.
9726          */
9727         if (sw_dcb == TRUE) {
9728                 ret = i40e_init_dcb(hw);
9729                 /* If lldp agent is stopped, the return value from
9730                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9731                  * adminq status. Otherwise, it should return success.
9732                  */
9733                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9734                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9735                         memset(&hw->local_dcbx_config, 0,
9736                                 sizeof(struct i40e_dcbx_config));
9737                         /* set dcb default configuration */
9738                         hw->local_dcbx_config.etscfg.willing = 0;
9739                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9740                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9741                         hw->local_dcbx_config.etscfg.tsatable[0] =
9742                                                 I40E_IEEE_TSA_ETS;
9743                         hw->local_dcbx_config.etsrec =
9744                                 hw->local_dcbx_config.etscfg;
9745                         hw->local_dcbx_config.pfc.willing = 0;
9746                         hw->local_dcbx_config.pfc.pfccap =
9747                                                 I40E_MAX_TRAFFIC_CLASS;
9748                         /* FW needs one App to configure HW */
9749                         hw->local_dcbx_config.numapps = 1;
9750                         hw->local_dcbx_config.app[0].selector =
9751                                                 I40E_APP_SEL_ETHTYPE;
9752                         hw->local_dcbx_config.app[0].priority = 3;
9753                         hw->local_dcbx_config.app[0].protocolid =
9754                                                 I40E_APP_PROTOID_FCOE;
9755                         ret = i40e_set_dcb_config(hw);
9756                         if (ret) {
9757                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9758                                         " err = %d, aq_err = %d.", ret,
9759                                           hw->aq.asq_last_status);
9760                                 return -ENOSYS;
9761                         }
9762                 } else {
9763                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9764                                           " err = %d, aq_err = %d.", ret,
9765                                           hw->aq.asq_last_status);
9766                         return -ENOTSUP;
9767                 }
9768         } else {
9769                 ret = i40e_aq_start_lldp(hw, NULL);
9770                 if (ret != I40E_SUCCESS)
9771                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9772
9773                 ret = i40e_init_dcb(hw);
9774                 if (!ret) {
9775                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9776                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9777                                                   " DCBX offload.");
9778                                 return -ENOTSUP;
9779                         }
9780                 } else {
9781                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9782                                           " aq_err = %d.", ret,
9783                                           hw->aq.asq_last_status);
9784                         return -ENOTSUP;
9785                 }
9786         }
9787         return 0;
9788 }
9789
9790 /*
9791  * i40e_dcb_setup - setup dcb related config
9792  * @dev: device being configured
9793  *
9794  * Returns 0 on success, negative value on failure
9795  */
9796 static int
9797 i40e_dcb_setup(struct rte_eth_dev *dev)
9798 {
9799         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9800         struct i40e_dcbx_config dcb_cfg;
9801         uint8_t tc_map = 0;
9802         int ret = 0;
9803
9804         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9805                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9806                 return -ENOTSUP;
9807         }
9808
9809         if (pf->vf_num != 0)
9810                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9811
9812         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9813         if (ret) {
9814                 PMD_INIT_LOG(ERR, "invalid dcb config");
9815                 return -EINVAL;
9816         }
9817         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9818         if (ret) {
9819                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9820                 return -ENOSYS;
9821         }
9822
9823         return 0;
9824 }
9825
9826 static int
9827 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9828                       struct rte_eth_dcb_info *dcb_info)
9829 {
9830         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9832         struct i40e_vsi *vsi = pf->main_vsi;
9833         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9834         uint16_t bsf, tc_mapping;
9835         int i, j = 0;
9836
9837         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9838                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9839         else
9840                 dcb_info->nb_tcs = 1;
9841         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9842                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9843         for (i = 0; i < dcb_info->nb_tcs; i++)
9844                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9845
9846         /* get queue mapping if vmdq is disabled */
9847         if (!pf->nb_cfg_vmdq_vsi) {
9848                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9849                         if (!(vsi->enabled_tc & (1 << i)))
9850                                 continue;
9851                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9852                         dcb_info->tc_queue.tc_rxq[j][i].base =
9853                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9854                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9855                         dcb_info->tc_queue.tc_txq[j][i].base =
9856                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9857                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9858                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9859                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9860                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9861                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9862                 }
9863                 return 0;
9864         }
9865
9866         /* get queue mapping if vmdq is enabled */
9867         do {
9868                 vsi = pf->vmdq[j].vsi;
9869                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9870                         if (!(vsi->enabled_tc & (1 << i)))
9871                                 continue;
9872                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9873                         dcb_info->tc_queue.tc_rxq[j][i].base =
9874                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9875                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9876                         dcb_info->tc_queue.tc_txq[j][i].base =
9877                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9878                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9879                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9880                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9881                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9882                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9883                 }
9884                 j++;
9885         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9886         return 0;
9887 }
9888
9889 static int
9890 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9891 {
9892         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9894         uint16_t msix_intr;
9895
9896         msix_intr = intr_handle->intr_vec[queue_id];
9897         if (msix_intr == I40E_MISC_VEC_ID)
9898                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9899                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
9900                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
9901                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
9902         else
9903                 I40E_WRITE_REG(hw,
9904                                I40E_PFINT_DYN_CTLN(msix_intr -
9905                                                    I40E_RX_VEC_START),
9906                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9907                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9908                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
9909
9910         I40E_WRITE_FLUSH(hw);
9911         rte_intr_enable(&dev->pci_dev->intr_handle);
9912
9913         return 0;
9914 }
9915
9916 static int
9917 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9918 {
9919         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9920         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9921         uint16_t msix_intr;
9922
9923         msix_intr = intr_handle->intr_vec[queue_id];
9924         if (msix_intr == I40E_MISC_VEC_ID)
9925                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9926                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
9927         else
9928                 I40E_WRITE_REG(hw,
9929                                I40E_PFINT_DYN_CTLN(msix_intr -
9930                                                    I40E_RX_VEC_START),
9931                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
9932         I40E_WRITE_FLUSH(hw);
9933
9934         return 0;
9935 }
9936
9937 static int i40e_get_regs(struct rte_eth_dev *dev,
9938                          struct rte_dev_reg_info *regs)
9939 {
9940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9941         uint32_t *ptr_data = regs->data;
9942         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9943         const struct i40e_reg_info *reg_info;
9944
9945         if (ptr_data == NULL) {
9946                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9947                 regs->width = sizeof(uint32_t);
9948                 return 0;
9949         }
9950
9951         /* The first few registers have to be read using AQ operations */
9952         reg_idx = 0;
9953         while (i40e_regs_adminq[reg_idx].name) {
9954                 reg_info = &i40e_regs_adminq[reg_idx++];
9955                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9956                         for (arr_idx2 = 0;
9957                                         arr_idx2 <= reg_info->count2;
9958                                         arr_idx2++) {
9959                                 reg_offset = arr_idx * reg_info->stride1 +
9960                                         arr_idx2 * reg_info->stride2;
9961                                 reg_offset += reg_info->base_addr;
9962                                 ptr_data[reg_offset >> 2] =
9963                                         i40e_read_rx_ctl(hw, reg_offset);
9964                         }
9965         }
9966
9967         /* The remaining registers can be read using primitives */
9968         reg_idx = 0;
9969         while (i40e_regs_others[reg_idx].name) {
9970                 reg_info = &i40e_regs_others[reg_idx++];
9971                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9972                         for (arr_idx2 = 0;
9973                                         arr_idx2 <= reg_info->count2;
9974                                         arr_idx2++) {
9975                                 reg_offset = arr_idx * reg_info->stride1 +
9976                                         arr_idx2 * reg_info->stride2;
9977                                 reg_offset += reg_info->base_addr;
9978                                 ptr_data[reg_offset >> 2] =
9979                                         I40E_READ_REG(hw, reg_offset);
9980                         }
9981         }
9982
9983         return 0;
9984 }
9985
9986 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9987 {
9988         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9989
9990         /* Convert word count to byte count */
9991         return hw->nvm.sr_size << 1;
9992 }
9993
9994 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9995                            struct rte_dev_eeprom_info *eeprom)
9996 {
9997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9998         uint16_t *data = eeprom->data;
9999         uint16_t offset, length, cnt_words;
10000         int ret_code;
10001
10002         offset = eeprom->offset >> 1;
10003         length = eeprom->length >> 1;
10004         cnt_words = length;
10005
10006         if (offset > hw->nvm.sr_size ||
10007                 offset + length > hw->nvm.sr_size) {
10008                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10009                 return -EINVAL;
10010         }
10011
10012         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10013
10014         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10015         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10016                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10017                 return -EIO;
10018         }
10019
10020         return 0;
10021 }
10022
10023 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10024                                       struct ether_addr *mac_addr)
10025 {
10026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10027         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10028         struct i40e_vsi *vsi = pf->main_vsi;
10029         struct i40e_mac_filter_info mac_filter;
10030         struct i40e_mac_filter *f;
10031         int ret;
10032
10033         if (!is_valid_assigned_ether_addr(mac_addr)) {
10034                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10035                 return;
10036         }
10037
10038         TAILQ_FOREACH(f, &vsi->mac_list, next) {
10039                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
10040                         break;
10041         }
10042
10043         if (f == NULL) {
10044                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
10045                 return;
10046         }
10047
10048         mac_filter = f->mac_info;
10049         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
10050         if (ret != I40E_SUCCESS) {
10051                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
10052                 return;
10053         }
10054         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
10055         ret = i40e_vsi_add_mac(vsi, &mac_filter);
10056         if (ret != I40E_SUCCESS) {
10057                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
10058                 return;
10059         }
10060         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
10061
10062         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
10063                                   mac_addr->addr_bytes, NULL);
10064 }
10065
10066 static int
10067 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10068 {
10069         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10070         struct rte_eth_dev_data *dev_data = pf->dev_data;
10071         uint32_t frame_size = mtu + ETHER_HDR_LEN
10072                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10073         int ret = 0;
10074
10075         /* check if mtu is within the allowed range */
10076         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10077                 return -EINVAL;
10078
10079         /* mtu setting is forbidden if port is start */
10080         if (dev_data->dev_started) {
10081                 PMD_DRV_LOG(ERR,
10082                             "port %d must be stopped before configuration\n",
10083                             dev_data->port_id);
10084                 return -EBUSY;
10085         }
10086
10087         if (frame_size > ETHER_MAX_LEN)
10088                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10089         else
10090                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10091
10092         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10093
10094         return ret;
10095 }