drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 458         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 459         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 460         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 461         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 462         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 463         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct eth_dev_ops i40e_eth_dev_ops = {
 482         .dev_configure                = i40e_dev_configure,
 483         .dev_start                    = i40e_dev_start,
 484         .dev_stop                     = i40e_dev_stop,
 485         .dev_close                    = i40e_dev_close,
 486         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 487         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 488         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 489         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 490         .dev_set_link_up              = i40e_dev_set_link_up,
 491         .dev_set_link_down            = i40e_dev_set_link_down,
 492         .link_update                  = i40e_dev_link_update,
 493         .stats_get                    = i40e_dev_stats_get,
 494         .xstats_get                   = i40e_dev_xstats_get,
 495         .xstats_get_names             = i40e_dev_xstats_get_names,
 496         .stats_reset                  = i40e_dev_stats_reset,
 497         .xstats_reset                 = i40e_dev_stats_reset,
 498         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 499         .dev_infos_get                = i40e_dev_info_get,
 500         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 501         .vlan_filter_set              = i40e_vlan_filter_set,
 502         .vlan_tpid_set                = i40e_vlan_tpid_set,
 503         .vlan_offload_set             = i40e_vlan_offload_set,
 504         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 505         .vlan_pvid_set                = i40e_vlan_pvid_set,
 506         .rx_queue_start               = i40e_dev_rx_queue_start,
 507         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 508         .tx_queue_start               = i40e_dev_tx_queue_start,
 509         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 510         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 511         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 512         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 513         .rx_queue_release             = i40e_dev_rx_queue_release,
 514         .rx_queue_count               = i40e_dev_rx_queue_count,
 515         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 516         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 517         .tx_queue_release             = i40e_dev_tx_queue_release,
 518         .dev_led_on                   = i40e_dev_led_on,
 519         .dev_led_off                  = i40e_dev_led_off,
 520         .flow_ctrl_get                = i40e_flow_ctrl_get,
 521         .flow_ctrl_set                = i40e_flow_ctrl_set,
 522         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 523         .mac_addr_add                 = i40e_macaddr_add,
 524         .mac_addr_remove              = i40e_macaddr_remove,
 525         .reta_update                  = i40e_dev_rss_reta_update,
 526         .reta_query                   = i40e_dev_rss_reta_query,
 527         .rss_hash_update              = i40e_dev_rss_hash_update,
 528         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 529         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 530         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 531         .filter_ctrl                  = i40e_dev_filter_ctrl,
 532         .rxq_info_get                 = i40e_rxq_info_get,
 533         .txq_info_get                 = i40e_txq_info_get,
 534         .mirror_rule_set              = i40e_mirror_rule_set,
 535         .mirror_rule_reset            = i40e_mirror_rule_reset,
 536         .timesync_enable              = i40e_timesync_enable,
 537         .timesync_disable             = i40e_timesync_disable,
 538         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 540         .get_dcb_info                 = i40e_dev_get_dcb_info,
 541         .timesync_adjust_time         = i40e_timesync_adjust_time,
 542         .timesync_read_time           = i40e_timesync_read_time,
 543         .timesync_write_time          = i40e_timesync_write_time,
 544         .get_reg                      = i40e_get_regs,
 545         .get_eeprom_length            = i40e_get_eeprom_length,
 546         .get_eeprom                   = i40e_get_eeprom,
 547         .mac_addr_set                 = i40e_set_default_mac_addr,
 548         .mtu_set                      = i40e_dev_mtu_set,
 549 };
 550
 551 /* store statistics names and its offset in stats structure */
 552 struct rte_i40e_xstats_name_off {
 553         char name[RTE_ETH_XSTATS_NAME_SIZE];
 554         unsigned offset;
 555 };
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 558         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 559         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 560         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 561         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 562         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 563                 rx_unknown_protocol)},
 564         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 565         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 566         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 567         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 568 };
 569
 570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 571                 sizeof(rte_i40e_stats_strings[0]))
 572
 573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 574         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 575                 tx_dropped_link_down)},
 576         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 577         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 578                 illegal_bytes)},
 579         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 580         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 581                 mac_local_faults)},
 582         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 583                 mac_remote_faults)},
 584         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_length_errors)},
 586         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 587         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 588         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 589         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 590         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 591         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 rx_size_127)},
 593         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 rx_size_255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 rx_size_511)},
 597         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 rx_size_1023)},
 599         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_1522)},
 601         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_big)},
 603         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 604                 rx_undersize)},
 605         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 606                 rx_oversize)},
 607         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 608                 mac_short_packet_dropped)},
 609         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 610                 rx_fragments)},
 611         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 612         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 614                 tx_size_127)},
 615         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 616                 tx_size_255)},
 617         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 618                 tx_size_511)},
 619         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 620                 tx_size_1023)},
 621         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_1522)},
 623         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_big)},
 625         {"rx_flow_director_atr_match_packets",
 626                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 627         {"rx_flow_director_sb_match_packets",
 628                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 629         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 630                 tx_lpi_status)},
 631         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 632                 rx_lpi_status)},
 633         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 634                 tx_lpi_count)},
 635         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 636                 rx_lpi_count)},
 637 };
 638
 639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 640                 sizeof(rte_i40e_hw_port_strings[0]))
 641
 642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 643         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 644                 priority_xon_rx)},
 645         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 646                 priority_xoff_rx)},
 647 };
 648
 649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 650                 sizeof(rte_i40e_rxq_prio_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_tx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_tx)},
 657         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_2_xoff)},
 659 };
 660
 661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 662                 sizeof(rte_i40e_txq_prio_strings[0]))
 663
 664 static struct eth_driver rte_i40e_pmd = {
 665         .pci_drv = {
 666                 .name = "rte_i40e_pmd",
 667                 .id_table = pci_id_i40e_map,
 668                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 669                         RTE_PCI_DRV_DETACHABLE,
 670         },
 671         .eth_dev_init = eth_i40e_dev_init,
 672         .eth_dev_uninit = eth_i40e_dev_uninit,
 673         .dev_private_size = sizeof(struct i40e_adapter),
 674 };
 675
 676 static inline int
 677 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 678                                      struct rte_eth_link *link)
 679 {
 680         struct rte_eth_link *dst = link;
 681         struct rte_eth_link *src = &(dev->data->dev_link);
 682
 683         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 684                                         *(uint64_t *)src) == 0)
 685                 return -1;
 686
 687         return 0;
 688 }
 689
 690 static inline int
 691 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 692                                       struct rte_eth_link *link)
 693 {
 694         struct rte_eth_link *dst = &(dev->data->dev_link);
 695         struct rte_eth_link *src = link;
 696
 697         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 698                                         *(uint64_t *)src) == 0)
 699                 return -1;
 700
 701         return 0;
 702 }
 703
 704 /*
 705  * Driver initialization routine.
 706  * Invoked once at EAL init time.
 707  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 708  */
 709 static int
 710 rte_i40e_pmd_init(const char *name __rte_unused,
 711                   const char *params __rte_unused)
 712 {
 713         PMD_INIT_FUNC_TRACE();
 714         rte_eth_driver_register(&rte_i40e_pmd);
 715
 716         return 0;
 717 }
 718
 719 static struct rte_driver rte_i40e_driver = {
 720         .type = PMD_PDEV,
 721         .init = rte_i40e_pmd_init,
 722 };
 723
 724 PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
 725 DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
 726
 727 /*
 728  * Initialize registers for flexible payload, which should be set by NVM.
 729  * This should be removed from code once it is fixed in NVM.
 730  */
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737
 738 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 739 {
 740         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 741         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 742         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 743         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 744         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 745         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 746         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 747         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 748         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 749         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 750
 751         /* GLQF_PIT Registers */
 752         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 753         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 754 }
 755
 756 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 757
 758 /*
 759  * Add a ethertype filter to drop all flow control frames transmitted
 760  * from VSIs.
 761 */
 762 static void
 763 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 764 {
 765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 766         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 767                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 768                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 769         int ret;
 770
 771         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 772                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 773                                 pf->main_vsi_seid, 0,
 774                                 TRUE, NULL, NULL);
 775         if (ret)
 776                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 777                                   " frames from VSIs.");
 778 }
 779
 780 static int
 781 floating_veb_list_handler(__rte_unused const char *key,
 782                           const char *floating_veb_value,
 783                           void *opaque)
 784 {
 785         int idx = 0;
 786         unsigned int count = 0;
 787         char *end = NULL;
 788         int min, max;
 789         bool *vf_floating_veb = opaque;
 790
 791         while (isblank(*floating_veb_value))
 792                 floating_veb_value++;
 793
 794         /* Reset floating VEB configuration for VFs */
 795         for (idx = 0; idx < I40E_MAX_VF; idx++)
 796                 vf_floating_veb[idx] = false;
 797
 798         min = I40E_MAX_VF;
 799         do {
 800                 while (isblank(*floating_veb_value))
 801                         floating_veb_value++;
 802                 if (*floating_veb_value == '\0')
 803                         return -1;
 804                 errno = 0;
 805                 idx = strtoul(floating_veb_value, &end, 10);
 806                 if (errno || end == NULL)
 807                         return -1;
 808                 while (isblank(*end))
 809                         end++;
 810                 if (*end == '-') {
 811                         min = idx;
 812                 } else if ((*end == ';') || (*end == '\0')) {
 813                         max = idx;
 814                         if (min == I40E_MAX_VF)
 815                                 min = idx;
 816                         if (max >= I40E_MAX_VF)
 817                                 max = I40E_MAX_VF - 1;
 818                         for (idx = min; idx <= max; idx++) {
 819                                 vf_floating_veb[idx] = true;
 820                                 count++;
 821                         }
 822                         min = I40E_MAX_VF;
 823                 } else {
 824                         return -1;
 825                 }
 826                 floating_veb_value = end + 1;
 827         } while (*end != '\0');
 828
 829         if (count == 0)
 830                 return -1;
 831
 832         return 0;
 833 }
 834
 835 static void
 836 config_vf_floating_veb(struct rte_devargs *devargs,
 837                        uint16_t floating_veb,
 838                        bool *vf_floating_veb)
 839 {
 840         struct rte_kvargs *kvlist;
 841         int i;
 842         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 843
 844         if (!floating_veb)
 845                 return;
 846         /* All the VFs attach to the floating VEB by default
 847          * when the floating VEB is enabled.
 848          */
 849         for (i = 0; i < I40E_MAX_VF; i++)
 850                 vf_floating_veb[i] = true;
 851
 852         if (devargs == NULL)
 853                 return;
 854
 855         kvlist = rte_kvargs_parse(devargs->args, NULL);
 856         if (kvlist == NULL)
 857                 return;
 858
 859         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 860                 rte_kvargs_free(kvlist);
 861                 return;
 862         }
 863         /* When the floating_veb_list parameter exists, all the VFs
 864          * will attach to the legacy VEB firstly, then configure VFs
 865          * to the floating VEB according to the floating_veb_list.
 866          */
 867         if (rte_kvargs_process(kvlist, floating_veb_list,
 868                                floating_veb_list_handler,
 869                                vf_floating_veb) < 0) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         rte_kvargs_free(kvlist);
 874 }
 875
 876 static int
 877 i40e_check_floating_handler(__rte_unused const char *key,
 878                             const char *value,
 879                             __rte_unused void *opaque)
 880 {
 881         if (strcmp(value, "1"))
 882                 return -1;
 883
 884         return 0;
 885 }
 886
 887 static int
 888 is_floating_veb_supported(struct rte_devargs *devargs)
 889 {
 890         struct rte_kvargs *kvlist;
 891         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 892
 893         if (devargs == NULL)
 894                 return 0;
 895
 896         kvlist = rte_kvargs_parse(devargs->args, NULL);
 897         if (kvlist == NULL)
 898                 return 0;
 899
 900         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 901                 rte_kvargs_free(kvlist);
 902                 return 0;
 903         }
 904         /* Floating VEB is enabled when there's key-value:
 905          * enable_floating_veb=1
 906          */
 907         if (rte_kvargs_process(kvlist, floating_veb_key,
 908                                i40e_check_floating_handler, NULL) < 0) {
 909                 rte_kvargs_free(kvlist);
 910                 return 0;
 911         }
 912         rte_kvargs_free(kvlist);
 913
 914         return 1;
 915 }
 916
 917 static void
 918 config_floating_veb(struct rte_eth_dev *dev)
 919 {
 920         struct rte_pci_device *pci_dev = dev->pci_dev;
 921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 925
 926         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 927                 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
 928                 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
 929                                        pf->floating_veb_list);
 930         } else {
 931                 pf->floating_veb = false;
 932         }
 933 }
 934
 935 static int
 936 eth_i40e_dev_init(struct rte_eth_dev *dev)
 937 {
 938         struct rte_pci_device *pci_dev;
 939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 941         struct i40e_vsi *vsi;
 942         int ret;
 943         uint32_t len;
 944         uint8_t aq_fail = 0;
 945
 946         PMD_INIT_FUNC_TRACE();
 947
 948         dev->dev_ops = &i40e_eth_dev_ops;
 949         dev->rx_pkt_burst = i40e_recv_pkts;
 950         dev->tx_pkt_burst = i40e_xmit_pkts;
 951
 952         /* for secondary processes, we don't initialise any further as primary
 953          * has already done this work. Only check we don't need a different
 954          * RX function */
 955         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 956                 i40e_set_rx_function(dev);
 957                 i40e_set_tx_function(dev);
 958                 return 0;
 959         }
 960         pci_dev = dev->pci_dev;
 961
 962         rte_eth_copy_pci_info(dev, pci_dev);
 963
 964         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 965         pf->adapter->eth_dev = dev;
 966         pf->dev_data = dev->data;
 967
 968         hw->back = I40E_PF_TO_ADAPTER(pf);
 969         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 970         if (!hw->hw_addr) {
 971                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 972                              "as address is NULL");
 973                 return -ENODEV;
 974         }
 975
 976         hw->vendor_id = pci_dev->id.vendor_id;
 977         hw->device_id = pci_dev->id.device_id;
 978         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 979         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 980         hw->bus.device = pci_dev->addr.devid;
 981         hw->bus.func = pci_dev->addr.function;
 982         hw->adapter_stopped = 0;
 983
 984         /* Make sure all is clean before doing PF reset */
 985         i40e_clear_hw(hw);
 986
 987         /* Initialize the hardware */
 988         i40e_hw_init(dev);
 989
 990         /* Reset here to make sure all is clean for each PF */
 991         ret = i40e_pf_reset(hw);
 992         if (ret) {
 993                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 994                 return ret;
 995         }
 996
 997         /* Initialize the shared code (base driver) */
 998         ret = i40e_init_shared_code(hw);
 999         if (ret) {
1000                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1001                 return ret;
1002         }
1003
1004         /*
1005          * To work around the NVM issue,initialize registers
1006          * for flexible payload by software.
1007          * It should be removed once issues are fixed in NVM.
1008          */
1009         i40e_flex_payload_reg_init(hw);
1010
1011         /* Initialize the input set for filters (hash and fd) to default value */
1012         i40e_filter_input_set_init(pf);
1013
1014         /* Initialize the parameters for adminq */
1015         i40e_init_adminq_parameter(hw);
1016         ret = i40e_init_adminq(hw);
1017         if (ret != I40E_SUCCESS) {
1018                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1019                 return -EIO;
1020         }
1021         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1022                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1023                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1024                      ((hw->nvm.version >> 12) & 0xf),
1025                      ((hw->nvm.version >> 4) & 0xff),
1026                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1027
1028         /* Need the special FW version to support floating VEB */
1029         config_floating_veb(dev);
1030         /* Clear PXE mode */
1031         i40e_clear_pxe_mode(hw);
1032
1033         /*
1034          * On X710, performance number is far from the expectation on recent
1035          * firmware versions. The fix for this issue may not be integrated in
1036          * the following firmware version. So the workaround in software driver
1037          * is needed. It needs to modify the initial values of 3 internal only
1038          * registers. Note that the workaround can be removed when it is fixed
1039          * in firmware in the future.
1040          */
1041         i40e_configure_registers(hw);
1042
1043         /* Get hw capabilities */
1044         ret = i40e_get_cap(hw);
1045         if (ret != I40E_SUCCESS) {
1046                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1047                 goto err_get_capabilities;
1048         }
1049
1050         /* Initialize parameters for PF */
1051         ret = i40e_pf_parameter_init(dev);
1052         if (ret != 0) {
1053                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1054                 goto err_parameter_init;
1055         }
1056
1057         /* Initialize the queue management */
1058         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1059         if (ret < 0) {
1060                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1061                 goto err_qp_pool_init;
1062         }
1063         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1064                                 hw->func_caps.num_msix_vectors - 1);
1065         if (ret < 0) {
1066                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1067                 goto err_msix_pool_init;
1068         }
1069
1070         /* Initialize lan hmc */
1071         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1072                                 hw->func_caps.num_rx_qp, 0, 0);
1073         if (ret != I40E_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1075                 goto err_init_lan_hmc;
1076         }
1077
1078         /* Configure lan hmc */
1079         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1080         if (ret != I40E_SUCCESS) {
1081                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1082                 goto err_configure_lan_hmc;
1083         }
1084
1085         /* Get and check the mac address */
1086         i40e_get_mac_addr(hw, hw->mac.addr);
1087         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "mac address is not valid");
1089                 ret = -EIO;
1090                 goto err_get_mac_addr;
1091         }
1092         /* Copy the permanent MAC address */
1093         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1094                         (struct ether_addr *) hw->mac.perm_addr);
1095
1096         /* Disable flow control */
1097         hw->fc.requested_mode = I40E_FC_NONE;
1098         i40e_set_fc(hw, &aq_fail, TRUE);
1099
1100         /* Set the global registers with default ether type value */
1101         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1102         if (ret != I40E_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1104                              "VLAN ether type");
1105                 goto err_setup_pf_switch;
1106         }
1107
1108         /* PF setup, which includes VSI setup */
1109         ret = i40e_pf_setup(pf);
1110         if (ret) {
1111                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1112                 goto err_setup_pf_switch;
1113         }
1114
1115         /* reset all stats of the device, including pf and main vsi */
1116         i40e_dev_stats_reset(dev);
1117
1118         vsi = pf->main_vsi;
1119
1120         /* Disable double vlan by default */
1121         i40e_vsi_config_double_vlan(vsi, FALSE);
1122
1123         if (!vsi->max_macaddrs)
1124                 len = ETHER_ADDR_LEN;
1125         else
1126                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1127
1128         /* Should be after VSI initialized */
1129         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1130         if (!dev->data->mac_addrs) {
1131                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1132                                         "for storing mac address");
1133                 goto err_mac_alloc;
1134         }
1135         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1136                                         &dev->data->mac_addrs[0]);
1137
1138         /* initialize pf host driver to setup SRIOV resource if applicable */
1139         i40e_pf_host_init(dev);
1140
1141         /* register callback func to eal lib */
1142         rte_intr_callback_register(&(pci_dev->intr_handle),
1143                 i40e_dev_interrupt_handler, (void *)dev);
1144
1145         /* configure and enable device interrupt */
1146         i40e_pf_config_irq0(hw, TRUE);
1147         i40e_pf_enable_irq0(hw);
1148
1149         /* enable uio intr after callback register */
1150         rte_intr_enable(&(pci_dev->intr_handle));
1151         /*
1152          * Add an ethertype filter to drop all flow control frames transmitted
1153          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1154          * frames to wire.
1155          */
1156         i40e_add_tx_flow_control_drop_filter(pf);
1157
1158         /* Set the max frame size to 0x2600 by default,
1159          * in case other drivers changed the default value.
1160          */
1161         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1162
1163         /* initialize mirror rule list */
1164         TAILQ_INIT(&pf->mirror_list);
1165
1166         /* Init dcb to sw mode by default */
1167         ret = i40e_dcb_init_configure(dev, TRUE);
1168         if (ret != I40E_SUCCESS) {
1169                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1170                 pf->flags &= ~I40E_FLAG_DCB;
1171         }
1172
1173         return 0;
1174
1175 err_mac_alloc:
1176         i40e_vsi_release(pf->main_vsi);
1177 err_setup_pf_switch:
1178 err_get_mac_addr:
1179 err_configure_lan_hmc:
1180         (void)i40e_shutdown_lan_hmc(hw);
1181 err_init_lan_hmc:
1182         i40e_res_pool_destroy(&pf->msix_pool);
1183 err_msix_pool_init:
1184         i40e_res_pool_destroy(&pf->qp_pool);
1185 err_qp_pool_init:
1186 err_parameter_init:
1187 err_get_capabilities:
1188         (void)i40e_shutdown_adminq(hw);
1189
1190         return ret;
1191 }
1192
1193 static int
1194 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1195 {
1196         struct rte_pci_device *pci_dev;
1197         struct i40e_hw *hw;
1198         struct i40e_filter_control_settings settings;
1199         int ret;
1200         uint8_t aq_fail = 0;
1201
1202         PMD_INIT_FUNC_TRACE();
1203
1204         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1205                 return 0;
1206
1207         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1208         pci_dev = dev->pci_dev;
1209
1210         if (hw->adapter_stopped == 0)
1211                 i40e_dev_close(dev);
1212
1213         dev->dev_ops = NULL;
1214         dev->rx_pkt_burst = NULL;
1215         dev->tx_pkt_burst = NULL;
1216
1217         /* Disable LLDP */
1218         ret = i40e_aq_stop_lldp(hw, true, NULL);
1219         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1220                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1221
1222         /* Clear PXE mode */
1223         i40e_clear_pxe_mode(hw);
1224
1225         /* Unconfigure filter control */
1226         memset(&settings, 0, sizeof(settings));
1227         ret = i40e_set_filter_control(hw, &settings);
1228         if (ret)
1229                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1230                                         ret);
1231
1232         /* Disable flow control */
1233         hw->fc.requested_mode = I40E_FC_NONE;
1234         i40e_set_fc(hw, &aq_fail, TRUE);
1235
1236         /* uninitialize pf host driver */
1237         i40e_pf_host_uninit(dev);
1238
1239         rte_free(dev->data->mac_addrs);
1240         dev->data->mac_addrs = NULL;
1241
1242         /* disable uio intr before callback unregister */
1243         rte_intr_disable(&(pci_dev->intr_handle));
1244
1245         /* register callback func to eal lib */
1246         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1247                 i40e_dev_interrupt_handler, (void *)dev);
1248
1249         return 0;
1250 }
1251
1252 static int
1253 i40e_dev_configure(struct rte_eth_dev *dev)
1254 {
1255         struct i40e_adapter *ad =
1256                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1258         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1259         int i, ret;
1260
1261         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1262          * bulk allocation or vector Rx preconditions we will reset it.
1263          */
1264         ad->rx_bulk_alloc_allowed = true;
1265         ad->rx_vec_allowed = true;
1266         ad->tx_simple_allowed = true;
1267         ad->tx_vec_allowed = true;
1268
1269         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1270                 ret = i40e_fdir_setup(pf);
1271                 if (ret != I40E_SUCCESS) {
1272                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1273                         return -ENOTSUP;
1274                 }
1275                 ret = i40e_fdir_configure(dev);
1276                 if (ret < 0) {
1277                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1278                         goto err;
1279                 }
1280         } else
1281                 i40e_fdir_teardown(pf);
1282
1283         ret = i40e_dev_init_vlan(dev);
1284         if (ret < 0)
1285                 goto err;
1286
1287         /* VMDQ setup.
1288          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1289          *  RSS setting have different requirements.
1290          *  General PMD driver call sequence are NIC init, configure,
1291          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1292          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1293          *  applicable. So, VMDQ setting has to be done before
1294          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1295          *  For RSS setting, it will try to calculate actual configured RX queue
1296          *  number, which will be available after rx_queue_setup(). dev_start()
1297          *  function is good to place RSS setup.
1298          */
1299         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1300                 ret = i40e_vmdq_setup(dev);
1301                 if (ret)
1302                         goto err;
1303         }
1304
1305         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1306                 ret = i40e_dcb_setup(dev);
1307                 if (ret) {
1308                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1309                         goto err_dcb;
1310                 }
1311         }
1312
1313         return 0;
1314
1315 err_dcb:
1316         /* need to release vmdq resource if exists */
1317         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1318                 i40e_vsi_release(pf->vmdq[i].vsi);
1319                 pf->vmdq[i].vsi = NULL;
1320         }
1321         rte_free(pf->vmdq);
1322         pf->vmdq = NULL;
1323 err:
1324         /* need to release fdir resource if exists */
1325         i40e_fdir_teardown(pf);
1326         return ret;
1327 }
1328
1329 void
1330 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1331 {
1332         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1333         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1334         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1335         uint16_t msix_vect = vsi->msix_intr;
1336         uint16_t i;
1337
1338         for (i = 0; i < vsi->nb_qps; i++) {
1339                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1340                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1341                 rte_wmb();
1342         }
1343
1344         if (vsi->type != I40E_VSI_SRIOV) {
1345                 if (!rte_intr_allow_others(intr_handle)) {
1346                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1347                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1348                         I40E_WRITE_REG(hw,
1349                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1350                                        0);
1351                 } else {
1352                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1353                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1354                         I40E_WRITE_REG(hw,
1355                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1356                                                        msix_vect - 1), 0);
1357                 }
1358         } else {
1359                 uint32_t reg;
1360                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1361                         vsi->user_param + (msix_vect - 1);
1362
1363                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1364                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1365         }
1366         I40E_WRITE_FLUSH(hw);
1367 }
1368
1369 static void
1370 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1371                        int base_queue, int nb_queue)
1372 {
1373         int i;
1374         uint32_t val;
1375         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1376
1377         /* Bind all RX queues to allocated MSIX interrupt */
1378         for (i = 0; i < nb_queue; i++) {
1379                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1380                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1381                         ((base_queue + i + 1) <<
1382                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1383                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1384                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1385
1386                 if (i == nb_queue - 1)
1387                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1388                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1389         }
1390
1391         /* Write first RX queue to Link list register as the head element */
1392         if (vsi->type != I40E_VSI_SRIOV) {
1393                 uint16_t interval =
1394                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1395
1396                 if (msix_vect == I40E_MISC_VEC_ID) {
1397                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1398                                        (base_queue <<
1399                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1400                                        (0x0 <<
1401                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1402                         I40E_WRITE_REG(hw,
1403                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1404                                        interval);
1405                 } else {
1406                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1407                                        (base_queue <<
1408                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1409                                        (0x0 <<
1410                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1411                         I40E_WRITE_REG(hw,
1412                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1413                                                        msix_vect - 1),
1414                                        interval);
1415                 }
1416         } else {
1417                 uint32_t reg;
1418
1419                 if (msix_vect == I40E_MISC_VEC_ID) {
1420                         I40E_WRITE_REG(hw,
1421                                        I40E_VPINT_LNKLST0(vsi->user_param),
1422                                        (base_queue <<
1423                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1424                                        (0x0 <<
1425                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1426                 } else {
1427                         /* num_msix_vectors_vf needs to minus irq0 */
1428                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1429                                 vsi->user_param + (msix_vect - 1);
1430
1431                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1432                                        (base_queue <<
1433                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1434                                        (0x0 <<
1435                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1436                 }
1437         }
1438
1439         I40E_WRITE_FLUSH(hw);
1440 }
1441
1442 void
1443 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1444 {
1445         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1446         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1447         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1448         uint16_t msix_vect = vsi->msix_intr;
1449         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1450         uint16_t queue_idx = 0;
1451         int record = 0;
1452         uint32_t val;
1453         int i;
1454
1455         for (i = 0; i < vsi->nb_qps; i++) {
1456                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1457                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1458         }
1459
1460         /* INTENA flag is not auto-cleared for interrupt */
1461         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1462         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1463                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1464                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1465         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1466
1467         /* VF bind interrupt */
1468         if (vsi->type == I40E_VSI_SRIOV) {
1469                 __vsi_queues_bind_intr(vsi, msix_vect,
1470                                        vsi->base_queue, vsi->nb_qps);
1471                 return;
1472         }
1473
1474         /* PF & VMDq bind interrupt */
1475         if (rte_intr_dp_is_en(intr_handle)) {
1476                 if (vsi->type == I40E_VSI_MAIN) {
1477                         queue_idx = 0;
1478                         record = 1;
1479                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1480                         struct i40e_vsi *main_vsi =
1481                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1482                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1483                         record = 1;
1484                 }
1485         }
1486
1487         for (i = 0; i < vsi->nb_used_qps; i++) {
1488                 if (nb_msix <= 1) {
1489                         if (!rte_intr_allow_others(intr_handle))
1490                                 /* allow to share MISC_VEC_ID */
1491                                 msix_vect = I40E_MISC_VEC_ID;
1492
1493                         /* no enough msix_vect, map all to one */
1494                         __vsi_queues_bind_intr(vsi, msix_vect,
1495                                                vsi->base_queue + i,
1496                                                vsi->nb_used_qps - i);
1497                         for (; !!record && i < vsi->nb_used_qps; i++)
1498                                 intr_handle->intr_vec[queue_idx + i] =
1499                                         msix_vect;
1500                         break;
1501                 }
1502                 /* 1:1 queue/msix_vect mapping */
1503                 __vsi_queues_bind_intr(vsi, msix_vect,
1504                                        vsi->base_queue + i, 1);
1505                 if (!!record)
1506                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1507
1508                 msix_vect++;
1509                 nb_msix--;
1510         }
1511 }
1512
1513 static void
1514 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1515 {
1516         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1517         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1518         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1519         uint16_t interval = i40e_calc_itr_interval(\
1520                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1521         uint16_t msix_intr, i;
1522
1523         if (rte_intr_allow_others(intr_handle))
1524                 for (i = 0; i < vsi->nb_msix; i++) {
1525                         msix_intr = vsi->msix_intr + i;
1526                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1527                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1528                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1529                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1530                                 (interval <<
1531                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1532                 }
1533         else
1534                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1535                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1536                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1537                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1538                                (interval <<
1539                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1540
1541         I40E_WRITE_FLUSH(hw);
1542 }
1543
1544 static void
1545 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1546 {
1547         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1548         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1549         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1550         uint16_t msix_intr, i;
1551
1552         if (rte_intr_allow_others(intr_handle))
1553                 for (i = 0; i < vsi->nb_msix; i++) {
1554                         msix_intr = vsi->msix_intr + i;
1555                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1556                                        0);
1557                 }
1558         else
1559                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1560
1561         I40E_WRITE_FLUSH(hw);
1562 }
1563
1564 static inline uint8_t
1565 i40e_parse_link_speeds(uint16_t link_speeds)
1566 {
1567         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1568
1569         if (link_speeds & ETH_LINK_SPEED_40G)
1570                 link_speed |= I40E_LINK_SPEED_40GB;
1571         if (link_speeds & ETH_LINK_SPEED_20G)
1572                 link_speed |= I40E_LINK_SPEED_20GB;
1573         if (link_speeds & ETH_LINK_SPEED_10G)
1574                 link_speed |= I40E_LINK_SPEED_10GB;
1575         if (link_speeds & ETH_LINK_SPEED_1G)
1576                 link_speed |= I40E_LINK_SPEED_1GB;
1577         if (link_speeds & ETH_LINK_SPEED_100M)
1578                 link_speed |= I40E_LINK_SPEED_100MB;
1579
1580         return link_speed;
1581 }
1582
1583 static int
1584 i40e_phy_conf_link(struct i40e_hw *hw,
1585                    uint8_t abilities,
1586                    uint8_t force_speed)
1587 {
1588         enum i40e_status_code status;
1589         struct i40e_aq_get_phy_abilities_resp phy_ab;
1590         struct i40e_aq_set_phy_config phy_conf;
1591         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1592                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1593                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1594                         I40E_AQ_PHY_FLAG_LOW_POWER;
1595         const uint8_t advt = I40E_LINK_SPEED_40GB |
1596                         I40E_LINK_SPEED_10GB |
1597                         I40E_LINK_SPEED_1GB |
1598                         I40E_LINK_SPEED_100MB;
1599         int ret = -ENOTSUP;
1600
1601
1602         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1603                                               NULL);
1604         if (status)
1605                 return ret;
1606
1607         memset(&phy_conf, 0, sizeof(phy_conf));
1608
1609         /* bits 0-2 use the values from get_phy_abilities_resp */
1610         abilities &= ~mask;
1611         abilities |= phy_ab.abilities & mask;
1612
1613         /* update ablities and speed */
1614         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1615                 phy_conf.link_speed = advt;
1616         else
1617                 phy_conf.link_speed = force_speed;
1618
1619         phy_conf.abilities = abilities;
1620
1621         /* use get_phy_abilities_resp value for the rest */
1622         phy_conf.phy_type = phy_ab.phy_type;
1623         phy_conf.eee_capability = phy_ab.eee_capability;
1624         phy_conf.eeer = phy_ab.eeer_val;
1625         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1626
1627         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1628                     phy_ab.abilities, phy_ab.link_speed);
1629         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1630                     phy_conf.abilities, phy_conf.link_speed);
1631
1632         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1633         if (status)
1634                 return ret;
1635
1636         return I40E_SUCCESS;
1637 }
1638
1639 static int
1640 i40e_apply_link_speed(struct rte_eth_dev *dev)
1641 {
1642         uint8_t speed;
1643         uint8_t abilities = 0;
1644         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         struct rte_eth_conf *conf = &dev->data->dev_conf;
1646
1647         speed = i40e_parse_link_speeds(conf->link_speeds);
1648         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1649         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1650                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1651         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1652
1653         /* Skip changing speed on 40G interfaces, FW does not support */
1654         if (i40e_is_40G_device(hw->device_id)) {
1655                 speed =  I40E_LINK_SPEED_UNKNOWN;
1656                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1657         }
1658
1659         return i40e_phy_conf_link(hw, abilities, speed);
1660 }
1661
1662 static int
1663 i40e_dev_start(struct rte_eth_dev *dev)
1664 {
1665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667         struct i40e_vsi *main_vsi = pf->main_vsi;
1668         int ret, i;
1669         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1670         uint32_t intr_vector = 0;
1671
1672         hw->adapter_stopped = 0;
1673
1674         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1675                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1676                              dev->data->port_id);
1677                 return -EINVAL;
1678         }
1679
1680         rte_intr_disable(intr_handle);
1681
1682         if ((rte_intr_cap_multiple(intr_handle) ||
1683              !RTE_ETH_DEV_SRIOV(dev).active) &&
1684             dev->data->dev_conf.intr_conf.rxq != 0) {
1685                 intr_vector = dev->data->nb_rx_queues;
1686                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1687                         return -1;
1688         }
1689
1690         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1691                 intr_handle->intr_vec =
1692                         rte_zmalloc("intr_vec",
1693                                     dev->data->nb_rx_queues * sizeof(int),
1694                                     0);
1695                 if (!intr_handle->intr_vec) {
1696                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1697                                      " intr_vec\n", dev->data->nb_rx_queues);
1698                         return -ENOMEM;
1699                 }
1700         }
1701
1702         /* Initialize VSI */
1703         ret = i40e_dev_rxtx_init(pf);
1704         if (ret != I40E_SUCCESS) {
1705                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1706                 goto err_up;
1707         }
1708
1709         /* Map queues with MSIX interrupt */
1710         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1711                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1712         i40e_vsi_queues_bind_intr(main_vsi);
1713         i40e_vsi_enable_queues_intr(main_vsi);
1714
1715         /* Map VMDQ VSI queues with MSIX interrupt */
1716         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1717                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1718                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1719                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1720         }
1721
1722         /* enable FDIR MSIX interrupt */
1723         if (pf->fdir.fdir_vsi) {
1724                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1725                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1726         }
1727
1728         /* Enable all queues which have been configured */
1729         ret = i40e_dev_switch_queues(pf, TRUE);
1730         if (ret != I40E_SUCCESS) {
1731                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1732                 goto err_up;
1733         }
1734
1735         /* Enable receiving broadcast packets */
1736         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1737         if (ret != I40E_SUCCESS)
1738                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1739
1740         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1741                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1742                                                 true, NULL);
1743                 if (ret != I40E_SUCCESS)
1744                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1745         }
1746
1747         /* Apply link configure */
1748         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1749                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1750                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1751                 PMD_DRV_LOG(ERR, "Invalid link setting");
1752                 goto err_up;
1753         }
1754         ret = i40e_apply_link_speed(dev);
1755         if (I40E_SUCCESS != ret) {
1756                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1757                 goto err_up;
1758         }
1759
1760         if (!rte_intr_allow_others(intr_handle)) {
1761                 rte_intr_callback_unregister(intr_handle,
1762                                              i40e_dev_interrupt_handler,
1763                                              (void *)dev);
1764                 /* configure and enable device interrupt */
1765                 i40e_pf_config_irq0(hw, FALSE);
1766                 i40e_pf_enable_irq0(hw);
1767
1768                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1769                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1770                                      " no intr multiplex\n");
1771         }
1772
1773         /* enable uio intr after callback register */
1774         rte_intr_enable(intr_handle);
1775
1776         return I40E_SUCCESS;
1777
1778 err_up:
1779         i40e_dev_switch_queues(pf, FALSE);
1780         i40e_dev_clear_queues(dev);
1781
1782         return ret;
1783 }
1784
1785 static void
1786 i40e_dev_stop(struct rte_eth_dev *dev)
1787 {
1788         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1789         struct i40e_vsi *main_vsi = pf->main_vsi;
1790         struct i40e_mirror_rule *p_mirror;
1791         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1792         int i;
1793
1794         /* Disable all queues */
1795         i40e_dev_switch_queues(pf, FALSE);
1796
1797         /* un-map queues with interrupt registers */
1798         i40e_vsi_disable_queues_intr(main_vsi);
1799         i40e_vsi_queues_unbind_intr(main_vsi);
1800
1801         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1802                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1803                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1804         }
1805
1806         if (pf->fdir.fdir_vsi) {
1807                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1808                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1809         }
1810         /* Clear all queues and release memory */
1811         i40e_dev_clear_queues(dev);
1812
1813         /* Set link down */
1814         i40e_dev_set_link_down(dev);
1815
1816         /* Remove all mirror rules */
1817         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1818                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1819                 rte_free(p_mirror);
1820         }
1821         pf->nb_mirror_rule = 0;
1822
1823         if (!rte_intr_allow_others(intr_handle))
1824                 /* resume to the default handler */
1825                 rte_intr_callback_register(intr_handle,
1826                                            i40e_dev_interrupt_handler,
1827                                            (void *)dev);
1828
1829         /* Clean datapath event and queue/vec mapping */
1830         rte_intr_efd_disable(intr_handle);
1831         if (intr_handle->intr_vec) {
1832                 rte_free(intr_handle->intr_vec);
1833                 intr_handle->intr_vec = NULL;
1834         }
1835 }
1836
1837 static void
1838 i40e_dev_close(struct rte_eth_dev *dev)
1839 {
1840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         uint32_t reg;
1843         int i;
1844
1845         PMD_INIT_FUNC_TRACE();
1846
1847         i40e_dev_stop(dev);
1848         hw->adapter_stopped = 1;
1849         i40e_dev_free_queues(dev);
1850
1851         /* Disable interrupt */
1852         i40e_pf_disable_irq0(hw);
1853         rte_intr_disable(&(dev->pci_dev->intr_handle));
1854
1855         /* shutdown and destroy the HMC */
1856         i40e_shutdown_lan_hmc(hw);
1857
1858         /* release all the existing VSIs and VEBs */
1859         i40e_fdir_teardown(pf);
1860         i40e_vsi_release(pf->main_vsi);
1861
1862         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1863                 i40e_vsi_release(pf->vmdq[i].vsi);
1864                 pf->vmdq[i].vsi = NULL;
1865         }
1866
1867         rte_free(pf->vmdq);
1868         pf->vmdq = NULL;
1869
1870         /* shutdown the adminq */
1871         i40e_aq_queue_shutdown(hw, true);
1872         i40e_shutdown_adminq(hw);
1873
1874         i40e_res_pool_destroy(&pf->qp_pool);
1875         i40e_res_pool_destroy(&pf->msix_pool);
1876
1877         /* force a PF reset to clean anything leftover */
1878         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1879         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1880                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1881         I40E_WRITE_FLUSH(hw);
1882 }
1883
1884 static void
1885 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1886 {
1887         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1888         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889         struct i40e_vsi *vsi = pf->main_vsi;
1890         int status;
1891
1892         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1893                                                      true, NULL, true);
1894         if (status != I40E_SUCCESS)
1895                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1896
1897         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1898                                                         TRUE, NULL);
1899         if (status != I40E_SUCCESS)
1900                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1901
1902 }
1903
1904 static void
1905 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_vsi *vsi = pf->main_vsi;
1910         int status;
1911
1912         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1913                                                      false, NULL, true);
1914         if (status != I40E_SUCCESS)
1915                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1916
1917         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1918                                                         false, NULL);
1919         if (status != I40E_SUCCESS)
1920                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1921 }
1922
1923 static void
1924 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1925 {
1926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct i40e_vsi *vsi = pf->main_vsi;
1929         int ret;
1930
1931         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1932         if (ret != I40E_SUCCESS)
1933                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1934 }
1935
1936 static void
1937 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1938 {
1939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct i40e_vsi *vsi = pf->main_vsi;
1942         int ret;
1943
1944         if (dev->data->promiscuous == 1)
1945                 return; /* must remain in all_multicast mode */
1946
1947         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1948                                 vsi->seid, FALSE, NULL);
1949         if (ret != I40E_SUCCESS)
1950                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1951 }
1952
1953 /*
1954  * Set device link up.
1955  */
1956 static int
1957 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1958 {
1959         /* re-apply link speed setting */
1960         return i40e_apply_link_speed(dev);
1961 }
1962
1963 /*
1964  * Set device link down.
1965  */
1966 static int
1967 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1968 {
1969         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1970         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972
1973         return i40e_phy_conf_link(hw, abilities, speed);
1974 }
1975
1976 int
1977 i40e_dev_link_update(struct rte_eth_dev *dev,
1978                      int wait_to_complete)
1979 {
1980 #define CHECK_INTERVAL 100  /* 100ms */
1981 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         struct i40e_link_status link_status;
1984         struct rte_eth_link link, old;
1985         int status;
1986         unsigned rep_cnt = MAX_REPEAT_TIME;
1987
1988         memset(&link, 0, sizeof(link));
1989         memset(&old, 0, sizeof(old));
1990         memset(&link_status, 0, sizeof(link_status));
1991         rte_i40e_dev_atomic_read_link_status(dev, &old);
1992
1993         do {
1994                 /* Get link status information from hardware */
1995                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1996                 if (status != I40E_SUCCESS) {
1997                         link.link_speed = ETH_SPEED_NUM_100M;
1998                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1999                         PMD_DRV_LOG(ERR, "Failed to get link info");
2000                         goto out;
2001                 }
2002
2003                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2004                 if (!wait_to_complete)
2005                         break;
2006
2007                 rte_delay_ms(CHECK_INTERVAL);
2008         } while (!link.link_status && rep_cnt--);
2009
2010         if (!link.link_status)
2011                 goto out;
2012
2013         /* i40e uses full duplex only */
2014         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2015
2016         /* Parse the link status */
2017         switch (link_status.link_speed) {
2018         case I40E_LINK_SPEED_100MB:
2019                 link.link_speed = ETH_SPEED_NUM_100M;
2020                 break;
2021         case I40E_LINK_SPEED_1GB:
2022                 link.link_speed = ETH_SPEED_NUM_1G;
2023                 break;
2024         case I40E_LINK_SPEED_10GB:
2025                 link.link_speed = ETH_SPEED_NUM_10G;
2026                 break;
2027         case I40E_LINK_SPEED_20GB:
2028                 link.link_speed = ETH_SPEED_NUM_20G;
2029                 break;
2030         case I40E_LINK_SPEED_40GB:
2031                 link.link_speed = ETH_SPEED_NUM_40G;
2032                 break;
2033         default:
2034                 link.link_speed = ETH_SPEED_NUM_100M;
2035                 break;
2036         }
2037
2038         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2039                         ETH_LINK_SPEED_FIXED);
2040
2041 out:
2042         rte_i40e_dev_atomic_write_link_status(dev, &link);
2043         if (link.link_status == old.link_status)
2044                 return -1;
2045
2046         return 0;
2047 }
2048
2049 /* Get all the statistics of a VSI */
2050 void
2051 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2052 {
2053         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2054         struct i40e_eth_stats *nes = &vsi->eth_stats;
2055         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2057
2058         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2059                             vsi->offset_loaded, &oes->rx_bytes,
2060                             &nes->rx_bytes);
2061         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2062                             vsi->offset_loaded, &oes->rx_unicast,
2063                             &nes->rx_unicast);
2064         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2065                             vsi->offset_loaded, &oes->rx_multicast,
2066                             &nes->rx_multicast);
2067         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2068                             vsi->offset_loaded, &oes->rx_broadcast,
2069                             &nes->rx_broadcast);
2070         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2071                             &oes->rx_discards, &nes->rx_discards);
2072         /* GLV_REPC not supported */
2073         /* GLV_RMPC not supported */
2074         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2075                             &oes->rx_unknown_protocol,
2076                             &nes->rx_unknown_protocol);
2077         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2078                             vsi->offset_loaded, &oes->tx_bytes,
2079                             &nes->tx_bytes);
2080         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2081                             vsi->offset_loaded, &oes->tx_unicast,
2082                             &nes->tx_unicast);
2083         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2084                             vsi->offset_loaded, &oes->tx_multicast,
2085                             &nes->tx_multicast);
2086         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2087                             vsi->offset_loaded,  &oes->tx_broadcast,
2088                             &nes->tx_broadcast);
2089         /* GLV_TDPC not supported */
2090         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2091                             &oes->tx_errors, &nes->tx_errors);
2092         vsi->offset_loaded = true;
2093
2094         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2095                     vsi->vsi_id);
2096         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2097         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2098         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2099         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2100         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2101         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2102                     nes->rx_unknown_protocol);
2103         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2104         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2105         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2106         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2107         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2108         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2109         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2110                     vsi->vsi_id);
2111 }
2112
2113 static void
2114 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2115 {
2116         unsigned int i;
2117         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2118         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2119
2120         /* Get statistics of struct i40e_eth_stats */
2121         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2122                             I40E_GLPRT_GORCL(hw->port),
2123                             pf->offset_loaded, &os->eth.rx_bytes,
2124                             &ns->eth.rx_bytes);
2125         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2126                             I40E_GLPRT_UPRCL(hw->port),
2127                             pf->offset_loaded, &os->eth.rx_unicast,
2128                             &ns->eth.rx_unicast);
2129         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2130                             I40E_GLPRT_MPRCL(hw->port),
2131                             pf->offset_loaded, &os->eth.rx_multicast,
2132                             &ns->eth.rx_multicast);
2133         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2134                             I40E_GLPRT_BPRCL(hw->port),
2135                             pf->offset_loaded, &os->eth.rx_broadcast,
2136                             &ns->eth.rx_broadcast);
2137         /* Workaround: CRC size should not be included in byte statistics,
2138          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2139          */
2140         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2141                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2142
2143         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2144                             pf->offset_loaded, &os->eth.rx_discards,
2145                             &ns->eth.rx_discards);
2146         /* GLPRT_REPC not supported */
2147         /* GLPRT_RMPC not supported */
2148         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2149                             pf->offset_loaded,
2150                             &os->eth.rx_unknown_protocol,
2151                             &ns->eth.rx_unknown_protocol);
2152         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2153                             I40E_GLPRT_GOTCL(hw->port),
2154                             pf->offset_loaded, &os->eth.tx_bytes,
2155                             &ns->eth.tx_bytes);
2156         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2157                             I40E_GLPRT_UPTCL(hw->port),
2158                             pf->offset_loaded, &os->eth.tx_unicast,
2159                             &ns->eth.tx_unicast);
2160         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2161                             I40E_GLPRT_MPTCL(hw->port),
2162                             pf->offset_loaded, &os->eth.tx_multicast,
2163                             &ns->eth.tx_multicast);
2164         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2165                             I40E_GLPRT_BPTCL(hw->port),
2166                             pf->offset_loaded, &os->eth.tx_broadcast,
2167                             &ns->eth.tx_broadcast);
2168         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2169                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2170         /* GLPRT_TEPC not supported */
2171
2172         /* additional port specific stats */
2173         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2174                             pf->offset_loaded, &os->tx_dropped_link_down,
2175                             &ns->tx_dropped_link_down);
2176         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2177                             pf->offset_loaded, &os->crc_errors,
2178                             &ns->crc_errors);
2179         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2180                             pf->offset_loaded, &os->illegal_bytes,
2181                             &ns->illegal_bytes);
2182         /* GLPRT_ERRBC not supported */
2183         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2184                             pf->offset_loaded, &os->mac_local_faults,
2185                             &ns->mac_local_faults);
2186         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2187                             pf->offset_loaded, &os->mac_remote_faults,
2188                             &ns->mac_remote_faults);
2189         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2190                             pf->offset_loaded, &os->rx_length_errors,
2191                             &ns->rx_length_errors);
2192         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2193                             pf->offset_loaded, &os->link_xon_rx,
2194                             &ns->link_xon_rx);
2195         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2196                             pf->offset_loaded, &os->link_xoff_rx,
2197                             &ns->link_xoff_rx);
2198         for (i = 0; i < 8; i++) {
2199                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2200                                     pf->offset_loaded,
2201                                     &os->priority_xon_rx[i],
2202                                     &ns->priority_xon_rx[i]);
2203                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2204                                     pf->offset_loaded,
2205                                     &os->priority_xoff_rx[i],
2206                                     &ns->priority_xoff_rx[i]);
2207         }
2208         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2209                             pf->offset_loaded, &os->link_xon_tx,
2210                             &ns->link_xon_tx);
2211         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2212                             pf->offset_loaded, &os->link_xoff_tx,
2213                             &ns->link_xoff_tx);
2214         for (i = 0; i < 8; i++) {
2215                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2216                                     pf->offset_loaded,
2217                                     &os->priority_xon_tx[i],
2218                                     &ns->priority_xon_tx[i]);
2219                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2220                                     pf->offset_loaded,
2221                                     &os->priority_xoff_tx[i],
2222                                     &ns->priority_xoff_tx[i]);
2223                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2224                                     pf->offset_loaded,
2225                                     &os->priority_xon_2_xoff[i],
2226                                     &ns->priority_xon_2_xoff[i]);
2227         }
2228         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2229                             I40E_GLPRT_PRC64L(hw->port),
2230                             pf->offset_loaded, &os->rx_size_64,
2231                             &ns->rx_size_64);
2232         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2233                             I40E_GLPRT_PRC127L(hw->port),
2234                             pf->offset_loaded, &os->rx_size_127,
2235                             &ns->rx_size_127);
2236         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2237                             I40E_GLPRT_PRC255L(hw->port),
2238                             pf->offset_loaded, &os->rx_size_255,
2239                             &ns->rx_size_255);
2240         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2241                             I40E_GLPRT_PRC511L(hw->port),
2242                             pf->offset_loaded, &os->rx_size_511,
2243                             &ns->rx_size_511);
2244         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2245                             I40E_GLPRT_PRC1023L(hw->port),
2246                             pf->offset_loaded, &os->rx_size_1023,
2247                             &ns->rx_size_1023);
2248         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2249                             I40E_GLPRT_PRC1522L(hw->port),
2250                             pf->offset_loaded, &os->rx_size_1522,
2251                             &ns->rx_size_1522);
2252         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2253                             I40E_GLPRT_PRC9522L(hw->port),
2254                             pf->offset_loaded, &os->rx_size_big,
2255                             &ns->rx_size_big);
2256         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2257                             pf->offset_loaded, &os->rx_undersize,
2258                             &ns->rx_undersize);
2259         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2260                             pf->offset_loaded, &os->rx_fragments,
2261                             &ns->rx_fragments);
2262         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2263                             pf->offset_loaded, &os->rx_oversize,
2264                             &ns->rx_oversize);
2265         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2266                             pf->offset_loaded, &os->rx_jabber,
2267                             &ns->rx_jabber);
2268         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2269                             I40E_GLPRT_PTC64L(hw->port),
2270                             pf->offset_loaded, &os->tx_size_64,
2271                             &ns->tx_size_64);
2272         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2273                             I40E_GLPRT_PTC127L(hw->port),
2274                             pf->offset_loaded, &os->tx_size_127,
2275                             &ns->tx_size_127);
2276         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2277                             I40E_GLPRT_PTC255L(hw->port),
2278                             pf->offset_loaded, &os->tx_size_255,
2279                             &ns->tx_size_255);
2280         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2281                             I40E_GLPRT_PTC511L(hw->port),
2282                             pf->offset_loaded, &os->tx_size_511,
2283                             &ns->tx_size_511);
2284         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2285                             I40E_GLPRT_PTC1023L(hw->port),
2286                             pf->offset_loaded, &os->tx_size_1023,
2287                             &ns->tx_size_1023);
2288         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2289                             I40E_GLPRT_PTC1522L(hw->port),
2290                             pf->offset_loaded, &os->tx_size_1522,
2291                             &ns->tx_size_1522);
2292         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2293                             I40E_GLPRT_PTC9522L(hw->port),
2294                             pf->offset_loaded, &os->tx_size_big,
2295                             &ns->tx_size_big);
2296         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2297                            pf->offset_loaded,
2298                            &os->fd_sb_match, &ns->fd_sb_match);
2299         /* GLPRT_MSPDC not supported */
2300         /* GLPRT_XEC not supported */
2301
2302         pf->offset_loaded = true;
2303
2304         if (pf->main_vsi)
2305                 i40e_update_vsi_stats(pf->main_vsi);
2306 }
2307
2308 /* Get all statistics of a port */
2309 static void
2310 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2311 {
2312         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2315         unsigned i;
2316
2317         /* call read registers - updates values, now write them to struct */
2318         i40e_read_stats_registers(pf, hw);
2319
2320         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2321                         pf->main_vsi->eth_stats.rx_multicast +
2322                         pf->main_vsi->eth_stats.rx_broadcast -
2323                         pf->main_vsi->eth_stats.rx_discards;
2324         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2325                         pf->main_vsi->eth_stats.tx_multicast +
2326                         pf->main_vsi->eth_stats.tx_broadcast;
2327         stats->ibytes   = ns->eth.rx_bytes;
2328         stats->obytes   = ns->eth.tx_bytes;
2329         stats->oerrors  = ns->eth.tx_errors +
2330                         pf->main_vsi->eth_stats.tx_errors;
2331
2332         /* Rx Errors */
2333         stats->imissed  = ns->eth.rx_discards +
2334                         pf->main_vsi->eth_stats.rx_discards;
2335         stats->ierrors  = ns->crc_errors +
2336                         ns->rx_length_errors + ns->rx_undersize +
2337                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2338
2339         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2340         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2341         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2342         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2343         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2344         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2345         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2346                     ns->eth.rx_unknown_protocol);
2347         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2348         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2349         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2350         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2351         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2352         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2353
2354         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2355                     ns->tx_dropped_link_down);
2356         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2357         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2358                     ns->illegal_bytes);
2359         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2360         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2361                     ns->mac_local_faults);
2362         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2363                     ns->mac_remote_faults);
2364         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2365                     ns->rx_length_errors);
2366         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2367         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2368         for (i = 0; i < 8; i++) {
2369                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2370                                 i, ns->priority_xon_rx[i]);
2371                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2372                                 i, ns->priority_xoff_rx[i]);
2373         }
2374         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2375         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2376         for (i = 0; i < 8; i++) {
2377                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2378                                 i, ns->priority_xon_tx[i]);
2379                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2380                                 i, ns->priority_xoff_tx[i]);
2381                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2382                                 i, ns->priority_xon_2_xoff[i]);
2383         }
2384         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2385         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2386         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2387         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2388         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2389         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2390         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2391         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2392         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2393         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2394         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2395         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2396         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2397         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2398         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2399         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2400         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2401         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2402         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2403                         ns->mac_short_packet_dropped);
2404         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2405                     ns->checksum_error);
2406         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2407         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2408 }
2409
2410 /* Reset the statistics */
2411 static void
2412 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2413 {
2414         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416
2417         /* Mark PF and VSI stats to update the offset, aka "reset" */
2418         pf->offset_loaded = false;
2419         if (pf->main_vsi)
2420                 pf->main_vsi->offset_loaded = false;
2421
2422         /* read the stats, reading current register values into offset */
2423         i40e_read_stats_registers(pf, hw);
2424 }
2425
2426 static uint32_t
2427 i40e_xstats_calc_num(void)
2428 {
2429         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2430                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2431                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2432 }
2433
2434 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2435                                      struct rte_eth_xstat_name *xstats_names,
2436                                      __rte_unused unsigned limit)
2437 {
2438         unsigned count = 0;
2439         unsigned i, prio;
2440
2441         if (xstats_names == NULL)
2442                 return i40e_xstats_calc_num();
2443
2444         /* Note: limit checked in rte_eth_xstats_names() */
2445
2446         /* Get stats from i40e_eth_stats struct */
2447         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2448                 snprintf(xstats_names[count].name,
2449                          sizeof(xstats_names[count].name),
2450                          "%s", rte_i40e_stats_strings[i].name);
2451                 count++;
2452         }
2453
2454         /* Get individiual stats from i40e_hw_port struct */
2455         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2456                 snprintf(xstats_names[count].name,
2457                         sizeof(xstats_names[count].name),
2458                          "%s", rte_i40e_hw_port_strings[i].name);
2459                 count++;
2460         }
2461
2462         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2463                 for (prio = 0; prio < 8; prio++) {
2464                         snprintf(xstats_names[count].name,
2465                                  sizeof(xstats_names[count].name),
2466                                  "rx_priority%u_%s", prio,
2467                                  rte_i40e_rxq_prio_strings[i].name);
2468                         count++;
2469                 }
2470         }
2471
2472         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2473                 for (prio = 0; prio < 8; prio++) {
2474                         snprintf(xstats_names[count].name,
2475                                  sizeof(xstats_names[count].name),
2476                                  "tx_priority%u_%s", prio,
2477                                  rte_i40e_txq_prio_strings[i].name);
2478                         count++;
2479                 }
2480         }
2481         return count;
2482 }
2483
2484 static int
2485 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2486                     unsigned n)
2487 {
2488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490         unsigned i, count, prio;
2491         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2492
2493         count = i40e_xstats_calc_num();
2494         if (n < count)
2495                 return count;
2496
2497         i40e_read_stats_registers(pf, hw);
2498
2499         if (xstats == NULL)
2500                 return 0;
2501
2502         count = 0;
2503
2504         /* Get stats from i40e_eth_stats struct */
2505         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2506                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2507                         rte_i40e_stats_strings[i].offset);
2508                 count++;
2509         }
2510
2511         /* Get individiual stats from i40e_hw_port struct */
2512         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2513                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2514                         rte_i40e_hw_port_strings[i].offset);
2515                 count++;
2516         }
2517
2518         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2519                 for (prio = 0; prio < 8; prio++) {
2520                         xstats[count].value =
2521                                 *(uint64_t *)(((char *)hw_stats) +
2522                                 rte_i40e_rxq_prio_strings[i].offset +
2523                                 (sizeof(uint64_t) * prio));
2524                         count++;
2525                 }
2526         }
2527
2528         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2529                 for (prio = 0; prio < 8; prio++) {
2530                         xstats[count].value =
2531                                 *(uint64_t *)(((char *)hw_stats) +
2532                                 rte_i40e_txq_prio_strings[i].offset +
2533                                 (sizeof(uint64_t) * prio));
2534                         count++;
2535                 }
2536         }
2537
2538         return count;
2539 }
2540
2541 static int
2542 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2543                                  __rte_unused uint16_t queue_id,
2544                                  __rte_unused uint8_t stat_idx,
2545                                  __rte_unused uint8_t is_rx)
2546 {
2547         PMD_INIT_FUNC_TRACE();
2548
2549         return -ENOSYS;
2550 }
2551
2552 static void
2553 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2554 {
2555         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2556         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557         struct i40e_vsi *vsi = pf->main_vsi;
2558
2559         dev_info->max_rx_queues = vsi->nb_qps;
2560         dev_info->max_tx_queues = vsi->nb_qps;
2561         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2562         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2563         dev_info->max_mac_addrs = vsi->max_macaddrs;
2564         dev_info->max_vfs = dev->pci_dev->max_vfs;
2565         dev_info->rx_offload_capa =
2566                 DEV_RX_OFFLOAD_VLAN_STRIP |
2567                 DEV_RX_OFFLOAD_QINQ_STRIP |
2568                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2569                 DEV_RX_OFFLOAD_UDP_CKSUM |
2570                 DEV_RX_OFFLOAD_TCP_CKSUM;
2571         dev_info->tx_offload_capa =
2572                 DEV_TX_OFFLOAD_VLAN_INSERT |
2573                 DEV_TX_OFFLOAD_QINQ_INSERT |
2574                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2575                 DEV_TX_OFFLOAD_UDP_CKSUM |
2576                 DEV_TX_OFFLOAD_TCP_CKSUM |
2577                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2578                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2579                 DEV_TX_OFFLOAD_TCP_TSO;
2580         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2581                                                 sizeof(uint32_t);
2582         dev_info->reta_size = pf->hash_lut_size;
2583         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2584
2585         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2586                 .rx_thresh = {
2587                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2588                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2589                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2590                 },
2591                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2592                 .rx_drop_en = 0,
2593         };
2594
2595         dev_info->default_txconf = (struct rte_eth_txconf) {
2596                 .tx_thresh = {
2597                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2598                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2599                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2600                 },
2601                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2602                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2603                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2604                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2605         };
2606
2607         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2608                 .nb_max = I40E_MAX_RING_DESC,
2609                 .nb_min = I40E_MIN_RING_DESC,
2610                 .nb_align = I40E_ALIGN_RING_DESC,
2611         };
2612
2613         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2614                 .nb_max = I40E_MAX_RING_DESC,
2615                 .nb_min = I40E_MIN_RING_DESC,
2616                 .nb_align = I40E_ALIGN_RING_DESC,
2617         };
2618
2619         if (pf->flags & I40E_FLAG_VMDQ) {
2620                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2621                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2622                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2623                                                 pf->max_nb_vmdq_vsi;
2624                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2625                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2626                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2627         }
2628
2629         if (i40e_is_40G_device(hw->device_id))
2630                 /* For XL710 */
2631                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2632         else
2633                 /* For X710 */
2634                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2635 }
2636
2637 static int
2638 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2639 {
2640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2641         struct i40e_vsi *vsi = pf->main_vsi;
2642         PMD_INIT_FUNC_TRACE();
2643
2644         if (on)
2645                 return i40e_vsi_add_vlan(vsi, vlan_id);
2646         else
2647                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2648 }
2649
2650 static int
2651 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2652                    enum rte_vlan_type vlan_type,
2653                    uint16_t tpid)
2654 {
2655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656         uint64_t reg_r = 0, reg_w = 0;
2657         uint16_t reg_id = 0;
2658         int ret = 0;
2659         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2660
2661         switch (vlan_type) {
2662         case ETH_VLAN_TYPE_OUTER:
2663                 if (qinq)
2664                         reg_id = 2;
2665                 else
2666                         reg_id = 3;
2667                 break;
2668         case ETH_VLAN_TYPE_INNER:
2669                 if (qinq)
2670                         reg_id = 3;
2671                 else {
2672                         ret = -EINVAL;
2673                         PMD_DRV_LOG(ERR,
2674                                 "Unsupported vlan type in single vlan.\n");
2675                         return ret;
2676                 }
2677                 break;
2678         default:
2679                 ret = -EINVAL;
2680                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2681                 return ret;
2682         }
2683         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2684                                           &reg_r, NULL);
2685         if (ret != I40E_SUCCESS) {
2686                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2687                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2688                 ret = -EIO;
2689                 return ret;
2690         }
2691         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2692                     "0x%08"PRIx64"", reg_id, reg_r);
2693
2694         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2695         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2696         if (reg_r == reg_w) {
2697                 ret = 0;
2698                 PMD_DRV_LOG(DEBUG, "No need to write");
2699                 return ret;
2700         }
2701
2702         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2703                                            reg_w, NULL);
2704         if (ret != I40E_SUCCESS) {
2705                 ret = -EIO;
2706                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2707                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2708                 return ret;
2709         }
2710         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2711                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2712
2713         return ret;
2714 }
2715
2716 static void
2717 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2718 {
2719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2720         struct i40e_vsi *vsi = pf->main_vsi;
2721
2722         if (mask & ETH_VLAN_FILTER_MASK) {
2723                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2724                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2725                 else
2726                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2727         }
2728
2729         if (mask & ETH_VLAN_STRIP_MASK) {
2730                 /* Enable or disable VLAN stripping */
2731                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2732                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2733                 else
2734                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2735         }
2736
2737         if (mask & ETH_VLAN_EXTEND_MASK) {
2738                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2739                         i40e_vsi_config_double_vlan(vsi, TRUE);
2740                         /* Set global registers with default ether type value */
2741                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2742                                            ETHER_TYPE_VLAN);
2743                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2744                                            ETHER_TYPE_VLAN);
2745                 }
2746                 else
2747                         i40e_vsi_config_double_vlan(vsi, FALSE);
2748         }
2749 }
2750
2751 static void
2752 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2753                           __rte_unused uint16_t queue,
2754                           __rte_unused int on)
2755 {
2756         PMD_INIT_FUNC_TRACE();
2757 }
2758
2759 static int
2760 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2761 {
2762         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2763         struct i40e_vsi *vsi = pf->main_vsi;
2764         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2765         struct i40e_vsi_vlan_pvid_info info;
2766
2767         memset(&info, 0, sizeof(info));
2768         info.on = on;
2769         if (info.on)
2770                 info.config.pvid = pvid;
2771         else {
2772                 info.config.reject.tagged =
2773                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2774                 info.config.reject.untagged =
2775                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2776         }
2777
2778         return i40e_vsi_vlan_pvid_set(vsi, &info);
2779 }
2780
2781 static int
2782 i40e_dev_led_on(struct rte_eth_dev *dev)
2783 {
2784         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785         uint32_t mode = i40e_led_get(hw);
2786
2787         if (mode == 0)
2788                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2789
2790         return 0;
2791 }
2792
2793 static int
2794 i40e_dev_led_off(struct rte_eth_dev *dev)
2795 {
2796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2797         uint32_t mode = i40e_led_get(hw);
2798
2799         if (mode != 0)
2800                 i40e_led_set(hw, 0, false);
2801
2802         return 0;
2803 }
2804
2805 static int
2806 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2807 {
2808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2810
2811         fc_conf->pause_time = pf->fc_conf.pause_time;
2812         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2813         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2814
2815          /* Return current mode according to actual setting*/
2816         switch (hw->fc.current_mode) {
2817         case I40E_FC_FULL:
2818                 fc_conf->mode = RTE_FC_FULL;
2819                 break;
2820         case I40E_FC_TX_PAUSE:
2821                 fc_conf->mode = RTE_FC_TX_PAUSE;
2822                 break;
2823         case I40E_FC_RX_PAUSE:
2824                 fc_conf->mode = RTE_FC_RX_PAUSE;
2825                 break;
2826         case I40E_FC_NONE:
2827         default:
2828                 fc_conf->mode = RTE_FC_NONE;
2829         };
2830
2831         return 0;
2832 }
2833
2834 static int
2835 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2836 {
2837         uint32_t mflcn_reg, fctrl_reg, reg;
2838         uint32_t max_high_water;
2839         uint8_t i, aq_failure;
2840         int err;
2841         struct i40e_hw *hw;
2842         struct i40e_pf *pf;
2843         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2844                 [RTE_FC_NONE] = I40E_FC_NONE,
2845                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2846                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2847                 [RTE_FC_FULL] = I40E_FC_FULL
2848         };
2849
2850         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2851
2852         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2853         if ((fc_conf->high_water > max_high_water) ||
2854                         (fc_conf->high_water < fc_conf->low_water)) {
2855                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2856                         "High_water must <= %d.", max_high_water);
2857                 return -EINVAL;
2858         }
2859
2860         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2862         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2863
2864         pf->fc_conf.pause_time = fc_conf->pause_time;
2865         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2866         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2867
2868         PMD_INIT_FUNC_TRACE();
2869
2870         /* All the link flow control related enable/disable register
2871          * configuration is handle by the F/W
2872          */
2873         err = i40e_set_fc(hw, &aq_failure, true);
2874         if (err < 0)
2875                 return -ENOSYS;
2876
2877         if (i40e_is_40G_device(hw->device_id)) {
2878                 /* Configure flow control refresh threshold,
2879                  * the value for stat_tx_pause_refresh_timer[8]
2880                  * is used for global pause operation.
2881                  */
2882
2883                 I40E_WRITE_REG(hw,
2884                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2885                                pf->fc_conf.pause_time);
2886
2887                 /* configure the timer value included in transmitted pause
2888                  * frame,
2889                  * the value for stat_tx_pause_quanta[8] is used for global
2890                  * pause operation
2891                  */
2892                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2893                                pf->fc_conf.pause_time);
2894
2895                 fctrl_reg = I40E_READ_REG(hw,
2896                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2897
2898                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2899                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2900                 else
2901                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2902
2903                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2904                                fctrl_reg);
2905         } else {
2906                 /* Configure pause time (2 TCs per register) */
2907                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2908                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2909                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2910
2911                 /* Configure flow control refresh threshold value */
2912                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2913                                pf->fc_conf.pause_time / 2);
2914
2915                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2916
2917                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2918                  *depending on configuration
2919                  */
2920                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2921                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2922                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2923                 } else {
2924                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2925                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2926                 }
2927
2928                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2929         }
2930
2931         /* config the water marker both based on the packets and bytes */
2932         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2933                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2934                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2935         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2936                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2937                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2938         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2939                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2940                        << I40E_KILOSHIFT);
2941         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2942                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2943                        << I40E_KILOSHIFT);
2944
2945         I40E_WRITE_FLUSH(hw);
2946
2947         return 0;
2948 }
2949
2950 static int
2951 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2952                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2953 {
2954         PMD_INIT_FUNC_TRACE();
2955
2956         return -ENOSYS;
2957 }
2958
2959 /* Add a MAC address, and update filters */
2960 static void
2961 i40e_macaddr_add(struct rte_eth_dev *dev,
2962                  struct ether_addr *mac_addr,
2963                  __rte_unused uint32_t index,
2964                  uint32_t pool)
2965 {
2966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2967         struct i40e_mac_filter_info mac_filter;
2968         struct i40e_vsi *vsi;
2969         int ret;
2970
2971         /* If VMDQ not enabled or configured, return */
2972         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2973                           !pf->nb_cfg_vmdq_vsi)) {
2974                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2975                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2976                         pool);
2977                 return;
2978         }
2979
2980         if (pool > pf->nb_cfg_vmdq_vsi) {
2981                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2982                                 pool, pf->nb_cfg_vmdq_vsi);
2983                 return;
2984         }
2985
2986         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2987         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2988                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2989         else
2990                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2991
2992         if (pool == 0)
2993                 vsi = pf->main_vsi;
2994         else
2995                 vsi = pf->vmdq[pool - 1].vsi;
2996
2997         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2998         if (ret != I40E_SUCCESS) {
2999                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3000                 return;
3001         }
3002 }
3003
3004 /* Remove a MAC address, and update filters */
3005 static void
3006 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3007 {
3008         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3009         struct i40e_vsi *vsi;
3010         struct rte_eth_dev_data *data = dev->data;
3011         struct ether_addr *macaddr;
3012         int ret;
3013         uint32_t i;
3014         uint64_t pool_sel;
3015
3016         macaddr = &(data->mac_addrs[index]);
3017
3018         pool_sel = dev->data->mac_pool_sel[index];
3019
3020         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3021                 if (pool_sel & (1ULL << i)) {
3022                         if (i == 0)
3023                                 vsi = pf->main_vsi;
3024                         else {
3025                                 /* No VMDQ pool enabled or configured */
3026                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3027                                         (i > pf->nb_cfg_vmdq_vsi)) {
3028                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3029                                                         "/configured");
3030                                         return;
3031                                 }
3032                                 vsi = pf->vmdq[i - 1].vsi;
3033                         }
3034                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3035
3036                         if (ret) {
3037                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3038                                 return;
3039                         }
3040                 }
3041         }
3042 }
3043
3044 /* Set perfect match or hash match of MAC and VLAN for a VF */
3045 static int
3046 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3047                  struct rte_eth_mac_filter *filter,
3048                  bool add)
3049 {
3050         struct i40e_hw *hw;
3051         struct i40e_mac_filter_info mac_filter;
3052         struct ether_addr old_mac;
3053         struct ether_addr *new_mac;
3054         struct i40e_pf_vf *vf = NULL;
3055         uint16_t vf_id;
3056         int ret;
3057
3058         if (pf == NULL) {
3059                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3060                 return -EINVAL;
3061         }
3062         hw = I40E_PF_TO_HW(pf);
3063
3064         if (filter == NULL) {
3065                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3066                 return -EINVAL;
3067         }
3068
3069         new_mac = &filter->mac_addr;
3070
3071         if (is_zero_ether_addr(new_mac)) {
3072                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3073                 return -EINVAL;
3074         }
3075
3076         vf_id = filter->dst_id;
3077
3078         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3079                 PMD_DRV_LOG(ERR, "Invalid argument.");
3080                 return -EINVAL;
3081         }
3082         vf = &pf->vfs[vf_id];
3083
3084         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3085                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3086                 return -EINVAL;
3087         }
3088
3089         if (add) {
3090                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3091                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3092                                 ETHER_ADDR_LEN);
3093                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3094                                  ETHER_ADDR_LEN);
3095
3096                 mac_filter.filter_type = filter->filter_type;
3097                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3098                 if (ret != I40E_SUCCESS) {
3099                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3100                         return -1;
3101                 }
3102                 ether_addr_copy(new_mac, &pf->dev_addr);
3103         } else {
3104                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3105                                 ETHER_ADDR_LEN);
3106                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3107                 if (ret != I40E_SUCCESS) {
3108                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3109                         return -1;
3110                 }
3111
3112                 /* Clear device address as it has been removed */
3113                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3114                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3115         }
3116
3117         return 0;
3118 }
3119
3120 /* MAC filter handle */
3121 static int
3122 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3123                 void *arg)
3124 {
3125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3126         struct rte_eth_mac_filter *filter;
3127         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3128         int ret = I40E_NOT_SUPPORTED;
3129
3130         filter = (struct rte_eth_mac_filter *)(arg);
3131
3132         switch (filter_op) {
3133         case RTE_ETH_FILTER_NOP:
3134                 ret = I40E_SUCCESS;
3135                 break;
3136         case RTE_ETH_FILTER_ADD:
3137                 i40e_pf_disable_irq0(hw);
3138                 if (filter->is_vf)
3139                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3140                 i40e_pf_enable_irq0(hw);
3141                 break;
3142         case RTE_ETH_FILTER_DELETE:
3143                 i40e_pf_disable_irq0(hw);
3144                 if (filter->is_vf)
3145                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3146                 i40e_pf_enable_irq0(hw);
3147                 break;
3148         default:
3149                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3150                 ret = I40E_ERR_PARAM;
3151                 break;
3152         }
3153
3154         return ret;
3155 }
3156
3157 static int
3158 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3159 {
3160         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3161         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3162         int ret;
3163
3164         if (!lut)
3165                 return -EINVAL;
3166
3167         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3168                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3169                                           lut, lut_size);
3170                 if (ret) {
3171                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3172                         return ret;
3173                 }
3174         } else {
3175                 uint32_t *lut_dw = (uint32_t *)lut;
3176                 uint16_t i, lut_size_dw = lut_size / 4;
3177
3178                 for (i = 0; i < lut_size_dw; i++)
3179                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3180         }
3181
3182         return 0;
3183 }
3184
3185 static int
3186 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3187 {
3188         struct i40e_pf *pf;
3189         struct i40e_hw *hw;
3190         int ret;
3191
3192         if (!vsi || !lut)
3193                 return -EINVAL;
3194
3195         pf = I40E_VSI_TO_PF(vsi);
3196         hw = I40E_VSI_TO_HW(vsi);
3197
3198         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3199                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3200                                           lut, lut_size);
3201                 if (ret) {
3202                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3203                         return ret;
3204                 }
3205         } else {
3206                 uint32_t *lut_dw = (uint32_t *)lut;
3207                 uint16_t i, lut_size_dw = lut_size / 4;
3208
3209                 for (i = 0; i < lut_size_dw; i++)
3210                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3211                 I40E_WRITE_FLUSH(hw);
3212         }
3213
3214         return 0;
3215 }
3216
3217 static int
3218 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3219                          struct rte_eth_rss_reta_entry64 *reta_conf,
3220                          uint16_t reta_size)
3221 {
3222         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3223         uint16_t i, lut_size = pf->hash_lut_size;
3224         uint16_t idx, shift;
3225         uint8_t *lut;
3226         int ret;
3227
3228         if (reta_size != lut_size ||
3229                 reta_size > ETH_RSS_RETA_SIZE_512) {
3230                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3231                         "(%d) doesn't match the number hardware can supported "
3232                                         "(%d)\n", reta_size, lut_size);
3233                 return -EINVAL;
3234         }
3235
3236         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3237         if (!lut) {
3238                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3239                 return -ENOMEM;
3240         }
3241         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3242         if (ret)
3243                 goto out;
3244         for (i = 0; i < reta_size; i++) {
3245                 idx = i / RTE_RETA_GROUP_SIZE;
3246                 shift = i % RTE_RETA_GROUP_SIZE;
3247                 if (reta_conf[idx].mask & (1ULL << shift))
3248                         lut[i] = reta_conf[idx].reta[shift];
3249         }
3250         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3251
3252 out:
3253         rte_free(lut);
3254
3255         return ret;
3256 }
3257
3258 static int
3259 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3260                         struct rte_eth_rss_reta_entry64 *reta_conf,
3261                         uint16_t reta_size)
3262 {
3263         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3264         uint16_t i, lut_size = pf->hash_lut_size;
3265         uint16_t idx, shift;
3266         uint8_t *lut;
3267         int ret;
3268
3269         if (reta_size != lut_size ||
3270                 reta_size > ETH_RSS_RETA_SIZE_512) {
3271                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3272                         "(%d) doesn't match the number hardware can supported "
3273                                         "(%d)\n", reta_size, lut_size);
3274                 return -EINVAL;
3275         }
3276
3277         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3278         if (!lut) {
3279                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3280                 return -ENOMEM;
3281         }
3282
3283         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3284         if (ret)
3285                 goto out;
3286         for (i = 0; i < reta_size; i++) {
3287                 idx = i / RTE_RETA_GROUP_SIZE;
3288                 shift = i % RTE_RETA_GROUP_SIZE;
3289                 if (reta_conf[idx].mask & (1ULL << shift))
3290                         reta_conf[idx].reta[shift] = lut[i];
3291         }
3292
3293 out:
3294         rte_free(lut);
3295
3296         return ret;
3297 }
3298
3299 /**
3300  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3301  * @hw:   pointer to the HW structure
3302  * @mem:  pointer to mem struct to fill out
3303  * @size: size of memory requested
3304  * @alignment: what to align the allocation to
3305  **/
3306 enum i40e_status_code
3307 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3308                         struct i40e_dma_mem *mem,
3309                         u64 size,
3310                         u32 alignment)
3311 {
3312         const struct rte_memzone *mz = NULL;
3313         char z_name[RTE_MEMZONE_NAMESIZE];
3314
3315         if (!mem)
3316                 return I40E_ERR_PARAM;
3317
3318         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3319         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3320                                          alignment, RTE_PGSIZE_2M);
3321         if (!mz)
3322                 return I40E_ERR_NO_MEMORY;
3323
3324         mem->size = size;
3325         mem->va = mz->addr;
3326         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3327         mem->zone = (const void *)mz;
3328         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3329                     "%"PRIu64, mz->name, mem->pa);
3330
3331         return I40E_SUCCESS;
3332 }
3333
3334 /**
3335  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3336  * @hw:   pointer to the HW structure
3337  * @mem:  ptr to mem struct to free
3338  **/
3339 enum i40e_status_code
3340 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3341                     struct i40e_dma_mem *mem)
3342 {
3343         if (!mem)
3344                 return I40E_ERR_PARAM;
3345
3346         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3347                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3348                     mem->pa);
3349         rte_memzone_free((const struct rte_memzone *)mem->zone);
3350         mem->zone = NULL;
3351         mem->va = NULL;
3352         mem->pa = (u64)0;
3353
3354         return I40E_SUCCESS;
3355 }
3356
3357 /**
3358  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3359  * @hw:   pointer to the HW structure
3360  * @mem:  pointer to mem struct to fill out
3361  * @size: size of memory requested
3362  **/
3363 enum i40e_status_code
3364 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3365                          struct i40e_virt_mem *mem,
3366                          u32 size)
3367 {
3368         if (!mem)
3369                 return I40E_ERR_PARAM;
3370
3371         mem->size = size;
3372         mem->va = rte_zmalloc("i40e", size, 0);
3373
3374         if (mem->va)
3375                 return I40E_SUCCESS;
3376         else
3377                 return I40E_ERR_NO_MEMORY;
3378 }
3379
3380 /**
3381  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3382  * @hw:   pointer to the HW structure
3383  * @mem:  pointer to mem struct to free
3384  **/
3385 enum i40e_status_code
3386 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3387                      struct i40e_virt_mem *mem)
3388 {
3389         if (!mem)
3390                 return I40E_ERR_PARAM;
3391
3392         rte_free(mem->va);
3393         mem->va = NULL;
3394
3395         return I40E_SUCCESS;
3396 }
3397
3398 void
3399 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3400 {
3401         rte_spinlock_init(&sp->spinlock);
3402 }
3403
3404 void
3405 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3406 {
3407         rte_spinlock_lock(&sp->spinlock);
3408 }
3409
3410 void
3411 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3412 {
3413         rte_spinlock_unlock(&sp->spinlock);
3414 }
3415
3416 void
3417 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3418 {
3419         return;
3420 }
3421
3422 /**
3423  * Get the hardware capabilities, which will be parsed
3424  * and saved into struct i40e_hw.
3425  */
3426 static int
3427 i40e_get_cap(struct i40e_hw *hw)
3428 {
3429         struct i40e_aqc_list_capabilities_element_resp *buf;
3430         uint16_t len, size = 0;
3431         int ret;
3432
3433         /* Calculate a huge enough buff for saving response data temporarily */
3434         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3435                                                 I40E_MAX_CAP_ELE_NUM;
3436         buf = rte_zmalloc("i40e", len, 0);
3437         if (!buf) {
3438                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3439                 return I40E_ERR_NO_MEMORY;
3440         }
3441
3442         /* Get, parse the capabilities and save it to hw */
3443         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3444                         i40e_aqc_opc_list_func_capabilities, NULL);
3445         if (ret != I40E_SUCCESS)
3446                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3447
3448         /* Free the temporary buffer after being used */
3449         rte_free(buf);
3450
3451         return ret;
3452 }
3453
3454 static int
3455 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3456 {
3457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3458         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3459         uint16_t qp_count = 0, vsi_count = 0;
3460
3461         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3462                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3463                 return -EINVAL;
3464         }
3465         /* Add the parameter init for LFC */
3466         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3467         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3468         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3469
3470         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3471         pf->max_num_vsi = hw->func_caps.num_vsis;
3472         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3473         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3474         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3475
3476         /* FDir queue/VSI allocation */
3477         pf->fdir_qp_offset = 0;
3478         if (hw->func_caps.fd) {
3479                 pf->flags |= I40E_FLAG_FDIR;
3480                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3481         } else {
3482                 pf->fdir_nb_qps = 0;
3483         }
3484         qp_count += pf->fdir_nb_qps;
3485         vsi_count += 1;
3486
3487         /* LAN queue/VSI allocation */
3488         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3489         if (!hw->func_caps.rss) {
3490                 pf->lan_nb_qps = 1;
3491         } else {
3492                 pf->flags |= I40E_FLAG_RSS;
3493                 if (hw->mac.type == I40E_MAC_X722)
3494                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3495                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3496         }
3497         qp_count += pf->lan_nb_qps;
3498         vsi_count += 1;
3499
3500         /* VF queue/VSI allocation */
3501         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3502         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3503                 pf->flags |= I40E_FLAG_SRIOV;
3504                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3505                 pf->vf_num = dev->pci_dev->max_vfs;
3506                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3507                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3508                             pf->vf_nb_qps * pf->vf_num);
3509         } else {
3510                 pf->vf_nb_qps = 0;
3511                 pf->vf_num = 0;
3512         }
3513         qp_count += pf->vf_nb_qps * pf->vf_num;
3514         vsi_count += pf->vf_num;
3515
3516         /* VMDq queue/VSI allocation */
3517         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3518         pf->vmdq_nb_qps = 0;
3519         pf->max_nb_vmdq_vsi = 0;
3520         if (hw->func_caps.vmdq) {
3521                 if (qp_count < hw->func_caps.num_tx_qp &&
3522                         vsi_count < hw->func_caps.num_vsis) {
3523                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3524                                 qp_count) / pf->vmdq_nb_qp_max;
3525
3526                         /* Limit the maximum number of VMDq vsi to the maximum
3527                          * ethdev can support
3528                          */
3529                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3530                                 hw->func_caps.num_vsis - vsi_count);
3531                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3532                                 ETH_64_POOLS);
3533                         if (pf->max_nb_vmdq_vsi) {
3534                                 pf->flags |= I40E_FLAG_VMDQ;
3535                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3536                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3537                                             "per VMDQ VSI, in total %u queues",
3538                                             pf->max_nb_vmdq_vsi,
3539                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3540                                             pf->max_nb_vmdq_vsi);
3541                         } else {
3542                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3543                                             "VMDq");
3544                         }
3545                 } else {
3546                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3547                 }
3548         }
3549         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3550         vsi_count += pf->max_nb_vmdq_vsi;
3551
3552         if (hw->func_caps.dcb)
3553                 pf->flags |= I40E_FLAG_DCB;
3554
3555         if (qp_count > hw->func_caps.num_tx_qp) {
3556                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3557                             "the hardware maximum %u", qp_count,
3558                             hw->func_caps.num_tx_qp);
3559                 return -EINVAL;
3560         }
3561         if (vsi_count > hw->func_caps.num_vsis) {
3562                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3563                             "the hardware maximum %u", vsi_count,
3564                             hw->func_caps.num_vsis);
3565                 return -EINVAL;
3566         }
3567
3568         return 0;
3569 }
3570
3571 static int
3572 i40e_pf_get_switch_config(struct i40e_pf *pf)
3573 {
3574         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3575         struct i40e_aqc_get_switch_config_resp *switch_config;
3576         struct i40e_aqc_switch_config_element_resp *element;
3577         uint16_t start_seid = 0, num_reported;
3578         int ret;
3579
3580         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3581                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3582         if (!switch_config) {
3583                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3584                 return -ENOMEM;
3585         }
3586
3587         /* Get the switch configurations */
3588         ret = i40e_aq_get_switch_config(hw, switch_config,
3589                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3590         if (ret != I40E_SUCCESS) {
3591                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3592                 goto fail;
3593         }
3594         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3595         if (num_reported != 1) { /* The number should be 1 */
3596                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3597                 goto fail;
3598         }
3599
3600         /* Parse the switch configuration elements */
3601         element = &(switch_config->element[0]);
3602         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3603                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3604                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3605         } else
3606                 PMD_DRV_LOG(INFO, "Unknown element type");
3607
3608 fail:
3609         rte_free(switch_config);
3610
3611         return ret;
3612 }
3613
3614 static int
3615 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3616                         uint32_t num)
3617 {
3618         struct pool_entry *entry;
3619
3620         if (pool == NULL || num == 0)
3621                 return -EINVAL;
3622
3623         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3624         if (entry == NULL) {
3625                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3626                 return -ENOMEM;
3627         }
3628
3629         /* queue heap initialize */
3630         pool->num_free = num;
3631         pool->num_alloc = 0;
3632         pool->base = base;
3633         LIST_INIT(&pool->alloc_list);
3634         LIST_INIT(&pool->free_list);
3635
3636         /* Initialize element  */
3637         entry->base = 0;
3638         entry->len = num;
3639
3640         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3641         return 0;
3642 }
3643
3644 static void
3645 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3646 {
3647         struct pool_entry *entry, *next_entry;
3648
3649         if (pool == NULL)
3650                 return;
3651
3652         for (entry = LIST_FIRST(&pool->alloc_list);
3653                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3654                         entry = next_entry) {
3655                 LIST_REMOVE(entry, next);
3656                 rte_free(entry);
3657         }
3658
3659         for (entry = LIST_FIRST(&pool->free_list);
3660                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3661                         entry = next_entry) {
3662                 LIST_REMOVE(entry, next);
3663                 rte_free(entry);
3664         }
3665
3666         pool->num_free = 0;
3667         pool->num_alloc = 0;
3668         pool->base = 0;
3669         LIST_INIT(&pool->alloc_list);
3670         LIST_INIT(&pool->free_list);
3671 }
3672
3673 static int
3674 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3675                        uint32_t base)
3676 {
3677         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3678         uint32_t pool_offset;
3679         int insert;
3680
3681         if (pool == NULL) {
3682                 PMD_DRV_LOG(ERR, "Invalid parameter");
3683                 return -EINVAL;
3684         }
3685
3686         pool_offset = base - pool->base;
3687         /* Lookup in alloc list */
3688         LIST_FOREACH(entry, &pool->alloc_list, next) {
3689                 if (entry->base == pool_offset) {
3690                         valid_entry = entry;
3691                         LIST_REMOVE(entry, next);
3692                         break;
3693                 }
3694         }
3695
3696         /* Not find, return */
3697         if (valid_entry == NULL) {
3698                 PMD_DRV_LOG(ERR, "Failed to find entry");
3699                 return -EINVAL;
3700         }
3701
3702         /**
3703          * Found it, move it to free list  and try to merge.
3704          * In order to make merge easier, always sort it by qbase.
3705          * Find adjacent prev and last entries.
3706          */
3707         prev = next = NULL;
3708         LIST_FOREACH(entry, &pool->free_list, next) {
3709                 if (entry->base > valid_entry->base) {
3710                         next = entry;
3711                         break;
3712                 }
3713                 prev = entry;
3714         }
3715
3716         insert = 0;
3717         /* Try to merge with next one*/
3718         if (next != NULL) {
3719                 /* Merge with next one */
3720                 if (valid_entry->base + valid_entry->len == next->base) {
3721                         next->base = valid_entry->base;
3722                         next->len += valid_entry->len;
3723                         rte_free(valid_entry);
3724                         valid_entry = next;
3725                         insert = 1;
3726                 }
3727         }
3728
3729         if (prev != NULL) {
3730                 /* Merge with previous one */
3731                 if (prev->base + prev->len == valid_entry->base) {
3732                         prev->len += valid_entry->len;
3733                         /* If it merge with next one, remove next node */
3734                         if (insert == 1) {
3735                                 LIST_REMOVE(valid_entry, next);
3736                                 rte_free(valid_entry);
3737                         } else {
3738                                 rte_free(valid_entry);
3739                                 insert = 1;
3740                         }
3741                 }
3742         }
3743
3744         /* Not find any entry to merge, insert */
3745         if (insert == 0) {
3746                 if (prev != NULL)
3747                         LIST_INSERT_AFTER(prev, valid_entry, next);
3748                 else if (next != NULL)
3749                         LIST_INSERT_BEFORE(next, valid_entry, next);
3750                 else /* It's empty list, insert to head */
3751                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3752         }
3753
3754         pool->num_free += valid_entry->len;
3755         pool->num_alloc -= valid_entry->len;
3756
3757         return 0;
3758 }
3759
3760 static int
3761 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3762                        uint16_t num)
3763 {
3764         struct pool_entry *entry, *valid_entry;
3765
3766         if (pool == NULL || num == 0) {
3767                 PMD_DRV_LOG(ERR, "Invalid parameter");
3768                 return -EINVAL;
3769         }
3770
3771         if (pool->num_free < num) {
3772                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3773                             num, pool->num_free);
3774                 return -ENOMEM;
3775         }
3776
3777         valid_entry = NULL;
3778         /* Lookup  in free list and find most fit one */
3779         LIST_FOREACH(entry, &pool->free_list, next) {
3780                 if (entry->len >= num) {
3781                         /* Find best one */
3782                         if (entry->len == num) {
3783                                 valid_entry = entry;
3784                                 break;
3785                         }
3786                         if (valid_entry == NULL || valid_entry->len > entry->len)
3787                                 valid_entry = entry;
3788                 }
3789         }
3790
3791         /* Not find one to satisfy the request, return */
3792         if (valid_entry == NULL) {
3793                 PMD_DRV_LOG(ERR, "No valid entry found");
3794                 return -ENOMEM;
3795         }
3796         /**
3797          * The entry have equal queue number as requested,
3798          * remove it from alloc_list.
3799          */
3800         if (valid_entry->len == num) {
3801                 LIST_REMOVE(valid_entry, next);
3802         } else {
3803                 /**
3804                  * The entry have more numbers than requested,
3805                  * create a new entry for alloc_list and minus its
3806                  * queue base and number in free_list.
3807                  */
3808                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3809                 if (entry == NULL) {
3810                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3811                                     "resource pool");
3812                         return -ENOMEM;
3813                 }
3814                 entry->base = valid_entry->base;
3815                 entry->len = num;
3816                 valid_entry->base += num;
3817                 valid_entry->len -= num;
3818                 valid_entry = entry;
3819         }
3820
3821         /* Insert it into alloc list, not sorted */
3822         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3823
3824         pool->num_free -= valid_entry->len;
3825         pool->num_alloc += valid_entry->len;
3826
3827         return valid_entry->base + pool->base;
3828 }
3829
3830 /**
3831  * bitmap_is_subset - Check whether src2 is subset of src1
3832  **/
3833 static inline int
3834 bitmap_is_subset(uint8_t src1, uint8_t src2)
3835 {
3836         return !((src1 ^ src2) & src2);
3837 }
3838
3839 static enum i40e_status_code
3840 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3841 {
3842         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3843
3844         /* If DCB is not supported, only default TC is supported */
3845         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3846                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3847                 return I40E_NOT_SUPPORTED;
3848         }
3849
3850         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3851                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3852                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3853                             enabled_tcmap);
3854                 return I40E_NOT_SUPPORTED;
3855         }
3856         return I40E_SUCCESS;
3857 }
3858
3859 int
3860 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3861                                 struct i40e_vsi_vlan_pvid_info *info)
3862 {
3863         struct i40e_hw *hw;
3864         struct i40e_vsi_context ctxt;
3865         uint8_t vlan_flags = 0;
3866         int ret;
3867
3868         if (vsi == NULL || info == NULL) {
3869                 PMD_DRV_LOG(ERR, "invalid parameters");
3870                 return I40E_ERR_PARAM;
3871         }
3872
3873         if (info->on) {
3874                 vsi->info.pvid = info->config.pvid;
3875                 /**
3876                  * If insert pvid is enabled, only tagged pkts are
3877                  * allowed to be sent out.
3878                  */
3879                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3880                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3881         } else {
3882                 vsi->info.pvid = 0;
3883                 if (info->config.reject.tagged == 0)
3884                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3885
3886                 if (info->config.reject.untagged == 0)
3887                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3888         }
3889         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3890                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3891         vsi->info.port_vlan_flags |= vlan_flags;
3892         vsi->info.valid_sections =
3893                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3894         memset(&ctxt, 0, sizeof(ctxt));
3895         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3896         ctxt.seid = vsi->seid;
3897
3898         hw = I40E_VSI_TO_HW(vsi);
3899         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3900         if (ret != I40E_SUCCESS)
3901                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3902
3903         return ret;
3904 }
3905
3906 static int
3907 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3908 {
3909         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3910         int i, ret;
3911         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3912
3913         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3914         if (ret != I40E_SUCCESS)
3915                 return ret;
3916
3917         if (!vsi->seid) {
3918                 PMD_DRV_LOG(ERR, "seid not valid");
3919                 return -EINVAL;
3920         }
3921
3922         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3923         tc_bw_data.tc_valid_bits = enabled_tcmap;
3924         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3925                 tc_bw_data.tc_bw_credits[i] =
3926                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3927
3928         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3929         if (ret != I40E_SUCCESS) {
3930                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3931                 return ret;
3932         }
3933
3934         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3935                                         sizeof(vsi->info.qs_handle));
3936         return I40E_SUCCESS;
3937 }
3938
3939 static enum i40e_status_code
3940 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3941                                  struct i40e_aqc_vsi_properties_data *info,
3942                                  uint8_t enabled_tcmap)
3943 {
3944         enum i40e_status_code ret;
3945         int i, total_tc = 0;
3946         uint16_t qpnum_per_tc, bsf, qp_idx;
3947
3948         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3949         if (ret != I40E_SUCCESS)
3950                 return ret;
3951
3952         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3953                 if (enabled_tcmap & (1 << i))
3954                         total_tc++;
3955         vsi->enabled_tc = enabled_tcmap;
3956
3957         /* Number of queues per enabled TC */
3958         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3959         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3960         bsf = rte_bsf32(qpnum_per_tc);
3961
3962         /* Adjust the queue number to actual queues that can be applied */
3963         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3964                 vsi->nb_qps = qpnum_per_tc * total_tc;
3965
3966         /**
3967          * Configure TC and queue mapping parameters, for enabled TC,
3968          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3969          * default queue will serve it.
3970          */
3971         qp_idx = 0;
3972         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3973                 if (vsi->enabled_tc & (1 << i)) {
3974                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3975                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3976                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3977                         qp_idx += qpnum_per_tc;
3978                 } else
3979                         info->tc_mapping[i] = 0;
3980         }
3981
3982         /* Associate queue number with VSI */
3983         if (vsi->type == I40E_VSI_SRIOV) {
3984                 info->mapping_flags |=
3985                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3986                 for (i = 0; i < vsi->nb_qps; i++)
3987                         info->queue_mapping[i] =
3988                                 rte_cpu_to_le_16(vsi->base_queue + i);
3989         } else {
3990                 info->mapping_flags |=
3991                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3992                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3993         }
3994         info->valid_sections |=
3995                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3996
3997         return I40E_SUCCESS;
3998 }
3999
4000 static int
4001 i40e_veb_release(struct i40e_veb *veb)
4002 {
4003         struct i40e_vsi *vsi;
4004         struct i40e_hw *hw;
4005
4006         if (veb == NULL)
4007                 return -EINVAL;
4008
4009         if (!TAILQ_EMPTY(&veb->head)) {
4010                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4011                 return -EACCES;
4012         }
4013         /* associate_vsi field is NULL for floating VEB */
4014         if (veb->associate_vsi != NULL) {
4015                 vsi = veb->associate_vsi;
4016                 hw = I40E_VSI_TO_HW(vsi);
4017
4018                 vsi->uplink_seid = veb->uplink_seid;
4019                 vsi->veb = NULL;
4020         } else {
4021                 veb->associate_pf->main_vsi->floating_veb = NULL;
4022                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4023         }
4024
4025         i40e_aq_delete_element(hw, veb->seid, NULL);
4026         rte_free(veb);
4027         return I40E_SUCCESS;
4028 }
4029
4030 /* Setup a veb */
4031 static struct i40e_veb *
4032 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4033 {
4034         struct i40e_veb *veb;
4035         int ret;
4036         struct i40e_hw *hw;
4037
4038         if (pf == NULL) {
4039                 PMD_DRV_LOG(ERR,
4040                             "veb setup failed, associated PF shouldn't null");
4041                 return NULL;
4042         }
4043         hw = I40E_PF_TO_HW(pf);
4044
4045         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4046         if (!veb) {
4047                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4048                 goto fail;
4049         }
4050
4051         veb->associate_vsi = vsi;
4052         veb->associate_pf = pf;
4053         TAILQ_INIT(&veb->head);
4054         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4055
4056         /* create floating veb if vsi is NULL */
4057         if (vsi != NULL) {
4058                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4059                                       I40E_DEFAULT_TCMAP, false,
4060                                       &veb->seid, false, NULL);
4061         } else {
4062                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4063                                       true, &veb->seid, false, NULL);
4064         }
4065
4066         if (ret != I40E_SUCCESS) {
4067                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4068                             hw->aq.asq_last_status);
4069                 goto fail;
4070         }
4071
4072         /* get statistics index */
4073         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4074                                 &veb->stats_idx, NULL, NULL, NULL);
4075         if (ret != I40E_SUCCESS) {
4076                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4077                             hw->aq.asq_last_status);
4078                 goto fail;
4079         }
4080         /* Get VEB bandwidth, to be implemented */
4081         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4082         if (vsi)
4083                 vsi->uplink_seid = veb->seid;
4084
4085         return veb;
4086 fail:
4087         rte_free(veb);
4088         return NULL;
4089 }
4090
4091 int
4092 i40e_vsi_release(struct i40e_vsi *vsi)
4093 {
4094         struct i40e_pf *pf;
4095         struct i40e_hw *hw;
4096         struct i40e_vsi_list *vsi_list;
4097         void *temp;
4098         int ret;
4099         struct i40e_mac_filter *f;
4100         uint16_t user_param = vsi->user_param;
4101
4102         if (!vsi)
4103                 return I40E_SUCCESS;
4104
4105         pf = I40E_VSI_TO_PF(vsi);
4106         hw = I40E_VSI_TO_HW(vsi);
4107
4108         /* VSI has child to attach, release child first */
4109         if (vsi->veb) {
4110                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4111                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4112                                 return -1;
4113                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
4114                 }
4115                 i40e_veb_release(vsi->veb);
4116         }
4117
4118         if (vsi->floating_veb) {
4119                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4120                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4121                                 return -1;
4122                         TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
4123                 }
4124         }
4125
4126         /* Remove all macvlan filters of the VSI */
4127         i40e_vsi_remove_all_macvlan_filter(vsi);
4128         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4129                 rte_free(f);
4130
4131         if (vsi->type != I40E_VSI_MAIN &&
4132             ((vsi->type != I40E_VSI_SRIOV) ||
4133             !pf->floating_veb_list[user_param])) {
4134                 /* Remove vsi from parent's sibling list */
4135                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4136                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4137                         return I40E_ERR_PARAM;
4138                 }
4139                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4140                                 &vsi->sib_vsi_list, list);
4141
4142                 /* Remove all switch element of the VSI */
4143                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4144                 if (ret != I40E_SUCCESS)
4145                         PMD_DRV_LOG(ERR, "Failed to delete element");
4146         }
4147
4148         if ((vsi->type == I40E_VSI_SRIOV) &&
4149             pf->floating_veb_list[user_param]) {
4150                 /* Remove vsi from parent's sibling list */
4151                 if (vsi->parent_vsi == NULL ||
4152                     vsi->parent_vsi->floating_veb == NULL) {
4153                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4154                         return I40E_ERR_PARAM;
4155                 }
4156                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4157                              &vsi->sib_vsi_list, list);
4158
4159                 /* Remove all switch element of the VSI */
4160                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4161                 if (ret != I40E_SUCCESS)
4162                         PMD_DRV_LOG(ERR, "Failed to delete element");
4163         }
4164
4165         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4166
4167         if (vsi->type != I40E_VSI_SRIOV)
4168                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4169         rte_free(vsi);
4170
4171         return I40E_SUCCESS;
4172 }
4173
4174 static int
4175 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4176 {
4177         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4178         struct i40e_aqc_remove_macvlan_element_data def_filter;
4179         struct i40e_mac_filter_info filter;
4180         int ret;
4181
4182         if (vsi->type != I40E_VSI_MAIN)
4183                 return I40E_ERR_CONFIG;
4184         memset(&def_filter, 0, sizeof(def_filter));
4185         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4186                                         ETH_ADDR_LEN);
4187         def_filter.vlan_tag = 0;
4188         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4189                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4190         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4191         if (ret != I40E_SUCCESS) {
4192                 struct i40e_mac_filter *f;
4193                 struct ether_addr *mac;
4194
4195                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4196                             "macvlan filter");
4197                 /* It needs to add the permanent mac into mac list */
4198                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4199                 if (f == NULL) {
4200                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4201                         return I40E_ERR_NO_MEMORY;
4202                 }
4203                 mac = &f->mac_info.mac_addr;
4204                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4205                                 ETH_ADDR_LEN);
4206                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4207                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4208                 vsi->mac_num++;
4209
4210                 return ret;
4211         }
4212         (void)rte_memcpy(&filter.mac_addr,
4213                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4214         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4215         return i40e_vsi_add_mac(vsi, &filter);
4216 }
4217
4218 /*
4219  * i40e_vsi_get_bw_config - Query VSI BW Information
4220  * @vsi: the VSI to be queried
4221  *
4222  * Returns 0 on success, negative value on failure
4223  */
4224 static enum i40e_status_code
4225 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4226 {
4227         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4228         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4229         struct i40e_hw *hw = &vsi->adapter->hw;
4230         i40e_status ret;
4231         int i;
4232         uint32_t bw_max;
4233
4234         memset(&bw_config, 0, sizeof(bw_config));
4235         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4236         if (ret != I40E_SUCCESS) {
4237                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4238                             hw->aq.asq_last_status);
4239                 return ret;
4240         }
4241
4242         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4243         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4244                                         &ets_sla_config, NULL);
4245         if (ret != I40E_SUCCESS) {
4246                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4247                             "configuration %u", hw->aq.asq_last_status);
4248                 return ret;
4249         }
4250
4251         /* store and print out BW info */
4252         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4253         vsi->bw_info.bw_max = bw_config.max_bw;
4254         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4255         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4256         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4257                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4258                      I40E_16_BIT_WIDTH);
4259         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4260                 vsi->bw_info.bw_ets_share_credits[i] =
4261                                 ets_sla_config.share_credits[i];
4262                 vsi->bw_info.bw_ets_credits[i] =
4263                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4264                 /* 4 bits per TC, 4th bit is reserved */
4265                 vsi->bw_info.bw_ets_max[i] =
4266                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4267                                   RTE_LEN2MASK(3, uint8_t));
4268                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4269                             vsi->bw_info.bw_ets_share_credits[i]);
4270                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4271                             vsi->bw_info.bw_ets_credits[i]);
4272                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4273                             vsi->bw_info.bw_ets_max[i]);
4274         }
4275
4276         return I40E_SUCCESS;
4277 }
4278
4279 /* i40e_enable_pf_lb
4280  * @pf: pointer to the pf structure
4281  *
4282  * allow loopback on pf
4283  */
4284 static inline void
4285 i40e_enable_pf_lb(struct i40e_pf *pf)
4286 {
4287         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4288         struct i40e_vsi_context ctxt;
4289         int ret;
4290
4291         /* Use the FW API if FW >= v5.0 */
4292         if (hw->aq.fw_maj_ver < 5) {
4293                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4294                 return;
4295         }
4296
4297         memset(&ctxt, 0, sizeof(ctxt));
4298         ctxt.seid = pf->main_vsi_seid;
4299         ctxt.pf_num = hw->pf_id;
4300         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4301         if (ret) {
4302                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4303                             ret, hw->aq.asq_last_status);
4304                 return;
4305         }
4306         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4307         ctxt.info.valid_sections =
4308                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4309         ctxt.info.switch_id |=
4310                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4311
4312         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4313         if (ret)
4314                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4315                             hw->aq.asq_last_status);
4316 }
4317
4318 /* Setup a VSI */
4319 struct i40e_vsi *
4320 i40e_vsi_setup(struct i40e_pf *pf,
4321                enum i40e_vsi_type type,
4322                struct i40e_vsi *uplink_vsi,
4323                uint16_t user_param)
4324 {
4325         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4326         struct i40e_vsi *vsi;
4327         struct i40e_mac_filter_info filter;
4328         int ret;
4329         struct i40e_vsi_context ctxt;
4330         struct ether_addr broadcast =
4331                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4332
4333         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4334             uplink_vsi == NULL) {
4335                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4336                             "VSI link shouldn't be NULL");
4337                 return NULL;
4338         }
4339
4340         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4341                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4342                             "uplink VSI should be NULL");
4343                 return NULL;
4344         }
4345
4346         /* two situations
4347          * 1.type is not MAIN and uplink vsi is not NULL
4348          * If uplink vsi didn't setup VEB, create one first under veb field
4349          * 2.type is SRIOV and the uplink is NULL
4350          * If floating VEB is NULL, create one veb under floating veb field
4351          */
4352
4353         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4354             uplink_vsi->veb == NULL) {
4355                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4356
4357                 if (uplink_vsi->veb == NULL) {
4358                         PMD_DRV_LOG(ERR, "VEB setup failed");
4359                         return NULL;
4360                 }
4361                 /* set ALLOWLOOPBACk on pf, when veb is created */
4362                 i40e_enable_pf_lb(pf);
4363         }
4364
4365         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4366             pf->main_vsi->floating_veb == NULL) {
4367                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4368
4369                 if (pf->main_vsi->floating_veb == NULL) {
4370                         PMD_DRV_LOG(ERR, "VEB setup failed");
4371                         return NULL;
4372                 }
4373         }
4374
4375         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4376         if (!vsi) {
4377                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4378                 return NULL;
4379         }
4380         TAILQ_INIT(&vsi->mac_list);
4381         vsi->type = type;
4382         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4383         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4384         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4385         vsi->user_param = user_param;
4386         /* Allocate queues */
4387         switch (vsi->type) {
4388         case I40E_VSI_MAIN  :
4389                 vsi->nb_qps = pf->lan_nb_qps;
4390                 break;
4391         case I40E_VSI_SRIOV :
4392                 vsi->nb_qps = pf->vf_nb_qps;
4393                 break;
4394         case I40E_VSI_VMDQ2:
4395                 vsi->nb_qps = pf->vmdq_nb_qps;
4396                 break;
4397         case I40E_VSI_FDIR:
4398                 vsi->nb_qps = pf->fdir_nb_qps;
4399                 break;
4400         default:
4401                 goto fail_mem;
4402         }
4403         /*
4404          * The filter status descriptor is reported in rx queue 0,
4405          * while the tx queue for fdir filter programming has no
4406          * such constraints, can be non-zero queues.
4407          * To simplify it, choose FDIR vsi use queue 0 pair.
4408          * To make sure it will use queue 0 pair, queue allocation
4409          * need be done before this function is called
4410          */
4411         if (type != I40E_VSI_FDIR) {
4412                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4413                         if (ret < 0) {
4414                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4415                                                 vsi->seid, ret);
4416                                 goto fail_mem;
4417                         }
4418                         vsi->base_queue = ret;
4419         } else
4420                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4421
4422         /* VF has MSIX interrupt in VF range, don't allocate here */
4423         if (type == I40E_VSI_MAIN) {
4424                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4425                                           RTE_MIN(vsi->nb_qps,
4426                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4427                 if (ret < 0) {
4428                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4429                                     vsi->seid, ret);
4430                         goto fail_queue_alloc;
4431                 }
4432                 vsi->msix_intr = ret;
4433                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4434         } else if (type != I40E_VSI_SRIOV) {
4435                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4436                 if (ret < 0) {
4437                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4438                         goto fail_queue_alloc;
4439                 }
4440                 vsi->msix_intr = ret;
4441                 vsi->nb_msix = 1;
4442         } else {
4443                 vsi->msix_intr = 0;
4444                 vsi->nb_msix = 0;
4445         }
4446
4447         /* Add VSI */
4448         if (type == I40E_VSI_MAIN) {
4449                 /* For main VSI, no need to add since it's default one */
4450                 vsi->uplink_seid = pf->mac_seid;
4451                 vsi->seid = pf->main_vsi_seid;
4452                 /* Bind queues with specific MSIX interrupt */
4453                 /**
4454                  * Needs 2 interrupt at least, one for misc cause which will
4455                  * enabled from OS side, Another for queues binding the
4456                  * interrupt from device side only.
4457                  */
4458
4459                 /* Get default VSI parameters from hardware */
4460                 memset(&ctxt, 0, sizeof(ctxt));
4461                 ctxt.seid = vsi->seid;
4462                 ctxt.pf_num = hw->pf_id;
4463                 ctxt.uplink_seid = vsi->uplink_seid;
4464                 ctxt.vf_num = 0;
4465                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4466                 if (ret != I40E_SUCCESS) {
4467                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4468                         goto fail_msix_alloc;
4469                 }
4470                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4471                         sizeof(struct i40e_aqc_vsi_properties_data));
4472                 vsi->vsi_id = ctxt.vsi_number;
4473                 vsi->info.valid_sections = 0;
4474
4475                 /* Configure tc, enabled TC0 only */
4476                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4477                         I40E_SUCCESS) {
4478                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4479                         goto fail_msix_alloc;
4480                 }
4481
4482                 /* TC, queue mapping */
4483                 memset(&ctxt, 0, sizeof(ctxt));
4484                 vsi->info.valid_sections |=
4485                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4486                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4487                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4488                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4489                         sizeof(struct i40e_aqc_vsi_properties_data));
4490                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4491                                                 I40E_DEFAULT_TCMAP);
4492                 if (ret != I40E_SUCCESS) {
4493                         PMD_DRV_LOG(ERR, "Failed to configure "
4494                                     "TC queue mapping");
4495                         goto fail_msix_alloc;
4496                 }
4497                 ctxt.seid = vsi->seid;
4498                 ctxt.pf_num = hw->pf_id;
4499                 ctxt.uplink_seid = vsi->uplink_seid;
4500                 ctxt.vf_num = 0;
4501
4502                 /* Update VSI parameters */
4503                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4504                 if (ret != I40E_SUCCESS) {
4505                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4506                         goto fail_msix_alloc;
4507                 }
4508
4509                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4510                                                 sizeof(vsi->info.tc_mapping));
4511                 (void)rte_memcpy(&vsi->info.queue_mapping,
4512                                 &ctxt.info.queue_mapping,
4513                         sizeof(vsi->info.queue_mapping));
4514                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4515                 vsi->info.valid_sections = 0;
4516
4517                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4518                                 ETH_ADDR_LEN);
4519
4520                 /**
4521                  * Updating default filter settings are necessary to prevent
4522                  * reception of tagged packets.
4523                  * Some old firmware configurations load a default macvlan
4524                  * filter which accepts both tagged and untagged packets.
4525                  * The updating is to use a normal filter instead if needed.
4526                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4527                  * The firmware with correct configurations load the default
4528                  * macvlan filter which is expected and cannot be removed.
4529                  */
4530                 i40e_update_default_filter_setting(vsi);
4531                 i40e_config_qinq(hw, vsi);
4532         } else if (type == I40E_VSI_SRIOV) {
4533                 memset(&ctxt, 0, sizeof(ctxt));
4534                 /**
4535                  * For other VSI, the uplink_seid equals to uplink VSI's
4536                  * uplink_seid since they share same VEB
4537                  */
4538                 if (uplink_vsi == NULL)
4539                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4540                 else
4541                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4542                 ctxt.pf_num = hw->pf_id;
4543                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4544                 ctxt.uplink_seid = vsi->uplink_seid;
4545                 ctxt.connection_type = 0x1;
4546                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4547
4548                 /* Use the VEB configuration if FW >= v5.0 */
4549                 if (hw->aq.fw_maj_ver >= 5) {
4550                         /* Configure switch ID */
4551                         ctxt.info.valid_sections |=
4552                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4553                         ctxt.info.switch_id =
4554                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4555                 }
4556
4557                 /* Configure port/vlan */
4558                 ctxt.info.valid_sections |=
4559                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4560                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4561                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4562                                                 I40E_DEFAULT_TCMAP);
4563                 if (ret != I40E_SUCCESS) {
4564                         PMD_DRV_LOG(ERR, "Failed to configure "
4565                                     "TC queue mapping");
4566                         goto fail_msix_alloc;
4567                 }
4568                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4569                 ctxt.info.valid_sections |=
4570                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4571                 /**
4572                  * Since VSI is not created yet, only configure parameter,
4573                  * will add vsi below.
4574                  */
4575
4576                 i40e_config_qinq(hw, vsi);
4577         } else if (type == I40E_VSI_VMDQ2) {
4578                 memset(&ctxt, 0, sizeof(ctxt));
4579                 /*
4580                  * For other VSI, the uplink_seid equals to uplink VSI's
4581                  * uplink_seid since they share same VEB
4582                  */
4583                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4584                 ctxt.pf_num = hw->pf_id;
4585                 ctxt.vf_num = 0;
4586                 ctxt.uplink_seid = vsi->uplink_seid;
4587                 ctxt.connection_type = 0x1;
4588                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4589
4590                 ctxt.info.valid_sections |=
4591                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4592                 /* user_param carries flag to enable loop back */
4593                 if (user_param) {
4594                         ctxt.info.switch_id =
4595                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4596                         ctxt.info.switch_id |=
4597                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4598                 }
4599
4600                 /* Configure port/vlan */
4601                 ctxt.info.valid_sections |=
4602                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4603                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4604                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4605                                                 I40E_DEFAULT_TCMAP);
4606                 if (ret != I40E_SUCCESS) {
4607                         PMD_DRV_LOG(ERR, "Failed to configure "
4608                                         "TC queue mapping");
4609                         goto fail_msix_alloc;
4610                 }
4611                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4612                 ctxt.info.valid_sections |=
4613                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4614         } else if (type == I40E_VSI_FDIR) {
4615                 memset(&ctxt, 0, sizeof(ctxt));
4616                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4617                 ctxt.pf_num = hw->pf_id;
4618                 ctxt.vf_num = 0;
4619                 ctxt.uplink_seid = vsi->uplink_seid;
4620                 ctxt.connection_type = 0x1;     /* regular data port */
4621                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4622                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4623                                                 I40E_DEFAULT_TCMAP);
4624                 if (ret != I40E_SUCCESS) {
4625                         PMD_DRV_LOG(ERR, "Failed to configure "
4626                                         "TC queue mapping.");
4627                         goto fail_msix_alloc;
4628                 }
4629                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4630                 ctxt.info.valid_sections |=
4631                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4632         } else {
4633                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4634                 goto fail_msix_alloc;
4635         }
4636
4637         if (vsi->type != I40E_VSI_MAIN) {
4638                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4639                 if (ret != I40E_SUCCESS) {
4640                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4641                                     hw->aq.asq_last_status);
4642                         goto fail_msix_alloc;
4643                 }
4644                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4645                 vsi->info.valid_sections = 0;
4646                 vsi->seid = ctxt.seid;
4647                 vsi->vsi_id = ctxt.vsi_number;
4648                 vsi->sib_vsi_list.vsi = vsi;
4649                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4650                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4651                                           &vsi->sib_vsi_list, list);
4652                 } else {
4653                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4654                                           &vsi->sib_vsi_list, list);
4655                 }
4656         }
4657
4658         /* MAC/VLAN configuration */
4659         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4660         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4661
4662         ret = i40e_vsi_add_mac(vsi, &filter);
4663         if (ret != I40E_SUCCESS) {
4664                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4665                 goto fail_msix_alloc;
4666         }
4667
4668         /* Get VSI BW information */
4669         i40e_vsi_get_bw_config(vsi);
4670         return vsi;
4671 fail_msix_alloc:
4672         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4673 fail_queue_alloc:
4674         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4675 fail_mem:
4676         rte_free(vsi);
4677         return NULL;
4678 }
4679
4680 /* Configure vlan filter on or off */
4681 int
4682 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4683 {
4684         int i, num;
4685         struct i40e_mac_filter *f;
4686         void *temp;
4687         struct i40e_mac_filter_info *mac_filter;
4688         enum rte_mac_filter_type desired_filter;
4689         int ret = I40E_SUCCESS;
4690
4691         if (on) {
4692                 /* Filter to match MAC and VLAN */
4693                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4694         } else {
4695                 /* Filter to match only MAC */
4696                 desired_filter = RTE_MAC_PERFECT_MATCH;
4697         }
4698
4699         num = vsi->mac_num;
4700
4701         mac_filter = rte_zmalloc("mac_filter_info_data",
4702                                  num * sizeof(*mac_filter), 0);
4703         if (mac_filter == NULL) {
4704                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4705                 return I40E_ERR_NO_MEMORY;
4706         }
4707
4708         i = 0;
4709
4710         /* Remove all existing mac */
4711         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4712                 mac_filter[i] = f->mac_info;
4713                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4714                 if (ret) {
4715                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4716                                     on ? "enable" : "disable");
4717                         goto DONE;
4718                 }
4719                 i++;
4720         }
4721
4722         /* Override with new filter */
4723         for (i = 0; i < num; i++) {
4724                 mac_filter[i].filter_type = desired_filter;
4725                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4726                 if (ret) {
4727                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4728                                     on ? "enable" : "disable");
4729                         goto DONE;
4730                 }
4731         }
4732
4733 DONE:
4734         rte_free(mac_filter);
4735         return ret;
4736 }
4737
4738 /* Configure vlan stripping on or off */
4739 int
4740 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4741 {
4742         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4743         struct i40e_vsi_context ctxt;
4744         uint8_t vlan_flags;
4745         int ret = I40E_SUCCESS;
4746
4747         /* Check if it has been already on or off */
4748         if (vsi->info.valid_sections &
4749                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4750                 if (on) {
4751                         if ((vsi->info.port_vlan_flags &
4752                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4753                                 return 0; /* already on */
4754                 } else {
4755                         if ((vsi->info.port_vlan_flags &
4756                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4757                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4758                                 return 0; /* already off */
4759                 }
4760         }
4761
4762         if (on)
4763                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4764         else
4765                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4766         vsi->info.valid_sections =
4767                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4768         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4769         vsi->info.port_vlan_flags |= vlan_flags;
4770         ctxt.seid = vsi->seid;
4771         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4772         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4773         if (ret)
4774                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4775                             on ? "enable" : "disable");
4776
4777         return ret;
4778 }
4779
4780 static int
4781 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4782 {
4783         struct rte_eth_dev_data *data = dev->data;
4784         int ret;
4785         int mask = 0;
4786
4787         /* Apply vlan offload setting */
4788         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4789         i40e_vlan_offload_set(dev, mask);
4790
4791         /* Apply double-vlan setting, not implemented yet */
4792
4793         /* Apply pvid setting */
4794         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4795                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4796         if (ret)
4797                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4798
4799         return ret;
4800 }
4801
4802 static int
4803 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4804 {
4805         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4806
4807         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4808 }
4809
4810 static int
4811 i40e_update_flow_control(struct i40e_hw *hw)
4812 {
4813 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4814         struct i40e_link_status link_status;
4815         uint32_t rxfc = 0, txfc = 0, reg;
4816         uint8_t an_info;
4817         int ret;
4818
4819         memset(&link_status, 0, sizeof(link_status));
4820         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4821         if (ret != I40E_SUCCESS) {
4822                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4823                 goto write_reg; /* Disable flow control */
4824         }
4825
4826         an_info = hw->phy.link_info.an_info;
4827         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4828                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4829                 ret = I40E_ERR_NOT_READY;
4830                 goto write_reg; /* Disable flow control */
4831         }
4832         /**
4833          * If link auto negotiation is enabled, flow control needs to
4834          * be configured according to it
4835          */
4836         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4837         case I40E_LINK_PAUSE_RXTX:
4838                 rxfc = 1;
4839                 txfc = 1;
4840                 hw->fc.current_mode = I40E_FC_FULL;
4841                 break;
4842         case I40E_AQ_LINK_PAUSE_RX:
4843                 rxfc = 1;
4844                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4845                 break;
4846         case I40E_AQ_LINK_PAUSE_TX:
4847                 txfc = 1;
4848                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4849                 break;
4850         default:
4851                 hw->fc.current_mode = I40E_FC_NONE;
4852                 break;
4853         }
4854
4855 write_reg:
4856         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4857                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4858         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4859         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4860         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4861         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4862
4863         return ret;
4864 }
4865
4866 /* PF setup */
4867 static int
4868 i40e_pf_setup(struct i40e_pf *pf)
4869 {
4870         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4871         struct i40e_filter_control_settings settings;
4872         struct i40e_vsi *vsi;
4873         int ret;
4874
4875         /* Clear all stats counters */
4876         pf->offset_loaded = FALSE;
4877         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4878         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4879
4880         ret = i40e_pf_get_switch_config(pf);
4881         if (ret != I40E_SUCCESS) {
4882                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4883                 return ret;
4884         }
4885         if (pf->flags & I40E_FLAG_FDIR) {
4886                 /* make queue allocated first, let FDIR use queue pair 0*/
4887                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4888                 if (ret != I40E_FDIR_QUEUE_ID) {
4889                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4890                                     " ret =%d", ret);
4891                         pf->flags &= ~I40E_FLAG_FDIR;
4892                 }
4893         }
4894         /*  main VSI setup */
4895         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4896         if (!vsi) {
4897                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4898                 return I40E_ERR_NOT_READY;
4899         }
4900         pf->main_vsi = vsi;
4901
4902         /* Configure filter control */
4903         memset(&settings, 0, sizeof(settings));
4904         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4905                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4906         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4907                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4908         else {
4909                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4910                                                 hw->func_caps.rss_table_size);
4911                 return I40E_ERR_PARAM;
4912         }
4913         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4914                         "size: %u\n", hw->func_caps.rss_table_size);
4915         pf->hash_lut_size = hw->func_caps.rss_table_size;
4916
4917         /* Enable ethtype and macvlan filters */
4918         settings.enable_ethtype = TRUE;
4919         settings.enable_macvlan = TRUE;
4920         ret = i40e_set_filter_control(hw, &settings);
4921         if (ret)
4922                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4923                                                                 ret);
4924
4925         /* Update flow control according to the auto negotiation */
4926         i40e_update_flow_control(hw);
4927
4928         return I40E_SUCCESS;
4929 }
4930
4931 int
4932 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4933 {
4934         uint32_t reg;
4935         uint16_t j;
4936
4937         /**
4938          * Set or clear TX Queue Disable flags,
4939          * which is required by hardware.
4940          */
4941         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4942         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4943
4944         /* Wait until the request is finished */
4945         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4946                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4947                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4948                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4949                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4950                                                         & 0x1))) {
4951                         break;
4952                 }
4953         }
4954         if (on) {
4955                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4956                         return I40E_SUCCESS; /* already on, skip next steps */
4957
4958                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4959                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4960         } else {
4961                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4962                         return I40E_SUCCESS; /* already off, skip next steps */
4963                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4964         }
4965         /* Write the register */
4966         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4967         /* Check the result */
4968         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4969                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4970                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4971                 if (on) {
4972                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4973                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4974                                 break;
4975                 } else {
4976                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4977                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4978                                 break;
4979                 }
4980         }
4981         /* Check if it is timeout */
4982         if (j >= I40E_CHK_Q_ENA_COUNT) {
4983                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4984                             (on ? "enable" : "disable"), q_idx);
4985                 return I40E_ERR_TIMEOUT;
4986         }
4987
4988         return I40E_SUCCESS;
4989 }
4990
4991 /* Swith on or off the tx queues */
4992 static int
4993 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4994 {
4995         struct rte_eth_dev_data *dev_data = pf->dev_data;
4996         struct i40e_tx_queue *txq;
4997         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4998         uint16_t i;
4999         int ret;
5000
5001         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5002                 txq = dev_data->tx_queues[i];
5003                 /* Don't operate the queue if not configured or
5004                  * if starting only per queue */
5005                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5006                         continue;
5007                 if (on)
5008                         ret = i40e_dev_tx_queue_start(dev, i);
5009                 else
5010                         ret = i40e_dev_tx_queue_stop(dev, i);
5011                 if ( ret != I40E_SUCCESS)
5012                         return ret;
5013         }
5014
5015         return I40E_SUCCESS;
5016 }
5017
5018 int
5019 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5020 {
5021         uint32_t reg;
5022         uint16_t j;
5023
5024         /* Wait until the request is finished */
5025         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5026                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5027                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5028                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5029                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5030                         break;
5031         }
5032
5033         if (on) {
5034                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5035                         return I40E_SUCCESS; /* Already on, skip next steps */
5036                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5037         } else {
5038                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5039                         return I40E_SUCCESS; /* Already off, skip next steps */
5040                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5041         }
5042
5043         /* Write the register */
5044         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5045         /* Check the result */
5046         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5047                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5048                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5049                 if (on) {
5050                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5051                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5052                                 break;
5053                 } else {
5054                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5055                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5056                                 break;
5057                 }
5058         }
5059
5060         /* Check if it is timeout */
5061         if (j >= I40E_CHK_Q_ENA_COUNT) {
5062                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5063                             (on ? "enable" : "disable"), q_idx);
5064                 return I40E_ERR_TIMEOUT;
5065         }
5066
5067         return I40E_SUCCESS;
5068 }
5069 /* Switch on or off the rx queues */
5070 static int
5071 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5072 {
5073         struct rte_eth_dev_data *dev_data = pf->dev_data;
5074         struct i40e_rx_queue *rxq;
5075         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5076         uint16_t i;
5077         int ret;
5078
5079         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5080                 rxq = dev_data->rx_queues[i];
5081                 /* Don't operate the queue if not configured or
5082                  * if starting only per queue */
5083                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5084                         continue;
5085                 if (on)
5086                         ret = i40e_dev_rx_queue_start(dev, i);
5087                 else
5088                         ret = i40e_dev_rx_queue_stop(dev, i);
5089                 if (ret != I40E_SUCCESS)
5090                         return ret;
5091         }
5092
5093         return I40E_SUCCESS;
5094 }
5095
5096 /* Switch on or off all the rx/tx queues */
5097 int
5098 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5099 {
5100         int ret;
5101
5102         if (on) {
5103                 /* enable rx queues before enabling tx queues */
5104                 ret = i40e_dev_switch_rx_queues(pf, on);
5105                 if (ret) {
5106                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5107                         return ret;
5108                 }
5109                 ret = i40e_dev_switch_tx_queues(pf, on);
5110         } else {
5111                 /* Stop tx queues before stopping rx queues */
5112                 ret = i40e_dev_switch_tx_queues(pf, on);
5113                 if (ret) {
5114                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5115                         return ret;
5116                 }
5117                 ret = i40e_dev_switch_rx_queues(pf, on);
5118         }
5119
5120         return ret;
5121 }
5122
5123 /* Initialize VSI for TX */
5124 static int
5125 i40e_dev_tx_init(struct i40e_pf *pf)
5126 {
5127         struct rte_eth_dev_data *data = pf->dev_data;
5128         uint16_t i;
5129         uint32_t ret = I40E_SUCCESS;
5130         struct i40e_tx_queue *txq;
5131
5132         for (i = 0; i < data->nb_tx_queues; i++) {
5133                 txq = data->tx_queues[i];
5134                 if (!txq || !txq->q_set)
5135                         continue;
5136                 ret = i40e_tx_queue_init(txq);
5137                 if (ret != I40E_SUCCESS)
5138                         break;
5139         }
5140         if (ret == I40E_SUCCESS)
5141                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5142                                      ->eth_dev);
5143
5144         return ret;
5145 }
5146
5147 /* Initialize VSI for RX */
5148 static int
5149 i40e_dev_rx_init(struct i40e_pf *pf)
5150 {
5151         struct rte_eth_dev_data *data = pf->dev_data;
5152         int ret = I40E_SUCCESS;
5153         uint16_t i;
5154         struct i40e_rx_queue *rxq;
5155
5156         i40e_pf_config_mq_rx(pf);
5157         for (i = 0; i < data->nb_rx_queues; i++) {
5158                 rxq = data->rx_queues[i];
5159                 if (!rxq || !rxq->q_set)
5160                         continue;
5161
5162                 ret = i40e_rx_queue_init(rxq);
5163                 if (ret != I40E_SUCCESS) {
5164                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5165                                     "initialization");
5166                         break;
5167                 }
5168         }
5169         if (ret == I40E_SUCCESS)
5170                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5171                                      ->eth_dev);
5172
5173         return ret;
5174 }
5175
5176 static int
5177 i40e_dev_rxtx_init(struct i40e_pf *pf)
5178 {
5179         int err;
5180
5181         err = i40e_dev_tx_init(pf);
5182         if (err) {
5183                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5184                 return err;
5185         }
5186         err = i40e_dev_rx_init(pf);
5187         if (err) {
5188                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5189                 return err;
5190         }
5191
5192         return err;
5193 }
5194
5195 static int
5196 i40e_vmdq_setup(struct rte_eth_dev *dev)
5197 {
5198         struct rte_eth_conf *conf = &dev->data->dev_conf;
5199         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5200         int i, err, conf_vsis, j, loop;
5201         struct i40e_vsi *vsi;
5202         struct i40e_vmdq_info *vmdq_info;
5203         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5204         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5205
5206         /*
5207          * Disable interrupt to avoid message from VF. Furthermore, it will
5208          * avoid race condition in VSI creation/destroy.
5209          */
5210         i40e_pf_disable_irq0(hw);
5211
5212         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5213                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5214                 return -ENOTSUP;
5215         }
5216
5217         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5218         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5219                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5220                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5221                         pf->max_nb_vmdq_vsi);
5222                 return -ENOTSUP;
5223         }
5224
5225         if (pf->vmdq != NULL) {
5226                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5227                 return 0;
5228         }
5229
5230         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5231                                 sizeof(*vmdq_info) * conf_vsis, 0);
5232
5233         if (pf->vmdq == NULL) {
5234                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5235                 return -ENOMEM;
5236         }
5237
5238         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5239
5240         /* Create VMDQ VSI */
5241         for (i = 0; i < conf_vsis; i++) {
5242                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5243                                 vmdq_conf->enable_loop_back);
5244                 if (vsi == NULL) {
5245                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5246                         err = -1;
5247                         goto err_vsi_setup;
5248                 }
5249                 vmdq_info = &pf->vmdq[i];
5250                 vmdq_info->pf = pf;
5251                 vmdq_info->vsi = vsi;
5252         }
5253         pf->nb_cfg_vmdq_vsi = conf_vsis;
5254
5255         /* Configure Vlan */
5256         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5257         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5258                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5259                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5260                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5261                                         vmdq_conf->pool_map[i].vlan_id, j);
5262
5263                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5264                                                 vmdq_conf->pool_map[i].vlan_id);
5265                                 if (err) {
5266                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5267                                         err = -1;
5268                                         goto err_vsi_setup;
5269                                 }
5270                         }
5271                 }
5272         }
5273
5274         i40e_pf_enable_irq0(hw);
5275
5276         return 0;
5277
5278 err_vsi_setup:
5279         for (i = 0; i < conf_vsis; i++)
5280                 if (pf->vmdq[i].vsi == NULL)
5281                         break;
5282                 else
5283                         i40e_vsi_release(pf->vmdq[i].vsi);
5284
5285         rte_free(pf->vmdq);
5286         pf->vmdq = NULL;
5287         i40e_pf_enable_irq0(hw);
5288         return err;
5289 }
5290
5291 static void
5292 i40e_stat_update_32(struct i40e_hw *hw,
5293                    uint32_t reg,
5294                    bool offset_loaded,
5295                    uint64_t *offset,
5296                    uint64_t *stat)
5297 {
5298         uint64_t new_data;
5299
5300         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5301         if (!offset_loaded)
5302                 *offset = new_data;
5303
5304         if (new_data >= *offset)
5305                 *stat = (uint64_t)(new_data - *offset);
5306         else
5307                 *stat = (uint64_t)((new_data +
5308                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5309 }
5310
5311 static void
5312 i40e_stat_update_48(struct i40e_hw *hw,
5313                    uint32_t hireg,
5314                    uint32_t loreg,
5315                    bool offset_loaded,
5316                    uint64_t *offset,
5317                    uint64_t *stat)
5318 {
5319         uint64_t new_data;
5320
5321         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5322         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5323                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5324
5325         if (!offset_loaded)
5326                 *offset = new_data;
5327
5328         if (new_data >= *offset)
5329                 *stat = new_data - *offset;
5330         else
5331                 *stat = (uint64_t)((new_data +
5332                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5333
5334         *stat &= I40E_48_BIT_MASK;
5335 }
5336
5337 /* Disable IRQ0 */
5338 void
5339 i40e_pf_disable_irq0(struct i40e_hw *hw)
5340 {
5341         /* Disable all interrupt types */
5342         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5343         I40E_WRITE_FLUSH(hw);
5344 }
5345
5346 /* Enable IRQ0 */
5347 void
5348 i40e_pf_enable_irq0(struct i40e_hw *hw)
5349 {
5350         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5351                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5352                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5353                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5354         I40E_WRITE_FLUSH(hw);
5355 }
5356
5357 static void
5358 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5359 {
5360         /* read pending request and disable first */
5361         i40e_pf_disable_irq0(hw);
5362         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5363         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5364                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5365
5366         if (no_queue)
5367                 /* Link no queues with irq0 */
5368                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5369                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5370 }
5371
5372 static void
5373 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5374 {
5375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5376         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5377         int i;
5378         uint16_t abs_vf_id;
5379         uint32_t index, offset, val;
5380
5381         if (!pf->vfs)
5382                 return;
5383         /**
5384          * Try to find which VF trigger a reset, use absolute VF id to access
5385          * since the reg is global register.
5386          */
5387         for (i = 0; i < pf->vf_num; i++) {
5388                 abs_vf_id = hw->func_caps.vf_base_id + i;
5389                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5390                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5391                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5392                 /* VFR event occured */
5393                 if (val & (0x1 << offset)) {
5394                         int ret;
5395
5396                         /* Clear the event first */
5397                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5398                                                         (0x1 << offset));
5399                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5400                         /**
5401                          * Only notify a VF reset event occured,
5402                          * don't trigger another SW reset
5403                          */
5404                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5405                         if (ret != I40E_SUCCESS)
5406                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5407                 }
5408         }
5409 }
5410
5411 static void
5412 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5413 {
5414         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5415         struct i40e_arq_event_info info;
5416         uint16_t pending, opcode;
5417         int ret;
5418
5419         info.buf_len = I40E_AQ_BUF_SZ;
5420         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5421         if (!info.msg_buf) {
5422                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5423                 return;
5424         }
5425
5426         pending = 1;
5427         while (pending) {
5428                 ret = i40e_clean_arq_element(hw, &info, &pending);
5429
5430                 if (ret != I40E_SUCCESS) {
5431                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5432                                     "aq_err: %u", hw->aq.asq_last_status);
5433                         break;
5434                 }
5435                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5436
5437                 switch (opcode) {
5438                 case i40e_aqc_opc_send_msg_to_pf:
5439                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5440                         i40e_pf_host_handle_vf_msg(dev,
5441                                         rte_le_to_cpu_16(info.desc.retval),
5442                                         rte_le_to_cpu_32(info.desc.cookie_high),
5443                                         rte_le_to_cpu_32(info.desc.cookie_low),
5444                                         info.msg_buf,
5445                                         info.msg_len);
5446                         break;
5447                 default:
5448                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5449                                     opcode);
5450                         break;
5451                 }
5452         }
5453         rte_free(info.msg_buf);
5454 }
5455
5456 /*
5457  * Interrupt handler is registered as the alarm callback for handling LSC
5458  * interrupt in a definite of time, in order to wait the NIC into a stable
5459  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5460  * no need for link down interrupt.
5461  */
5462 static void
5463 i40e_dev_interrupt_delayed_handler(void *param)
5464 {
5465         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5466         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5467         uint32_t icr0;
5468
5469         /* read interrupt causes again */
5470         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5471
5472 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5473         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5474                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5475         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5476                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5477         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5478                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5479         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5480                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5481         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5482                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5483                                                                 "state\n");
5484         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5485                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5486         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5487                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5488 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5489
5490         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5491                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5492                 i40e_dev_handle_vfr_event(dev);
5493         }
5494         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5495                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5496                 i40e_dev_handle_aq_msg(dev);
5497         }
5498
5499         /* handle the link up interrupt in an alarm callback */
5500         i40e_dev_link_update(dev, 0);
5501         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5502
5503         i40e_pf_enable_irq0(hw);
5504         rte_intr_enable(&(dev->pci_dev->intr_handle));
5505 }
5506
5507 /**
5508  * Interrupt handler triggered by NIC  for handling
5509  * specific interrupt.
5510  *
5511  * @param handle
5512  *  Pointer to interrupt handle.
5513  * @param param
5514  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5515  *
5516  * @return
5517  *  void
5518  */
5519 static void
5520 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5521                            void *param)
5522 {
5523         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5525         uint32_t icr0;
5526
5527         /* Disable interrupt */
5528         i40e_pf_disable_irq0(hw);
5529
5530         /* read out interrupt causes */
5531         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5532
5533         /* No interrupt event indicated */
5534         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5535                 PMD_DRV_LOG(INFO, "No interrupt event");
5536                 goto done;
5537         }
5538 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5539         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5540                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5541         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5542                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5543         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5544                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5545         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5546                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5547         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5548                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5549         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5550                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5551         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5552                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5553 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5554
5555         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5556                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5557                 i40e_dev_handle_vfr_event(dev);
5558         }
5559         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5560                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5561                 i40e_dev_handle_aq_msg(dev);
5562         }
5563
5564         /* Link Status Change interrupt */
5565         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5566 #define I40E_US_PER_SECOND 1000000
5567                 struct rte_eth_link link;
5568
5569                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5570                 memset(&link, 0, sizeof(link));
5571                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5572                 i40e_dev_link_update(dev, 0);
5573
5574                 /*
5575                  * For link up interrupt, it needs to wait 1 second to let the
5576                  * hardware be a stable state. Otherwise several consecutive
5577                  * interrupts can be observed.
5578                  * For link down interrupt, no need to wait.
5579                  */
5580                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5581                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5582                         return;
5583                 else
5584                         _rte_eth_dev_callback_process(dev,
5585                                 RTE_ETH_EVENT_INTR_LSC);
5586         }
5587
5588 done:
5589         /* Enable interrupt */
5590         i40e_pf_enable_irq0(hw);
5591         rte_intr_enable(&(dev->pci_dev->intr_handle));
5592 }
5593
5594 static int
5595 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5596                          struct i40e_macvlan_filter *filter,
5597                          int total)
5598 {
5599         int ele_num, ele_buff_size;
5600         int num, actual_num, i;
5601         uint16_t flags;
5602         int ret = I40E_SUCCESS;
5603         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5604         struct i40e_aqc_add_macvlan_element_data *req_list;
5605
5606         if (filter == NULL  || total == 0)
5607                 return I40E_ERR_PARAM;
5608         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5609         ele_buff_size = hw->aq.asq_buf_size;
5610
5611         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5612         if (req_list == NULL) {
5613                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5614                 return I40E_ERR_NO_MEMORY;
5615         }
5616
5617         num = 0;
5618         do {
5619                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5620                 memset(req_list, 0, ele_buff_size);
5621
5622                 for (i = 0; i < actual_num; i++) {
5623                         (void)rte_memcpy(req_list[i].mac_addr,
5624                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5625                         req_list[i].vlan_tag =
5626                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5627
5628                         switch (filter[num + i].filter_type) {
5629                         case RTE_MAC_PERFECT_MATCH:
5630                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5631                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5632                                 break;
5633                         case RTE_MACVLAN_PERFECT_MATCH:
5634                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5635                                 break;
5636                         case RTE_MAC_HASH_MATCH:
5637                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5638                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5639                                 break;
5640                         case RTE_MACVLAN_HASH_MATCH:
5641                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5642                                 break;
5643                         default:
5644                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5645                                 ret = I40E_ERR_PARAM;
5646                                 goto DONE;
5647                         }
5648
5649                         req_list[i].queue_number = 0;
5650
5651                         req_list[i].flags = rte_cpu_to_le_16(flags);
5652                 }
5653
5654                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5655                                                 actual_num, NULL);
5656                 if (ret != I40E_SUCCESS) {
5657                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5658                         goto DONE;
5659                 }
5660                 num += actual_num;
5661         } while (num < total);
5662
5663 DONE:
5664         rte_free(req_list);
5665         return ret;
5666 }
5667
5668 static int
5669 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5670                             struct i40e_macvlan_filter *filter,
5671                             int total)
5672 {
5673         int ele_num, ele_buff_size;
5674         int num, actual_num, i;
5675         uint16_t flags;
5676         int ret = I40E_SUCCESS;
5677         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5678         struct i40e_aqc_remove_macvlan_element_data *req_list;
5679
5680         if (filter == NULL  || total == 0)
5681                 return I40E_ERR_PARAM;
5682
5683         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5684         ele_buff_size = hw->aq.asq_buf_size;
5685
5686         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5687         if (req_list == NULL) {
5688                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5689                 return I40E_ERR_NO_MEMORY;
5690         }
5691
5692         num = 0;
5693         do {
5694                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5695                 memset(req_list, 0, ele_buff_size);
5696
5697                 for (i = 0; i < actual_num; i++) {
5698                         (void)rte_memcpy(req_list[i].mac_addr,
5699                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5700                         req_list[i].vlan_tag =
5701                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5702
5703                         switch (filter[num + i].filter_type) {
5704                         case RTE_MAC_PERFECT_MATCH:
5705                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5706                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5707                                 break;
5708                         case RTE_MACVLAN_PERFECT_MATCH:
5709                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5710                                 break;
5711                         case RTE_MAC_HASH_MATCH:
5712                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5713                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5714                                 break;
5715                         case RTE_MACVLAN_HASH_MATCH:
5716                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5717                                 break;
5718                         default:
5719                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5720                                 ret = I40E_ERR_PARAM;
5721                                 goto DONE;
5722                         }
5723                         req_list[i].flags = rte_cpu_to_le_16(flags);
5724                 }
5725
5726                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5727                                                 actual_num, NULL);
5728                 if (ret != I40E_SUCCESS) {
5729                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5730                         goto DONE;
5731                 }
5732                 num += actual_num;
5733         } while (num < total);
5734
5735 DONE:
5736         rte_free(req_list);
5737         return ret;
5738 }
5739
5740 /* Find out specific MAC filter */
5741 static struct i40e_mac_filter *
5742 i40e_find_mac_filter(struct i40e_vsi *vsi,
5743                          struct ether_addr *macaddr)
5744 {
5745         struct i40e_mac_filter *f;
5746
5747         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5748                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5749                         return f;
5750         }
5751
5752         return NULL;
5753 }
5754
5755 static bool
5756 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5757                          uint16_t vlan_id)
5758 {
5759         uint32_t vid_idx, vid_bit;
5760
5761         if (vlan_id > ETH_VLAN_ID_MAX)
5762                 return 0;
5763
5764         vid_idx = I40E_VFTA_IDX(vlan_id);
5765         vid_bit = I40E_VFTA_BIT(vlan_id);
5766
5767         if (vsi->vfta[vid_idx] & vid_bit)
5768                 return 1;
5769         else
5770                 return 0;
5771 }
5772
5773 static void
5774 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5775                          uint16_t vlan_id, bool on)
5776 {
5777         uint32_t vid_idx, vid_bit;
5778
5779         if (vlan_id > ETH_VLAN_ID_MAX)
5780                 return;
5781
5782         vid_idx = I40E_VFTA_IDX(vlan_id);
5783         vid_bit = I40E_VFTA_BIT(vlan_id);
5784
5785         if (on)
5786                 vsi->vfta[vid_idx] |= vid_bit;
5787         else
5788                 vsi->vfta[vid_idx] &= ~vid_bit;
5789 }
5790
5791 /**
5792  * Find all vlan options for specific mac addr,
5793  * return with actual vlan found.
5794  */
5795 static inline int
5796 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5797                            struct i40e_macvlan_filter *mv_f,
5798                            int num, struct ether_addr *addr)
5799 {
5800         int i;
5801         uint32_t j, k;
5802
5803         /**
5804          * Not to use i40e_find_vlan_filter to decrease the loop time,
5805          * although the code looks complex.
5806           */
5807         if (num < vsi->vlan_num)
5808                 return I40E_ERR_PARAM;
5809
5810         i = 0;
5811         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5812                 if (vsi->vfta[j]) {
5813                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5814                                 if (vsi->vfta[j] & (1 << k)) {
5815                                         if (i > num - 1) {
5816                                                 PMD_DRV_LOG(ERR, "vlan number "
5817                                                             "not match");
5818                                                 return I40E_ERR_PARAM;
5819                                         }
5820                                         (void)rte_memcpy(&mv_f[i].macaddr,
5821                                                         addr, ETH_ADDR_LEN);
5822                                         mv_f[i].vlan_id =
5823                                                 j * I40E_UINT32_BIT_SIZE + k;
5824                                         i++;
5825                                 }
5826                         }
5827                 }
5828         }
5829         return I40E_SUCCESS;
5830 }
5831
5832 static inline int
5833 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5834                            struct i40e_macvlan_filter *mv_f,
5835                            int num,
5836                            uint16_t vlan)
5837 {
5838         int i = 0;
5839         struct i40e_mac_filter *f;
5840
5841         if (num < vsi->mac_num)
5842                 return I40E_ERR_PARAM;
5843
5844         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5845                 if (i > num - 1) {
5846                         PMD_DRV_LOG(ERR, "buffer number not match");
5847                         return I40E_ERR_PARAM;
5848                 }
5849                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5850                                 ETH_ADDR_LEN);
5851                 mv_f[i].vlan_id = vlan;
5852                 mv_f[i].filter_type = f->mac_info.filter_type;
5853                 i++;
5854         }
5855
5856         return I40E_SUCCESS;
5857 }
5858
5859 static int
5860 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5861 {
5862         int i, num;
5863         struct i40e_mac_filter *f;
5864         struct i40e_macvlan_filter *mv_f;
5865         int ret = I40E_SUCCESS;
5866
5867         if (vsi == NULL || vsi->mac_num == 0)
5868                 return I40E_ERR_PARAM;
5869
5870         /* Case that no vlan is set */
5871         if (vsi->vlan_num == 0)
5872                 num = vsi->mac_num;
5873         else
5874                 num = vsi->mac_num * vsi->vlan_num;
5875
5876         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5877         if (mv_f == NULL) {
5878                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5879                 return I40E_ERR_NO_MEMORY;
5880         }
5881
5882         i = 0;
5883         if (vsi->vlan_num == 0) {
5884                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5885                         (void)rte_memcpy(&mv_f[i].macaddr,
5886                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5887                         mv_f[i].vlan_id = 0;
5888                         i++;
5889                 }
5890         } else {
5891                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5892                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5893                                         vsi->vlan_num, &f->mac_info.mac_addr);
5894                         if (ret != I40E_SUCCESS)
5895                                 goto DONE;
5896                         i += vsi->vlan_num;
5897                 }
5898         }
5899
5900         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5901 DONE:
5902         rte_free(mv_f);
5903
5904         return ret;
5905 }
5906
5907 int
5908 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5909 {
5910         struct i40e_macvlan_filter *mv_f;
5911         int mac_num;
5912         int ret = I40E_SUCCESS;
5913
5914         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5915                 return I40E_ERR_PARAM;
5916
5917         /* If it's already set, just return */
5918         if (i40e_find_vlan_filter(vsi,vlan))
5919                 return I40E_SUCCESS;
5920
5921         mac_num = vsi->mac_num;
5922
5923         if (mac_num == 0) {
5924                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5925                 return I40E_ERR_PARAM;
5926         }
5927
5928         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5929
5930         if (mv_f == NULL) {
5931                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5932                 return I40E_ERR_NO_MEMORY;
5933         }
5934
5935         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5936
5937         if (ret != I40E_SUCCESS)
5938                 goto DONE;
5939
5940         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5941
5942         if (ret != I40E_SUCCESS)
5943                 goto DONE;
5944
5945         i40e_set_vlan_filter(vsi, vlan, 1);
5946
5947         vsi->vlan_num++;
5948         ret = I40E_SUCCESS;
5949 DONE:
5950         rte_free(mv_f);
5951         return ret;
5952 }
5953
5954 int
5955 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5956 {
5957         struct i40e_macvlan_filter *mv_f;
5958         int mac_num;
5959         int ret = I40E_SUCCESS;
5960
5961         /**
5962          * Vlan 0 is the generic filter for untagged packets
5963          * and can't be removed.
5964          */
5965         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5966                 return I40E_ERR_PARAM;
5967
5968         /* If can't find it, just return */
5969         if (!i40e_find_vlan_filter(vsi, vlan))
5970                 return I40E_ERR_PARAM;
5971
5972         mac_num = vsi->mac_num;
5973
5974         if (mac_num == 0) {
5975                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5976                 return I40E_ERR_PARAM;
5977         }
5978
5979         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5980
5981         if (mv_f == NULL) {
5982                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5983                 return I40E_ERR_NO_MEMORY;
5984         }
5985
5986         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5987
5988         if (ret != I40E_SUCCESS)
5989                 goto DONE;
5990
5991         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5992
5993         if (ret != I40E_SUCCESS)
5994                 goto DONE;
5995
5996         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5997         if (vsi->vlan_num == 1) {
5998                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5999                 if (ret != I40E_SUCCESS)
6000                         goto DONE;
6001
6002                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6003                 if (ret != I40E_SUCCESS)
6004                         goto DONE;
6005         }
6006
6007         i40e_set_vlan_filter(vsi, vlan, 0);
6008
6009         vsi->vlan_num--;
6010         ret = I40E_SUCCESS;
6011 DONE:
6012         rte_free(mv_f);
6013         return ret;
6014 }
6015
6016 int
6017 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6018 {
6019         struct i40e_mac_filter *f;
6020         struct i40e_macvlan_filter *mv_f;
6021         int i, vlan_num = 0;
6022         int ret = I40E_SUCCESS;
6023
6024         /* If it's add and we've config it, return */
6025         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6026         if (f != NULL)
6027                 return I40E_SUCCESS;
6028         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6029                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6030
6031                 /**
6032                  * If vlan_num is 0, that's the first time to add mac,
6033                  * set mask for vlan_id 0.
6034                  */
6035                 if (vsi->vlan_num == 0) {
6036                         i40e_set_vlan_filter(vsi, 0, 1);
6037                         vsi->vlan_num = 1;
6038                 }
6039                 vlan_num = vsi->vlan_num;
6040         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6041                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6042                 vlan_num = 1;
6043
6044         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6045         if (mv_f == NULL) {
6046                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6047                 return I40E_ERR_NO_MEMORY;
6048         }
6049
6050         for (i = 0; i < vlan_num; i++) {
6051                 mv_f[i].filter_type = mac_filter->filter_type;
6052                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6053                                 ETH_ADDR_LEN);
6054         }
6055
6056         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6057                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6058                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6059                                         &mac_filter->mac_addr);
6060                 if (ret != I40E_SUCCESS)
6061                         goto DONE;
6062         }
6063
6064         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6065         if (ret != I40E_SUCCESS)
6066                 goto DONE;
6067
6068         /* Add the mac addr into mac list */
6069         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6070         if (f == NULL) {
6071                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6072                 ret = I40E_ERR_NO_MEMORY;
6073                 goto DONE;
6074         }
6075         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6076                         ETH_ADDR_LEN);
6077         f->mac_info.filter_type = mac_filter->filter_type;
6078         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6079         vsi->mac_num++;
6080
6081         ret = I40E_SUCCESS;
6082 DONE:
6083         rte_free(mv_f);
6084
6085         return ret;
6086 }
6087
6088 int
6089 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6090 {
6091         struct i40e_mac_filter *f;
6092         struct i40e_macvlan_filter *mv_f;
6093         int i, vlan_num;
6094         enum rte_mac_filter_type filter_type;
6095         int ret = I40E_SUCCESS;
6096
6097         /* Can't find it, return an error */
6098         f = i40e_find_mac_filter(vsi, addr);
6099         if (f == NULL)
6100                 return I40E_ERR_PARAM;
6101
6102         vlan_num = vsi->vlan_num;
6103         filter_type = f->mac_info.filter_type;
6104         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6105                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6106                 if (vlan_num == 0) {
6107                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6108                         return I40E_ERR_PARAM;
6109                 }
6110         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6111                         filter_type == RTE_MAC_HASH_MATCH)
6112                 vlan_num = 1;
6113
6114         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6115         if (mv_f == NULL) {
6116                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6117                 return I40E_ERR_NO_MEMORY;
6118         }
6119
6120         for (i = 0; i < vlan_num; i++) {
6121                 mv_f[i].filter_type = filter_type;
6122                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6123                                 ETH_ADDR_LEN);
6124         }
6125         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6126                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6127                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6128                 if (ret != I40E_SUCCESS)
6129                         goto DONE;
6130         }
6131
6132         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6133         if (ret != I40E_SUCCESS)
6134                 goto DONE;
6135
6136         /* Remove the mac addr into mac list */
6137         TAILQ_REMOVE(&vsi->mac_list, f, next);
6138         rte_free(f);
6139         vsi->mac_num--;
6140
6141         ret = I40E_SUCCESS;
6142 DONE:
6143         rte_free(mv_f);
6144         return ret;
6145 }
6146
6147 /* Configure hash enable flags for RSS */
6148 uint64_t
6149 i40e_config_hena(uint64_t flags)
6150 {
6151         uint64_t hena = 0;
6152
6153         if (!flags)
6154                 return hena;
6155
6156         if (flags & ETH_RSS_FRAG_IPV4)
6157                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6158         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6159                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6160         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6161                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6162         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6163                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6164         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6165                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6166         if (flags & ETH_RSS_FRAG_IPV6)
6167                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6168         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6169                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6170         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6171                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6172         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6173                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6174         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6175                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6176         if (flags & ETH_RSS_L2_PAYLOAD)
6177                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6178
6179         return hena;
6180 }
6181
6182 /* Parse the hash enable flags */
6183 uint64_t
6184 i40e_parse_hena(uint64_t flags)
6185 {
6186         uint64_t rss_hf = 0;
6187
6188         if (!flags)
6189                 return rss_hf;
6190         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6191                 rss_hf |= ETH_RSS_FRAG_IPV4;
6192         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6193                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6194         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6195                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6196         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6197                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6198         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6199                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6200         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6201                 rss_hf |= ETH_RSS_FRAG_IPV6;
6202         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6203                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6204         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6205                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6206         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6207                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6208         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6209                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6210         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6211                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6212
6213         return rss_hf;
6214 }
6215
6216 /* Disable RSS */
6217 static void
6218 i40e_pf_disable_rss(struct i40e_pf *pf)
6219 {
6220         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6221         uint64_t hena;
6222
6223         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6224         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6225         hena &= ~I40E_RSS_HENA_ALL;
6226         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6227         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6228         I40E_WRITE_FLUSH(hw);
6229 }
6230
6231 static int
6232 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6233 {
6234         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6235         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6236         int ret = 0;
6237
6238         if (!key || key_len == 0) {
6239                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6240                 return 0;
6241         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6242                 sizeof(uint32_t)) {
6243                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6244                 return -EINVAL;
6245         }
6246
6247         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6248                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6249                         (struct i40e_aqc_get_set_rss_key_data *)key;
6250
6251                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6252                 if (ret)
6253                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6254                                      "via AQ");
6255         } else {
6256                 uint32_t *hash_key = (uint32_t *)key;
6257                 uint16_t i;
6258
6259                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6260                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6261                 I40E_WRITE_FLUSH(hw);
6262         }
6263
6264         return ret;
6265 }
6266
6267 static int
6268 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6269 {
6270         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6271         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6272         int ret;
6273
6274         if (!key || !key_len)
6275                 return -EINVAL;
6276
6277         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6278                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6279                         (struct i40e_aqc_get_set_rss_key_data *)key);
6280                 if (ret) {
6281                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6282                         return ret;
6283                 }
6284         } else {
6285                 uint32_t *key_dw = (uint32_t *)key;
6286                 uint16_t i;
6287
6288                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6289                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6290         }
6291         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6292
6293         return 0;
6294 }
6295
6296 static int
6297 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6298 {
6299         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6300         uint64_t rss_hf;
6301         uint64_t hena;
6302         int ret;
6303
6304         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6305                                rss_conf->rss_key_len);
6306         if (ret)
6307                 return ret;
6308
6309         rss_hf = rss_conf->rss_hf;
6310         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6311         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6312         hena &= ~I40E_RSS_HENA_ALL;
6313         hena |= i40e_config_hena(rss_hf);
6314         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6315         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6316         I40E_WRITE_FLUSH(hw);
6317
6318         return 0;
6319 }
6320
6321 static int
6322 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6323                          struct rte_eth_rss_conf *rss_conf)
6324 {
6325         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6327         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6328         uint64_t hena;
6329
6330         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6331         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6332         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6333                 if (rss_hf != 0) /* Enable RSS */
6334                         return -EINVAL;
6335                 return 0; /* Nothing to do */
6336         }
6337         /* RSS enabled */
6338         if (rss_hf == 0) /* Disable RSS */
6339                 return -EINVAL;
6340
6341         return i40e_hw_rss_hash_set(pf, rss_conf);
6342 }
6343
6344 static int
6345 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6346                            struct rte_eth_rss_conf *rss_conf)
6347 {
6348         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6349         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6350         uint64_t hena;
6351
6352         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6353                          &rss_conf->rss_key_len);
6354
6355         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6356         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6357         rss_conf->rss_hf = i40e_parse_hena(hena);
6358
6359         return 0;
6360 }
6361
6362 static int
6363 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6364 {
6365         switch (filter_type) {
6366         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6367                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6368                 break;
6369         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6370                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6371                 break;
6372         case RTE_TUNNEL_FILTER_IMAC_TENID:
6373                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6374                 break;
6375         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6376                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6377                 break;
6378         case ETH_TUNNEL_FILTER_IMAC:
6379                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6380                 break;
6381         case ETH_TUNNEL_FILTER_OIP:
6382                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6383                 break;
6384         case ETH_TUNNEL_FILTER_IIP:
6385                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6386                 break;
6387         default:
6388                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6389                 return -EINVAL;
6390         }
6391
6392         return 0;
6393 }
6394
6395 static int
6396 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6397                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6398                         uint8_t add)
6399 {
6400         uint16_t ip_type;
6401         uint32_t ipv4_addr;
6402         uint8_t i, tun_type = 0;
6403         /* internal varialbe to convert ipv6 byte order */
6404         uint32_t convert_ipv6[4];
6405         int val, ret = 0;
6406         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6407         struct i40e_vsi *vsi = pf->main_vsi;
6408         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6409         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6410
6411         cld_filter = rte_zmalloc("tunnel_filter",
6412                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6413                 0);
6414
6415         if (NULL == cld_filter) {
6416                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6417                 return -EINVAL;
6418         }
6419         pfilter = cld_filter;
6420
6421         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6422         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6423
6424         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6425         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6426                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6427                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6428                 rte_memcpy(&pfilter->ipaddr.v4.data,
6429                                 &rte_cpu_to_le_32(ipv4_addr),
6430                                 sizeof(pfilter->ipaddr.v4.data));
6431         } else {
6432                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6433                 for (i = 0; i < 4; i++) {
6434                         convert_ipv6[i] =
6435                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6436                 }
6437                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6438                                 sizeof(pfilter->ipaddr.v6.data));
6439         }
6440
6441         /* check tunneled type */
6442         switch (tunnel_filter->tunnel_type) {
6443         case RTE_TUNNEL_TYPE_VXLAN:
6444                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6445                 break;
6446         case RTE_TUNNEL_TYPE_NVGRE:
6447                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6448                 break;
6449         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6450                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6451                 break;
6452         default:
6453                 /* Other tunnel types is not supported. */
6454                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6455                 rte_free(cld_filter);
6456                 return -EINVAL;
6457         }
6458
6459         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6460                                                 &pfilter->flags);
6461         if (val < 0) {
6462                 rte_free(cld_filter);
6463                 return -EINVAL;
6464         }
6465
6466         pfilter->flags |= rte_cpu_to_le_16(
6467                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6468                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6469         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6470         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6471
6472         if (add)
6473                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6474         else
6475                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6476                                                 cld_filter, 1);
6477
6478         rte_free(cld_filter);
6479         return ret;
6480 }
6481
6482 static int
6483 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6484 {
6485         uint8_t i;
6486
6487         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6488                 if (pf->vxlan_ports[i] == port)
6489                         return i;
6490         }
6491
6492         return -1;
6493 }
6494
6495 static int
6496 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6497 {
6498         int  idx, ret;
6499         uint8_t filter_idx;
6500         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6501
6502         idx = i40e_get_vxlan_port_idx(pf, port);
6503
6504         /* Check if port already exists */
6505         if (idx >= 0) {
6506                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6507                 return -EINVAL;
6508         }
6509
6510         /* Now check if there is space to add the new port */
6511         idx = i40e_get_vxlan_port_idx(pf, 0);
6512         if (idx < 0) {
6513                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6514                         "not adding port %d", port);
6515                 return -ENOSPC;
6516         }
6517
6518         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6519                                         &filter_idx, NULL);
6520         if (ret < 0) {
6521                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6522                 return -1;
6523         }
6524
6525         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6526                          port,  filter_idx);
6527
6528         /* New port: add it and mark its index in the bitmap */
6529         pf->vxlan_ports[idx] = port;
6530         pf->vxlan_bitmap |= (1 << idx);
6531
6532         if (!(pf->flags & I40E_FLAG_VXLAN))
6533                 pf->flags |= I40E_FLAG_VXLAN;
6534
6535         return 0;
6536 }
6537
6538 static int
6539 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6540 {
6541         int idx;
6542         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6543
6544         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6545                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6546                 return -EINVAL;
6547         }
6548
6549         idx = i40e_get_vxlan_port_idx(pf, port);
6550
6551         if (idx < 0) {
6552                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6553                 return -EINVAL;
6554         }
6555
6556         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6557                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6558                 return -1;
6559         }
6560
6561         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6562                         port, idx);
6563
6564         pf->vxlan_ports[idx] = 0;
6565         pf->vxlan_bitmap &= ~(1 << idx);
6566
6567         if (!pf->vxlan_bitmap)
6568                 pf->flags &= ~I40E_FLAG_VXLAN;
6569
6570         return 0;
6571 }
6572
6573 /* Add UDP tunneling port */
6574 static int
6575 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6576                              struct rte_eth_udp_tunnel *udp_tunnel)
6577 {
6578         int ret = 0;
6579         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6580
6581         if (udp_tunnel == NULL)
6582                 return -EINVAL;
6583
6584         switch (udp_tunnel->prot_type) {
6585         case RTE_TUNNEL_TYPE_VXLAN:
6586                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6587                 break;
6588
6589         case RTE_TUNNEL_TYPE_GENEVE:
6590         case RTE_TUNNEL_TYPE_TEREDO:
6591                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6592                 ret = -1;
6593                 break;
6594
6595         default:
6596                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6597                 ret = -1;
6598                 break;
6599         }
6600
6601         return ret;
6602 }
6603
6604 /* Remove UDP tunneling port */
6605 static int
6606 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6607                              struct rte_eth_udp_tunnel *udp_tunnel)
6608 {
6609         int ret = 0;
6610         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6611
6612         if (udp_tunnel == NULL)
6613                 return -EINVAL;
6614
6615         switch (udp_tunnel->prot_type) {
6616         case RTE_TUNNEL_TYPE_VXLAN:
6617                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6618                 break;
6619         case RTE_TUNNEL_TYPE_GENEVE:
6620         case RTE_TUNNEL_TYPE_TEREDO:
6621                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6622                 ret = -1;
6623                 break;
6624         default:
6625                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6626                 ret = -1;
6627                 break;
6628         }
6629
6630         return ret;
6631 }
6632
6633 /* Calculate the maximum number of contiguous PF queues that are configured */
6634 static int
6635 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6636 {
6637         struct rte_eth_dev_data *data = pf->dev_data;
6638         int i, num;
6639         struct i40e_rx_queue *rxq;
6640
6641         num = 0;
6642         for (i = 0; i < pf->lan_nb_qps; i++) {
6643                 rxq = data->rx_queues[i];
6644                 if (rxq && rxq->q_set)
6645                         num++;
6646                 else
6647                         break;
6648         }
6649
6650         return num;
6651 }
6652
6653 /* Configure RSS */
6654 static int
6655 i40e_pf_config_rss(struct i40e_pf *pf)
6656 {
6657         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6658         struct rte_eth_rss_conf rss_conf;
6659         uint32_t i, lut = 0;
6660         uint16_t j, num;
6661
6662         /*
6663          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6664          * It's necessary to calulate the actual PF queues that are configured.
6665          */
6666         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6667                 num = i40e_pf_calc_configured_queues_num(pf);
6668         else
6669                 num = pf->dev_data->nb_rx_queues;
6670
6671         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6672         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6673                         num);
6674
6675         if (num == 0) {
6676                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6677                 return -ENOTSUP;
6678         }
6679
6680         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6681                 if (j == num)
6682                         j = 0;
6683                 lut = (lut << 8) | (j & ((0x1 <<
6684                         hw->func_caps.rss_table_entry_width) - 1));
6685                 if ((i & 3) == 3)
6686                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6687         }
6688
6689         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6690         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6691                 i40e_pf_disable_rss(pf);
6692                 return 0;
6693         }
6694         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6695                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6696                 /* Random default keys */
6697                 static uint32_t rss_key_default[] = {0x6b793944,
6698                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6699                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6700                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6701
6702                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6703                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6704                                                         sizeof(uint32_t);
6705         }
6706
6707         return i40e_hw_rss_hash_set(pf, &rss_conf);
6708 }
6709
6710 static int
6711 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6712                                struct rte_eth_tunnel_filter_conf *filter)
6713 {
6714         if (pf == NULL || filter == NULL) {
6715                 PMD_DRV_LOG(ERR, "Invalid parameter");
6716                 return -EINVAL;
6717         }
6718
6719         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6720                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6721                 return -EINVAL;
6722         }
6723
6724         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6725                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6726                 return -EINVAL;
6727         }
6728
6729         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6730                 (is_zero_ether_addr(&filter->outer_mac))) {
6731                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6732                 return -EINVAL;
6733         }
6734
6735         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6736                 (is_zero_ether_addr(&filter->inner_mac))) {
6737                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6738                 return -EINVAL;
6739         }
6740
6741         return 0;
6742 }
6743
6744 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6745 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6746 static int
6747 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6748 {
6749         uint32_t val, reg;
6750         int ret = -EINVAL;
6751
6752         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6753         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6754
6755         if (len == 3) {
6756                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6757         } else if (len == 4) {
6758                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6759         } else {
6760                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6761                 return ret;
6762         }
6763
6764         if (reg != val) {
6765                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6766                                                    reg, NULL);
6767                 if (ret != 0)
6768                         return ret;
6769         } else {
6770                 ret = 0;
6771         }
6772         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6773                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6774
6775         return ret;
6776 }
6777
6778 static int
6779 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6780 {
6781         int ret = -EINVAL;
6782
6783         if (!hw || !cfg)
6784                 return -EINVAL;
6785
6786         switch (cfg->cfg_type) {
6787         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6788                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6789                 break;
6790         default:
6791                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6792                 break;
6793         }
6794
6795         return ret;
6796 }
6797
6798 static int
6799 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6800                                enum rte_filter_op filter_op,
6801                                void *arg)
6802 {
6803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6804         int ret = I40E_ERR_PARAM;
6805
6806         switch (filter_op) {
6807         case RTE_ETH_FILTER_SET:
6808                 ret = i40e_dev_global_config_set(hw,
6809                         (struct rte_eth_global_cfg *)arg);
6810                 break;
6811         default:
6812                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6813                 break;
6814         }
6815
6816         return ret;
6817 }
6818
6819 static int
6820 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6821                           enum rte_filter_op filter_op,
6822                           void *arg)
6823 {
6824         struct rte_eth_tunnel_filter_conf *filter;
6825         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6826         int ret = I40E_SUCCESS;
6827
6828         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6829
6830         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6831                 return I40E_ERR_PARAM;
6832
6833         switch (filter_op) {
6834         case RTE_ETH_FILTER_NOP:
6835                 if (!(pf->flags & I40E_FLAG_VXLAN))
6836                         ret = I40E_NOT_SUPPORTED;
6837                 break;
6838         case RTE_ETH_FILTER_ADD:
6839                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6840                 break;
6841         case RTE_ETH_FILTER_DELETE:
6842                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6843                 break;
6844         default:
6845                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6846                 ret = I40E_ERR_PARAM;
6847                 break;
6848         }
6849
6850         return ret;
6851 }
6852
6853 static int
6854 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6855 {
6856         int ret = 0;
6857         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6858
6859         /* RSS setup */
6860         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6861                 ret = i40e_pf_config_rss(pf);
6862         else
6863                 i40e_pf_disable_rss(pf);
6864
6865         return ret;
6866 }
6867
6868 /* Get the symmetric hash enable configurations per port */
6869 static void
6870 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6871 {
6872         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6873
6874         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6875 }
6876
6877 /* Set the symmetric hash enable configurations per port */
6878 static void
6879 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6880 {
6881         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6882
6883         if (enable > 0) {
6884                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6885                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6886                                                         "been enabled");
6887                         return;
6888                 }
6889                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6890         } else {
6891                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6892                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6893                                                         "been disabled");
6894                         return;
6895                 }
6896                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6897         }
6898         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6899         I40E_WRITE_FLUSH(hw);
6900 }
6901
6902 /*
6903  * Get global configurations of hash function type and symmetric hash enable
6904  * per flow type (pctype). Note that global configuration means it affects all
6905  * the ports on the same NIC.
6906  */
6907 static int
6908 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6909                                    struct rte_eth_hash_global_conf *g_cfg)
6910 {
6911         uint32_t reg, mask = I40E_FLOW_TYPES;
6912         uint16_t i;
6913         enum i40e_filter_pctype pctype;
6914
6915         memset(g_cfg, 0, sizeof(*g_cfg));
6916         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6917         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6918                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6919         else
6920                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6921         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6922                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6923
6924         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6925                 if (!(mask & (1UL << i)))
6926                         continue;
6927                 mask &= ~(1UL << i);
6928                 /* Bit set indicats the coresponding flow type is supported */
6929                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6930                 /* if flowtype is invalid, continue */
6931                 if (!I40E_VALID_FLOW(i))
6932                         continue;
6933                 pctype = i40e_flowtype_to_pctype(i);
6934                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6935                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6936                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6937         }
6938
6939         return 0;
6940 }
6941
6942 static int
6943 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6944 {
6945         uint32_t i;
6946         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6947
6948         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6949                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6950                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6951                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6952                                                 g_cfg->hash_func);
6953                 return -EINVAL;
6954         }
6955
6956         /*
6957          * As i40e supports less than 32 flow types, only first 32 bits need to
6958          * be checked.
6959          */
6960         mask0 = g_cfg->valid_bit_mask[0];
6961         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6962                 if (i == 0) {
6963                         /* Check if any unsupported flow type configured */
6964                         if ((mask0 | i40e_mask) ^ i40e_mask)
6965                                 goto mask_err;
6966                 } else {
6967                         if (g_cfg->valid_bit_mask[i])
6968                                 goto mask_err;
6969                 }
6970         }
6971
6972         return 0;
6973
6974 mask_err:
6975         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6976
6977         return -EINVAL;
6978 }
6979
6980 /*
6981  * Set global configurations of hash function type and symmetric hash enable
6982  * per flow type (pctype). Note any modifying global configuration will affect
6983  * all the ports on the same NIC.
6984  */
6985 static int
6986 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6987                                    struct rte_eth_hash_global_conf *g_cfg)
6988 {
6989         int ret;
6990         uint16_t i;
6991         uint32_t reg;
6992         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6993         enum i40e_filter_pctype pctype;
6994
6995         /* Check the input parameters */
6996         ret = i40e_hash_global_config_check(g_cfg);
6997         if (ret < 0)
6998                 return ret;
6999
7000         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7001                 if (!(mask0 & (1UL << i)))
7002                         continue;
7003                 mask0 &= ~(1UL << i);
7004                 /* if flowtype is invalid, continue */
7005                 if (!I40E_VALID_FLOW(i))
7006                         continue;
7007                 pctype = i40e_flowtype_to_pctype(i);
7008                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7009                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7010                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7011         }
7012
7013         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7014         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7015                 /* Toeplitz */
7016                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7017                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7018                                                                 "Toeplitz");
7019                         goto out;
7020                 }
7021                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7022         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7023                 /* Simple XOR */
7024                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7025                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7026                                                         "Simple XOR");
7027                         goto out;
7028                 }
7029                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7030         } else
7031                 /* Use the default, and keep it as it is */
7032                 goto out;
7033
7034         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7035
7036 out:
7037         I40E_WRITE_FLUSH(hw);
7038
7039         return 0;
7040 }
7041
7042 /**
7043  * Valid input sets for hash and flow director filters per PCTYPE
7044  */
7045 static uint64_t
7046 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7047                 enum rte_filter_type filter)
7048 {
7049         uint64_t valid;
7050
7051         static const uint64_t valid_hash_inset_table[] = {
7052                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7053                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7054                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7055                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7056                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7057                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7058                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7059                         I40E_INSET_FLEX_PAYLOAD,
7060                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7061                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7062                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7063                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7064                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7065                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7066                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7067                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7068                         I40E_INSET_FLEX_PAYLOAD,
7069                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7070                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7071                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7072                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7073                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7074                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7075                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7076                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7077                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7078                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7079                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7080                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7081                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7082                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7083                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7084                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7085                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7086                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7087                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7088                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7089                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7090                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7091                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7092                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7093                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7094                         I40E_INSET_FLEX_PAYLOAD,
7095                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7096                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7097                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7098                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7099                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7100                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7101                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7102                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7103                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7104                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7105                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7106                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7107                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7108                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7109                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7110                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7111                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7112                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7113                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7114                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7115                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7116                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7117                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7118                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7119                         I40E_INSET_FLEX_PAYLOAD,
7120                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7121                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7122                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7123                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7124                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7125                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7126                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7127                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7128                         I40E_INSET_FLEX_PAYLOAD,
7129                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7130                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7131                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7132                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7133                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7134                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7135                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7136                         I40E_INSET_FLEX_PAYLOAD,
7137                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7138                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7139                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7140                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7141                         I40E_INSET_FLEX_PAYLOAD,
7142         };
7143
7144         /**
7145          * Flow director supports only fields defined in
7146          * union rte_eth_fdir_flow.
7147          */
7148         static const uint64_t valid_fdir_inset_table[] = {
7149                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7150                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7151                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7152                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7153                 I40E_INSET_IPV4_TTL,
7154                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7155                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7156                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7157                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7158                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7159                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7160                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7161                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7162                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7163                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7164                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7165                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7166                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7167                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7168                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7169                 I40E_INSET_SCTP_VT,
7170                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7171                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7172                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7173                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7174                 I40E_INSET_IPV4_TTL,
7175                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7176                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7177                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7178                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7179                 I40E_INSET_IPV6_HOP_LIMIT,
7180                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7181                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7182                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7183                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7184                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7185                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7186                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7187                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7188                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7189                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7190                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7191                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7192                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7193                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7194                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7195                 I40E_INSET_SCTP_VT,
7196                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7197                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7198                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7199                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7200                 I40E_INSET_IPV6_HOP_LIMIT,
7201                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7202                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7203                 I40E_INSET_LAST_ETHER_TYPE,
7204         };
7205
7206         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7207                 return 0;
7208         if (filter == RTE_ETH_FILTER_HASH)
7209                 valid = valid_hash_inset_table[pctype];
7210         else
7211                 valid = valid_fdir_inset_table[pctype];
7212
7213         return valid;
7214 }
7215
7216 /**
7217  * Validate if the input set is allowed for a specific PCTYPE
7218  */
7219 static int
7220 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7221                 enum rte_filter_type filter, uint64_t inset)
7222 {
7223         uint64_t valid;
7224
7225         valid = i40e_get_valid_input_set(pctype, filter);
7226         if (inset & (~valid))
7227                 return -EINVAL;
7228
7229         return 0;
7230 }
7231
7232 /* default input set fields combination per pctype */
7233 static uint64_t
7234 i40e_get_default_input_set(uint16_t pctype)
7235 {
7236         static const uint64_t default_inset_table[] = {
7237                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7238                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7239                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7240                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7241                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7242                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7243                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7244                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7245                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7246                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7247                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7248                         I40E_INSET_SCTP_VT,
7249                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7250                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7251                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7252                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7253                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7254                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7255                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7256                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7257                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7258                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7259                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7260                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7261                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7262                         I40E_INSET_SCTP_VT,
7263                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7264                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7265                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7266                         I40E_INSET_LAST_ETHER_TYPE,
7267         };
7268
7269         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7270                 return 0;
7271
7272         return default_inset_table[pctype];
7273 }
7274
7275 /**
7276  * Parse the input set from index to logical bit masks
7277  */
7278 static int
7279 i40e_parse_input_set(uint64_t *inset,
7280                      enum i40e_filter_pctype pctype,
7281                      enum rte_eth_input_set_field *field,
7282                      uint16_t size)
7283 {
7284         uint16_t i, j;
7285         int ret = -EINVAL;
7286
7287         static const struct {
7288                 enum rte_eth_input_set_field field;
7289                 uint64_t inset;
7290         } inset_convert_table[] = {
7291                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7292                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7293                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7294                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7295                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7296                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7297                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7298                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7299                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7300                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7301                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7302                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7303                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7304                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7305                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7306                         I40E_INSET_IPV6_NEXT_HDR},
7307                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7308                         I40E_INSET_IPV6_HOP_LIMIT},
7309                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7310                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7311                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7312                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7313                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7314                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7315                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7316                         I40E_INSET_SCTP_VT},
7317                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7318                         I40E_INSET_TUNNEL_DMAC},
7319                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7320                         I40E_INSET_VLAN_TUNNEL},
7321                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7322                         I40E_INSET_TUNNEL_ID},
7323                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7324                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7325                         I40E_INSET_FLEX_PAYLOAD_W1},
7326                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7327                         I40E_INSET_FLEX_PAYLOAD_W2},
7328                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7329                         I40E_INSET_FLEX_PAYLOAD_W3},
7330                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7331                         I40E_INSET_FLEX_PAYLOAD_W4},
7332                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7333                         I40E_INSET_FLEX_PAYLOAD_W5},
7334                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7335                         I40E_INSET_FLEX_PAYLOAD_W6},
7336                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7337                         I40E_INSET_FLEX_PAYLOAD_W7},
7338                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7339                         I40E_INSET_FLEX_PAYLOAD_W8},
7340         };
7341
7342         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7343                 return ret;
7344
7345         /* Only one item allowed for default or all */
7346         if (size == 1) {
7347                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7348                         *inset = i40e_get_default_input_set(pctype);
7349                         return 0;
7350                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7351                         *inset = I40E_INSET_NONE;
7352                         return 0;
7353                 }
7354         }
7355
7356         for (i = 0, *inset = 0; i < size; i++) {
7357                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7358                         if (field[i] == inset_convert_table[j].field) {
7359                                 *inset |= inset_convert_table[j].inset;
7360                                 break;
7361                         }
7362                 }
7363
7364                 /* It contains unsupported input set, return immediately */
7365                 if (j == RTE_DIM(inset_convert_table))
7366                         return ret;
7367         }
7368
7369         return 0;
7370 }
7371
7372 /**
7373  * Translate the input set from bit masks to register aware bit masks
7374  * and vice versa
7375  */
7376 static uint64_t
7377 i40e_translate_input_set_reg(uint64_t input)
7378 {
7379         uint64_t val = 0;
7380         uint16_t i;
7381
7382         static const struct {
7383                 uint64_t inset;
7384                 uint64_t inset_reg;
7385         } inset_map[] = {
7386                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7387                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7388                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7389                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7390                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7391                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7392                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7393                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7394                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7395                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7396                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7397                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7398                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7399                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7400                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7401                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7402                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7403                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7404                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7405                 {I40E_INSET_TUNNEL_DMAC,
7406                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7407                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7408                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7409                 {I40E_INSET_TUNNEL_SRC_PORT,
7410                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7411                 {I40E_INSET_TUNNEL_DST_PORT,
7412                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7413                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7414                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7415                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7416                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7417                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7418                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7419                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7420                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7421                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7422         };
7423
7424         if (input == 0)
7425                 return val;
7426
7427         /* Translate input set to register aware inset */
7428         for (i = 0; i < RTE_DIM(inset_map); i++) {
7429                 if (input & inset_map[i].inset)
7430                         val |= inset_map[i].inset_reg;
7431         }
7432
7433         return val;
7434 }
7435
7436 static int
7437 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7438 {
7439         uint8_t i, idx = 0;
7440         uint64_t inset_need_mask = inset;
7441
7442         static const struct {
7443                 uint64_t inset;
7444                 uint32_t mask;
7445         } inset_mask_map[] = {
7446                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7447                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7448                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7449                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7450                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7451                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7452                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7453                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7454         };
7455
7456         if (!inset || !mask || !nb_elem)
7457                 return 0;
7458
7459         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7460                 /* Clear the inset bit, if no MASK is required,
7461                  * for example proto + ttl
7462                  */
7463                 if ((inset & inset_mask_map[i].inset) ==
7464                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7465                         inset_need_mask &= ~inset_mask_map[i].inset;
7466                 if (!inset_need_mask)
7467                         return 0;
7468         }
7469         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7470                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7471                     inset_mask_map[i].inset) {
7472                         if (idx >= nb_elem) {
7473                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7474                                 return -EINVAL;
7475                         }
7476                         mask[idx] = inset_mask_map[i].mask;
7477                         idx++;
7478                 }
7479         }
7480
7481         return idx;
7482 }
7483
7484 static void
7485 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7486 {
7487         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7488
7489         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7490         if (reg != val)
7491                 i40e_write_rx_ctl(hw, addr, val);
7492         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7493                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7494 }
7495
7496 static void
7497 i40e_filter_input_set_init(struct i40e_pf *pf)
7498 {
7499         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7500         enum i40e_filter_pctype pctype;
7501         uint64_t input_set, inset_reg;
7502         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7503         int num, i;
7504
7505         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7506              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7507                 if (!I40E_VALID_PCTYPE(pctype))
7508                         continue;
7509                 input_set = i40e_get_default_input_set(pctype);
7510
7511                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7512                                                    I40E_INSET_MASK_NUM_REG);
7513                 if (num < 0)
7514                         return;
7515                 inset_reg = i40e_translate_input_set_reg(input_set);
7516
7517                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7518                                       (uint32_t)(inset_reg & UINT32_MAX));
7519                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7520                                      (uint32_t)((inset_reg >>
7521                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7522                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7523                                       (uint32_t)(inset_reg & UINT32_MAX));
7524                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7525                                      (uint32_t)((inset_reg >>
7526                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7527
7528                 for (i = 0; i < num; i++) {
7529                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7530                                              mask_reg[i]);
7531                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7532                                              mask_reg[i]);
7533                 }
7534                 /*clear unused mask registers of the pctype */
7535                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7536                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7537                                              0);
7538                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7539                                              0);
7540                 }
7541                 I40E_WRITE_FLUSH(hw);
7542
7543                 /* store the default input set */
7544                 pf->hash_input_set[pctype] = input_set;
7545                 pf->fdir.input_set[pctype] = input_set;
7546         }
7547 }
7548
7549 int
7550 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7551                          struct rte_eth_input_set_conf *conf)
7552 {
7553         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7554         enum i40e_filter_pctype pctype;
7555         uint64_t input_set, inset_reg = 0;
7556         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7557         int ret, i, num;
7558
7559         if (!conf) {
7560                 PMD_DRV_LOG(ERR, "Invalid pointer");
7561                 return -EFAULT;
7562         }
7563         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7564             conf->op != RTE_ETH_INPUT_SET_ADD) {
7565                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7566                 return -EINVAL;
7567         }
7568
7569         if (!I40E_VALID_FLOW(conf->flow_type)) {
7570                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7571                 return -EINVAL;
7572         }
7573         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7574         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7575                                    conf->inset_size);
7576         if (ret) {
7577                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7578                 return -EINVAL;
7579         }
7580         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7581                                     input_set) != 0) {
7582                 PMD_DRV_LOG(ERR, "Invalid input set");
7583                 return -EINVAL;
7584         }
7585         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7586                 /* get inset value in register */
7587                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7588                 inset_reg <<= I40E_32_BIT_WIDTH;
7589                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7590                 input_set |= pf->hash_input_set[pctype];
7591         }
7592         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7593                                            I40E_INSET_MASK_NUM_REG);
7594         if (num < 0)
7595                 return -EINVAL;
7596
7597         inset_reg |= i40e_translate_input_set_reg(input_set);
7598
7599         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7600                               (uint32_t)(inset_reg & UINT32_MAX));
7601         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7602                              (uint32_t)((inset_reg >>
7603                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7604
7605         for (i = 0; i < num; i++)
7606                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7607                                      mask_reg[i]);
7608         /*clear unused mask registers of the pctype */
7609         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7610                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7611                                      0);
7612         I40E_WRITE_FLUSH(hw);
7613
7614         pf->hash_input_set[pctype] = input_set;
7615         return 0;
7616 }
7617
7618 int
7619 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7620                          struct rte_eth_input_set_conf *conf)
7621 {
7622         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7623         enum i40e_filter_pctype pctype;
7624         uint64_t input_set, inset_reg = 0;
7625         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7626         int ret, i, num;
7627
7628         if (!hw || !conf) {
7629                 PMD_DRV_LOG(ERR, "Invalid pointer");
7630                 return -EFAULT;
7631         }
7632         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7633             conf->op != RTE_ETH_INPUT_SET_ADD) {
7634                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7635                 return -EINVAL;
7636         }
7637
7638         if (!I40E_VALID_FLOW(conf->flow_type)) {
7639                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7640                 return -EINVAL;
7641         }
7642         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7643         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7644                                    conf->inset_size);
7645         if (ret) {
7646                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7647                 return -EINVAL;
7648         }
7649         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7650                                     input_set) != 0) {
7651                 PMD_DRV_LOG(ERR, "Invalid input set");
7652                 return -EINVAL;
7653         }
7654
7655         /* get inset value in register */
7656         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7657         inset_reg <<= I40E_32_BIT_WIDTH;
7658         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7659
7660         /* Can not change the inset reg for flex payload for fdir,
7661          * it is done by writing I40E_PRTQF_FD_FLXINSET
7662          * in i40e_set_flex_mask_on_pctype.
7663          */
7664         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7665                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7666         else
7667                 input_set |= pf->fdir.input_set[pctype];
7668         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7669                                            I40E_INSET_MASK_NUM_REG);
7670         if (num < 0)
7671                 return -EINVAL;
7672
7673         inset_reg |= i40e_translate_input_set_reg(input_set);
7674
7675         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7676                               (uint32_t)(inset_reg & UINT32_MAX));
7677         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7678                              (uint32_t)((inset_reg >>
7679                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7680
7681         for (i = 0; i < num; i++)
7682                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7683                                      mask_reg[i]);
7684         /*clear unused mask registers of the pctype */
7685         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7686                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7687                                      0);
7688         I40E_WRITE_FLUSH(hw);
7689
7690         pf->fdir.input_set[pctype] = input_set;
7691         return 0;
7692 }
7693
7694 static int
7695 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7696 {
7697         int ret = 0;
7698
7699         if (!hw || !info) {
7700                 PMD_DRV_LOG(ERR, "Invalid pointer");
7701                 return -EFAULT;
7702         }
7703
7704         switch (info->info_type) {
7705         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7706                 i40e_get_symmetric_hash_enable_per_port(hw,
7707                                         &(info->info.enable));
7708                 break;
7709         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7710                 ret = i40e_get_hash_filter_global_config(hw,
7711                                 &(info->info.global_conf));
7712                 break;
7713         default:
7714                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7715                                                         info->info_type);
7716                 ret = -EINVAL;
7717                 break;
7718         }
7719
7720         return ret;
7721 }
7722
7723 static int
7724 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7725 {
7726         int ret = 0;
7727
7728         if (!hw || !info) {
7729                 PMD_DRV_LOG(ERR, "Invalid pointer");
7730                 return -EFAULT;
7731         }
7732
7733         switch (info->info_type) {
7734         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7735                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7736                 break;
7737         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7738                 ret = i40e_set_hash_filter_global_config(hw,
7739                                 &(info->info.global_conf));
7740                 break;
7741         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7742                 ret = i40e_hash_filter_inset_select(hw,
7743                                                &(info->info.input_set_conf));
7744                 break;
7745
7746         default:
7747                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7748                                                         info->info_type);
7749                 ret = -EINVAL;
7750                 break;
7751         }
7752
7753         return ret;
7754 }
7755
7756 /* Operations for hash function */
7757 static int
7758 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7759                       enum rte_filter_op filter_op,
7760                       void *arg)
7761 {
7762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7763         int ret = 0;
7764
7765         switch (filter_op) {
7766         case RTE_ETH_FILTER_NOP:
7767                 break;
7768         case RTE_ETH_FILTER_GET:
7769                 ret = i40e_hash_filter_get(hw,
7770                         (struct rte_eth_hash_filter_info *)arg);
7771                 break;
7772         case RTE_ETH_FILTER_SET:
7773                 ret = i40e_hash_filter_set(hw,
7774                         (struct rte_eth_hash_filter_info *)arg);
7775                 break;
7776         default:
7777                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7778                                                                 filter_op);
7779                 ret = -ENOTSUP;
7780                 break;
7781         }
7782
7783         return ret;
7784 }
7785
7786 /*
7787  * Configure ethertype filter, which can director packet by filtering
7788  * with mac address and ether_type or only ether_type
7789  */
7790 static int
7791 i40e_ethertype_filter_set(struct i40e_pf *pf,
7792                         struct rte_eth_ethertype_filter *filter,
7793                         bool add)
7794 {
7795         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7796         struct i40e_control_filter_stats stats;
7797         uint16_t flags = 0;
7798         int ret;
7799
7800         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7801                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7802                 return -EINVAL;
7803         }
7804         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7805                 filter->ether_type == ETHER_TYPE_IPv6) {
7806                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7807                         " control packet filter.", filter->ether_type);
7808                 return -EINVAL;
7809         }
7810         if (filter->ether_type == ETHER_TYPE_VLAN)
7811                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7812                         " not supported.");
7813
7814         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7815                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7816         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7817                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7818         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7819
7820         memset(&stats, 0, sizeof(stats));
7821         ret = i40e_aq_add_rem_control_packet_filter(hw,
7822                         filter->mac_addr.addr_bytes,
7823                         filter->ether_type, flags,
7824                         pf->main_vsi->seid,
7825                         filter->queue, add, &stats, NULL);
7826
7827         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7828                          " mac_etype_used = %u, etype_used = %u,"
7829                          " mac_etype_free = %u, etype_free = %u\n",
7830                          ret, stats.mac_etype_used, stats.etype_used,
7831                          stats.mac_etype_free, stats.etype_free);
7832         if (ret < 0)
7833                 return -ENOSYS;
7834         return 0;
7835 }
7836
7837 /*
7838  * Handle operations for ethertype filter.
7839  */
7840 static int
7841 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7842                                 enum rte_filter_op filter_op,
7843                                 void *arg)
7844 {
7845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7846         int ret = 0;
7847
7848         if (filter_op == RTE_ETH_FILTER_NOP)
7849                 return ret;
7850
7851         if (arg == NULL) {
7852                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7853                             filter_op);
7854                 return -EINVAL;
7855         }
7856
7857         switch (filter_op) {
7858         case RTE_ETH_FILTER_ADD:
7859                 ret = i40e_ethertype_filter_set(pf,
7860                         (struct rte_eth_ethertype_filter *)arg,
7861                         TRUE);
7862                 break;
7863         case RTE_ETH_FILTER_DELETE:
7864                 ret = i40e_ethertype_filter_set(pf,
7865                         (struct rte_eth_ethertype_filter *)arg,
7866                         FALSE);
7867                 break;
7868         default:
7869                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7870                 ret = -ENOSYS;
7871                 break;
7872         }
7873         return ret;
7874 }
7875
7876 static int
7877 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7878                      enum rte_filter_type filter_type,
7879                      enum rte_filter_op filter_op,
7880                      void *arg)
7881 {
7882         int ret = 0;
7883
7884         if (dev == NULL)
7885                 return -EINVAL;
7886
7887         switch (filter_type) {
7888         case RTE_ETH_FILTER_NONE:
7889                 /* For global configuration */
7890                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7891                 break;
7892         case RTE_ETH_FILTER_HASH:
7893                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7894                 break;
7895         case RTE_ETH_FILTER_MACVLAN:
7896                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7897                 break;
7898         case RTE_ETH_FILTER_ETHERTYPE:
7899                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7900                 break;
7901         case RTE_ETH_FILTER_TUNNEL:
7902                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7903                 break;
7904         case RTE_ETH_FILTER_FDIR:
7905                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7906                 break;
7907         default:
7908                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7909                                                         filter_type);
7910                 ret = -EINVAL;
7911                 break;
7912         }
7913
7914         return ret;
7915 }
7916
7917 /*
7918  * Check and enable Extended Tag.
7919  * Enabling Extended Tag is important for 40G performance.
7920  */
7921 static void
7922 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7923 {
7924         uint32_t buf = 0;
7925         int ret;
7926
7927         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7928                                       PCI_DEV_CAP_REG);
7929         if (ret < 0) {
7930                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7931                             PCI_DEV_CAP_REG);
7932                 return;
7933         }
7934         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7935                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7936                 return;
7937         }
7938
7939         buf = 0;
7940         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7941                                       PCI_DEV_CTRL_REG);
7942         if (ret < 0) {
7943                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7944                             PCI_DEV_CTRL_REG);
7945                 return;
7946         }
7947         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7948                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7949                 return;
7950         }
7951         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7952         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7953                                        PCI_DEV_CTRL_REG);
7954         if (ret < 0) {
7955                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7956                             PCI_DEV_CTRL_REG);
7957                 return;
7958         }
7959 }
7960
7961 /*
7962  * As some registers wouldn't be reset unless a global hardware reset,
7963  * hardware initialization is needed to put those registers into an
7964  * expected initial state.
7965  */
7966 static void
7967 i40e_hw_init(struct rte_eth_dev *dev)
7968 {
7969         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7970
7971         i40e_enable_extended_tag(dev);
7972
7973         /* clear the PF Queue Filter control register */
7974         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7975
7976         /* Disable symmetric hash per port */
7977         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7978 }
7979
7980 enum i40e_filter_pctype
7981 i40e_flowtype_to_pctype(uint16_t flow_type)
7982 {
7983         static const enum i40e_filter_pctype pctype_table[] = {
7984                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7985                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7986                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7987                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7988                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7989                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7990                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7991                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7992                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7993                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7994                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7995                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7996                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7997                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7998                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7999                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8000                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8001                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8002                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8003         };
8004
8005         return pctype_table[flow_type];
8006 }
8007
8008 uint16_t
8009 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8010 {
8011         static const uint16_t flowtype_table[] = {
8012                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8013                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8014                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8015                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8016                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8017                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8018                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8019                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8020                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8021                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8022                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8023                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8024                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8025                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8026                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8027                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8028                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8029                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8030                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8031         };
8032
8033         return flowtype_table[pctype];
8034 }
8035
8036 /*
8037  * On X710, performance number is far from the expectation on recent firmware
8038  * versions; on XL710, performance number is also far from the expectation on
8039  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8040  * mode is enabled and port MAC address is equal to the packet destination MAC
8041  * address. The fix for this issue may not be integrated in the following
8042  * firmware version. So the workaround in software driver is needed. It needs
8043  * to modify the initial values of 3 internal only registers for both X710 and
8044  * XL710. Note that the values for X710 or XL710 could be different, and the
8045  * workaround can be removed when it is fixed in firmware in the future.
8046  */
8047
8048 /* For both X710 and XL710 */
8049 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8050 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8051
8052 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8053 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8054
8055 /* For X710 */
8056 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8057 /* For XL710 */
8058 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8059 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8060
8061 static void
8062 i40e_configure_registers(struct i40e_hw *hw)
8063 {
8064         static struct {
8065                 uint32_t addr;
8066                 uint64_t val;
8067         } reg_table[] = {
8068                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8069                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8070                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8071         };
8072         uint64_t reg;
8073         uint32_t i;
8074         int ret;
8075
8076         for (i = 0; i < RTE_DIM(reg_table); i++) {
8077                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8078                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8079                                 reg_table[i].val =
8080                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8081                         else /* For X710 */
8082                                 reg_table[i].val =
8083                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8084                 }
8085
8086                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8087                                                         &reg, NULL);
8088                 if (ret < 0) {
8089                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8090                                                         reg_table[i].addr);
8091                         break;
8092                 }
8093                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8094                                                 reg_table[i].addr, reg);
8095                 if (reg == reg_table[i].val)
8096                         continue;
8097
8098                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8099                                                 reg_table[i].val, NULL);
8100                 if (ret < 0) {
8101                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8102                                 "address of 0x%"PRIx32, reg_table[i].val,
8103                                                         reg_table[i].addr);
8104                         break;
8105                 }
8106                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8107                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8108         }
8109 }
8110
8111 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8112 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8113 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8114 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8115 static int
8116 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8117 {
8118         uint32_t reg;
8119         int ret;
8120
8121         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8122                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8123                 return -EINVAL;
8124         }
8125
8126         /* Configure for double VLAN RX stripping */
8127         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8128         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8129                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8130                 ret = i40e_aq_debug_write_register(hw,
8131                                                    I40E_VSI_TSR(vsi->vsi_id),
8132                                                    reg, NULL);
8133                 if (ret < 0) {
8134                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8135                                     vsi->vsi_id);
8136                         return I40E_ERR_CONFIG;
8137                 }
8138         }
8139
8140         /* Configure for double VLAN TX insertion */
8141         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8142         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8143                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8144                 ret = i40e_aq_debug_write_register(hw,
8145                                                    I40E_VSI_L2TAGSTXVALID(
8146                                                    vsi->vsi_id), reg, NULL);
8147                 if (ret < 0) {
8148                         PMD_DRV_LOG(ERR, "Failed to update "
8149                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8150                         return I40E_ERR_CONFIG;
8151                 }
8152         }
8153
8154         return 0;
8155 }
8156
8157 /**
8158  * i40e_aq_add_mirror_rule
8159  * @hw: pointer to the hardware structure
8160  * @seid: VEB seid to add mirror rule to
8161  * @dst_id: destination vsi seid
8162  * @entries: Buffer which contains the entities to be mirrored
8163  * @count: number of entities contained in the buffer
8164  * @rule_id:the rule_id of the rule to be added
8165  *
8166  * Add a mirror rule for a given veb.
8167  *
8168  **/
8169 static enum i40e_status_code
8170 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8171                         uint16_t seid, uint16_t dst_id,
8172                         uint16_t rule_type, uint16_t *entries,
8173                         uint16_t count, uint16_t *rule_id)
8174 {
8175         struct i40e_aq_desc desc;
8176         struct i40e_aqc_add_delete_mirror_rule cmd;
8177         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8178                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8179                 &desc.params.raw;
8180         uint16_t buff_len;
8181         enum i40e_status_code status;
8182
8183         i40e_fill_default_direct_cmd_desc(&desc,
8184                                           i40e_aqc_opc_add_mirror_rule);
8185         memset(&cmd, 0, sizeof(cmd));
8186
8187         buff_len = sizeof(uint16_t) * count;
8188         desc.datalen = rte_cpu_to_le_16(buff_len);
8189         if (buff_len > 0)
8190                 desc.flags |= rte_cpu_to_le_16(
8191                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8192         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8193                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8194         cmd.num_entries = rte_cpu_to_le_16(count);
8195         cmd.seid = rte_cpu_to_le_16(seid);
8196         cmd.destination = rte_cpu_to_le_16(dst_id);
8197
8198         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8199         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8200         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8201                          "rule_id = %u"
8202                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8203                          hw->aq.asq_last_status, resp->rule_id,
8204                          resp->mirror_rules_used, resp->mirror_rules_free);
8205         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8206
8207         return status;
8208 }
8209
8210 /**
8211  * i40e_aq_del_mirror_rule
8212  * @hw: pointer to the hardware structure
8213  * @seid: VEB seid to add mirror rule to
8214  * @entries: Buffer which contains the entities to be mirrored
8215  * @count: number of entities contained in the buffer
8216  * @rule_id:the rule_id of the rule to be delete
8217  *
8218  * Delete a mirror rule for a given veb.
8219  *
8220  **/
8221 static enum i40e_status_code
8222 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8223                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8224                 uint16_t count, uint16_t rule_id)
8225 {
8226         struct i40e_aq_desc desc;
8227         struct i40e_aqc_add_delete_mirror_rule cmd;
8228         uint16_t buff_len = 0;
8229         enum i40e_status_code status;
8230         void *buff = NULL;
8231
8232         i40e_fill_default_direct_cmd_desc(&desc,
8233                                           i40e_aqc_opc_delete_mirror_rule);
8234         memset(&cmd, 0, sizeof(cmd));
8235         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8236                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8237                                                           I40E_AQ_FLAG_RD));
8238                 cmd.num_entries = count;
8239                 buff_len = sizeof(uint16_t) * count;
8240                 desc.datalen = rte_cpu_to_le_16(buff_len);
8241                 buff = (void *)entries;
8242         } else
8243                 /* rule id is filled in destination field for deleting mirror rule */
8244                 cmd.destination = rte_cpu_to_le_16(rule_id);
8245
8246         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8247                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8248         cmd.seid = rte_cpu_to_le_16(seid);
8249
8250         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8251         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8252
8253         return status;
8254 }
8255
8256 /**
8257  * i40e_mirror_rule_set
8258  * @dev: pointer to the hardware structure
8259  * @mirror_conf: mirror rule info
8260  * @sw_id: mirror rule's sw_id
8261  * @on: enable/disable
8262  *
8263  * set a mirror rule.
8264  *
8265  **/
8266 static int
8267 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8268                         struct rte_eth_mirror_conf *mirror_conf,
8269                         uint8_t sw_id, uint8_t on)
8270 {
8271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8272         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8273         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8274         struct i40e_mirror_rule *parent = NULL;
8275         uint16_t seid, dst_seid, rule_id;
8276         uint16_t i, j = 0;
8277         int ret;
8278
8279         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8280
8281         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8282                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8283                         " without veb or vfs.");
8284                 return -ENOSYS;
8285         }
8286         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8287                 PMD_DRV_LOG(ERR, "mirror table is full.");
8288                 return -ENOSPC;
8289         }
8290         if (mirror_conf->dst_pool > pf->vf_num) {
8291                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8292                                  mirror_conf->dst_pool);
8293                 return -EINVAL;
8294         }
8295
8296         seid = pf->main_vsi->veb->seid;
8297
8298         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8299                 if (sw_id <= it->index) {
8300                         mirr_rule = it;
8301                         break;
8302                 }
8303                 parent = it;
8304         }
8305         if (mirr_rule && sw_id == mirr_rule->index) {
8306                 if (on) {
8307                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8308                         return -EEXIST;
8309                 } else {
8310                         ret = i40e_aq_del_mirror_rule(hw, seid,
8311                                         mirr_rule->rule_type,
8312                                         mirr_rule->entries,
8313                                         mirr_rule->num_entries, mirr_rule->id);
8314                         if (ret < 0) {
8315                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8316                                                    " ret = %d, aq_err = %d.",
8317                                                    ret, hw->aq.asq_last_status);
8318                                 return -ENOSYS;
8319                         }
8320                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8321                         rte_free(mirr_rule);
8322                         pf->nb_mirror_rule--;
8323                         return 0;
8324                 }
8325         } else if (!on) {
8326                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8327                 return -ENOENT;
8328         }
8329
8330         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8331                                 sizeof(struct i40e_mirror_rule) , 0);
8332         if (!mirr_rule) {
8333                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8334                 return I40E_ERR_NO_MEMORY;
8335         }
8336         switch (mirror_conf->rule_type) {
8337         case ETH_MIRROR_VLAN:
8338                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8339                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8340                                 mirr_rule->entries[j] =
8341                                         mirror_conf->vlan.vlan_id[i];
8342                                 j++;
8343                         }
8344                 }
8345                 if (j == 0) {
8346                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8347                         rte_free(mirr_rule);
8348                         return -EINVAL;
8349                 }
8350                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8351                 break;
8352         case ETH_MIRROR_VIRTUAL_POOL_UP:
8353         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8354                 /* check if the specified pool bit is out of range */
8355                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8356                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8357                         rte_free(mirr_rule);
8358                         return -EINVAL;
8359                 }
8360                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8361                         if (mirror_conf->pool_mask & (1ULL << i)) {
8362                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8363                                 j++;
8364                         }
8365                 }
8366                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8367                         /* add pf vsi to entries */
8368                         mirr_rule->entries[j] = pf->main_vsi_seid;
8369                         j++;
8370                 }
8371                 if (j == 0) {
8372                         PMD_DRV_LOG(ERR, "pool is not specified.");
8373                         rte_free(mirr_rule);
8374                         return -EINVAL;
8375                 }
8376                 /* egress and ingress in aq commands means from switch but not port */
8377                 mirr_rule->rule_type =
8378                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8379                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8380                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8381                 break;
8382         case ETH_MIRROR_UPLINK_PORT:
8383                 /* egress and ingress in aq commands means from switch but not port*/
8384                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8385                 break;
8386         case ETH_MIRROR_DOWNLINK_PORT:
8387                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8388                 break;
8389         default:
8390                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8391                         mirror_conf->rule_type);
8392                 rte_free(mirr_rule);
8393                 return -EINVAL;
8394         }
8395
8396         /* If the dst_pool is equal to vf_num, consider it as PF */
8397         if (mirror_conf->dst_pool == pf->vf_num)
8398                 dst_seid = pf->main_vsi_seid;
8399         else
8400                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8401
8402         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8403                                       mirr_rule->rule_type, mirr_rule->entries,
8404                                       j, &rule_id);
8405         if (ret < 0) {
8406                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8407                                    " ret = %d, aq_err = %d.",
8408                                    ret, hw->aq.asq_last_status);
8409                 rte_free(mirr_rule);
8410                 return -ENOSYS;
8411         }
8412
8413         mirr_rule->index = sw_id;
8414         mirr_rule->num_entries = j;
8415         mirr_rule->id = rule_id;
8416         mirr_rule->dst_vsi_seid = dst_seid;
8417
8418         if (parent)
8419                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8420         else
8421                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8422
8423         pf->nb_mirror_rule++;
8424         return 0;
8425 }
8426
8427 /**
8428  * i40e_mirror_rule_reset
8429  * @dev: pointer to the device
8430  * @sw_id: mirror rule's sw_id
8431  *
8432  * reset a mirror rule.
8433  *
8434  **/
8435 static int
8436 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8437 {
8438         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8439         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8440         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8441         uint16_t seid;
8442         int ret;
8443
8444         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8445
8446         seid = pf->main_vsi->veb->seid;
8447
8448         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8449                 if (sw_id == it->index) {
8450                         mirr_rule = it;
8451                         break;
8452                 }
8453         }
8454         if (mirr_rule) {
8455                 ret = i40e_aq_del_mirror_rule(hw, seid,
8456                                 mirr_rule->rule_type,
8457                                 mirr_rule->entries,
8458                                 mirr_rule->num_entries, mirr_rule->id);
8459                 if (ret < 0) {
8460                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8461                                            " status = %d, aq_err = %d.",
8462                                            ret, hw->aq.asq_last_status);
8463                         return -ENOSYS;
8464                 }
8465                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8466                 rte_free(mirr_rule);
8467                 pf->nb_mirror_rule--;
8468         } else {
8469                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8470                 return -ENOENT;
8471         }
8472         return 0;
8473 }
8474
8475 static uint64_t
8476 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8477 {
8478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8479         uint64_t systim_cycles;
8480
8481         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8482         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8483                         << 32;
8484
8485         return systim_cycles;
8486 }
8487
8488 static uint64_t
8489 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8490 {
8491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8492         uint64_t rx_tstamp;
8493
8494         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8495         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8496                         << 32;
8497
8498         return rx_tstamp;
8499 }
8500
8501 static uint64_t
8502 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8503 {
8504         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8505         uint64_t tx_tstamp;
8506
8507         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8508         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8509                         << 32;
8510
8511         return tx_tstamp;
8512 }
8513
8514 static void
8515 i40e_start_timecounters(struct rte_eth_dev *dev)
8516 {
8517         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8518         struct i40e_adapter *adapter =
8519                         (struct i40e_adapter *)dev->data->dev_private;
8520         struct rte_eth_link link;
8521         uint32_t tsync_inc_l;
8522         uint32_t tsync_inc_h;
8523
8524         /* Get current link speed. */
8525         memset(&link, 0, sizeof(link));
8526         i40e_dev_link_update(dev, 1);
8527         rte_i40e_dev_atomic_read_link_status(dev, &link);
8528
8529         switch (link.link_speed) {
8530         case ETH_SPEED_NUM_40G:
8531                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8532                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8533                 break;
8534         case ETH_SPEED_NUM_10G:
8535                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8536                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8537                 break;
8538         case ETH_SPEED_NUM_1G:
8539                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8540                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8541                 break;
8542         default:
8543                 tsync_inc_l = 0x0;
8544                 tsync_inc_h = 0x0;
8545         }
8546
8547         /* Set the timesync increment value. */
8548         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8549         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8550
8551         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8552         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8553         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8554
8555         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8556         adapter->systime_tc.cc_shift = 0;
8557         adapter->systime_tc.nsec_mask = 0;
8558
8559         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8560         adapter->rx_tstamp_tc.cc_shift = 0;
8561         adapter->rx_tstamp_tc.nsec_mask = 0;
8562
8563         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8564         adapter->tx_tstamp_tc.cc_shift = 0;
8565         adapter->tx_tstamp_tc.nsec_mask = 0;
8566 }
8567
8568 static int
8569 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8570 {
8571         struct i40e_adapter *adapter =
8572                         (struct i40e_adapter *)dev->data->dev_private;
8573
8574         adapter->systime_tc.nsec += delta;
8575         adapter->rx_tstamp_tc.nsec += delta;
8576         adapter->tx_tstamp_tc.nsec += delta;
8577
8578         return 0;
8579 }
8580
8581 static int
8582 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8583 {
8584         uint64_t ns;
8585         struct i40e_adapter *adapter =
8586                         (struct i40e_adapter *)dev->data->dev_private;
8587
8588         ns = rte_timespec_to_ns(ts);
8589
8590         /* Set the timecounters to a new value. */
8591         adapter->systime_tc.nsec = ns;
8592         adapter->rx_tstamp_tc.nsec = ns;
8593         adapter->tx_tstamp_tc.nsec = ns;
8594
8595         return 0;
8596 }
8597
8598 static int
8599 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8600 {
8601         uint64_t ns, systime_cycles;
8602         struct i40e_adapter *adapter =
8603                         (struct i40e_adapter *)dev->data->dev_private;
8604
8605         systime_cycles = i40e_read_systime_cyclecounter(dev);
8606         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8607         *ts = rte_ns_to_timespec(ns);
8608
8609         return 0;
8610 }
8611
8612 static int
8613 i40e_timesync_enable(struct rte_eth_dev *dev)
8614 {
8615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8616         uint32_t tsync_ctl_l;
8617         uint32_t tsync_ctl_h;
8618
8619         /* Stop the timesync system time. */
8620         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8621         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8622         /* Reset the timesync system time value. */
8623         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8624         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8625
8626         i40e_start_timecounters(dev);
8627
8628         /* Clear timesync registers. */
8629         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8630         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8631         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8632         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8633         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8634         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8635
8636         /* Enable timestamping of PTP packets. */
8637         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8638         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8639
8640         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8641         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8642         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8643
8644         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8645         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8646
8647         return 0;
8648 }
8649
8650 static int
8651 i40e_timesync_disable(struct rte_eth_dev *dev)
8652 {
8653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8654         uint32_t tsync_ctl_l;
8655         uint32_t tsync_ctl_h;
8656
8657         /* Disable timestamping of transmitted PTP packets. */
8658         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8659         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8660
8661         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8662         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8663
8664         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8665         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8666
8667         /* Reset the timesync increment value. */
8668         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8669         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8670
8671         return 0;
8672 }
8673
8674 static int
8675 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8676                                 struct timespec *timestamp, uint32_t flags)
8677 {
8678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8679         struct i40e_adapter *adapter =
8680                 (struct i40e_adapter *)dev->data->dev_private;
8681
8682         uint32_t sync_status;
8683         uint32_t index = flags & 0x03;
8684         uint64_t rx_tstamp_cycles;
8685         uint64_t ns;
8686
8687         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8688         if ((sync_status & (1 << index)) == 0)
8689                 return -EINVAL;
8690
8691         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8692         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8693         *timestamp = rte_ns_to_timespec(ns);
8694
8695         return 0;
8696 }
8697
8698 static int
8699 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8700                                 struct timespec *timestamp)
8701 {
8702         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8703         struct i40e_adapter *adapter =
8704                 (struct i40e_adapter *)dev->data->dev_private;
8705
8706         uint32_t sync_status;
8707         uint64_t tx_tstamp_cycles;
8708         uint64_t ns;
8709
8710         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8711         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8712                 return -EINVAL;
8713
8714         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8715         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8716         *timestamp = rte_ns_to_timespec(ns);
8717
8718         return 0;
8719 }
8720
8721 /*
8722  * i40e_parse_dcb_configure - parse dcb configure from user
8723  * @dev: the device being configured
8724  * @dcb_cfg: pointer of the result of parse
8725  * @*tc_map: bit map of enabled traffic classes
8726  *
8727  * Returns 0 on success, negative value on failure
8728  */
8729 static int
8730 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8731                          struct i40e_dcbx_config *dcb_cfg,
8732                          uint8_t *tc_map)
8733 {
8734         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8735         uint8_t i, tc_bw, bw_lf;
8736
8737         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8738
8739         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8740         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8741                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8742                 return -EINVAL;
8743         }
8744
8745         /* assume each tc has the same bw */
8746         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8747         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8748                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8749         /* to ensure the sum of tcbw is equal to 100 */
8750         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8751         for (i = 0; i < bw_lf; i++)
8752                 dcb_cfg->etscfg.tcbwtable[i]++;
8753
8754         /* assume each tc has the same Transmission Selection Algorithm */
8755         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8756                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8757
8758         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8759                 dcb_cfg->etscfg.prioritytable[i] =
8760                                 dcb_rx_conf->dcb_tc[i];
8761
8762         /* FW needs one App to configure HW */
8763         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8764         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8765         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8766         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8767
8768         if (dcb_rx_conf->nb_tcs == 0)
8769                 *tc_map = 1; /* tc0 only */
8770         else
8771                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8772
8773         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8774                 dcb_cfg->pfc.willing = 0;
8775                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8776                 dcb_cfg->pfc.pfcenable = *tc_map;
8777         }
8778         return 0;
8779 }
8780
8781
8782 static enum i40e_status_code
8783 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8784                               struct i40e_aqc_vsi_properties_data *info,
8785                               uint8_t enabled_tcmap)
8786 {
8787         enum i40e_status_code ret;
8788         int i, total_tc = 0;
8789         uint16_t qpnum_per_tc, bsf, qp_idx;
8790         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8791         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8792         uint16_t used_queues;
8793
8794         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8795         if (ret != I40E_SUCCESS)
8796                 return ret;
8797
8798         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8799                 if (enabled_tcmap & (1 << i))
8800                         total_tc++;
8801         }
8802         if (total_tc == 0)
8803                 total_tc = 1;
8804         vsi->enabled_tc = enabled_tcmap;
8805
8806         /* different VSI has different queues assigned */
8807         if (vsi->type == I40E_VSI_MAIN)
8808                 used_queues = dev_data->nb_rx_queues -
8809                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8810         else if (vsi->type == I40E_VSI_VMDQ2)
8811                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8812         else {
8813                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8814                 return I40E_ERR_NO_AVAILABLE_VSI;
8815         }
8816
8817         qpnum_per_tc = used_queues / total_tc;
8818         /* Number of queues per enabled TC */
8819         if (qpnum_per_tc == 0) {
8820                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8821                 return I40E_ERR_INVALID_QP_ID;
8822         }
8823         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8824                                 I40E_MAX_Q_PER_TC);
8825         bsf = rte_bsf32(qpnum_per_tc);
8826
8827         /**
8828          * Configure TC and queue mapping parameters, for enabled TC,
8829          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8830          * default queue will serve it.
8831          */
8832         qp_idx = 0;
8833         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8834                 if (vsi->enabled_tc & (1 << i)) {
8835                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8836                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8837                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8838                         qp_idx += qpnum_per_tc;
8839                 } else
8840                         info->tc_mapping[i] = 0;
8841         }
8842
8843         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8844         if (vsi->type == I40E_VSI_SRIOV) {
8845                 info->mapping_flags |=
8846                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8847                 for (i = 0; i < vsi->nb_qps; i++)
8848                         info->queue_mapping[i] =
8849                                 rte_cpu_to_le_16(vsi->base_queue + i);
8850         } else {
8851                 info->mapping_flags |=
8852                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8853                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8854         }
8855         info->valid_sections |=
8856                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8857
8858         return I40E_SUCCESS;
8859 }
8860
8861 /*
8862  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8863  * @veb: VEB to be configured
8864  * @tc_map: enabled TC bitmap
8865  *
8866  * Returns 0 on success, negative value on failure
8867  */
8868 static enum i40e_status_code
8869 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8870 {
8871         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8872         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8873         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8874         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8875         enum i40e_status_code ret = I40E_SUCCESS;
8876         int i;
8877         uint32_t bw_max;
8878
8879         /* Check if enabled_tc is same as existing or new TCs */
8880         if (veb->enabled_tc == tc_map)
8881                 return ret;
8882
8883         /* configure tc bandwidth */
8884         memset(&veb_bw, 0, sizeof(veb_bw));
8885         veb_bw.tc_valid_bits = tc_map;
8886         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8887         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8888                 if (tc_map & BIT_ULL(i))
8889                         veb_bw.tc_bw_share_credits[i] = 1;
8890         }
8891         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8892                                                    &veb_bw, NULL);
8893         if (ret) {
8894                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8895                                   " per TC failed = %d",
8896                                   hw->aq.asq_last_status);
8897                 return ret;
8898         }
8899
8900         memset(&ets_query, 0, sizeof(ets_query));
8901         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8902                                                    &ets_query, NULL);
8903         if (ret != I40E_SUCCESS) {
8904                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8905                                  " configuration %u", hw->aq.asq_last_status);
8906                 return ret;
8907         }
8908         memset(&bw_query, 0, sizeof(bw_query));
8909         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8910                                                   &bw_query, NULL);
8911         if (ret != I40E_SUCCESS) {
8912                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8913                                  " configuration %u", hw->aq.asq_last_status);
8914                 return ret;
8915         }
8916
8917         /* store and print out BW info */
8918         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8919         veb->bw_info.bw_max = ets_query.tc_bw_max;
8920         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8921         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8922         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8923                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8924                      I40E_16_BIT_WIDTH);
8925         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8926                 veb->bw_info.bw_ets_share_credits[i] =
8927                                 bw_query.tc_bw_share_credits[i];
8928                 veb->bw_info.bw_ets_credits[i] =
8929                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8930                 /* 4 bits per TC, 4th bit is reserved */
8931                 veb->bw_info.bw_ets_max[i] =
8932                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8933                                   RTE_LEN2MASK(3, uint8_t));
8934                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8935                             veb->bw_info.bw_ets_share_credits[i]);
8936                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8937                             veb->bw_info.bw_ets_credits[i]);
8938                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8939                             veb->bw_info.bw_ets_max[i]);
8940         }
8941
8942         veb->enabled_tc = tc_map;
8943
8944         return ret;
8945 }
8946
8947
8948 /*
8949  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8950  * @vsi: VSI to be configured
8951  * @tc_map: enabled TC bitmap
8952  *
8953  * Returns 0 on success, negative value on failure
8954  */
8955 static enum i40e_status_code
8956 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8957 {
8958         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8959         struct i40e_vsi_context ctxt;
8960         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8961         enum i40e_status_code ret = I40E_SUCCESS;
8962         int i;
8963
8964         /* Check if enabled_tc is same as existing or new TCs */
8965         if (vsi->enabled_tc == tc_map)
8966                 return ret;
8967
8968         /* configure tc bandwidth */
8969         memset(&bw_data, 0, sizeof(bw_data));
8970         bw_data.tc_valid_bits = tc_map;
8971         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8972         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8973                 if (tc_map & BIT_ULL(i))
8974                         bw_data.tc_bw_credits[i] = 1;
8975         }
8976         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8977         if (ret) {
8978                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8979                         " per TC failed = %d",
8980                         hw->aq.asq_last_status);
8981                 goto out;
8982         }
8983         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8984                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8985
8986         /* Update Queue Pairs Mapping for currently enabled UPs */
8987         ctxt.seid = vsi->seid;
8988         ctxt.pf_num = hw->pf_id;
8989         ctxt.vf_num = 0;
8990         ctxt.uplink_seid = vsi->uplink_seid;
8991         ctxt.info = vsi->info;
8992         i40e_get_cap(hw);
8993         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8994         if (ret)
8995                 goto out;
8996
8997         /* Update the VSI after updating the VSI queue-mapping information */
8998         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8999         if (ret) {
9000                 PMD_INIT_LOG(ERR, "Failed to configure "
9001                             "TC queue mapping = %d",
9002                             hw->aq.asq_last_status);
9003                 goto out;
9004         }
9005         /* update the local VSI info with updated queue map */
9006         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9007                                         sizeof(vsi->info.tc_mapping));
9008         (void)rte_memcpy(&vsi->info.queue_mapping,
9009                         &ctxt.info.queue_mapping,
9010                 sizeof(vsi->info.queue_mapping));
9011         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9012         vsi->info.valid_sections = 0;
9013
9014         /* query and update current VSI BW information */
9015         ret = i40e_vsi_get_bw_config(vsi);
9016         if (ret) {
9017                 PMD_INIT_LOG(ERR,
9018                          "Failed updating vsi bw info, err %s aq_err %s",
9019                          i40e_stat_str(hw, ret),
9020                          i40e_aq_str(hw, hw->aq.asq_last_status));
9021                 goto out;
9022         }
9023
9024         vsi->enabled_tc = tc_map;
9025
9026 out:
9027         return ret;
9028 }
9029
9030 /*
9031  * i40e_dcb_hw_configure - program the dcb setting to hw
9032  * @pf: pf the configuration is taken on
9033  * @new_cfg: new configuration
9034  * @tc_map: enabled TC bitmap
9035  *
9036  * Returns 0 on success, negative value on failure
9037  */
9038 static enum i40e_status_code
9039 i40e_dcb_hw_configure(struct i40e_pf *pf,
9040                       struct i40e_dcbx_config *new_cfg,
9041                       uint8_t tc_map)
9042 {
9043         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9044         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9045         struct i40e_vsi *main_vsi = pf->main_vsi;
9046         struct i40e_vsi_list *vsi_list;
9047         enum i40e_status_code ret;
9048         int i;
9049         uint32_t val;
9050
9051         /* Use the FW API if FW > v4.4*/
9052         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9053               (hw->aq.fw_maj_ver >= 5))) {
9054                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9055                                   " to configure DCB");
9056                 return I40E_ERR_FIRMWARE_API_VERSION;
9057         }
9058
9059         /* Check if need reconfiguration */
9060         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9061                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9062                 return I40E_SUCCESS;
9063         }
9064
9065         /* Copy the new config to the current config */
9066         *old_cfg = *new_cfg;
9067         old_cfg->etsrec = old_cfg->etscfg;
9068         ret = i40e_set_dcb_config(hw);
9069         if (ret) {
9070                 PMD_INIT_LOG(ERR,
9071                          "Set DCB Config failed, err %s aq_err %s\n",
9072                          i40e_stat_str(hw, ret),
9073                          i40e_aq_str(hw, hw->aq.asq_last_status));
9074                 return ret;
9075         }
9076         /* set receive Arbiter to RR mode and ETS scheme by default */
9077         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9078                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9079                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9080                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9081                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9082                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9083                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9084                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9085                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9086                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9087                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9088                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9089                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9090         }
9091         /* get local mib to check whether it is configured correctly */
9092         /* IEEE mode */
9093         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9094         /* Get Local DCB Config */
9095         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9096                                      &hw->local_dcbx_config);
9097
9098         /* if Veb is created, need to update TC of it at first */
9099         if (main_vsi->veb) {
9100                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9101                 if (ret)
9102                         PMD_INIT_LOG(WARNING,
9103                                  "Failed configuring TC for VEB seid=%d\n",
9104                                  main_vsi->veb->seid);
9105         }
9106         /* Update each VSI */
9107         i40e_vsi_config_tc(main_vsi, tc_map);
9108         if (main_vsi->veb) {
9109                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9110                         /* Beside main VSI and VMDQ VSIs, only enable default
9111                          * TC for other VSIs
9112                          */
9113                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9114                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9115                                                          tc_map);
9116                         else
9117                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9118                                                          I40E_DEFAULT_TCMAP);
9119                         if (ret)
9120                                 PMD_INIT_LOG(WARNING,
9121                                          "Failed configuring TC for VSI seid=%d\n",
9122                                          vsi_list->vsi->seid);
9123                         /* continue */
9124                 }
9125         }
9126         return I40E_SUCCESS;
9127 }
9128
9129 /*
9130  * i40e_dcb_init_configure - initial dcb config
9131  * @dev: device being configured
9132  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9133  *
9134  * Returns 0 on success, negative value on failure
9135  */
9136 static int
9137 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9138 {
9139         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9140         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9141         int ret = 0;
9142
9143         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9144                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9145                 return -ENOTSUP;
9146         }
9147
9148         /* DCB initialization:
9149          * Update DCB configuration from the Firmware and configure
9150          * LLDP MIB change event.
9151          */
9152         if (sw_dcb == TRUE) {
9153                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9154                 if (ret != I40E_SUCCESS)
9155                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9156
9157                 ret = i40e_init_dcb(hw);
9158                 /* if sw_dcb, lldp agent is stopped, the return from
9159                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9160                  * adminq status.
9161                  */
9162                 if (ret != I40E_SUCCESS &&
9163                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9164                         memset(&hw->local_dcbx_config, 0,
9165                                 sizeof(struct i40e_dcbx_config));
9166                         /* set dcb default configuration */
9167                         hw->local_dcbx_config.etscfg.willing = 0;
9168                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9169                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9170                         hw->local_dcbx_config.etscfg.tsatable[0] =
9171                                                 I40E_IEEE_TSA_ETS;
9172                         hw->local_dcbx_config.etsrec =
9173                                 hw->local_dcbx_config.etscfg;
9174                         hw->local_dcbx_config.pfc.willing = 0;
9175                         hw->local_dcbx_config.pfc.pfccap =
9176                                                 I40E_MAX_TRAFFIC_CLASS;
9177                         /* FW needs one App to configure HW */
9178                         hw->local_dcbx_config.numapps = 1;
9179                         hw->local_dcbx_config.app[0].selector =
9180                                                 I40E_APP_SEL_ETHTYPE;
9181                         hw->local_dcbx_config.app[0].priority = 3;
9182                         hw->local_dcbx_config.app[0].protocolid =
9183                                                 I40E_APP_PROTOID_FCOE;
9184                         ret = i40e_set_dcb_config(hw);
9185                         if (ret) {
9186                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9187                                         " err = %d, aq_err = %d.", ret,
9188                                           hw->aq.asq_last_status);
9189                                 return -ENOSYS;
9190                         }
9191                 } else {
9192                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9193                                           " aq_err = %d.", ret,
9194                                           hw->aq.asq_last_status);
9195                         return -ENOTSUP;
9196                 }
9197         } else {
9198                 ret = i40e_aq_start_lldp(hw, NULL);
9199                 if (ret != I40E_SUCCESS)
9200                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9201
9202                 ret = i40e_init_dcb(hw);
9203                 if (!ret) {
9204                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9205                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9206                                                   " DCBX offload.");
9207                                 return -ENOTSUP;
9208                         }
9209                 } else {
9210                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9211                                           " aq_err = %d.", ret,
9212                                           hw->aq.asq_last_status);
9213                         return -ENOTSUP;
9214                 }
9215         }
9216         return 0;
9217 }
9218
9219 /*
9220  * i40e_dcb_setup - setup dcb related config
9221  * @dev: device being configured
9222  *
9223  * Returns 0 on success, negative value on failure
9224  */
9225 static int
9226 i40e_dcb_setup(struct rte_eth_dev *dev)
9227 {
9228         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9229         struct i40e_dcbx_config dcb_cfg;
9230         uint8_t tc_map = 0;
9231         int ret = 0;
9232
9233         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9234                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9235                 return -ENOTSUP;
9236         }
9237
9238         if (pf->vf_num != 0)
9239                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9240
9241         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9242         if (ret) {
9243                 PMD_INIT_LOG(ERR, "invalid dcb config");
9244                 return -EINVAL;
9245         }
9246         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9247         if (ret) {
9248                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9249                 return -ENOSYS;
9250         }
9251
9252         return 0;
9253 }
9254
9255 static int
9256 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9257                       struct rte_eth_dcb_info *dcb_info)
9258 {
9259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9260         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9261         struct i40e_vsi *vsi = pf->main_vsi;
9262         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9263         uint16_t bsf, tc_mapping;
9264         int i, j = 0;
9265
9266         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9267                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9268         else
9269                 dcb_info->nb_tcs = 1;
9270         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9271                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9272         for (i = 0; i < dcb_info->nb_tcs; i++)
9273                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9274
9275         /* get queue mapping if vmdq is disabled */
9276         if (!pf->nb_cfg_vmdq_vsi) {
9277                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9278                         if (!(vsi->enabled_tc & (1 << i)))
9279                                 continue;
9280                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9281                         dcb_info->tc_queue.tc_rxq[j][i].base =
9282                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9283                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9284                         dcb_info->tc_queue.tc_txq[j][i].base =
9285                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9286                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9287                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9288                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9289                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9290                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9291                 }
9292                 return 0;
9293         }
9294
9295         /* get queue mapping if vmdq is enabled */
9296         do {
9297                 vsi = pf->vmdq[j].vsi;
9298                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9299                         if (!(vsi->enabled_tc & (1 << i)))
9300                                 continue;
9301                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9302                         dcb_info->tc_queue.tc_rxq[j][i].base =
9303                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9304                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9305                         dcb_info->tc_queue.tc_txq[j][i].base =
9306                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9307                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9308                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9309                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9310                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9311                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9312                 }
9313                 j++;
9314         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9315         return 0;
9316 }
9317
9318 static int
9319 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9320 {
9321         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9322         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9323         uint16_t interval =
9324                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9325         uint16_t msix_intr;
9326
9327         msix_intr = intr_handle->intr_vec[queue_id];
9328         if (msix_intr == I40E_MISC_VEC_ID)
9329                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9330                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9331                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9332                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9333                                (interval <<
9334                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9335         else
9336                 I40E_WRITE_REG(hw,
9337                                I40E_PFINT_DYN_CTLN(msix_intr -
9338                                                    I40E_RX_VEC_START),
9339                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9340                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9341                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9342                                (interval <<
9343                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9344
9345         I40E_WRITE_FLUSH(hw);
9346         rte_intr_enable(&dev->pci_dev->intr_handle);
9347
9348         return 0;
9349 }
9350
9351 static int
9352 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9353 {
9354         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9356         uint16_t msix_intr;
9357
9358         msix_intr = intr_handle->intr_vec[queue_id];
9359         if (msix_intr == I40E_MISC_VEC_ID)
9360                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9361         else
9362                 I40E_WRITE_REG(hw,
9363                                I40E_PFINT_DYN_CTLN(msix_intr -
9364                                                    I40E_RX_VEC_START),
9365                                0);
9366         I40E_WRITE_FLUSH(hw);
9367
9368         return 0;
9369 }
9370
9371 static int i40e_get_regs(struct rte_eth_dev *dev,
9372                          struct rte_dev_reg_info *regs)
9373 {
9374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9375         uint32_t *ptr_data = regs->data;
9376         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9377         const struct i40e_reg_info *reg_info;
9378
9379         if (ptr_data == NULL) {
9380                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9381                 regs->width = sizeof(uint32_t);
9382                 return 0;
9383         }
9384
9385         /* The first few registers have to be read using AQ operations */
9386         reg_idx = 0;
9387         while (i40e_regs_adminq[reg_idx].name) {
9388                 reg_info = &i40e_regs_adminq[reg_idx++];
9389                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9390                         for (arr_idx2 = 0;
9391                                         arr_idx2 <= reg_info->count2;
9392                                         arr_idx2++) {
9393                                 reg_offset = arr_idx * reg_info->stride1 +
9394                                         arr_idx2 * reg_info->stride2;
9395                                 reg_offset += reg_info->base_addr;
9396                                 ptr_data[reg_offset >> 2] =
9397                                         i40e_read_rx_ctl(hw, reg_offset);
9398                         }
9399         }
9400
9401         /* The remaining registers can be read using primitives */
9402         reg_idx = 0;
9403         while (i40e_regs_others[reg_idx].name) {
9404                 reg_info = &i40e_regs_others[reg_idx++];
9405                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9406                         for (arr_idx2 = 0;
9407                                         arr_idx2 <= reg_info->count2;
9408                                         arr_idx2++) {
9409                                 reg_offset = arr_idx * reg_info->stride1 +
9410                                         arr_idx2 * reg_info->stride2;
9411                                 reg_offset += reg_info->base_addr;
9412                                 ptr_data[reg_offset >> 2] =
9413                                         I40E_READ_REG(hw, reg_offset);
9414                         }
9415         }
9416
9417         return 0;
9418 }
9419
9420 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9421 {
9422         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9423
9424         /* Convert word count to byte count */
9425         return hw->nvm.sr_size << 1;
9426 }
9427
9428 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9429                            struct rte_dev_eeprom_info *eeprom)
9430 {
9431         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9432         uint16_t *data = eeprom->data;
9433         uint16_t offset, length, cnt_words;
9434         int ret_code;
9435
9436         offset = eeprom->offset >> 1;
9437         length = eeprom->length >> 1;
9438         cnt_words = length;
9439
9440         if (offset > hw->nvm.sr_size ||
9441                 offset + length > hw->nvm.sr_size) {
9442                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9443                 return -EINVAL;
9444         }
9445
9446         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9447
9448         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9449         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9450                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9451                 return -EIO;
9452         }
9453
9454         return 0;
9455 }
9456
9457 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9458                                       struct ether_addr *mac_addr)
9459 {
9460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9461
9462         if (!is_valid_assigned_ether_addr(mac_addr)) {
9463                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9464                 return;
9465         }
9466
9467         /* Flags: 0x3 updates port address */
9468         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9469 }
9470
9471 static int
9472 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9473 {
9474         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9475         struct rte_eth_dev_data *dev_data = pf->dev_data;
9476         uint32_t frame_size = mtu + ETHER_HDR_LEN
9477                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9478         int ret = 0;
9479
9480         /* check if mtu is within the allowed range */
9481         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9482                 return -EINVAL;
9483
9484         /* mtu setting is forbidden if port is start */
9485         if (dev_data->dev_started) {
9486                 PMD_DRV_LOG(ERR,
9487                             "port %d must be stopped before configuration\n",
9488                             dev_data->port_id);
9489                 return -EBUSY;
9490         }
9491
9492         if (frame_size > ETHER_MAX_LEN)
9493                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9494         else
9495                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9496
9497         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9498
9499         return ret;
9500 }