drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(
 377                 __rte_unused struct rte_intr_handle *handle, void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static void i40e_configure_registers(struct i40e_hw *hw);
 422 static void i40e_hw_init(struct rte_eth_dev *dev);
 423 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 424 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 425                         struct rte_eth_mirror_conf *mirror_conf,
 426                         uint8_t sw_id, uint8_t on);
 427 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 428
 429 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 430 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 431 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 432                                            struct timespec *timestamp,
 433                                            uint32_t flags);
 434 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 435                                            struct timespec *timestamp);
 436 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 437
 438 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 439
 440 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 441                                    struct timespec *timestamp);
 442 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 443                                     const struct timespec *timestamp);
 444
 445 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 446                                          uint16_t queue_id);
 447 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 448                                           uint16_t queue_id);
 449
 450 static int i40e_get_regs(struct rte_eth_dev *dev,
 451                          struct rte_dev_reg_info *regs);
 452
 453 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 454
 455 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 456                            struct rte_dev_eeprom_info *eeprom);
 457
 458 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 459                                       struct ether_addr *mac_addr);
 460
 461 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 462
 463 static const struct rte_pci_id pci_id_i40e_map[] = {
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct eth_dev_ops i40e_eth_dev_ops = {
 489         .dev_configure                = i40e_dev_configure,
 490         .dev_start                    = i40e_dev_start,
 491         .dev_stop                     = i40e_dev_stop,
 492         .dev_close                    = i40e_dev_close,
 493         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 494         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 495         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 496         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 497         .dev_set_link_up              = i40e_dev_set_link_up,
 498         .dev_set_link_down            = i40e_dev_set_link_down,
 499         .link_update                  = i40e_dev_link_update,
 500         .stats_get                    = i40e_dev_stats_get,
 501         .xstats_get                   = i40e_dev_xstats_get,
 502         .xstats_get_names             = i40e_dev_xstats_get_names,
 503         .stats_reset                  = i40e_dev_stats_reset,
 504         .xstats_reset                 = i40e_dev_stats_reset,
 505         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 506         .dev_infos_get                = i40e_dev_info_get,
 507         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 508         .vlan_filter_set              = i40e_vlan_filter_set,
 509         .vlan_tpid_set                = i40e_vlan_tpid_set,
 510         .vlan_offload_set             = i40e_vlan_offload_set,
 511         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 512         .vlan_pvid_set                = i40e_vlan_pvid_set,
 513         .rx_queue_start               = i40e_dev_rx_queue_start,
 514         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 515         .tx_queue_start               = i40e_dev_tx_queue_start,
 516         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 517         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 518         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 519         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 520         .rx_queue_release             = i40e_dev_rx_queue_release,
 521         .rx_queue_count               = i40e_dev_rx_queue_count,
 522         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 523         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 524         .tx_queue_release             = i40e_dev_tx_queue_release,
 525         .dev_led_on                   = i40e_dev_led_on,
 526         .dev_led_off                  = i40e_dev_led_off,
 527         .flow_ctrl_get                = i40e_flow_ctrl_get,
 528         .flow_ctrl_set                = i40e_flow_ctrl_set,
 529         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 530         .mac_addr_add                 = i40e_macaddr_add,
 531         .mac_addr_remove              = i40e_macaddr_remove,
 532         .reta_update                  = i40e_dev_rss_reta_update,
 533         .reta_query                   = i40e_dev_rss_reta_query,
 534         .rss_hash_update              = i40e_dev_rss_hash_update,
 535         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 536         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 537         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 538         .filter_ctrl                  = i40e_dev_filter_ctrl,
 539         .rxq_info_get                 = i40e_rxq_info_get,
 540         .txq_info_get                 = i40e_txq_info_get,
 541         .mirror_rule_set              = i40e_mirror_rule_set,
 542         .mirror_rule_reset            = i40e_mirror_rule_reset,
 543         .timesync_enable              = i40e_timesync_enable,
 544         .timesync_disable             = i40e_timesync_disable,
 545         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 547         .get_dcb_info                 = i40e_dev_get_dcb_info,
 548         .timesync_adjust_time         = i40e_timesync_adjust_time,
 549         .timesync_read_time           = i40e_timesync_read_time,
 550         .timesync_write_time          = i40e_timesync_write_time,
 551         .get_reg                      = i40e_get_regs,
 552         .get_eeprom_length            = i40e_get_eeprom_length,
 553         .get_eeprom                   = i40e_get_eeprom,
 554         .mac_addr_set                 = i40e_set_default_mac_addr,
 555         .mtu_set                      = i40e_dev_mtu_set,
 556 };
 557
 558 /* store statistics names and its offset in stats structure */
 559 struct rte_i40e_xstats_name_off {
 560         char name[RTE_ETH_XSTATS_NAME_SIZE];
 561         unsigned offset;
 562 };
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 565         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 566         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 567         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 568         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 569         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 570                 rx_unknown_protocol)},
 571         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 572         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 573         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 574         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 575 };
 576
 577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 578                 sizeof(rte_i40e_stats_strings[0]))
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 581         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 582                 tx_dropped_link_down)},
 583         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 584         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 585                 illegal_bytes)},
 586         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 587         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 588                 mac_local_faults)},
 589         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 590                 mac_remote_faults)},
 591         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_length_errors)},
 593         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 594         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 595         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 596         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 597         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 598         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 599                 rx_size_127)},
 600         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 601                 rx_size_255)},
 602         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 603                 rx_size_511)},
 604         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 605                 rx_size_1023)},
 606         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 607                 rx_size_1522)},
 608         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 609                 rx_size_big)},
 610         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_undersize)},
 612         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 613                 rx_oversize)},
 614         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 615                 mac_short_packet_dropped)},
 616         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 617                 rx_fragments)},
 618         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 619         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 620         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 621                 tx_size_127)},
 622         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 623                 tx_size_255)},
 624         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 625                 tx_size_511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 627                 tx_size_1023)},
 628         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 629                 tx_size_1522)},
 630         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 631                 tx_size_big)},
 632         {"rx_flow_director_atr_match_packets",
 633                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 634         {"rx_flow_director_sb_match_packets",
 635                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 636         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 637                 tx_lpi_status)},
 638         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 639                 rx_lpi_status)},
 640         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 641                 tx_lpi_count)},
 642         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 643                 rx_lpi_count)},
 644 };
 645
 646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 647                 sizeof(rte_i40e_hw_port_strings[0]))
 648
 649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 650         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 651                 priority_xon_rx)},
 652         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 653                 priority_xoff_rx)},
 654 };
 655
 656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 657                 sizeof(rte_i40e_rxq_prio_strings[0]))
 658
 659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 660         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 661                 priority_xon_tx)},
 662         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 663                 priority_xoff_tx)},
 664         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 665                 priority_xon_2_xoff)},
 666 };
 667
 668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 669                 sizeof(rte_i40e_txq_prio_strings[0]))
 670
 671 static struct eth_driver rte_i40e_pmd = {
 672         .pci_drv = {
 673                 .name = "rte_i40e_pmd",
 674                 .id_table = pci_id_i40e_map,
 675                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 676                         RTE_PCI_DRV_DETACHABLE,
 677         },
 678         .eth_dev_init = eth_i40e_dev_init,
 679         .eth_dev_uninit = eth_i40e_dev_uninit,
 680         .dev_private_size = sizeof(struct i40e_adapter),
 681 };
 682
 683 static inline int
 684 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 685                                      struct rte_eth_link *link)
 686 {
 687         struct rte_eth_link *dst = link;
 688         struct rte_eth_link *src = &(dev->data->dev_link);
 689
 690         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 691                                         *(uint64_t *)src) == 0)
 692                 return -1;
 693
 694         return 0;
 695 }
 696
 697 static inline int
 698 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 699                                       struct rte_eth_link *link)
 700 {
 701         struct rte_eth_link *dst = &(dev->data->dev_link);
 702         struct rte_eth_link *src = link;
 703
 704         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 705                                         *(uint64_t *)src) == 0)
 706                 return -1;
 707
 708         return 0;
 709 }
 710
 711 /*
 712  * Driver initialization routine.
 713  * Invoked once at EAL init time.
 714  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 715  */
 716 static int
 717 rte_i40e_pmd_init(const char *name __rte_unused,
 718                   const char *params __rte_unused)
 719 {
 720         PMD_INIT_FUNC_TRACE();
 721         rte_eth_driver_register(&rte_i40e_pmd);
 722
 723         return 0;
 724 }
 725
 726 static struct rte_driver rte_i40e_driver = {
 727         .type = PMD_PDEV,
 728         .init = rte_i40e_pmd_init,
 729 };
 730
 731 PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
 732 DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
 733
 734 #ifndef I40E_GLQF_ORT
 735 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 736 #endif
 737 #ifndef I40E_GLQF_PIT
 738 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 739 #endif
 740
 741 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 742 {
 743         /*
 744          * Initialize registers for flexible payload, which should be set by NVM.
 745          * This should be removed from code once it is fixed in NVM.
 746          */
 747         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 748         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 749         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 750         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 751         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 752         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 753         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 754         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 755         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 756         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 757         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 758         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 759
 760         /* Initialize registers for parsing packet type of QinQ */
 761         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 762         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 763 }
 764
 765 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 766
 767 /*
 768  * Add a ethertype filter to drop all flow control frames transmitted
 769  * from VSIs.
 770 */
 771 static void
 772 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 773 {
 774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 775         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 776                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 777                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 778         int ret;
 779
 780         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 781                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 782                                 pf->main_vsi_seid, 0,
 783                                 TRUE, NULL, NULL);
 784         if (ret)
 785                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 786                                   " frames from VSIs.");
 787 }
 788
 789 static int
 790 floating_veb_list_handler(__rte_unused const char *key,
 791                           const char *floating_veb_value,
 792                           void *opaque)
 793 {
 794         int idx = 0;
 795         unsigned int count = 0;
 796         char *end = NULL;
 797         int min, max;
 798         bool *vf_floating_veb = opaque;
 799
 800         while (isblank(*floating_veb_value))
 801                 floating_veb_value++;
 802
 803         /* Reset floating VEB configuration for VFs */
 804         for (idx = 0; idx < I40E_MAX_VF; idx++)
 805                 vf_floating_veb[idx] = false;
 806
 807         min = I40E_MAX_VF;
 808         do {
 809                 while (isblank(*floating_veb_value))
 810                         floating_veb_value++;
 811                 if (*floating_veb_value == '\0')
 812                         return -1;
 813                 errno = 0;
 814                 idx = strtoul(floating_veb_value, &end, 10);
 815                 if (errno || end == NULL)
 816                         return -1;
 817                 while (isblank(*end))
 818                         end++;
 819                 if (*end == '-') {
 820                         min = idx;
 821                 } else if ((*end == ';') || (*end == '\0')) {
 822                         max = idx;
 823                         if (min == I40E_MAX_VF)
 824                                 min = idx;
 825                         if (max >= I40E_MAX_VF)
 826                                 max = I40E_MAX_VF - 1;
 827                         for (idx = min; idx <= max; idx++) {
 828                                 vf_floating_veb[idx] = true;
 829                                 count++;
 830                         }
 831                         min = I40E_MAX_VF;
 832                 } else {
 833                         return -1;
 834                 }
 835                 floating_veb_value = end + 1;
 836         } while (*end != '\0');
 837
 838         if (count == 0)
 839                 return -1;
 840
 841         return 0;
 842 }
 843
 844 static void
 845 config_vf_floating_veb(struct rte_devargs *devargs,
 846                        uint16_t floating_veb,
 847                        bool *vf_floating_veb)
 848 {
 849         struct rte_kvargs *kvlist;
 850         int i;
 851         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 852
 853         if (!floating_veb)
 854                 return;
 855         /* All the VFs attach to the floating VEB by default
 856          * when the floating VEB is enabled.
 857          */
 858         for (i = 0; i < I40E_MAX_VF; i++)
 859                 vf_floating_veb[i] = true;
 860
 861         if (devargs == NULL)
 862                 return;
 863
 864         kvlist = rte_kvargs_parse(devargs->args, NULL);
 865         if (kvlist == NULL)
 866                 return;
 867
 868         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 869                 rte_kvargs_free(kvlist);
 870                 return;
 871         }
 872         /* When the floating_veb_list parameter exists, all the VFs
 873          * will attach to the legacy VEB firstly, then configure VFs
 874          * to the floating VEB according to the floating_veb_list.
 875          */
 876         if (rte_kvargs_process(kvlist, floating_veb_list,
 877                                floating_veb_list_handler,
 878                                vf_floating_veb) < 0) {
 879                 rte_kvargs_free(kvlist);
 880                 return;
 881         }
 882         rte_kvargs_free(kvlist);
 883 }
 884
 885 static int
 886 i40e_check_floating_handler(__rte_unused const char *key,
 887                             const char *value,
 888                             __rte_unused void *opaque)
 889 {
 890         if (strcmp(value, "1"))
 891                 return -1;
 892
 893         return 0;
 894 }
 895
 896 static int
 897 is_floating_veb_supported(struct rte_devargs *devargs)
 898 {
 899         struct rte_kvargs *kvlist;
 900         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 901
 902         if (devargs == NULL)
 903                 return 0;
 904
 905         kvlist = rte_kvargs_parse(devargs->args, NULL);
 906         if (kvlist == NULL)
 907                 return 0;
 908
 909         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 910                 rte_kvargs_free(kvlist);
 911                 return 0;
 912         }
 913         /* Floating VEB is enabled when there's key-value:
 914          * enable_floating_veb=1
 915          */
 916         if (rte_kvargs_process(kvlist, floating_veb_key,
 917                                i40e_check_floating_handler, NULL) < 0) {
 918                 rte_kvargs_free(kvlist);
 919                 return 0;
 920         }
 921         rte_kvargs_free(kvlist);
 922
 923         return 1;
 924 }
 925
 926 static void
 927 config_floating_veb(struct rte_eth_dev *dev)
 928 {
 929         struct rte_pci_device *pci_dev = dev->pci_dev;
 930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 932
 933         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 934
 935         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 936                 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
 937                 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
 938                                        pf->floating_veb_list);
 939         } else {
 940                 pf->floating_veb = false;
 941         }
 942 }
 943
 944 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 945 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 946
 947 static int
 948 eth_i40e_dev_init(struct rte_eth_dev *dev)
 949 {
 950         struct rte_pci_device *pci_dev;
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 953         struct i40e_vsi *vsi;
 954         int ret;
 955         uint32_t len;
 956         uint8_t aq_fail = 0;
 957
 958         PMD_INIT_FUNC_TRACE();
 959
 960         dev->dev_ops = &i40e_eth_dev_ops;
 961         dev->rx_pkt_burst = i40e_recv_pkts;
 962         dev->tx_pkt_burst = i40e_xmit_pkts;
 963
 964         /* for secondary processes, we don't initialise any further as primary
 965          * has already done this work. Only check we don't need a different
 966          * RX function */
 967         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 968                 i40e_set_rx_function(dev);
 969                 i40e_set_tx_function(dev);
 970                 return 0;
 971         }
 972         pci_dev = dev->pci_dev;
 973
 974         rte_eth_copy_pci_info(dev, pci_dev);
 975
 976         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 977         pf->adapter->eth_dev = dev;
 978         pf->dev_data = dev->data;
 979
 980         hw->back = I40E_PF_TO_ADAPTER(pf);
 981         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 982         if (!hw->hw_addr) {
 983                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 984                              "as address is NULL");
 985                 return -ENODEV;
 986         }
 987
 988         hw->vendor_id = pci_dev->id.vendor_id;
 989         hw->device_id = pci_dev->id.device_id;
 990         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 991         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 992         hw->bus.device = pci_dev->addr.devid;
 993         hw->bus.func = pci_dev->addr.function;
 994         hw->adapter_stopped = 0;
 995
 996         /* Make sure all is clean before doing PF reset */
 997         i40e_clear_hw(hw);
 998
 999         /* Initialize the hardware */
1000         i40e_hw_init(dev);
1001
1002         /* Reset here to make sure all is clean for each PF */
1003         ret = i40e_pf_reset(hw);
1004         if (ret) {
1005                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1006                 return ret;
1007         }
1008
1009         /* Initialize the shared code (base driver) */
1010         ret = i40e_init_shared_code(hw);
1011         if (ret) {
1012                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1013                 return ret;
1014         }
1015
1016         /*
1017          * To work around the NVM issue, initialize registers
1018          * for flexible payload and packet type of QinQ by
1019          * software. It should be removed once issues are fixed
1020          * in NVM.
1021          */
1022         i40e_GLQF_reg_init(hw);
1023
1024         /* Initialize the input set for filters (hash and fd) to default value */
1025         i40e_filter_input_set_init(pf);
1026
1027         /* Initialize the parameters for adminq */
1028         i40e_init_adminq_parameter(hw);
1029         ret = i40e_init_adminq(hw);
1030         if (ret != I40E_SUCCESS) {
1031                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1032                 return -EIO;
1033         }
1034         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1035                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1036                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1037                      ((hw->nvm.version >> 12) & 0xf),
1038                      ((hw->nvm.version >> 4) & 0xff),
1039                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1040
1041         /* Need the special FW version to support floating VEB */
1042         config_floating_veb(dev);
1043         /* Clear PXE mode */
1044         i40e_clear_pxe_mode(hw);
1045
1046         /*
1047          * On X710, performance number is far from the expectation on recent
1048          * firmware versions. The fix for this issue may not be integrated in
1049          * the following firmware version. So the workaround in software driver
1050          * is needed. It needs to modify the initial values of 3 internal only
1051          * registers. Note that the workaround can be removed when it is fixed
1052          * in firmware in the future.
1053          */
1054         i40e_configure_registers(hw);
1055
1056         /* Get hw capabilities */
1057         ret = i40e_get_cap(hw);
1058         if (ret != I40E_SUCCESS) {
1059                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1060                 goto err_get_capabilities;
1061         }
1062
1063         /* Initialize parameters for PF */
1064         ret = i40e_pf_parameter_init(dev);
1065         if (ret != 0) {
1066                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1067                 goto err_parameter_init;
1068         }
1069
1070         /* Initialize the queue management */
1071         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1072         if (ret < 0) {
1073                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1074                 goto err_qp_pool_init;
1075         }
1076         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1077                                 hw->func_caps.num_msix_vectors - 1);
1078         if (ret < 0) {
1079                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1080                 goto err_msix_pool_init;
1081         }
1082
1083         /* Initialize lan hmc */
1084         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1085                                 hw->func_caps.num_rx_qp, 0, 0);
1086         if (ret != I40E_SUCCESS) {
1087                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1088                 goto err_init_lan_hmc;
1089         }
1090
1091         /* Configure lan hmc */
1092         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1093         if (ret != I40E_SUCCESS) {
1094                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1095                 goto err_configure_lan_hmc;
1096         }
1097
1098         /* Get and check the mac address */
1099         i40e_get_mac_addr(hw, hw->mac.addr);
1100         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1101                 PMD_INIT_LOG(ERR, "mac address is not valid");
1102                 ret = -EIO;
1103                 goto err_get_mac_addr;
1104         }
1105         /* Copy the permanent MAC address */
1106         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1107                         (struct ether_addr *) hw->mac.perm_addr);
1108
1109         /* Disable flow control */
1110         hw->fc.requested_mode = I40E_FC_NONE;
1111         i40e_set_fc(hw, &aq_fail, TRUE);
1112
1113         /* Set the global registers with default ether type value */
1114         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1115         if (ret != I40E_SUCCESS) {
1116                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1117                              "VLAN ether type");
1118                 goto err_setup_pf_switch;
1119         }
1120
1121         /* PF setup, which includes VSI setup */
1122         ret = i40e_pf_setup(pf);
1123         if (ret) {
1124                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1125                 goto err_setup_pf_switch;
1126         }
1127
1128         /* reset all stats of the device, including pf and main vsi */
1129         i40e_dev_stats_reset(dev);
1130
1131         vsi = pf->main_vsi;
1132
1133         /* Disable double vlan by default */
1134         i40e_vsi_config_double_vlan(vsi, FALSE);
1135
1136         /* Disable S-TAG identification when floating_veb is disabled */
1137         if (!pf->floating_veb) {
1138                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1139                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1140                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1141                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1142                 }
1143         }
1144
1145         if (!vsi->max_macaddrs)
1146                 len = ETHER_ADDR_LEN;
1147         else
1148                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1149
1150         /* Should be after VSI initialized */
1151         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1152         if (!dev->data->mac_addrs) {
1153                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1154                                         "for storing mac address");
1155                 goto err_mac_alloc;
1156         }
1157         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1158                                         &dev->data->mac_addrs[0]);
1159
1160         /* initialize pf host driver to setup SRIOV resource if applicable */
1161         i40e_pf_host_init(dev);
1162
1163         /* register callback func to eal lib */
1164         rte_intr_callback_register(&(pci_dev->intr_handle),
1165                 i40e_dev_interrupt_handler, (void *)dev);
1166
1167         /* configure and enable device interrupt */
1168         i40e_pf_config_irq0(hw, TRUE);
1169         i40e_pf_enable_irq0(hw);
1170
1171         /* enable uio intr after callback register */
1172         rte_intr_enable(&(pci_dev->intr_handle));
1173         /*
1174          * Add an ethertype filter to drop all flow control frames transmitted
1175          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1176          * frames to wire.
1177          */
1178         i40e_add_tx_flow_control_drop_filter(pf);
1179
1180         /* Set the max frame size to 0x2600 by default,
1181          * in case other drivers changed the default value.
1182          */
1183         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1184
1185         /* initialize mirror rule list */
1186         TAILQ_INIT(&pf->mirror_list);
1187
1188         /* Init dcb to sw mode by default */
1189         ret = i40e_dcb_init_configure(dev, TRUE);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1192                 pf->flags &= ~I40E_FLAG_DCB;
1193         }
1194
1195         return 0;
1196
1197 err_mac_alloc:
1198         i40e_vsi_release(pf->main_vsi);
1199 err_setup_pf_switch:
1200 err_get_mac_addr:
1201 err_configure_lan_hmc:
1202         (void)i40e_shutdown_lan_hmc(hw);
1203 err_init_lan_hmc:
1204         i40e_res_pool_destroy(&pf->msix_pool);
1205 err_msix_pool_init:
1206         i40e_res_pool_destroy(&pf->qp_pool);
1207 err_qp_pool_init:
1208 err_parameter_init:
1209 err_get_capabilities:
1210         (void)i40e_shutdown_adminq(hw);
1211
1212         return ret;
1213 }
1214
1215 static int
1216 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1217 {
1218         struct rte_pci_device *pci_dev;
1219         struct i40e_hw *hw;
1220         struct i40e_filter_control_settings settings;
1221         int ret;
1222         uint8_t aq_fail = 0;
1223
1224         PMD_INIT_FUNC_TRACE();
1225
1226         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1227                 return 0;
1228
1229         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1230         pci_dev = dev->pci_dev;
1231
1232         if (hw->adapter_stopped == 0)
1233                 i40e_dev_close(dev);
1234
1235         dev->dev_ops = NULL;
1236         dev->rx_pkt_burst = NULL;
1237         dev->tx_pkt_burst = NULL;
1238
1239         /* Clear PXE mode */
1240         i40e_clear_pxe_mode(hw);
1241
1242         /* Unconfigure filter control */
1243         memset(&settings, 0, sizeof(settings));
1244         ret = i40e_set_filter_control(hw, &settings);
1245         if (ret)
1246                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1247                                         ret);
1248
1249         /* Disable flow control */
1250         hw->fc.requested_mode = I40E_FC_NONE;
1251         i40e_set_fc(hw, &aq_fail, TRUE);
1252
1253         /* uninitialize pf host driver */
1254         i40e_pf_host_uninit(dev);
1255
1256         rte_free(dev->data->mac_addrs);
1257         dev->data->mac_addrs = NULL;
1258
1259         /* disable uio intr before callback unregister */
1260         rte_intr_disable(&(pci_dev->intr_handle));
1261
1262         /* register callback func to eal lib */
1263         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1264                 i40e_dev_interrupt_handler, (void *)dev);
1265
1266         return 0;
1267 }
1268
1269 static int
1270 i40e_dev_configure(struct rte_eth_dev *dev)
1271 {
1272         struct i40e_adapter *ad =
1273                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1274         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1275         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1276         int i, ret;
1277
1278         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1279          * bulk allocation or vector Rx preconditions we will reset it.
1280          */
1281         ad->rx_bulk_alloc_allowed = true;
1282         ad->rx_vec_allowed = true;
1283         ad->tx_simple_allowed = true;
1284         ad->tx_vec_allowed = true;
1285
1286         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1287                 ret = i40e_fdir_setup(pf);
1288                 if (ret != I40E_SUCCESS) {
1289                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1290                         return -ENOTSUP;
1291                 }
1292                 ret = i40e_fdir_configure(dev);
1293                 if (ret < 0) {
1294                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1295                         goto err;
1296                 }
1297         } else
1298                 i40e_fdir_teardown(pf);
1299
1300         ret = i40e_dev_init_vlan(dev);
1301         if (ret < 0)
1302                 goto err;
1303
1304         /* VMDQ setup.
1305          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1306          *  RSS setting have different requirements.
1307          *  General PMD driver call sequence are NIC init, configure,
1308          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1309          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1310          *  applicable. So, VMDQ setting has to be done before
1311          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1312          *  For RSS setting, it will try to calculate actual configured RX queue
1313          *  number, which will be available after rx_queue_setup(). dev_start()
1314          *  function is good to place RSS setup.
1315          */
1316         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1317                 ret = i40e_vmdq_setup(dev);
1318                 if (ret)
1319                         goto err;
1320         }
1321
1322         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1323                 ret = i40e_dcb_setup(dev);
1324                 if (ret) {
1325                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1326                         goto err_dcb;
1327                 }
1328         }
1329
1330         return 0;
1331
1332 err_dcb:
1333         /* need to release vmdq resource if exists */
1334         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1335                 i40e_vsi_release(pf->vmdq[i].vsi);
1336                 pf->vmdq[i].vsi = NULL;
1337         }
1338         rte_free(pf->vmdq);
1339         pf->vmdq = NULL;
1340 err:
1341         /* need to release fdir resource if exists */
1342         i40e_fdir_teardown(pf);
1343         return ret;
1344 }
1345
1346 void
1347 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1348 {
1349         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1350         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1351         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1352         uint16_t msix_vect = vsi->msix_intr;
1353         uint16_t i;
1354
1355         for (i = 0; i < vsi->nb_qps; i++) {
1356                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1357                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1358                 rte_wmb();
1359         }
1360
1361         if (vsi->type != I40E_VSI_SRIOV) {
1362                 if (!rte_intr_allow_others(intr_handle)) {
1363                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1364                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1365                         I40E_WRITE_REG(hw,
1366                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1367                                        0);
1368                 } else {
1369                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1370                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1371                         I40E_WRITE_REG(hw,
1372                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1373                                                        msix_vect - 1), 0);
1374                 }
1375         } else {
1376                 uint32_t reg;
1377                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1378                         vsi->user_param + (msix_vect - 1);
1379
1380                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1381                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1382         }
1383         I40E_WRITE_FLUSH(hw);
1384 }
1385
1386 static void
1387 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1388                        int base_queue, int nb_queue)
1389 {
1390         int i;
1391         uint32_t val;
1392         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1393
1394         /* Bind all RX queues to allocated MSIX interrupt */
1395         for (i = 0; i < nb_queue; i++) {
1396                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1397                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1398                         ((base_queue + i + 1) <<
1399                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1400                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1401                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1402
1403                 if (i == nb_queue - 1)
1404                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1405                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1406         }
1407
1408         /* Write first RX queue to Link list register as the head element */
1409         if (vsi->type != I40E_VSI_SRIOV) {
1410                 uint16_t interval =
1411                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1412
1413                 if (msix_vect == I40E_MISC_VEC_ID) {
1414                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1415                                        (base_queue <<
1416                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1417                                        (0x0 <<
1418                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1419                         I40E_WRITE_REG(hw,
1420                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1421                                        interval);
1422                 } else {
1423                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1424                                        (base_queue <<
1425                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1426                                        (0x0 <<
1427                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1428                         I40E_WRITE_REG(hw,
1429                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1430                                                        msix_vect - 1),
1431                                        interval);
1432                 }
1433         } else {
1434                 uint32_t reg;
1435
1436                 if (msix_vect == I40E_MISC_VEC_ID) {
1437                         I40E_WRITE_REG(hw,
1438                                        I40E_VPINT_LNKLST0(vsi->user_param),
1439                                        (base_queue <<
1440                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1441                                        (0x0 <<
1442                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1443                 } else {
1444                         /* num_msix_vectors_vf needs to minus irq0 */
1445                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1446                                 vsi->user_param + (msix_vect - 1);
1447
1448                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1449                                        (base_queue <<
1450                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1451                                        (0x0 <<
1452                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1453                 }
1454         }
1455
1456         I40E_WRITE_FLUSH(hw);
1457 }
1458
1459 void
1460 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1461 {
1462         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1463         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1464         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1465         uint16_t msix_vect = vsi->msix_intr;
1466         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1467         uint16_t queue_idx = 0;
1468         int record = 0;
1469         uint32_t val;
1470         int i;
1471
1472         for (i = 0; i < vsi->nb_qps; i++) {
1473                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1474                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1475         }
1476
1477         /* INTENA flag is not auto-cleared for interrupt */
1478         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1479         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1480                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1481                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1482         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1483
1484         /* VF bind interrupt */
1485         if (vsi->type == I40E_VSI_SRIOV) {
1486                 __vsi_queues_bind_intr(vsi, msix_vect,
1487                                        vsi->base_queue, vsi->nb_qps);
1488                 return;
1489         }
1490
1491         /* PF & VMDq bind interrupt */
1492         if (rte_intr_dp_is_en(intr_handle)) {
1493                 if (vsi->type == I40E_VSI_MAIN) {
1494                         queue_idx = 0;
1495                         record = 1;
1496                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1497                         struct i40e_vsi *main_vsi =
1498                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1499                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1500                         record = 1;
1501                 }
1502         }
1503
1504         for (i = 0; i < vsi->nb_used_qps; i++) {
1505                 if (nb_msix <= 1) {
1506                         if (!rte_intr_allow_others(intr_handle))
1507                                 /* allow to share MISC_VEC_ID */
1508                                 msix_vect = I40E_MISC_VEC_ID;
1509
1510                         /* no enough msix_vect, map all to one */
1511                         __vsi_queues_bind_intr(vsi, msix_vect,
1512                                                vsi->base_queue + i,
1513                                                vsi->nb_used_qps - i);
1514                         for (; !!record && i < vsi->nb_used_qps; i++)
1515                                 intr_handle->intr_vec[queue_idx + i] =
1516                                         msix_vect;
1517                         break;
1518                 }
1519                 /* 1:1 queue/msix_vect mapping */
1520                 __vsi_queues_bind_intr(vsi, msix_vect,
1521                                        vsi->base_queue + i, 1);
1522                 if (!!record)
1523                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1524
1525                 msix_vect++;
1526                 nb_msix--;
1527         }
1528 }
1529
1530 static void
1531 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1532 {
1533         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1534         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1535         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1536         uint16_t interval = i40e_calc_itr_interval(\
1537                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1538         uint16_t msix_intr, i;
1539
1540         if (rte_intr_allow_others(intr_handle))
1541                 for (i = 0; i < vsi->nb_msix; i++) {
1542                         msix_intr = vsi->msix_intr + i;
1543                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1544                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1545                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1546                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1547                                 (interval <<
1548                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1549                 }
1550         else
1551                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1552                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1553                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1554                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1555                                (interval <<
1556                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1557
1558         I40E_WRITE_FLUSH(hw);
1559 }
1560
1561 static void
1562 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1563 {
1564         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1565         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1566         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1567         uint16_t msix_intr, i;
1568
1569         if (rte_intr_allow_others(intr_handle))
1570                 for (i = 0; i < vsi->nb_msix; i++) {
1571                         msix_intr = vsi->msix_intr + i;
1572                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1573                                        0);
1574                 }
1575         else
1576                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1577
1578         I40E_WRITE_FLUSH(hw);
1579 }
1580
1581 static inline uint8_t
1582 i40e_parse_link_speeds(uint16_t link_speeds)
1583 {
1584         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1585
1586         if (link_speeds & ETH_LINK_SPEED_40G)
1587                 link_speed |= I40E_LINK_SPEED_40GB;
1588         if (link_speeds & ETH_LINK_SPEED_20G)
1589                 link_speed |= I40E_LINK_SPEED_20GB;
1590         if (link_speeds & ETH_LINK_SPEED_10G)
1591                 link_speed |= I40E_LINK_SPEED_10GB;
1592         if (link_speeds & ETH_LINK_SPEED_1G)
1593                 link_speed |= I40E_LINK_SPEED_1GB;
1594         if (link_speeds & ETH_LINK_SPEED_100M)
1595                 link_speed |= I40E_LINK_SPEED_100MB;
1596
1597         return link_speed;
1598 }
1599
1600 static int
1601 i40e_phy_conf_link(struct i40e_hw *hw,
1602                    uint8_t abilities,
1603                    uint8_t force_speed)
1604 {
1605         enum i40e_status_code status;
1606         struct i40e_aq_get_phy_abilities_resp phy_ab;
1607         struct i40e_aq_set_phy_config phy_conf;
1608         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1609                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1610                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1611                         I40E_AQ_PHY_FLAG_LOW_POWER;
1612         const uint8_t advt = I40E_LINK_SPEED_40GB |
1613                         I40E_LINK_SPEED_10GB |
1614                         I40E_LINK_SPEED_1GB |
1615                         I40E_LINK_SPEED_100MB;
1616         int ret = -ENOTSUP;
1617
1618
1619         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1620                                               NULL);
1621         if (status)
1622                 return ret;
1623
1624         memset(&phy_conf, 0, sizeof(phy_conf));
1625
1626         /* bits 0-2 use the values from get_phy_abilities_resp */
1627         abilities &= ~mask;
1628         abilities |= phy_ab.abilities & mask;
1629
1630         /* update ablities and speed */
1631         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1632                 phy_conf.link_speed = advt;
1633         else
1634                 phy_conf.link_speed = force_speed;
1635
1636         phy_conf.abilities = abilities;
1637
1638         /* use get_phy_abilities_resp value for the rest */
1639         phy_conf.phy_type = phy_ab.phy_type;
1640         phy_conf.eee_capability = phy_ab.eee_capability;
1641         phy_conf.eeer = phy_ab.eeer_val;
1642         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1643
1644         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1645                     phy_ab.abilities, phy_ab.link_speed);
1646         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1647                     phy_conf.abilities, phy_conf.link_speed);
1648
1649         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1650         if (status)
1651                 return ret;
1652
1653         return I40E_SUCCESS;
1654 }
1655
1656 static int
1657 i40e_apply_link_speed(struct rte_eth_dev *dev)
1658 {
1659         uint8_t speed;
1660         uint8_t abilities = 0;
1661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662         struct rte_eth_conf *conf = &dev->data->dev_conf;
1663
1664         speed = i40e_parse_link_speeds(conf->link_speeds);
1665         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1666         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1667                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1668         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1669
1670         /* Skip changing speed on 40G interfaces, FW does not support */
1671         if (i40e_is_40G_device(hw->device_id)) {
1672                 speed =  I40E_LINK_SPEED_UNKNOWN;
1673                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1674         }
1675
1676         return i40e_phy_conf_link(hw, abilities, speed);
1677 }
1678
1679 static int
1680 i40e_dev_start(struct rte_eth_dev *dev)
1681 {
1682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         struct i40e_vsi *main_vsi = pf->main_vsi;
1685         int ret, i;
1686         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1687         uint32_t intr_vector = 0;
1688
1689         hw->adapter_stopped = 0;
1690
1691         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1692                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1693                              dev->data->port_id);
1694                 return -EINVAL;
1695         }
1696
1697         rte_intr_disable(intr_handle);
1698
1699         if ((rte_intr_cap_multiple(intr_handle) ||
1700              !RTE_ETH_DEV_SRIOV(dev).active) &&
1701             dev->data->dev_conf.intr_conf.rxq != 0) {
1702                 intr_vector = dev->data->nb_rx_queues;
1703                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1704                         return -1;
1705         }
1706
1707         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1708                 intr_handle->intr_vec =
1709                         rte_zmalloc("intr_vec",
1710                                     dev->data->nb_rx_queues * sizeof(int),
1711                                     0);
1712                 if (!intr_handle->intr_vec) {
1713                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1714                                      " intr_vec\n", dev->data->nb_rx_queues);
1715                         return -ENOMEM;
1716                 }
1717         }
1718
1719         /* Initialize VSI */
1720         ret = i40e_dev_rxtx_init(pf);
1721         if (ret != I40E_SUCCESS) {
1722                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1723                 goto err_up;
1724         }
1725
1726         /* Map queues with MSIX interrupt */
1727         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1728                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1729         i40e_vsi_queues_bind_intr(main_vsi);
1730         i40e_vsi_enable_queues_intr(main_vsi);
1731
1732         /* Map VMDQ VSI queues with MSIX interrupt */
1733         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1734                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1735                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1736                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1737         }
1738
1739         /* enable FDIR MSIX interrupt */
1740         if (pf->fdir.fdir_vsi) {
1741                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1742                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1743         }
1744
1745         /* Enable all queues which have been configured */
1746         ret = i40e_dev_switch_queues(pf, TRUE);
1747         if (ret != I40E_SUCCESS) {
1748                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1749                 goto err_up;
1750         }
1751
1752         /* Enable receiving broadcast packets */
1753         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1754         if (ret != I40E_SUCCESS)
1755                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1756
1757         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1758                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1759                                                 true, NULL);
1760                 if (ret != I40E_SUCCESS)
1761                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1762         }
1763
1764         /* Apply link configure */
1765         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1766                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1767                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1768                 PMD_DRV_LOG(ERR, "Invalid link setting");
1769                 goto err_up;
1770         }
1771         ret = i40e_apply_link_speed(dev);
1772         if (I40E_SUCCESS != ret) {
1773                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1774                 goto err_up;
1775         }
1776
1777         if (!rte_intr_allow_others(intr_handle)) {
1778                 rte_intr_callback_unregister(intr_handle,
1779                                              i40e_dev_interrupt_handler,
1780                                              (void *)dev);
1781                 /* configure and enable device interrupt */
1782                 i40e_pf_config_irq0(hw, FALSE);
1783                 i40e_pf_enable_irq0(hw);
1784
1785                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1786                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1787                                      " no intr multiplex\n");
1788         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1789                 ret = i40e_aq_set_phy_int_mask(hw,
1790                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1791                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1792                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1793                 if (ret != I40E_SUCCESS)
1794                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1795
1796                 /* Call get_link_info aq commond to enable LSE */
1797                 i40e_dev_link_update(dev, 0);
1798         }
1799
1800         /* enable uio intr after callback register */
1801         rte_intr_enable(intr_handle);
1802
1803         return I40E_SUCCESS;
1804
1805 err_up:
1806         i40e_dev_switch_queues(pf, FALSE);
1807         i40e_dev_clear_queues(dev);
1808
1809         return ret;
1810 }
1811
1812 static void
1813 i40e_dev_stop(struct rte_eth_dev *dev)
1814 {
1815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1816         struct i40e_vsi *main_vsi = pf->main_vsi;
1817         struct i40e_mirror_rule *p_mirror;
1818         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1819         int i;
1820
1821         /* Disable all queues */
1822         i40e_dev_switch_queues(pf, FALSE);
1823
1824         /* un-map queues with interrupt registers */
1825         i40e_vsi_disable_queues_intr(main_vsi);
1826         i40e_vsi_queues_unbind_intr(main_vsi);
1827
1828         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1829                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1830                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1831         }
1832
1833         if (pf->fdir.fdir_vsi) {
1834                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1835                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1836         }
1837         /* Clear all queues and release memory */
1838         i40e_dev_clear_queues(dev);
1839
1840         /* Set link down */
1841         i40e_dev_set_link_down(dev);
1842
1843         /* Remove all mirror rules */
1844         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1845                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1846                 rte_free(p_mirror);
1847         }
1848         pf->nb_mirror_rule = 0;
1849
1850         if (!rte_intr_allow_others(intr_handle))
1851                 /* resume to the default handler */
1852                 rte_intr_callback_register(intr_handle,
1853                                            i40e_dev_interrupt_handler,
1854                                            (void *)dev);
1855
1856         /* Clean datapath event and queue/vec mapping */
1857         rte_intr_efd_disable(intr_handle);
1858         if (intr_handle->intr_vec) {
1859                 rte_free(intr_handle->intr_vec);
1860                 intr_handle->intr_vec = NULL;
1861         }
1862 }
1863
1864 static void
1865 i40e_dev_close(struct rte_eth_dev *dev)
1866 {
1867         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1869         uint32_t reg;
1870         int i;
1871
1872         PMD_INIT_FUNC_TRACE();
1873
1874         i40e_dev_stop(dev);
1875         hw->adapter_stopped = 1;
1876         i40e_dev_free_queues(dev);
1877
1878         /* Disable interrupt */
1879         i40e_pf_disable_irq0(hw);
1880         rte_intr_disable(&(dev->pci_dev->intr_handle));
1881
1882         /* shutdown and destroy the HMC */
1883         i40e_shutdown_lan_hmc(hw);
1884
1885         /* release all the existing VSIs and VEBs */
1886         i40e_fdir_teardown(pf);
1887         i40e_vsi_release(pf->main_vsi);
1888
1889         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1890                 i40e_vsi_release(pf->vmdq[i].vsi);
1891                 pf->vmdq[i].vsi = NULL;
1892         }
1893
1894         rte_free(pf->vmdq);
1895         pf->vmdq = NULL;
1896
1897         /* shutdown the adminq */
1898         i40e_aq_queue_shutdown(hw, true);
1899         i40e_shutdown_adminq(hw);
1900
1901         i40e_res_pool_destroy(&pf->qp_pool);
1902         i40e_res_pool_destroy(&pf->msix_pool);
1903
1904         /* force a PF reset to clean anything leftover */
1905         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1906         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1907                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1908         I40E_WRITE_FLUSH(hw);
1909 }
1910
1911 static void
1912 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1913 {
1914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         struct i40e_vsi *vsi = pf->main_vsi;
1917         int status;
1918
1919         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1920                                                      true, NULL, true);
1921         if (status != I40E_SUCCESS)
1922                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1923
1924         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1925                                                         TRUE, NULL);
1926         if (status != I40E_SUCCESS)
1927                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1928
1929 }
1930
1931 static void
1932 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1933 {
1934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1936         struct i40e_vsi *vsi = pf->main_vsi;
1937         int status;
1938
1939         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1940                                                      false, NULL, true);
1941         if (status != I40E_SUCCESS)
1942                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1943
1944         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1945                                                         false, NULL);
1946         if (status != I40E_SUCCESS)
1947                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1948 }
1949
1950 static void
1951 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1952 {
1953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1954         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955         struct i40e_vsi *vsi = pf->main_vsi;
1956         int ret;
1957
1958         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1959         if (ret != I40E_SUCCESS)
1960                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1961 }
1962
1963 static void
1964 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1965 {
1966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1967         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1968         struct i40e_vsi *vsi = pf->main_vsi;
1969         int ret;
1970
1971         if (dev->data->promiscuous == 1)
1972                 return; /* must remain in all_multicast mode */
1973
1974         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1975                                 vsi->seid, FALSE, NULL);
1976         if (ret != I40E_SUCCESS)
1977                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1978 }
1979
1980 /*
1981  * Set device link up.
1982  */
1983 static int
1984 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1985 {
1986         /* re-apply link speed setting */
1987         return i40e_apply_link_speed(dev);
1988 }
1989
1990 /*
1991  * Set device link down.
1992  */
1993 static int
1994 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1995 {
1996         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1997         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999
2000         return i40e_phy_conf_link(hw, abilities, speed);
2001 }
2002
2003 int
2004 i40e_dev_link_update(struct rte_eth_dev *dev,
2005                      int wait_to_complete)
2006 {
2007 #define CHECK_INTERVAL 100  /* 100ms */
2008 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2009         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010         struct i40e_link_status link_status;
2011         struct rte_eth_link link, old;
2012         int status;
2013         unsigned rep_cnt = MAX_REPEAT_TIME;
2014         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2015
2016         memset(&link, 0, sizeof(link));
2017         memset(&old, 0, sizeof(old));
2018         memset(&link_status, 0, sizeof(link_status));
2019         rte_i40e_dev_atomic_read_link_status(dev, &old);
2020
2021         do {
2022                 /* Get link status information from hardware */
2023                 status = i40e_aq_get_link_info(hw, enable_lse,
2024                                                 &link_status, NULL);
2025                 if (status != I40E_SUCCESS) {
2026                         link.link_speed = ETH_SPEED_NUM_100M;
2027                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2028                         PMD_DRV_LOG(ERR, "Failed to get link info");
2029                         goto out;
2030                 }
2031
2032                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2033                 if (!wait_to_complete)
2034                         break;
2035
2036                 rte_delay_ms(CHECK_INTERVAL);
2037         } while (!link.link_status && rep_cnt--);
2038
2039         if (!link.link_status)
2040                 goto out;
2041
2042         /* i40e uses full duplex only */
2043         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2044
2045         /* Parse the link status */
2046         switch (link_status.link_speed) {
2047         case I40E_LINK_SPEED_100MB:
2048                 link.link_speed = ETH_SPEED_NUM_100M;
2049                 break;
2050         case I40E_LINK_SPEED_1GB:
2051                 link.link_speed = ETH_SPEED_NUM_1G;
2052                 break;
2053         case I40E_LINK_SPEED_10GB:
2054                 link.link_speed = ETH_SPEED_NUM_10G;
2055                 break;
2056         case I40E_LINK_SPEED_20GB:
2057                 link.link_speed = ETH_SPEED_NUM_20G;
2058                 break;
2059         case I40E_LINK_SPEED_40GB:
2060                 link.link_speed = ETH_SPEED_NUM_40G;
2061                 break;
2062         default:
2063                 link.link_speed = ETH_SPEED_NUM_100M;
2064                 break;
2065         }
2066
2067         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2068                         ETH_LINK_SPEED_FIXED);
2069
2070 out:
2071         rte_i40e_dev_atomic_write_link_status(dev, &link);
2072         if (link.link_status == old.link_status)
2073                 return -1;
2074
2075         return 0;
2076 }
2077
2078 /* Get all the statistics of a VSI */
2079 void
2080 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2081 {
2082         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2083         struct i40e_eth_stats *nes = &vsi->eth_stats;
2084         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2085         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2086
2087         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2088                             vsi->offset_loaded, &oes->rx_bytes,
2089                             &nes->rx_bytes);
2090         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2091                             vsi->offset_loaded, &oes->rx_unicast,
2092                             &nes->rx_unicast);
2093         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2094                             vsi->offset_loaded, &oes->rx_multicast,
2095                             &nes->rx_multicast);
2096         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2097                             vsi->offset_loaded, &oes->rx_broadcast,
2098                             &nes->rx_broadcast);
2099         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2100                             &oes->rx_discards, &nes->rx_discards);
2101         /* GLV_REPC not supported */
2102         /* GLV_RMPC not supported */
2103         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2104                             &oes->rx_unknown_protocol,
2105                             &nes->rx_unknown_protocol);
2106         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2107                             vsi->offset_loaded, &oes->tx_bytes,
2108                             &nes->tx_bytes);
2109         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2110                             vsi->offset_loaded, &oes->tx_unicast,
2111                             &nes->tx_unicast);
2112         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2113                             vsi->offset_loaded, &oes->tx_multicast,
2114                             &nes->tx_multicast);
2115         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2116                             vsi->offset_loaded,  &oes->tx_broadcast,
2117                             &nes->tx_broadcast);
2118         /* GLV_TDPC not supported */
2119         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2120                             &oes->tx_errors, &nes->tx_errors);
2121         vsi->offset_loaded = true;
2122
2123         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2124                     vsi->vsi_id);
2125         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2126         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2127         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2128         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2129         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2130         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2131                     nes->rx_unknown_protocol);
2132         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2133         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2134         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2135         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2136         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2137         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2138         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2139                     vsi->vsi_id);
2140 }
2141
2142 static void
2143 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2144 {
2145         unsigned int i;
2146         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2147         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2148
2149         /* Get statistics of struct i40e_eth_stats */
2150         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2151                             I40E_GLPRT_GORCL(hw->port),
2152                             pf->offset_loaded, &os->eth.rx_bytes,
2153                             &ns->eth.rx_bytes);
2154         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2155                             I40E_GLPRT_UPRCL(hw->port),
2156                             pf->offset_loaded, &os->eth.rx_unicast,
2157                             &ns->eth.rx_unicast);
2158         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2159                             I40E_GLPRT_MPRCL(hw->port),
2160                             pf->offset_loaded, &os->eth.rx_multicast,
2161                             &ns->eth.rx_multicast);
2162         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2163                             I40E_GLPRT_BPRCL(hw->port),
2164                             pf->offset_loaded, &os->eth.rx_broadcast,
2165                             &ns->eth.rx_broadcast);
2166         /* Workaround: CRC size should not be included in byte statistics,
2167          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2168          */
2169         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2170                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2171
2172         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2173                             pf->offset_loaded, &os->eth.rx_discards,
2174                             &ns->eth.rx_discards);
2175         /* GLPRT_REPC not supported */
2176         /* GLPRT_RMPC not supported */
2177         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2178                             pf->offset_loaded,
2179                             &os->eth.rx_unknown_protocol,
2180                             &ns->eth.rx_unknown_protocol);
2181         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2182                             I40E_GLPRT_GOTCL(hw->port),
2183                             pf->offset_loaded, &os->eth.tx_bytes,
2184                             &ns->eth.tx_bytes);
2185         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2186                             I40E_GLPRT_UPTCL(hw->port),
2187                             pf->offset_loaded, &os->eth.tx_unicast,
2188                             &ns->eth.tx_unicast);
2189         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2190                             I40E_GLPRT_MPTCL(hw->port),
2191                             pf->offset_loaded, &os->eth.tx_multicast,
2192                             &ns->eth.tx_multicast);
2193         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2194                             I40E_GLPRT_BPTCL(hw->port),
2195                             pf->offset_loaded, &os->eth.tx_broadcast,
2196                             &ns->eth.tx_broadcast);
2197         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2198                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2199         /* GLPRT_TEPC not supported */
2200
2201         /* additional port specific stats */
2202         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2203                             pf->offset_loaded, &os->tx_dropped_link_down,
2204                             &ns->tx_dropped_link_down);
2205         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2206                             pf->offset_loaded, &os->crc_errors,
2207                             &ns->crc_errors);
2208         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2209                             pf->offset_loaded, &os->illegal_bytes,
2210                             &ns->illegal_bytes);
2211         /* GLPRT_ERRBC not supported */
2212         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2213                             pf->offset_loaded, &os->mac_local_faults,
2214                             &ns->mac_local_faults);
2215         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2216                             pf->offset_loaded, &os->mac_remote_faults,
2217                             &ns->mac_remote_faults);
2218         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2219                             pf->offset_loaded, &os->rx_length_errors,
2220                             &ns->rx_length_errors);
2221         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2222                             pf->offset_loaded, &os->link_xon_rx,
2223                             &ns->link_xon_rx);
2224         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2225                             pf->offset_loaded, &os->link_xoff_rx,
2226                             &ns->link_xoff_rx);
2227         for (i = 0; i < 8; i++) {
2228                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2229                                     pf->offset_loaded,
2230                                     &os->priority_xon_rx[i],
2231                                     &ns->priority_xon_rx[i]);
2232                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2233                                     pf->offset_loaded,
2234                                     &os->priority_xoff_rx[i],
2235                                     &ns->priority_xoff_rx[i]);
2236         }
2237         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2238                             pf->offset_loaded, &os->link_xon_tx,
2239                             &ns->link_xon_tx);
2240         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2241                             pf->offset_loaded, &os->link_xoff_tx,
2242                             &ns->link_xoff_tx);
2243         for (i = 0; i < 8; i++) {
2244                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2245                                     pf->offset_loaded,
2246                                     &os->priority_xon_tx[i],
2247                                     &ns->priority_xon_tx[i]);
2248                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2249                                     pf->offset_loaded,
2250                                     &os->priority_xoff_tx[i],
2251                                     &ns->priority_xoff_tx[i]);
2252                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2253                                     pf->offset_loaded,
2254                                     &os->priority_xon_2_xoff[i],
2255                                     &ns->priority_xon_2_xoff[i]);
2256         }
2257         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2258                             I40E_GLPRT_PRC64L(hw->port),
2259                             pf->offset_loaded, &os->rx_size_64,
2260                             &ns->rx_size_64);
2261         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2262                             I40E_GLPRT_PRC127L(hw->port),
2263                             pf->offset_loaded, &os->rx_size_127,
2264                             &ns->rx_size_127);
2265         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2266                             I40E_GLPRT_PRC255L(hw->port),
2267                             pf->offset_loaded, &os->rx_size_255,
2268                             &ns->rx_size_255);
2269         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2270                             I40E_GLPRT_PRC511L(hw->port),
2271                             pf->offset_loaded, &os->rx_size_511,
2272                             &ns->rx_size_511);
2273         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2274                             I40E_GLPRT_PRC1023L(hw->port),
2275                             pf->offset_loaded, &os->rx_size_1023,
2276                             &ns->rx_size_1023);
2277         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2278                             I40E_GLPRT_PRC1522L(hw->port),
2279                             pf->offset_loaded, &os->rx_size_1522,
2280                             &ns->rx_size_1522);
2281         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2282                             I40E_GLPRT_PRC9522L(hw->port),
2283                             pf->offset_loaded, &os->rx_size_big,
2284                             &ns->rx_size_big);
2285         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2286                             pf->offset_loaded, &os->rx_undersize,
2287                             &ns->rx_undersize);
2288         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2289                             pf->offset_loaded, &os->rx_fragments,
2290                             &ns->rx_fragments);
2291         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2292                             pf->offset_loaded, &os->rx_oversize,
2293                             &ns->rx_oversize);
2294         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2295                             pf->offset_loaded, &os->rx_jabber,
2296                             &ns->rx_jabber);
2297         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2298                             I40E_GLPRT_PTC64L(hw->port),
2299                             pf->offset_loaded, &os->tx_size_64,
2300                             &ns->tx_size_64);
2301         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2302                             I40E_GLPRT_PTC127L(hw->port),
2303                             pf->offset_loaded, &os->tx_size_127,
2304                             &ns->tx_size_127);
2305         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2306                             I40E_GLPRT_PTC255L(hw->port),
2307                             pf->offset_loaded, &os->tx_size_255,
2308                             &ns->tx_size_255);
2309         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2310                             I40E_GLPRT_PTC511L(hw->port),
2311                             pf->offset_loaded, &os->tx_size_511,
2312                             &ns->tx_size_511);
2313         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2314                             I40E_GLPRT_PTC1023L(hw->port),
2315                             pf->offset_loaded, &os->tx_size_1023,
2316                             &ns->tx_size_1023);
2317         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2318                             I40E_GLPRT_PTC1522L(hw->port),
2319                             pf->offset_loaded, &os->tx_size_1522,
2320                             &ns->tx_size_1522);
2321         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2322                             I40E_GLPRT_PTC9522L(hw->port),
2323                             pf->offset_loaded, &os->tx_size_big,
2324                             &ns->tx_size_big);
2325         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2326                            pf->offset_loaded,
2327                            &os->fd_sb_match, &ns->fd_sb_match);
2328         /* GLPRT_MSPDC not supported */
2329         /* GLPRT_XEC not supported */
2330
2331         pf->offset_loaded = true;
2332
2333         if (pf->main_vsi)
2334                 i40e_update_vsi_stats(pf->main_vsi);
2335 }
2336
2337 /* Get all statistics of a port */
2338 static void
2339 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2340 {
2341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2344         unsigned i;
2345
2346         /* call read registers - updates values, now write them to struct */
2347         i40e_read_stats_registers(pf, hw);
2348
2349         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2350                         pf->main_vsi->eth_stats.rx_multicast +
2351                         pf->main_vsi->eth_stats.rx_broadcast -
2352                         pf->main_vsi->eth_stats.rx_discards;
2353         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2354                         pf->main_vsi->eth_stats.tx_multicast +
2355                         pf->main_vsi->eth_stats.tx_broadcast;
2356         stats->ibytes   = ns->eth.rx_bytes;
2357         stats->obytes   = ns->eth.tx_bytes;
2358         stats->oerrors  = ns->eth.tx_errors +
2359                         pf->main_vsi->eth_stats.tx_errors;
2360
2361         /* Rx Errors */
2362         stats->imissed  = ns->eth.rx_discards +
2363                         pf->main_vsi->eth_stats.rx_discards;
2364         stats->ierrors  = ns->crc_errors +
2365                         ns->rx_length_errors + ns->rx_undersize +
2366                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2367
2368         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2369         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2370         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2371         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2372         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2373         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2374         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2375                     ns->eth.rx_unknown_protocol);
2376         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2377         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2378         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2379         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2380         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2381         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2382
2383         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2384                     ns->tx_dropped_link_down);
2385         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2386         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2387                     ns->illegal_bytes);
2388         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2389         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2390                     ns->mac_local_faults);
2391         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2392                     ns->mac_remote_faults);
2393         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2394                     ns->rx_length_errors);
2395         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2396         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2397         for (i = 0; i < 8; i++) {
2398                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2399                                 i, ns->priority_xon_rx[i]);
2400                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2401                                 i, ns->priority_xoff_rx[i]);
2402         }
2403         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2404         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2405         for (i = 0; i < 8; i++) {
2406                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2407                                 i, ns->priority_xon_tx[i]);
2408                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2409                                 i, ns->priority_xoff_tx[i]);
2410                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2411                                 i, ns->priority_xon_2_xoff[i]);
2412         }
2413         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2414         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2415         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2416         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2417         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2418         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2419         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2420         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2421         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2422         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2423         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2424         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2425         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2426         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2427         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2428         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2429         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2430         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2431         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2432                         ns->mac_short_packet_dropped);
2433         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2434                     ns->checksum_error);
2435         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2436         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2437 }
2438
2439 /* Reset the statistics */
2440 static void
2441 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2442 {
2443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2444         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445
2446         /* Mark PF and VSI stats to update the offset, aka "reset" */
2447         pf->offset_loaded = false;
2448         if (pf->main_vsi)
2449                 pf->main_vsi->offset_loaded = false;
2450
2451         /* read the stats, reading current register values into offset */
2452         i40e_read_stats_registers(pf, hw);
2453 }
2454
2455 static uint32_t
2456 i40e_xstats_calc_num(void)
2457 {
2458         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2459                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2460                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2461 }
2462
2463 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2464                                      struct rte_eth_xstat_name *xstats_names,
2465                                      __rte_unused unsigned limit)
2466 {
2467         unsigned count = 0;
2468         unsigned i, prio;
2469
2470         if (xstats_names == NULL)
2471                 return i40e_xstats_calc_num();
2472
2473         /* Note: limit checked in rte_eth_xstats_names() */
2474
2475         /* Get stats from i40e_eth_stats struct */
2476         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2477                 snprintf(xstats_names[count].name,
2478                          sizeof(xstats_names[count].name),
2479                          "%s", rte_i40e_stats_strings[i].name);
2480                 count++;
2481         }
2482
2483         /* Get individiual stats from i40e_hw_port struct */
2484         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2485                 snprintf(xstats_names[count].name,
2486                         sizeof(xstats_names[count].name),
2487                          "%s", rte_i40e_hw_port_strings[i].name);
2488                 count++;
2489         }
2490
2491         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2492                 for (prio = 0; prio < 8; prio++) {
2493                         snprintf(xstats_names[count].name,
2494                                  sizeof(xstats_names[count].name),
2495                                  "rx_priority%u_%s", prio,
2496                                  rte_i40e_rxq_prio_strings[i].name);
2497                         count++;
2498                 }
2499         }
2500
2501         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2502                 for (prio = 0; prio < 8; prio++) {
2503                         snprintf(xstats_names[count].name,
2504                                  sizeof(xstats_names[count].name),
2505                                  "tx_priority%u_%s", prio,
2506                                  rte_i40e_txq_prio_strings[i].name);
2507                         count++;
2508                 }
2509         }
2510         return count;
2511 }
2512
2513 static int
2514 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2515                     unsigned n)
2516 {
2517         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2518         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519         unsigned i, count, prio;
2520         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2521
2522         count = i40e_xstats_calc_num();
2523         if (n < count)
2524                 return count;
2525
2526         i40e_read_stats_registers(pf, hw);
2527
2528         if (xstats == NULL)
2529                 return 0;
2530
2531         count = 0;
2532
2533         /* Get stats from i40e_eth_stats struct */
2534         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2535                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2536                         rte_i40e_stats_strings[i].offset);
2537                 count++;
2538         }
2539
2540         /* Get individiual stats from i40e_hw_port struct */
2541         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2542                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2543                         rte_i40e_hw_port_strings[i].offset);
2544                 count++;
2545         }
2546
2547         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2548                 for (prio = 0; prio < 8; prio++) {
2549                         xstats[count].value =
2550                                 *(uint64_t *)(((char *)hw_stats) +
2551                                 rte_i40e_rxq_prio_strings[i].offset +
2552                                 (sizeof(uint64_t) * prio));
2553                         count++;
2554                 }
2555         }
2556
2557         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2558                 for (prio = 0; prio < 8; prio++) {
2559                         xstats[count].value =
2560                                 *(uint64_t *)(((char *)hw_stats) +
2561                                 rte_i40e_txq_prio_strings[i].offset +
2562                                 (sizeof(uint64_t) * prio));
2563                         count++;
2564                 }
2565         }
2566
2567         return count;
2568 }
2569
2570 static int
2571 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2572                                  __rte_unused uint16_t queue_id,
2573                                  __rte_unused uint8_t stat_idx,
2574                                  __rte_unused uint8_t is_rx)
2575 {
2576         PMD_INIT_FUNC_TRACE();
2577
2578         return -ENOSYS;
2579 }
2580
2581 static void
2582 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2583 {
2584         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586         struct i40e_vsi *vsi = pf->main_vsi;
2587
2588         dev_info->max_rx_queues = vsi->nb_qps;
2589         dev_info->max_tx_queues = vsi->nb_qps;
2590         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2591         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2592         dev_info->max_mac_addrs = vsi->max_macaddrs;
2593         dev_info->max_vfs = dev->pci_dev->max_vfs;
2594         dev_info->rx_offload_capa =
2595                 DEV_RX_OFFLOAD_VLAN_STRIP |
2596                 DEV_RX_OFFLOAD_QINQ_STRIP |
2597                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2598                 DEV_RX_OFFLOAD_UDP_CKSUM |
2599                 DEV_RX_OFFLOAD_TCP_CKSUM;
2600         dev_info->tx_offload_capa =
2601                 DEV_TX_OFFLOAD_VLAN_INSERT |
2602                 DEV_TX_OFFLOAD_QINQ_INSERT |
2603                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2604                 DEV_TX_OFFLOAD_UDP_CKSUM |
2605                 DEV_TX_OFFLOAD_TCP_CKSUM |
2606                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2607                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2608                 DEV_TX_OFFLOAD_TCP_TSO;
2609         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2610                                                 sizeof(uint32_t);
2611         dev_info->reta_size = pf->hash_lut_size;
2612         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2613
2614         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2615                 .rx_thresh = {
2616                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2617                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2618                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2619                 },
2620                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2621                 .rx_drop_en = 0,
2622         };
2623
2624         dev_info->default_txconf = (struct rte_eth_txconf) {
2625                 .tx_thresh = {
2626                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2627                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2628                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2629                 },
2630                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2631                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2632                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2633                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2634         };
2635
2636         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2637                 .nb_max = I40E_MAX_RING_DESC,
2638                 .nb_min = I40E_MIN_RING_DESC,
2639                 .nb_align = I40E_ALIGN_RING_DESC,
2640         };
2641
2642         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2643                 .nb_max = I40E_MAX_RING_DESC,
2644                 .nb_min = I40E_MIN_RING_DESC,
2645                 .nb_align = I40E_ALIGN_RING_DESC,
2646         };
2647
2648         if (pf->flags & I40E_FLAG_VMDQ) {
2649                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2650                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2651                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2652                                                 pf->max_nb_vmdq_vsi;
2653                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2654                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2655                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2656         }
2657
2658         if (i40e_is_40G_device(hw->device_id))
2659                 /* For XL710 */
2660                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2661         else
2662                 /* For X710 */
2663                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2664 }
2665
2666 static int
2667 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2668 {
2669         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2670         struct i40e_vsi *vsi = pf->main_vsi;
2671         PMD_INIT_FUNC_TRACE();
2672
2673         if (on)
2674                 return i40e_vsi_add_vlan(vsi, vlan_id);
2675         else
2676                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2677 }
2678
2679 static int
2680 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2681                    enum rte_vlan_type vlan_type,
2682                    uint16_t tpid)
2683 {
2684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2685         uint64_t reg_r = 0, reg_w = 0;
2686         uint16_t reg_id = 0;
2687         int ret = 0;
2688         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2689
2690         switch (vlan_type) {
2691         case ETH_VLAN_TYPE_OUTER:
2692                 if (qinq)
2693                         reg_id = 2;
2694                 else
2695                         reg_id = 3;
2696                 break;
2697         case ETH_VLAN_TYPE_INNER:
2698                 if (qinq)
2699                         reg_id = 3;
2700                 else {
2701                         ret = -EINVAL;
2702                         PMD_DRV_LOG(ERR,
2703                                 "Unsupported vlan type in single vlan.\n");
2704                         return ret;
2705                 }
2706                 break;
2707         default:
2708                 ret = -EINVAL;
2709                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2710                 return ret;
2711         }
2712         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2713                                           &reg_r, NULL);
2714         if (ret != I40E_SUCCESS) {
2715                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2716                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2717                 ret = -EIO;
2718                 return ret;
2719         }
2720         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2721                     "0x%08"PRIx64"", reg_id, reg_r);
2722
2723         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2724         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2725         if (reg_r == reg_w) {
2726                 ret = 0;
2727                 PMD_DRV_LOG(DEBUG, "No need to write");
2728                 return ret;
2729         }
2730
2731         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2732                                            reg_w, NULL);
2733         if (ret != I40E_SUCCESS) {
2734                 ret = -EIO;
2735                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2736                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2737                 return ret;
2738         }
2739         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2740                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2741
2742         return ret;
2743 }
2744
2745 static void
2746 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2747 {
2748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2749         struct i40e_vsi *vsi = pf->main_vsi;
2750
2751         if (mask & ETH_VLAN_FILTER_MASK) {
2752                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2753                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2754                 else
2755                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2756         }
2757
2758         if (mask & ETH_VLAN_STRIP_MASK) {
2759                 /* Enable or disable VLAN stripping */
2760                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2761                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2762                 else
2763                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2764         }
2765
2766         if (mask & ETH_VLAN_EXTEND_MASK) {
2767                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2768                         i40e_vsi_config_double_vlan(vsi, TRUE);
2769                         /* Set global registers with default ether type value */
2770                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2771                                            ETHER_TYPE_VLAN);
2772                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2773                                            ETHER_TYPE_VLAN);
2774                 }
2775                 else
2776                         i40e_vsi_config_double_vlan(vsi, FALSE);
2777         }
2778 }
2779
2780 static void
2781 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2782                           __rte_unused uint16_t queue,
2783                           __rte_unused int on)
2784 {
2785         PMD_INIT_FUNC_TRACE();
2786 }
2787
2788 static int
2789 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2790 {
2791         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2792         struct i40e_vsi *vsi = pf->main_vsi;
2793         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2794         struct i40e_vsi_vlan_pvid_info info;
2795
2796         memset(&info, 0, sizeof(info));
2797         info.on = on;
2798         if (info.on)
2799                 info.config.pvid = pvid;
2800         else {
2801                 info.config.reject.tagged =
2802                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2803                 info.config.reject.untagged =
2804                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2805         }
2806
2807         return i40e_vsi_vlan_pvid_set(vsi, &info);
2808 }
2809
2810 static int
2811 i40e_dev_led_on(struct rte_eth_dev *dev)
2812 {
2813         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814         uint32_t mode = i40e_led_get(hw);
2815
2816         if (mode == 0)
2817                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2818
2819         return 0;
2820 }
2821
2822 static int
2823 i40e_dev_led_off(struct rte_eth_dev *dev)
2824 {
2825         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826         uint32_t mode = i40e_led_get(hw);
2827
2828         if (mode != 0)
2829                 i40e_led_set(hw, 0, false);
2830
2831         return 0;
2832 }
2833
2834 static int
2835 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2836 {
2837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2838         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2839
2840         fc_conf->pause_time = pf->fc_conf.pause_time;
2841         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2842         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2843
2844          /* Return current mode according to actual setting*/
2845         switch (hw->fc.current_mode) {
2846         case I40E_FC_FULL:
2847                 fc_conf->mode = RTE_FC_FULL;
2848                 break;
2849         case I40E_FC_TX_PAUSE:
2850                 fc_conf->mode = RTE_FC_TX_PAUSE;
2851                 break;
2852         case I40E_FC_RX_PAUSE:
2853                 fc_conf->mode = RTE_FC_RX_PAUSE;
2854                 break;
2855         case I40E_FC_NONE:
2856         default:
2857                 fc_conf->mode = RTE_FC_NONE;
2858         };
2859
2860         return 0;
2861 }
2862
2863 static int
2864 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2865 {
2866         uint32_t mflcn_reg, fctrl_reg, reg;
2867         uint32_t max_high_water;
2868         uint8_t i, aq_failure;
2869         int err;
2870         struct i40e_hw *hw;
2871         struct i40e_pf *pf;
2872         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2873                 [RTE_FC_NONE] = I40E_FC_NONE,
2874                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2875                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2876                 [RTE_FC_FULL] = I40E_FC_FULL
2877         };
2878
2879         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2880
2881         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2882         if ((fc_conf->high_water > max_high_water) ||
2883                         (fc_conf->high_water < fc_conf->low_water)) {
2884                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2885                         "High_water must <= %d.", max_high_water);
2886                 return -EINVAL;
2887         }
2888
2889         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2891         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2892
2893         pf->fc_conf.pause_time = fc_conf->pause_time;
2894         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2895         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2896
2897         PMD_INIT_FUNC_TRACE();
2898
2899         /* All the link flow control related enable/disable register
2900          * configuration is handle by the F/W
2901          */
2902         err = i40e_set_fc(hw, &aq_failure, true);
2903         if (err < 0)
2904                 return -ENOSYS;
2905
2906         if (i40e_is_40G_device(hw->device_id)) {
2907                 /* Configure flow control refresh threshold,
2908                  * the value for stat_tx_pause_refresh_timer[8]
2909                  * is used for global pause operation.
2910                  */
2911
2912                 I40E_WRITE_REG(hw,
2913                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2914                                pf->fc_conf.pause_time);
2915
2916                 /* configure the timer value included in transmitted pause
2917                  * frame,
2918                  * the value for stat_tx_pause_quanta[8] is used for global
2919                  * pause operation
2920                  */
2921                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2922                                pf->fc_conf.pause_time);
2923
2924                 fctrl_reg = I40E_READ_REG(hw,
2925                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2926
2927                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2928                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2929                 else
2930                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2931
2932                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2933                                fctrl_reg);
2934         } else {
2935                 /* Configure pause time (2 TCs per register) */
2936                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2937                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2938                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2939
2940                 /* Configure flow control refresh threshold value */
2941                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2942                                pf->fc_conf.pause_time / 2);
2943
2944                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2945
2946                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2947                  *depending on configuration
2948                  */
2949                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2950                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2951                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2952                 } else {
2953                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2954                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2955                 }
2956
2957                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2958         }
2959
2960         /* config the water marker both based on the packets and bytes */
2961         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2962                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2963                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2964         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2965                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2966                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2967         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2968                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2969                        << I40E_KILOSHIFT);
2970         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2971                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2972                        << I40E_KILOSHIFT);
2973
2974         I40E_WRITE_FLUSH(hw);
2975
2976         return 0;
2977 }
2978
2979 static int
2980 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2981                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2982 {
2983         PMD_INIT_FUNC_TRACE();
2984
2985         return -ENOSYS;
2986 }
2987
2988 /* Add a MAC address, and update filters */
2989 static void
2990 i40e_macaddr_add(struct rte_eth_dev *dev,
2991                  struct ether_addr *mac_addr,
2992                  __rte_unused uint32_t index,
2993                  uint32_t pool)
2994 {
2995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2996         struct i40e_mac_filter_info mac_filter;
2997         struct i40e_vsi *vsi;
2998         int ret;
2999
3000         /* If VMDQ not enabled or configured, return */
3001         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3002                           !pf->nb_cfg_vmdq_vsi)) {
3003                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3004                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3005                         pool);
3006                 return;
3007         }
3008
3009         if (pool > pf->nb_cfg_vmdq_vsi) {
3010                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3011                                 pool, pf->nb_cfg_vmdq_vsi);
3012                 return;
3013         }
3014
3015         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3016         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3017                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3018         else
3019                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3020
3021         if (pool == 0)
3022                 vsi = pf->main_vsi;
3023         else
3024                 vsi = pf->vmdq[pool - 1].vsi;
3025
3026         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3027         if (ret != I40E_SUCCESS) {
3028                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3029                 return;
3030         }
3031 }
3032
3033 /* Remove a MAC address, and update filters */
3034 static void
3035 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3036 {
3037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3038         struct i40e_vsi *vsi;
3039         struct rte_eth_dev_data *data = dev->data;
3040         struct ether_addr *macaddr;
3041         int ret;
3042         uint32_t i;
3043         uint64_t pool_sel;
3044
3045         macaddr = &(data->mac_addrs[index]);
3046
3047         pool_sel = dev->data->mac_pool_sel[index];
3048
3049         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3050                 if (pool_sel & (1ULL << i)) {
3051                         if (i == 0)
3052                                 vsi = pf->main_vsi;
3053                         else {
3054                                 /* No VMDQ pool enabled or configured */
3055                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3056                                         (i > pf->nb_cfg_vmdq_vsi)) {
3057                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3058                                                         "/configured");
3059                                         return;
3060                                 }
3061                                 vsi = pf->vmdq[i - 1].vsi;
3062                         }
3063                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3064
3065                         if (ret) {
3066                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3067                                 return;
3068                         }
3069                 }
3070         }
3071 }
3072
3073 /* Set perfect match or hash match of MAC and VLAN for a VF */
3074 static int
3075 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3076                  struct rte_eth_mac_filter *filter,
3077                  bool add)
3078 {
3079         struct i40e_hw *hw;
3080         struct i40e_mac_filter_info mac_filter;
3081         struct ether_addr old_mac;
3082         struct ether_addr *new_mac;
3083         struct i40e_pf_vf *vf = NULL;
3084         uint16_t vf_id;
3085         int ret;
3086
3087         if (pf == NULL) {
3088                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3089                 return -EINVAL;
3090         }
3091         hw = I40E_PF_TO_HW(pf);
3092
3093         if (filter == NULL) {
3094                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3095                 return -EINVAL;
3096         }
3097
3098         new_mac = &filter->mac_addr;
3099
3100         if (is_zero_ether_addr(new_mac)) {
3101                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3102                 return -EINVAL;
3103         }
3104
3105         vf_id = filter->dst_id;
3106
3107         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3108                 PMD_DRV_LOG(ERR, "Invalid argument.");
3109                 return -EINVAL;
3110         }
3111         vf = &pf->vfs[vf_id];
3112
3113         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3114                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3115                 return -EINVAL;
3116         }
3117
3118         if (add) {
3119                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3120                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3121                                 ETHER_ADDR_LEN);
3122                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3123                                  ETHER_ADDR_LEN);
3124
3125                 mac_filter.filter_type = filter->filter_type;
3126                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3127                 if (ret != I40E_SUCCESS) {
3128                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3129                         return -1;
3130                 }
3131                 ether_addr_copy(new_mac, &pf->dev_addr);
3132         } else {
3133                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3134                                 ETHER_ADDR_LEN);
3135                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3136                 if (ret != I40E_SUCCESS) {
3137                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3138                         return -1;
3139                 }
3140
3141                 /* Clear device address as it has been removed */
3142                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3143                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3144         }
3145
3146         return 0;
3147 }
3148
3149 /* MAC filter handle */
3150 static int
3151 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3152                 void *arg)
3153 {
3154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3155         struct rte_eth_mac_filter *filter;
3156         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3157         int ret = I40E_NOT_SUPPORTED;
3158
3159         filter = (struct rte_eth_mac_filter *)(arg);
3160
3161         switch (filter_op) {
3162         case RTE_ETH_FILTER_NOP:
3163                 ret = I40E_SUCCESS;
3164                 break;
3165         case RTE_ETH_FILTER_ADD:
3166                 i40e_pf_disable_irq0(hw);
3167                 if (filter->is_vf)
3168                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3169                 i40e_pf_enable_irq0(hw);
3170                 break;
3171         case RTE_ETH_FILTER_DELETE:
3172                 i40e_pf_disable_irq0(hw);
3173                 if (filter->is_vf)
3174                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3175                 i40e_pf_enable_irq0(hw);
3176                 break;
3177         default:
3178                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3179                 ret = I40E_ERR_PARAM;
3180                 break;
3181         }
3182
3183         return ret;
3184 }
3185
3186 static int
3187 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3188 {
3189         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3190         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3191         int ret;
3192
3193         if (!lut)
3194                 return -EINVAL;
3195
3196         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3197                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3198                                           lut, lut_size);
3199                 if (ret) {
3200                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3201                         return ret;
3202                 }
3203         } else {
3204                 uint32_t *lut_dw = (uint32_t *)lut;
3205                 uint16_t i, lut_size_dw = lut_size / 4;
3206
3207                 for (i = 0; i < lut_size_dw; i++)
3208                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3209         }
3210
3211         return 0;
3212 }
3213
3214 static int
3215 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3216 {
3217         struct i40e_pf *pf;
3218         struct i40e_hw *hw;
3219         int ret;
3220
3221         if (!vsi || !lut)
3222                 return -EINVAL;
3223
3224         pf = I40E_VSI_TO_PF(vsi);
3225         hw = I40E_VSI_TO_HW(vsi);
3226
3227         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3228                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3229                                           lut, lut_size);
3230                 if (ret) {
3231                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3232                         return ret;
3233                 }
3234         } else {
3235                 uint32_t *lut_dw = (uint32_t *)lut;
3236                 uint16_t i, lut_size_dw = lut_size / 4;
3237
3238                 for (i = 0; i < lut_size_dw; i++)
3239                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3240                 I40E_WRITE_FLUSH(hw);
3241         }
3242
3243         return 0;
3244 }
3245
3246 static int
3247 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3248                          struct rte_eth_rss_reta_entry64 *reta_conf,
3249                          uint16_t reta_size)
3250 {
3251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3252         uint16_t i, lut_size = pf->hash_lut_size;
3253         uint16_t idx, shift;
3254         uint8_t *lut;
3255         int ret;
3256
3257         if (reta_size != lut_size ||
3258                 reta_size > ETH_RSS_RETA_SIZE_512) {
3259                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3260                         "(%d) doesn't match the number hardware can supported "
3261                                         "(%d)\n", reta_size, lut_size);
3262                 return -EINVAL;
3263         }
3264
3265         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3266         if (!lut) {
3267                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3268                 return -ENOMEM;
3269         }
3270         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3271         if (ret)
3272                 goto out;
3273         for (i = 0; i < reta_size; i++) {
3274                 idx = i / RTE_RETA_GROUP_SIZE;
3275                 shift = i % RTE_RETA_GROUP_SIZE;
3276                 if (reta_conf[idx].mask & (1ULL << shift))
3277                         lut[i] = reta_conf[idx].reta[shift];
3278         }
3279         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3280
3281 out:
3282         rte_free(lut);
3283
3284         return ret;
3285 }
3286
3287 static int
3288 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3289                         struct rte_eth_rss_reta_entry64 *reta_conf,
3290                         uint16_t reta_size)
3291 {
3292         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3293         uint16_t i, lut_size = pf->hash_lut_size;
3294         uint16_t idx, shift;
3295         uint8_t *lut;
3296         int ret;
3297
3298         if (reta_size != lut_size ||
3299                 reta_size > ETH_RSS_RETA_SIZE_512) {
3300                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3301                         "(%d) doesn't match the number hardware can supported "
3302                                         "(%d)\n", reta_size, lut_size);
3303                 return -EINVAL;
3304         }
3305
3306         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3307         if (!lut) {
3308                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3309                 return -ENOMEM;
3310         }
3311
3312         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3313         if (ret)
3314                 goto out;
3315         for (i = 0; i < reta_size; i++) {
3316                 idx = i / RTE_RETA_GROUP_SIZE;
3317                 shift = i % RTE_RETA_GROUP_SIZE;
3318                 if (reta_conf[idx].mask & (1ULL << shift))
3319                         reta_conf[idx].reta[shift] = lut[i];
3320         }
3321
3322 out:
3323         rte_free(lut);
3324
3325         return ret;
3326 }
3327
3328 /**
3329  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3330  * @hw:   pointer to the HW structure
3331  * @mem:  pointer to mem struct to fill out
3332  * @size: size of memory requested
3333  * @alignment: what to align the allocation to
3334  **/
3335 enum i40e_status_code
3336 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3337                         struct i40e_dma_mem *mem,
3338                         u64 size,
3339                         u32 alignment)
3340 {
3341         const struct rte_memzone *mz = NULL;
3342         char z_name[RTE_MEMZONE_NAMESIZE];
3343
3344         if (!mem)
3345                 return I40E_ERR_PARAM;
3346
3347         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3348         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3349                                          alignment, RTE_PGSIZE_2M);
3350         if (!mz)
3351                 return I40E_ERR_NO_MEMORY;
3352
3353         mem->size = size;
3354         mem->va = mz->addr;
3355         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3356         mem->zone = (const void *)mz;
3357         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3358                     "%"PRIu64, mz->name, mem->pa);
3359
3360         return I40E_SUCCESS;
3361 }
3362
3363 /**
3364  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3365  * @hw:   pointer to the HW structure
3366  * @mem:  ptr to mem struct to free
3367  **/
3368 enum i40e_status_code
3369 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3370                     struct i40e_dma_mem *mem)
3371 {
3372         if (!mem)
3373                 return I40E_ERR_PARAM;
3374
3375         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3376                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3377                     mem->pa);
3378         rte_memzone_free((const struct rte_memzone *)mem->zone);
3379         mem->zone = NULL;
3380         mem->va = NULL;
3381         mem->pa = (u64)0;
3382
3383         return I40E_SUCCESS;
3384 }
3385
3386 /**
3387  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3388  * @hw:   pointer to the HW structure
3389  * @mem:  pointer to mem struct to fill out
3390  * @size: size of memory requested
3391  **/
3392 enum i40e_status_code
3393 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3394                          struct i40e_virt_mem *mem,
3395                          u32 size)
3396 {
3397         if (!mem)
3398                 return I40E_ERR_PARAM;
3399
3400         mem->size = size;
3401         mem->va = rte_zmalloc("i40e", size, 0);
3402
3403         if (mem->va)
3404                 return I40E_SUCCESS;
3405         else
3406                 return I40E_ERR_NO_MEMORY;
3407 }
3408
3409 /**
3410  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3411  * @hw:   pointer to the HW structure
3412  * @mem:  pointer to mem struct to free
3413  **/
3414 enum i40e_status_code
3415 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3416                      struct i40e_virt_mem *mem)
3417 {
3418         if (!mem)
3419                 return I40E_ERR_PARAM;
3420
3421         rte_free(mem->va);
3422         mem->va = NULL;
3423
3424         return I40E_SUCCESS;
3425 }
3426
3427 void
3428 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3429 {
3430         rte_spinlock_init(&sp->spinlock);
3431 }
3432
3433 void
3434 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3435 {
3436         rte_spinlock_lock(&sp->spinlock);
3437 }
3438
3439 void
3440 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3441 {
3442         rte_spinlock_unlock(&sp->spinlock);
3443 }
3444
3445 void
3446 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3447 {
3448         return;
3449 }
3450
3451 /**
3452  * Get the hardware capabilities, which will be parsed
3453  * and saved into struct i40e_hw.
3454  */
3455 static int
3456 i40e_get_cap(struct i40e_hw *hw)
3457 {
3458         struct i40e_aqc_list_capabilities_element_resp *buf;
3459         uint16_t len, size = 0;
3460         int ret;
3461
3462         /* Calculate a huge enough buff for saving response data temporarily */
3463         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3464                                                 I40E_MAX_CAP_ELE_NUM;
3465         buf = rte_zmalloc("i40e", len, 0);
3466         if (!buf) {
3467                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3468                 return I40E_ERR_NO_MEMORY;
3469         }
3470
3471         /* Get, parse the capabilities and save it to hw */
3472         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3473                         i40e_aqc_opc_list_func_capabilities, NULL);
3474         if (ret != I40E_SUCCESS)
3475                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3476
3477         /* Free the temporary buffer after being used */
3478         rte_free(buf);
3479
3480         return ret;
3481 }
3482
3483 static int
3484 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3485 {
3486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3487         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3488         uint16_t qp_count = 0, vsi_count = 0;
3489
3490         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3491                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3492                 return -EINVAL;
3493         }
3494         /* Add the parameter init for LFC */
3495         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3496         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3497         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3498
3499         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3500         pf->max_num_vsi = hw->func_caps.num_vsis;
3501         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3502         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3503         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3504
3505         /* FDir queue/VSI allocation */
3506         pf->fdir_qp_offset = 0;
3507         if (hw->func_caps.fd) {
3508                 pf->flags |= I40E_FLAG_FDIR;
3509                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3510         } else {
3511                 pf->fdir_nb_qps = 0;
3512         }
3513         qp_count += pf->fdir_nb_qps;
3514         vsi_count += 1;
3515
3516         /* LAN queue/VSI allocation */
3517         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3518         if (!hw->func_caps.rss) {
3519                 pf->lan_nb_qps = 1;
3520         } else {
3521                 pf->flags |= I40E_FLAG_RSS;
3522                 if (hw->mac.type == I40E_MAC_X722)
3523                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3524                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3525         }
3526         qp_count += pf->lan_nb_qps;
3527         vsi_count += 1;
3528
3529         /* VF queue/VSI allocation */
3530         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3531         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3532                 pf->flags |= I40E_FLAG_SRIOV;
3533                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3534                 pf->vf_num = dev->pci_dev->max_vfs;
3535                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3536                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3537                             pf->vf_nb_qps * pf->vf_num);
3538         } else {
3539                 pf->vf_nb_qps = 0;
3540                 pf->vf_num = 0;
3541         }
3542         qp_count += pf->vf_nb_qps * pf->vf_num;
3543         vsi_count += pf->vf_num;
3544
3545         /* VMDq queue/VSI allocation */
3546         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3547         pf->vmdq_nb_qps = 0;
3548         pf->max_nb_vmdq_vsi = 0;
3549         if (hw->func_caps.vmdq) {
3550                 if (qp_count < hw->func_caps.num_tx_qp &&
3551                         vsi_count < hw->func_caps.num_vsis) {
3552                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3553                                 qp_count) / pf->vmdq_nb_qp_max;
3554
3555                         /* Limit the maximum number of VMDq vsi to the maximum
3556                          * ethdev can support
3557                          */
3558                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3559                                 hw->func_caps.num_vsis - vsi_count);
3560                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3561                                 ETH_64_POOLS);
3562                         if (pf->max_nb_vmdq_vsi) {
3563                                 pf->flags |= I40E_FLAG_VMDQ;
3564                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3565                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3566                                             "per VMDQ VSI, in total %u queues",
3567                                             pf->max_nb_vmdq_vsi,
3568                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3569                                             pf->max_nb_vmdq_vsi);
3570                         } else {
3571                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3572                                             "VMDq");
3573                         }
3574                 } else {
3575                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3576                 }
3577         }
3578         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3579         vsi_count += pf->max_nb_vmdq_vsi;
3580
3581         if (hw->func_caps.dcb)
3582                 pf->flags |= I40E_FLAG_DCB;
3583
3584         if (qp_count > hw->func_caps.num_tx_qp) {
3585                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3586                             "the hardware maximum %u", qp_count,
3587                             hw->func_caps.num_tx_qp);
3588                 return -EINVAL;
3589         }
3590         if (vsi_count > hw->func_caps.num_vsis) {
3591                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3592                             "the hardware maximum %u", vsi_count,
3593                             hw->func_caps.num_vsis);
3594                 return -EINVAL;
3595         }
3596
3597         return 0;
3598 }
3599
3600 static int
3601 i40e_pf_get_switch_config(struct i40e_pf *pf)
3602 {
3603         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3604         struct i40e_aqc_get_switch_config_resp *switch_config;
3605         struct i40e_aqc_switch_config_element_resp *element;
3606         uint16_t start_seid = 0, num_reported;
3607         int ret;
3608
3609         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3610                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3611         if (!switch_config) {
3612                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3613                 return -ENOMEM;
3614         }
3615
3616         /* Get the switch configurations */
3617         ret = i40e_aq_get_switch_config(hw, switch_config,
3618                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3619         if (ret != I40E_SUCCESS) {
3620                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3621                 goto fail;
3622         }
3623         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3624         if (num_reported != 1) { /* The number should be 1 */
3625                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3626                 goto fail;
3627         }
3628
3629         /* Parse the switch configuration elements */
3630         element = &(switch_config->element[0]);
3631         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3632                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3633                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3634         } else
3635                 PMD_DRV_LOG(INFO, "Unknown element type");
3636
3637 fail:
3638         rte_free(switch_config);
3639
3640         return ret;
3641 }
3642
3643 static int
3644 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3645                         uint32_t num)
3646 {
3647         struct pool_entry *entry;
3648
3649         if (pool == NULL || num == 0)
3650                 return -EINVAL;
3651
3652         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3653         if (entry == NULL) {
3654                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3655                 return -ENOMEM;
3656         }
3657
3658         /* queue heap initialize */
3659         pool->num_free = num;
3660         pool->num_alloc = 0;
3661         pool->base = base;
3662         LIST_INIT(&pool->alloc_list);
3663         LIST_INIT(&pool->free_list);
3664
3665         /* Initialize element  */
3666         entry->base = 0;
3667         entry->len = num;
3668
3669         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3670         return 0;
3671 }
3672
3673 static void
3674 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3675 {
3676         struct pool_entry *entry, *next_entry;
3677
3678         if (pool == NULL)
3679                 return;
3680
3681         for (entry = LIST_FIRST(&pool->alloc_list);
3682                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3683                         entry = next_entry) {
3684                 LIST_REMOVE(entry, next);
3685                 rte_free(entry);
3686         }
3687
3688         for (entry = LIST_FIRST(&pool->free_list);
3689                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3690                         entry = next_entry) {
3691                 LIST_REMOVE(entry, next);
3692                 rte_free(entry);
3693         }
3694
3695         pool->num_free = 0;
3696         pool->num_alloc = 0;
3697         pool->base = 0;
3698         LIST_INIT(&pool->alloc_list);
3699         LIST_INIT(&pool->free_list);
3700 }
3701
3702 static int
3703 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3704                        uint32_t base)
3705 {
3706         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3707         uint32_t pool_offset;
3708         int insert;
3709
3710         if (pool == NULL) {
3711                 PMD_DRV_LOG(ERR, "Invalid parameter");
3712                 return -EINVAL;
3713         }
3714
3715         pool_offset = base - pool->base;
3716         /* Lookup in alloc list */
3717         LIST_FOREACH(entry, &pool->alloc_list, next) {
3718                 if (entry->base == pool_offset) {
3719                         valid_entry = entry;
3720                         LIST_REMOVE(entry, next);
3721                         break;
3722                 }
3723         }
3724
3725         /* Not find, return */
3726         if (valid_entry == NULL) {
3727                 PMD_DRV_LOG(ERR, "Failed to find entry");
3728                 return -EINVAL;
3729         }
3730
3731         /**
3732          * Found it, move it to free list  and try to merge.
3733          * In order to make merge easier, always sort it by qbase.
3734          * Find adjacent prev and last entries.
3735          */
3736         prev = next = NULL;
3737         LIST_FOREACH(entry, &pool->free_list, next) {
3738                 if (entry->base > valid_entry->base) {
3739                         next = entry;
3740                         break;
3741                 }
3742                 prev = entry;
3743         }
3744
3745         insert = 0;
3746         /* Try to merge with next one*/
3747         if (next != NULL) {
3748                 /* Merge with next one */
3749                 if (valid_entry->base + valid_entry->len == next->base) {
3750                         next->base = valid_entry->base;
3751                         next->len += valid_entry->len;
3752                         rte_free(valid_entry);
3753                         valid_entry = next;
3754                         insert = 1;
3755                 }
3756         }
3757
3758         if (prev != NULL) {
3759                 /* Merge with previous one */
3760                 if (prev->base + prev->len == valid_entry->base) {
3761                         prev->len += valid_entry->len;
3762                         /* If it merge with next one, remove next node */
3763                         if (insert == 1) {
3764                                 LIST_REMOVE(valid_entry, next);
3765                                 rte_free(valid_entry);
3766                         } else {
3767                                 rte_free(valid_entry);
3768                                 insert = 1;
3769                         }
3770                 }
3771         }
3772
3773         /* Not find any entry to merge, insert */
3774         if (insert == 0) {
3775                 if (prev != NULL)
3776                         LIST_INSERT_AFTER(prev, valid_entry, next);
3777                 else if (next != NULL)
3778                         LIST_INSERT_BEFORE(next, valid_entry, next);
3779                 else /* It's empty list, insert to head */
3780                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3781         }
3782
3783         pool->num_free += valid_entry->len;
3784         pool->num_alloc -= valid_entry->len;
3785
3786         return 0;
3787 }
3788
3789 static int
3790 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3791                        uint16_t num)
3792 {
3793         struct pool_entry *entry, *valid_entry;
3794
3795         if (pool == NULL || num == 0) {
3796                 PMD_DRV_LOG(ERR, "Invalid parameter");
3797                 return -EINVAL;
3798         }
3799
3800         if (pool->num_free < num) {
3801                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3802                             num, pool->num_free);
3803                 return -ENOMEM;
3804         }
3805
3806         valid_entry = NULL;
3807         /* Lookup  in free list and find most fit one */
3808         LIST_FOREACH(entry, &pool->free_list, next) {
3809                 if (entry->len >= num) {
3810                         /* Find best one */
3811                         if (entry->len == num) {
3812                                 valid_entry = entry;
3813                                 break;
3814                         }
3815                         if (valid_entry == NULL || valid_entry->len > entry->len)
3816                                 valid_entry = entry;
3817                 }
3818         }
3819
3820         /* Not find one to satisfy the request, return */
3821         if (valid_entry == NULL) {
3822                 PMD_DRV_LOG(ERR, "No valid entry found");
3823                 return -ENOMEM;
3824         }
3825         /**
3826          * The entry have equal queue number as requested,
3827          * remove it from alloc_list.
3828          */
3829         if (valid_entry->len == num) {
3830                 LIST_REMOVE(valid_entry, next);
3831         } else {
3832                 /**
3833                  * The entry have more numbers than requested,
3834                  * create a new entry for alloc_list and minus its
3835                  * queue base and number in free_list.
3836                  */
3837                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3838                 if (entry == NULL) {
3839                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3840                                     "resource pool");
3841                         return -ENOMEM;
3842                 }
3843                 entry->base = valid_entry->base;
3844                 entry->len = num;
3845                 valid_entry->base += num;
3846                 valid_entry->len -= num;
3847                 valid_entry = entry;
3848         }
3849
3850         /* Insert it into alloc list, not sorted */
3851         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3852
3853         pool->num_free -= valid_entry->len;
3854         pool->num_alloc += valid_entry->len;
3855
3856         return valid_entry->base + pool->base;
3857 }
3858
3859 /**
3860  * bitmap_is_subset - Check whether src2 is subset of src1
3861  **/
3862 static inline int
3863 bitmap_is_subset(uint8_t src1, uint8_t src2)
3864 {
3865         return !((src1 ^ src2) & src2);
3866 }
3867
3868 static enum i40e_status_code
3869 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3870 {
3871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3872
3873         /* If DCB is not supported, only default TC is supported */
3874         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3875                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3876                 return I40E_NOT_SUPPORTED;
3877         }
3878
3879         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3880                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3881                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3882                             enabled_tcmap);
3883                 return I40E_NOT_SUPPORTED;
3884         }
3885         return I40E_SUCCESS;
3886 }
3887
3888 int
3889 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3890                                 struct i40e_vsi_vlan_pvid_info *info)
3891 {
3892         struct i40e_hw *hw;
3893         struct i40e_vsi_context ctxt;
3894         uint8_t vlan_flags = 0;
3895         int ret;
3896
3897         if (vsi == NULL || info == NULL) {
3898                 PMD_DRV_LOG(ERR, "invalid parameters");
3899                 return I40E_ERR_PARAM;
3900         }
3901
3902         if (info->on) {
3903                 vsi->info.pvid = info->config.pvid;
3904                 /**
3905                  * If insert pvid is enabled, only tagged pkts are
3906                  * allowed to be sent out.
3907                  */
3908                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3909                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3910         } else {
3911                 vsi->info.pvid = 0;
3912                 if (info->config.reject.tagged == 0)
3913                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3914
3915                 if (info->config.reject.untagged == 0)
3916                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3917         }
3918         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3919                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3920         vsi->info.port_vlan_flags |= vlan_flags;
3921         vsi->info.valid_sections =
3922                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3923         memset(&ctxt, 0, sizeof(ctxt));
3924         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3925         ctxt.seid = vsi->seid;
3926
3927         hw = I40E_VSI_TO_HW(vsi);
3928         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3929         if (ret != I40E_SUCCESS)
3930                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3931
3932         return ret;
3933 }
3934
3935 static int
3936 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3937 {
3938         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3939         int i, ret;
3940         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3941
3942         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3943         if (ret != I40E_SUCCESS)
3944                 return ret;
3945
3946         if (!vsi->seid) {
3947                 PMD_DRV_LOG(ERR, "seid not valid");
3948                 return -EINVAL;
3949         }
3950
3951         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3952         tc_bw_data.tc_valid_bits = enabled_tcmap;
3953         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3954                 tc_bw_data.tc_bw_credits[i] =
3955                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3956
3957         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3958         if (ret != I40E_SUCCESS) {
3959                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3960                 return ret;
3961         }
3962
3963         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3964                                         sizeof(vsi->info.qs_handle));
3965         return I40E_SUCCESS;
3966 }
3967
3968 static enum i40e_status_code
3969 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3970                                  struct i40e_aqc_vsi_properties_data *info,
3971                                  uint8_t enabled_tcmap)
3972 {
3973         enum i40e_status_code ret;
3974         int i, total_tc = 0;
3975         uint16_t qpnum_per_tc, bsf, qp_idx;
3976
3977         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3978         if (ret != I40E_SUCCESS)
3979                 return ret;
3980
3981         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3982                 if (enabled_tcmap & (1 << i))
3983                         total_tc++;
3984         vsi->enabled_tc = enabled_tcmap;
3985
3986         /* Number of queues per enabled TC */
3987         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3988         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3989         bsf = rte_bsf32(qpnum_per_tc);
3990
3991         /* Adjust the queue number to actual queues that can be applied */
3992         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3993                 vsi->nb_qps = qpnum_per_tc * total_tc;
3994
3995         /**
3996          * Configure TC and queue mapping parameters, for enabled TC,
3997          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3998          * default queue will serve it.
3999          */
4000         qp_idx = 0;
4001         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4002                 if (vsi->enabled_tc & (1 << i)) {
4003                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4004                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4005                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4006                         qp_idx += qpnum_per_tc;
4007                 } else
4008                         info->tc_mapping[i] = 0;
4009         }
4010
4011         /* Associate queue number with VSI */
4012         if (vsi->type == I40E_VSI_SRIOV) {
4013                 info->mapping_flags |=
4014                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4015                 for (i = 0; i < vsi->nb_qps; i++)
4016                         info->queue_mapping[i] =
4017                                 rte_cpu_to_le_16(vsi->base_queue + i);
4018         } else {
4019                 info->mapping_flags |=
4020                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4021                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4022         }
4023         info->valid_sections |=
4024                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4025
4026         return I40E_SUCCESS;
4027 }
4028
4029 static int
4030 i40e_veb_release(struct i40e_veb *veb)
4031 {
4032         struct i40e_vsi *vsi;
4033         struct i40e_hw *hw;
4034
4035         if (veb == NULL)
4036                 return -EINVAL;
4037
4038         if (!TAILQ_EMPTY(&veb->head)) {
4039                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4040                 return -EACCES;
4041         }
4042         /* associate_vsi field is NULL for floating VEB */
4043         if (veb->associate_vsi != NULL) {
4044                 vsi = veb->associate_vsi;
4045                 hw = I40E_VSI_TO_HW(vsi);
4046
4047                 vsi->uplink_seid = veb->uplink_seid;
4048                 vsi->veb = NULL;
4049         } else {
4050                 veb->associate_pf->main_vsi->floating_veb = NULL;
4051                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4052         }
4053
4054         i40e_aq_delete_element(hw, veb->seid, NULL);
4055         rte_free(veb);
4056         return I40E_SUCCESS;
4057 }
4058
4059 /* Setup a veb */
4060 static struct i40e_veb *
4061 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4062 {
4063         struct i40e_veb *veb;
4064         int ret;
4065         struct i40e_hw *hw;
4066
4067         if (pf == NULL) {
4068                 PMD_DRV_LOG(ERR,
4069                             "veb setup failed, associated PF shouldn't null");
4070                 return NULL;
4071         }
4072         hw = I40E_PF_TO_HW(pf);
4073
4074         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4075         if (!veb) {
4076                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4077                 goto fail;
4078         }
4079
4080         veb->associate_vsi = vsi;
4081         veb->associate_pf = pf;
4082         TAILQ_INIT(&veb->head);
4083         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4084
4085         /* create floating veb if vsi is NULL */
4086         if (vsi != NULL) {
4087                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4088                                       I40E_DEFAULT_TCMAP, false,
4089                                       &veb->seid, false, NULL);
4090         } else {
4091                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4092                                       true, &veb->seid, false, NULL);
4093         }
4094
4095         if (ret != I40E_SUCCESS) {
4096                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4097                             hw->aq.asq_last_status);
4098                 goto fail;
4099         }
4100
4101         /* get statistics index */
4102         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4103                                 &veb->stats_idx, NULL, NULL, NULL);
4104         if (ret != I40E_SUCCESS) {
4105                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4106                             hw->aq.asq_last_status);
4107                 goto fail;
4108         }
4109         /* Get VEB bandwidth, to be implemented */
4110         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4111         if (vsi)
4112                 vsi->uplink_seid = veb->seid;
4113
4114         return veb;
4115 fail:
4116         rte_free(veb);
4117         return NULL;
4118 }
4119
4120 int
4121 i40e_vsi_release(struct i40e_vsi *vsi)
4122 {
4123         struct i40e_pf *pf;
4124         struct i40e_hw *hw;
4125         struct i40e_vsi_list *vsi_list;
4126         void *temp;
4127         int ret;
4128         struct i40e_mac_filter *f;
4129         uint16_t user_param;
4130
4131         if (!vsi)
4132                 return I40E_SUCCESS;
4133
4134         user_param = vsi->user_param;
4135
4136         pf = I40E_VSI_TO_PF(vsi);
4137         hw = I40E_VSI_TO_HW(vsi);
4138
4139         /* VSI has child to attach, release child first */
4140         if (vsi->veb) {
4141                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4142                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4143                                 return -1;
4144                 }
4145                 i40e_veb_release(vsi->veb);
4146         }
4147
4148         if (vsi->floating_veb) {
4149                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4150                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4151                                 return -1;
4152                 }
4153         }
4154
4155         /* Remove all macvlan filters of the VSI */
4156         i40e_vsi_remove_all_macvlan_filter(vsi);
4157         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4158                 rte_free(f);
4159
4160         if (vsi->type != I40E_VSI_MAIN &&
4161             ((vsi->type != I40E_VSI_SRIOV) ||
4162             !pf->floating_veb_list[user_param])) {
4163                 /* Remove vsi from parent's sibling list */
4164                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4165                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4166                         return I40E_ERR_PARAM;
4167                 }
4168                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4169                                 &vsi->sib_vsi_list, list);
4170
4171                 /* Remove all switch element of the VSI */
4172                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4173                 if (ret != I40E_SUCCESS)
4174                         PMD_DRV_LOG(ERR, "Failed to delete element");
4175         }
4176
4177         if ((vsi->type == I40E_VSI_SRIOV) &&
4178             pf->floating_veb_list[user_param]) {
4179                 /* Remove vsi from parent's sibling list */
4180                 if (vsi->parent_vsi == NULL ||
4181                     vsi->parent_vsi->floating_veb == NULL) {
4182                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4183                         return I40E_ERR_PARAM;
4184                 }
4185                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4186                              &vsi->sib_vsi_list, list);
4187
4188                 /* Remove all switch element of the VSI */
4189                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4190                 if (ret != I40E_SUCCESS)
4191                         PMD_DRV_LOG(ERR, "Failed to delete element");
4192         }
4193
4194         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4195
4196         if (vsi->type != I40E_VSI_SRIOV)
4197                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4198         rte_free(vsi);
4199
4200         return I40E_SUCCESS;
4201 }
4202
4203 static int
4204 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4205 {
4206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4207         struct i40e_aqc_remove_macvlan_element_data def_filter;
4208         struct i40e_mac_filter_info filter;
4209         int ret;
4210
4211         if (vsi->type != I40E_VSI_MAIN)
4212                 return I40E_ERR_CONFIG;
4213         memset(&def_filter, 0, sizeof(def_filter));
4214         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4215                                         ETH_ADDR_LEN);
4216         def_filter.vlan_tag = 0;
4217         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4218                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4219         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4220         if (ret != I40E_SUCCESS) {
4221                 struct i40e_mac_filter *f;
4222                 struct ether_addr *mac;
4223
4224                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4225                             "macvlan filter");
4226                 /* It needs to add the permanent mac into mac list */
4227                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4228                 if (f == NULL) {
4229                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4230                         return I40E_ERR_NO_MEMORY;
4231                 }
4232                 mac = &f->mac_info.mac_addr;
4233                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4234                                 ETH_ADDR_LEN);
4235                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4236                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4237                 vsi->mac_num++;
4238
4239                 return ret;
4240         }
4241         (void)rte_memcpy(&filter.mac_addr,
4242                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4243         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4244         return i40e_vsi_add_mac(vsi, &filter);
4245 }
4246
4247 /*
4248  * i40e_vsi_get_bw_config - Query VSI BW Information
4249  * @vsi: the VSI to be queried
4250  *
4251  * Returns 0 on success, negative value on failure
4252  */
4253 static enum i40e_status_code
4254 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4255 {
4256         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4257         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4258         struct i40e_hw *hw = &vsi->adapter->hw;
4259         i40e_status ret;
4260         int i;
4261         uint32_t bw_max;
4262
4263         memset(&bw_config, 0, sizeof(bw_config));
4264         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4265         if (ret != I40E_SUCCESS) {
4266                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4267                             hw->aq.asq_last_status);
4268                 return ret;
4269         }
4270
4271         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4272         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4273                                         &ets_sla_config, NULL);
4274         if (ret != I40E_SUCCESS) {
4275                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4276                             "configuration %u", hw->aq.asq_last_status);
4277                 return ret;
4278         }
4279
4280         /* store and print out BW info */
4281         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4282         vsi->bw_info.bw_max = bw_config.max_bw;
4283         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4284         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4285         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4286                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4287                      I40E_16_BIT_WIDTH);
4288         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4289                 vsi->bw_info.bw_ets_share_credits[i] =
4290                                 ets_sla_config.share_credits[i];
4291                 vsi->bw_info.bw_ets_credits[i] =
4292                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4293                 /* 4 bits per TC, 4th bit is reserved */
4294                 vsi->bw_info.bw_ets_max[i] =
4295                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4296                                   RTE_LEN2MASK(3, uint8_t));
4297                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4298                             vsi->bw_info.bw_ets_share_credits[i]);
4299                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4300                             vsi->bw_info.bw_ets_credits[i]);
4301                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4302                             vsi->bw_info.bw_ets_max[i]);
4303         }
4304
4305         return I40E_SUCCESS;
4306 }
4307
4308 /* i40e_enable_pf_lb
4309  * @pf: pointer to the pf structure
4310  *
4311  * allow loopback on pf
4312  */
4313 static inline void
4314 i40e_enable_pf_lb(struct i40e_pf *pf)
4315 {
4316         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4317         struct i40e_vsi_context ctxt;
4318         int ret;
4319
4320         /* Use the FW API if FW >= v5.0 */
4321         if (hw->aq.fw_maj_ver < 5) {
4322                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4323                 return;
4324         }
4325
4326         memset(&ctxt, 0, sizeof(ctxt));
4327         ctxt.seid = pf->main_vsi_seid;
4328         ctxt.pf_num = hw->pf_id;
4329         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4330         if (ret) {
4331                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4332                             ret, hw->aq.asq_last_status);
4333                 return;
4334         }
4335         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4336         ctxt.info.valid_sections =
4337                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4338         ctxt.info.switch_id |=
4339                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4340
4341         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4342         if (ret)
4343                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4344                             hw->aq.asq_last_status);
4345 }
4346
4347 /* Setup a VSI */
4348 struct i40e_vsi *
4349 i40e_vsi_setup(struct i40e_pf *pf,
4350                enum i40e_vsi_type type,
4351                struct i40e_vsi *uplink_vsi,
4352                uint16_t user_param)
4353 {
4354         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4355         struct i40e_vsi *vsi;
4356         struct i40e_mac_filter_info filter;
4357         int ret;
4358         struct i40e_vsi_context ctxt;
4359         struct ether_addr broadcast =
4360                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4361
4362         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4363             uplink_vsi == NULL) {
4364                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4365                             "VSI link shouldn't be NULL");
4366                 return NULL;
4367         }
4368
4369         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4370                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4371                             "uplink VSI should be NULL");
4372                 return NULL;
4373         }
4374
4375         /* two situations
4376          * 1.type is not MAIN and uplink vsi is not NULL
4377          * If uplink vsi didn't setup VEB, create one first under veb field
4378          * 2.type is SRIOV and the uplink is NULL
4379          * If floating VEB is NULL, create one veb under floating veb field
4380          */
4381
4382         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4383             uplink_vsi->veb == NULL) {
4384                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4385
4386                 if (uplink_vsi->veb == NULL) {
4387                         PMD_DRV_LOG(ERR, "VEB setup failed");
4388                         return NULL;
4389                 }
4390                 /* set ALLOWLOOPBACk on pf, when veb is created */
4391                 i40e_enable_pf_lb(pf);
4392         }
4393
4394         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4395             pf->main_vsi->floating_veb == NULL) {
4396                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4397
4398                 if (pf->main_vsi->floating_veb == NULL) {
4399                         PMD_DRV_LOG(ERR, "VEB setup failed");
4400                         return NULL;
4401                 }
4402         }
4403
4404         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4405         if (!vsi) {
4406                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4407                 return NULL;
4408         }
4409         TAILQ_INIT(&vsi->mac_list);
4410         vsi->type = type;
4411         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4412         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4413         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4414         vsi->user_param = user_param;
4415         /* Allocate queues */
4416         switch (vsi->type) {
4417         case I40E_VSI_MAIN  :
4418                 vsi->nb_qps = pf->lan_nb_qps;
4419                 break;
4420         case I40E_VSI_SRIOV :
4421                 vsi->nb_qps = pf->vf_nb_qps;
4422                 break;
4423         case I40E_VSI_VMDQ2:
4424                 vsi->nb_qps = pf->vmdq_nb_qps;
4425                 break;
4426         case I40E_VSI_FDIR:
4427                 vsi->nb_qps = pf->fdir_nb_qps;
4428                 break;
4429         default:
4430                 goto fail_mem;
4431         }
4432         /*
4433          * The filter status descriptor is reported in rx queue 0,
4434          * while the tx queue for fdir filter programming has no
4435          * such constraints, can be non-zero queues.
4436          * To simplify it, choose FDIR vsi use queue 0 pair.
4437          * To make sure it will use queue 0 pair, queue allocation
4438          * need be done before this function is called
4439          */
4440         if (type != I40E_VSI_FDIR) {
4441                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4442                         if (ret < 0) {
4443                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4444                                                 vsi->seid, ret);
4445                                 goto fail_mem;
4446                         }
4447                         vsi->base_queue = ret;
4448         } else
4449                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4450
4451         /* VF has MSIX interrupt in VF range, don't allocate here */
4452         if (type == I40E_VSI_MAIN) {
4453                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4454                                           RTE_MIN(vsi->nb_qps,
4455                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4456                 if (ret < 0) {
4457                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4458                                     vsi->seid, ret);
4459                         goto fail_queue_alloc;
4460                 }
4461                 vsi->msix_intr = ret;
4462                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4463         } else if (type != I40E_VSI_SRIOV) {
4464                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4465                 if (ret < 0) {
4466                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4467                         goto fail_queue_alloc;
4468                 }
4469                 vsi->msix_intr = ret;
4470                 vsi->nb_msix = 1;
4471         } else {
4472                 vsi->msix_intr = 0;
4473                 vsi->nb_msix = 0;
4474         }
4475
4476         /* Add VSI */
4477         if (type == I40E_VSI_MAIN) {
4478                 /* For main VSI, no need to add since it's default one */
4479                 vsi->uplink_seid = pf->mac_seid;
4480                 vsi->seid = pf->main_vsi_seid;
4481                 /* Bind queues with specific MSIX interrupt */
4482                 /**
4483                  * Needs 2 interrupt at least, one for misc cause which will
4484                  * enabled from OS side, Another for queues binding the
4485                  * interrupt from device side only.
4486                  */
4487
4488                 /* Get default VSI parameters from hardware */
4489                 memset(&ctxt, 0, sizeof(ctxt));
4490                 ctxt.seid = vsi->seid;
4491                 ctxt.pf_num = hw->pf_id;
4492                 ctxt.uplink_seid = vsi->uplink_seid;
4493                 ctxt.vf_num = 0;
4494                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4495                 if (ret != I40E_SUCCESS) {
4496                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4497                         goto fail_msix_alloc;
4498                 }
4499                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4500                         sizeof(struct i40e_aqc_vsi_properties_data));
4501                 vsi->vsi_id = ctxt.vsi_number;
4502                 vsi->info.valid_sections = 0;
4503
4504                 /* Configure tc, enabled TC0 only */
4505                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4506                         I40E_SUCCESS) {
4507                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4508                         goto fail_msix_alloc;
4509                 }
4510
4511                 /* TC, queue mapping */
4512                 memset(&ctxt, 0, sizeof(ctxt));
4513                 vsi->info.valid_sections |=
4514                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4515                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4516                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4517                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4518                         sizeof(struct i40e_aqc_vsi_properties_data));
4519                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4520                                                 I40E_DEFAULT_TCMAP);
4521                 if (ret != I40E_SUCCESS) {
4522                         PMD_DRV_LOG(ERR, "Failed to configure "
4523                                     "TC queue mapping");
4524                         goto fail_msix_alloc;
4525                 }
4526                 ctxt.seid = vsi->seid;
4527                 ctxt.pf_num = hw->pf_id;
4528                 ctxt.uplink_seid = vsi->uplink_seid;
4529                 ctxt.vf_num = 0;
4530
4531                 /* Update VSI parameters */
4532                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4533                 if (ret != I40E_SUCCESS) {
4534                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4535                         goto fail_msix_alloc;
4536                 }
4537
4538                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4539                                                 sizeof(vsi->info.tc_mapping));
4540                 (void)rte_memcpy(&vsi->info.queue_mapping,
4541                                 &ctxt.info.queue_mapping,
4542                         sizeof(vsi->info.queue_mapping));
4543                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4544                 vsi->info.valid_sections = 0;
4545
4546                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4547                                 ETH_ADDR_LEN);
4548
4549                 /**
4550                  * Updating default filter settings are necessary to prevent
4551                  * reception of tagged packets.
4552                  * Some old firmware configurations load a default macvlan
4553                  * filter which accepts both tagged and untagged packets.
4554                  * The updating is to use a normal filter instead if needed.
4555                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4556                  * The firmware with correct configurations load the default
4557                  * macvlan filter which is expected and cannot be removed.
4558                  */
4559                 i40e_update_default_filter_setting(vsi);
4560                 i40e_config_qinq(hw, vsi);
4561         } else if (type == I40E_VSI_SRIOV) {
4562                 memset(&ctxt, 0, sizeof(ctxt));
4563                 /**
4564                  * For other VSI, the uplink_seid equals to uplink VSI's
4565                  * uplink_seid since they share same VEB
4566                  */
4567                 if (uplink_vsi == NULL)
4568                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4569                 else
4570                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4571                 ctxt.pf_num = hw->pf_id;
4572                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4573                 ctxt.uplink_seid = vsi->uplink_seid;
4574                 ctxt.connection_type = 0x1;
4575                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4576
4577                 /* Use the VEB configuration if FW >= v5.0 */
4578                 if (hw->aq.fw_maj_ver >= 5) {
4579                         /* Configure switch ID */
4580                         ctxt.info.valid_sections |=
4581                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4582                         ctxt.info.switch_id =
4583                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4584                 }
4585
4586                 /* Configure port/vlan */
4587                 ctxt.info.valid_sections |=
4588                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4589                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4590                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4591                                                 I40E_DEFAULT_TCMAP);
4592                 if (ret != I40E_SUCCESS) {
4593                         PMD_DRV_LOG(ERR, "Failed to configure "
4594                                     "TC queue mapping");
4595                         goto fail_msix_alloc;
4596                 }
4597                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4598                 ctxt.info.valid_sections |=
4599                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4600                 /**
4601                  * Since VSI is not created yet, only configure parameter,
4602                  * will add vsi below.
4603                  */
4604
4605                 i40e_config_qinq(hw, vsi);
4606         } else if (type == I40E_VSI_VMDQ2) {
4607                 memset(&ctxt, 0, sizeof(ctxt));
4608                 /*
4609                  * For other VSI, the uplink_seid equals to uplink VSI's
4610                  * uplink_seid since they share same VEB
4611                  */
4612                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4613                 ctxt.pf_num = hw->pf_id;
4614                 ctxt.vf_num = 0;
4615                 ctxt.uplink_seid = vsi->uplink_seid;
4616                 ctxt.connection_type = 0x1;
4617                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4618
4619                 ctxt.info.valid_sections |=
4620                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4621                 /* user_param carries flag to enable loop back */
4622                 if (user_param) {
4623                         ctxt.info.switch_id =
4624                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4625                         ctxt.info.switch_id |=
4626                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4627                 }
4628
4629                 /* Configure port/vlan */
4630                 ctxt.info.valid_sections |=
4631                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4632                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4633                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4634                                                 I40E_DEFAULT_TCMAP);
4635                 if (ret != I40E_SUCCESS) {
4636                         PMD_DRV_LOG(ERR, "Failed to configure "
4637                                         "TC queue mapping");
4638                         goto fail_msix_alloc;
4639                 }
4640                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4641                 ctxt.info.valid_sections |=
4642                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4643         } else if (type == I40E_VSI_FDIR) {
4644                 memset(&ctxt, 0, sizeof(ctxt));
4645                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4646                 ctxt.pf_num = hw->pf_id;
4647                 ctxt.vf_num = 0;
4648                 ctxt.uplink_seid = vsi->uplink_seid;
4649                 ctxt.connection_type = 0x1;     /* regular data port */
4650                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4651                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4652                                                 I40E_DEFAULT_TCMAP);
4653                 if (ret != I40E_SUCCESS) {
4654                         PMD_DRV_LOG(ERR, "Failed to configure "
4655                                         "TC queue mapping.");
4656                         goto fail_msix_alloc;
4657                 }
4658                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4659                 ctxt.info.valid_sections |=
4660                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4661         } else {
4662                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4663                 goto fail_msix_alloc;
4664         }
4665
4666         if (vsi->type != I40E_VSI_MAIN) {
4667                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4668                 if (ret != I40E_SUCCESS) {
4669                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4670                                     hw->aq.asq_last_status);
4671                         goto fail_msix_alloc;
4672                 }
4673                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4674                 vsi->info.valid_sections = 0;
4675                 vsi->seid = ctxt.seid;
4676                 vsi->vsi_id = ctxt.vsi_number;
4677                 vsi->sib_vsi_list.vsi = vsi;
4678                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4679                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4680                                           &vsi->sib_vsi_list, list);
4681                 } else {
4682                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4683                                           &vsi->sib_vsi_list, list);
4684                 }
4685         }
4686
4687         /* MAC/VLAN configuration */
4688         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4689         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4690
4691         ret = i40e_vsi_add_mac(vsi, &filter);
4692         if (ret != I40E_SUCCESS) {
4693                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4694                 goto fail_msix_alloc;
4695         }
4696
4697         /* Get VSI BW information */
4698         i40e_vsi_get_bw_config(vsi);
4699         return vsi;
4700 fail_msix_alloc:
4701         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4702 fail_queue_alloc:
4703         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4704 fail_mem:
4705         rte_free(vsi);
4706         return NULL;
4707 }
4708
4709 /* Configure vlan filter on or off */
4710 int
4711 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4712 {
4713         int i, num;
4714         struct i40e_mac_filter *f;
4715         void *temp;
4716         struct i40e_mac_filter_info *mac_filter;
4717         enum rte_mac_filter_type desired_filter;
4718         int ret = I40E_SUCCESS;
4719
4720         if (on) {
4721                 /* Filter to match MAC and VLAN */
4722                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4723         } else {
4724                 /* Filter to match only MAC */
4725                 desired_filter = RTE_MAC_PERFECT_MATCH;
4726         }
4727
4728         num = vsi->mac_num;
4729
4730         mac_filter = rte_zmalloc("mac_filter_info_data",
4731                                  num * sizeof(*mac_filter), 0);
4732         if (mac_filter == NULL) {
4733                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4734                 return I40E_ERR_NO_MEMORY;
4735         }
4736
4737         i = 0;
4738
4739         /* Remove all existing mac */
4740         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4741                 mac_filter[i] = f->mac_info;
4742                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4743                 if (ret) {
4744                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4745                                     on ? "enable" : "disable");
4746                         goto DONE;
4747                 }
4748                 i++;
4749         }
4750
4751         /* Override with new filter */
4752         for (i = 0; i < num; i++) {
4753                 mac_filter[i].filter_type = desired_filter;
4754                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4755                 if (ret) {
4756                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4757                                     on ? "enable" : "disable");
4758                         goto DONE;
4759                 }
4760         }
4761
4762 DONE:
4763         rte_free(mac_filter);
4764         return ret;
4765 }
4766
4767 /* Configure vlan stripping on or off */
4768 int
4769 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4770 {
4771         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4772         struct i40e_vsi_context ctxt;
4773         uint8_t vlan_flags;
4774         int ret = I40E_SUCCESS;
4775
4776         /* Check if it has been already on or off */
4777         if (vsi->info.valid_sections &
4778                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4779                 if (on) {
4780                         if ((vsi->info.port_vlan_flags &
4781                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4782                                 return 0; /* already on */
4783                 } else {
4784                         if ((vsi->info.port_vlan_flags &
4785                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4786                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4787                                 return 0; /* already off */
4788                 }
4789         }
4790
4791         if (on)
4792                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4793         else
4794                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4795         vsi->info.valid_sections =
4796                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4797         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4798         vsi->info.port_vlan_flags |= vlan_flags;
4799         ctxt.seid = vsi->seid;
4800         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4801         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4802         if (ret)
4803                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4804                             on ? "enable" : "disable");
4805
4806         return ret;
4807 }
4808
4809 static int
4810 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4811 {
4812         struct rte_eth_dev_data *data = dev->data;
4813         int ret;
4814         int mask = 0;
4815
4816         /* Apply vlan offload setting */
4817         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4818         i40e_vlan_offload_set(dev, mask);
4819
4820         /* Apply double-vlan setting, not implemented yet */
4821
4822         /* Apply pvid setting */
4823         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4824                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4825         if (ret)
4826                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4827
4828         return ret;
4829 }
4830
4831 static int
4832 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4833 {
4834         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4835
4836         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4837 }
4838
4839 static int
4840 i40e_update_flow_control(struct i40e_hw *hw)
4841 {
4842 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4843         struct i40e_link_status link_status;
4844         uint32_t rxfc = 0, txfc = 0, reg;
4845         uint8_t an_info;
4846         int ret;
4847
4848         memset(&link_status, 0, sizeof(link_status));
4849         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4850         if (ret != I40E_SUCCESS) {
4851                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4852                 goto write_reg; /* Disable flow control */
4853         }
4854
4855         an_info = hw->phy.link_info.an_info;
4856         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4857                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4858                 ret = I40E_ERR_NOT_READY;
4859                 goto write_reg; /* Disable flow control */
4860         }
4861         /**
4862          * If link auto negotiation is enabled, flow control needs to
4863          * be configured according to it
4864          */
4865         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4866         case I40E_LINK_PAUSE_RXTX:
4867                 rxfc = 1;
4868                 txfc = 1;
4869                 hw->fc.current_mode = I40E_FC_FULL;
4870                 break;
4871         case I40E_AQ_LINK_PAUSE_RX:
4872                 rxfc = 1;
4873                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4874                 break;
4875         case I40E_AQ_LINK_PAUSE_TX:
4876                 txfc = 1;
4877                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4878                 break;
4879         default:
4880                 hw->fc.current_mode = I40E_FC_NONE;
4881                 break;
4882         }
4883
4884 write_reg:
4885         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4886                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4887         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4888         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4889         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4890         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4891
4892         return ret;
4893 }
4894
4895 /* PF setup */
4896 static int
4897 i40e_pf_setup(struct i40e_pf *pf)
4898 {
4899         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4900         struct i40e_filter_control_settings settings;
4901         struct i40e_vsi *vsi;
4902         int ret;
4903
4904         /* Clear all stats counters */
4905         pf->offset_loaded = FALSE;
4906         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4907         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4908
4909         ret = i40e_pf_get_switch_config(pf);
4910         if (ret != I40E_SUCCESS) {
4911                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4912                 return ret;
4913         }
4914         if (pf->flags & I40E_FLAG_FDIR) {
4915                 /* make queue allocated first, let FDIR use queue pair 0*/
4916                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4917                 if (ret != I40E_FDIR_QUEUE_ID) {
4918                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4919                                     " ret =%d", ret);
4920                         pf->flags &= ~I40E_FLAG_FDIR;
4921                 }
4922         }
4923         /*  main VSI setup */
4924         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4925         if (!vsi) {
4926                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4927                 return I40E_ERR_NOT_READY;
4928         }
4929         pf->main_vsi = vsi;
4930
4931         /* Configure filter control */
4932         memset(&settings, 0, sizeof(settings));
4933         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4934                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4935         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4936                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4937         else {
4938                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4939                                                 hw->func_caps.rss_table_size);
4940                 return I40E_ERR_PARAM;
4941         }
4942         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4943                         "size: %u\n", hw->func_caps.rss_table_size);
4944         pf->hash_lut_size = hw->func_caps.rss_table_size;
4945
4946         /* Enable ethtype and macvlan filters */
4947         settings.enable_ethtype = TRUE;
4948         settings.enable_macvlan = TRUE;
4949         ret = i40e_set_filter_control(hw, &settings);
4950         if (ret)
4951                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4952                                                                 ret);
4953
4954         /* Update flow control according to the auto negotiation */
4955         i40e_update_flow_control(hw);
4956
4957         return I40E_SUCCESS;
4958 }
4959
4960 int
4961 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4962 {
4963         uint32_t reg;
4964         uint16_t j;
4965
4966         /**
4967          * Set or clear TX Queue Disable flags,
4968          * which is required by hardware.
4969          */
4970         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4971         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4972
4973         /* Wait until the request is finished */
4974         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4975                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4976                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4977                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4978                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4979                                                         & 0x1))) {
4980                         break;
4981                 }
4982         }
4983         if (on) {
4984                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4985                         return I40E_SUCCESS; /* already on, skip next steps */
4986
4987                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4988                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4989         } else {
4990                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4991                         return I40E_SUCCESS; /* already off, skip next steps */
4992                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4993         }
4994         /* Write the register */
4995         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4996         /* Check the result */
4997         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4998                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4999                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5000                 if (on) {
5001                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5002                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5003                                 break;
5004                 } else {
5005                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5006                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5007                                 break;
5008                 }
5009         }
5010         /* Check if it is timeout */
5011         if (j >= I40E_CHK_Q_ENA_COUNT) {
5012                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5013                             (on ? "enable" : "disable"), q_idx);
5014                 return I40E_ERR_TIMEOUT;
5015         }
5016
5017         return I40E_SUCCESS;
5018 }
5019
5020 /* Swith on or off the tx queues */
5021 static int
5022 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5023 {
5024         struct rte_eth_dev_data *dev_data = pf->dev_data;
5025         struct i40e_tx_queue *txq;
5026         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5027         uint16_t i;
5028         int ret;
5029
5030         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5031                 txq = dev_data->tx_queues[i];
5032                 /* Don't operate the queue if not configured or
5033                  * if starting only per queue */
5034                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5035                         continue;
5036                 if (on)
5037                         ret = i40e_dev_tx_queue_start(dev, i);
5038                 else
5039                         ret = i40e_dev_tx_queue_stop(dev, i);
5040                 if ( ret != I40E_SUCCESS)
5041                         return ret;
5042         }
5043
5044         return I40E_SUCCESS;
5045 }
5046
5047 int
5048 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5049 {
5050         uint32_t reg;
5051         uint16_t j;
5052
5053         /* Wait until the request is finished */
5054         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5055                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5056                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5057                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5058                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5059                         break;
5060         }
5061
5062         if (on) {
5063                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5064                         return I40E_SUCCESS; /* Already on, skip next steps */
5065                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5066         } else {
5067                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5068                         return I40E_SUCCESS; /* Already off, skip next steps */
5069                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5070         }
5071
5072         /* Write the register */
5073         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5074         /* Check the result */
5075         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5076                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5077                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5078                 if (on) {
5079                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5080                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5081                                 break;
5082                 } else {
5083                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5084                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5085                                 break;
5086                 }
5087         }
5088
5089         /* Check if it is timeout */
5090         if (j >= I40E_CHK_Q_ENA_COUNT) {
5091                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5092                             (on ? "enable" : "disable"), q_idx);
5093                 return I40E_ERR_TIMEOUT;
5094         }
5095
5096         return I40E_SUCCESS;
5097 }
5098 /* Switch on or off the rx queues */
5099 static int
5100 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5101 {
5102         struct rte_eth_dev_data *dev_data = pf->dev_data;
5103         struct i40e_rx_queue *rxq;
5104         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5105         uint16_t i;
5106         int ret;
5107
5108         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5109                 rxq = dev_data->rx_queues[i];
5110                 /* Don't operate the queue if not configured or
5111                  * if starting only per queue */
5112                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5113                         continue;
5114                 if (on)
5115                         ret = i40e_dev_rx_queue_start(dev, i);
5116                 else
5117                         ret = i40e_dev_rx_queue_stop(dev, i);
5118                 if (ret != I40E_SUCCESS)
5119                         return ret;
5120         }
5121
5122         return I40E_SUCCESS;
5123 }
5124
5125 /* Switch on or off all the rx/tx queues */
5126 int
5127 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5128 {
5129         int ret;
5130
5131         if (on) {
5132                 /* enable rx queues before enabling tx queues */
5133                 ret = i40e_dev_switch_rx_queues(pf, on);
5134                 if (ret) {
5135                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5136                         return ret;
5137                 }
5138                 ret = i40e_dev_switch_tx_queues(pf, on);
5139         } else {
5140                 /* Stop tx queues before stopping rx queues */
5141                 ret = i40e_dev_switch_tx_queues(pf, on);
5142                 if (ret) {
5143                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5144                         return ret;
5145                 }
5146                 ret = i40e_dev_switch_rx_queues(pf, on);
5147         }
5148
5149         return ret;
5150 }
5151
5152 /* Initialize VSI for TX */
5153 static int
5154 i40e_dev_tx_init(struct i40e_pf *pf)
5155 {
5156         struct rte_eth_dev_data *data = pf->dev_data;
5157         uint16_t i;
5158         uint32_t ret = I40E_SUCCESS;
5159         struct i40e_tx_queue *txq;
5160
5161         for (i = 0; i < data->nb_tx_queues; i++) {
5162                 txq = data->tx_queues[i];
5163                 if (!txq || !txq->q_set)
5164                         continue;
5165                 ret = i40e_tx_queue_init(txq);
5166                 if (ret != I40E_SUCCESS)
5167                         break;
5168         }
5169         if (ret == I40E_SUCCESS)
5170                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5171                                      ->eth_dev);
5172
5173         return ret;
5174 }
5175
5176 /* Initialize VSI for RX */
5177 static int
5178 i40e_dev_rx_init(struct i40e_pf *pf)
5179 {
5180         struct rte_eth_dev_data *data = pf->dev_data;
5181         int ret = I40E_SUCCESS;
5182         uint16_t i;
5183         struct i40e_rx_queue *rxq;
5184
5185         i40e_pf_config_mq_rx(pf);
5186         for (i = 0; i < data->nb_rx_queues; i++) {
5187                 rxq = data->rx_queues[i];
5188                 if (!rxq || !rxq->q_set)
5189                         continue;
5190
5191                 ret = i40e_rx_queue_init(rxq);
5192                 if (ret != I40E_SUCCESS) {
5193                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5194                                     "initialization");
5195                         break;
5196                 }
5197         }
5198         if (ret == I40E_SUCCESS)
5199                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5200                                      ->eth_dev);
5201
5202         return ret;
5203 }
5204
5205 static int
5206 i40e_dev_rxtx_init(struct i40e_pf *pf)
5207 {
5208         int err;
5209
5210         err = i40e_dev_tx_init(pf);
5211         if (err) {
5212                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5213                 return err;
5214         }
5215         err = i40e_dev_rx_init(pf);
5216         if (err) {
5217                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5218                 return err;
5219         }
5220
5221         return err;
5222 }
5223
5224 static int
5225 i40e_vmdq_setup(struct rte_eth_dev *dev)
5226 {
5227         struct rte_eth_conf *conf = &dev->data->dev_conf;
5228         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5229         int i, err, conf_vsis, j, loop;
5230         struct i40e_vsi *vsi;
5231         struct i40e_vmdq_info *vmdq_info;
5232         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5233         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5234
5235         /*
5236          * Disable interrupt to avoid message from VF. Furthermore, it will
5237          * avoid race condition in VSI creation/destroy.
5238          */
5239         i40e_pf_disable_irq0(hw);
5240
5241         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5242                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5243                 return -ENOTSUP;
5244         }
5245
5246         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5247         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5248                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5249                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5250                         pf->max_nb_vmdq_vsi);
5251                 return -ENOTSUP;
5252         }
5253
5254         if (pf->vmdq != NULL) {
5255                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5256                 return 0;
5257         }
5258
5259         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5260                                 sizeof(*vmdq_info) * conf_vsis, 0);
5261
5262         if (pf->vmdq == NULL) {
5263                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5264                 return -ENOMEM;
5265         }
5266
5267         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5268
5269         /* Create VMDQ VSI */
5270         for (i = 0; i < conf_vsis; i++) {
5271                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5272                                 vmdq_conf->enable_loop_back);
5273                 if (vsi == NULL) {
5274                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5275                         err = -1;
5276                         goto err_vsi_setup;
5277                 }
5278                 vmdq_info = &pf->vmdq[i];
5279                 vmdq_info->pf = pf;
5280                 vmdq_info->vsi = vsi;
5281         }
5282         pf->nb_cfg_vmdq_vsi = conf_vsis;
5283
5284         /* Configure Vlan */
5285         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5286         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5287                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5288                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5289                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5290                                         vmdq_conf->pool_map[i].vlan_id, j);
5291
5292                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5293                                                 vmdq_conf->pool_map[i].vlan_id);
5294                                 if (err) {
5295                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5296                                         err = -1;
5297                                         goto err_vsi_setup;
5298                                 }
5299                         }
5300                 }
5301         }
5302
5303         i40e_pf_enable_irq0(hw);
5304
5305         return 0;
5306
5307 err_vsi_setup:
5308         for (i = 0; i < conf_vsis; i++)
5309                 if (pf->vmdq[i].vsi == NULL)
5310                         break;
5311                 else
5312                         i40e_vsi_release(pf->vmdq[i].vsi);
5313
5314         rte_free(pf->vmdq);
5315         pf->vmdq = NULL;
5316         i40e_pf_enable_irq0(hw);
5317         return err;
5318 }
5319
5320 static void
5321 i40e_stat_update_32(struct i40e_hw *hw,
5322                    uint32_t reg,
5323                    bool offset_loaded,
5324                    uint64_t *offset,
5325                    uint64_t *stat)
5326 {
5327         uint64_t new_data;
5328
5329         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5330         if (!offset_loaded)
5331                 *offset = new_data;
5332
5333         if (new_data >= *offset)
5334                 *stat = (uint64_t)(new_data - *offset);
5335         else
5336                 *stat = (uint64_t)((new_data +
5337                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5338 }
5339
5340 static void
5341 i40e_stat_update_48(struct i40e_hw *hw,
5342                    uint32_t hireg,
5343                    uint32_t loreg,
5344                    bool offset_loaded,
5345                    uint64_t *offset,
5346                    uint64_t *stat)
5347 {
5348         uint64_t new_data;
5349
5350         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5351         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5352                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5353
5354         if (!offset_loaded)
5355                 *offset = new_data;
5356
5357         if (new_data >= *offset)
5358                 *stat = new_data - *offset;
5359         else
5360                 *stat = (uint64_t)((new_data +
5361                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5362
5363         *stat &= I40E_48_BIT_MASK;
5364 }
5365
5366 /* Disable IRQ0 */
5367 void
5368 i40e_pf_disable_irq0(struct i40e_hw *hw)
5369 {
5370         /* Disable all interrupt types */
5371         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5372         I40E_WRITE_FLUSH(hw);
5373 }
5374
5375 /* Enable IRQ0 */
5376 void
5377 i40e_pf_enable_irq0(struct i40e_hw *hw)
5378 {
5379         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5380                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5381                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5382                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5383         I40E_WRITE_FLUSH(hw);
5384 }
5385
5386 static void
5387 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5388 {
5389         /* read pending request and disable first */
5390         i40e_pf_disable_irq0(hw);
5391         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5392         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5393                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5394
5395         if (no_queue)
5396                 /* Link no queues with irq0 */
5397                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5398                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5399 }
5400
5401 static void
5402 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5403 {
5404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5406         int i;
5407         uint16_t abs_vf_id;
5408         uint32_t index, offset, val;
5409
5410         if (!pf->vfs)
5411                 return;
5412         /**
5413          * Try to find which VF trigger a reset, use absolute VF id to access
5414          * since the reg is global register.
5415          */
5416         for (i = 0; i < pf->vf_num; i++) {
5417                 abs_vf_id = hw->func_caps.vf_base_id + i;
5418                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5419                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5420                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5421                 /* VFR event occured */
5422                 if (val & (0x1 << offset)) {
5423                         int ret;
5424
5425                         /* Clear the event first */
5426                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5427                                                         (0x1 << offset));
5428                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5429                         /**
5430                          * Only notify a VF reset event occured,
5431                          * don't trigger another SW reset
5432                          */
5433                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5434                         if (ret != I40E_SUCCESS)
5435                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5436                 }
5437         }
5438 }
5439
5440 static void
5441 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5442 {
5443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5444         struct i40e_virtchnl_pf_event event;
5445         int i;
5446
5447         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5448         event.event_data.link_event.link_status =
5449                 dev->data->dev_link.link_status;
5450         event.event_data.link_event.link_speed =
5451                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5452
5453         for (i = 0; i < pf->vf_num; i++)
5454                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5455                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5456 }
5457
5458 static void
5459 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5460 {
5461         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5462         struct i40e_arq_event_info info;
5463         uint16_t pending, opcode;
5464         int ret;
5465
5466         info.buf_len = I40E_AQ_BUF_SZ;
5467         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5468         if (!info.msg_buf) {
5469                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5470                 return;
5471         }
5472
5473         pending = 1;
5474         while (pending) {
5475                 ret = i40e_clean_arq_element(hw, &info, &pending);
5476
5477                 if (ret != I40E_SUCCESS) {
5478                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5479                                     "aq_err: %u", hw->aq.asq_last_status);
5480                         break;
5481                 }
5482                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5483
5484                 switch (opcode) {
5485                 case i40e_aqc_opc_send_msg_to_pf:
5486                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5487                         i40e_pf_host_handle_vf_msg(dev,
5488                                         rte_le_to_cpu_16(info.desc.retval),
5489                                         rte_le_to_cpu_32(info.desc.cookie_high),
5490                                         rte_le_to_cpu_32(info.desc.cookie_low),
5491                                         info.msg_buf,
5492                                         info.msg_len);
5493                         break;
5494                 case i40e_aqc_opc_get_link_status:
5495                         ret = i40e_dev_link_update(dev, 0);
5496                         if (!ret) {
5497                                 i40e_notify_all_vfs_link_status(dev);
5498                                 _rte_eth_dev_callback_process(dev,
5499                                         RTE_ETH_EVENT_INTR_LSC);
5500                         }
5501                         break;
5502                 default:
5503                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5504                                     opcode);
5505                         break;
5506                 }
5507         }
5508         rte_free(info.msg_buf);
5509 }
5510
5511 /**
5512  * Interrupt handler triggered by NIC  for handling
5513  * specific interrupt.
5514  *
5515  * @param handle
5516  *  Pointer to interrupt handle.
5517  * @param param
5518  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5519  *
5520  * @return
5521  *  void
5522  */
5523 static void
5524 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5525                            void *param)
5526 {
5527         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5528         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5529         uint32_t icr0;
5530
5531         /* Disable interrupt */
5532         i40e_pf_disable_irq0(hw);
5533
5534         /* read out interrupt causes */
5535         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5536
5537         /* No interrupt event indicated */
5538         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5539                 PMD_DRV_LOG(INFO, "No interrupt event");
5540                 goto done;
5541         }
5542 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5543         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5544                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5545         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5546                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5547         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5548                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5549         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5550                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5551         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5552                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5553         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5554                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5555         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5556                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5557 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5558
5559         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5560                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5561                 i40e_dev_handle_vfr_event(dev);
5562         }
5563         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5564                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5565                 i40e_dev_handle_aq_msg(dev);
5566         }
5567 done:
5568         /* Enable interrupt */
5569         i40e_pf_enable_irq0(hw);
5570         rte_intr_enable(&(dev->pci_dev->intr_handle));
5571 }
5572
5573 static int
5574 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5575                          struct i40e_macvlan_filter *filter,
5576                          int total)
5577 {
5578         int ele_num, ele_buff_size;
5579         int num, actual_num, i;
5580         uint16_t flags;
5581         int ret = I40E_SUCCESS;
5582         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5583         struct i40e_aqc_add_macvlan_element_data *req_list;
5584
5585         if (filter == NULL  || total == 0)
5586                 return I40E_ERR_PARAM;
5587         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5588         ele_buff_size = hw->aq.asq_buf_size;
5589
5590         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5591         if (req_list == NULL) {
5592                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5593                 return I40E_ERR_NO_MEMORY;
5594         }
5595
5596         num = 0;
5597         do {
5598                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5599                 memset(req_list, 0, ele_buff_size);
5600
5601                 for (i = 0; i < actual_num; i++) {
5602                         (void)rte_memcpy(req_list[i].mac_addr,
5603                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5604                         req_list[i].vlan_tag =
5605                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5606
5607                         switch (filter[num + i].filter_type) {
5608                         case RTE_MAC_PERFECT_MATCH:
5609                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5610                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5611                                 break;
5612                         case RTE_MACVLAN_PERFECT_MATCH:
5613                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5614                                 break;
5615                         case RTE_MAC_HASH_MATCH:
5616                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5617                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5618                                 break;
5619                         case RTE_MACVLAN_HASH_MATCH:
5620                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5621                                 break;
5622                         default:
5623                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5624                                 ret = I40E_ERR_PARAM;
5625                                 goto DONE;
5626                         }
5627
5628                         req_list[i].queue_number = 0;
5629
5630                         req_list[i].flags = rte_cpu_to_le_16(flags);
5631                 }
5632
5633                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5634                                                 actual_num, NULL);
5635                 if (ret != I40E_SUCCESS) {
5636                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5637                         goto DONE;
5638                 }
5639                 num += actual_num;
5640         } while (num < total);
5641
5642 DONE:
5643         rte_free(req_list);
5644         return ret;
5645 }
5646
5647 static int
5648 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5649                             struct i40e_macvlan_filter *filter,
5650                             int total)
5651 {
5652         int ele_num, ele_buff_size;
5653         int num, actual_num, i;
5654         uint16_t flags;
5655         int ret = I40E_SUCCESS;
5656         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5657         struct i40e_aqc_remove_macvlan_element_data *req_list;
5658
5659         if (filter == NULL  || total == 0)
5660                 return I40E_ERR_PARAM;
5661
5662         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5663         ele_buff_size = hw->aq.asq_buf_size;
5664
5665         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5666         if (req_list == NULL) {
5667                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5668                 return I40E_ERR_NO_MEMORY;
5669         }
5670
5671         num = 0;
5672         do {
5673                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5674                 memset(req_list, 0, ele_buff_size);
5675
5676                 for (i = 0; i < actual_num; i++) {
5677                         (void)rte_memcpy(req_list[i].mac_addr,
5678                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5679                         req_list[i].vlan_tag =
5680                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5681
5682                         switch (filter[num + i].filter_type) {
5683                         case RTE_MAC_PERFECT_MATCH:
5684                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5685                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5686                                 break;
5687                         case RTE_MACVLAN_PERFECT_MATCH:
5688                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5689                                 break;
5690                         case RTE_MAC_HASH_MATCH:
5691                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5692                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5693                                 break;
5694                         case RTE_MACVLAN_HASH_MATCH:
5695                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5696                                 break;
5697                         default:
5698                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5699                                 ret = I40E_ERR_PARAM;
5700                                 goto DONE;
5701                         }
5702                         req_list[i].flags = rte_cpu_to_le_16(flags);
5703                 }
5704
5705                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5706                                                 actual_num, NULL);
5707                 if (ret != I40E_SUCCESS) {
5708                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5709                         goto DONE;
5710                 }
5711                 num += actual_num;
5712         } while (num < total);
5713
5714 DONE:
5715         rte_free(req_list);
5716         return ret;
5717 }
5718
5719 /* Find out specific MAC filter */
5720 static struct i40e_mac_filter *
5721 i40e_find_mac_filter(struct i40e_vsi *vsi,
5722                          struct ether_addr *macaddr)
5723 {
5724         struct i40e_mac_filter *f;
5725
5726         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5727                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5728                         return f;
5729         }
5730
5731         return NULL;
5732 }
5733
5734 static bool
5735 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5736                          uint16_t vlan_id)
5737 {
5738         uint32_t vid_idx, vid_bit;
5739
5740         if (vlan_id > ETH_VLAN_ID_MAX)
5741                 return 0;
5742
5743         vid_idx = I40E_VFTA_IDX(vlan_id);
5744         vid_bit = I40E_VFTA_BIT(vlan_id);
5745
5746         if (vsi->vfta[vid_idx] & vid_bit)
5747                 return 1;
5748         else
5749                 return 0;
5750 }
5751
5752 static void
5753 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5754                          uint16_t vlan_id, bool on)
5755 {
5756         uint32_t vid_idx, vid_bit;
5757
5758         if (vlan_id > ETH_VLAN_ID_MAX)
5759                 return;
5760
5761         vid_idx = I40E_VFTA_IDX(vlan_id);
5762         vid_bit = I40E_VFTA_BIT(vlan_id);
5763
5764         if (on)
5765                 vsi->vfta[vid_idx] |= vid_bit;
5766         else
5767                 vsi->vfta[vid_idx] &= ~vid_bit;
5768 }
5769
5770 /**
5771  * Find all vlan options for specific mac addr,
5772  * return with actual vlan found.
5773  */
5774 static inline int
5775 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5776                            struct i40e_macvlan_filter *mv_f,
5777                            int num, struct ether_addr *addr)
5778 {
5779         int i;
5780         uint32_t j, k;
5781
5782         /**
5783          * Not to use i40e_find_vlan_filter to decrease the loop time,
5784          * although the code looks complex.
5785           */
5786         if (num < vsi->vlan_num)
5787                 return I40E_ERR_PARAM;
5788
5789         i = 0;
5790         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5791                 if (vsi->vfta[j]) {
5792                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5793                                 if (vsi->vfta[j] & (1 << k)) {
5794                                         if (i > num - 1) {
5795                                                 PMD_DRV_LOG(ERR, "vlan number "
5796                                                             "not match");
5797                                                 return I40E_ERR_PARAM;
5798                                         }
5799                                         (void)rte_memcpy(&mv_f[i].macaddr,
5800                                                         addr, ETH_ADDR_LEN);
5801                                         mv_f[i].vlan_id =
5802                                                 j * I40E_UINT32_BIT_SIZE + k;
5803                                         i++;
5804                                 }
5805                         }
5806                 }
5807         }
5808         return I40E_SUCCESS;
5809 }
5810
5811 static inline int
5812 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5813                            struct i40e_macvlan_filter *mv_f,
5814                            int num,
5815                            uint16_t vlan)
5816 {
5817         int i = 0;
5818         struct i40e_mac_filter *f;
5819
5820         if (num < vsi->mac_num)
5821                 return I40E_ERR_PARAM;
5822
5823         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5824                 if (i > num - 1) {
5825                         PMD_DRV_LOG(ERR, "buffer number not match");
5826                         return I40E_ERR_PARAM;
5827                 }
5828                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5829                                 ETH_ADDR_LEN);
5830                 mv_f[i].vlan_id = vlan;
5831                 mv_f[i].filter_type = f->mac_info.filter_type;
5832                 i++;
5833         }
5834
5835         return I40E_SUCCESS;
5836 }
5837
5838 static int
5839 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5840 {
5841         int i, num;
5842         struct i40e_mac_filter *f;
5843         struct i40e_macvlan_filter *mv_f;
5844         int ret = I40E_SUCCESS;
5845
5846         if (vsi == NULL || vsi->mac_num == 0)
5847                 return I40E_ERR_PARAM;
5848
5849         /* Case that no vlan is set */
5850         if (vsi->vlan_num == 0)
5851                 num = vsi->mac_num;
5852         else
5853                 num = vsi->mac_num * vsi->vlan_num;
5854
5855         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5856         if (mv_f == NULL) {
5857                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5858                 return I40E_ERR_NO_MEMORY;
5859         }
5860
5861         i = 0;
5862         if (vsi->vlan_num == 0) {
5863                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5864                         (void)rte_memcpy(&mv_f[i].macaddr,
5865                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5866                         mv_f[i].vlan_id = 0;
5867                         i++;
5868                 }
5869         } else {
5870                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5871                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5872                                         vsi->vlan_num, &f->mac_info.mac_addr);
5873                         if (ret != I40E_SUCCESS)
5874                                 goto DONE;
5875                         i += vsi->vlan_num;
5876                 }
5877         }
5878
5879         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5880 DONE:
5881         rte_free(mv_f);
5882
5883         return ret;
5884 }
5885
5886 int
5887 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5888 {
5889         struct i40e_macvlan_filter *mv_f;
5890         int mac_num;
5891         int ret = I40E_SUCCESS;
5892
5893         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5894                 return I40E_ERR_PARAM;
5895
5896         /* If it's already set, just return */
5897         if (i40e_find_vlan_filter(vsi,vlan))
5898                 return I40E_SUCCESS;
5899
5900         mac_num = vsi->mac_num;
5901
5902         if (mac_num == 0) {
5903                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5904                 return I40E_ERR_PARAM;
5905         }
5906
5907         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5908
5909         if (mv_f == NULL) {
5910                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5911                 return I40E_ERR_NO_MEMORY;
5912         }
5913
5914         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5915
5916         if (ret != I40E_SUCCESS)
5917                 goto DONE;
5918
5919         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5920
5921         if (ret != I40E_SUCCESS)
5922                 goto DONE;
5923
5924         i40e_set_vlan_filter(vsi, vlan, 1);
5925
5926         vsi->vlan_num++;
5927         ret = I40E_SUCCESS;
5928 DONE:
5929         rte_free(mv_f);
5930         return ret;
5931 }
5932
5933 int
5934 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5935 {
5936         struct i40e_macvlan_filter *mv_f;
5937         int mac_num;
5938         int ret = I40E_SUCCESS;
5939
5940         /**
5941          * Vlan 0 is the generic filter for untagged packets
5942          * and can't be removed.
5943          */
5944         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5945                 return I40E_ERR_PARAM;
5946
5947         /* If can't find it, just return */
5948         if (!i40e_find_vlan_filter(vsi, vlan))
5949                 return I40E_ERR_PARAM;
5950
5951         mac_num = vsi->mac_num;
5952
5953         if (mac_num == 0) {
5954                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5955                 return I40E_ERR_PARAM;
5956         }
5957
5958         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5959
5960         if (mv_f == NULL) {
5961                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5962                 return I40E_ERR_NO_MEMORY;
5963         }
5964
5965         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5966
5967         if (ret != I40E_SUCCESS)
5968                 goto DONE;
5969
5970         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5971
5972         if (ret != I40E_SUCCESS)
5973                 goto DONE;
5974
5975         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5976         if (vsi->vlan_num == 1) {
5977                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5978                 if (ret != I40E_SUCCESS)
5979                         goto DONE;
5980
5981                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5982                 if (ret != I40E_SUCCESS)
5983                         goto DONE;
5984         }
5985
5986         i40e_set_vlan_filter(vsi, vlan, 0);
5987
5988         vsi->vlan_num--;
5989         ret = I40E_SUCCESS;
5990 DONE:
5991         rte_free(mv_f);
5992         return ret;
5993 }
5994
5995 int
5996 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5997 {
5998         struct i40e_mac_filter *f;
5999         struct i40e_macvlan_filter *mv_f;
6000         int i, vlan_num = 0;
6001         int ret = I40E_SUCCESS;
6002
6003         /* If it's add and we've config it, return */
6004         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6005         if (f != NULL)
6006                 return I40E_SUCCESS;
6007         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6008                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6009
6010                 /**
6011                  * If vlan_num is 0, that's the first time to add mac,
6012                  * set mask for vlan_id 0.
6013                  */
6014                 if (vsi->vlan_num == 0) {
6015                         i40e_set_vlan_filter(vsi, 0, 1);
6016                         vsi->vlan_num = 1;
6017                 }
6018                 vlan_num = vsi->vlan_num;
6019         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6020                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6021                 vlan_num = 1;
6022
6023         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6024         if (mv_f == NULL) {
6025                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6026                 return I40E_ERR_NO_MEMORY;
6027         }
6028
6029         for (i = 0; i < vlan_num; i++) {
6030                 mv_f[i].filter_type = mac_filter->filter_type;
6031                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6032                                 ETH_ADDR_LEN);
6033         }
6034
6035         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6036                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6037                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6038                                         &mac_filter->mac_addr);
6039                 if (ret != I40E_SUCCESS)
6040                         goto DONE;
6041         }
6042
6043         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6044         if (ret != I40E_SUCCESS)
6045                 goto DONE;
6046
6047         /* Add the mac addr into mac list */
6048         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6049         if (f == NULL) {
6050                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6051                 ret = I40E_ERR_NO_MEMORY;
6052                 goto DONE;
6053         }
6054         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6055                         ETH_ADDR_LEN);
6056         f->mac_info.filter_type = mac_filter->filter_type;
6057         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6058         vsi->mac_num++;
6059
6060         ret = I40E_SUCCESS;
6061 DONE:
6062         rte_free(mv_f);
6063
6064         return ret;
6065 }
6066
6067 int
6068 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6069 {
6070         struct i40e_mac_filter *f;
6071         struct i40e_macvlan_filter *mv_f;
6072         int i, vlan_num;
6073         enum rte_mac_filter_type filter_type;
6074         int ret = I40E_SUCCESS;
6075
6076         /* Can't find it, return an error */
6077         f = i40e_find_mac_filter(vsi, addr);
6078         if (f == NULL)
6079                 return I40E_ERR_PARAM;
6080
6081         vlan_num = vsi->vlan_num;
6082         filter_type = f->mac_info.filter_type;
6083         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6084                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6085                 if (vlan_num == 0) {
6086                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6087                         return I40E_ERR_PARAM;
6088                 }
6089         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6090                         filter_type == RTE_MAC_HASH_MATCH)
6091                 vlan_num = 1;
6092
6093         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6094         if (mv_f == NULL) {
6095                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6096                 return I40E_ERR_NO_MEMORY;
6097         }
6098
6099         for (i = 0; i < vlan_num; i++) {
6100                 mv_f[i].filter_type = filter_type;
6101                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6102                                 ETH_ADDR_LEN);
6103         }
6104         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6105                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6106                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6107                 if (ret != I40E_SUCCESS)
6108                         goto DONE;
6109         }
6110
6111         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6112         if (ret != I40E_SUCCESS)
6113                 goto DONE;
6114
6115         /* Remove the mac addr into mac list */
6116         TAILQ_REMOVE(&vsi->mac_list, f, next);
6117         rte_free(f);
6118         vsi->mac_num--;
6119
6120         ret = I40E_SUCCESS;
6121 DONE:
6122         rte_free(mv_f);
6123         return ret;
6124 }
6125
6126 /* Configure hash enable flags for RSS */
6127 uint64_t
6128 i40e_config_hena(uint64_t flags)
6129 {
6130         uint64_t hena = 0;
6131
6132         if (!flags)
6133                 return hena;
6134
6135         if (flags & ETH_RSS_FRAG_IPV4)
6136                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6137         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6138                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6139         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6140                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6141         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6142                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6143         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6144                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6145         if (flags & ETH_RSS_FRAG_IPV6)
6146                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6147         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6148                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6149         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6150                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6151         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6152                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6153         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6154                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6155         if (flags & ETH_RSS_L2_PAYLOAD)
6156                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6157
6158         return hena;
6159 }
6160
6161 /* Parse the hash enable flags */
6162 uint64_t
6163 i40e_parse_hena(uint64_t flags)
6164 {
6165         uint64_t rss_hf = 0;
6166
6167         if (!flags)
6168                 return rss_hf;
6169         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6170                 rss_hf |= ETH_RSS_FRAG_IPV4;
6171         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6172                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6173         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6174                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6175         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6176                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6177         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6178                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6179         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6180                 rss_hf |= ETH_RSS_FRAG_IPV6;
6181         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6182                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6183         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6184                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6185         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6186                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6187         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6188                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6189         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6190                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6191
6192         return rss_hf;
6193 }
6194
6195 /* Disable RSS */
6196 static void
6197 i40e_pf_disable_rss(struct i40e_pf *pf)
6198 {
6199         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6200         uint64_t hena;
6201
6202         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6203         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6204         hena &= ~I40E_RSS_HENA_ALL;
6205         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6206         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6207         I40E_WRITE_FLUSH(hw);
6208 }
6209
6210 static int
6211 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6212 {
6213         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6214         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6215         int ret = 0;
6216
6217         if (!key || key_len == 0) {
6218                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6219                 return 0;
6220         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6221                 sizeof(uint32_t)) {
6222                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6223                 return -EINVAL;
6224         }
6225
6226         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6227                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6228                         (struct i40e_aqc_get_set_rss_key_data *)key;
6229
6230                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6231                 if (ret)
6232                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6233                                      "via AQ");
6234         } else {
6235                 uint32_t *hash_key = (uint32_t *)key;
6236                 uint16_t i;
6237
6238                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6239                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6240                 I40E_WRITE_FLUSH(hw);
6241         }
6242
6243         return ret;
6244 }
6245
6246 static int
6247 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6248 {
6249         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6250         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6251         int ret;
6252
6253         if (!key || !key_len)
6254                 return -EINVAL;
6255
6256         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6257                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6258                         (struct i40e_aqc_get_set_rss_key_data *)key);
6259                 if (ret) {
6260                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6261                         return ret;
6262                 }
6263         } else {
6264                 uint32_t *key_dw = (uint32_t *)key;
6265                 uint16_t i;
6266
6267                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6268                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6269         }
6270         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6271
6272         return 0;
6273 }
6274
6275 static int
6276 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6277 {
6278         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6279         uint64_t rss_hf;
6280         uint64_t hena;
6281         int ret;
6282
6283         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6284                                rss_conf->rss_key_len);
6285         if (ret)
6286                 return ret;
6287
6288         rss_hf = rss_conf->rss_hf;
6289         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6290         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6291         hena &= ~I40E_RSS_HENA_ALL;
6292         hena |= i40e_config_hena(rss_hf);
6293         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6294         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6295         I40E_WRITE_FLUSH(hw);
6296
6297         return 0;
6298 }
6299
6300 static int
6301 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6302                          struct rte_eth_rss_conf *rss_conf)
6303 {
6304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6306         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6307         uint64_t hena;
6308
6309         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6310         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6311         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6312                 if (rss_hf != 0) /* Enable RSS */
6313                         return -EINVAL;
6314                 return 0; /* Nothing to do */
6315         }
6316         /* RSS enabled */
6317         if (rss_hf == 0) /* Disable RSS */
6318                 return -EINVAL;
6319
6320         return i40e_hw_rss_hash_set(pf, rss_conf);
6321 }
6322
6323 static int
6324 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6325                            struct rte_eth_rss_conf *rss_conf)
6326 {
6327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6328         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6329         uint64_t hena;
6330
6331         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6332                          &rss_conf->rss_key_len);
6333
6334         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6335         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6336         rss_conf->rss_hf = i40e_parse_hena(hena);
6337
6338         return 0;
6339 }
6340
6341 static int
6342 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6343 {
6344         switch (filter_type) {
6345         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6346                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6347                 break;
6348         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6349                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6350                 break;
6351         case RTE_TUNNEL_FILTER_IMAC_TENID:
6352                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6353                 break;
6354         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6355                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6356                 break;
6357         case ETH_TUNNEL_FILTER_IMAC:
6358                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6359                 break;
6360         case ETH_TUNNEL_FILTER_OIP:
6361                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6362                 break;
6363         case ETH_TUNNEL_FILTER_IIP:
6364                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6365                 break;
6366         default:
6367                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6368                 return -EINVAL;
6369         }
6370
6371         return 0;
6372 }
6373
6374 static int
6375 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6376                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6377                         uint8_t add)
6378 {
6379         uint16_t ip_type;
6380         uint32_t ipv4_addr;
6381         uint8_t i, tun_type = 0;
6382         /* internal varialbe to convert ipv6 byte order */
6383         uint32_t convert_ipv6[4];
6384         int val, ret = 0;
6385         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6386         struct i40e_vsi *vsi = pf->main_vsi;
6387         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6388         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6389
6390         cld_filter = rte_zmalloc("tunnel_filter",
6391                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6392                 0);
6393
6394         if (NULL == cld_filter) {
6395                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6396                 return -EINVAL;
6397         }
6398         pfilter = cld_filter;
6399
6400         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6401         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6402
6403         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6404         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6405                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6406                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6407                 rte_memcpy(&pfilter->ipaddr.v4.data,
6408                                 &rte_cpu_to_le_32(ipv4_addr),
6409                                 sizeof(pfilter->ipaddr.v4.data));
6410         } else {
6411                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6412                 for (i = 0; i < 4; i++) {
6413                         convert_ipv6[i] =
6414                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6415                 }
6416                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6417                                 sizeof(pfilter->ipaddr.v6.data));
6418         }
6419
6420         /* check tunneled type */
6421         switch (tunnel_filter->tunnel_type) {
6422         case RTE_TUNNEL_TYPE_VXLAN:
6423                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6424                 break;
6425         case RTE_TUNNEL_TYPE_NVGRE:
6426                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6427                 break;
6428         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6429                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6430                 break;
6431         default:
6432                 /* Other tunnel types is not supported. */
6433                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6434                 rte_free(cld_filter);
6435                 return -EINVAL;
6436         }
6437
6438         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6439                                                 &pfilter->flags);
6440         if (val < 0) {
6441                 rte_free(cld_filter);
6442                 return -EINVAL;
6443         }
6444
6445         pfilter->flags |= rte_cpu_to_le_16(
6446                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6447                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6448         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6449         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6450
6451         if (add)
6452                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6453         else
6454                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6455                                                 cld_filter, 1);
6456
6457         rte_free(cld_filter);
6458         return ret;
6459 }
6460
6461 static int
6462 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6463 {
6464         uint8_t i;
6465
6466         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6467                 if (pf->vxlan_ports[i] == port)
6468                         return i;
6469         }
6470
6471         return -1;
6472 }
6473
6474 static int
6475 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6476 {
6477         int  idx, ret;
6478         uint8_t filter_idx;
6479         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6480
6481         idx = i40e_get_vxlan_port_idx(pf, port);
6482
6483         /* Check if port already exists */
6484         if (idx >= 0) {
6485                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6486                 return -EINVAL;
6487         }
6488
6489         /* Now check if there is space to add the new port */
6490         idx = i40e_get_vxlan_port_idx(pf, 0);
6491         if (idx < 0) {
6492                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6493                         "not adding port %d", port);
6494                 return -ENOSPC;
6495         }
6496
6497         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6498                                         &filter_idx, NULL);
6499         if (ret < 0) {
6500                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6501                 return -1;
6502         }
6503
6504         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6505                          port,  filter_idx);
6506
6507         /* New port: add it and mark its index in the bitmap */
6508         pf->vxlan_ports[idx] = port;
6509         pf->vxlan_bitmap |= (1 << idx);
6510
6511         if (!(pf->flags & I40E_FLAG_VXLAN))
6512                 pf->flags |= I40E_FLAG_VXLAN;
6513
6514         return 0;
6515 }
6516
6517 static int
6518 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6519 {
6520         int idx;
6521         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6522
6523         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6524                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6525                 return -EINVAL;
6526         }
6527
6528         idx = i40e_get_vxlan_port_idx(pf, port);
6529
6530         if (idx < 0) {
6531                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6532                 return -EINVAL;
6533         }
6534
6535         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6536                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6537                 return -1;
6538         }
6539
6540         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6541                         port, idx);
6542
6543         pf->vxlan_ports[idx] = 0;
6544         pf->vxlan_bitmap &= ~(1 << idx);
6545
6546         if (!pf->vxlan_bitmap)
6547                 pf->flags &= ~I40E_FLAG_VXLAN;
6548
6549         return 0;
6550 }
6551
6552 /* Add UDP tunneling port */
6553 static int
6554 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6555                              struct rte_eth_udp_tunnel *udp_tunnel)
6556 {
6557         int ret = 0;
6558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6559
6560         if (udp_tunnel == NULL)
6561                 return -EINVAL;
6562
6563         switch (udp_tunnel->prot_type) {
6564         case RTE_TUNNEL_TYPE_VXLAN:
6565                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6566                 break;
6567
6568         case RTE_TUNNEL_TYPE_GENEVE:
6569         case RTE_TUNNEL_TYPE_TEREDO:
6570                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6571                 ret = -1;
6572                 break;
6573
6574         default:
6575                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6576                 ret = -1;
6577                 break;
6578         }
6579
6580         return ret;
6581 }
6582
6583 /* Remove UDP tunneling port */
6584 static int
6585 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6586                              struct rte_eth_udp_tunnel *udp_tunnel)
6587 {
6588         int ret = 0;
6589         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6590
6591         if (udp_tunnel == NULL)
6592                 return -EINVAL;
6593
6594         switch (udp_tunnel->prot_type) {
6595         case RTE_TUNNEL_TYPE_VXLAN:
6596                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6597                 break;
6598         case RTE_TUNNEL_TYPE_GENEVE:
6599         case RTE_TUNNEL_TYPE_TEREDO:
6600                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6601                 ret = -1;
6602                 break;
6603         default:
6604                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6605                 ret = -1;
6606                 break;
6607         }
6608
6609         return ret;
6610 }
6611
6612 /* Calculate the maximum number of contiguous PF queues that are configured */
6613 static int
6614 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6615 {
6616         struct rte_eth_dev_data *data = pf->dev_data;
6617         int i, num;
6618         struct i40e_rx_queue *rxq;
6619
6620         num = 0;
6621         for (i = 0; i < pf->lan_nb_qps; i++) {
6622                 rxq = data->rx_queues[i];
6623                 if (rxq && rxq->q_set)
6624                         num++;
6625                 else
6626                         break;
6627         }
6628
6629         return num;
6630 }
6631
6632 /* Configure RSS */
6633 static int
6634 i40e_pf_config_rss(struct i40e_pf *pf)
6635 {
6636         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6637         struct rte_eth_rss_conf rss_conf;
6638         uint32_t i, lut = 0;
6639         uint16_t j, num;
6640
6641         /*
6642          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6643          * It's necessary to calulate the actual PF queues that are configured.
6644          */
6645         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6646                 num = i40e_pf_calc_configured_queues_num(pf);
6647         else
6648                 num = pf->dev_data->nb_rx_queues;
6649
6650         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6651         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6652                         num);
6653
6654         if (num == 0) {
6655                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6656                 return -ENOTSUP;
6657         }
6658
6659         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6660                 if (j == num)
6661                         j = 0;
6662                 lut = (lut << 8) | (j & ((0x1 <<
6663                         hw->func_caps.rss_table_entry_width) - 1));
6664                 if ((i & 3) == 3)
6665                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6666         }
6667
6668         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6669         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6670                 i40e_pf_disable_rss(pf);
6671                 return 0;
6672         }
6673         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6674                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6675                 /* Random default keys */
6676                 static uint32_t rss_key_default[] = {0x6b793944,
6677                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6678                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6679                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6680
6681                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6682                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6683                                                         sizeof(uint32_t);
6684         }
6685
6686         return i40e_hw_rss_hash_set(pf, &rss_conf);
6687 }
6688
6689 static int
6690 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6691                                struct rte_eth_tunnel_filter_conf *filter)
6692 {
6693         if (pf == NULL || filter == NULL) {
6694                 PMD_DRV_LOG(ERR, "Invalid parameter");
6695                 return -EINVAL;
6696         }
6697
6698         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6699                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6700                 return -EINVAL;
6701         }
6702
6703         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6704                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6705                 return -EINVAL;
6706         }
6707
6708         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6709                 (is_zero_ether_addr(&filter->outer_mac))) {
6710                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6711                 return -EINVAL;
6712         }
6713
6714         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6715                 (is_zero_ether_addr(&filter->inner_mac))) {
6716                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6717                 return -EINVAL;
6718         }
6719
6720         return 0;
6721 }
6722
6723 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6724 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6725 static int
6726 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6727 {
6728         uint32_t val, reg;
6729         int ret = -EINVAL;
6730
6731         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6732         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6733
6734         if (len == 3) {
6735                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6736         } else if (len == 4) {
6737                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6738         } else {
6739                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6740                 return ret;
6741         }
6742
6743         if (reg != val) {
6744                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6745                                                    reg, NULL);
6746                 if (ret != 0)
6747                         return ret;
6748         } else {
6749                 ret = 0;
6750         }
6751         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6752                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6753
6754         return ret;
6755 }
6756
6757 static int
6758 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6759 {
6760         int ret = -EINVAL;
6761
6762         if (!hw || !cfg)
6763                 return -EINVAL;
6764
6765         switch (cfg->cfg_type) {
6766         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6767                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6768                 break;
6769         default:
6770                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6771                 break;
6772         }
6773
6774         return ret;
6775 }
6776
6777 static int
6778 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6779                                enum rte_filter_op filter_op,
6780                                void *arg)
6781 {
6782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         int ret = I40E_ERR_PARAM;
6784
6785         switch (filter_op) {
6786         case RTE_ETH_FILTER_SET:
6787                 ret = i40e_dev_global_config_set(hw,
6788                         (struct rte_eth_global_cfg *)arg);
6789                 break;
6790         default:
6791                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6792                 break;
6793         }
6794
6795         return ret;
6796 }
6797
6798 static int
6799 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6800                           enum rte_filter_op filter_op,
6801                           void *arg)
6802 {
6803         struct rte_eth_tunnel_filter_conf *filter;
6804         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6805         int ret = I40E_SUCCESS;
6806
6807         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6808
6809         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6810                 return I40E_ERR_PARAM;
6811
6812         switch (filter_op) {
6813         case RTE_ETH_FILTER_NOP:
6814                 if (!(pf->flags & I40E_FLAG_VXLAN))
6815                         ret = I40E_NOT_SUPPORTED;
6816                 break;
6817         case RTE_ETH_FILTER_ADD:
6818                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6819                 break;
6820         case RTE_ETH_FILTER_DELETE:
6821                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6822                 break;
6823         default:
6824                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6825                 ret = I40E_ERR_PARAM;
6826                 break;
6827         }
6828
6829         return ret;
6830 }
6831
6832 static int
6833 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6834 {
6835         int ret = 0;
6836         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6837
6838         /* RSS setup */
6839         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6840                 ret = i40e_pf_config_rss(pf);
6841         else
6842                 i40e_pf_disable_rss(pf);
6843
6844         return ret;
6845 }
6846
6847 /* Get the symmetric hash enable configurations per port */
6848 static void
6849 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6850 {
6851         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6852
6853         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6854 }
6855
6856 /* Set the symmetric hash enable configurations per port */
6857 static void
6858 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6859 {
6860         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6861
6862         if (enable > 0) {
6863                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6864                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6865                                                         "been enabled");
6866                         return;
6867                 }
6868                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6869         } else {
6870                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6871                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6872                                                         "been disabled");
6873                         return;
6874                 }
6875                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6876         }
6877         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6878         I40E_WRITE_FLUSH(hw);
6879 }
6880
6881 /*
6882  * Get global configurations of hash function type and symmetric hash enable
6883  * per flow type (pctype). Note that global configuration means it affects all
6884  * the ports on the same NIC.
6885  */
6886 static int
6887 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6888                                    struct rte_eth_hash_global_conf *g_cfg)
6889 {
6890         uint32_t reg, mask = I40E_FLOW_TYPES;
6891         uint16_t i;
6892         enum i40e_filter_pctype pctype;
6893
6894         memset(g_cfg, 0, sizeof(*g_cfg));
6895         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6896         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6897                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6898         else
6899                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6900         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6901                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6902
6903         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6904                 if (!(mask & (1UL << i)))
6905                         continue;
6906                 mask &= ~(1UL << i);
6907                 /* Bit set indicats the coresponding flow type is supported */
6908                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6909                 /* if flowtype is invalid, continue */
6910                 if (!I40E_VALID_FLOW(i))
6911                         continue;
6912                 pctype = i40e_flowtype_to_pctype(i);
6913                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6914                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6915                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6916         }
6917
6918         return 0;
6919 }
6920
6921 static int
6922 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6923 {
6924         uint32_t i;
6925         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6926
6927         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6928                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6929                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6930                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6931                                                 g_cfg->hash_func);
6932                 return -EINVAL;
6933         }
6934
6935         /*
6936          * As i40e supports less than 32 flow types, only first 32 bits need to
6937          * be checked.
6938          */
6939         mask0 = g_cfg->valid_bit_mask[0];
6940         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6941                 if (i == 0) {
6942                         /* Check if any unsupported flow type configured */
6943                         if ((mask0 | i40e_mask) ^ i40e_mask)
6944                                 goto mask_err;
6945                 } else {
6946                         if (g_cfg->valid_bit_mask[i])
6947                                 goto mask_err;
6948                 }
6949         }
6950
6951         return 0;
6952
6953 mask_err:
6954         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6955
6956         return -EINVAL;
6957 }
6958
6959 /*
6960  * Set global configurations of hash function type and symmetric hash enable
6961  * per flow type (pctype). Note any modifying global configuration will affect
6962  * all the ports on the same NIC.
6963  */
6964 static int
6965 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6966                                    struct rte_eth_hash_global_conf *g_cfg)
6967 {
6968         int ret;
6969         uint16_t i;
6970         uint32_t reg;
6971         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6972         enum i40e_filter_pctype pctype;
6973
6974         /* Check the input parameters */
6975         ret = i40e_hash_global_config_check(g_cfg);
6976         if (ret < 0)
6977                 return ret;
6978
6979         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6980                 if (!(mask0 & (1UL << i)))
6981                         continue;
6982                 mask0 &= ~(1UL << i);
6983                 /* if flowtype is invalid, continue */
6984                 if (!I40E_VALID_FLOW(i))
6985                         continue;
6986                 pctype = i40e_flowtype_to_pctype(i);
6987                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6988                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6989                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6990         }
6991
6992         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6993         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6994                 /* Toeplitz */
6995                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6996                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6997                                                                 "Toeplitz");
6998                         goto out;
6999                 }
7000                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7001         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7002                 /* Simple XOR */
7003                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7004                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7005                                                         "Simple XOR");
7006                         goto out;
7007                 }
7008                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7009         } else
7010                 /* Use the default, and keep it as it is */
7011                 goto out;
7012
7013         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7014
7015 out:
7016         I40E_WRITE_FLUSH(hw);
7017
7018         return 0;
7019 }
7020
7021 /**
7022  * Valid input sets for hash and flow director filters per PCTYPE
7023  */
7024 static uint64_t
7025 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7026                 enum rte_filter_type filter)
7027 {
7028         uint64_t valid;
7029
7030         static const uint64_t valid_hash_inset_table[] = {
7031                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7032                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7033                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7034                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7035                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7036                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7037                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7038                         I40E_INSET_FLEX_PAYLOAD,
7039                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7040                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7041                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7042                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7043                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7044                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7045                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7046                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7047                         I40E_INSET_FLEX_PAYLOAD,
7048                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7049                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7050                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7051                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7052                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7053                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7054                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7055                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7056                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7057                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7058                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7059                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7060                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7061                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7062                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7063                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7064                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7065                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7066                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7067                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7068                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7069                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7070                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7071                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7072                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7073                         I40E_INSET_FLEX_PAYLOAD,
7074                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7075                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7076                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7077                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7078                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7079                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7080                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7081                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7082                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7083                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7084                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7085                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7086                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7087                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7088                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7089                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7090                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7091                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7092                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7093                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7094                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7095                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7096                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7097                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7098                         I40E_INSET_FLEX_PAYLOAD,
7099                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7100                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7101                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7102                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7103                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7104                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7105                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7106                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7107                         I40E_INSET_FLEX_PAYLOAD,
7108                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7109                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7110                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7111                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7112                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7113                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7114                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7115                         I40E_INSET_FLEX_PAYLOAD,
7116                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7117                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7118                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7119                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7120                         I40E_INSET_FLEX_PAYLOAD,
7121         };
7122
7123         /**
7124          * Flow director supports only fields defined in
7125          * union rte_eth_fdir_flow.
7126          */
7127         static const uint64_t valid_fdir_inset_table[] = {
7128                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7129                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7130                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7131                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7132                 I40E_INSET_IPV4_TTL,
7133                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7134                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7135                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7136                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7137                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7138                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7139                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7140                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7141                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7142                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7143                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7144                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7145                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7146                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7147                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7148                 I40E_INSET_SCTP_VT,
7149                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7150                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7151                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7152                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7153                 I40E_INSET_IPV4_TTL,
7154                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7155                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7156                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7157                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7158                 I40E_INSET_IPV6_HOP_LIMIT,
7159                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7160                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7161                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7162                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7163                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7164                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7165                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7166                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7167                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7168                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7169                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7170                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7171                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7172                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7173                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7174                 I40E_INSET_SCTP_VT,
7175                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7176                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7177                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7178                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7179                 I40E_INSET_IPV6_HOP_LIMIT,
7180                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7181                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7182                 I40E_INSET_LAST_ETHER_TYPE,
7183         };
7184
7185         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7186                 return 0;
7187         if (filter == RTE_ETH_FILTER_HASH)
7188                 valid = valid_hash_inset_table[pctype];
7189         else
7190                 valid = valid_fdir_inset_table[pctype];
7191
7192         return valid;
7193 }
7194
7195 /**
7196  * Validate if the input set is allowed for a specific PCTYPE
7197  */
7198 static int
7199 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7200                 enum rte_filter_type filter, uint64_t inset)
7201 {
7202         uint64_t valid;
7203
7204         valid = i40e_get_valid_input_set(pctype, filter);
7205         if (inset & (~valid))
7206                 return -EINVAL;
7207
7208         return 0;
7209 }
7210
7211 /* default input set fields combination per pctype */
7212 static uint64_t
7213 i40e_get_default_input_set(uint16_t pctype)
7214 {
7215         static const uint64_t default_inset_table[] = {
7216                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7217                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7218                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7219                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7220                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7221                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7222                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7223                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7224                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7225                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7226                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7227                         I40E_INSET_SCTP_VT,
7228                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7229                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7230                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7231                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7232                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7233                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7234                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7235                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7236                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7237                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7238                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7239                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7240                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7241                         I40E_INSET_SCTP_VT,
7242                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7243                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7244                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7245                         I40E_INSET_LAST_ETHER_TYPE,
7246         };
7247
7248         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7249                 return 0;
7250
7251         return default_inset_table[pctype];
7252 }
7253
7254 /**
7255  * Parse the input set from index to logical bit masks
7256  */
7257 static int
7258 i40e_parse_input_set(uint64_t *inset,
7259                      enum i40e_filter_pctype pctype,
7260                      enum rte_eth_input_set_field *field,
7261                      uint16_t size)
7262 {
7263         uint16_t i, j;
7264         int ret = -EINVAL;
7265
7266         static const struct {
7267                 enum rte_eth_input_set_field field;
7268                 uint64_t inset;
7269         } inset_convert_table[] = {
7270                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7271                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7272                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7273                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7274                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7275                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7276                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7277                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7278                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7279                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7280                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7281                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7282                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7283                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7284                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7285                         I40E_INSET_IPV6_NEXT_HDR},
7286                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7287                         I40E_INSET_IPV6_HOP_LIMIT},
7288                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7289                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7290                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7291                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7292                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7293                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7294                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7295                         I40E_INSET_SCTP_VT},
7296                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7297                         I40E_INSET_TUNNEL_DMAC},
7298                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7299                         I40E_INSET_VLAN_TUNNEL},
7300                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7301                         I40E_INSET_TUNNEL_ID},
7302                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7303                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7304                         I40E_INSET_FLEX_PAYLOAD_W1},
7305                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7306                         I40E_INSET_FLEX_PAYLOAD_W2},
7307                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7308                         I40E_INSET_FLEX_PAYLOAD_W3},
7309                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7310                         I40E_INSET_FLEX_PAYLOAD_W4},
7311                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7312                         I40E_INSET_FLEX_PAYLOAD_W5},
7313                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7314                         I40E_INSET_FLEX_PAYLOAD_W6},
7315                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7316                         I40E_INSET_FLEX_PAYLOAD_W7},
7317                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7318                         I40E_INSET_FLEX_PAYLOAD_W8},
7319         };
7320
7321         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7322                 return ret;
7323
7324         /* Only one item allowed for default or all */
7325         if (size == 1) {
7326                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7327                         *inset = i40e_get_default_input_set(pctype);
7328                         return 0;
7329                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7330                         *inset = I40E_INSET_NONE;
7331                         return 0;
7332                 }
7333         }
7334
7335         for (i = 0, *inset = 0; i < size; i++) {
7336                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7337                         if (field[i] == inset_convert_table[j].field) {
7338                                 *inset |= inset_convert_table[j].inset;
7339                                 break;
7340                         }
7341                 }
7342
7343                 /* It contains unsupported input set, return immediately */
7344                 if (j == RTE_DIM(inset_convert_table))
7345                         return ret;
7346         }
7347
7348         return 0;
7349 }
7350
7351 /**
7352  * Translate the input set from bit masks to register aware bit masks
7353  * and vice versa
7354  */
7355 static uint64_t
7356 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7357 {
7358         uint64_t val = 0;
7359         uint16_t i;
7360
7361         struct inset_map {
7362                 uint64_t inset;
7363                 uint64_t inset_reg;
7364         };
7365
7366         static const struct inset_map inset_map_common[] = {
7367                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7368                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7369                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7370                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7371                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7372                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7373                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7374                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7375                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7376                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7377                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7378                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7379                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7380                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7381                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7382                 {I40E_INSET_TUNNEL_DMAC,
7383                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7384                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7385                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7386                 {I40E_INSET_TUNNEL_SRC_PORT,
7387                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7388                 {I40E_INSET_TUNNEL_DST_PORT,
7389                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7390                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7391                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7392                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7393                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7394                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7395                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7396                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7397                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7398                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7399         };
7400
7401     /* some different registers map in x722*/
7402         static const struct inset_map inset_map_diff_x722[] = {
7403                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7404                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7405                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7406                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7407         };
7408
7409         static const struct inset_map inset_map_diff_not_x722[] = {
7410                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7411                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7412                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7413                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7414         };
7415
7416         if (input == 0)
7417                 return val;
7418
7419         /* Translate input set to register aware inset */
7420         if (type == I40E_MAC_X722) {
7421                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7422                         if (input & inset_map_diff_x722[i].inset)
7423                                 val |= inset_map_diff_x722[i].inset_reg;
7424                 }
7425         } else {
7426                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7427                         if (input & inset_map_diff_not_x722[i].inset)
7428                                 val |= inset_map_diff_not_x722[i].inset_reg;
7429                 }
7430         }
7431
7432         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7433                 if (input & inset_map_common[i].inset)
7434                         val |= inset_map_common[i].inset_reg;
7435         }
7436
7437         return val;
7438 }
7439
7440 static int
7441 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7442 {
7443         uint8_t i, idx = 0;
7444         uint64_t inset_need_mask = inset;
7445
7446         static const struct {
7447                 uint64_t inset;
7448                 uint32_t mask;
7449         } inset_mask_map[] = {
7450                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7451                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7452                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7453                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7454                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7455                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7456                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7457                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7458         };
7459
7460         if (!inset || !mask || !nb_elem)
7461                 return 0;
7462
7463         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7464                 /* Clear the inset bit, if no MASK is required,
7465                  * for example proto + ttl
7466                  */
7467                 if ((inset & inset_mask_map[i].inset) ==
7468                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7469                         inset_need_mask &= ~inset_mask_map[i].inset;
7470                 if (!inset_need_mask)
7471                         return 0;
7472         }
7473         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7474                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7475                     inset_mask_map[i].inset) {
7476                         if (idx >= nb_elem) {
7477                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7478                                 return -EINVAL;
7479                         }
7480                         mask[idx] = inset_mask_map[i].mask;
7481                         idx++;
7482                 }
7483         }
7484
7485         return idx;
7486 }
7487
7488 static void
7489 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7490 {
7491         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7492
7493         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7494         if (reg != val)
7495                 i40e_write_rx_ctl(hw, addr, val);
7496         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7497                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7498 }
7499
7500 static void
7501 i40e_filter_input_set_init(struct i40e_pf *pf)
7502 {
7503         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7504         enum i40e_filter_pctype pctype;
7505         uint64_t input_set, inset_reg;
7506         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7507         int num, i;
7508
7509         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7510              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7511                 if (!I40E_VALID_PCTYPE(pctype))
7512                         continue;
7513                 input_set = i40e_get_default_input_set(pctype);
7514
7515                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7516                                                    I40E_INSET_MASK_NUM_REG);
7517                 if (num < 0)
7518                         return;
7519                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7520                                         input_set);
7521
7522                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7523                                       (uint32_t)(inset_reg & UINT32_MAX));
7524                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7525                                      (uint32_t)((inset_reg >>
7526                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7527                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7528                                       (uint32_t)(inset_reg & UINT32_MAX));
7529                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7530                                      (uint32_t)((inset_reg >>
7531                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7532
7533                 for (i = 0; i < num; i++) {
7534                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7535                                              mask_reg[i]);
7536                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7537                                              mask_reg[i]);
7538                 }
7539                 /*clear unused mask registers of the pctype */
7540                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7541                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7542                                              0);
7543                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7544                                              0);
7545                 }
7546                 I40E_WRITE_FLUSH(hw);
7547
7548                 /* store the default input set */
7549                 pf->hash_input_set[pctype] = input_set;
7550                 pf->fdir.input_set[pctype] = input_set;
7551         }
7552 }
7553
7554 int
7555 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7556                          struct rte_eth_input_set_conf *conf)
7557 {
7558         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7559         enum i40e_filter_pctype pctype;
7560         uint64_t input_set, inset_reg = 0;
7561         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7562         int ret, i, num;
7563
7564         if (!conf) {
7565                 PMD_DRV_LOG(ERR, "Invalid pointer");
7566                 return -EFAULT;
7567         }
7568         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7569             conf->op != RTE_ETH_INPUT_SET_ADD) {
7570                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7571                 return -EINVAL;
7572         }
7573
7574         if (!I40E_VALID_FLOW(conf->flow_type)) {
7575                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7576                 return -EINVAL;
7577         }
7578         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7579         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7580                                    conf->inset_size);
7581         if (ret) {
7582                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7583                 return -EINVAL;
7584         }
7585         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7586                                     input_set) != 0) {
7587                 PMD_DRV_LOG(ERR, "Invalid input set");
7588                 return -EINVAL;
7589         }
7590         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7591                 /* get inset value in register */
7592                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7593                 inset_reg <<= I40E_32_BIT_WIDTH;
7594                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7595                 input_set |= pf->hash_input_set[pctype];
7596         }
7597         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7598                                            I40E_INSET_MASK_NUM_REG);
7599         if (num < 0)
7600                 return -EINVAL;
7601
7602         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7603
7604         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7605                               (uint32_t)(inset_reg & UINT32_MAX));
7606         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7607                              (uint32_t)((inset_reg >>
7608                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7609
7610         for (i = 0; i < num; i++)
7611                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7612                                      mask_reg[i]);
7613         /*clear unused mask registers of the pctype */
7614         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7615                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7616                                      0);
7617         I40E_WRITE_FLUSH(hw);
7618
7619         pf->hash_input_set[pctype] = input_set;
7620         return 0;
7621 }
7622
7623 int
7624 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7625                          struct rte_eth_input_set_conf *conf)
7626 {
7627         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7628         enum i40e_filter_pctype pctype;
7629         uint64_t input_set, inset_reg = 0;
7630         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7631         int ret, i, num;
7632
7633         if (!hw || !conf) {
7634                 PMD_DRV_LOG(ERR, "Invalid pointer");
7635                 return -EFAULT;
7636         }
7637         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7638             conf->op != RTE_ETH_INPUT_SET_ADD) {
7639                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7640                 return -EINVAL;
7641         }
7642
7643         if (!I40E_VALID_FLOW(conf->flow_type)) {
7644                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7645                 return -EINVAL;
7646         }
7647         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7648         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7649                                    conf->inset_size);
7650         if (ret) {
7651                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7652                 return -EINVAL;
7653         }
7654         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7655                                     input_set) != 0) {
7656                 PMD_DRV_LOG(ERR, "Invalid input set");
7657                 return -EINVAL;
7658         }
7659
7660         /* get inset value in register */
7661         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7662         inset_reg <<= I40E_32_BIT_WIDTH;
7663         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7664
7665         /* Can not change the inset reg for flex payload for fdir,
7666          * it is done by writing I40E_PRTQF_FD_FLXINSET
7667          * in i40e_set_flex_mask_on_pctype.
7668          */
7669         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7670                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7671         else
7672                 input_set |= pf->fdir.input_set[pctype];
7673         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7674                                            I40E_INSET_MASK_NUM_REG);
7675         if (num < 0)
7676                 return -EINVAL;
7677
7678         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7679
7680         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7681                               (uint32_t)(inset_reg & UINT32_MAX));
7682         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7683                              (uint32_t)((inset_reg >>
7684                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7685
7686         for (i = 0; i < num; i++)
7687                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7688                                      mask_reg[i]);
7689         /*clear unused mask registers of the pctype */
7690         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7691                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7692                                      0);
7693         I40E_WRITE_FLUSH(hw);
7694
7695         pf->fdir.input_set[pctype] = input_set;
7696         return 0;
7697 }
7698
7699 static int
7700 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7701 {
7702         int ret = 0;
7703
7704         if (!hw || !info) {
7705                 PMD_DRV_LOG(ERR, "Invalid pointer");
7706                 return -EFAULT;
7707         }
7708
7709         switch (info->info_type) {
7710         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7711                 i40e_get_symmetric_hash_enable_per_port(hw,
7712                                         &(info->info.enable));
7713                 break;
7714         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7715                 ret = i40e_get_hash_filter_global_config(hw,
7716                                 &(info->info.global_conf));
7717                 break;
7718         default:
7719                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7720                                                         info->info_type);
7721                 ret = -EINVAL;
7722                 break;
7723         }
7724
7725         return ret;
7726 }
7727
7728 static int
7729 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7730 {
7731         int ret = 0;
7732
7733         if (!hw || !info) {
7734                 PMD_DRV_LOG(ERR, "Invalid pointer");
7735                 return -EFAULT;
7736         }
7737
7738         switch (info->info_type) {
7739         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7740                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7741                 break;
7742         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7743                 ret = i40e_set_hash_filter_global_config(hw,
7744                                 &(info->info.global_conf));
7745                 break;
7746         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7747                 ret = i40e_hash_filter_inset_select(hw,
7748                                                &(info->info.input_set_conf));
7749                 break;
7750
7751         default:
7752                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7753                                                         info->info_type);
7754                 ret = -EINVAL;
7755                 break;
7756         }
7757
7758         return ret;
7759 }
7760
7761 /* Operations for hash function */
7762 static int
7763 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7764                       enum rte_filter_op filter_op,
7765                       void *arg)
7766 {
7767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7768         int ret = 0;
7769
7770         switch (filter_op) {
7771         case RTE_ETH_FILTER_NOP:
7772                 break;
7773         case RTE_ETH_FILTER_GET:
7774                 ret = i40e_hash_filter_get(hw,
7775                         (struct rte_eth_hash_filter_info *)arg);
7776                 break;
7777         case RTE_ETH_FILTER_SET:
7778                 ret = i40e_hash_filter_set(hw,
7779                         (struct rte_eth_hash_filter_info *)arg);
7780                 break;
7781         default:
7782                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7783                                                                 filter_op);
7784                 ret = -ENOTSUP;
7785                 break;
7786         }
7787
7788         return ret;
7789 }
7790
7791 /*
7792  * Configure ethertype filter, which can director packet by filtering
7793  * with mac address and ether_type or only ether_type
7794  */
7795 static int
7796 i40e_ethertype_filter_set(struct i40e_pf *pf,
7797                         struct rte_eth_ethertype_filter *filter,
7798                         bool add)
7799 {
7800         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7801         struct i40e_control_filter_stats stats;
7802         uint16_t flags = 0;
7803         int ret;
7804
7805         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7806                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7807                 return -EINVAL;
7808         }
7809         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7810                 filter->ether_type == ETHER_TYPE_IPv6) {
7811                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7812                         " control packet filter.", filter->ether_type);
7813                 return -EINVAL;
7814         }
7815         if (filter->ether_type == ETHER_TYPE_VLAN)
7816                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7817                         " not supported.");
7818
7819         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7820                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7821         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7822                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7823         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7824
7825         memset(&stats, 0, sizeof(stats));
7826         ret = i40e_aq_add_rem_control_packet_filter(hw,
7827                         filter->mac_addr.addr_bytes,
7828                         filter->ether_type, flags,
7829                         pf->main_vsi->seid,
7830                         filter->queue, add, &stats, NULL);
7831
7832         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7833                          " mac_etype_used = %u, etype_used = %u,"
7834                          " mac_etype_free = %u, etype_free = %u\n",
7835                          ret, stats.mac_etype_used, stats.etype_used,
7836                          stats.mac_etype_free, stats.etype_free);
7837         if (ret < 0)
7838                 return -ENOSYS;
7839         return 0;
7840 }
7841
7842 /*
7843  * Handle operations for ethertype filter.
7844  */
7845 static int
7846 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7847                                 enum rte_filter_op filter_op,
7848                                 void *arg)
7849 {
7850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7851         int ret = 0;
7852
7853         if (filter_op == RTE_ETH_FILTER_NOP)
7854                 return ret;
7855
7856         if (arg == NULL) {
7857                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7858                             filter_op);
7859                 return -EINVAL;
7860         }
7861
7862         switch (filter_op) {
7863         case RTE_ETH_FILTER_ADD:
7864                 ret = i40e_ethertype_filter_set(pf,
7865                         (struct rte_eth_ethertype_filter *)arg,
7866                         TRUE);
7867                 break;
7868         case RTE_ETH_FILTER_DELETE:
7869                 ret = i40e_ethertype_filter_set(pf,
7870                         (struct rte_eth_ethertype_filter *)arg,
7871                         FALSE);
7872                 break;
7873         default:
7874                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7875                 ret = -ENOSYS;
7876                 break;
7877         }
7878         return ret;
7879 }
7880
7881 static int
7882 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7883                      enum rte_filter_type filter_type,
7884                      enum rte_filter_op filter_op,
7885                      void *arg)
7886 {
7887         int ret = 0;
7888
7889         if (dev == NULL)
7890                 return -EINVAL;
7891
7892         switch (filter_type) {
7893         case RTE_ETH_FILTER_NONE:
7894                 /* For global configuration */
7895                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7896                 break;
7897         case RTE_ETH_FILTER_HASH:
7898                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7899                 break;
7900         case RTE_ETH_FILTER_MACVLAN:
7901                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7902                 break;
7903         case RTE_ETH_FILTER_ETHERTYPE:
7904                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7905                 break;
7906         case RTE_ETH_FILTER_TUNNEL:
7907                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7908                 break;
7909         case RTE_ETH_FILTER_FDIR:
7910                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7911                 break;
7912         default:
7913                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7914                                                         filter_type);
7915                 ret = -EINVAL;
7916                 break;
7917         }
7918
7919         return ret;
7920 }
7921
7922 /*
7923  * Check and enable Extended Tag.
7924  * Enabling Extended Tag is important for 40G performance.
7925  */
7926 static void
7927 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7928 {
7929         uint32_t buf = 0;
7930         int ret;
7931
7932         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7933                                       PCI_DEV_CAP_REG);
7934         if (ret < 0) {
7935                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7936                             PCI_DEV_CAP_REG);
7937                 return;
7938         }
7939         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7940                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7941                 return;
7942         }
7943
7944         buf = 0;
7945         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7946                                       PCI_DEV_CTRL_REG);
7947         if (ret < 0) {
7948                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7949                             PCI_DEV_CTRL_REG);
7950                 return;
7951         }
7952         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7953                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7954                 return;
7955         }
7956         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7957         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7958                                        PCI_DEV_CTRL_REG);
7959         if (ret < 0) {
7960                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7961                             PCI_DEV_CTRL_REG);
7962                 return;
7963         }
7964 }
7965
7966 /*
7967  * As some registers wouldn't be reset unless a global hardware reset,
7968  * hardware initialization is needed to put those registers into an
7969  * expected initial state.
7970  */
7971 static void
7972 i40e_hw_init(struct rte_eth_dev *dev)
7973 {
7974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7975
7976         i40e_enable_extended_tag(dev);
7977
7978         /* clear the PF Queue Filter control register */
7979         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7980
7981         /* Disable symmetric hash per port */
7982         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7983 }
7984
7985 enum i40e_filter_pctype
7986 i40e_flowtype_to_pctype(uint16_t flow_type)
7987 {
7988         static const enum i40e_filter_pctype pctype_table[] = {
7989                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7990                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7991                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7992                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7993                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7994                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7995                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7996                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7997                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7998                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7999                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8000                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8001                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8002                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8003                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8004                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8005                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8006                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8007                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8008         };
8009
8010         return pctype_table[flow_type];
8011 }
8012
8013 uint16_t
8014 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8015 {
8016         static const uint16_t flowtype_table[] = {
8017                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8018                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8019                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8020                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8021                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8022                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8023                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8024                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8025                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8026                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8027                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8028                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8029                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8030                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8031                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8032                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8033                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8034                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8035                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8036         };
8037
8038         return flowtype_table[pctype];
8039 }
8040
8041 /*
8042  * On X710, performance number is far from the expectation on recent firmware
8043  * versions; on XL710, performance number is also far from the expectation on
8044  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8045  * mode is enabled and port MAC address is equal to the packet destination MAC
8046  * address. The fix for this issue may not be integrated in the following
8047  * firmware version. So the workaround in software driver is needed. It needs
8048  * to modify the initial values of 3 internal only registers for both X710 and
8049  * XL710. Note that the values for X710 or XL710 could be different, and the
8050  * workaround can be removed when it is fixed in firmware in the future.
8051  */
8052
8053 /* For both X710 and XL710 */
8054 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8055 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8056
8057 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8058 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8059
8060 /* For X710 */
8061 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8062 /* For XL710 */
8063 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8064 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8065
8066 static void
8067 i40e_configure_registers(struct i40e_hw *hw)
8068 {
8069         static struct {
8070                 uint32_t addr;
8071                 uint64_t val;
8072         } reg_table[] = {
8073                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8074                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8075                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8076         };
8077         uint64_t reg;
8078         uint32_t i;
8079         int ret;
8080
8081         for (i = 0; i < RTE_DIM(reg_table); i++) {
8082                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8083                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8084                                 reg_table[i].val =
8085                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8086                         else /* For X710 */
8087                                 reg_table[i].val =
8088                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8089                 }
8090
8091                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8092                                                         &reg, NULL);
8093                 if (ret < 0) {
8094                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8095                                                         reg_table[i].addr);
8096                         break;
8097                 }
8098                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8099                                                 reg_table[i].addr, reg);
8100                 if (reg == reg_table[i].val)
8101                         continue;
8102
8103                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8104                                                 reg_table[i].val, NULL);
8105                 if (ret < 0) {
8106                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8107                                 "address of 0x%"PRIx32, reg_table[i].val,
8108                                                         reg_table[i].addr);
8109                         break;
8110                 }
8111                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8112                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8113         }
8114 }
8115
8116 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8117 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8118 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8119 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8120 static int
8121 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8122 {
8123         uint32_t reg;
8124         int ret;
8125
8126         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8127                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8128                 return -EINVAL;
8129         }
8130
8131         /* Configure for double VLAN RX stripping */
8132         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8133         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8134                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8135                 ret = i40e_aq_debug_write_register(hw,
8136                                                    I40E_VSI_TSR(vsi->vsi_id),
8137                                                    reg, NULL);
8138                 if (ret < 0) {
8139                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8140                                     vsi->vsi_id);
8141                         return I40E_ERR_CONFIG;
8142                 }
8143         }
8144
8145         /* Configure for double VLAN TX insertion */
8146         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8147         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8148                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8149                 ret = i40e_aq_debug_write_register(hw,
8150                                                    I40E_VSI_L2TAGSTXVALID(
8151                                                    vsi->vsi_id), reg, NULL);
8152                 if (ret < 0) {
8153                         PMD_DRV_LOG(ERR, "Failed to update "
8154                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8155                         return I40E_ERR_CONFIG;
8156                 }
8157         }
8158
8159         return 0;
8160 }
8161
8162 /**
8163  * i40e_aq_add_mirror_rule
8164  * @hw: pointer to the hardware structure
8165  * @seid: VEB seid to add mirror rule to
8166  * @dst_id: destination vsi seid
8167  * @entries: Buffer which contains the entities to be mirrored
8168  * @count: number of entities contained in the buffer
8169  * @rule_id:the rule_id of the rule to be added
8170  *
8171  * Add a mirror rule for a given veb.
8172  *
8173  **/
8174 static enum i40e_status_code
8175 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8176                         uint16_t seid, uint16_t dst_id,
8177                         uint16_t rule_type, uint16_t *entries,
8178                         uint16_t count, uint16_t *rule_id)
8179 {
8180         struct i40e_aq_desc desc;
8181         struct i40e_aqc_add_delete_mirror_rule cmd;
8182         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8183                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8184                 &desc.params.raw;
8185         uint16_t buff_len;
8186         enum i40e_status_code status;
8187
8188         i40e_fill_default_direct_cmd_desc(&desc,
8189                                           i40e_aqc_opc_add_mirror_rule);
8190         memset(&cmd, 0, sizeof(cmd));
8191
8192         buff_len = sizeof(uint16_t) * count;
8193         desc.datalen = rte_cpu_to_le_16(buff_len);
8194         if (buff_len > 0)
8195                 desc.flags |= rte_cpu_to_le_16(
8196                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8197         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8198                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8199         cmd.num_entries = rte_cpu_to_le_16(count);
8200         cmd.seid = rte_cpu_to_le_16(seid);
8201         cmd.destination = rte_cpu_to_le_16(dst_id);
8202
8203         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8204         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8205         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8206                          "rule_id = %u"
8207                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8208                          hw->aq.asq_last_status, resp->rule_id,
8209                          resp->mirror_rules_used, resp->mirror_rules_free);
8210         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8211
8212         return status;
8213 }
8214
8215 /**
8216  * i40e_aq_del_mirror_rule
8217  * @hw: pointer to the hardware structure
8218  * @seid: VEB seid to add mirror rule to
8219  * @entries: Buffer which contains the entities to be mirrored
8220  * @count: number of entities contained in the buffer
8221  * @rule_id:the rule_id of the rule to be delete
8222  *
8223  * Delete a mirror rule for a given veb.
8224  *
8225  **/
8226 static enum i40e_status_code
8227 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8228                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8229                 uint16_t count, uint16_t rule_id)
8230 {
8231         struct i40e_aq_desc desc;
8232         struct i40e_aqc_add_delete_mirror_rule cmd;
8233         uint16_t buff_len = 0;
8234         enum i40e_status_code status;
8235         void *buff = NULL;
8236
8237         i40e_fill_default_direct_cmd_desc(&desc,
8238                                           i40e_aqc_opc_delete_mirror_rule);
8239         memset(&cmd, 0, sizeof(cmd));
8240         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8241                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8242                                                           I40E_AQ_FLAG_RD));
8243                 cmd.num_entries = count;
8244                 buff_len = sizeof(uint16_t) * count;
8245                 desc.datalen = rte_cpu_to_le_16(buff_len);
8246                 buff = (void *)entries;
8247         } else
8248                 /* rule id is filled in destination field for deleting mirror rule */
8249                 cmd.destination = rte_cpu_to_le_16(rule_id);
8250
8251         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8252                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8253         cmd.seid = rte_cpu_to_le_16(seid);
8254
8255         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8256         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8257
8258         return status;
8259 }
8260
8261 /**
8262  * i40e_mirror_rule_set
8263  * @dev: pointer to the hardware structure
8264  * @mirror_conf: mirror rule info
8265  * @sw_id: mirror rule's sw_id
8266  * @on: enable/disable
8267  *
8268  * set a mirror rule.
8269  *
8270  **/
8271 static int
8272 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8273                         struct rte_eth_mirror_conf *mirror_conf,
8274                         uint8_t sw_id, uint8_t on)
8275 {
8276         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8277         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8278         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8279         struct i40e_mirror_rule *parent = NULL;
8280         uint16_t seid, dst_seid, rule_id;
8281         uint16_t i, j = 0;
8282         int ret;
8283
8284         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8285
8286         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8287                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8288                         " without veb or vfs.");
8289                 return -ENOSYS;
8290         }
8291         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8292                 PMD_DRV_LOG(ERR, "mirror table is full.");
8293                 return -ENOSPC;
8294         }
8295         if (mirror_conf->dst_pool > pf->vf_num) {
8296                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8297                                  mirror_conf->dst_pool);
8298                 return -EINVAL;
8299         }
8300
8301         seid = pf->main_vsi->veb->seid;
8302
8303         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8304                 if (sw_id <= it->index) {
8305                         mirr_rule = it;
8306                         break;
8307                 }
8308                 parent = it;
8309         }
8310         if (mirr_rule && sw_id == mirr_rule->index) {
8311                 if (on) {
8312                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8313                         return -EEXIST;
8314                 } else {
8315                         ret = i40e_aq_del_mirror_rule(hw, seid,
8316                                         mirr_rule->rule_type,
8317                                         mirr_rule->entries,
8318                                         mirr_rule->num_entries, mirr_rule->id);
8319                         if (ret < 0) {
8320                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8321                                                    " ret = %d, aq_err = %d.",
8322                                                    ret, hw->aq.asq_last_status);
8323                                 return -ENOSYS;
8324                         }
8325                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8326                         rte_free(mirr_rule);
8327                         pf->nb_mirror_rule--;
8328                         return 0;
8329                 }
8330         } else if (!on) {
8331                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8332                 return -ENOENT;
8333         }
8334
8335         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8336                                 sizeof(struct i40e_mirror_rule) , 0);
8337         if (!mirr_rule) {
8338                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8339                 return I40E_ERR_NO_MEMORY;
8340         }
8341         switch (mirror_conf->rule_type) {
8342         case ETH_MIRROR_VLAN:
8343                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8344                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8345                                 mirr_rule->entries[j] =
8346                                         mirror_conf->vlan.vlan_id[i];
8347                                 j++;
8348                         }
8349                 }
8350                 if (j == 0) {
8351                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8352                         rte_free(mirr_rule);
8353                         return -EINVAL;
8354                 }
8355                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8356                 break;
8357         case ETH_MIRROR_VIRTUAL_POOL_UP:
8358         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8359                 /* check if the specified pool bit is out of range */
8360                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8361                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8362                         rte_free(mirr_rule);
8363                         return -EINVAL;
8364                 }
8365                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8366                         if (mirror_conf->pool_mask & (1ULL << i)) {
8367                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8368                                 j++;
8369                         }
8370                 }
8371                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8372                         /* add pf vsi to entries */
8373                         mirr_rule->entries[j] = pf->main_vsi_seid;
8374                         j++;
8375                 }
8376                 if (j == 0) {
8377                         PMD_DRV_LOG(ERR, "pool is not specified.");
8378                         rte_free(mirr_rule);
8379                         return -EINVAL;
8380                 }
8381                 /* egress and ingress in aq commands means from switch but not port */
8382                 mirr_rule->rule_type =
8383                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8384                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8385                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8386                 break;
8387         case ETH_MIRROR_UPLINK_PORT:
8388                 /* egress and ingress in aq commands means from switch but not port*/
8389                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8390                 break;
8391         case ETH_MIRROR_DOWNLINK_PORT:
8392                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8393                 break;
8394         default:
8395                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8396                         mirror_conf->rule_type);
8397                 rte_free(mirr_rule);
8398                 return -EINVAL;
8399         }
8400
8401         /* If the dst_pool is equal to vf_num, consider it as PF */
8402         if (mirror_conf->dst_pool == pf->vf_num)
8403                 dst_seid = pf->main_vsi_seid;
8404         else
8405                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8406
8407         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8408                                       mirr_rule->rule_type, mirr_rule->entries,
8409                                       j, &rule_id);
8410         if (ret < 0) {
8411                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8412                                    " ret = %d, aq_err = %d.",
8413                                    ret, hw->aq.asq_last_status);
8414                 rte_free(mirr_rule);
8415                 return -ENOSYS;
8416         }
8417
8418         mirr_rule->index = sw_id;
8419         mirr_rule->num_entries = j;
8420         mirr_rule->id = rule_id;
8421         mirr_rule->dst_vsi_seid = dst_seid;
8422
8423         if (parent)
8424                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8425         else
8426                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8427
8428         pf->nb_mirror_rule++;
8429         return 0;
8430 }
8431
8432 /**
8433  * i40e_mirror_rule_reset
8434  * @dev: pointer to the device
8435  * @sw_id: mirror rule's sw_id
8436  *
8437  * reset a mirror rule.
8438  *
8439  **/
8440 static int
8441 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8442 {
8443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8444         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8445         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8446         uint16_t seid;
8447         int ret;
8448
8449         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8450
8451         seid = pf->main_vsi->veb->seid;
8452
8453         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8454                 if (sw_id == it->index) {
8455                         mirr_rule = it;
8456                         break;
8457                 }
8458         }
8459         if (mirr_rule) {
8460                 ret = i40e_aq_del_mirror_rule(hw, seid,
8461                                 mirr_rule->rule_type,
8462                                 mirr_rule->entries,
8463                                 mirr_rule->num_entries, mirr_rule->id);
8464                 if (ret < 0) {
8465                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8466                                            " status = %d, aq_err = %d.",
8467                                            ret, hw->aq.asq_last_status);
8468                         return -ENOSYS;
8469                 }
8470                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8471                 rte_free(mirr_rule);
8472                 pf->nb_mirror_rule--;
8473         } else {
8474                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8475                 return -ENOENT;
8476         }
8477         return 0;
8478 }
8479
8480 static uint64_t
8481 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8482 {
8483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8484         uint64_t systim_cycles;
8485
8486         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8487         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8488                         << 32;
8489
8490         return systim_cycles;
8491 }
8492
8493 static uint64_t
8494 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8495 {
8496         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8497         uint64_t rx_tstamp;
8498
8499         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8500         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8501                         << 32;
8502
8503         return rx_tstamp;
8504 }
8505
8506 static uint64_t
8507 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8508 {
8509         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8510         uint64_t tx_tstamp;
8511
8512         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8513         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8514                         << 32;
8515
8516         return tx_tstamp;
8517 }
8518
8519 static void
8520 i40e_start_timecounters(struct rte_eth_dev *dev)
8521 {
8522         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8523         struct i40e_adapter *adapter =
8524                         (struct i40e_adapter *)dev->data->dev_private;
8525         struct rte_eth_link link;
8526         uint32_t tsync_inc_l;
8527         uint32_t tsync_inc_h;
8528
8529         /* Get current link speed. */
8530         memset(&link, 0, sizeof(link));
8531         i40e_dev_link_update(dev, 1);
8532         rte_i40e_dev_atomic_read_link_status(dev, &link);
8533
8534         switch (link.link_speed) {
8535         case ETH_SPEED_NUM_40G:
8536                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8537                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8538                 break;
8539         case ETH_SPEED_NUM_10G:
8540                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8541                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8542                 break;
8543         case ETH_SPEED_NUM_1G:
8544                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8545                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8546                 break;
8547         default:
8548                 tsync_inc_l = 0x0;
8549                 tsync_inc_h = 0x0;
8550         }
8551
8552         /* Set the timesync increment value. */
8553         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8554         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8555
8556         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8557         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8558         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8559
8560         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8561         adapter->systime_tc.cc_shift = 0;
8562         adapter->systime_tc.nsec_mask = 0;
8563
8564         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8565         adapter->rx_tstamp_tc.cc_shift = 0;
8566         adapter->rx_tstamp_tc.nsec_mask = 0;
8567
8568         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8569         adapter->tx_tstamp_tc.cc_shift = 0;
8570         adapter->tx_tstamp_tc.nsec_mask = 0;
8571 }
8572
8573 static int
8574 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8575 {
8576         struct i40e_adapter *adapter =
8577                         (struct i40e_adapter *)dev->data->dev_private;
8578
8579         adapter->systime_tc.nsec += delta;
8580         adapter->rx_tstamp_tc.nsec += delta;
8581         adapter->tx_tstamp_tc.nsec += delta;
8582
8583         return 0;
8584 }
8585
8586 static int
8587 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8588 {
8589         uint64_t ns;
8590         struct i40e_adapter *adapter =
8591                         (struct i40e_adapter *)dev->data->dev_private;
8592
8593         ns = rte_timespec_to_ns(ts);
8594
8595         /* Set the timecounters to a new value. */
8596         adapter->systime_tc.nsec = ns;
8597         adapter->rx_tstamp_tc.nsec = ns;
8598         adapter->tx_tstamp_tc.nsec = ns;
8599
8600         return 0;
8601 }
8602
8603 static int
8604 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8605 {
8606         uint64_t ns, systime_cycles;
8607         struct i40e_adapter *adapter =
8608                         (struct i40e_adapter *)dev->data->dev_private;
8609
8610         systime_cycles = i40e_read_systime_cyclecounter(dev);
8611         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8612         *ts = rte_ns_to_timespec(ns);
8613
8614         return 0;
8615 }
8616
8617 static int
8618 i40e_timesync_enable(struct rte_eth_dev *dev)
8619 {
8620         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8621         uint32_t tsync_ctl_l;
8622         uint32_t tsync_ctl_h;
8623
8624         /* Stop the timesync system time. */
8625         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8626         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8627         /* Reset the timesync system time value. */
8628         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8629         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8630
8631         i40e_start_timecounters(dev);
8632
8633         /* Clear timesync registers. */
8634         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8635         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8636         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8637         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8638         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8639         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8640
8641         /* Enable timestamping of PTP packets. */
8642         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8643         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8644
8645         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8646         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8647         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8648
8649         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8650         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8651
8652         return 0;
8653 }
8654
8655 static int
8656 i40e_timesync_disable(struct rte_eth_dev *dev)
8657 {
8658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8659         uint32_t tsync_ctl_l;
8660         uint32_t tsync_ctl_h;
8661
8662         /* Disable timestamping of transmitted PTP packets. */
8663         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8664         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8665
8666         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8667         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8668
8669         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8670         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8671
8672         /* Reset the timesync increment value. */
8673         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8674         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8675
8676         return 0;
8677 }
8678
8679 static int
8680 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8681                                 struct timespec *timestamp, uint32_t flags)
8682 {
8683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8684         struct i40e_adapter *adapter =
8685                 (struct i40e_adapter *)dev->data->dev_private;
8686
8687         uint32_t sync_status;
8688         uint32_t index = flags & 0x03;
8689         uint64_t rx_tstamp_cycles;
8690         uint64_t ns;
8691
8692         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8693         if ((sync_status & (1 << index)) == 0)
8694                 return -EINVAL;
8695
8696         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8697         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8698         *timestamp = rte_ns_to_timespec(ns);
8699
8700         return 0;
8701 }
8702
8703 static int
8704 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8705                                 struct timespec *timestamp)
8706 {
8707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8708         struct i40e_adapter *adapter =
8709                 (struct i40e_adapter *)dev->data->dev_private;
8710
8711         uint32_t sync_status;
8712         uint64_t tx_tstamp_cycles;
8713         uint64_t ns;
8714
8715         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8716         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8717                 return -EINVAL;
8718
8719         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8720         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8721         *timestamp = rte_ns_to_timespec(ns);
8722
8723         return 0;
8724 }
8725
8726 /*
8727  * i40e_parse_dcb_configure - parse dcb configure from user
8728  * @dev: the device being configured
8729  * @dcb_cfg: pointer of the result of parse
8730  * @*tc_map: bit map of enabled traffic classes
8731  *
8732  * Returns 0 on success, negative value on failure
8733  */
8734 static int
8735 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8736                          struct i40e_dcbx_config *dcb_cfg,
8737                          uint8_t *tc_map)
8738 {
8739         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8740         uint8_t i, tc_bw, bw_lf;
8741
8742         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8743
8744         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8745         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8746                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8747                 return -EINVAL;
8748         }
8749
8750         /* assume each tc has the same bw */
8751         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8752         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8753                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8754         /* to ensure the sum of tcbw is equal to 100 */
8755         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8756         for (i = 0; i < bw_lf; i++)
8757                 dcb_cfg->etscfg.tcbwtable[i]++;
8758
8759         /* assume each tc has the same Transmission Selection Algorithm */
8760         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8761                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8762
8763         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8764                 dcb_cfg->etscfg.prioritytable[i] =
8765                                 dcb_rx_conf->dcb_tc[i];
8766
8767         /* FW needs one App to configure HW */
8768         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8769         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8770         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8771         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8772
8773         if (dcb_rx_conf->nb_tcs == 0)
8774                 *tc_map = 1; /* tc0 only */
8775         else
8776                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8777
8778         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8779                 dcb_cfg->pfc.willing = 0;
8780                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8781                 dcb_cfg->pfc.pfcenable = *tc_map;
8782         }
8783         return 0;
8784 }
8785
8786
8787 static enum i40e_status_code
8788 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8789                               struct i40e_aqc_vsi_properties_data *info,
8790                               uint8_t enabled_tcmap)
8791 {
8792         enum i40e_status_code ret;
8793         int i, total_tc = 0;
8794         uint16_t qpnum_per_tc, bsf, qp_idx;
8795         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8796         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8797         uint16_t used_queues;
8798
8799         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8800         if (ret != I40E_SUCCESS)
8801                 return ret;
8802
8803         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8804                 if (enabled_tcmap & (1 << i))
8805                         total_tc++;
8806         }
8807         if (total_tc == 0)
8808                 total_tc = 1;
8809         vsi->enabled_tc = enabled_tcmap;
8810
8811         /* different VSI has different queues assigned */
8812         if (vsi->type == I40E_VSI_MAIN)
8813                 used_queues = dev_data->nb_rx_queues -
8814                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8815         else if (vsi->type == I40E_VSI_VMDQ2)
8816                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8817         else {
8818                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8819                 return I40E_ERR_NO_AVAILABLE_VSI;
8820         }
8821
8822         qpnum_per_tc = used_queues / total_tc;
8823         /* Number of queues per enabled TC */
8824         if (qpnum_per_tc == 0) {
8825                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8826                 return I40E_ERR_INVALID_QP_ID;
8827         }
8828         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8829                                 I40E_MAX_Q_PER_TC);
8830         bsf = rte_bsf32(qpnum_per_tc);
8831
8832         /**
8833          * Configure TC and queue mapping parameters, for enabled TC,
8834          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8835          * default queue will serve it.
8836          */
8837         qp_idx = 0;
8838         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8839                 if (vsi->enabled_tc & (1 << i)) {
8840                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8841                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8842                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8843                         qp_idx += qpnum_per_tc;
8844                 } else
8845                         info->tc_mapping[i] = 0;
8846         }
8847
8848         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8849         if (vsi->type == I40E_VSI_SRIOV) {
8850                 info->mapping_flags |=
8851                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8852                 for (i = 0; i < vsi->nb_qps; i++)
8853                         info->queue_mapping[i] =
8854                                 rte_cpu_to_le_16(vsi->base_queue + i);
8855         } else {
8856                 info->mapping_flags |=
8857                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8858                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8859         }
8860         info->valid_sections |=
8861                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8862
8863         return I40E_SUCCESS;
8864 }
8865
8866 /*
8867  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8868  * @veb: VEB to be configured
8869  * @tc_map: enabled TC bitmap
8870  *
8871  * Returns 0 on success, negative value on failure
8872  */
8873 static enum i40e_status_code
8874 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8875 {
8876         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8877         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8878         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8879         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8880         enum i40e_status_code ret = I40E_SUCCESS;
8881         int i;
8882         uint32_t bw_max;
8883
8884         /* Check if enabled_tc is same as existing or new TCs */
8885         if (veb->enabled_tc == tc_map)
8886                 return ret;
8887
8888         /* configure tc bandwidth */
8889         memset(&veb_bw, 0, sizeof(veb_bw));
8890         veb_bw.tc_valid_bits = tc_map;
8891         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8892         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8893                 if (tc_map & BIT_ULL(i))
8894                         veb_bw.tc_bw_share_credits[i] = 1;
8895         }
8896         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8897                                                    &veb_bw, NULL);
8898         if (ret) {
8899                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8900                                   " per TC failed = %d",
8901                                   hw->aq.asq_last_status);
8902                 return ret;
8903         }
8904
8905         memset(&ets_query, 0, sizeof(ets_query));
8906         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8907                                                    &ets_query, NULL);
8908         if (ret != I40E_SUCCESS) {
8909                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8910                                  " configuration %u", hw->aq.asq_last_status);
8911                 return ret;
8912         }
8913         memset(&bw_query, 0, sizeof(bw_query));
8914         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8915                                                   &bw_query, NULL);
8916         if (ret != I40E_SUCCESS) {
8917                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8918                                  " configuration %u", hw->aq.asq_last_status);
8919                 return ret;
8920         }
8921
8922         /* store and print out BW info */
8923         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8924         veb->bw_info.bw_max = ets_query.tc_bw_max;
8925         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8926         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8927         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8928                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8929                      I40E_16_BIT_WIDTH);
8930         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8931                 veb->bw_info.bw_ets_share_credits[i] =
8932                                 bw_query.tc_bw_share_credits[i];
8933                 veb->bw_info.bw_ets_credits[i] =
8934                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8935                 /* 4 bits per TC, 4th bit is reserved */
8936                 veb->bw_info.bw_ets_max[i] =
8937                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8938                                   RTE_LEN2MASK(3, uint8_t));
8939                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8940                             veb->bw_info.bw_ets_share_credits[i]);
8941                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8942                             veb->bw_info.bw_ets_credits[i]);
8943                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8944                             veb->bw_info.bw_ets_max[i]);
8945         }
8946
8947         veb->enabled_tc = tc_map;
8948
8949         return ret;
8950 }
8951
8952
8953 /*
8954  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8955  * @vsi: VSI to be configured
8956  * @tc_map: enabled TC bitmap
8957  *
8958  * Returns 0 on success, negative value on failure
8959  */
8960 static enum i40e_status_code
8961 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8962 {
8963         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8964         struct i40e_vsi_context ctxt;
8965         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8966         enum i40e_status_code ret = I40E_SUCCESS;
8967         int i;
8968
8969         /* Check if enabled_tc is same as existing or new TCs */
8970         if (vsi->enabled_tc == tc_map)
8971                 return ret;
8972
8973         /* configure tc bandwidth */
8974         memset(&bw_data, 0, sizeof(bw_data));
8975         bw_data.tc_valid_bits = tc_map;
8976         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8977         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8978                 if (tc_map & BIT_ULL(i))
8979                         bw_data.tc_bw_credits[i] = 1;
8980         }
8981         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8982         if (ret) {
8983                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8984                         " per TC failed = %d",
8985                         hw->aq.asq_last_status);
8986                 goto out;
8987         }
8988         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8989                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8990
8991         /* Update Queue Pairs Mapping for currently enabled UPs */
8992         ctxt.seid = vsi->seid;
8993         ctxt.pf_num = hw->pf_id;
8994         ctxt.vf_num = 0;
8995         ctxt.uplink_seid = vsi->uplink_seid;
8996         ctxt.info = vsi->info;
8997         i40e_get_cap(hw);
8998         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8999         if (ret)
9000                 goto out;
9001
9002         /* Update the VSI after updating the VSI queue-mapping information */
9003         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9004         if (ret) {
9005                 PMD_INIT_LOG(ERR, "Failed to configure "
9006                             "TC queue mapping = %d",
9007                             hw->aq.asq_last_status);
9008                 goto out;
9009         }
9010         /* update the local VSI info with updated queue map */
9011         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9012                                         sizeof(vsi->info.tc_mapping));
9013         (void)rte_memcpy(&vsi->info.queue_mapping,
9014                         &ctxt.info.queue_mapping,
9015                 sizeof(vsi->info.queue_mapping));
9016         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9017         vsi->info.valid_sections = 0;
9018
9019         /* query and update current VSI BW information */
9020         ret = i40e_vsi_get_bw_config(vsi);
9021         if (ret) {
9022                 PMD_INIT_LOG(ERR,
9023                          "Failed updating vsi bw info, err %s aq_err %s",
9024                          i40e_stat_str(hw, ret),
9025                          i40e_aq_str(hw, hw->aq.asq_last_status));
9026                 goto out;
9027         }
9028
9029         vsi->enabled_tc = tc_map;
9030
9031 out:
9032         return ret;
9033 }
9034
9035 /*
9036  * i40e_dcb_hw_configure - program the dcb setting to hw
9037  * @pf: pf the configuration is taken on
9038  * @new_cfg: new configuration
9039  * @tc_map: enabled TC bitmap
9040  *
9041  * Returns 0 on success, negative value on failure
9042  */
9043 static enum i40e_status_code
9044 i40e_dcb_hw_configure(struct i40e_pf *pf,
9045                       struct i40e_dcbx_config *new_cfg,
9046                       uint8_t tc_map)
9047 {
9048         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9049         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9050         struct i40e_vsi *main_vsi = pf->main_vsi;
9051         struct i40e_vsi_list *vsi_list;
9052         enum i40e_status_code ret;
9053         int i;
9054         uint32_t val;
9055
9056         /* Use the FW API if FW > v4.4*/
9057         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9058               (hw->aq.fw_maj_ver >= 5))) {
9059                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9060                                   " to configure DCB");
9061                 return I40E_ERR_FIRMWARE_API_VERSION;
9062         }
9063
9064         /* Check if need reconfiguration */
9065         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9066                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9067                 return I40E_SUCCESS;
9068         }
9069
9070         /* Copy the new config to the current config */
9071         *old_cfg = *new_cfg;
9072         old_cfg->etsrec = old_cfg->etscfg;
9073         ret = i40e_set_dcb_config(hw);
9074         if (ret) {
9075                 PMD_INIT_LOG(ERR,
9076                          "Set DCB Config failed, err %s aq_err %s\n",
9077                          i40e_stat_str(hw, ret),
9078                          i40e_aq_str(hw, hw->aq.asq_last_status));
9079                 return ret;
9080         }
9081         /* set receive Arbiter to RR mode and ETS scheme by default */
9082         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9083                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9084                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9085                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9086                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9087                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9088                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9089                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9090                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9091                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9092                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9093                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9094                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9095         }
9096         /* get local mib to check whether it is configured correctly */
9097         /* IEEE mode */
9098         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9099         /* Get Local DCB Config */
9100         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9101                                      &hw->local_dcbx_config);
9102
9103         /* if Veb is created, need to update TC of it at first */
9104         if (main_vsi->veb) {
9105                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9106                 if (ret)
9107                         PMD_INIT_LOG(WARNING,
9108                                  "Failed configuring TC for VEB seid=%d\n",
9109                                  main_vsi->veb->seid);
9110         }
9111         /* Update each VSI */
9112         i40e_vsi_config_tc(main_vsi, tc_map);
9113         if (main_vsi->veb) {
9114                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9115                         /* Beside main VSI and VMDQ VSIs, only enable default
9116                          * TC for other VSIs
9117                          */
9118                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9119                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9120                                                          tc_map);
9121                         else
9122                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9123                                                          I40E_DEFAULT_TCMAP);
9124                         if (ret)
9125                                 PMD_INIT_LOG(WARNING,
9126                                          "Failed configuring TC for VSI seid=%d\n",
9127                                          vsi_list->vsi->seid);
9128                         /* continue */
9129                 }
9130         }
9131         return I40E_SUCCESS;
9132 }
9133
9134 /*
9135  * i40e_dcb_init_configure - initial dcb config
9136  * @dev: device being configured
9137  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9138  *
9139  * Returns 0 on success, negative value on failure
9140  */
9141 static int
9142 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9143 {
9144         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9145         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9146         int ret = 0;
9147
9148         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9149                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9150                 return -ENOTSUP;
9151         }
9152
9153         /* DCB initialization:
9154          * Update DCB configuration from the Firmware and configure
9155          * LLDP MIB change event.
9156          */
9157         if (sw_dcb == TRUE) {
9158                 ret = i40e_init_dcb(hw);
9159                 /* If lldp agent is stopped, the return value from
9160                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9161                  * adminq status. Otherwise, it should return success.
9162                  */
9163                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9164                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9165                         memset(&hw->local_dcbx_config, 0,
9166                                 sizeof(struct i40e_dcbx_config));
9167                         /* set dcb default configuration */
9168                         hw->local_dcbx_config.etscfg.willing = 0;
9169                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9170                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9171                         hw->local_dcbx_config.etscfg.tsatable[0] =
9172                                                 I40E_IEEE_TSA_ETS;
9173                         hw->local_dcbx_config.etsrec =
9174                                 hw->local_dcbx_config.etscfg;
9175                         hw->local_dcbx_config.pfc.willing = 0;
9176                         hw->local_dcbx_config.pfc.pfccap =
9177                                                 I40E_MAX_TRAFFIC_CLASS;
9178                         /* FW needs one App to configure HW */
9179                         hw->local_dcbx_config.numapps = 1;
9180                         hw->local_dcbx_config.app[0].selector =
9181                                                 I40E_APP_SEL_ETHTYPE;
9182                         hw->local_dcbx_config.app[0].priority = 3;
9183                         hw->local_dcbx_config.app[0].protocolid =
9184                                                 I40E_APP_PROTOID_FCOE;
9185                         ret = i40e_set_dcb_config(hw);
9186                         if (ret) {
9187                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9188                                         " err = %d, aq_err = %d.", ret,
9189                                           hw->aq.asq_last_status);
9190                                 return -ENOSYS;
9191                         }
9192                 } else {
9193                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9194                                           " err = %d, aq_err = %d.", ret,
9195                                           hw->aq.asq_last_status);
9196                         return -ENOTSUP;
9197                 }
9198         } else {
9199                 ret = i40e_aq_start_lldp(hw, NULL);
9200                 if (ret != I40E_SUCCESS)
9201                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9202
9203                 ret = i40e_init_dcb(hw);
9204                 if (!ret) {
9205                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9206                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9207                                                   " DCBX offload.");
9208                                 return -ENOTSUP;
9209                         }
9210                 } else {
9211                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9212                                           " aq_err = %d.", ret,
9213                                           hw->aq.asq_last_status);
9214                         return -ENOTSUP;
9215                 }
9216         }
9217         return 0;
9218 }
9219
9220 /*
9221  * i40e_dcb_setup - setup dcb related config
9222  * @dev: device being configured
9223  *
9224  * Returns 0 on success, negative value on failure
9225  */
9226 static int
9227 i40e_dcb_setup(struct rte_eth_dev *dev)
9228 {
9229         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9230         struct i40e_dcbx_config dcb_cfg;
9231         uint8_t tc_map = 0;
9232         int ret = 0;
9233
9234         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9235                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9236                 return -ENOTSUP;
9237         }
9238
9239         if (pf->vf_num != 0)
9240                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9241
9242         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9243         if (ret) {
9244                 PMD_INIT_LOG(ERR, "invalid dcb config");
9245                 return -EINVAL;
9246         }
9247         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9248         if (ret) {
9249                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9250                 return -ENOSYS;
9251         }
9252
9253         return 0;
9254 }
9255
9256 static int
9257 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9258                       struct rte_eth_dcb_info *dcb_info)
9259 {
9260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9261         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9262         struct i40e_vsi *vsi = pf->main_vsi;
9263         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9264         uint16_t bsf, tc_mapping;
9265         int i, j = 0;
9266
9267         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9268                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9269         else
9270                 dcb_info->nb_tcs = 1;
9271         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9272                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9273         for (i = 0; i < dcb_info->nb_tcs; i++)
9274                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9275
9276         /* get queue mapping if vmdq is disabled */
9277         if (!pf->nb_cfg_vmdq_vsi) {
9278                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9279                         if (!(vsi->enabled_tc & (1 << i)))
9280                                 continue;
9281                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9282                         dcb_info->tc_queue.tc_rxq[j][i].base =
9283                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9284                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9285                         dcb_info->tc_queue.tc_txq[j][i].base =
9286                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9287                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9288                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9289                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9290                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9291                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9292                 }
9293                 return 0;
9294         }
9295
9296         /* get queue mapping if vmdq is enabled */
9297         do {
9298                 vsi = pf->vmdq[j].vsi;
9299                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9300                         if (!(vsi->enabled_tc & (1 << i)))
9301                                 continue;
9302                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9303                         dcb_info->tc_queue.tc_rxq[j][i].base =
9304                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9305                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9306                         dcb_info->tc_queue.tc_txq[j][i].base =
9307                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9308                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9309                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9310                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9311                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9312                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9313                 }
9314                 j++;
9315         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9316         return 0;
9317 }
9318
9319 static int
9320 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9321 {
9322         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9323         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9324         uint16_t interval =
9325                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9326         uint16_t msix_intr;
9327
9328         msix_intr = intr_handle->intr_vec[queue_id];
9329         if (msix_intr == I40E_MISC_VEC_ID)
9330                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9331                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9332                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9333                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9334                                (interval <<
9335                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9336         else
9337                 I40E_WRITE_REG(hw,
9338                                I40E_PFINT_DYN_CTLN(msix_intr -
9339                                                    I40E_RX_VEC_START),
9340                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9341                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9342                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9343                                (interval <<
9344                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9345
9346         I40E_WRITE_FLUSH(hw);
9347         rte_intr_enable(&dev->pci_dev->intr_handle);
9348
9349         return 0;
9350 }
9351
9352 static int
9353 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9354 {
9355         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9357         uint16_t msix_intr;
9358
9359         msix_intr = intr_handle->intr_vec[queue_id];
9360         if (msix_intr == I40E_MISC_VEC_ID)
9361                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9362         else
9363                 I40E_WRITE_REG(hw,
9364                                I40E_PFINT_DYN_CTLN(msix_intr -
9365                                                    I40E_RX_VEC_START),
9366                                0);
9367         I40E_WRITE_FLUSH(hw);
9368
9369         return 0;
9370 }
9371
9372 static int i40e_get_regs(struct rte_eth_dev *dev,
9373                          struct rte_dev_reg_info *regs)
9374 {
9375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9376         uint32_t *ptr_data = regs->data;
9377         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9378         const struct i40e_reg_info *reg_info;
9379
9380         if (ptr_data == NULL) {
9381                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9382                 regs->width = sizeof(uint32_t);
9383                 return 0;
9384         }
9385
9386         /* The first few registers have to be read using AQ operations */
9387         reg_idx = 0;
9388         while (i40e_regs_adminq[reg_idx].name) {
9389                 reg_info = &i40e_regs_adminq[reg_idx++];
9390                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9391                         for (arr_idx2 = 0;
9392                                         arr_idx2 <= reg_info->count2;
9393                                         arr_idx2++) {
9394                                 reg_offset = arr_idx * reg_info->stride1 +
9395                                         arr_idx2 * reg_info->stride2;
9396                                 reg_offset += reg_info->base_addr;
9397                                 ptr_data[reg_offset >> 2] =
9398                                         i40e_read_rx_ctl(hw, reg_offset);
9399                         }
9400         }
9401
9402         /* The remaining registers can be read using primitives */
9403         reg_idx = 0;
9404         while (i40e_regs_others[reg_idx].name) {
9405                 reg_info = &i40e_regs_others[reg_idx++];
9406                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9407                         for (arr_idx2 = 0;
9408                                         arr_idx2 <= reg_info->count2;
9409                                         arr_idx2++) {
9410                                 reg_offset = arr_idx * reg_info->stride1 +
9411                                         arr_idx2 * reg_info->stride2;
9412                                 reg_offset += reg_info->base_addr;
9413                                 ptr_data[reg_offset >> 2] =
9414                                         I40E_READ_REG(hw, reg_offset);
9415                         }
9416         }
9417
9418         return 0;
9419 }
9420
9421 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9422 {
9423         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9424
9425         /* Convert word count to byte count */
9426         return hw->nvm.sr_size << 1;
9427 }
9428
9429 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9430                            struct rte_dev_eeprom_info *eeprom)
9431 {
9432         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9433         uint16_t *data = eeprom->data;
9434         uint16_t offset, length, cnt_words;
9435         int ret_code;
9436
9437         offset = eeprom->offset >> 1;
9438         length = eeprom->length >> 1;
9439         cnt_words = length;
9440
9441         if (offset > hw->nvm.sr_size ||
9442                 offset + length > hw->nvm.sr_size) {
9443                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9444                 return -EINVAL;
9445         }
9446
9447         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9448
9449         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9450         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9451                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9452                 return -EIO;
9453         }
9454
9455         return 0;
9456 }
9457
9458 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9459                                       struct ether_addr *mac_addr)
9460 {
9461         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9462
9463         if (!is_valid_assigned_ether_addr(mac_addr)) {
9464                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9465                 return;
9466         }
9467
9468         /* Flags: 0x3 updates port address */
9469         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9470 }
9471
9472 static int
9473 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9474 {
9475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9476         struct rte_eth_dev_data *dev_data = pf->dev_data;
9477         uint32_t frame_size = mtu + ETHER_HDR_LEN
9478                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9479         int ret = 0;
9480
9481         /* check if mtu is within the allowed range */
9482         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9483                 return -EINVAL;
9484
9485         /* mtu setting is forbidden if port is start */
9486         if (dev_data->dev_started) {
9487                 PMD_DRV_LOG(ERR,
9488                             "port %d must be stopped before configuration\n",
9489                             dev_data->port_id);
9490                 return -EBUSY;
9491         }
9492
9493         if (frame_size > ETHER_MAX_LEN)
9494                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9495         else
9496                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9497
9498         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9499
9500         return ret;
9501 }