drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and inteval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518 };
 519
 520 /* store statistics names and its offset in stats structure */
 521 struct rte_i40e_xstats_name_off {
 522         char name[RTE_ETH_XSTATS_NAME_SIZE];
 523         unsigned offset;
 524 };
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 527         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 528         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 529         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 530         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 531         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 532                 rx_unknown_protocol)},
 533         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 534         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 535         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 536         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 537 };
 538
 539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 540                 sizeof(rte_i40e_stats_strings[0]))
 541
 542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 543         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 544                 tx_dropped_link_down)},
 545         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 546         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 547                 illegal_bytes)},
 548         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 549         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_local_faults)},
 551         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 552                 mac_remote_faults)},
 553         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 554                 rx_length_errors)},
 555         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 556         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 557         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 558         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 559         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 560         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_127)},
 562         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_255)},
 564         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_511)},
 566         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1023)},
 568         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_1522)},
 570         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_big)},
 572         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_undersize)},
 574         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_oversize)},
 576         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 577                 mac_short_packet_dropped)},
 578         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_fragments)},
 580         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 581         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 582         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_127)},
 584         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_255)},
 586         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_511)},
 588         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1023)},
 590         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_1522)},
 592         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_big)},
 594         {"rx_flow_director_atr_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 596         {"rx_flow_director_sb_match_packets",
 597                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 598         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_status)},
 600         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_status)},
 602         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 tx_lpi_count)},
 604         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 605                 rx_lpi_count)},
 606 };
 607
 608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 609                 sizeof(rte_i40e_hw_port_strings[0]))
 610
 611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 612         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xon_rx)},
 614         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 615                 priority_xoff_rx)},
 616 };
 617
 618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 619                 sizeof(rte_i40e_rxq_prio_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_tx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_tx)},
 626         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xon_2_xoff)},
 628 };
 629
 630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 631                 sizeof(rte_i40e_txq_prio_strings[0]))
 632
 633 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 634         struct rte_pci_device *pci_dev)
 635 {
 636         return rte_eth_dev_pci_generic_probe(pci_dev,
 637                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 638 }
 639
 640 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 641 {
 642         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 643 }
 644
 645 static struct rte_pci_driver rte_i40e_pmd = {
 646         .id_table = pci_id_i40e_map,
 647         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 648         .probe = eth_i40e_pci_probe,
 649         .remove = eth_i40e_pci_remove,
 650 };
 651
 652 static inline int
 653 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 654                                      struct rte_eth_link *link)
 655 {
 656         struct rte_eth_link *dst = link;
 657         struct rte_eth_link *src = &(dev->data->dev_link);
 658
 659         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 660                                         *(uint64_t *)src) == 0)
 661                 return -1;
 662
 663         return 0;
 664 }
 665
 666 static inline int
 667 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 668                                       struct rte_eth_link *link)
 669 {
 670         struct rte_eth_link *dst = &(dev->data->dev_link);
 671         struct rte_eth_link *src = link;
 672
 673         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 674                                         *(uint64_t *)src) == 0)
 675                 return -1;
 676
 677         return 0;
 678 }
 679
 680 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 681 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 682 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 683
 684 #ifndef I40E_GLQF_ORT
 685 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 686 #endif
 687 #ifndef I40E_GLQF_PIT
 688 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 689 #endif
 690 #ifndef I40E_GLQF_L3_MAP
 691 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 692 #endif
 693
 694 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 695 {
 696         /*
 697          * Initialize registers for flexible payload, which should be set by NVM.
 698          * This should be removed from code once it is fixed in NVM.
 699          */
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 710         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 712
 713         /* Initialize registers for parsing packet type of QinQ */
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 715         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 716 }
 717
 718 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 719
 720 /*
 721  * Add a ethertype filter to drop all flow control frames transmitted
 722  * from VSIs.
 723 */
 724 static void
 725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 726 {
 727         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 728         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 729                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 731         int ret;
 732
 733         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 734                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 735                                 pf->main_vsi_seid, 0,
 736                                 TRUE, NULL, NULL);
 737         if (ret)
 738                 PMD_INIT_LOG(ERR,
 739                         "Failed to add filter to drop flow control frames from VSIs.");
 740 }
 741
 742 static int
 743 floating_veb_list_handler(__rte_unused const char *key,
 744                           const char *floating_veb_value,
 745                           void *opaque)
 746 {
 747         int idx = 0;
 748         unsigned int count = 0;
 749         char *end = NULL;
 750         int min, max;
 751         bool *vf_floating_veb = opaque;
 752
 753         while (isblank(*floating_veb_value))
 754                 floating_veb_value++;
 755
 756         /* Reset floating VEB configuration for VFs */
 757         for (idx = 0; idx < I40E_MAX_VF; idx++)
 758                 vf_floating_veb[idx] = false;
 759
 760         min = I40E_MAX_VF;
 761         do {
 762                 while (isblank(*floating_veb_value))
 763                         floating_veb_value++;
 764                 if (*floating_veb_value == '\0')
 765                         return -1;
 766                 errno = 0;
 767                 idx = strtoul(floating_veb_value, &end, 10);
 768                 if (errno || end == NULL)
 769                         return -1;
 770                 while (isblank(*end))
 771                         end++;
 772                 if (*end == '-') {
 773                         min = idx;
 774                 } else if ((*end == ';') || (*end == '\0')) {
 775                         max = idx;
 776                         if (min == I40E_MAX_VF)
 777                                 min = idx;
 778                         if (max >= I40E_MAX_VF)
 779                                 max = I40E_MAX_VF - 1;
 780                         for (idx = min; idx <= max; idx++) {
 781                                 vf_floating_veb[idx] = true;
 782                                 count++;
 783                         }
 784                         min = I40E_MAX_VF;
 785                 } else {
 786                         return -1;
 787                 }
 788                 floating_veb_value = end + 1;
 789         } while (*end != '\0');
 790
 791         if (count == 0)
 792                 return -1;
 793
 794         return 0;
 795 }
 796
 797 static void
 798 config_vf_floating_veb(struct rte_devargs *devargs,
 799                        uint16_t floating_veb,
 800                        bool *vf_floating_veb)
 801 {
 802         struct rte_kvargs *kvlist;
 803         int i;
 804         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 805
 806         if (!floating_veb)
 807                 return;
 808         /* All the VFs attach to the floating VEB by default
 809          * when the floating VEB is enabled.
 810          */
 811         for (i = 0; i < I40E_MAX_VF; i++)
 812                 vf_floating_veb[i] = true;
 813
 814         if (devargs == NULL)
 815                 return;
 816
 817         kvlist = rte_kvargs_parse(devargs->args, NULL);
 818         if (kvlist == NULL)
 819                 return;
 820
 821         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 822                 rte_kvargs_free(kvlist);
 823                 return;
 824         }
 825         /* When the floating_veb_list parameter exists, all the VFs
 826          * will attach to the legacy VEB firstly, then configure VFs
 827          * to the floating VEB according to the floating_veb_list.
 828          */
 829         if (rte_kvargs_process(kvlist, floating_veb_list,
 830                                floating_veb_list_handler,
 831                                vf_floating_veb) < 0) {
 832                 rte_kvargs_free(kvlist);
 833                 return;
 834         }
 835         rte_kvargs_free(kvlist);
 836 }
 837
 838 static int
 839 i40e_check_floating_handler(__rte_unused const char *key,
 840                             const char *value,
 841                             __rte_unused void *opaque)
 842 {
 843         if (strcmp(value, "1"))
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 static int
 850 is_floating_veb_supported(struct rte_devargs *devargs)
 851 {
 852         struct rte_kvargs *kvlist;
 853         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 854
 855         if (devargs == NULL)
 856                 return 0;
 857
 858         kvlist = rte_kvargs_parse(devargs->args, NULL);
 859         if (kvlist == NULL)
 860                 return 0;
 861
 862         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 863                 rte_kvargs_free(kvlist);
 864                 return 0;
 865         }
 866         /* Floating VEB is enabled when there's key-value:
 867          * enable_floating_veb=1
 868          */
 869         if (rte_kvargs_process(kvlist, floating_veb_key,
 870                                i40e_check_floating_handler, NULL) < 0) {
 871                 rte_kvargs_free(kvlist);
 872                 return 0;
 873         }
 874         rte_kvargs_free(kvlist);
 875
 876         return 1;
 877 }
 878
 879 static void
 880 config_floating_veb(struct rte_eth_dev *dev)
 881 {
 882         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 885
 886         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 887
 888         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 889                 pf->floating_veb =
 890                         is_floating_veb_supported(pci_dev->device.devargs);
 891                 config_vf_floating_veb(pci_dev->device.devargs,
 892                                        pf->floating_veb,
 893                                        pf->floating_veb_list);
 894         } else {
 895                 pf->floating_veb = false;
 896         }
 897 }
 898
 899 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 900 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 901
 902 static int
 903 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 904 {
 905         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 906         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 907         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 908         int ret;
 909
 910         struct rte_hash_parameters ethertype_hash_params = {
 911                 .name = ethertype_hash_name,
 912                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 913                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 914                 .hash_func = rte_hash_crc,
 915                 .hash_func_init_val = 0,
 916                 .socket_id = rte_socket_id(),
 917         };
 918
 919         /* Initialize ethertype filter rule list and hash */
 920         TAILQ_INIT(&ethertype_rule->ethertype_list);
 921         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 922                  "ethertype_%s", dev->data->name);
 923         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 924         if (!ethertype_rule->hash_table) {
 925                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 926                 return -EINVAL;
 927         }
 928         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 929                                        sizeof(struct i40e_ethertype_filter *) *
 930                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 931                                        0);
 932         if (!ethertype_rule->hash_map) {
 933                 PMD_INIT_LOG(ERR,
 934                              "Failed to allocate memory for ethertype hash map!");
 935                 ret = -ENOMEM;
 936                 goto err_ethertype_hash_map_alloc;
 937         }
 938
 939         return 0;
 940
 941 err_ethertype_hash_map_alloc:
 942         rte_hash_free(ethertype_rule->hash_table);
 943
 944         return ret;
 945 }
 946
 947 static int
 948 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 949 {
 950         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 951         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 952         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 953         int ret;
 954
 955         struct rte_hash_parameters tunnel_hash_params = {
 956                 .name = tunnel_hash_name,
 957                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 958                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 959                 .hash_func = rte_hash_crc,
 960                 .hash_func_init_val = 0,
 961                 .socket_id = rte_socket_id(),
 962         };
 963
 964         /* Initialize tunnel filter rule list and hash */
 965         TAILQ_INIT(&tunnel_rule->tunnel_list);
 966         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 967                  "tunnel_%s", dev->data->name);
 968         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 969         if (!tunnel_rule->hash_table) {
 970                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 971                 return -EINVAL;
 972         }
 973         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 974                                     sizeof(struct i40e_tunnel_filter *) *
 975                                     I40E_MAX_TUNNEL_FILTER_NUM,
 976                                     0);
 977         if (!tunnel_rule->hash_map) {
 978                 PMD_INIT_LOG(ERR,
 979                              "Failed to allocate memory for tunnel hash map!");
 980                 ret = -ENOMEM;
 981                 goto err_tunnel_hash_map_alloc;
 982         }
 983
 984         return 0;
 985
 986 err_tunnel_hash_map_alloc:
 987         rte_hash_free(tunnel_rule->hash_table);
 988
 989         return ret;
 990 }
 991
 992 static int
 993 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 994 {
 995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 996         struct i40e_fdir_info *fdir_info = &pf->fdir;
 997         char fdir_hash_name[RTE_HASH_NAMESIZE];
 998         int ret;
 999
1000         struct rte_hash_parameters fdir_hash_params = {
1001                 .name = fdir_hash_name,
1002                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1003                 .key_len = sizeof(struct rte_eth_fdir_input),
1004                 .hash_func = rte_hash_crc,
1005                 .hash_func_init_val = 0,
1006                 .socket_id = rte_socket_id(),
1007         };
1008
1009         /* Initialize flow director filter rule list and hash */
1010         TAILQ_INIT(&fdir_info->fdir_list);
1011         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1012                  "fdir_%s", dev->data->name);
1013         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1014         if (!fdir_info->hash_table) {
1015                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1016                 return -EINVAL;
1017         }
1018         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1019                                           sizeof(struct i40e_fdir_filter *) *
1020                                           I40E_MAX_FDIR_FILTER_NUM,
1021                                           0);
1022         if (!fdir_info->hash_map) {
1023                 PMD_INIT_LOG(ERR,
1024                              "Failed to allocate memory for fdir hash map!");
1025                 ret = -ENOMEM;
1026                 goto err_fdir_hash_map_alloc;
1027         }
1028         return 0;
1029
1030 err_fdir_hash_map_alloc:
1031         rte_hash_free(fdir_info->hash_table);
1032
1033         return ret;
1034 }
1035
1036 static int
1037 eth_i40e_dev_init(struct rte_eth_dev *dev)
1038 {
1039         struct rte_pci_device *pci_dev;
1040         struct rte_intr_handle *intr_handle;
1041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043         struct i40e_vsi *vsi;
1044         int ret;
1045         uint32_t len;
1046         uint8_t aq_fail = 0;
1047
1048         PMD_INIT_FUNC_TRACE();
1049
1050         dev->dev_ops = &i40e_eth_dev_ops;
1051         dev->rx_pkt_burst = i40e_recv_pkts;
1052         dev->tx_pkt_burst = i40e_xmit_pkts;
1053         dev->tx_pkt_prepare = i40e_prep_pkts;
1054
1055         /* for secondary processes, we don't initialise any further as primary
1056          * has already done this work. Only check we don't need a different
1057          * RX function */
1058         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1059                 i40e_set_rx_function(dev);
1060                 i40e_set_tx_function(dev);
1061                 return 0;
1062         }
1063         i40e_set_default_ptype_table(dev);
1064         pci_dev = I40E_DEV_TO_PCI(dev);
1065         intr_handle = &pci_dev->intr_handle;
1066
1067         rte_eth_copy_pci_info(dev, pci_dev);
1068         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1069
1070         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071         pf->adapter->eth_dev = dev;
1072         pf->dev_data = dev->data;
1073
1074         hw->back = I40E_PF_TO_ADAPTER(pf);
1075         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1076         if (!hw->hw_addr) {
1077                 PMD_INIT_LOG(ERR,
1078                         "Hardware is not available, as address is NULL");
1079                 return -ENODEV;
1080         }
1081
1082         hw->vendor_id = pci_dev->id.vendor_id;
1083         hw->device_id = pci_dev->id.device_id;
1084         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086         hw->bus.device = pci_dev->addr.devid;
1087         hw->bus.func = pci_dev->addr.function;
1088         hw->adapter_stopped = 0;
1089
1090         /* Make sure all is clean before doing PF reset */
1091         i40e_clear_hw(hw);
1092
1093         /* Initialize the hardware */
1094         i40e_hw_init(dev);
1095
1096         /* Reset here to make sure all is clean for each PF */
1097         ret = i40e_pf_reset(hw);
1098         if (ret) {
1099                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1100                 return ret;
1101         }
1102
1103         /* Initialize the shared code (base driver) */
1104         ret = i40e_init_shared_code(hw);
1105         if (ret) {
1106                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1107                 return ret;
1108         }
1109
1110         /*
1111          * To work around the NVM issue, initialize registers
1112          * for flexible payload and packet type of QinQ by
1113          * software. It should be removed once issues are fixed
1114          * in NVM.
1115          */
1116         i40e_GLQF_reg_init(hw);
1117
1118         /* Initialize the input set for filters (hash and fd) to default value */
1119         i40e_filter_input_set_init(pf);
1120
1121         /* Initialize the parameters for adminq */
1122         i40e_init_adminq_parameter(hw);
1123         ret = i40e_init_adminq(hw);
1124         if (ret != I40E_SUCCESS) {
1125                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1126                 return -EIO;
1127         }
1128         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131                      ((hw->nvm.version >> 12) & 0xf),
1132                      ((hw->nvm.version >> 4) & 0xff),
1133                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1134
1135         /* initialise the L3_MAP register */
1136         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1137                                    0x00000028,  NULL);
1138         if (ret)
1139                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1140
1141         /* Need the special FW version to support floating VEB */
1142         config_floating_veb(dev);
1143         /* Clear PXE mode */
1144         i40e_clear_pxe_mode(hw);
1145         ret = i40e_dev_sync_phy_type(hw);
1146         if (ret) {
1147                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1148                 goto err_sync_phy_type;
1149         }
1150         /*
1151          * On X710, performance number is far from the expectation on recent
1152          * firmware versions. The fix for this issue may not be integrated in
1153          * the following firmware version. So the workaround in software driver
1154          * is needed. It needs to modify the initial values of 3 internal only
1155          * registers. Note that the workaround can be removed when it is fixed
1156          * in firmware in the future.
1157          */
1158         i40e_configure_registers(hw);
1159
1160         /* Get hw capabilities */
1161         ret = i40e_get_cap(hw);
1162         if (ret != I40E_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164                 goto err_get_capabilities;
1165         }
1166
1167         /* Initialize parameters for PF */
1168         ret = i40e_pf_parameter_init(dev);
1169         if (ret != 0) {
1170                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171                 goto err_parameter_init;
1172         }
1173
1174         /* Initialize the queue management */
1175         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1176         if (ret < 0) {
1177                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178                 goto err_qp_pool_init;
1179         }
1180         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181                                 hw->func_caps.num_msix_vectors - 1);
1182         if (ret < 0) {
1183                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184                 goto err_msix_pool_init;
1185         }
1186
1187         /* Initialize lan hmc */
1188         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189                                 hw->func_caps.num_rx_qp, 0, 0);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192                 goto err_init_lan_hmc;
1193         }
1194
1195         /* Configure lan hmc */
1196         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197         if (ret != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199                 goto err_configure_lan_hmc;
1200         }
1201
1202         /* Get and check the mac address */
1203         i40e_get_mac_addr(hw, hw->mac.addr);
1204         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205                 PMD_INIT_LOG(ERR, "mac address is not valid");
1206                 ret = -EIO;
1207                 goto err_get_mac_addr;
1208         }
1209         /* Copy the permanent MAC address */
1210         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211                         (struct ether_addr *) hw->mac.perm_addr);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* Set the global registers with default ether type value */
1218         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219         if (ret != I40E_SUCCESS) {
1220                 PMD_INIT_LOG(ERR,
1221                         "Failed to set the default outer VLAN ether type");
1222                 goto err_setup_pf_switch;
1223         }
1224
1225         /* PF setup, which includes VSI setup */
1226         ret = i40e_pf_setup(pf);
1227         if (ret) {
1228                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229                 goto err_setup_pf_switch;
1230         }
1231
1232         /* reset all stats of the device, including pf and main vsi */
1233         i40e_dev_stats_reset(dev);
1234
1235         vsi = pf->main_vsi;
1236
1237         /* Disable double vlan by default */
1238         i40e_vsi_config_double_vlan(vsi, FALSE);
1239
1240         /* Disable S-TAG identification when floating_veb is disabled */
1241         if (!pf->floating_veb) {
1242                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1246                 }
1247         }
1248
1249         if (!vsi->max_macaddrs)
1250                 len = ETHER_ADDR_LEN;
1251         else
1252                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1253
1254         /* Should be after VSI initialized */
1255         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256         if (!dev->data->mac_addrs) {
1257                 PMD_INIT_LOG(ERR,
1258                         "Failed to allocated memory for storing mac address");
1259                 goto err_mac_alloc;
1260         }
1261         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262                                         &dev->data->mac_addrs[0]);
1263
1264         /* Init dcb to sw mode by default */
1265         ret = i40e_dcb_init_configure(dev, TRUE);
1266         if (ret != I40E_SUCCESS) {
1267                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268                 pf->flags &= ~I40E_FLAG_DCB;
1269         }
1270         /* Update HW struct after DCB configuration */
1271         i40e_get_cap(hw);
1272
1273         /* initialize pf host driver to setup SRIOV resource if applicable */
1274         i40e_pf_host_init(dev);
1275
1276         /* register callback func to eal lib */
1277         rte_intr_callback_register(intr_handle,
1278                                    i40e_dev_interrupt_handler, dev);
1279
1280         /* configure and enable device interrupt */
1281         i40e_pf_config_irq0(hw, TRUE);
1282         i40e_pf_enable_irq0(hw);
1283
1284         /* enable uio intr after callback register */
1285         rte_intr_enable(intr_handle);
1286         /*
1287          * Add an ethertype filter to drop all flow control frames transmitted
1288          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1289          * frames to wire.
1290          */
1291         i40e_add_tx_flow_control_drop_filter(pf);
1292
1293         /* Set the max frame size to 0x2600 by default,
1294          * in case other drivers changed the default value.
1295          */
1296         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1297
1298         /* initialize mirror rule list */
1299         TAILQ_INIT(&pf->mirror_list);
1300
1301         ret = i40e_init_ethtype_filter_list(dev);
1302         if (ret < 0)
1303                 goto err_init_ethtype_filter_list;
1304         ret = i40e_init_tunnel_filter_list(dev);
1305         if (ret < 0)
1306                 goto err_init_tunnel_filter_list;
1307         ret = i40e_init_fdir_filter_list(dev);
1308         if (ret < 0)
1309                 goto err_init_fdir_filter_list;
1310
1311         return 0;
1312
1313 err_init_fdir_filter_list:
1314         rte_free(pf->tunnel.hash_table);
1315         rte_free(pf->tunnel.hash_map);
1316 err_init_tunnel_filter_list:
1317         rte_free(pf->ethertype.hash_table);
1318         rte_free(pf->ethertype.hash_map);
1319 err_init_ethtype_filter_list:
1320         rte_free(dev->data->mac_addrs);
1321 err_mac_alloc:
1322         i40e_vsi_release(pf->main_vsi);
1323 err_setup_pf_switch:
1324 err_get_mac_addr:
1325 err_configure_lan_hmc:
1326         (void)i40e_shutdown_lan_hmc(hw);
1327 err_init_lan_hmc:
1328         i40e_res_pool_destroy(&pf->msix_pool);
1329 err_msix_pool_init:
1330         i40e_res_pool_destroy(&pf->qp_pool);
1331 err_qp_pool_init:
1332 err_parameter_init:
1333 err_get_capabilities:
1334 err_sync_phy_type:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = I40E_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int
1468 i40e_dev_configure(struct rte_eth_dev *dev)
1469 {
1470         struct i40e_adapter *ad =
1471                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1473         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1474         int i, ret;
1475
1476         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1477          * bulk allocation or vector Rx preconditions we will reset it.
1478          */
1479         ad->rx_bulk_alloc_allowed = true;
1480         ad->rx_vec_allowed = true;
1481         ad->tx_simple_allowed = true;
1482         ad->tx_vec_allowed = true;
1483
1484         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1485                 ret = i40e_fdir_setup(pf);
1486                 if (ret != I40E_SUCCESS) {
1487                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1488                         return -ENOTSUP;
1489                 }
1490                 ret = i40e_fdir_configure(dev);
1491                 if (ret < 0) {
1492                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1493                         goto err;
1494                 }
1495         } else
1496                 i40e_fdir_teardown(pf);
1497
1498         ret = i40e_dev_init_vlan(dev);
1499         if (ret < 0)
1500                 goto err;
1501
1502         /* VMDQ setup.
1503          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1504          *  RSS setting have different requirements.
1505          *  General PMD driver call sequence are NIC init, configure,
1506          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1507          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1508          *  applicable. So, VMDQ setting has to be done before
1509          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1510          *  For RSS setting, it will try to calculate actual configured RX queue
1511          *  number, which will be available after rx_queue_setup(). dev_start()
1512          *  function is good to place RSS setup.
1513          */
1514         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1515                 ret = i40e_vmdq_setup(dev);
1516                 if (ret)
1517                         goto err;
1518         }
1519
1520         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1521                 ret = i40e_dcb_setup(dev);
1522                 if (ret) {
1523                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1524                         goto err_dcb;
1525                 }
1526         }
1527
1528         TAILQ_INIT(&pf->flow_list);
1529
1530         return 0;
1531
1532 err_dcb:
1533         /* need to release vmdq resource if exists */
1534         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1535                 i40e_vsi_release(pf->vmdq[i].vsi);
1536                 pf->vmdq[i].vsi = NULL;
1537         }
1538         rte_free(pf->vmdq);
1539         pf->vmdq = NULL;
1540 err:
1541         /* need to release fdir resource if exists */
1542         i40e_fdir_teardown(pf);
1543         return ret;
1544 }
1545
1546 void
1547 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1548 {
1549         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1550         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1551         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1553         uint16_t msix_vect = vsi->msix_intr;
1554         uint16_t i;
1555
1556         for (i = 0; i < vsi->nb_qps; i++) {
1557                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1558                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1559                 rte_wmb();
1560         }
1561
1562         if (vsi->type != I40E_VSI_SRIOV) {
1563                 if (!rte_intr_allow_others(intr_handle)) {
1564                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1565                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1566                         I40E_WRITE_REG(hw,
1567                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1568                                        0);
1569                 } else {
1570                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1571                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1572                         I40E_WRITE_REG(hw,
1573                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1574                                                        msix_vect - 1), 0);
1575                 }
1576         } else {
1577                 uint32_t reg;
1578                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1579                         vsi->user_param + (msix_vect - 1);
1580
1581                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1582                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1583         }
1584         I40E_WRITE_FLUSH(hw);
1585 }
1586
1587 static void
1588 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1589                        int base_queue, int nb_queue)
1590 {
1591         int i;
1592         uint32_t val;
1593         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1594
1595         /* Bind all RX queues to allocated MSIX interrupt */
1596         for (i = 0; i < nb_queue; i++) {
1597                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1598                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1599                         ((base_queue + i + 1) <<
1600                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1601                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1602                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1603
1604                 if (i == nb_queue - 1)
1605                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1606                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1607         }
1608
1609         /* Write first RX queue to Link list register as the head element */
1610         if (vsi->type != I40E_VSI_SRIOV) {
1611                 uint16_t interval =
1612                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1613
1614                 if (msix_vect == I40E_MISC_VEC_ID) {
1615                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1616                                        (base_queue <<
1617                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1618                                        (0x0 <<
1619                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1620                         I40E_WRITE_REG(hw,
1621                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1622                                        interval);
1623                 } else {
1624                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1625                                        (base_queue <<
1626                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1627                                        (0x0 <<
1628                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1629                         I40E_WRITE_REG(hw,
1630                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1631                                                        msix_vect - 1),
1632                                        interval);
1633                 }
1634         } else {
1635                 uint32_t reg;
1636
1637                 if (msix_vect == I40E_MISC_VEC_ID) {
1638                         I40E_WRITE_REG(hw,
1639                                        I40E_VPINT_LNKLST0(vsi->user_param),
1640                                        (base_queue <<
1641                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1642                                        (0x0 <<
1643                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1644                 } else {
1645                         /* num_msix_vectors_vf needs to minus irq0 */
1646                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1647                                 vsi->user_param + (msix_vect - 1);
1648
1649                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1650                                        (base_queue <<
1651                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1652                                        (0x0 <<
1653                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1654                 }
1655         }
1656
1657         I40E_WRITE_FLUSH(hw);
1658 }
1659
1660 void
1661 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1662 {
1663         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1664         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1665         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1667         uint16_t msix_vect = vsi->msix_intr;
1668         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1669         uint16_t queue_idx = 0;
1670         int record = 0;
1671         uint32_t val;
1672         int i;
1673
1674         for (i = 0; i < vsi->nb_qps; i++) {
1675                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1676                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1677         }
1678
1679         /* INTENA flag is not auto-cleared for interrupt */
1680         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1681         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1682                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1683                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1684         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1685
1686         /* VF bind interrupt */
1687         if (vsi->type == I40E_VSI_SRIOV) {
1688                 __vsi_queues_bind_intr(vsi, msix_vect,
1689                                        vsi->base_queue, vsi->nb_qps);
1690                 return;
1691         }
1692
1693         /* PF & VMDq bind interrupt */
1694         if (rte_intr_dp_is_en(intr_handle)) {
1695                 if (vsi->type == I40E_VSI_MAIN) {
1696                         queue_idx = 0;
1697                         record = 1;
1698                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1699                         struct i40e_vsi *main_vsi =
1700                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1701                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1702                         record = 1;
1703                 }
1704         }
1705
1706         for (i = 0; i < vsi->nb_used_qps; i++) {
1707                 if (nb_msix <= 1) {
1708                         if (!rte_intr_allow_others(intr_handle))
1709                                 /* allow to share MISC_VEC_ID */
1710                                 msix_vect = I40E_MISC_VEC_ID;
1711
1712                         /* no enough msix_vect, map all to one */
1713                         __vsi_queues_bind_intr(vsi, msix_vect,
1714                                                vsi->base_queue + i,
1715                                                vsi->nb_used_qps - i);
1716                         for (; !!record && i < vsi->nb_used_qps; i++)
1717                                 intr_handle->intr_vec[queue_idx + i] =
1718                                         msix_vect;
1719                         break;
1720                 }
1721                 /* 1:1 queue/msix_vect mapping */
1722                 __vsi_queues_bind_intr(vsi, msix_vect,
1723                                        vsi->base_queue + i, 1);
1724                 if (!!record)
1725                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1726
1727                 msix_vect++;
1728                 nb_msix--;
1729         }
1730 }
1731
1732 static void
1733 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1734 {
1735         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1736         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1737         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1738         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1739         uint16_t interval = i40e_calc_itr_interval(\
1740                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1741         uint16_t msix_intr, i;
1742
1743         if (rte_intr_allow_others(intr_handle))
1744                 for (i = 0; i < vsi->nb_msix; i++) {
1745                         msix_intr = vsi->msix_intr + i;
1746                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1747                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1748                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1749                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1750                                 (interval <<
1751                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1752                 }
1753         else
1754                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1755                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1756                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1757                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1758                                (interval <<
1759                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1760
1761         I40E_WRITE_FLUSH(hw);
1762 }
1763
1764 static void
1765 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1766 {
1767         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1769         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771         uint16_t msix_intr, i;
1772
1773         if (rte_intr_allow_others(intr_handle))
1774                 for (i = 0; i < vsi->nb_msix; i++) {
1775                         msix_intr = vsi->msix_intr + i;
1776                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1777                                        0);
1778                 }
1779         else
1780                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1781
1782         I40E_WRITE_FLUSH(hw);
1783 }
1784
1785 static inline uint8_t
1786 i40e_parse_link_speeds(uint16_t link_speeds)
1787 {
1788         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1789
1790         if (link_speeds & ETH_LINK_SPEED_40G)
1791                 link_speed |= I40E_LINK_SPEED_40GB;
1792         if (link_speeds & ETH_LINK_SPEED_25G)
1793                 link_speed |= I40E_LINK_SPEED_25GB;
1794         if (link_speeds & ETH_LINK_SPEED_20G)
1795                 link_speed |= I40E_LINK_SPEED_20GB;
1796         if (link_speeds & ETH_LINK_SPEED_10G)
1797                 link_speed |= I40E_LINK_SPEED_10GB;
1798         if (link_speeds & ETH_LINK_SPEED_1G)
1799                 link_speed |= I40E_LINK_SPEED_1GB;
1800         if (link_speeds & ETH_LINK_SPEED_100M)
1801                 link_speed |= I40E_LINK_SPEED_100MB;
1802
1803         return link_speed;
1804 }
1805
1806 static int
1807 i40e_phy_conf_link(struct i40e_hw *hw,
1808                    uint8_t abilities,
1809                    uint8_t force_speed,
1810                    bool is_up)
1811 {
1812         enum i40e_status_code status;
1813         struct i40e_aq_get_phy_abilities_resp phy_ab;
1814         struct i40e_aq_set_phy_config phy_conf;
1815         enum i40e_aq_phy_type cnt;
1816         uint32_t phy_type_mask = 0;
1817
1818         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1819                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1820                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1821                         I40E_AQ_PHY_FLAG_LOW_POWER;
1822         const uint8_t advt = I40E_LINK_SPEED_40GB |
1823                         I40E_LINK_SPEED_25GB |
1824                         I40E_LINK_SPEED_10GB |
1825                         I40E_LINK_SPEED_1GB |
1826                         I40E_LINK_SPEED_100MB;
1827         int ret = -ENOTSUP;
1828
1829
1830         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1831                                               NULL);
1832         if (status)
1833                 return ret;
1834
1835         /* If link already up, no need to set up again */
1836         if (is_up && phy_ab.phy_type != 0)
1837                 return I40E_SUCCESS;
1838
1839         memset(&phy_conf, 0, sizeof(phy_conf));
1840
1841         /* bits 0-2 use the values from get_phy_abilities_resp */
1842         abilities &= ~mask;
1843         abilities |= phy_ab.abilities & mask;
1844
1845         /* update ablities and speed */
1846         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1847                 phy_conf.link_speed = advt;
1848         else
1849                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1850
1851         phy_conf.abilities = abilities;
1852
1853
1854
1855         /* To enable link, phy_type mask needs to include each type */
1856         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1857                 phy_type_mask |= 1 << cnt;
1858
1859         /* use get_phy_abilities_resp value for the rest */
1860         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1861         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1862                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1863                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1864         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1865         phy_conf.eee_capability = phy_ab.eee_capability;
1866         phy_conf.eeer = phy_ab.eeer_val;
1867         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1868
1869         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1870                     phy_ab.abilities, phy_ab.link_speed);
1871         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1872                     phy_conf.abilities, phy_conf.link_speed);
1873
1874         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1875         if (status)
1876                 return ret;
1877
1878         return I40E_SUCCESS;
1879 }
1880
1881 static int
1882 i40e_apply_link_speed(struct rte_eth_dev *dev)
1883 {
1884         uint8_t speed;
1885         uint8_t abilities = 0;
1886         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1887         struct rte_eth_conf *conf = &dev->data->dev_conf;
1888
1889         speed = i40e_parse_link_speeds(conf->link_speeds);
1890         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1891         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1892                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1893         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1894
1895         return i40e_phy_conf_link(hw, abilities, speed, true);
1896 }
1897
1898 static int
1899 i40e_dev_start(struct rte_eth_dev *dev)
1900 {
1901         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1903         struct i40e_vsi *main_vsi = pf->main_vsi;
1904         int ret, i;
1905         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1906         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1907         uint32_t intr_vector = 0;
1908         struct i40e_vsi *vsi;
1909
1910         hw->adapter_stopped = 0;
1911
1912         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1913                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1914                              dev->data->port_id);
1915                 return -EINVAL;
1916         }
1917
1918         rte_intr_disable(intr_handle);
1919
1920         if ((rte_intr_cap_multiple(intr_handle) ||
1921              !RTE_ETH_DEV_SRIOV(dev).active) &&
1922             dev->data->dev_conf.intr_conf.rxq != 0) {
1923                 intr_vector = dev->data->nb_rx_queues;
1924                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1925                 if (ret)
1926                         return ret;
1927         }
1928
1929         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1930                 intr_handle->intr_vec =
1931                         rte_zmalloc("intr_vec",
1932                                     dev->data->nb_rx_queues * sizeof(int),
1933                                     0);
1934                 if (!intr_handle->intr_vec) {
1935                         PMD_INIT_LOG(ERR,
1936                                 "Failed to allocate %d rx_queues intr_vec",
1937                                 dev->data->nb_rx_queues);
1938                         return -ENOMEM;
1939                 }
1940         }
1941
1942         /* Initialize VSI */
1943         ret = i40e_dev_rxtx_init(pf);
1944         if (ret != I40E_SUCCESS) {
1945                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1946                 goto err_up;
1947         }
1948
1949         /* Map queues with MSIX interrupt */
1950         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1951                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1952         i40e_vsi_queues_bind_intr(main_vsi);
1953         i40e_vsi_enable_queues_intr(main_vsi);
1954
1955         /* Map VMDQ VSI queues with MSIX interrupt */
1956         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1957                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1958                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1959                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1960         }
1961
1962         /* enable FDIR MSIX interrupt */
1963         if (pf->fdir.fdir_vsi) {
1964                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1965                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1966         }
1967
1968         /* Enable all queues which have been configured */
1969         ret = i40e_dev_switch_queues(pf, TRUE);
1970         if (ret != I40E_SUCCESS) {
1971                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1972                 goto err_up;
1973         }
1974
1975         /* Enable receiving broadcast packets */
1976         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1977         if (ret != I40E_SUCCESS)
1978                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1979
1980         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1981                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1982                                                 true, NULL);
1983                 if (ret != I40E_SUCCESS)
1984                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1985         }
1986
1987         /* Enable the VLAN promiscuous mode. */
1988         if (pf->vfs) {
1989                 for (i = 0; i < pf->vf_num; i++) {
1990                         vsi = pf->vfs[i].vsi;
1991                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1992                                                      true, NULL);
1993                 }
1994         }
1995
1996         /* Apply link configure */
1997         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1998                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1999                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2000                                 ETH_LINK_SPEED_40G)) {
2001                 PMD_DRV_LOG(ERR, "Invalid link setting");
2002                 goto err_up;
2003         }
2004         ret = i40e_apply_link_speed(dev);
2005         if (I40E_SUCCESS != ret) {
2006                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2007                 goto err_up;
2008         }
2009
2010         if (!rte_intr_allow_others(intr_handle)) {
2011                 rte_intr_callback_unregister(intr_handle,
2012                                              i40e_dev_interrupt_handler,
2013                                              (void *)dev);
2014                 /* configure and enable device interrupt */
2015                 i40e_pf_config_irq0(hw, FALSE);
2016                 i40e_pf_enable_irq0(hw);
2017
2018                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2019                         PMD_INIT_LOG(INFO,
2020                                 "lsc won't enable because of no intr multiplex");
2021         } else {
2022                 ret = i40e_aq_set_phy_int_mask(hw,
2023                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2024                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2025                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2026                 if (ret != I40E_SUCCESS)
2027                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2028
2029                 /* Call get_link_info aq commond to enable/disable LSE */
2030                 i40e_dev_link_update(dev, 0);
2031         }
2032
2033         /* enable uio intr after callback register */
2034         rte_intr_enable(intr_handle);
2035
2036         i40e_filter_restore(pf);
2037
2038         return I40E_SUCCESS;
2039
2040 err_up:
2041         i40e_dev_switch_queues(pf, FALSE);
2042         i40e_dev_clear_queues(dev);
2043
2044         return ret;
2045 }
2046
2047 static void
2048 i40e_dev_stop(struct rte_eth_dev *dev)
2049 {
2050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2051         struct i40e_vsi *main_vsi = pf->main_vsi;
2052         struct i40e_mirror_rule *p_mirror;
2053         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055         int i;
2056
2057         /* Disable all queues */
2058         i40e_dev_switch_queues(pf, FALSE);
2059
2060         /* un-map queues with interrupt registers */
2061         i40e_vsi_disable_queues_intr(main_vsi);
2062         i40e_vsi_queues_unbind_intr(main_vsi);
2063
2064         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2065                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2066                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2067         }
2068
2069         if (pf->fdir.fdir_vsi) {
2070                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2071                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2072         }
2073         /* Clear all queues and release memory */
2074         i40e_dev_clear_queues(dev);
2075
2076         /* Set link down */
2077         i40e_dev_set_link_down(dev);
2078
2079         /* Remove all mirror rules */
2080         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2081                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2082                 rte_free(p_mirror);
2083         }
2084         pf->nb_mirror_rule = 0;
2085
2086         if (!rte_intr_allow_others(intr_handle))
2087                 /* resume to the default handler */
2088                 rte_intr_callback_register(intr_handle,
2089                                            i40e_dev_interrupt_handler,
2090                                            (void *)dev);
2091
2092         /* Clean datapath event and queue/vec mapping */
2093         rte_intr_efd_disable(intr_handle);
2094         if (intr_handle->intr_vec) {
2095                 rte_free(intr_handle->intr_vec);
2096                 intr_handle->intr_vec = NULL;
2097         }
2098 }
2099
2100 static void
2101 i40e_dev_close(struct rte_eth_dev *dev)
2102 {
2103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2106         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2107         uint32_t reg;
2108         int i;
2109
2110         PMD_INIT_FUNC_TRACE();
2111
2112         i40e_dev_stop(dev);
2113         hw->adapter_stopped = 1;
2114         i40e_dev_free_queues(dev);
2115
2116         /* Disable interrupt */
2117         i40e_pf_disable_irq0(hw);
2118         rte_intr_disable(intr_handle);
2119
2120         /* shutdown and destroy the HMC */
2121         i40e_shutdown_lan_hmc(hw);
2122
2123         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2124                 i40e_vsi_release(pf->vmdq[i].vsi);
2125                 pf->vmdq[i].vsi = NULL;
2126         }
2127         rte_free(pf->vmdq);
2128         pf->vmdq = NULL;
2129
2130         /* release all the existing VSIs and VEBs */
2131         i40e_fdir_teardown(pf);
2132         i40e_vsi_release(pf->main_vsi);
2133
2134         /* shutdown the adminq */
2135         i40e_aq_queue_shutdown(hw, true);
2136         i40e_shutdown_adminq(hw);
2137
2138         i40e_res_pool_destroy(&pf->qp_pool);
2139         i40e_res_pool_destroy(&pf->msix_pool);
2140
2141         /* force a PF reset to clean anything leftover */
2142         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2143         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2144                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2145         I40E_WRITE_FLUSH(hw);
2146 }
2147
2148 static void
2149 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2150 {
2151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153         struct i40e_vsi *vsi = pf->main_vsi;
2154         int status;
2155
2156         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2157                                                      true, NULL, true);
2158         if (status != I40E_SUCCESS)
2159                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2160
2161         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2162                                                         TRUE, NULL);
2163         if (status != I40E_SUCCESS)
2164                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2165
2166 }
2167
2168 static void
2169 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2170 {
2171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         struct i40e_vsi *vsi = pf->main_vsi;
2174         int status;
2175
2176         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2177                                                      false, NULL, true);
2178         if (status != I40E_SUCCESS)
2179                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2180
2181         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2182                                                         false, NULL);
2183         if (status != I40E_SUCCESS)
2184                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2185 }
2186
2187 static void
2188 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2189 {
2190         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2191         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         struct i40e_vsi *vsi = pf->main_vsi;
2193         int ret;
2194
2195         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2196         if (ret != I40E_SUCCESS)
2197                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2198 }
2199
2200 static void
2201 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2202 {
2203         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2204         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2205         struct i40e_vsi *vsi = pf->main_vsi;
2206         int ret;
2207
2208         if (dev->data->promiscuous == 1)
2209                 return; /* must remain in all_multicast mode */
2210
2211         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2212                                 vsi->seid, FALSE, NULL);
2213         if (ret != I40E_SUCCESS)
2214                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2215 }
2216
2217 /*
2218  * Set device link up.
2219  */
2220 static int
2221 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2222 {
2223         /* re-apply link speed setting */
2224         return i40e_apply_link_speed(dev);
2225 }
2226
2227 /*
2228  * Set device link down.
2229  */
2230 static int
2231 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2232 {
2233         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2234         uint8_t abilities = 0;
2235         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2236
2237         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2238         return i40e_phy_conf_link(hw, abilities, speed, false);
2239 }
2240
2241 int
2242 i40e_dev_link_update(struct rte_eth_dev *dev,
2243                      int wait_to_complete)
2244 {
2245 #define CHECK_INTERVAL 100  /* 100ms */
2246 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         struct i40e_link_status link_status;
2249         struct rte_eth_link link, old;
2250         int status;
2251         unsigned rep_cnt = MAX_REPEAT_TIME;
2252         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2253
2254         memset(&link, 0, sizeof(link));
2255         memset(&old, 0, sizeof(old));
2256         memset(&link_status, 0, sizeof(link_status));
2257         rte_i40e_dev_atomic_read_link_status(dev, &old);
2258
2259         do {
2260                 /* Get link status information from hardware */
2261                 status = i40e_aq_get_link_info(hw, enable_lse,
2262                                                 &link_status, NULL);
2263                 if (status != I40E_SUCCESS) {
2264                         link.link_speed = ETH_SPEED_NUM_100M;
2265                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2266                         PMD_DRV_LOG(ERR, "Failed to get link info");
2267                         goto out;
2268                 }
2269
2270                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2271                 if (!wait_to_complete || link.link_status)
2272                         break;
2273
2274                 rte_delay_ms(CHECK_INTERVAL);
2275         } while (--rep_cnt);
2276
2277         if (!link.link_status)
2278                 goto out;
2279
2280         /* i40e uses full duplex only */
2281         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2282
2283         /* Parse the link status */
2284         switch (link_status.link_speed) {
2285         case I40E_LINK_SPEED_100MB:
2286                 link.link_speed = ETH_SPEED_NUM_100M;
2287                 break;
2288         case I40E_LINK_SPEED_1GB:
2289                 link.link_speed = ETH_SPEED_NUM_1G;
2290                 break;
2291         case I40E_LINK_SPEED_10GB:
2292                 link.link_speed = ETH_SPEED_NUM_10G;
2293                 break;
2294         case I40E_LINK_SPEED_20GB:
2295                 link.link_speed = ETH_SPEED_NUM_20G;
2296                 break;
2297         case I40E_LINK_SPEED_25GB:
2298                 link.link_speed = ETH_SPEED_NUM_25G;
2299                 break;
2300         case I40E_LINK_SPEED_40GB:
2301                 link.link_speed = ETH_SPEED_NUM_40G;
2302                 break;
2303         default:
2304                 link.link_speed = ETH_SPEED_NUM_100M;
2305                 break;
2306         }
2307
2308         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2309                         ETH_LINK_SPEED_FIXED);
2310
2311 out:
2312         rte_i40e_dev_atomic_write_link_status(dev, &link);
2313         if (link.link_status == old.link_status)
2314                 return -1;
2315
2316         i40e_notify_all_vfs_link_status(dev);
2317
2318         return 0;
2319 }
2320
2321 /* Get all the statistics of a VSI */
2322 void
2323 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2324 {
2325         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2326         struct i40e_eth_stats *nes = &vsi->eth_stats;
2327         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2328         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2329
2330         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2331                             vsi->offset_loaded, &oes->rx_bytes,
2332                             &nes->rx_bytes);
2333         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2334                             vsi->offset_loaded, &oes->rx_unicast,
2335                             &nes->rx_unicast);
2336         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2337                             vsi->offset_loaded, &oes->rx_multicast,
2338                             &nes->rx_multicast);
2339         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2340                             vsi->offset_loaded, &oes->rx_broadcast,
2341                             &nes->rx_broadcast);
2342         /* exclude CRC bytes */
2343         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2344                 nes->rx_broadcast) * ETHER_CRC_LEN;
2345
2346         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2347                             &oes->rx_discards, &nes->rx_discards);
2348         /* GLV_REPC not supported */
2349         /* GLV_RMPC not supported */
2350         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2351                             &oes->rx_unknown_protocol,
2352                             &nes->rx_unknown_protocol);
2353         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2354                             vsi->offset_loaded, &oes->tx_bytes,
2355                             &nes->tx_bytes);
2356         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2357                             vsi->offset_loaded, &oes->tx_unicast,
2358                             &nes->tx_unicast);
2359         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2360                             vsi->offset_loaded, &oes->tx_multicast,
2361                             &nes->tx_multicast);
2362         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2363                             vsi->offset_loaded,  &oes->tx_broadcast,
2364                             &nes->tx_broadcast);
2365         /* GLV_TDPC not supported */
2366         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2367                             &oes->tx_errors, &nes->tx_errors);
2368         vsi->offset_loaded = true;
2369
2370         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2371                     vsi->vsi_id);
2372         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2373         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2374         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2375         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2376         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2377         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2378                     nes->rx_unknown_protocol);
2379         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2380         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2381         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2382         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2383         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2384         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2385         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2386                     vsi->vsi_id);
2387 }
2388
2389 static void
2390 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2391 {
2392         unsigned int i;
2393         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2394         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2395
2396         /* Get rx/tx bytes of internal transfer packets */
2397         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2398                         I40E_GLV_GORCL(hw->port),
2399                         pf->offset_loaded,
2400                         &pf->internal_stats_offset.rx_bytes,
2401                         &pf->internal_stats.rx_bytes);
2402
2403         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2404                         I40E_GLV_GOTCL(hw->port),
2405                         pf->offset_loaded,
2406                         &pf->internal_stats_offset.tx_bytes,
2407                         &pf->internal_stats.tx_bytes);
2408         /* Get total internal rx packet count */
2409         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2410                             I40E_GLV_UPRCL(hw->port),
2411                             pf->offset_loaded,
2412                             &pf->internal_stats_offset.rx_unicast,
2413                             &pf->internal_stats.rx_unicast);
2414         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2415                             I40E_GLV_MPRCL(hw->port),
2416                             pf->offset_loaded,
2417                             &pf->internal_stats_offset.rx_multicast,
2418                             &pf->internal_stats.rx_multicast);
2419         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2420                             I40E_GLV_BPRCL(hw->port),
2421                             pf->offset_loaded,
2422                             &pf->internal_stats_offset.rx_broadcast,
2423                             &pf->internal_stats.rx_broadcast);
2424
2425         /* exclude CRC size */
2426         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2427                 pf->internal_stats.rx_multicast +
2428                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2429
2430         /* Get statistics of struct i40e_eth_stats */
2431         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2432                             I40E_GLPRT_GORCL(hw->port),
2433                             pf->offset_loaded, &os->eth.rx_bytes,
2434                             &ns->eth.rx_bytes);
2435         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2436                             I40E_GLPRT_UPRCL(hw->port),
2437                             pf->offset_loaded, &os->eth.rx_unicast,
2438                             &ns->eth.rx_unicast);
2439         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2440                             I40E_GLPRT_MPRCL(hw->port),
2441                             pf->offset_loaded, &os->eth.rx_multicast,
2442                             &ns->eth.rx_multicast);
2443         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2444                             I40E_GLPRT_BPRCL(hw->port),
2445                             pf->offset_loaded, &os->eth.rx_broadcast,
2446                             &ns->eth.rx_broadcast);
2447         /* Workaround: CRC size should not be included in byte statistics,
2448          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2449          */
2450         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2451                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2452
2453         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2454          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2455          * value.
2456          */
2457         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2458                 ns->eth.rx_bytes = 0;
2459         /* exlude internal rx bytes */
2460         else
2461                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2462
2463         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2464                             pf->offset_loaded, &os->eth.rx_discards,
2465                             &ns->eth.rx_discards);
2466         /* GLPRT_REPC not supported */
2467         /* GLPRT_RMPC not supported */
2468         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2469                             pf->offset_loaded,
2470                             &os->eth.rx_unknown_protocol,
2471                             &ns->eth.rx_unknown_protocol);
2472         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2473                             I40E_GLPRT_GOTCL(hw->port),
2474                             pf->offset_loaded, &os->eth.tx_bytes,
2475                             &ns->eth.tx_bytes);
2476         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2477                             I40E_GLPRT_UPTCL(hw->port),
2478                             pf->offset_loaded, &os->eth.tx_unicast,
2479                             &ns->eth.tx_unicast);
2480         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2481                             I40E_GLPRT_MPTCL(hw->port),
2482                             pf->offset_loaded, &os->eth.tx_multicast,
2483                             &ns->eth.tx_multicast);
2484         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2485                             I40E_GLPRT_BPTCL(hw->port),
2486                             pf->offset_loaded, &os->eth.tx_broadcast,
2487                             &ns->eth.tx_broadcast);
2488         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2489                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2490
2491         /* exclude internal tx bytes */
2492         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2493                 ns->eth.tx_bytes = 0;
2494         else
2495                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2496
2497         /* GLPRT_TEPC not supported */
2498
2499         /* additional port specific stats */
2500         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2501                             pf->offset_loaded, &os->tx_dropped_link_down,
2502                             &ns->tx_dropped_link_down);
2503         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2504                             pf->offset_loaded, &os->crc_errors,
2505                             &ns->crc_errors);
2506         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2507                             pf->offset_loaded, &os->illegal_bytes,
2508                             &ns->illegal_bytes);
2509         /* GLPRT_ERRBC not supported */
2510         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2511                             pf->offset_loaded, &os->mac_local_faults,
2512                             &ns->mac_local_faults);
2513         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2514                             pf->offset_loaded, &os->mac_remote_faults,
2515                             &ns->mac_remote_faults);
2516         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2517                             pf->offset_loaded, &os->rx_length_errors,
2518                             &ns->rx_length_errors);
2519         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2520                             pf->offset_loaded, &os->link_xon_rx,
2521                             &ns->link_xon_rx);
2522         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2523                             pf->offset_loaded, &os->link_xoff_rx,
2524                             &ns->link_xoff_rx);
2525         for (i = 0; i < 8; i++) {
2526                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2527                                     pf->offset_loaded,
2528                                     &os->priority_xon_rx[i],
2529                                     &ns->priority_xon_rx[i]);
2530                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2531                                     pf->offset_loaded,
2532                                     &os->priority_xoff_rx[i],
2533                                     &ns->priority_xoff_rx[i]);
2534         }
2535         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2536                             pf->offset_loaded, &os->link_xon_tx,
2537                             &ns->link_xon_tx);
2538         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2539                             pf->offset_loaded, &os->link_xoff_tx,
2540                             &ns->link_xoff_tx);
2541         for (i = 0; i < 8; i++) {
2542                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2543                                     pf->offset_loaded,
2544                                     &os->priority_xon_tx[i],
2545                                     &ns->priority_xon_tx[i]);
2546                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2547                                     pf->offset_loaded,
2548                                     &os->priority_xoff_tx[i],
2549                                     &ns->priority_xoff_tx[i]);
2550                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2551                                     pf->offset_loaded,
2552                                     &os->priority_xon_2_xoff[i],
2553                                     &ns->priority_xon_2_xoff[i]);
2554         }
2555         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2556                             I40E_GLPRT_PRC64L(hw->port),
2557                             pf->offset_loaded, &os->rx_size_64,
2558                             &ns->rx_size_64);
2559         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2560                             I40E_GLPRT_PRC127L(hw->port),
2561                             pf->offset_loaded, &os->rx_size_127,
2562                             &ns->rx_size_127);
2563         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2564                             I40E_GLPRT_PRC255L(hw->port),
2565                             pf->offset_loaded, &os->rx_size_255,
2566                             &ns->rx_size_255);
2567         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2568                             I40E_GLPRT_PRC511L(hw->port),
2569                             pf->offset_loaded, &os->rx_size_511,
2570                             &ns->rx_size_511);
2571         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2572                             I40E_GLPRT_PRC1023L(hw->port),
2573                             pf->offset_loaded, &os->rx_size_1023,
2574                             &ns->rx_size_1023);
2575         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2576                             I40E_GLPRT_PRC1522L(hw->port),
2577                             pf->offset_loaded, &os->rx_size_1522,
2578                             &ns->rx_size_1522);
2579         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2580                             I40E_GLPRT_PRC9522L(hw->port),
2581                             pf->offset_loaded, &os->rx_size_big,
2582                             &ns->rx_size_big);
2583         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2584                             pf->offset_loaded, &os->rx_undersize,
2585                             &ns->rx_undersize);
2586         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2587                             pf->offset_loaded, &os->rx_fragments,
2588                             &ns->rx_fragments);
2589         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2590                             pf->offset_loaded, &os->rx_oversize,
2591                             &ns->rx_oversize);
2592         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2593                             pf->offset_loaded, &os->rx_jabber,
2594                             &ns->rx_jabber);
2595         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2596                             I40E_GLPRT_PTC64L(hw->port),
2597                             pf->offset_loaded, &os->tx_size_64,
2598                             &ns->tx_size_64);
2599         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2600                             I40E_GLPRT_PTC127L(hw->port),
2601                             pf->offset_loaded, &os->tx_size_127,
2602                             &ns->tx_size_127);
2603         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2604                             I40E_GLPRT_PTC255L(hw->port),
2605                             pf->offset_loaded, &os->tx_size_255,
2606                             &ns->tx_size_255);
2607         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2608                             I40E_GLPRT_PTC511L(hw->port),
2609                             pf->offset_loaded, &os->tx_size_511,
2610                             &ns->tx_size_511);
2611         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2612                             I40E_GLPRT_PTC1023L(hw->port),
2613                             pf->offset_loaded, &os->tx_size_1023,
2614                             &ns->tx_size_1023);
2615         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2616                             I40E_GLPRT_PTC1522L(hw->port),
2617                             pf->offset_loaded, &os->tx_size_1522,
2618                             &ns->tx_size_1522);
2619         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2620                             I40E_GLPRT_PTC9522L(hw->port),
2621                             pf->offset_loaded, &os->tx_size_big,
2622                             &ns->tx_size_big);
2623         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2624                            pf->offset_loaded,
2625                            &os->fd_sb_match, &ns->fd_sb_match);
2626         /* GLPRT_MSPDC not supported */
2627         /* GLPRT_XEC not supported */
2628
2629         pf->offset_loaded = true;
2630
2631         if (pf->main_vsi)
2632                 i40e_update_vsi_stats(pf->main_vsi);
2633 }
2634
2635 /* Get all statistics of a port */
2636 static void
2637 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2638 {
2639         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2642         unsigned i;
2643
2644         /* call read registers - updates values, now write them to struct */
2645         i40e_read_stats_registers(pf, hw);
2646
2647         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2648                         pf->main_vsi->eth_stats.rx_multicast +
2649                         pf->main_vsi->eth_stats.rx_broadcast -
2650                         pf->main_vsi->eth_stats.rx_discards;
2651         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2652                         pf->main_vsi->eth_stats.tx_multicast +
2653                         pf->main_vsi->eth_stats.tx_broadcast;
2654         stats->ibytes   = ns->eth.rx_bytes;
2655         stats->obytes   = ns->eth.tx_bytes;
2656         stats->oerrors  = ns->eth.tx_errors +
2657                         pf->main_vsi->eth_stats.tx_errors;
2658
2659         /* Rx Errors */
2660         stats->imissed  = ns->eth.rx_discards +
2661                         pf->main_vsi->eth_stats.rx_discards;
2662         stats->ierrors  = ns->crc_errors +
2663                         ns->rx_length_errors + ns->rx_undersize +
2664                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2665
2666         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2667         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2668         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2669         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2670         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2671         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2672         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2673                     ns->eth.rx_unknown_protocol);
2674         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2675         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2676         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2677         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2678         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2679         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2680
2681         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2682                     ns->tx_dropped_link_down);
2683         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2684         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2685                     ns->illegal_bytes);
2686         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2687         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2688                     ns->mac_local_faults);
2689         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2690                     ns->mac_remote_faults);
2691         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2692                     ns->rx_length_errors);
2693         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2694         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2695         for (i = 0; i < 8; i++) {
2696                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2697                                 i, ns->priority_xon_rx[i]);
2698                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2699                                 i, ns->priority_xoff_rx[i]);
2700         }
2701         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2702         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2703         for (i = 0; i < 8; i++) {
2704                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2705                                 i, ns->priority_xon_tx[i]);
2706                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2707                                 i, ns->priority_xoff_tx[i]);
2708                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2709                                 i, ns->priority_xon_2_xoff[i]);
2710         }
2711         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2712         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2713         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2714         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2715         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2716         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2717         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2718         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2719         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2720         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2721         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2722         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2723         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2724         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2725         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2726         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2727         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2728         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2729         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2730                         ns->mac_short_packet_dropped);
2731         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2732                     ns->checksum_error);
2733         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2734         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2735 }
2736
2737 /* Reset the statistics */
2738 static void
2739 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2740 {
2741         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2742         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743
2744         /* Mark PF and VSI stats to update the offset, aka "reset" */
2745         pf->offset_loaded = false;
2746         if (pf->main_vsi)
2747                 pf->main_vsi->offset_loaded = false;
2748
2749         /* read the stats, reading current register values into offset */
2750         i40e_read_stats_registers(pf, hw);
2751 }
2752
2753 static uint32_t
2754 i40e_xstats_calc_num(void)
2755 {
2756         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2757                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2758                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2759 }
2760
2761 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2762                                      struct rte_eth_xstat_name *xstats_names,
2763                                      __rte_unused unsigned limit)
2764 {
2765         unsigned count = 0;
2766         unsigned i, prio;
2767
2768         if (xstats_names == NULL)
2769                 return i40e_xstats_calc_num();
2770
2771         /* Note: limit checked in rte_eth_xstats_names() */
2772
2773         /* Get stats from i40e_eth_stats struct */
2774         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2775                 snprintf(xstats_names[count].name,
2776                          sizeof(xstats_names[count].name),
2777                          "%s", rte_i40e_stats_strings[i].name);
2778                 count++;
2779         }
2780
2781         /* Get individiual stats from i40e_hw_port struct */
2782         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2783                 snprintf(xstats_names[count].name,
2784                         sizeof(xstats_names[count].name),
2785                          "%s", rte_i40e_hw_port_strings[i].name);
2786                 count++;
2787         }
2788
2789         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2790                 for (prio = 0; prio < 8; prio++) {
2791                         snprintf(xstats_names[count].name,
2792                                  sizeof(xstats_names[count].name),
2793                                  "rx_priority%u_%s", prio,
2794                                  rte_i40e_rxq_prio_strings[i].name);
2795                         count++;
2796                 }
2797         }
2798
2799         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2800                 for (prio = 0; prio < 8; prio++) {
2801                         snprintf(xstats_names[count].name,
2802                                  sizeof(xstats_names[count].name),
2803                                  "tx_priority%u_%s", prio,
2804                                  rte_i40e_txq_prio_strings[i].name);
2805                         count++;
2806                 }
2807         }
2808         return count;
2809 }
2810
2811 static int
2812 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2813                     unsigned n)
2814 {
2815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2817         unsigned i, count, prio;
2818         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2819
2820         count = i40e_xstats_calc_num();
2821         if (n < count)
2822                 return count;
2823
2824         i40e_read_stats_registers(pf, hw);
2825
2826         if (xstats == NULL)
2827                 return 0;
2828
2829         count = 0;
2830
2831         /* Get stats from i40e_eth_stats struct */
2832         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2833                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2834                         rte_i40e_stats_strings[i].offset);
2835                 xstats[count].id = count;
2836                 count++;
2837         }
2838
2839         /* Get individiual stats from i40e_hw_port struct */
2840         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2841                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2842                         rte_i40e_hw_port_strings[i].offset);
2843                 xstats[count].id = count;
2844                 count++;
2845         }
2846
2847         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2848                 for (prio = 0; prio < 8; prio++) {
2849                         xstats[count].value =
2850                                 *(uint64_t *)(((char *)hw_stats) +
2851                                 rte_i40e_rxq_prio_strings[i].offset +
2852                                 (sizeof(uint64_t) * prio));
2853                         xstats[count].id = count;
2854                         count++;
2855                 }
2856         }
2857
2858         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2859                 for (prio = 0; prio < 8; prio++) {
2860                         xstats[count].value =
2861                                 *(uint64_t *)(((char *)hw_stats) +
2862                                 rte_i40e_txq_prio_strings[i].offset +
2863                                 (sizeof(uint64_t) * prio));
2864                         xstats[count].id = count;
2865                         count++;
2866                 }
2867         }
2868
2869         return count;
2870 }
2871
2872 static int
2873 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2874                                  __rte_unused uint16_t queue_id,
2875                                  __rte_unused uint8_t stat_idx,
2876                                  __rte_unused uint8_t is_rx)
2877 {
2878         PMD_INIT_FUNC_TRACE();
2879
2880         return -ENOSYS;
2881 }
2882
2883 static int
2884 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2885 {
2886         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2887         u32 full_ver;
2888         u8 ver, patch;
2889         u16 build;
2890         int ret;
2891
2892         full_ver = hw->nvm.oem_ver;
2893         ver = (u8)(full_ver >> 24);
2894         build = (u16)((full_ver >> 8) & 0xffff);
2895         patch = (u8)(full_ver & 0xff);
2896
2897         ret = snprintf(fw_version, fw_size,
2898                  "%d.%d%d 0x%08x %d.%d.%d",
2899                  ((hw->nvm.version >> 12) & 0xf),
2900                  ((hw->nvm.version >> 4) & 0xff),
2901                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2902                  ver, build, patch);
2903
2904         ret += 1; /* add the size of '\0' */
2905         if (fw_size < (u32)ret)
2906                 return ret;
2907         else
2908                 return 0;
2909 }
2910
2911 static void
2912 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2913 {
2914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916         struct i40e_vsi *vsi = pf->main_vsi;
2917         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2918
2919         dev_info->pci_dev = pci_dev;
2920         dev_info->max_rx_queues = vsi->nb_qps;
2921         dev_info->max_tx_queues = vsi->nb_qps;
2922         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2923         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2924         dev_info->max_mac_addrs = vsi->max_macaddrs;
2925         dev_info->max_vfs = pci_dev->max_vfs;
2926         dev_info->rx_offload_capa =
2927                 DEV_RX_OFFLOAD_VLAN_STRIP |
2928                 DEV_RX_OFFLOAD_QINQ_STRIP |
2929                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2930                 DEV_RX_OFFLOAD_UDP_CKSUM |
2931                 DEV_RX_OFFLOAD_TCP_CKSUM;
2932         dev_info->tx_offload_capa =
2933                 DEV_TX_OFFLOAD_VLAN_INSERT |
2934                 DEV_TX_OFFLOAD_QINQ_INSERT |
2935                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2936                 DEV_TX_OFFLOAD_UDP_CKSUM |
2937                 DEV_TX_OFFLOAD_TCP_CKSUM |
2938                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2939                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2940                 DEV_TX_OFFLOAD_TCP_TSO |
2941                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2942                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2943                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2944                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2945         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2946                                                 sizeof(uint32_t);
2947         dev_info->reta_size = pf->hash_lut_size;
2948         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2949
2950         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2951                 .rx_thresh = {
2952                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2953                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2954                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2955                 },
2956                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2957                 .rx_drop_en = 0,
2958         };
2959
2960         dev_info->default_txconf = (struct rte_eth_txconf) {
2961                 .tx_thresh = {
2962                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2963                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2964                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2965                 },
2966                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2967                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2968                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2969                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2970         };
2971
2972         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2973                 .nb_max = I40E_MAX_RING_DESC,
2974                 .nb_min = I40E_MIN_RING_DESC,
2975                 .nb_align = I40E_ALIGN_RING_DESC,
2976         };
2977
2978         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2979                 .nb_max = I40E_MAX_RING_DESC,
2980                 .nb_min = I40E_MIN_RING_DESC,
2981                 .nb_align = I40E_ALIGN_RING_DESC,
2982                 .nb_seg_max = I40E_TX_MAX_SEG,
2983                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2984         };
2985
2986         if (pf->flags & I40E_FLAG_VMDQ) {
2987                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2988                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2989                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2990                                                 pf->max_nb_vmdq_vsi;
2991                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2992                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2993                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2994         }
2995
2996         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2997                 /* For XL710 */
2998                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2999         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3000                 /* For XXV710 */
3001                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3002         else
3003                 /* For X710 */
3004                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3005 }
3006
3007 static int
3008 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3009 {
3010         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3011         struct i40e_vsi *vsi = pf->main_vsi;
3012         PMD_INIT_FUNC_TRACE();
3013
3014         if (on)
3015                 return i40e_vsi_add_vlan(vsi, vlan_id);
3016         else
3017                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3018 }
3019
3020 static int
3021 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3022                    enum rte_vlan_type vlan_type,
3023                    uint16_t tpid)
3024 {
3025         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3026         uint64_t reg_r = 0, reg_w = 0;
3027         uint16_t reg_id = 0;
3028         int ret = 0;
3029         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3030
3031         switch (vlan_type) {
3032         case ETH_VLAN_TYPE_OUTER:
3033                 if (qinq)
3034                         reg_id = 2;
3035                 else
3036                         reg_id = 3;
3037                 break;
3038         case ETH_VLAN_TYPE_INNER:
3039                 if (qinq)
3040                         reg_id = 3;
3041                 else {
3042                         ret = -EINVAL;
3043                         PMD_DRV_LOG(ERR,
3044                                 "Unsupported vlan type in single vlan.");
3045                         return ret;
3046                 }
3047                 break;
3048         default:
3049                 ret = -EINVAL;
3050                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3051                 return ret;
3052         }
3053         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3054                                           &reg_r, NULL);
3055         if (ret != I40E_SUCCESS) {
3056                 PMD_DRV_LOG(ERR,
3057                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3058                            reg_id);
3059                 ret = -EIO;
3060                 return ret;
3061         }
3062         PMD_DRV_LOG(DEBUG,
3063                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3064                 reg_id, reg_r);
3065
3066         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3067         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3068         if (reg_r == reg_w) {
3069                 ret = 0;
3070                 PMD_DRV_LOG(DEBUG, "No need to write");
3071                 return ret;
3072         }
3073
3074         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3075                                            reg_w, NULL);
3076         if (ret != I40E_SUCCESS) {
3077                 ret = -EIO;
3078                 PMD_DRV_LOG(ERR,
3079                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3080                         reg_id);
3081                 return ret;
3082         }
3083         PMD_DRV_LOG(DEBUG,
3084                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3085                 reg_w, reg_id);
3086
3087         return ret;
3088 }
3089
3090 static void
3091 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3092 {
3093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3094         struct i40e_vsi *vsi = pf->main_vsi;
3095
3096         if (mask & ETH_VLAN_FILTER_MASK) {
3097                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3098                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3099                 else
3100                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3101         }
3102
3103         if (mask & ETH_VLAN_STRIP_MASK) {
3104                 /* Enable or disable VLAN stripping */
3105                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3106                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3107                 else
3108                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3109         }
3110
3111         if (mask & ETH_VLAN_EXTEND_MASK) {
3112                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3113                         i40e_vsi_config_double_vlan(vsi, TRUE);
3114                         /* Set global registers with default ether type value */
3115                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3116                                            ETHER_TYPE_VLAN);
3117                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3118                                            ETHER_TYPE_VLAN);
3119                 }
3120                 else
3121                         i40e_vsi_config_double_vlan(vsi, FALSE);
3122         }
3123 }
3124
3125 static void
3126 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3127                           __rte_unused uint16_t queue,
3128                           __rte_unused int on)
3129 {
3130         PMD_INIT_FUNC_TRACE();
3131 }
3132
3133 static int
3134 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3135 {
3136         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3137         struct i40e_vsi *vsi = pf->main_vsi;
3138         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3139         struct i40e_vsi_vlan_pvid_info info;
3140
3141         memset(&info, 0, sizeof(info));
3142         info.on = on;
3143         if (info.on)
3144                 info.config.pvid = pvid;
3145         else {
3146                 info.config.reject.tagged =
3147                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3148                 info.config.reject.untagged =
3149                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3150         }
3151
3152         return i40e_vsi_vlan_pvid_set(vsi, &info);
3153 }
3154
3155 static int
3156 i40e_dev_led_on(struct rte_eth_dev *dev)
3157 {
3158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159         uint32_t mode = i40e_led_get(hw);
3160
3161         if (mode == 0)
3162                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3163
3164         return 0;
3165 }
3166
3167 static int
3168 i40e_dev_led_off(struct rte_eth_dev *dev)
3169 {
3170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171         uint32_t mode = i40e_led_get(hw);
3172
3173         if (mode != 0)
3174                 i40e_led_set(hw, 0, false);
3175
3176         return 0;
3177 }
3178
3179 static int
3180 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3181 {
3182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3184
3185         fc_conf->pause_time = pf->fc_conf.pause_time;
3186         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3187         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3188
3189          /* Return current mode according to actual setting*/
3190         switch (hw->fc.current_mode) {
3191         case I40E_FC_FULL:
3192                 fc_conf->mode = RTE_FC_FULL;
3193                 break;
3194         case I40E_FC_TX_PAUSE:
3195                 fc_conf->mode = RTE_FC_TX_PAUSE;
3196                 break;
3197         case I40E_FC_RX_PAUSE:
3198                 fc_conf->mode = RTE_FC_RX_PAUSE;
3199                 break;
3200         case I40E_FC_NONE:
3201         default:
3202                 fc_conf->mode = RTE_FC_NONE;
3203         };
3204
3205         return 0;
3206 }
3207
3208 static int
3209 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3210 {
3211         uint32_t mflcn_reg, fctrl_reg, reg;
3212         uint32_t max_high_water;
3213         uint8_t i, aq_failure;
3214         int err;
3215         struct i40e_hw *hw;
3216         struct i40e_pf *pf;
3217         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3218                 [RTE_FC_NONE] = I40E_FC_NONE,
3219                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3220                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3221                 [RTE_FC_FULL] = I40E_FC_FULL
3222         };
3223
3224         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3225
3226         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3227         if ((fc_conf->high_water > max_high_water) ||
3228                         (fc_conf->high_water < fc_conf->low_water)) {
3229                 PMD_INIT_LOG(ERR,
3230                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3231                         max_high_water);
3232                 return -EINVAL;
3233         }
3234
3235         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3236         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3237         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3238
3239         pf->fc_conf.pause_time = fc_conf->pause_time;
3240         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3241         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3242
3243         PMD_INIT_FUNC_TRACE();
3244
3245         /* All the link flow control related enable/disable register
3246          * configuration is handle by the F/W
3247          */
3248         err = i40e_set_fc(hw, &aq_failure, true);
3249         if (err < 0)
3250                 return -ENOSYS;
3251
3252         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3253                 /* Configure flow control refresh threshold,
3254                  * the value for stat_tx_pause_refresh_timer[8]
3255                  * is used for global pause operation.
3256                  */
3257
3258                 I40E_WRITE_REG(hw,
3259                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3260                                pf->fc_conf.pause_time);
3261
3262                 /* configure the timer value included in transmitted pause
3263                  * frame,
3264                  * the value for stat_tx_pause_quanta[8] is used for global
3265                  * pause operation
3266                  */
3267                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3268                                pf->fc_conf.pause_time);
3269
3270                 fctrl_reg = I40E_READ_REG(hw,
3271                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3272
3273                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3274                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3275                 else
3276                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3277
3278                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3279                                fctrl_reg);
3280         } else {
3281                 /* Configure pause time (2 TCs per register) */
3282                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3283                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3284                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3285
3286                 /* Configure flow control refresh threshold value */
3287                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3288                                pf->fc_conf.pause_time / 2);
3289
3290                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3291
3292                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3293                  *depending on configuration
3294                  */
3295                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3296                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3297                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3298                 } else {
3299                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3300                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3301                 }
3302
3303                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3304         }
3305
3306         /* config the water marker both based on the packets and bytes */
3307         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3308                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3309                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3310         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3311                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3312                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3313         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3314                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3315                        << I40E_KILOSHIFT);
3316         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3317                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3318                        << I40E_KILOSHIFT);
3319
3320         I40E_WRITE_FLUSH(hw);
3321
3322         return 0;
3323 }
3324
3325 static int
3326 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3327                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3328 {
3329         PMD_INIT_FUNC_TRACE();
3330
3331         return -ENOSYS;
3332 }
3333
3334 /* Add a MAC address, and update filters */
3335 static int
3336 i40e_macaddr_add(struct rte_eth_dev *dev,
3337                  struct ether_addr *mac_addr,
3338                  __rte_unused uint32_t index,
3339                  uint32_t pool)
3340 {
3341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3342         struct i40e_mac_filter_info mac_filter;
3343         struct i40e_vsi *vsi;
3344         int ret;
3345
3346         /* If VMDQ not enabled or configured, return */
3347         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3348                           !pf->nb_cfg_vmdq_vsi)) {
3349                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3350                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3351                         pool);
3352                 return -ENOTSUP;
3353         }
3354
3355         if (pool > pf->nb_cfg_vmdq_vsi) {
3356                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3357                                 pool, pf->nb_cfg_vmdq_vsi);
3358                 return -EINVAL;
3359         }
3360
3361         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3362         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3363                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3364         else
3365                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3366
3367         if (pool == 0)
3368                 vsi = pf->main_vsi;
3369         else
3370                 vsi = pf->vmdq[pool - 1].vsi;
3371
3372         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3373         if (ret != I40E_SUCCESS) {
3374                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3375                 return -ENODEV;
3376         }
3377         return 0;
3378 }
3379
3380 /* Remove a MAC address, and update filters */
3381 static void
3382 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3383 {
3384         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3385         struct i40e_vsi *vsi;
3386         struct rte_eth_dev_data *data = dev->data;
3387         struct ether_addr *macaddr;
3388         int ret;
3389         uint32_t i;
3390         uint64_t pool_sel;
3391
3392         macaddr = &(data->mac_addrs[index]);
3393
3394         pool_sel = dev->data->mac_pool_sel[index];
3395
3396         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3397                 if (pool_sel & (1ULL << i)) {
3398                         if (i == 0)
3399                                 vsi = pf->main_vsi;
3400                         else {
3401                                 /* No VMDQ pool enabled or configured */
3402                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3403                                         (i > pf->nb_cfg_vmdq_vsi)) {
3404                                         PMD_DRV_LOG(ERR,
3405                                                 "No VMDQ pool enabled/configured");
3406                                         return;
3407                                 }
3408                                 vsi = pf->vmdq[i - 1].vsi;
3409                         }
3410                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3411
3412                         if (ret) {
3413                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3414                                 return;
3415                         }
3416                 }
3417         }
3418 }
3419
3420 /* Set perfect match or hash match of MAC and VLAN for a VF */
3421 static int
3422 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3423                  struct rte_eth_mac_filter *filter,
3424                  bool add)
3425 {
3426         struct i40e_hw *hw;
3427         struct i40e_mac_filter_info mac_filter;
3428         struct ether_addr old_mac;
3429         struct ether_addr *new_mac;
3430         struct i40e_pf_vf *vf = NULL;
3431         uint16_t vf_id;
3432         int ret;
3433
3434         if (pf == NULL) {
3435                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3436                 return -EINVAL;
3437         }
3438         hw = I40E_PF_TO_HW(pf);
3439
3440         if (filter == NULL) {
3441                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3442                 return -EINVAL;
3443         }
3444
3445         new_mac = &filter->mac_addr;
3446
3447         if (is_zero_ether_addr(new_mac)) {
3448                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3449                 return -EINVAL;
3450         }
3451
3452         vf_id = filter->dst_id;
3453
3454         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3455                 PMD_DRV_LOG(ERR, "Invalid argument.");
3456                 return -EINVAL;
3457         }
3458         vf = &pf->vfs[vf_id];
3459
3460         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3461                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3462                 return -EINVAL;
3463         }
3464
3465         if (add) {
3466                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3467                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3468                                 ETHER_ADDR_LEN);
3469                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3470                                  ETHER_ADDR_LEN);
3471
3472                 mac_filter.filter_type = filter->filter_type;
3473                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3474                 if (ret != I40E_SUCCESS) {
3475                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3476                         return -1;
3477                 }
3478                 ether_addr_copy(new_mac, &pf->dev_addr);
3479         } else {
3480                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3481                                 ETHER_ADDR_LEN);
3482                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3483                 if (ret != I40E_SUCCESS) {
3484                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3485                         return -1;
3486                 }
3487
3488                 /* Clear device address as it has been removed */
3489                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3490                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3491         }
3492
3493         return 0;
3494 }
3495
3496 /* MAC filter handle */
3497 static int
3498 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3499                 void *arg)
3500 {
3501         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3502         struct rte_eth_mac_filter *filter;
3503         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3504         int ret = I40E_NOT_SUPPORTED;
3505
3506         filter = (struct rte_eth_mac_filter *)(arg);
3507
3508         switch (filter_op) {
3509         case RTE_ETH_FILTER_NOP:
3510                 ret = I40E_SUCCESS;
3511                 break;
3512         case RTE_ETH_FILTER_ADD:
3513                 i40e_pf_disable_irq0(hw);
3514                 if (filter->is_vf)
3515                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3516                 i40e_pf_enable_irq0(hw);
3517                 break;
3518         case RTE_ETH_FILTER_DELETE:
3519                 i40e_pf_disable_irq0(hw);
3520                 if (filter->is_vf)
3521                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3522                 i40e_pf_enable_irq0(hw);
3523                 break;
3524         default:
3525                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3526                 ret = I40E_ERR_PARAM;
3527                 break;
3528         }
3529
3530         return ret;
3531 }
3532
3533 static int
3534 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3535 {
3536         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3537         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3538         int ret;
3539
3540         if (!lut)
3541                 return -EINVAL;
3542
3543         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3544                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3545                                           lut, lut_size);
3546                 if (ret) {
3547                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3548                         return ret;
3549                 }
3550         } else {
3551                 uint32_t *lut_dw = (uint32_t *)lut;
3552                 uint16_t i, lut_size_dw = lut_size / 4;
3553
3554                 for (i = 0; i < lut_size_dw; i++)
3555                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3556         }
3557
3558         return 0;
3559 }
3560
3561 static int
3562 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3563 {
3564         struct i40e_pf *pf;
3565         struct i40e_hw *hw;
3566         int ret;
3567
3568         if (!vsi || !lut)
3569                 return -EINVAL;
3570
3571         pf = I40E_VSI_TO_PF(vsi);
3572         hw = I40E_VSI_TO_HW(vsi);
3573
3574         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3575                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3576                                           lut, lut_size);
3577                 if (ret) {
3578                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3579                         return ret;
3580                 }
3581         } else {
3582                 uint32_t *lut_dw = (uint32_t *)lut;
3583                 uint16_t i, lut_size_dw = lut_size / 4;
3584
3585                 for (i = 0; i < lut_size_dw; i++)
3586                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3587                 I40E_WRITE_FLUSH(hw);
3588         }
3589
3590         return 0;
3591 }
3592
3593 static int
3594 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3595                          struct rte_eth_rss_reta_entry64 *reta_conf,
3596                          uint16_t reta_size)
3597 {
3598         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3599         uint16_t i, lut_size = pf->hash_lut_size;
3600         uint16_t idx, shift;
3601         uint8_t *lut;
3602         int ret;
3603
3604         if (reta_size != lut_size ||
3605                 reta_size > ETH_RSS_RETA_SIZE_512) {
3606                 PMD_DRV_LOG(ERR,
3607                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3608                         reta_size, lut_size);
3609                 return -EINVAL;
3610         }
3611
3612         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3613         if (!lut) {
3614                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3615                 return -ENOMEM;
3616         }
3617         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3618         if (ret)
3619                 goto out;
3620         for (i = 0; i < reta_size; i++) {
3621                 idx = i / RTE_RETA_GROUP_SIZE;
3622                 shift = i % RTE_RETA_GROUP_SIZE;
3623                 if (reta_conf[idx].mask & (1ULL << shift))
3624                         lut[i] = reta_conf[idx].reta[shift];
3625         }
3626         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3627
3628 out:
3629         rte_free(lut);
3630
3631         return ret;
3632 }
3633
3634 static int
3635 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3636                         struct rte_eth_rss_reta_entry64 *reta_conf,
3637                         uint16_t reta_size)
3638 {
3639         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3640         uint16_t i, lut_size = pf->hash_lut_size;
3641         uint16_t idx, shift;
3642         uint8_t *lut;
3643         int ret;
3644
3645         if (reta_size != lut_size ||
3646                 reta_size > ETH_RSS_RETA_SIZE_512) {
3647                 PMD_DRV_LOG(ERR,
3648                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3649                         reta_size, lut_size);
3650                 return -EINVAL;
3651         }
3652
3653         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3654         if (!lut) {
3655                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3656                 return -ENOMEM;
3657         }
3658
3659         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3660         if (ret)
3661                 goto out;
3662         for (i = 0; i < reta_size; i++) {
3663                 idx = i / RTE_RETA_GROUP_SIZE;
3664                 shift = i % RTE_RETA_GROUP_SIZE;
3665                 if (reta_conf[idx].mask & (1ULL << shift))
3666                         reta_conf[idx].reta[shift] = lut[i];
3667         }
3668
3669 out:
3670         rte_free(lut);
3671
3672         return ret;
3673 }
3674
3675 /**
3676  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3677  * @hw:   pointer to the HW structure
3678  * @mem:  pointer to mem struct to fill out
3679  * @size: size of memory requested
3680  * @alignment: what to align the allocation to
3681  **/
3682 enum i40e_status_code
3683 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3684                         struct i40e_dma_mem *mem,
3685                         u64 size,
3686                         u32 alignment)
3687 {
3688         const struct rte_memzone *mz = NULL;
3689         char z_name[RTE_MEMZONE_NAMESIZE];
3690
3691         if (!mem)
3692                 return I40E_ERR_PARAM;
3693
3694         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3695         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3696                                          alignment, RTE_PGSIZE_2M);
3697         if (!mz)
3698                 return I40E_ERR_NO_MEMORY;
3699
3700         mem->size = size;
3701         mem->va = mz->addr;
3702         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3703         mem->zone = (const void *)mz;
3704         PMD_DRV_LOG(DEBUG,
3705                 "memzone %s allocated with physical address: %"PRIu64,
3706                 mz->name, mem->pa);
3707
3708         return I40E_SUCCESS;
3709 }
3710
3711 /**
3712  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3713  * @hw:   pointer to the HW structure
3714  * @mem:  ptr to mem struct to free
3715  **/
3716 enum i40e_status_code
3717 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3718                     struct i40e_dma_mem *mem)
3719 {
3720         if (!mem)
3721                 return I40E_ERR_PARAM;
3722
3723         PMD_DRV_LOG(DEBUG,
3724                 "memzone %s to be freed with physical address: %"PRIu64,
3725                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3726         rte_memzone_free((const struct rte_memzone *)mem->zone);
3727         mem->zone = NULL;
3728         mem->va = NULL;
3729         mem->pa = (u64)0;
3730
3731         return I40E_SUCCESS;
3732 }
3733
3734 /**
3735  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3736  * @hw:   pointer to the HW structure
3737  * @mem:  pointer to mem struct to fill out
3738  * @size: size of memory requested
3739  **/
3740 enum i40e_status_code
3741 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3742                          struct i40e_virt_mem *mem,
3743                          u32 size)
3744 {
3745         if (!mem)
3746                 return I40E_ERR_PARAM;
3747
3748         mem->size = size;
3749         mem->va = rte_zmalloc("i40e", size, 0);
3750
3751         if (mem->va)
3752                 return I40E_SUCCESS;
3753         else
3754                 return I40E_ERR_NO_MEMORY;
3755 }
3756
3757 /**
3758  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3759  * @hw:   pointer to the HW structure
3760  * @mem:  pointer to mem struct to free
3761  **/
3762 enum i40e_status_code
3763 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3764                      struct i40e_virt_mem *mem)
3765 {
3766         if (!mem)
3767                 return I40E_ERR_PARAM;
3768
3769         rte_free(mem->va);
3770         mem->va = NULL;
3771
3772         return I40E_SUCCESS;
3773 }
3774
3775 void
3776 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3777 {
3778         rte_spinlock_init(&sp->spinlock);
3779 }
3780
3781 void
3782 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3783 {
3784         rte_spinlock_lock(&sp->spinlock);
3785 }
3786
3787 void
3788 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3789 {
3790         rte_spinlock_unlock(&sp->spinlock);
3791 }
3792
3793 void
3794 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3795 {
3796         return;
3797 }
3798
3799 /**
3800  * Get the hardware capabilities, which will be parsed
3801  * and saved into struct i40e_hw.
3802  */
3803 static int
3804 i40e_get_cap(struct i40e_hw *hw)
3805 {
3806         struct i40e_aqc_list_capabilities_element_resp *buf;
3807         uint16_t len, size = 0;
3808         int ret;
3809
3810         /* Calculate a huge enough buff for saving response data temporarily */
3811         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3812                                                 I40E_MAX_CAP_ELE_NUM;
3813         buf = rte_zmalloc("i40e", len, 0);
3814         if (!buf) {
3815                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3816                 return I40E_ERR_NO_MEMORY;
3817         }
3818
3819         /* Get, parse the capabilities and save it to hw */
3820         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3821                         i40e_aqc_opc_list_func_capabilities, NULL);
3822         if (ret != I40E_SUCCESS)
3823                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3824
3825         /* Free the temporary buffer after being used */
3826         rte_free(buf);
3827
3828         return ret;
3829 }
3830
3831 static int
3832 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3833 {
3834         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3835         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3836         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3837         uint16_t qp_count = 0, vsi_count = 0;
3838
3839         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3840                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3841                 return -EINVAL;
3842         }
3843         /* Add the parameter init for LFC */
3844         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3845         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3846         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3847
3848         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3849         pf->max_num_vsi = hw->func_caps.num_vsis;
3850         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3851         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3852         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3853
3854         /* FDir queue/VSI allocation */
3855         pf->fdir_qp_offset = 0;
3856         if (hw->func_caps.fd) {
3857                 pf->flags |= I40E_FLAG_FDIR;
3858                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3859         } else {
3860                 pf->fdir_nb_qps = 0;
3861         }
3862         qp_count += pf->fdir_nb_qps;
3863         vsi_count += 1;
3864
3865         /* LAN queue/VSI allocation */
3866         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3867         if (!hw->func_caps.rss) {
3868                 pf->lan_nb_qps = 1;
3869         } else {
3870                 pf->flags |= I40E_FLAG_RSS;
3871                 if (hw->mac.type == I40E_MAC_X722)
3872                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3873                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3874         }
3875         qp_count += pf->lan_nb_qps;
3876         vsi_count += 1;
3877
3878         /* VF queue/VSI allocation */
3879         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3880         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3881                 pf->flags |= I40E_FLAG_SRIOV;
3882                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3883                 pf->vf_num = pci_dev->max_vfs;
3884                 PMD_DRV_LOG(DEBUG,
3885                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3886                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3887         } else {
3888                 pf->vf_nb_qps = 0;
3889                 pf->vf_num = 0;
3890         }
3891         qp_count += pf->vf_nb_qps * pf->vf_num;
3892         vsi_count += pf->vf_num;
3893
3894         /* VMDq queue/VSI allocation */
3895         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3896         pf->vmdq_nb_qps = 0;
3897         pf->max_nb_vmdq_vsi = 0;
3898         if (hw->func_caps.vmdq) {
3899                 if (qp_count < hw->func_caps.num_tx_qp &&
3900                         vsi_count < hw->func_caps.num_vsis) {
3901                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3902                                 qp_count) / pf->vmdq_nb_qp_max;
3903
3904                         /* Limit the maximum number of VMDq vsi to the maximum
3905                          * ethdev can support
3906                          */
3907                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3908                                 hw->func_caps.num_vsis - vsi_count);
3909                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3910                                 ETH_64_POOLS);
3911                         if (pf->max_nb_vmdq_vsi) {
3912                                 pf->flags |= I40E_FLAG_VMDQ;
3913                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3914                                 PMD_DRV_LOG(DEBUG,
3915                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3916                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3917                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3918                         } else {
3919                                 PMD_DRV_LOG(INFO,
3920                                         "No enough queues left for VMDq");
3921                         }
3922                 } else {
3923                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3924                 }
3925         }
3926         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3927         vsi_count += pf->max_nb_vmdq_vsi;
3928
3929         if (hw->func_caps.dcb)
3930                 pf->flags |= I40E_FLAG_DCB;
3931
3932         if (qp_count > hw->func_caps.num_tx_qp) {
3933                 PMD_DRV_LOG(ERR,
3934                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3935                         qp_count, hw->func_caps.num_tx_qp);
3936                 return -EINVAL;
3937         }
3938         if (vsi_count > hw->func_caps.num_vsis) {
3939                 PMD_DRV_LOG(ERR,
3940                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3941                         vsi_count, hw->func_caps.num_vsis);
3942                 return -EINVAL;
3943         }
3944
3945         return 0;
3946 }
3947
3948 static int
3949 i40e_pf_get_switch_config(struct i40e_pf *pf)
3950 {
3951         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3952         struct i40e_aqc_get_switch_config_resp *switch_config;
3953         struct i40e_aqc_switch_config_element_resp *element;
3954         uint16_t start_seid = 0, num_reported;
3955         int ret;
3956
3957         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3958                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3959         if (!switch_config) {
3960                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3961                 return -ENOMEM;
3962         }
3963
3964         /* Get the switch configurations */
3965         ret = i40e_aq_get_switch_config(hw, switch_config,
3966                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3967         if (ret != I40E_SUCCESS) {
3968                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3969                 goto fail;
3970         }
3971         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3972         if (num_reported != 1) { /* The number should be 1 */
3973                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3974                 goto fail;
3975         }
3976
3977         /* Parse the switch configuration elements */
3978         element = &(switch_config->element[0]);
3979         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3980                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3981                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3982         } else
3983                 PMD_DRV_LOG(INFO, "Unknown element type");
3984
3985 fail:
3986         rte_free(switch_config);
3987
3988         return ret;
3989 }
3990
3991 static int
3992 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3993                         uint32_t num)
3994 {
3995         struct pool_entry *entry;
3996
3997         if (pool == NULL || num == 0)
3998                 return -EINVAL;
3999
4000         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4001         if (entry == NULL) {
4002                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4003                 return -ENOMEM;
4004         }
4005
4006         /* queue heap initialize */
4007         pool->num_free = num;
4008         pool->num_alloc = 0;
4009         pool->base = base;
4010         LIST_INIT(&pool->alloc_list);
4011         LIST_INIT(&pool->free_list);
4012
4013         /* Initialize element  */
4014         entry->base = 0;
4015         entry->len = num;
4016
4017         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4018         return 0;
4019 }
4020
4021 static void
4022 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4023 {
4024         struct pool_entry *entry, *next_entry;
4025
4026         if (pool == NULL)
4027                 return;
4028
4029         for (entry = LIST_FIRST(&pool->alloc_list);
4030                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4031                         entry = next_entry) {
4032                 LIST_REMOVE(entry, next);
4033                 rte_free(entry);
4034         }
4035
4036         for (entry = LIST_FIRST(&pool->free_list);
4037                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4038                         entry = next_entry) {
4039                 LIST_REMOVE(entry, next);
4040                 rte_free(entry);
4041         }
4042
4043         pool->num_free = 0;
4044         pool->num_alloc = 0;
4045         pool->base = 0;
4046         LIST_INIT(&pool->alloc_list);
4047         LIST_INIT(&pool->free_list);
4048 }
4049
4050 static int
4051 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4052                        uint32_t base)
4053 {
4054         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4055         uint32_t pool_offset;
4056         int insert;
4057
4058         if (pool == NULL) {
4059                 PMD_DRV_LOG(ERR, "Invalid parameter");
4060                 return -EINVAL;
4061         }
4062
4063         pool_offset = base - pool->base;
4064         /* Lookup in alloc list */
4065         LIST_FOREACH(entry, &pool->alloc_list, next) {
4066                 if (entry->base == pool_offset) {
4067                         valid_entry = entry;
4068                         LIST_REMOVE(entry, next);
4069                         break;
4070                 }
4071         }
4072
4073         /* Not find, return */
4074         if (valid_entry == NULL) {
4075                 PMD_DRV_LOG(ERR, "Failed to find entry");
4076                 return -EINVAL;
4077         }
4078
4079         /**
4080          * Found it, move it to free list  and try to merge.
4081          * In order to make merge easier, always sort it by qbase.
4082          * Find adjacent prev and last entries.
4083          */
4084         prev = next = NULL;
4085         LIST_FOREACH(entry, &pool->free_list, next) {
4086                 if (entry->base > valid_entry->base) {
4087                         next = entry;
4088                         break;
4089                 }
4090                 prev = entry;
4091         }
4092
4093         insert = 0;
4094         /* Try to merge with next one*/
4095         if (next != NULL) {
4096                 /* Merge with next one */
4097                 if (valid_entry->base + valid_entry->len == next->base) {
4098                         next->base = valid_entry->base;
4099                         next->len += valid_entry->len;
4100                         rte_free(valid_entry);
4101                         valid_entry = next;
4102                         insert = 1;
4103                 }
4104         }
4105
4106         if (prev != NULL) {
4107                 /* Merge with previous one */
4108                 if (prev->base + prev->len == valid_entry->base) {
4109                         prev->len += valid_entry->len;
4110                         /* If it merge with next one, remove next node */
4111                         if (insert == 1) {
4112                                 LIST_REMOVE(valid_entry, next);
4113                                 rte_free(valid_entry);
4114                         } else {
4115                                 rte_free(valid_entry);
4116                                 insert = 1;
4117                         }
4118                 }
4119         }
4120
4121         /* Not find any entry to merge, insert */
4122         if (insert == 0) {
4123                 if (prev != NULL)
4124                         LIST_INSERT_AFTER(prev, valid_entry, next);
4125                 else if (next != NULL)
4126                         LIST_INSERT_BEFORE(next, valid_entry, next);
4127                 else /* It's empty list, insert to head */
4128                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4129         }
4130
4131         pool->num_free += valid_entry->len;
4132         pool->num_alloc -= valid_entry->len;
4133
4134         return 0;
4135 }
4136
4137 static int
4138 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4139                        uint16_t num)
4140 {
4141         struct pool_entry *entry, *valid_entry;
4142
4143         if (pool == NULL || num == 0) {
4144                 PMD_DRV_LOG(ERR, "Invalid parameter");
4145                 return -EINVAL;
4146         }
4147
4148         if (pool->num_free < num) {
4149                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4150                             num, pool->num_free);
4151                 return -ENOMEM;
4152         }
4153
4154         valid_entry = NULL;
4155         /* Lookup  in free list and find most fit one */
4156         LIST_FOREACH(entry, &pool->free_list, next) {
4157                 if (entry->len >= num) {
4158                         /* Find best one */
4159                         if (entry->len == num) {
4160                                 valid_entry = entry;
4161                                 break;
4162                         }
4163                         if (valid_entry == NULL || valid_entry->len > entry->len)
4164                                 valid_entry = entry;
4165                 }
4166         }
4167
4168         /* Not find one to satisfy the request, return */
4169         if (valid_entry == NULL) {
4170                 PMD_DRV_LOG(ERR, "No valid entry found");
4171                 return -ENOMEM;
4172         }
4173         /**
4174          * The entry have equal queue number as requested,
4175          * remove it from alloc_list.
4176          */
4177         if (valid_entry->len == num) {
4178                 LIST_REMOVE(valid_entry, next);
4179         } else {
4180                 /**
4181                  * The entry have more numbers than requested,
4182                  * create a new entry for alloc_list and minus its
4183                  * queue base and number in free_list.
4184                  */
4185                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4186                 if (entry == NULL) {
4187                         PMD_DRV_LOG(ERR,
4188                                 "Failed to allocate memory for resource pool");
4189                         return -ENOMEM;
4190                 }
4191                 entry->base = valid_entry->base;
4192                 entry->len = num;
4193                 valid_entry->base += num;
4194                 valid_entry->len -= num;
4195                 valid_entry = entry;
4196         }
4197
4198         /* Insert it into alloc list, not sorted */
4199         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4200
4201         pool->num_free -= valid_entry->len;
4202         pool->num_alloc += valid_entry->len;
4203
4204         return valid_entry->base + pool->base;
4205 }
4206
4207 /**
4208  * bitmap_is_subset - Check whether src2 is subset of src1
4209  **/
4210 static inline int
4211 bitmap_is_subset(uint8_t src1, uint8_t src2)
4212 {
4213         return !((src1 ^ src2) & src2);
4214 }
4215
4216 static enum i40e_status_code
4217 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4218 {
4219         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4220
4221         /* If DCB is not supported, only default TC is supported */
4222         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4223                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4224                 return I40E_NOT_SUPPORTED;
4225         }
4226
4227         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4228                 PMD_DRV_LOG(ERR,
4229                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4230                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4231                 return I40E_NOT_SUPPORTED;
4232         }
4233         return I40E_SUCCESS;
4234 }
4235
4236 int
4237 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4238                                 struct i40e_vsi_vlan_pvid_info *info)
4239 {
4240         struct i40e_hw *hw;
4241         struct i40e_vsi_context ctxt;
4242         uint8_t vlan_flags = 0;
4243         int ret;
4244
4245         if (vsi == NULL || info == NULL) {
4246                 PMD_DRV_LOG(ERR, "invalid parameters");
4247                 return I40E_ERR_PARAM;
4248         }
4249
4250         if (info->on) {
4251                 vsi->info.pvid = info->config.pvid;
4252                 /**
4253                  * If insert pvid is enabled, only tagged pkts are
4254                  * allowed to be sent out.
4255                  */
4256                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4257                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4258         } else {
4259                 vsi->info.pvid = 0;
4260                 if (info->config.reject.tagged == 0)
4261                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4262
4263                 if (info->config.reject.untagged == 0)
4264                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4265         }
4266         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4267                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4268         vsi->info.port_vlan_flags |= vlan_flags;
4269         vsi->info.valid_sections =
4270                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4271         memset(&ctxt, 0, sizeof(ctxt));
4272         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4273         ctxt.seid = vsi->seid;
4274
4275         hw = I40E_VSI_TO_HW(vsi);
4276         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4277         if (ret != I40E_SUCCESS)
4278                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4279
4280         return ret;
4281 }
4282
4283 static int
4284 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4285 {
4286         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4287         int i, ret;
4288         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4289
4290         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4291         if (ret != I40E_SUCCESS)
4292                 return ret;
4293
4294         if (!vsi->seid) {
4295                 PMD_DRV_LOG(ERR, "seid not valid");
4296                 return -EINVAL;
4297         }
4298
4299         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4300         tc_bw_data.tc_valid_bits = enabled_tcmap;
4301         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4302                 tc_bw_data.tc_bw_credits[i] =
4303                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4304
4305         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4306         if (ret != I40E_SUCCESS) {
4307                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4308                 return ret;
4309         }
4310
4311         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4312                                         sizeof(vsi->info.qs_handle));
4313         return I40E_SUCCESS;
4314 }
4315
4316 static enum i40e_status_code
4317 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4318                                  struct i40e_aqc_vsi_properties_data *info,
4319                                  uint8_t enabled_tcmap)
4320 {
4321         enum i40e_status_code ret;
4322         int i, total_tc = 0;
4323         uint16_t qpnum_per_tc, bsf, qp_idx;
4324
4325         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4326         if (ret != I40E_SUCCESS)
4327                 return ret;
4328
4329         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4330                 if (enabled_tcmap & (1 << i))
4331                         total_tc++;
4332         if (total_tc == 0)
4333                 total_tc = 1;
4334         vsi->enabled_tc = enabled_tcmap;
4335
4336         /* Number of queues per enabled TC */
4337         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4338         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4339         bsf = rte_bsf32(qpnum_per_tc);
4340
4341         /* Adjust the queue number to actual queues that can be applied */
4342         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4343                 vsi->nb_qps = qpnum_per_tc * total_tc;
4344
4345         /**
4346          * Configure TC and queue mapping parameters, for enabled TC,
4347          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4348          * default queue will serve it.
4349          */
4350         qp_idx = 0;
4351         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4352                 if (vsi->enabled_tc & (1 << i)) {
4353                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4354                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4355                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4356                         qp_idx += qpnum_per_tc;
4357                 } else
4358                         info->tc_mapping[i] = 0;
4359         }
4360
4361         /* Associate queue number with VSI */
4362         if (vsi->type == I40E_VSI_SRIOV) {
4363                 info->mapping_flags |=
4364                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4365                 for (i = 0; i < vsi->nb_qps; i++)
4366                         info->queue_mapping[i] =
4367                                 rte_cpu_to_le_16(vsi->base_queue + i);
4368         } else {
4369                 info->mapping_flags |=
4370                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4371                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4372         }
4373         info->valid_sections |=
4374                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4375
4376         return I40E_SUCCESS;
4377 }
4378
4379 static int
4380 i40e_veb_release(struct i40e_veb *veb)
4381 {
4382         struct i40e_vsi *vsi;
4383         struct i40e_hw *hw;
4384
4385         if (veb == NULL)
4386                 return -EINVAL;
4387
4388         if (!TAILQ_EMPTY(&veb->head)) {
4389                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4390                 return -EACCES;
4391         }
4392         /* associate_vsi field is NULL for floating VEB */
4393         if (veb->associate_vsi != NULL) {
4394                 vsi = veb->associate_vsi;
4395                 hw = I40E_VSI_TO_HW(vsi);
4396
4397                 vsi->uplink_seid = veb->uplink_seid;
4398                 vsi->veb = NULL;
4399         } else {
4400                 veb->associate_pf->main_vsi->floating_veb = NULL;
4401                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4402         }
4403
4404         i40e_aq_delete_element(hw, veb->seid, NULL);
4405         rte_free(veb);
4406         return I40E_SUCCESS;
4407 }
4408
4409 /* Setup a veb */
4410 static struct i40e_veb *
4411 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4412 {
4413         struct i40e_veb *veb;
4414         int ret;
4415         struct i40e_hw *hw;
4416
4417         if (pf == NULL) {
4418                 PMD_DRV_LOG(ERR,
4419                             "veb setup failed, associated PF shouldn't null");
4420                 return NULL;
4421         }
4422         hw = I40E_PF_TO_HW(pf);
4423
4424         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4425         if (!veb) {
4426                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4427                 goto fail;
4428         }
4429
4430         veb->associate_vsi = vsi;
4431         veb->associate_pf = pf;
4432         TAILQ_INIT(&veb->head);
4433         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4434
4435         /* create floating veb if vsi is NULL */
4436         if (vsi != NULL) {
4437                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4438                                       I40E_DEFAULT_TCMAP, false,
4439                                       &veb->seid, false, NULL);
4440         } else {
4441                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4442                                       true, &veb->seid, false, NULL);
4443         }
4444
4445         if (ret != I40E_SUCCESS) {
4446                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4447                             hw->aq.asq_last_status);
4448                 goto fail;
4449         }
4450         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4451
4452         /* get statistics index */
4453         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4454                                 &veb->stats_idx, NULL, NULL, NULL);
4455         if (ret != I40E_SUCCESS) {
4456                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4457                             hw->aq.asq_last_status);
4458                 goto fail;
4459         }
4460         /* Get VEB bandwidth, to be implemented */
4461         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4462         if (vsi)
4463                 vsi->uplink_seid = veb->seid;
4464
4465         return veb;
4466 fail:
4467         rte_free(veb);
4468         return NULL;
4469 }
4470
4471 int
4472 i40e_vsi_release(struct i40e_vsi *vsi)
4473 {
4474         struct i40e_pf *pf;
4475         struct i40e_hw *hw;
4476         struct i40e_vsi_list *vsi_list;
4477         void *temp;
4478         int ret;
4479         struct i40e_mac_filter *f;
4480         uint16_t user_param;
4481
4482         if (!vsi)
4483                 return I40E_SUCCESS;
4484
4485         if (!vsi->adapter)
4486                 return -EFAULT;
4487
4488         user_param = vsi->user_param;
4489
4490         pf = I40E_VSI_TO_PF(vsi);
4491         hw = I40E_VSI_TO_HW(vsi);
4492
4493         /* VSI has child to attach, release child first */
4494         if (vsi->veb) {
4495                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4496                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4497                                 return -1;
4498                 }
4499                 i40e_veb_release(vsi->veb);
4500         }
4501
4502         if (vsi->floating_veb) {
4503                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4504                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4505                                 return -1;
4506                 }
4507         }
4508
4509         /* Remove all macvlan filters of the VSI */
4510         i40e_vsi_remove_all_macvlan_filter(vsi);
4511         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4512                 rte_free(f);
4513
4514         if (vsi->type != I40E_VSI_MAIN &&
4515             ((vsi->type != I40E_VSI_SRIOV) ||
4516             !pf->floating_veb_list[user_param])) {
4517                 /* Remove vsi from parent's sibling list */
4518                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4519                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4520                         return I40E_ERR_PARAM;
4521                 }
4522                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4523                                 &vsi->sib_vsi_list, list);
4524
4525                 /* Remove all switch element of the VSI */
4526                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4527                 if (ret != I40E_SUCCESS)
4528                         PMD_DRV_LOG(ERR, "Failed to delete element");
4529         }
4530
4531         if ((vsi->type == I40E_VSI_SRIOV) &&
4532             pf->floating_veb_list[user_param]) {
4533                 /* Remove vsi from parent's sibling list */
4534                 if (vsi->parent_vsi == NULL ||
4535                     vsi->parent_vsi->floating_veb == NULL) {
4536                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4537                         return I40E_ERR_PARAM;
4538                 }
4539                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4540                              &vsi->sib_vsi_list, list);
4541
4542                 /* Remove all switch element of the VSI */
4543                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4544                 if (ret != I40E_SUCCESS)
4545                         PMD_DRV_LOG(ERR, "Failed to delete element");
4546         }
4547
4548         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4549
4550         if (vsi->type != I40E_VSI_SRIOV)
4551                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4552         rte_free(vsi);
4553
4554         return I40E_SUCCESS;
4555 }
4556
4557 static int
4558 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4559 {
4560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4561         struct i40e_aqc_remove_macvlan_element_data def_filter;
4562         struct i40e_mac_filter_info filter;
4563         int ret;
4564
4565         if (vsi->type != I40E_VSI_MAIN)
4566                 return I40E_ERR_CONFIG;
4567         memset(&def_filter, 0, sizeof(def_filter));
4568         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4569                                         ETH_ADDR_LEN);
4570         def_filter.vlan_tag = 0;
4571         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4572                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4573         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4574         if (ret != I40E_SUCCESS) {
4575                 struct i40e_mac_filter *f;
4576                 struct ether_addr *mac;
4577
4578                 PMD_DRV_LOG(DEBUG,
4579                             "Cannot remove the default macvlan filter");
4580                 /* It needs to add the permanent mac into mac list */
4581                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4582                 if (f == NULL) {
4583                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4584                         return I40E_ERR_NO_MEMORY;
4585                 }
4586                 mac = &f->mac_info.mac_addr;
4587                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4588                                 ETH_ADDR_LEN);
4589                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4590                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4591                 vsi->mac_num++;
4592
4593                 return ret;
4594         }
4595         (void)rte_memcpy(&filter.mac_addr,
4596                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4597         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4598         return i40e_vsi_add_mac(vsi, &filter);
4599 }
4600
4601 /*
4602  * i40e_vsi_get_bw_config - Query VSI BW Information
4603  * @vsi: the VSI to be queried
4604  *
4605  * Returns 0 on success, negative value on failure
4606  */
4607 static enum i40e_status_code
4608 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4609 {
4610         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4611         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4612         struct i40e_hw *hw = &vsi->adapter->hw;
4613         i40e_status ret;
4614         int i;
4615         uint32_t bw_max;
4616
4617         memset(&bw_config, 0, sizeof(bw_config));
4618         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4619         if (ret != I40E_SUCCESS) {
4620                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4621                             hw->aq.asq_last_status);
4622                 return ret;
4623         }
4624
4625         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4626         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4627                                         &ets_sla_config, NULL);
4628         if (ret != I40E_SUCCESS) {
4629                 PMD_DRV_LOG(ERR,
4630                         "VSI failed to get TC bandwdith configuration %u",
4631                         hw->aq.asq_last_status);
4632                 return ret;
4633         }
4634
4635         /* store and print out BW info */
4636         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4637         vsi->bw_info.bw_max = bw_config.max_bw;
4638         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4639         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4640         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4641                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4642                      I40E_16_BIT_WIDTH);
4643         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4644                 vsi->bw_info.bw_ets_share_credits[i] =
4645                                 ets_sla_config.share_credits[i];
4646                 vsi->bw_info.bw_ets_credits[i] =
4647                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4648                 /* 4 bits per TC, 4th bit is reserved */
4649                 vsi->bw_info.bw_ets_max[i] =
4650                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4651                                   RTE_LEN2MASK(3, uint8_t));
4652                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4653                             vsi->bw_info.bw_ets_share_credits[i]);
4654                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4655                             vsi->bw_info.bw_ets_credits[i]);
4656                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4657                             vsi->bw_info.bw_ets_max[i]);
4658         }
4659
4660         return I40E_SUCCESS;
4661 }
4662
4663 /* i40e_enable_pf_lb
4664  * @pf: pointer to the pf structure
4665  *
4666  * allow loopback on pf
4667  */
4668 static inline void
4669 i40e_enable_pf_lb(struct i40e_pf *pf)
4670 {
4671         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4672         struct i40e_vsi_context ctxt;
4673         int ret;
4674
4675         /* Use the FW API if FW >= v5.0 */
4676         if (hw->aq.fw_maj_ver < 5) {
4677                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4678                 return;
4679         }
4680
4681         memset(&ctxt, 0, sizeof(ctxt));
4682         ctxt.seid = pf->main_vsi_seid;
4683         ctxt.pf_num = hw->pf_id;
4684         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4685         if (ret) {
4686                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4687                             ret, hw->aq.asq_last_status);
4688                 return;
4689         }
4690         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4691         ctxt.info.valid_sections =
4692                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4693         ctxt.info.switch_id |=
4694                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4695
4696         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4697         if (ret)
4698                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4699                             hw->aq.asq_last_status);
4700 }
4701
4702 /* Setup a VSI */
4703 struct i40e_vsi *
4704 i40e_vsi_setup(struct i40e_pf *pf,
4705                enum i40e_vsi_type type,
4706                struct i40e_vsi *uplink_vsi,
4707                uint16_t user_param)
4708 {
4709         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4710         struct i40e_vsi *vsi;
4711         struct i40e_mac_filter_info filter;
4712         int ret;
4713         struct i40e_vsi_context ctxt;
4714         struct ether_addr broadcast =
4715                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4716
4717         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4718             uplink_vsi == NULL) {
4719                 PMD_DRV_LOG(ERR,
4720                         "VSI setup failed, VSI link shouldn't be NULL");
4721                 return NULL;
4722         }
4723
4724         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4725                 PMD_DRV_LOG(ERR,
4726                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4727                 return NULL;
4728         }
4729
4730         /* two situations
4731          * 1.type is not MAIN and uplink vsi is not NULL
4732          * If uplink vsi didn't setup VEB, create one first under veb field
4733          * 2.type is SRIOV and the uplink is NULL
4734          * If floating VEB is NULL, create one veb under floating veb field
4735          */
4736
4737         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4738             uplink_vsi->veb == NULL) {
4739                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4740
4741                 if (uplink_vsi->veb == NULL) {
4742                         PMD_DRV_LOG(ERR, "VEB setup failed");
4743                         return NULL;
4744                 }
4745                 /* set ALLOWLOOPBACk on pf, when veb is created */
4746                 i40e_enable_pf_lb(pf);
4747         }
4748
4749         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4750             pf->main_vsi->floating_veb == NULL) {
4751                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4752
4753                 if (pf->main_vsi->floating_veb == NULL) {
4754                         PMD_DRV_LOG(ERR, "VEB setup failed");
4755                         return NULL;
4756                 }
4757         }
4758
4759         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4760         if (!vsi) {
4761                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4762                 return NULL;
4763         }
4764         TAILQ_INIT(&vsi->mac_list);
4765         vsi->type = type;
4766         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4767         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4768         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4769         vsi->user_param = user_param;
4770         vsi->vlan_anti_spoof_on = 0;
4771         vsi->vlan_filter_on = 0;
4772         /* Allocate queues */
4773         switch (vsi->type) {
4774         case I40E_VSI_MAIN  :
4775                 vsi->nb_qps = pf->lan_nb_qps;
4776                 break;
4777         case I40E_VSI_SRIOV :
4778                 vsi->nb_qps = pf->vf_nb_qps;
4779                 break;
4780         case I40E_VSI_VMDQ2:
4781                 vsi->nb_qps = pf->vmdq_nb_qps;
4782                 break;
4783         case I40E_VSI_FDIR:
4784                 vsi->nb_qps = pf->fdir_nb_qps;
4785                 break;
4786         default:
4787                 goto fail_mem;
4788         }
4789         /*
4790          * The filter status descriptor is reported in rx queue 0,
4791          * while the tx queue for fdir filter programming has no
4792          * such constraints, can be non-zero queues.
4793          * To simplify it, choose FDIR vsi use queue 0 pair.
4794          * To make sure it will use queue 0 pair, queue allocation
4795          * need be done before this function is called
4796          */
4797         if (type != I40E_VSI_FDIR) {
4798                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4799                         if (ret < 0) {
4800                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4801                                                 vsi->seid, ret);
4802                                 goto fail_mem;
4803                         }
4804                         vsi->base_queue = ret;
4805         } else
4806                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4807
4808         /* VF has MSIX interrupt in VF range, don't allocate here */
4809         if (type == I40E_VSI_MAIN) {
4810                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4811                                           RTE_MIN(vsi->nb_qps,
4812                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4813                 if (ret < 0) {
4814                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4815                                     vsi->seid, ret);
4816                         goto fail_queue_alloc;
4817                 }
4818                 vsi->msix_intr = ret;
4819                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4820         } else if (type != I40E_VSI_SRIOV) {
4821                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4822                 if (ret < 0) {
4823                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4824                         goto fail_queue_alloc;
4825                 }
4826                 vsi->msix_intr = ret;
4827                 vsi->nb_msix = 1;
4828         } else {
4829                 vsi->msix_intr = 0;
4830                 vsi->nb_msix = 0;
4831         }
4832
4833         /* Add VSI */
4834         if (type == I40E_VSI_MAIN) {
4835                 /* For main VSI, no need to add since it's default one */
4836                 vsi->uplink_seid = pf->mac_seid;
4837                 vsi->seid = pf->main_vsi_seid;
4838                 /* Bind queues with specific MSIX interrupt */
4839                 /**
4840                  * Needs 2 interrupt at least, one for misc cause which will
4841                  * enabled from OS side, Another for queues binding the
4842                  * interrupt from device side only.
4843                  */
4844
4845                 /* Get default VSI parameters from hardware */
4846                 memset(&ctxt, 0, sizeof(ctxt));
4847                 ctxt.seid = vsi->seid;
4848                 ctxt.pf_num = hw->pf_id;
4849                 ctxt.uplink_seid = vsi->uplink_seid;
4850                 ctxt.vf_num = 0;
4851                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4852                 if (ret != I40E_SUCCESS) {
4853                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4854                         goto fail_msix_alloc;
4855                 }
4856                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4857                         sizeof(struct i40e_aqc_vsi_properties_data));
4858                 vsi->vsi_id = ctxt.vsi_number;
4859                 vsi->info.valid_sections = 0;
4860
4861                 /* Configure tc, enabled TC0 only */
4862                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4863                         I40E_SUCCESS) {
4864                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4865                         goto fail_msix_alloc;
4866                 }
4867
4868                 /* TC, queue mapping */
4869                 memset(&ctxt, 0, sizeof(ctxt));
4870                 vsi->info.valid_sections |=
4871                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4872                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4873                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4874                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4875                         sizeof(struct i40e_aqc_vsi_properties_data));
4876                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4877                                                 I40E_DEFAULT_TCMAP);
4878                 if (ret != I40E_SUCCESS) {
4879                         PMD_DRV_LOG(ERR,
4880                                 "Failed to configure TC queue mapping");
4881                         goto fail_msix_alloc;
4882                 }
4883                 ctxt.seid = vsi->seid;
4884                 ctxt.pf_num = hw->pf_id;
4885                 ctxt.uplink_seid = vsi->uplink_seid;
4886                 ctxt.vf_num = 0;
4887
4888                 /* Update VSI parameters */
4889                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4890                 if (ret != I40E_SUCCESS) {
4891                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4892                         goto fail_msix_alloc;
4893                 }
4894
4895                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4896                                                 sizeof(vsi->info.tc_mapping));
4897                 (void)rte_memcpy(&vsi->info.queue_mapping,
4898                                 &ctxt.info.queue_mapping,
4899                         sizeof(vsi->info.queue_mapping));
4900                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4901                 vsi->info.valid_sections = 0;
4902
4903                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4904                                 ETH_ADDR_LEN);
4905
4906                 /**
4907                  * Updating default filter settings are necessary to prevent
4908                  * reception of tagged packets.
4909                  * Some old firmware configurations load a default macvlan
4910                  * filter which accepts both tagged and untagged packets.
4911                  * The updating is to use a normal filter instead if needed.
4912                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4913                  * The firmware with correct configurations load the default
4914                  * macvlan filter which is expected and cannot be removed.
4915                  */
4916                 i40e_update_default_filter_setting(vsi);
4917                 i40e_config_qinq(hw, vsi);
4918         } else if (type == I40E_VSI_SRIOV) {
4919                 memset(&ctxt, 0, sizeof(ctxt));
4920                 /**
4921                  * For other VSI, the uplink_seid equals to uplink VSI's
4922                  * uplink_seid since they share same VEB
4923                  */
4924                 if (uplink_vsi == NULL)
4925                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4926                 else
4927                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4928                 ctxt.pf_num = hw->pf_id;
4929                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4930                 ctxt.uplink_seid = vsi->uplink_seid;
4931                 ctxt.connection_type = 0x1;
4932                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4933
4934                 /* Use the VEB configuration if FW >= v5.0 */
4935                 if (hw->aq.fw_maj_ver >= 5) {
4936                         /* Configure switch ID */
4937                         ctxt.info.valid_sections |=
4938                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4939                         ctxt.info.switch_id =
4940                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4941                 }
4942
4943                 /* Configure port/vlan */
4944                 ctxt.info.valid_sections |=
4945                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4946                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4947                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4948                                                 hw->func_caps.enabled_tcmap);
4949                 if (ret != I40E_SUCCESS) {
4950                         PMD_DRV_LOG(ERR,
4951                                 "Failed to configure TC queue mapping");
4952                         goto fail_msix_alloc;
4953                 }
4954
4955                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4956                 ctxt.info.valid_sections |=
4957                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4958                 /**
4959                  * Since VSI is not created yet, only configure parameter,
4960                  * will add vsi below.
4961                  */
4962
4963                 i40e_config_qinq(hw, vsi);
4964         } else if (type == I40E_VSI_VMDQ2) {
4965                 memset(&ctxt, 0, sizeof(ctxt));
4966                 /*
4967                  * For other VSI, the uplink_seid equals to uplink VSI's
4968                  * uplink_seid since they share same VEB
4969                  */
4970                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4971                 ctxt.pf_num = hw->pf_id;
4972                 ctxt.vf_num = 0;
4973                 ctxt.uplink_seid = vsi->uplink_seid;
4974                 ctxt.connection_type = 0x1;
4975                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4976
4977                 ctxt.info.valid_sections |=
4978                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4979                 /* user_param carries flag to enable loop back */
4980                 if (user_param) {
4981                         ctxt.info.switch_id =
4982                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4983                         ctxt.info.switch_id |=
4984                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4985                 }
4986
4987                 /* Configure port/vlan */
4988                 ctxt.info.valid_sections |=
4989                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4990                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4991                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4992                                                 I40E_DEFAULT_TCMAP);
4993                 if (ret != I40E_SUCCESS) {
4994                         PMD_DRV_LOG(ERR,
4995                                 "Failed to configure TC queue mapping");
4996                         goto fail_msix_alloc;
4997                 }
4998                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4999                 ctxt.info.valid_sections |=
5000                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5001         } else if (type == I40E_VSI_FDIR) {
5002                 memset(&ctxt, 0, sizeof(ctxt));
5003                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5004                 ctxt.pf_num = hw->pf_id;
5005                 ctxt.vf_num = 0;
5006                 ctxt.uplink_seid = vsi->uplink_seid;
5007                 ctxt.connection_type = 0x1;     /* regular data port */
5008                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5009                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5010                                                 I40E_DEFAULT_TCMAP);
5011                 if (ret != I40E_SUCCESS) {
5012                         PMD_DRV_LOG(ERR,
5013                                 "Failed to configure TC queue mapping.");
5014                         goto fail_msix_alloc;
5015                 }
5016                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5017                 ctxt.info.valid_sections |=
5018                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5019         } else {
5020                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5021                 goto fail_msix_alloc;
5022         }
5023
5024         if (vsi->type != I40E_VSI_MAIN) {
5025                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5026                 if (ret != I40E_SUCCESS) {
5027                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5028                                     hw->aq.asq_last_status);
5029                         goto fail_msix_alloc;
5030                 }
5031                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5032                 vsi->info.valid_sections = 0;
5033                 vsi->seid = ctxt.seid;
5034                 vsi->vsi_id = ctxt.vsi_number;
5035                 vsi->sib_vsi_list.vsi = vsi;
5036                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5037                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5038                                           &vsi->sib_vsi_list, list);
5039                 } else {
5040                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5041                                           &vsi->sib_vsi_list, list);
5042                 }
5043         }
5044
5045         /* MAC/VLAN configuration */
5046         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5047         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5048
5049         ret = i40e_vsi_add_mac(vsi, &filter);
5050         if (ret != I40E_SUCCESS) {
5051                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5052                 goto fail_msix_alloc;
5053         }
5054
5055         /* Get VSI BW information */
5056         i40e_vsi_get_bw_config(vsi);
5057         return vsi;
5058 fail_msix_alloc:
5059         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5060 fail_queue_alloc:
5061         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5062 fail_mem:
5063         rte_free(vsi);
5064         return NULL;
5065 }
5066
5067 /* Configure vlan filter on or off */
5068 int
5069 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5070 {
5071         int i, num;
5072         struct i40e_mac_filter *f;
5073         void *temp;
5074         struct i40e_mac_filter_info *mac_filter;
5075         enum rte_mac_filter_type desired_filter;
5076         int ret = I40E_SUCCESS;
5077
5078         if (on) {
5079                 /* Filter to match MAC and VLAN */
5080                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5081         } else {
5082                 /* Filter to match only MAC */
5083                 desired_filter = RTE_MAC_PERFECT_MATCH;
5084         }
5085
5086         num = vsi->mac_num;
5087
5088         mac_filter = rte_zmalloc("mac_filter_info_data",
5089                                  num * sizeof(*mac_filter), 0);
5090         if (mac_filter == NULL) {
5091                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5092                 return I40E_ERR_NO_MEMORY;
5093         }
5094
5095         i = 0;
5096
5097         /* Remove all existing mac */
5098         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5099                 mac_filter[i] = f->mac_info;
5100                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5101                 if (ret) {
5102                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5103                                     on ? "enable" : "disable");
5104                         goto DONE;
5105                 }
5106                 i++;
5107         }
5108
5109         /* Override with new filter */
5110         for (i = 0; i < num; i++) {
5111                 mac_filter[i].filter_type = desired_filter;
5112                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5113                 if (ret) {
5114                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5115                                     on ? "enable" : "disable");
5116                         goto DONE;
5117                 }
5118         }
5119
5120 DONE:
5121         rte_free(mac_filter);
5122         return ret;
5123 }
5124
5125 /* Configure vlan stripping on or off */
5126 int
5127 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5128 {
5129         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5130         struct i40e_vsi_context ctxt;
5131         uint8_t vlan_flags;
5132         int ret = I40E_SUCCESS;
5133
5134         /* Check if it has been already on or off */
5135         if (vsi->info.valid_sections &
5136                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5137                 if (on) {
5138                         if ((vsi->info.port_vlan_flags &
5139                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5140                                 return 0; /* already on */
5141                 } else {
5142                         if ((vsi->info.port_vlan_flags &
5143                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5144                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5145                                 return 0; /* already off */
5146                 }
5147         }
5148
5149         if (on)
5150                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5151         else
5152                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5153         vsi->info.valid_sections =
5154                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5155         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5156         vsi->info.port_vlan_flags |= vlan_flags;
5157         ctxt.seid = vsi->seid;
5158         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5159         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5160         if (ret)
5161                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5162                             on ? "enable" : "disable");
5163
5164         return ret;
5165 }
5166
5167 static int
5168 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5169 {
5170         struct rte_eth_dev_data *data = dev->data;
5171         int ret;
5172         int mask = 0;
5173
5174         /* Apply vlan offload setting */
5175         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5176         i40e_vlan_offload_set(dev, mask);
5177
5178         /* Apply double-vlan setting, not implemented yet */
5179
5180         /* Apply pvid setting */
5181         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5182                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5183         if (ret)
5184                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5185
5186         return ret;
5187 }
5188
5189 static int
5190 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5191 {
5192         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5193
5194         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5195 }
5196
5197 static int
5198 i40e_update_flow_control(struct i40e_hw *hw)
5199 {
5200 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5201         struct i40e_link_status link_status;
5202         uint32_t rxfc = 0, txfc = 0, reg;
5203         uint8_t an_info;
5204         int ret;
5205
5206         memset(&link_status, 0, sizeof(link_status));
5207         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5208         if (ret != I40E_SUCCESS) {
5209                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5210                 goto write_reg; /* Disable flow control */
5211         }
5212
5213         an_info = hw->phy.link_info.an_info;
5214         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5215                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5216                 ret = I40E_ERR_NOT_READY;
5217                 goto write_reg; /* Disable flow control */
5218         }
5219         /**
5220          * If link auto negotiation is enabled, flow control needs to
5221          * be configured according to it
5222          */
5223         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5224         case I40E_LINK_PAUSE_RXTX:
5225                 rxfc = 1;
5226                 txfc = 1;
5227                 hw->fc.current_mode = I40E_FC_FULL;
5228                 break;
5229         case I40E_AQ_LINK_PAUSE_RX:
5230                 rxfc = 1;
5231                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5232                 break;
5233         case I40E_AQ_LINK_PAUSE_TX:
5234                 txfc = 1;
5235                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5236                 break;
5237         default:
5238                 hw->fc.current_mode = I40E_FC_NONE;
5239                 break;
5240         }
5241
5242 write_reg:
5243         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5244                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5245         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5246         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5247         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5248         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5249
5250         return ret;
5251 }
5252
5253 /* PF setup */
5254 static int
5255 i40e_pf_setup(struct i40e_pf *pf)
5256 {
5257         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5258         struct i40e_filter_control_settings settings;
5259         struct i40e_vsi *vsi;
5260         int ret;
5261
5262         /* Clear all stats counters */
5263         pf->offset_loaded = FALSE;
5264         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5265         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5266         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5267         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5268
5269         ret = i40e_pf_get_switch_config(pf);
5270         if (ret != I40E_SUCCESS) {
5271                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5272                 return ret;
5273         }
5274         if (pf->flags & I40E_FLAG_FDIR) {
5275                 /* make queue allocated first, let FDIR use queue pair 0*/
5276                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5277                 if (ret != I40E_FDIR_QUEUE_ID) {
5278                         PMD_DRV_LOG(ERR,
5279                                 "queue allocation fails for FDIR: ret =%d",
5280                                 ret);
5281                         pf->flags &= ~I40E_FLAG_FDIR;
5282                 }
5283         }
5284         /*  main VSI setup */
5285         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5286         if (!vsi) {
5287                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5288                 return I40E_ERR_NOT_READY;
5289         }
5290         pf->main_vsi = vsi;
5291
5292         /* Configure filter control */
5293         memset(&settings, 0, sizeof(settings));
5294         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5295                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5296         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5297                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5298         else {
5299                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5300                         hw->func_caps.rss_table_size);
5301                 return I40E_ERR_PARAM;
5302         }
5303         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5304                 hw->func_caps.rss_table_size);
5305         pf->hash_lut_size = hw->func_caps.rss_table_size;
5306
5307         /* Enable ethtype and macvlan filters */
5308         settings.enable_ethtype = TRUE;
5309         settings.enable_macvlan = TRUE;
5310         ret = i40e_set_filter_control(hw, &settings);
5311         if (ret)
5312                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5313                                                                 ret);
5314
5315         /* Update flow control according to the auto negotiation */
5316         i40e_update_flow_control(hw);
5317
5318         return I40E_SUCCESS;
5319 }
5320
5321 int
5322 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5323 {
5324         uint32_t reg;
5325         uint16_t j;
5326
5327         /**
5328          * Set or clear TX Queue Disable flags,
5329          * which is required by hardware.
5330          */
5331         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5332         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5333
5334         /* Wait until the request is finished */
5335         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5336                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5337                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5338                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5339                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5340                                                         & 0x1))) {
5341                         break;
5342                 }
5343         }
5344         if (on) {
5345                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5346                         return I40E_SUCCESS; /* already on, skip next steps */
5347
5348                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5349                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5350         } else {
5351                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5352                         return I40E_SUCCESS; /* already off, skip next steps */
5353                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5354         }
5355         /* Write the register */
5356         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5357         /* Check the result */
5358         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5359                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5360                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5361                 if (on) {
5362                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5363                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5364                                 break;
5365                 } else {
5366                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5367                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5368                                 break;
5369                 }
5370         }
5371         /* Check if it is timeout */
5372         if (j >= I40E_CHK_Q_ENA_COUNT) {
5373                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5374                             (on ? "enable" : "disable"), q_idx);
5375                 return I40E_ERR_TIMEOUT;
5376         }
5377
5378         return I40E_SUCCESS;
5379 }
5380
5381 /* Swith on or off the tx queues */
5382 static int
5383 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5384 {
5385         struct rte_eth_dev_data *dev_data = pf->dev_data;
5386         struct i40e_tx_queue *txq;
5387         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5388         uint16_t i;
5389         int ret;
5390
5391         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5392                 txq = dev_data->tx_queues[i];
5393                 /* Don't operate the queue if not configured or
5394                  * if starting only per queue */
5395                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5396                         continue;
5397                 if (on)
5398                         ret = i40e_dev_tx_queue_start(dev, i);
5399                 else
5400                         ret = i40e_dev_tx_queue_stop(dev, i);
5401                 if ( ret != I40E_SUCCESS)
5402                         return ret;
5403         }
5404
5405         return I40E_SUCCESS;
5406 }
5407
5408 int
5409 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5410 {
5411         uint32_t reg;
5412         uint16_t j;
5413
5414         /* Wait until the request is finished */
5415         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5416                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5417                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5418                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5419                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5420                         break;
5421         }
5422
5423         if (on) {
5424                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5425                         return I40E_SUCCESS; /* Already on, skip next steps */
5426                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5427         } else {
5428                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5429                         return I40E_SUCCESS; /* Already off, skip next steps */
5430                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5431         }
5432
5433         /* Write the register */
5434         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5435         /* Check the result */
5436         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5437                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5438                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5439                 if (on) {
5440                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5441                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5442                                 break;
5443                 } else {
5444                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5445                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5446                                 break;
5447                 }
5448         }
5449
5450         /* Check if it is timeout */
5451         if (j >= I40E_CHK_Q_ENA_COUNT) {
5452                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5453                             (on ? "enable" : "disable"), q_idx);
5454                 return I40E_ERR_TIMEOUT;
5455         }
5456
5457         return I40E_SUCCESS;
5458 }
5459 /* Switch on or off the rx queues */
5460 static int
5461 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5462 {
5463         struct rte_eth_dev_data *dev_data = pf->dev_data;
5464         struct i40e_rx_queue *rxq;
5465         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5466         uint16_t i;
5467         int ret;
5468
5469         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5470                 rxq = dev_data->rx_queues[i];
5471                 /* Don't operate the queue if not configured or
5472                  * if starting only per queue */
5473                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5474                         continue;
5475                 if (on)
5476                         ret = i40e_dev_rx_queue_start(dev, i);
5477                 else
5478                         ret = i40e_dev_rx_queue_stop(dev, i);
5479                 if (ret != I40E_SUCCESS)
5480                         return ret;
5481         }
5482
5483         return I40E_SUCCESS;
5484 }
5485
5486 /* Switch on or off all the rx/tx queues */
5487 int
5488 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5489 {
5490         int ret;
5491
5492         if (on) {
5493                 /* enable rx queues before enabling tx queues */
5494                 ret = i40e_dev_switch_rx_queues(pf, on);
5495                 if (ret) {
5496                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5497                         return ret;
5498                 }
5499                 ret = i40e_dev_switch_tx_queues(pf, on);
5500         } else {
5501                 /* Stop tx queues before stopping rx queues */
5502                 ret = i40e_dev_switch_tx_queues(pf, on);
5503                 if (ret) {
5504                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5505                         return ret;
5506                 }
5507                 ret = i40e_dev_switch_rx_queues(pf, on);
5508         }
5509
5510         return ret;
5511 }
5512
5513 /* Initialize VSI for TX */
5514 static int
5515 i40e_dev_tx_init(struct i40e_pf *pf)
5516 {
5517         struct rte_eth_dev_data *data = pf->dev_data;
5518         uint16_t i;
5519         uint32_t ret = I40E_SUCCESS;
5520         struct i40e_tx_queue *txq;
5521
5522         for (i = 0; i < data->nb_tx_queues; i++) {
5523                 txq = data->tx_queues[i];
5524                 if (!txq || !txq->q_set)
5525                         continue;
5526                 ret = i40e_tx_queue_init(txq);
5527                 if (ret != I40E_SUCCESS)
5528                         break;
5529         }
5530         if (ret == I40E_SUCCESS)
5531                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5532                                      ->eth_dev);
5533
5534         return ret;
5535 }
5536
5537 /* Initialize VSI for RX */
5538 static int
5539 i40e_dev_rx_init(struct i40e_pf *pf)
5540 {
5541         struct rte_eth_dev_data *data = pf->dev_data;
5542         int ret = I40E_SUCCESS;
5543         uint16_t i;
5544         struct i40e_rx_queue *rxq;
5545
5546         i40e_pf_config_mq_rx(pf);
5547         for (i = 0; i < data->nb_rx_queues; i++) {
5548                 rxq = data->rx_queues[i];
5549                 if (!rxq || !rxq->q_set)
5550                         continue;
5551
5552                 ret = i40e_rx_queue_init(rxq);
5553                 if (ret != I40E_SUCCESS) {
5554                         PMD_DRV_LOG(ERR,
5555                                 "Failed to do RX queue initialization");
5556                         break;
5557                 }
5558         }
5559         if (ret == I40E_SUCCESS)
5560                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5561                                      ->eth_dev);
5562
5563         return ret;
5564 }
5565
5566 static int
5567 i40e_dev_rxtx_init(struct i40e_pf *pf)
5568 {
5569         int err;
5570
5571         err = i40e_dev_tx_init(pf);
5572         if (err) {
5573                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5574                 return err;
5575         }
5576         err = i40e_dev_rx_init(pf);
5577         if (err) {
5578                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5579                 return err;
5580         }
5581
5582         return err;
5583 }
5584
5585 static int
5586 i40e_vmdq_setup(struct rte_eth_dev *dev)
5587 {
5588         struct rte_eth_conf *conf = &dev->data->dev_conf;
5589         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5590         int i, err, conf_vsis, j, loop;
5591         struct i40e_vsi *vsi;
5592         struct i40e_vmdq_info *vmdq_info;
5593         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5594         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5595
5596         /*
5597          * Disable interrupt to avoid message from VF. Furthermore, it will
5598          * avoid race condition in VSI creation/destroy.
5599          */
5600         i40e_pf_disable_irq0(hw);
5601
5602         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5603                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5604                 return -ENOTSUP;
5605         }
5606
5607         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5608         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5609                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5610                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5611                         pf->max_nb_vmdq_vsi);
5612                 return -ENOTSUP;
5613         }
5614
5615         if (pf->vmdq != NULL) {
5616                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5617                 return 0;
5618         }
5619
5620         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5621                                 sizeof(*vmdq_info) * conf_vsis, 0);
5622
5623         if (pf->vmdq == NULL) {
5624                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5625                 return -ENOMEM;
5626         }
5627
5628         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5629
5630         /* Create VMDQ VSI */
5631         for (i = 0; i < conf_vsis; i++) {
5632                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5633                                 vmdq_conf->enable_loop_back);
5634                 if (vsi == NULL) {
5635                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5636                         err = -1;
5637                         goto err_vsi_setup;
5638                 }
5639                 vmdq_info = &pf->vmdq[i];
5640                 vmdq_info->pf = pf;
5641                 vmdq_info->vsi = vsi;
5642         }
5643         pf->nb_cfg_vmdq_vsi = conf_vsis;
5644
5645         /* Configure Vlan */
5646         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5647         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5648                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5649                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5650                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5651                                         vmdq_conf->pool_map[i].vlan_id, j);
5652
5653                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5654                                                 vmdq_conf->pool_map[i].vlan_id);
5655                                 if (err) {
5656                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5657                                         err = -1;
5658                                         goto err_vsi_setup;
5659                                 }
5660                         }
5661                 }
5662         }
5663
5664         i40e_pf_enable_irq0(hw);
5665
5666         return 0;
5667
5668 err_vsi_setup:
5669         for (i = 0; i < conf_vsis; i++)
5670                 if (pf->vmdq[i].vsi == NULL)
5671                         break;
5672                 else
5673                         i40e_vsi_release(pf->vmdq[i].vsi);
5674
5675         rte_free(pf->vmdq);
5676         pf->vmdq = NULL;
5677         i40e_pf_enable_irq0(hw);
5678         return err;
5679 }
5680
5681 static void
5682 i40e_stat_update_32(struct i40e_hw *hw,
5683                    uint32_t reg,
5684                    bool offset_loaded,
5685                    uint64_t *offset,
5686                    uint64_t *stat)
5687 {
5688         uint64_t new_data;
5689
5690         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5691         if (!offset_loaded)
5692                 *offset = new_data;
5693
5694         if (new_data >= *offset)
5695                 *stat = (uint64_t)(new_data - *offset);
5696         else
5697                 *stat = (uint64_t)((new_data +
5698                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5699 }
5700
5701 static void
5702 i40e_stat_update_48(struct i40e_hw *hw,
5703                    uint32_t hireg,
5704                    uint32_t loreg,
5705                    bool offset_loaded,
5706                    uint64_t *offset,
5707                    uint64_t *stat)
5708 {
5709         uint64_t new_data;
5710
5711         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5712         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5713                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5714
5715         if (!offset_loaded)
5716                 *offset = new_data;
5717
5718         if (new_data >= *offset)
5719                 *stat = new_data - *offset;
5720         else
5721                 *stat = (uint64_t)((new_data +
5722                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5723
5724         *stat &= I40E_48_BIT_MASK;
5725 }
5726
5727 /* Disable IRQ0 */
5728 void
5729 i40e_pf_disable_irq0(struct i40e_hw *hw)
5730 {
5731         /* Disable all interrupt types */
5732         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5733         I40E_WRITE_FLUSH(hw);
5734 }
5735
5736 /* Enable IRQ0 */
5737 void
5738 i40e_pf_enable_irq0(struct i40e_hw *hw)
5739 {
5740         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5741                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5742                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5743                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5744         I40E_WRITE_FLUSH(hw);
5745 }
5746
5747 static void
5748 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5749 {
5750         /* read pending request and disable first */
5751         i40e_pf_disable_irq0(hw);
5752         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5753         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5754                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5755
5756         if (no_queue)
5757                 /* Link no queues with irq0 */
5758                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5759                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5760 }
5761
5762 static void
5763 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5764 {
5765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5766         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5767         int i;
5768         uint16_t abs_vf_id;
5769         uint32_t index, offset, val;
5770
5771         if (!pf->vfs)
5772                 return;
5773         /**
5774          * Try to find which VF trigger a reset, use absolute VF id to access
5775          * since the reg is global register.
5776          */
5777         for (i = 0; i < pf->vf_num; i++) {
5778                 abs_vf_id = hw->func_caps.vf_base_id + i;
5779                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5780                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5781                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5782                 /* VFR event occured */
5783                 if (val & (0x1 << offset)) {
5784                         int ret;
5785
5786                         /* Clear the event first */
5787                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5788                                                         (0x1 << offset));
5789                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5790                         /**
5791                          * Only notify a VF reset event occured,
5792                          * don't trigger another SW reset
5793                          */
5794                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5795                         if (ret != I40E_SUCCESS)
5796                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5797                 }
5798         }
5799 }
5800
5801 static void
5802 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5803 {
5804         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5805         int i;
5806
5807         for (i = 0; i < pf->vf_num; i++)
5808                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5809 }
5810
5811 static void
5812 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5813 {
5814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5815         struct i40e_arq_event_info info;
5816         uint16_t pending, opcode;
5817         int ret;
5818
5819         info.buf_len = I40E_AQ_BUF_SZ;
5820         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5821         if (!info.msg_buf) {
5822                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5823                 return;
5824         }
5825
5826         pending = 1;
5827         while (pending) {
5828                 ret = i40e_clean_arq_element(hw, &info, &pending);
5829
5830                 if (ret != I40E_SUCCESS) {
5831                         PMD_DRV_LOG(INFO,
5832                                 "Failed to read msg from AdminQ, aq_err: %u",
5833                                 hw->aq.asq_last_status);
5834                         break;
5835                 }
5836                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5837
5838                 switch (opcode) {
5839                 case i40e_aqc_opc_send_msg_to_pf:
5840                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5841                         i40e_pf_host_handle_vf_msg(dev,
5842                                         rte_le_to_cpu_16(info.desc.retval),
5843                                         rte_le_to_cpu_32(info.desc.cookie_high),
5844                                         rte_le_to_cpu_32(info.desc.cookie_low),
5845                                         info.msg_buf,
5846                                         info.msg_len);
5847                         break;
5848                 case i40e_aqc_opc_get_link_status:
5849                         ret = i40e_dev_link_update(dev, 0);
5850                         if (!ret)
5851                                 _rte_eth_dev_callback_process(dev,
5852                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5853                         break;
5854                 default:
5855                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5856                                     opcode);
5857                         break;
5858                 }
5859         }
5860         rte_free(info.msg_buf);
5861 }
5862
5863 /**
5864  * Interrupt handler triggered by NIC  for handling
5865  * specific interrupt.
5866  *
5867  * @param handle
5868  *  Pointer to interrupt handle.
5869  * @param param
5870  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5871  *
5872  * @return
5873  *  void
5874  */
5875 static void
5876 i40e_dev_interrupt_handler(void *param)
5877 {
5878         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5879         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5880         uint32_t icr0;
5881
5882         /* Disable interrupt */
5883         i40e_pf_disable_irq0(hw);
5884
5885         /* read out interrupt causes */
5886         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5887
5888         /* No interrupt event indicated */
5889         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5890                 PMD_DRV_LOG(INFO, "No interrupt event");
5891                 goto done;
5892         }
5893         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5894                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5895         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5896                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5897         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5898                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5899         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5900                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5901         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5902                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5903         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5904                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5905         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5906                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5907
5908         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5909                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5910                 i40e_dev_handle_vfr_event(dev);
5911         }
5912         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5913                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5914                 i40e_dev_handle_aq_msg(dev);
5915         }
5916
5917 done:
5918         /* Enable interrupt */
5919         i40e_pf_enable_irq0(hw);
5920         rte_intr_enable(dev->intr_handle);
5921 }
5922
5923 int
5924 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5925                          struct i40e_macvlan_filter *filter,
5926                          int total)
5927 {
5928         int ele_num, ele_buff_size;
5929         int num, actual_num, i;
5930         uint16_t flags;
5931         int ret = I40E_SUCCESS;
5932         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5933         struct i40e_aqc_add_macvlan_element_data *req_list;
5934
5935         if (filter == NULL  || total == 0)
5936                 return I40E_ERR_PARAM;
5937         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5938         ele_buff_size = hw->aq.asq_buf_size;
5939
5940         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5941         if (req_list == NULL) {
5942                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5943                 return I40E_ERR_NO_MEMORY;
5944         }
5945
5946         num = 0;
5947         do {
5948                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5949                 memset(req_list, 0, ele_buff_size);
5950
5951                 for (i = 0; i < actual_num; i++) {
5952                         (void)rte_memcpy(req_list[i].mac_addr,
5953                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5954                         req_list[i].vlan_tag =
5955                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5956
5957                         switch (filter[num + i].filter_type) {
5958                         case RTE_MAC_PERFECT_MATCH:
5959                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5960                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5961                                 break;
5962                         case RTE_MACVLAN_PERFECT_MATCH:
5963                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5964                                 break;
5965                         case RTE_MAC_HASH_MATCH:
5966                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5967                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5968                                 break;
5969                         case RTE_MACVLAN_HASH_MATCH:
5970                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5971                                 break;
5972                         default:
5973                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5974                                 ret = I40E_ERR_PARAM;
5975                                 goto DONE;
5976                         }
5977
5978                         req_list[i].queue_number = 0;
5979
5980                         req_list[i].flags = rte_cpu_to_le_16(flags);
5981                 }
5982
5983                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5984                                                 actual_num, NULL);
5985                 if (ret != I40E_SUCCESS) {
5986                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5987                         goto DONE;
5988                 }
5989                 num += actual_num;
5990         } while (num < total);
5991
5992 DONE:
5993         rte_free(req_list);
5994         return ret;
5995 }
5996
5997 int
5998 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5999                             struct i40e_macvlan_filter *filter,
6000                             int total)
6001 {
6002         int ele_num, ele_buff_size;
6003         int num, actual_num, i;
6004         uint16_t flags;
6005         int ret = I40E_SUCCESS;
6006         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6007         struct i40e_aqc_remove_macvlan_element_data *req_list;
6008
6009         if (filter == NULL  || total == 0)
6010                 return I40E_ERR_PARAM;
6011
6012         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6013         ele_buff_size = hw->aq.asq_buf_size;
6014
6015         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6016         if (req_list == NULL) {
6017                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6018                 return I40E_ERR_NO_MEMORY;
6019         }
6020
6021         num = 0;
6022         do {
6023                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6024                 memset(req_list, 0, ele_buff_size);
6025
6026                 for (i = 0; i < actual_num; i++) {
6027                         (void)rte_memcpy(req_list[i].mac_addr,
6028                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6029                         req_list[i].vlan_tag =
6030                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6031
6032                         switch (filter[num + i].filter_type) {
6033                         case RTE_MAC_PERFECT_MATCH:
6034                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6035                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6036                                 break;
6037                         case RTE_MACVLAN_PERFECT_MATCH:
6038                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6039                                 break;
6040                         case RTE_MAC_HASH_MATCH:
6041                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6042                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6043                                 break;
6044                         case RTE_MACVLAN_HASH_MATCH:
6045                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6046                                 break;
6047                         default:
6048                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6049                                 ret = I40E_ERR_PARAM;
6050                                 goto DONE;
6051                         }
6052                         req_list[i].flags = rte_cpu_to_le_16(flags);
6053                 }
6054
6055                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6056                                                 actual_num, NULL);
6057                 if (ret != I40E_SUCCESS) {
6058                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6059                         goto DONE;
6060                 }
6061                 num += actual_num;
6062         } while (num < total);
6063
6064 DONE:
6065         rte_free(req_list);
6066         return ret;
6067 }
6068
6069 /* Find out specific MAC filter */
6070 static struct i40e_mac_filter *
6071 i40e_find_mac_filter(struct i40e_vsi *vsi,
6072                          struct ether_addr *macaddr)
6073 {
6074         struct i40e_mac_filter *f;
6075
6076         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6077                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6078                         return f;
6079         }
6080
6081         return NULL;
6082 }
6083
6084 static bool
6085 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6086                          uint16_t vlan_id)
6087 {
6088         uint32_t vid_idx, vid_bit;
6089
6090         if (vlan_id > ETH_VLAN_ID_MAX)
6091                 return 0;
6092
6093         vid_idx = I40E_VFTA_IDX(vlan_id);
6094         vid_bit = I40E_VFTA_BIT(vlan_id);
6095
6096         if (vsi->vfta[vid_idx] & vid_bit)
6097                 return 1;
6098         else
6099                 return 0;
6100 }
6101
6102 static void
6103 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6104                        uint16_t vlan_id, bool on)
6105 {
6106         uint32_t vid_idx, vid_bit;
6107
6108         vid_idx = I40E_VFTA_IDX(vlan_id);
6109         vid_bit = I40E_VFTA_BIT(vlan_id);
6110
6111         if (on)
6112                 vsi->vfta[vid_idx] |= vid_bit;
6113         else
6114                 vsi->vfta[vid_idx] &= ~vid_bit;
6115 }
6116
6117 void
6118 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6119                      uint16_t vlan_id, bool on)
6120 {
6121         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6122         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6123         int ret;
6124
6125         if (vlan_id > ETH_VLAN_ID_MAX)
6126                 return;
6127
6128         i40e_store_vlan_filter(vsi, vlan_id, on);
6129
6130         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6131                 return;
6132
6133         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6134
6135         if (on) {
6136                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6137                                        &vlan_data, 1, NULL);
6138                 if (ret != I40E_SUCCESS)
6139                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6140         } else {
6141                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6142                                           &vlan_data, 1, NULL);
6143                 if (ret != I40E_SUCCESS)
6144                         PMD_DRV_LOG(ERR,
6145                                     "Failed to remove vlan filter");
6146         }
6147 }
6148
6149 /**
6150  * Find all vlan options for specific mac addr,
6151  * return with actual vlan found.
6152  */
6153 int
6154 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6155                            struct i40e_macvlan_filter *mv_f,
6156                            int num, struct ether_addr *addr)
6157 {
6158         int i;
6159         uint32_t j, k;
6160
6161         /**
6162          * Not to use i40e_find_vlan_filter to decrease the loop time,
6163          * although the code looks complex.
6164           */
6165         if (num < vsi->vlan_num)
6166                 return I40E_ERR_PARAM;
6167
6168         i = 0;
6169         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6170                 if (vsi->vfta[j]) {
6171                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6172                                 if (vsi->vfta[j] & (1 << k)) {
6173                                         if (i > num - 1) {
6174                                                 PMD_DRV_LOG(ERR,
6175                                                         "vlan number doesn't match");
6176                                                 return I40E_ERR_PARAM;
6177                                         }
6178                                         (void)rte_memcpy(&mv_f[i].macaddr,
6179                                                         addr, ETH_ADDR_LEN);
6180                                         mv_f[i].vlan_id =
6181                                                 j * I40E_UINT32_BIT_SIZE + k;
6182                                         i++;
6183                                 }
6184                         }
6185                 }
6186         }
6187         return I40E_SUCCESS;
6188 }
6189
6190 static inline int
6191 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6192                            struct i40e_macvlan_filter *mv_f,
6193                            int num,
6194                            uint16_t vlan)
6195 {
6196         int i = 0;
6197         struct i40e_mac_filter *f;
6198
6199         if (num < vsi->mac_num)
6200                 return I40E_ERR_PARAM;
6201
6202         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6203                 if (i > num - 1) {
6204                         PMD_DRV_LOG(ERR, "buffer number not match");
6205                         return I40E_ERR_PARAM;
6206                 }
6207                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6208                                 ETH_ADDR_LEN);
6209                 mv_f[i].vlan_id = vlan;
6210                 mv_f[i].filter_type = f->mac_info.filter_type;
6211                 i++;
6212         }
6213
6214         return I40E_SUCCESS;
6215 }
6216
6217 static int
6218 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6219 {
6220         int i, j, num;
6221         struct i40e_mac_filter *f;
6222         struct i40e_macvlan_filter *mv_f;
6223         int ret = I40E_SUCCESS;
6224
6225         if (vsi == NULL || vsi->mac_num == 0)
6226                 return I40E_ERR_PARAM;
6227
6228         /* Case that no vlan is set */
6229         if (vsi->vlan_num == 0)
6230                 num = vsi->mac_num;
6231         else
6232                 num = vsi->mac_num * vsi->vlan_num;
6233
6234         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6235         if (mv_f == NULL) {
6236                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6237                 return I40E_ERR_NO_MEMORY;
6238         }
6239
6240         i = 0;
6241         if (vsi->vlan_num == 0) {
6242                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6243                         (void)rte_memcpy(&mv_f[i].macaddr,
6244                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6245                         mv_f[i].filter_type = f->mac_info.filter_type;
6246                         mv_f[i].vlan_id = 0;
6247                         i++;
6248                 }
6249         } else {
6250                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6251                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6252                                         vsi->vlan_num, &f->mac_info.mac_addr);
6253                         if (ret != I40E_SUCCESS)
6254                                 goto DONE;
6255                         for (j = i; j < i + vsi->vlan_num; j++)
6256                                 mv_f[j].filter_type = f->mac_info.filter_type;
6257                         i += vsi->vlan_num;
6258                 }
6259         }
6260
6261         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6262 DONE:
6263         rte_free(mv_f);
6264
6265         return ret;
6266 }
6267
6268 int
6269 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6270 {
6271         struct i40e_macvlan_filter *mv_f;
6272         int mac_num;
6273         int ret = I40E_SUCCESS;
6274
6275         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6276                 return I40E_ERR_PARAM;
6277
6278         /* If it's already set, just return */
6279         if (i40e_find_vlan_filter(vsi,vlan))
6280                 return I40E_SUCCESS;
6281
6282         mac_num = vsi->mac_num;
6283
6284         if (mac_num == 0) {
6285                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6286                 return I40E_ERR_PARAM;
6287         }
6288
6289         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6290
6291         if (mv_f == NULL) {
6292                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6293                 return I40E_ERR_NO_MEMORY;
6294         }
6295
6296         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6297
6298         if (ret != I40E_SUCCESS)
6299                 goto DONE;
6300
6301         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6302
6303         if (ret != I40E_SUCCESS)
6304                 goto DONE;
6305
6306         i40e_set_vlan_filter(vsi, vlan, 1);
6307
6308         vsi->vlan_num++;
6309         ret = I40E_SUCCESS;
6310 DONE:
6311         rte_free(mv_f);
6312         return ret;
6313 }
6314
6315 int
6316 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6317 {
6318         struct i40e_macvlan_filter *mv_f;
6319         int mac_num;
6320         int ret = I40E_SUCCESS;
6321
6322         /**
6323          * Vlan 0 is the generic filter for untagged packets
6324          * and can't be removed.
6325          */
6326         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6327                 return I40E_ERR_PARAM;
6328
6329         /* If can't find it, just return */
6330         if (!i40e_find_vlan_filter(vsi, vlan))
6331                 return I40E_ERR_PARAM;
6332
6333         mac_num = vsi->mac_num;
6334
6335         if (mac_num == 0) {
6336                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6337                 return I40E_ERR_PARAM;
6338         }
6339
6340         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6341
6342         if (mv_f == NULL) {
6343                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6344                 return I40E_ERR_NO_MEMORY;
6345         }
6346
6347         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6348
6349         if (ret != I40E_SUCCESS)
6350                 goto DONE;
6351
6352         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6353
6354         if (ret != I40E_SUCCESS)
6355                 goto DONE;
6356
6357         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6358         if (vsi->vlan_num == 1) {
6359                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6360                 if (ret != I40E_SUCCESS)
6361                         goto DONE;
6362
6363                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6364                 if (ret != I40E_SUCCESS)
6365                         goto DONE;
6366         }
6367
6368         i40e_set_vlan_filter(vsi, vlan, 0);
6369
6370         vsi->vlan_num--;
6371         ret = I40E_SUCCESS;
6372 DONE:
6373         rte_free(mv_f);
6374         return ret;
6375 }
6376
6377 int
6378 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6379 {
6380         struct i40e_mac_filter *f;
6381         struct i40e_macvlan_filter *mv_f;
6382         int i, vlan_num = 0;
6383         int ret = I40E_SUCCESS;
6384
6385         /* If it's add and we've config it, return */
6386         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6387         if (f != NULL)
6388                 return I40E_SUCCESS;
6389         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6390                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6391
6392                 /**
6393                  * If vlan_num is 0, that's the first time to add mac,
6394                  * set mask for vlan_id 0.
6395                  */
6396                 if (vsi->vlan_num == 0) {
6397                         i40e_set_vlan_filter(vsi, 0, 1);
6398                         vsi->vlan_num = 1;
6399                 }
6400                 vlan_num = vsi->vlan_num;
6401         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6402                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6403                 vlan_num = 1;
6404
6405         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6406         if (mv_f == NULL) {
6407                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6408                 return I40E_ERR_NO_MEMORY;
6409         }
6410
6411         for (i = 0; i < vlan_num; i++) {
6412                 mv_f[i].filter_type = mac_filter->filter_type;
6413                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6414                                 ETH_ADDR_LEN);
6415         }
6416
6417         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6418                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6419                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6420                                         &mac_filter->mac_addr);
6421                 if (ret != I40E_SUCCESS)
6422                         goto DONE;
6423         }
6424
6425         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6426         if (ret != I40E_SUCCESS)
6427                 goto DONE;
6428
6429         /* Add the mac addr into mac list */
6430         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6431         if (f == NULL) {
6432                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6433                 ret = I40E_ERR_NO_MEMORY;
6434                 goto DONE;
6435         }
6436         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6437                         ETH_ADDR_LEN);
6438         f->mac_info.filter_type = mac_filter->filter_type;
6439         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6440         vsi->mac_num++;
6441
6442         ret = I40E_SUCCESS;
6443 DONE:
6444         rte_free(mv_f);
6445
6446         return ret;
6447 }
6448
6449 int
6450 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6451 {
6452         struct i40e_mac_filter *f;
6453         struct i40e_macvlan_filter *mv_f;
6454         int i, vlan_num;
6455         enum rte_mac_filter_type filter_type;
6456         int ret = I40E_SUCCESS;
6457
6458         /* Can't find it, return an error */
6459         f = i40e_find_mac_filter(vsi, addr);
6460         if (f == NULL)
6461                 return I40E_ERR_PARAM;
6462
6463         vlan_num = vsi->vlan_num;
6464         filter_type = f->mac_info.filter_type;
6465         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6466                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6467                 if (vlan_num == 0) {
6468                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6469                         return I40E_ERR_PARAM;
6470                 }
6471         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6472                         filter_type == RTE_MAC_HASH_MATCH)
6473                 vlan_num = 1;
6474
6475         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6476         if (mv_f == NULL) {
6477                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6478                 return I40E_ERR_NO_MEMORY;
6479         }
6480
6481         for (i = 0; i < vlan_num; i++) {
6482                 mv_f[i].filter_type = filter_type;
6483                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6484                                 ETH_ADDR_LEN);
6485         }
6486         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6487                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6488                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6489                 if (ret != I40E_SUCCESS)
6490                         goto DONE;
6491         }
6492
6493         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6494         if (ret != I40E_SUCCESS)
6495                 goto DONE;
6496
6497         /* Remove the mac addr into mac list */
6498         TAILQ_REMOVE(&vsi->mac_list, f, next);
6499         rte_free(f);
6500         vsi->mac_num--;
6501
6502         ret = I40E_SUCCESS;
6503 DONE:
6504         rte_free(mv_f);
6505         return ret;
6506 }
6507
6508 /* Configure hash enable flags for RSS */
6509 uint64_t
6510 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6511 {
6512         uint64_t hena = 0;
6513
6514         if (!flags)
6515                 return hena;
6516
6517         if (flags & ETH_RSS_FRAG_IPV4)
6518                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6519         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6520                 if (type == I40E_MAC_X722) {
6521                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6522                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6523                 } else
6524                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6525         }
6526         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6527                 if (type == I40E_MAC_X722) {
6528                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6529                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6530                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6531                 } else
6532                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6533         }
6534         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6535                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6536         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6537                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6538         if (flags & ETH_RSS_FRAG_IPV6)
6539                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6540         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6541                 if (type == I40E_MAC_X722) {
6542                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6543                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6544                 } else
6545                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6546         }
6547         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6548                 if (type == I40E_MAC_X722) {
6549                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6550                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6551                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6552                 } else
6553                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6554         }
6555         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6556                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6557         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6558                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6559         if (flags & ETH_RSS_L2_PAYLOAD)
6560                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6561
6562         return hena;
6563 }
6564
6565 /* Parse the hash enable flags */
6566 uint64_t
6567 i40e_parse_hena(uint64_t flags)
6568 {
6569         uint64_t rss_hf = 0;
6570
6571         if (!flags)
6572                 return rss_hf;
6573         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6574                 rss_hf |= ETH_RSS_FRAG_IPV4;
6575         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6576                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6577         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6578                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6579         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6580                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6581         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6582                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6583         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6584                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6585         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6586                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6587         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6588                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6589         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6590                 rss_hf |= ETH_RSS_FRAG_IPV6;
6591         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6592                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6593         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6594                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6595         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6596                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6597         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6598                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6599         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6600                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6601         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6602                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6603         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6604                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6605         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6606                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6607
6608         return rss_hf;
6609 }
6610
6611 /* Disable RSS */
6612 static void
6613 i40e_pf_disable_rss(struct i40e_pf *pf)
6614 {
6615         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6616         uint64_t hena;
6617
6618         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6619         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6620         if (hw->mac.type == I40E_MAC_X722)
6621                 hena &= ~I40E_RSS_HENA_ALL_X722;
6622         else
6623                 hena &= ~I40E_RSS_HENA_ALL;
6624         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6625         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6626         I40E_WRITE_FLUSH(hw);
6627 }
6628
6629 static int
6630 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6631 {
6632         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6633         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6634         int ret = 0;
6635
6636         if (!key || key_len == 0) {
6637                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6638                 return 0;
6639         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6640                 sizeof(uint32_t)) {
6641                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6642                 return -EINVAL;
6643         }
6644
6645         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6646                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6647                         (struct i40e_aqc_get_set_rss_key_data *)key;
6648
6649                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6650                 if (ret)
6651                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6652         } else {
6653                 uint32_t *hash_key = (uint32_t *)key;
6654                 uint16_t i;
6655
6656                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6657                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6658                 I40E_WRITE_FLUSH(hw);
6659         }
6660
6661         return ret;
6662 }
6663
6664 static int
6665 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6666 {
6667         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6668         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6669         int ret;
6670
6671         if (!key || !key_len)
6672                 return -EINVAL;
6673
6674         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6675                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6676                         (struct i40e_aqc_get_set_rss_key_data *)key);
6677                 if (ret) {
6678                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6679                         return ret;
6680                 }
6681         } else {
6682                 uint32_t *key_dw = (uint32_t *)key;
6683                 uint16_t i;
6684
6685                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6686                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6687         }
6688         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6689
6690         return 0;
6691 }
6692
6693 static int
6694 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6695 {
6696         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6697         uint64_t rss_hf;
6698         uint64_t hena;
6699         int ret;
6700
6701         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6702                                rss_conf->rss_key_len);
6703         if (ret)
6704                 return ret;
6705
6706         rss_hf = rss_conf->rss_hf;
6707         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6708         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6709         if (hw->mac.type == I40E_MAC_X722)
6710                 hena &= ~I40E_RSS_HENA_ALL_X722;
6711         else
6712                 hena &= ~I40E_RSS_HENA_ALL;
6713         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6714         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6715         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6716         I40E_WRITE_FLUSH(hw);
6717
6718         return 0;
6719 }
6720
6721 static int
6722 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6723                          struct rte_eth_rss_conf *rss_conf)
6724 {
6725         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6726         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6727         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6728         uint64_t hena;
6729
6730         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6731         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6732         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6733                  ? I40E_RSS_HENA_ALL_X722
6734                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6735                 if (rss_hf != 0) /* Enable RSS */
6736                         return -EINVAL;
6737                 return 0; /* Nothing to do */
6738         }
6739         /* RSS enabled */
6740         if (rss_hf == 0) /* Disable RSS */
6741                 return -EINVAL;
6742
6743         return i40e_hw_rss_hash_set(pf, rss_conf);
6744 }
6745
6746 static int
6747 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6748                            struct rte_eth_rss_conf *rss_conf)
6749 {
6750         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6752         uint64_t hena;
6753
6754         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6755                          &rss_conf->rss_key_len);
6756
6757         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6758         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6759         rss_conf->rss_hf = i40e_parse_hena(hena);
6760
6761         return 0;
6762 }
6763
6764 static int
6765 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6766 {
6767         switch (filter_type) {
6768         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6769                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6770                 break;
6771         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6772                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6773                 break;
6774         case RTE_TUNNEL_FILTER_IMAC_TENID:
6775                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6776                 break;
6777         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6778                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6779                 break;
6780         case ETH_TUNNEL_FILTER_IMAC:
6781                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6782                 break;
6783         case ETH_TUNNEL_FILTER_OIP:
6784                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6785                 break;
6786         case ETH_TUNNEL_FILTER_IIP:
6787                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6788                 break;
6789         default:
6790                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6791                 return -EINVAL;
6792         }
6793
6794         return 0;
6795 }
6796
6797 /* Convert tunnel filter structure */
6798 static int
6799 i40e_tunnel_filter_convert(
6800         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6801         struct i40e_tunnel_filter *tunnel_filter)
6802 {
6803         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6804                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6805         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6806                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6807         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6808         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6809              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6810             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6811                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6812         else
6813                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6814         tunnel_filter->input.flags = cld_filter->element.flags;
6815         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6816         tunnel_filter->queue = cld_filter->element.queue_number;
6817         rte_memcpy(tunnel_filter->input.general_fields,
6818                    cld_filter->general_fields,
6819                    sizeof(cld_filter->general_fields));
6820
6821         return 0;
6822 }
6823
6824 /* Check if there exists the tunnel filter */
6825 struct i40e_tunnel_filter *
6826 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6827                              const struct i40e_tunnel_filter_input *input)
6828 {
6829         int ret;
6830
6831         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6832         if (ret < 0)
6833                 return NULL;
6834
6835         return tunnel_rule->hash_map[ret];
6836 }
6837
6838 /* Add a tunnel filter into the SW list */
6839 static int
6840 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6841                              struct i40e_tunnel_filter *tunnel_filter)
6842 {
6843         struct i40e_tunnel_rule *rule = &pf->tunnel;
6844         int ret;
6845
6846         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6847         if (ret < 0) {
6848                 PMD_DRV_LOG(ERR,
6849                             "Failed to insert tunnel filter to hash table %d!",
6850                             ret);
6851                 return ret;
6852         }
6853         rule->hash_map[ret] = tunnel_filter;
6854
6855         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6856
6857         return 0;
6858 }
6859
6860 /* Delete a tunnel filter from the SW list */
6861 int
6862 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6863                           struct i40e_tunnel_filter_input *input)
6864 {
6865         struct i40e_tunnel_rule *rule = &pf->tunnel;
6866         struct i40e_tunnel_filter *tunnel_filter;
6867         int ret;
6868
6869         ret = rte_hash_del_key(rule->hash_table, input);
6870         if (ret < 0) {
6871                 PMD_DRV_LOG(ERR,
6872                             "Failed to delete tunnel filter to hash table %d!",
6873                             ret);
6874                 return ret;
6875         }
6876         tunnel_filter = rule->hash_map[ret];
6877         rule->hash_map[ret] = NULL;
6878
6879         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6880         rte_free(tunnel_filter);
6881
6882         return 0;
6883 }
6884
6885 int
6886 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6887                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6888                         uint8_t add)
6889 {
6890         uint16_t ip_type;
6891         uint32_t ipv4_addr;
6892         uint8_t i, tun_type = 0;
6893         /* internal varialbe to convert ipv6 byte order */
6894         uint32_t convert_ipv6[4];
6895         int val, ret = 0;
6896         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6897         struct i40e_vsi *vsi = pf->main_vsi;
6898         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6899         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6900         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6901         struct i40e_tunnel_filter *tunnel, *node;
6902         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6903
6904         cld_filter = rte_zmalloc("tunnel_filter",
6905                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6906         0);
6907
6908         if (NULL == cld_filter) {
6909                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6910                 return -ENOMEM;
6911         }
6912         pfilter = cld_filter;
6913
6914         ether_addr_copy(&tunnel_filter->outer_mac,
6915                         (struct ether_addr *)&pfilter->element.outer_mac);
6916         ether_addr_copy(&tunnel_filter->inner_mac,
6917                         (struct ether_addr *)&pfilter->element.inner_mac);
6918
6919         pfilter->element.inner_vlan =
6920                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6921         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6922                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6923                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6924                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6925                                 &rte_cpu_to_le_32(ipv4_addr),
6926                                 sizeof(pfilter->element.ipaddr.v4.data));
6927         } else {
6928                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6929                 for (i = 0; i < 4; i++) {
6930                         convert_ipv6[i] =
6931                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6932                 }
6933                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6934                            &convert_ipv6,
6935                            sizeof(pfilter->element.ipaddr.v6.data));
6936         }
6937
6938         /* check tunneled type */
6939         switch (tunnel_filter->tunnel_type) {
6940         case RTE_TUNNEL_TYPE_VXLAN:
6941                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6942                 break;
6943         case RTE_TUNNEL_TYPE_NVGRE:
6944                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6945                 break;
6946         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6947                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6948                 break;
6949         default:
6950                 /* Other tunnel types is not supported. */
6951                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6952                 rte_free(cld_filter);
6953                 return -EINVAL;
6954         }
6955
6956         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6957                                        &pfilter->element.flags);
6958         if (val < 0) {
6959                 rte_free(cld_filter);
6960                 return -EINVAL;
6961         }
6962
6963         pfilter->element.flags |= rte_cpu_to_le_16(
6964                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6965                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6966         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6967         pfilter->element.queue_number =
6968                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6969
6970         /* Check if there is the filter in SW list */
6971         memset(&check_filter, 0, sizeof(check_filter));
6972         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6973         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6974         if (add && node) {
6975                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6976                 return -EINVAL;
6977         }
6978
6979         if (!add && !node) {
6980                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6981                 return -EINVAL;
6982         }
6983
6984         if (add) {
6985                 ret = i40e_aq_add_cloud_filters(hw,
6986                                         vsi->seid, &cld_filter->element, 1);
6987                 if (ret < 0) {
6988                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6989                         return -ENOTSUP;
6990                 }
6991                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6992                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6993                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6994         } else {
6995                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6996                                                    &cld_filter->element, 1);
6997                 if (ret < 0) {
6998                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6999                         return -ENOTSUP;
7000                 }
7001                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7002         }
7003
7004         rte_free(cld_filter);
7005         return ret;
7006 }
7007
7008 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7009 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7010 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7011 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7012 #define I40E_TR_GRE_KEY_MASK                    0x400
7013 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7014 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7015
7016 static enum
7017 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7018 {
7019         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7020         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7021         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7022         enum i40e_status_code status = I40E_SUCCESS;
7023
7024         memset(&filter_replace, 0,
7025                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7026         memset(&filter_replace_buf, 0,
7027                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7028
7029         /* create L1 filter */
7030         filter_replace.old_filter_type =
7031                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7032         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7033         filter_replace.tr_bit = 0;
7034
7035         /* Prepare the buffer, 3 entries */
7036         filter_replace_buf.data[0] =
7037                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7038         filter_replace_buf.data[0] |=
7039                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7040         filter_replace_buf.data[2] = 0xFF;
7041         filter_replace_buf.data[3] = 0xFF;
7042         filter_replace_buf.data[4] =
7043                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7044         filter_replace_buf.data[4] |=
7045                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7046         filter_replace_buf.data[7] = 0xF0;
7047         filter_replace_buf.data[8]
7048                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7049         filter_replace_buf.data[8] |=
7050                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7051         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7052                 I40E_TR_GENEVE_KEY_MASK |
7053                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7054         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7055                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7056                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7057
7058         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7059                                                &filter_replace_buf);
7060         return status;
7061 }
7062
7063 static enum
7064 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7065 {
7066         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7067         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7068         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7069         enum i40e_status_code status = I40E_SUCCESS;
7070
7071         /* For MPLSoUDP */
7072         memset(&filter_replace, 0,
7073                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7074         memset(&filter_replace_buf, 0,
7075                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7076         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7077                 I40E_AQC_MIRROR_CLOUD_FILTER;
7078         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7079         filter_replace.new_filter_type =
7080                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7081         /* Prepare the buffer, 2 entries */
7082         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7083         filter_replace_buf.data[0] |=
7084                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7085         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7086         filter_replace_buf.data[4] |=
7087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7088         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7089                                                &filter_replace_buf);
7090         if (status < 0)
7091                 return status;
7092
7093         /* For MPLSoGRE */
7094         memset(&filter_replace, 0,
7095                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7096         memset(&filter_replace_buf, 0,
7097                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7098
7099         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7100                 I40E_AQC_MIRROR_CLOUD_FILTER;
7101         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7102         filter_replace.new_filter_type =
7103                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7104         /* Prepare the buffer, 2 entries */
7105         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7106         filter_replace_buf.data[0] |=
7107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7108         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7109         filter_replace_buf.data[4] |=
7110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7111
7112         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7113                                                &filter_replace_buf);
7114         return status;
7115 }
7116
7117 int
7118 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7119                       struct i40e_tunnel_filter_conf *tunnel_filter,
7120                       uint8_t add)
7121 {
7122         uint16_t ip_type;
7123         uint32_t ipv4_addr;
7124         uint8_t i, tun_type = 0;
7125         /* internal variable to convert ipv6 byte order */
7126         uint32_t convert_ipv6[4];
7127         int val, ret = 0;
7128         struct i40e_pf_vf *vf = NULL;
7129         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7130         struct i40e_vsi *vsi;
7131         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7132         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7133         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7134         struct i40e_tunnel_filter *tunnel, *node;
7135         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7136         uint32_t teid_le;
7137         bool big_buffer = 0;
7138
7139         cld_filter = rte_zmalloc("tunnel_filter",
7140                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7141                          0);
7142
7143         if (cld_filter == NULL) {
7144                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7145                 return -ENOMEM;
7146         }
7147         pfilter = cld_filter;
7148
7149         ether_addr_copy(&tunnel_filter->outer_mac,
7150                         (struct ether_addr *)&pfilter->element.outer_mac);
7151         ether_addr_copy(&tunnel_filter->inner_mac,
7152                         (struct ether_addr *)&pfilter->element.inner_mac);
7153
7154         pfilter->element.inner_vlan =
7155                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7156         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7157                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7158                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7159                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7160                                 &rte_cpu_to_le_32(ipv4_addr),
7161                                 sizeof(pfilter->element.ipaddr.v4.data));
7162         } else {
7163                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7164                 for (i = 0; i < 4; i++) {
7165                         convert_ipv6[i] =
7166                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7167                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7168                 }
7169                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7170                            &convert_ipv6,
7171                            sizeof(pfilter->element.ipaddr.v6.data));
7172         }
7173
7174         /* check tunneled type */
7175         switch (tunnel_filter->tunnel_type) {
7176         case I40E_TUNNEL_TYPE_VXLAN:
7177                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7178                 break;
7179         case I40E_TUNNEL_TYPE_NVGRE:
7180                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7181                 break;
7182         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7183                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7184                 break;
7185         case I40E_TUNNEL_TYPE_MPLSoUDP:
7186                 if (!pf->mpls_replace_flag) {
7187                         i40e_replace_mpls_l1_filter(pf);
7188                         i40e_replace_mpls_cloud_filter(pf);
7189                         pf->mpls_replace_flag = 1;
7190                 }
7191                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7192                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7193                         teid_le >> 4;
7194                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7195                         (teid_le & 0xF) << 12;
7196                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7197                         0x40;
7198                 big_buffer = 1;
7199                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7200                 break;
7201         case I40E_TUNNEL_TYPE_MPLSoGRE:
7202                 if (!pf->mpls_replace_flag) {
7203                         i40e_replace_mpls_l1_filter(pf);
7204                         i40e_replace_mpls_cloud_filter(pf);
7205                         pf->mpls_replace_flag = 1;
7206                 }
7207                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7208                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7209                         teid_le >> 4;
7210                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7211                         (teid_le & 0xF) << 12;
7212                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7213                         0x0;
7214                 big_buffer = 1;
7215                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7216                 break;
7217         case I40E_TUNNEL_TYPE_QINQ:
7218                 if (!pf->qinq_replace_flag) {
7219                         ret = i40e_cloud_filter_qinq_create(pf);
7220                         if (ret < 0)
7221                                 PMD_DRV_LOG(DEBUG,
7222                                             "QinQ tunnel filter already created.");
7223                         pf->qinq_replace_flag = 1;
7224                 }
7225                 /*      Add in the General fields the values of
7226                  *      the Outer and Inner VLAN
7227                  *      Big Buffer should be set, see changes in
7228                  *      i40e_aq_add_cloud_filters
7229                  */
7230                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7231                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7232                 big_buffer = 1;
7233                 break;
7234         default:
7235                 /* Other tunnel types is not supported. */
7236                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7237                 rte_free(cld_filter);
7238                 return -EINVAL;
7239         }
7240
7241         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7242                 pfilter->element.flags =
7243                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7244         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7245                 pfilter->element.flags =
7246                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7247         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7248                 pfilter->element.flags |=
7249                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7250         else {
7251                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7252                                                 &pfilter->element.flags);
7253                 if (val < 0) {
7254                         rte_free(cld_filter);
7255                         return -EINVAL;
7256                 }
7257         }
7258
7259         pfilter->element.flags |= rte_cpu_to_le_16(
7260                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7261                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7262         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7263         pfilter->element.queue_number =
7264                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7265
7266         if (!tunnel_filter->is_to_vf)
7267                 vsi = pf->main_vsi;
7268         else {
7269                 if (tunnel_filter->vf_id >= pf->vf_num) {
7270                         PMD_DRV_LOG(ERR, "Invalid argument.");
7271                         return -EINVAL;
7272                 }
7273                 vf = &pf->vfs[tunnel_filter->vf_id];
7274                 vsi = vf->vsi;
7275         }
7276
7277         /* Check if there is the filter in SW list */
7278         memset(&check_filter, 0, sizeof(check_filter));
7279         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7280         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7281         check_filter.vf_id = tunnel_filter->vf_id;
7282         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7283         if (add && node) {
7284                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7285                 return -EINVAL;
7286         }
7287
7288         if (!add && !node) {
7289                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7290                 return -EINVAL;
7291         }
7292
7293         if (add) {
7294                 if (big_buffer)
7295                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7296                                                    vsi->seid, cld_filter, 1);
7297                 else
7298                         ret = i40e_aq_add_cloud_filters(hw,
7299                                         vsi->seid, &cld_filter->element, 1);
7300                 if (ret < 0) {
7301                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7302                         return -ENOTSUP;
7303                 }
7304                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7305                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7306                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7307         } else {
7308                 if (big_buffer)
7309                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7310                                 hw, vsi->seid, cld_filter, 1);
7311                 else
7312                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7313                                                    &cld_filter->element, 1);
7314                 if (ret < 0) {
7315                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7316                         return -ENOTSUP;
7317                 }
7318                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7319         }
7320
7321         rte_free(cld_filter);
7322         return ret;
7323 }
7324
7325 static int
7326 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7327 {
7328         uint8_t i;
7329
7330         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7331                 if (pf->vxlan_ports[i] == port)
7332                         return i;
7333         }
7334
7335         return -1;
7336 }
7337
7338 static int
7339 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7340 {
7341         int  idx, ret;
7342         uint8_t filter_idx;
7343         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7344
7345         idx = i40e_get_vxlan_port_idx(pf, port);
7346
7347         /* Check if port already exists */
7348         if (idx >= 0) {
7349                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7350                 return -EINVAL;
7351         }
7352
7353         /* Now check if there is space to add the new port */
7354         idx = i40e_get_vxlan_port_idx(pf, 0);
7355         if (idx < 0) {
7356                 PMD_DRV_LOG(ERR,
7357                         "Maximum number of UDP ports reached, not adding port %d",
7358                         port);
7359                 return -ENOSPC;
7360         }
7361
7362         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7363                                         &filter_idx, NULL);
7364         if (ret < 0) {
7365                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7366                 return -1;
7367         }
7368
7369         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7370                          port,  filter_idx);
7371
7372         /* New port: add it and mark its index in the bitmap */
7373         pf->vxlan_ports[idx] = port;
7374         pf->vxlan_bitmap |= (1 << idx);
7375
7376         if (!(pf->flags & I40E_FLAG_VXLAN))
7377                 pf->flags |= I40E_FLAG_VXLAN;
7378
7379         return 0;
7380 }
7381
7382 static int
7383 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7384 {
7385         int idx;
7386         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7387
7388         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7389                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7390                 return -EINVAL;
7391         }
7392
7393         idx = i40e_get_vxlan_port_idx(pf, port);
7394
7395         if (idx < 0) {
7396                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7397                 return -EINVAL;
7398         }
7399
7400         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7401                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7402                 return -1;
7403         }
7404
7405         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7406                         port, idx);
7407
7408         pf->vxlan_ports[idx] = 0;
7409         pf->vxlan_bitmap &= ~(1 << idx);
7410
7411         if (!pf->vxlan_bitmap)
7412                 pf->flags &= ~I40E_FLAG_VXLAN;
7413
7414         return 0;
7415 }
7416
7417 /* Add UDP tunneling port */
7418 static int
7419 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7420                              struct rte_eth_udp_tunnel *udp_tunnel)
7421 {
7422         int ret = 0;
7423         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7424
7425         if (udp_tunnel == NULL)
7426                 return -EINVAL;
7427
7428         switch (udp_tunnel->prot_type) {
7429         case RTE_TUNNEL_TYPE_VXLAN:
7430                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7431                 break;
7432
7433         case RTE_TUNNEL_TYPE_GENEVE:
7434         case RTE_TUNNEL_TYPE_TEREDO:
7435                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7436                 ret = -1;
7437                 break;
7438
7439         default:
7440                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7441                 ret = -1;
7442                 break;
7443         }
7444
7445         return ret;
7446 }
7447
7448 /* Remove UDP tunneling port */
7449 static int
7450 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7451                              struct rte_eth_udp_tunnel *udp_tunnel)
7452 {
7453         int ret = 0;
7454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7455
7456         if (udp_tunnel == NULL)
7457                 return -EINVAL;
7458
7459         switch (udp_tunnel->prot_type) {
7460         case RTE_TUNNEL_TYPE_VXLAN:
7461                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7462                 break;
7463         case RTE_TUNNEL_TYPE_GENEVE:
7464         case RTE_TUNNEL_TYPE_TEREDO:
7465                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7466                 ret = -1;
7467                 break;
7468         default:
7469                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7470                 ret = -1;
7471                 break;
7472         }
7473
7474         return ret;
7475 }
7476
7477 /* Calculate the maximum number of contiguous PF queues that are configured */
7478 static int
7479 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7480 {
7481         struct rte_eth_dev_data *data = pf->dev_data;
7482         int i, num;
7483         struct i40e_rx_queue *rxq;
7484
7485         num = 0;
7486         for (i = 0; i < pf->lan_nb_qps; i++) {
7487                 rxq = data->rx_queues[i];
7488                 if (rxq && rxq->q_set)
7489                         num++;
7490                 else
7491                         break;
7492         }
7493
7494         return num;
7495 }
7496
7497 /* Configure RSS */
7498 static int
7499 i40e_pf_config_rss(struct i40e_pf *pf)
7500 {
7501         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7502         struct rte_eth_rss_conf rss_conf;
7503         uint32_t i, lut = 0;
7504         uint16_t j, num;
7505
7506         /*
7507          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7508          * It's necessary to calulate the actual PF queues that are configured.
7509          */
7510         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7511                 num = i40e_pf_calc_configured_queues_num(pf);
7512         else
7513                 num = pf->dev_data->nb_rx_queues;
7514
7515         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7516         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7517                         num);
7518
7519         if (num == 0) {
7520                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7521                 return -ENOTSUP;
7522         }
7523
7524         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7525                 if (j == num)
7526                         j = 0;
7527                 lut = (lut << 8) | (j & ((0x1 <<
7528                         hw->func_caps.rss_table_entry_width) - 1));
7529                 if ((i & 3) == 3)
7530                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7531         }
7532
7533         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7534         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7535                 i40e_pf_disable_rss(pf);
7536                 return 0;
7537         }
7538         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7539                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7540                 /* Random default keys */
7541                 static uint32_t rss_key_default[] = {0x6b793944,
7542                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7543                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7544                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7545
7546                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7547                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7548                                                         sizeof(uint32_t);
7549         }
7550
7551         return i40e_hw_rss_hash_set(pf, &rss_conf);
7552 }
7553
7554 static int
7555 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7556                                struct rte_eth_tunnel_filter_conf *filter)
7557 {
7558         if (pf == NULL || filter == NULL) {
7559                 PMD_DRV_LOG(ERR, "Invalid parameter");
7560                 return -EINVAL;
7561         }
7562
7563         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7564                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7565                 return -EINVAL;
7566         }
7567
7568         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7569                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7570                 return -EINVAL;
7571         }
7572
7573         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7574                 (is_zero_ether_addr(&filter->outer_mac))) {
7575                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7576                 return -EINVAL;
7577         }
7578
7579         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7580                 (is_zero_ether_addr(&filter->inner_mac))) {
7581                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7582                 return -EINVAL;
7583         }
7584
7585         return 0;
7586 }
7587
7588 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7589 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7590 static int
7591 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7592 {
7593         uint32_t val, reg;
7594         int ret = -EINVAL;
7595
7596         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7597         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7598
7599         if (len == 3) {
7600                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7601         } else if (len == 4) {
7602                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7603         } else {
7604                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7605                 return ret;
7606         }
7607
7608         if (reg != val) {
7609                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7610                                                    reg, NULL);
7611                 if (ret != 0)
7612                         return ret;
7613         } else {
7614                 ret = 0;
7615         }
7616         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7617                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7618
7619         return ret;
7620 }
7621
7622 static int
7623 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7624 {
7625         int ret = -EINVAL;
7626
7627         if (!hw || !cfg)
7628                 return -EINVAL;
7629
7630         switch (cfg->cfg_type) {
7631         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7632                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7633                 break;
7634         default:
7635                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7636                 break;
7637         }
7638
7639         return ret;
7640 }
7641
7642 static int
7643 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7644                                enum rte_filter_op filter_op,
7645                                void *arg)
7646 {
7647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7648         int ret = I40E_ERR_PARAM;
7649
7650         switch (filter_op) {
7651         case RTE_ETH_FILTER_SET:
7652                 ret = i40e_dev_global_config_set(hw,
7653                         (struct rte_eth_global_cfg *)arg);
7654                 break;
7655         default:
7656                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7657                 break;
7658         }
7659
7660         return ret;
7661 }
7662
7663 static int
7664 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7665                           enum rte_filter_op filter_op,
7666                           void *arg)
7667 {
7668         struct rte_eth_tunnel_filter_conf *filter;
7669         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7670         int ret = I40E_SUCCESS;
7671
7672         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7673
7674         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7675                 return I40E_ERR_PARAM;
7676
7677         switch (filter_op) {
7678         case RTE_ETH_FILTER_NOP:
7679                 if (!(pf->flags & I40E_FLAG_VXLAN))
7680                         ret = I40E_NOT_SUPPORTED;
7681                 break;
7682         case RTE_ETH_FILTER_ADD:
7683                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7684                 break;
7685         case RTE_ETH_FILTER_DELETE:
7686                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7687                 break;
7688         default:
7689                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7690                 ret = I40E_ERR_PARAM;
7691                 break;
7692         }
7693
7694         return ret;
7695 }
7696
7697 static int
7698 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7699 {
7700         int ret = 0;
7701         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7702
7703         /* RSS setup */
7704         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7705                 ret = i40e_pf_config_rss(pf);
7706         else
7707                 i40e_pf_disable_rss(pf);
7708
7709         return ret;
7710 }
7711
7712 /* Get the symmetric hash enable configurations per port */
7713 static void
7714 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7715 {
7716         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7717
7718         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7719 }
7720
7721 /* Set the symmetric hash enable configurations per port */
7722 static void
7723 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7724 {
7725         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7726
7727         if (enable > 0) {
7728                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7729                         PMD_DRV_LOG(INFO,
7730                                 "Symmetric hash has already been enabled");
7731                         return;
7732                 }
7733                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7734         } else {
7735                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7736                         PMD_DRV_LOG(INFO,
7737                                 "Symmetric hash has already been disabled");
7738                         return;
7739                 }
7740                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7741         }
7742         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7743         I40E_WRITE_FLUSH(hw);
7744 }
7745
7746 /*
7747  * Get global configurations of hash function type and symmetric hash enable
7748  * per flow type (pctype). Note that global configuration means it affects all
7749  * the ports on the same NIC.
7750  */
7751 static int
7752 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7753                                    struct rte_eth_hash_global_conf *g_cfg)
7754 {
7755         uint32_t reg, mask = I40E_FLOW_TYPES;
7756         uint16_t i;
7757         enum i40e_filter_pctype pctype;
7758
7759         memset(g_cfg, 0, sizeof(*g_cfg));
7760         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7761         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7762                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7763         else
7764                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7765         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7766                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7767
7768         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7769                 if (!(mask & (1UL << i)))
7770                         continue;
7771                 mask &= ~(1UL << i);
7772                 /* Bit set indicats the coresponding flow type is supported */
7773                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7774                 /* if flowtype is invalid, continue */
7775                 if (!I40E_VALID_FLOW(i))
7776                         continue;
7777                 pctype = i40e_flowtype_to_pctype(i);
7778                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7779                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7780                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7781         }
7782
7783         return 0;
7784 }
7785
7786 static int
7787 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7788 {
7789         uint32_t i;
7790         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7791
7792         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7793                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7794                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7795                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7796                                                 g_cfg->hash_func);
7797                 return -EINVAL;
7798         }
7799
7800         /*
7801          * As i40e supports less than 32 flow types, only first 32 bits need to
7802          * be checked.
7803          */
7804         mask0 = g_cfg->valid_bit_mask[0];
7805         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7806                 if (i == 0) {
7807                         /* Check if any unsupported flow type configured */
7808                         if ((mask0 | i40e_mask) ^ i40e_mask)
7809                                 goto mask_err;
7810                 } else {
7811                         if (g_cfg->valid_bit_mask[i])
7812                                 goto mask_err;
7813                 }
7814         }
7815
7816         return 0;
7817
7818 mask_err:
7819         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7820
7821         return -EINVAL;
7822 }
7823
7824 /*
7825  * Set global configurations of hash function type and symmetric hash enable
7826  * per flow type (pctype). Note any modifying global configuration will affect
7827  * all the ports on the same NIC.
7828  */
7829 static int
7830 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7831                                    struct rte_eth_hash_global_conf *g_cfg)
7832 {
7833         int ret;
7834         uint16_t i;
7835         uint32_t reg;
7836         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7837         enum i40e_filter_pctype pctype;
7838
7839         /* Check the input parameters */
7840         ret = i40e_hash_global_config_check(g_cfg);
7841         if (ret < 0)
7842                 return ret;
7843
7844         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7845                 if (!(mask0 & (1UL << i)))
7846                         continue;
7847                 mask0 &= ~(1UL << i);
7848                 /* if flowtype is invalid, continue */
7849                 if (!I40E_VALID_FLOW(i))
7850                         continue;
7851                 pctype = i40e_flowtype_to_pctype(i);
7852                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7853                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7854                 if (hw->mac.type == I40E_MAC_X722) {
7855                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7856                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7857                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7858                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7859                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7860                                   reg);
7861                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7862                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7863                                   reg);
7864                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7865                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7866                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7867                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7868                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7869                                   reg);
7870                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7871                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7872                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7873                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7874                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7875                                   reg);
7876                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7877                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7878                                   reg);
7879                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7880                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7881                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7882                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7883                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7884                                   reg);
7885                         } else {
7886                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7887                                   reg);
7888                         }
7889                 } else {
7890                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7891                 }
7892         }
7893
7894         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7895         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7896                 /* Toeplitz */
7897                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7898                         PMD_DRV_LOG(DEBUG,
7899                                 "Hash function already set to Toeplitz");
7900                         goto out;
7901                 }
7902                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7903         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7904                 /* Simple XOR */
7905                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7906                         PMD_DRV_LOG(DEBUG,
7907                                 "Hash function already set to Simple XOR");
7908                         goto out;
7909                 }
7910                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7911         } else
7912                 /* Use the default, and keep it as it is */
7913                 goto out;
7914
7915         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7916
7917 out:
7918         I40E_WRITE_FLUSH(hw);
7919
7920         return 0;
7921 }
7922
7923 /**
7924  * Valid input sets for hash and flow director filters per PCTYPE
7925  */
7926 static uint64_t
7927 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7928                 enum rte_filter_type filter)
7929 {
7930         uint64_t valid;
7931
7932         static const uint64_t valid_hash_inset_table[] = {
7933                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7934                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7935                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7936                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7937                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7938                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7939                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7940                         I40E_INSET_FLEX_PAYLOAD,
7941                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7942                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7943                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7944                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7945                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7946                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7947                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7948                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7949                         I40E_INSET_FLEX_PAYLOAD,
7950                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7951                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7952                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7953                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7954                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7955                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7956                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7957                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7958                         I40E_INSET_FLEX_PAYLOAD,
7959                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7960                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7961                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7962                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7963                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7964                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7965                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7966                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7967                         I40E_INSET_FLEX_PAYLOAD,
7968                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7969                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7970                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7971                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7972                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7973                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7974                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7975                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7976                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7977                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7978                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7979                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7980                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7981                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7982                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7983                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7984                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7985                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7986                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7987                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7988                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7989                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7990                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7991                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7992                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7993                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7994                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7995                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7996                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7997                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7998                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7999                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8000                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8001                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8002                         I40E_INSET_FLEX_PAYLOAD,
8003                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8004                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8005                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8006                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8007                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8008                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8009                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8010                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8011                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8012                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8013                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8014                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8015                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8016                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8017                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8018                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8019                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8020                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8021                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8022                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8023                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8024                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8025                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8026                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8027                         I40E_INSET_FLEX_PAYLOAD,
8028                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8029                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8030                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8031                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8032                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8033                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8034                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8035                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8036                         I40E_INSET_FLEX_PAYLOAD,
8037                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8038                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8039                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8040                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8041                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8042                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8043                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8044                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8045                         I40E_INSET_FLEX_PAYLOAD,
8046                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8047                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8048                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8049                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8050                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8051                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8052                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8053                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8054                         I40E_INSET_FLEX_PAYLOAD,
8055                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8056                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8057                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8058                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8059                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8060                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8061                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8062                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8063                         I40E_INSET_FLEX_PAYLOAD,
8064                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8065                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8066                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8067                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8068                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8069                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8070                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8071                         I40E_INSET_FLEX_PAYLOAD,
8072                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8076                         I40E_INSET_FLEX_PAYLOAD,
8077         };
8078
8079         /**
8080          * Flow director supports only fields defined in
8081          * union rte_eth_fdir_flow.
8082          */
8083         static const uint64_t valid_fdir_inset_table[] = {
8084                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8085                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8086                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8087                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8088                 I40E_INSET_IPV4_TTL,
8089                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8090                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8091                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8092                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8093                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8094                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8095                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8096                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8097                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8098                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8099                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8100                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8101                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8102                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8103                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8104                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8105                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8106                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8107                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8108                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8109                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8110                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8111                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8112                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8113                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8114                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8115                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8116                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8117                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8118                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8119                 I40E_INSET_SCTP_VT,
8120                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8121                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8122                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8123                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8124                 I40E_INSET_IPV4_TTL,
8125                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8126                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8127                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8128                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8129                 I40E_INSET_IPV6_HOP_LIMIT,
8130                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8131                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8132                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8133                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8134                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8135                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8136                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8137                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8138                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8139                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8140                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8141                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8142                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8143                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8144                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8145                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8146                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8147                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8148                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8149                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8150                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8151                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8152                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8153                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8154                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8155                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8156                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8157                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8158                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8159                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8160                 I40E_INSET_SCTP_VT,
8161                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8162                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8163                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8164                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8165                 I40E_INSET_IPV6_HOP_LIMIT,
8166                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8167                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8168                 I40E_INSET_LAST_ETHER_TYPE,
8169         };
8170
8171         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8172                 return 0;
8173         if (filter == RTE_ETH_FILTER_HASH)
8174                 valid = valid_hash_inset_table[pctype];
8175         else
8176                 valid = valid_fdir_inset_table[pctype];
8177
8178         return valid;
8179 }
8180
8181 /**
8182  * Validate if the input set is allowed for a specific PCTYPE
8183  */
8184 static int
8185 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8186                 enum rte_filter_type filter, uint64_t inset)
8187 {
8188         uint64_t valid;
8189
8190         valid = i40e_get_valid_input_set(pctype, filter);
8191         if (inset & (~valid))
8192                 return -EINVAL;
8193
8194         return 0;
8195 }
8196
8197 /* default input set fields combination per pctype */
8198 uint64_t
8199 i40e_get_default_input_set(uint16_t pctype)
8200 {
8201         static const uint64_t default_inset_table[] = {
8202                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8203                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8204                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8205                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8206                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8207                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8208                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8209                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8210                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8211                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8212                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8213                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8214                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8215                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8216                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8217                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8218                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8219                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8220                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8221                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8222                         I40E_INSET_SCTP_VT,
8223                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8224                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8225                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8226                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8227                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8228                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8229                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8230                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8231                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8232                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8233                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8234                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8235                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8236                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8237                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8238                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8239                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8240                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8241                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8242                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8243                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8244                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8245                         I40E_INSET_SCTP_VT,
8246                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8247                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8248                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8249                         I40E_INSET_LAST_ETHER_TYPE,
8250         };
8251
8252         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8253                 return 0;
8254
8255         return default_inset_table[pctype];
8256 }
8257
8258 /**
8259  * Parse the input set from index to logical bit masks
8260  */
8261 static int
8262 i40e_parse_input_set(uint64_t *inset,
8263                      enum i40e_filter_pctype pctype,
8264                      enum rte_eth_input_set_field *field,
8265                      uint16_t size)
8266 {
8267         uint16_t i, j;
8268         int ret = -EINVAL;
8269
8270         static const struct {
8271                 enum rte_eth_input_set_field field;
8272                 uint64_t inset;
8273         } inset_convert_table[] = {
8274                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8275                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8276                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8277                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8278                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8279                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8280                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8281                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8282                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8283                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8284                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8285                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8286                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8287                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8288                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8289                         I40E_INSET_IPV6_NEXT_HDR},
8290                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8291                         I40E_INSET_IPV6_HOP_LIMIT},
8292                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8293                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8294                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8295                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8296                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8297                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8298                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8299                         I40E_INSET_SCTP_VT},
8300                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8301                         I40E_INSET_TUNNEL_DMAC},
8302                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8303                         I40E_INSET_VLAN_TUNNEL},
8304                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8305                         I40E_INSET_TUNNEL_ID},
8306                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8307                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8308                         I40E_INSET_FLEX_PAYLOAD_W1},
8309                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8310                         I40E_INSET_FLEX_PAYLOAD_W2},
8311                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8312                         I40E_INSET_FLEX_PAYLOAD_W3},
8313                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8314                         I40E_INSET_FLEX_PAYLOAD_W4},
8315                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8316                         I40E_INSET_FLEX_PAYLOAD_W5},
8317                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8318                         I40E_INSET_FLEX_PAYLOAD_W6},
8319                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8320                         I40E_INSET_FLEX_PAYLOAD_W7},
8321                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8322                         I40E_INSET_FLEX_PAYLOAD_W8},
8323         };
8324
8325         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8326                 return ret;
8327
8328         /* Only one item allowed for default or all */
8329         if (size == 1) {
8330                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8331                         *inset = i40e_get_default_input_set(pctype);
8332                         return 0;
8333                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8334                         *inset = I40E_INSET_NONE;
8335                         return 0;
8336                 }
8337         }
8338
8339         for (i = 0, *inset = 0; i < size; i++) {
8340                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8341                         if (field[i] == inset_convert_table[j].field) {
8342                                 *inset |= inset_convert_table[j].inset;
8343                                 break;
8344                         }
8345                 }
8346
8347                 /* It contains unsupported input set, return immediately */
8348                 if (j == RTE_DIM(inset_convert_table))
8349                         return ret;
8350         }
8351
8352         return 0;
8353 }
8354
8355 /**
8356  * Translate the input set from bit masks to register aware bit masks
8357  * and vice versa
8358  */
8359 static uint64_t
8360 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8361 {
8362         uint64_t val = 0;
8363         uint16_t i;
8364
8365         struct inset_map {
8366                 uint64_t inset;
8367                 uint64_t inset_reg;
8368         };
8369
8370         static const struct inset_map inset_map_common[] = {
8371                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8372                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8373                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8374                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8375                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8376                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8377                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8378                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8379                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8380                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8381                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8382                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8383                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8384                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8385                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8386                 {I40E_INSET_TUNNEL_DMAC,
8387                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8388                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8389                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8390                 {I40E_INSET_TUNNEL_SRC_PORT,
8391                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8392                 {I40E_INSET_TUNNEL_DST_PORT,
8393                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8394                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8395                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8396                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8397                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8398                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8399                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8400                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8401                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8402                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8403         };
8404
8405     /* some different registers map in x722*/
8406         static const struct inset_map inset_map_diff_x722[] = {
8407                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8408                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8409                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8410                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8411         };
8412
8413         static const struct inset_map inset_map_diff_not_x722[] = {
8414                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8415                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8416                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8417                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8418         };
8419
8420         if (input == 0)
8421                 return val;
8422
8423         /* Translate input set to register aware inset */
8424         if (type == I40E_MAC_X722) {
8425                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8426                         if (input & inset_map_diff_x722[i].inset)
8427                                 val |= inset_map_diff_x722[i].inset_reg;
8428                 }
8429         } else {
8430                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8431                         if (input & inset_map_diff_not_x722[i].inset)
8432                                 val |= inset_map_diff_not_x722[i].inset_reg;
8433                 }
8434         }
8435
8436         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8437                 if (input & inset_map_common[i].inset)
8438                         val |= inset_map_common[i].inset_reg;
8439         }
8440
8441         return val;
8442 }
8443
8444 static int
8445 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8446 {
8447         uint8_t i, idx = 0;
8448         uint64_t inset_need_mask = inset;
8449
8450         static const struct {
8451                 uint64_t inset;
8452                 uint32_t mask;
8453         } inset_mask_map[] = {
8454                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8455                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8456                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8457                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8458                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8459                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8460                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8461                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8462         };
8463
8464         if (!inset || !mask || !nb_elem)
8465                 return 0;
8466
8467         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8468                 /* Clear the inset bit, if no MASK is required,
8469                  * for example proto + ttl
8470                  */
8471                 if ((inset & inset_mask_map[i].inset) ==
8472                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8473                         inset_need_mask &= ~inset_mask_map[i].inset;
8474                 if (!inset_need_mask)
8475                         return 0;
8476         }
8477         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8478                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8479                     inset_mask_map[i].inset) {
8480                         if (idx >= nb_elem) {
8481                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8482                                 return -EINVAL;
8483                         }
8484                         mask[idx] = inset_mask_map[i].mask;
8485                         idx++;
8486                 }
8487         }
8488
8489         return idx;
8490 }
8491
8492 static void
8493 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8494 {
8495         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8496
8497         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8498         if (reg != val)
8499                 i40e_write_rx_ctl(hw, addr, val);
8500         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8501                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8502 }
8503
8504 static void
8505 i40e_filter_input_set_init(struct i40e_pf *pf)
8506 {
8507         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8508         enum i40e_filter_pctype pctype;
8509         uint64_t input_set, inset_reg;
8510         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8511         int num, i;
8512
8513         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8514              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8515                 if (hw->mac.type == I40E_MAC_X722) {
8516                         if (!I40E_VALID_PCTYPE_X722(pctype))
8517                                 continue;
8518                 } else {
8519                         if (!I40E_VALID_PCTYPE(pctype))
8520                                 continue;
8521                 }
8522
8523                 input_set = i40e_get_default_input_set(pctype);
8524
8525                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8526                                                    I40E_INSET_MASK_NUM_REG);
8527                 if (num < 0)
8528                         return;
8529                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8530                                         input_set);
8531
8532                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8533                                       (uint32_t)(inset_reg & UINT32_MAX));
8534                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8535                                      (uint32_t)((inset_reg >>
8536                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8537                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8538                                       (uint32_t)(inset_reg & UINT32_MAX));
8539                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8540                                      (uint32_t)((inset_reg >>
8541                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8542
8543                 for (i = 0; i < num; i++) {
8544                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8545                                              mask_reg[i]);
8546                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8547                                              mask_reg[i]);
8548                 }
8549                 /*clear unused mask registers of the pctype */
8550                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8551                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8552                                              0);
8553                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8554                                              0);
8555                 }
8556                 I40E_WRITE_FLUSH(hw);
8557
8558                 /* store the default input set */
8559                 pf->hash_input_set[pctype] = input_set;
8560                 pf->fdir.input_set[pctype] = input_set;
8561         }
8562 }
8563
8564 int
8565 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8566                          struct rte_eth_input_set_conf *conf)
8567 {
8568         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8569         enum i40e_filter_pctype pctype;
8570         uint64_t input_set, inset_reg = 0;
8571         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8572         int ret, i, num;
8573
8574         if (!conf) {
8575                 PMD_DRV_LOG(ERR, "Invalid pointer");
8576                 return -EFAULT;
8577         }
8578         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8579             conf->op != RTE_ETH_INPUT_SET_ADD) {
8580                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8581                 return -EINVAL;
8582         }
8583
8584         if (!I40E_VALID_FLOW(conf->flow_type)) {
8585                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8586                 return -EINVAL;
8587         }
8588
8589         if (hw->mac.type == I40E_MAC_X722) {
8590                 /* get translated pctype value in fd pctype register */
8591                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8592                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8593                         conf->flow_type)));
8594         } else
8595                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8596
8597         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8598                                    conf->inset_size);
8599         if (ret) {
8600                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8601                 return -EINVAL;
8602         }
8603         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8604                                     input_set) != 0) {
8605                 PMD_DRV_LOG(ERR, "Invalid input set");
8606                 return -EINVAL;
8607         }
8608         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8609                 /* get inset value in register */
8610                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8611                 inset_reg <<= I40E_32_BIT_WIDTH;
8612                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8613                 input_set |= pf->hash_input_set[pctype];
8614         }
8615         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8616                                            I40E_INSET_MASK_NUM_REG);
8617         if (num < 0)
8618                 return -EINVAL;
8619
8620         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8621
8622         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8623                               (uint32_t)(inset_reg & UINT32_MAX));
8624         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8625                              (uint32_t)((inset_reg >>
8626                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8627
8628         for (i = 0; i < num; i++)
8629                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8630                                      mask_reg[i]);
8631         /*clear unused mask registers of the pctype */
8632         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8633                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8634                                      0);
8635         I40E_WRITE_FLUSH(hw);
8636
8637         pf->hash_input_set[pctype] = input_set;
8638         return 0;
8639 }
8640
8641 int
8642 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8643                          struct rte_eth_input_set_conf *conf)
8644 {
8645         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8646         enum i40e_filter_pctype pctype;
8647         uint64_t input_set, inset_reg = 0;
8648         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8649         int ret, i, num;
8650
8651         if (!hw || !conf) {
8652                 PMD_DRV_LOG(ERR, "Invalid pointer");
8653                 return -EFAULT;
8654         }
8655         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8656             conf->op != RTE_ETH_INPUT_SET_ADD) {
8657                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8658                 return -EINVAL;
8659         }
8660
8661         if (!I40E_VALID_FLOW(conf->flow_type)) {
8662                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8663                 return -EINVAL;
8664         }
8665
8666         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8667
8668         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8669                                    conf->inset_size);
8670         if (ret) {
8671                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8672                 return -EINVAL;
8673         }
8674         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8675                                     input_set) != 0) {
8676                 PMD_DRV_LOG(ERR, "Invalid input set");
8677                 return -EINVAL;
8678         }
8679
8680         /* get inset value in register */
8681         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8682         inset_reg <<= I40E_32_BIT_WIDTH;
8683         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8684
8685         /* Can not change the inset reg for flex payload for fdir,
8686          * it is done by writing I40E_PRTQF_FD_FLXINSET
8687          * in i40e_set_flex_mask_on_pctype.
8688          */
8689         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8690                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8691         else
8692                 input_set |= pf->fdir.input_set[pctype];
8693         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8694                                            I40E_INSET_MASK_NUM_REG);
8695         if (num < 0)
8696                 return -EINVAL;
8697
8698         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8699
8700         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8701                               (uint32_t)(inset_reg & UINT32_MAX));
8702         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8703                              (uint32_t)((inset_reg >>
8704                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8705
8706         for (i = 0; i < num; i++)
8707                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8708                                      mask_reg[i]);
8709         /*clear unused mask registers of the pctype */
8710         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8711                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8712                                      0);
8713         I40E_WRITE_FLUSH(hw);
8714
8715         pf->fdir.input_set[pctype] = input_set;
8716         return 0;
8717 }
8718
8719 static int
8720 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8721 {
8722         int ret = 0;
8723
8724         if (!hw || !info) {
8725                 PMD_DRV_LOG(ERR, "Invalid pointer");
8726                 return -EFAULT;
8727         }
8728
8729         switch (info->info_type) {
8730         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8731                 i40e_get_symmetric_hash_enable_per_port(hw,
8732                                         &(info->info.enable));
8733                 break;
8734         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8735                 ret = i40e_get_hash_filter_global_config(hw,
8736                                 &(info->info.global_conf));
8737                 break;
8738         default:
8739                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8740                                                         info->info_type);
8741                 ret = -EINVAL;
8742                 break;
8743         }
8744
8745         return ret;
8746 }
8747
8748 static int
8749 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8750 {
8751         int ret = 0;
8752
8753         if (!hw || !info) {
8754                 PMD_DRV_LOG(ERR, "Invalid pointer");
8755                 return -EFAULT;
8756         }
8757
8758         switch (info->info_type) {
8759         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8760                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8761                 break;
8762         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8763                 ret = i40e_set_hash_filter_global_config(hw,
8764                                 &(info->info.global_conf));
8765                 break;
8766         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8767                 ret = i40e_hash_filter_inset_select(hw,
8768                                                &(info->info.input_set_conf));
8769                 break;
8770
8771         default:
8772                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8773                                                         info->info_type);
8774                 ret = -EINVAL;
8775                 break;
8776         }
8777
8778         return ret;
8779 }
8780
8781 /* Operations for hash function */
8782 static int
8783 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8784                       enum rte_filter_op filter_op,
8785                       void *arg)
8786 {
8787         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8788         int ret = 0;
8789
8790         switch (filter_op) {
8791         case RTE_ETH_FILTER_NOP:
8792                 break;
8793         case RTE_ETH_FILTER_GET:
8794                 ret = i40e_hash_filter_get(hw,
8795                         (struct rte_eth_hash_filter_info *)arg);
8796                 break;
8797         case RTE_ETH_FILTER_SET:
8798                 ret = i40e_hash_filter_set(hw,
8799                         (struct rte_eth_hash_filter_info *)arg);
8800                 break;
8801         default:
8802                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8803                                                                 filter_op);
8804                 ret = -ENOTSUP;
8805                 break;
8806         }
8807
8808         return ret;
8809 }
8810
8811 /* Convert ethertype filter structure */
8812 static int
8813 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8814                               struct i40e_ethertype_filter *filter)
8815 {
8816         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8817         filter->input.ether_type = input->ether_type;
8818         filter->flags = input->flags;
8819         filter->queue = input->queue;
8820
8821         return 0;
8822 }
8823
8824 /* Check if there exists the ehtertype filter */
8825 struct i40e_ethertype_filter *
8826 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8827                                 const struct i40e_ethertype_filter_input *input)
8828 {
8829         int ret;
8830
8831         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8832         if (ret < 0)
8833                 return NULL;
8834
8835         return ethertype_rule->hash_map[ret];
8836 }
8837
8838 /* Add ethertype filter in SW list */
8839 static int
8840 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8841                                 struct i40e_ethertype_filter *filter)
8842 {
8843         struct i40e_ethertype_rule *rule = &pf->ethertype;
8844         int ret;
8845
8846         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8847         if (ret < 0) {
8848                 PMD_DRV_LOG(ERR,
8849                             "Failed to insert ethertype filter"
8850                             " to hash table %d!",
8851                             ret);
8852                 return ret;
8853         }
8854         rule->hash_map[ret] = filter;
8855
8856         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8857
8858         return 0;
8859 }
8860
8861 /* Delete ethertype filter in SW list */
8862 int
8863 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8864                              struct i40e_ethertype_filter_input *input)
8865 {
8866         struct i40e_ethertype_rule *rule = &pf->ethertype;
8867         struct i40e_ethertype_filter *filter;
8868         int ret;
8869
8870         ret = rte_hash_del_key(rule->hash_table, input);
8871         if (ret < 0) {
8872                 PMD_DRV_LOG(ERR,
8873                             "Failed to delete ethertype filter"
8874                             " to hash table %d!",
8875                             ret);
8876                 return ret;
8877         }
8878         filter = rule->hash_map[ret];
8879         rule->hash_map[ret] = NULL;
8880
8881         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8882         rte_free(filter);
8883
8884         return 0;
8885 }
8886
8887 /*
8888  * Configure ethertype filter, which can director packet by filtering
8889  * with mac address and ether_type or only ether_type
8890  */
8891 int
8892 i40e_ethertype_filter_set(struct i40e_pf *pf,
8893                         struct rte_eth_ethertype_filter *filter,
8894                         bool add)
8895 {
8896         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8897         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8898         struct i40e_ethertype_filter *ethertype_filter, *node;
8899         struct i40e_ethertype_filter check_filter;
8900         struct i40e_control_filter_stats stats;
8901         uint16_t flags = 0;
8902         int ret;
8903
8904         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8905                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8906                 return -EINVAL;
8907         }
8908         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8909                 filter->ether_type == ETHER_TYPE_IPv6) {
8910                 PMD_DRV_LOG(ERR,
8911                         "unsupported ether_type(0x%04x) in control packet filter.",
8912                         filter->ether_type);
8913                 return -EINVAL;
8914         }
8915         if (filter->ether_type == ETHER_TYPE_VLAN)
8916                 PMD_DRV_LOG(WARNING,
8917                         "filter vlan ether_type in first tag is not supported.");
8918
8919         /* Check if there is the filter in SW list */
8920         memset(&check_filter, 0, sizeof(check_filter));
8921         i40e_ethertype_filter_convert(filter, &check_filter);
8922         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8923                                                &check_filter.input);
8924         if (add && node) {
8925                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8926                 return -EINVAL;
8927         }
8928
8929         if (!add && !node) {
8930                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8931                 return -EINVAL;
8932         }
8933
8934         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8935                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8936         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8937                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8938         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8939
8940         memset(&stats, 0, sizeof(stats));
8941         ret = i40e_aq_add_rem_control_packet_filter(hw,
8942                         filter->mac_addr.addr_bytes,
8943                         filter->ether_type, flags,
8944                         pf->main_vsi->seid,
8945                         filter->queue, add, &stats, NULL);
8946
8947         PMD_DRV_LOG(INFO,
8948                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8949                 ret, stats.mac_etype_used, stats.etype_used,
8950                 stats.mac_etype_free, stats.etype_free);
8951         if (ret < 0)
8952                 return -ENOSYS;
8953
8954         /* Add or delete a filter in SW list */
8955         if (add) {
8956                 ethertype_filter = rte_zmalloc("ethertype_filter",
8957                                        sizeof(*ethertype_filter), 0);
8958                 rte_memcpy(ethertype_filter, &check_filter,
8959                            sizeof(check_filter));
8960                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8961         } else {
8962                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8963         }
8964
8965         return ret;
8966 }
8967
8968 /*
8969  * Handle operations for ethertype filter.
8970  */
8971 static int
8972 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8973                                 enum rte_filter_op filter_op,
8974                                 void *arg)
8975 {
8976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8977         int ret = 0;
8978
8979         if (filter_op == RTE_ETH_FILTER_NOP)
8980                 return ret;
8981
8982         if (arg == NULL) {
8983                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8984                             filter_op);
8985                 return -EINVAL;
8986         }
8987
8988         switch (filter_op) {
8989         case RTE_ETH_FILTER_ADD:
8990                 ret = i40e_ethertype_filter_set(pf,
8991                         (struct rte_eth_ethertype_filter *)arg,
8992                         TRUE);
8993                 break;
8994         case RTE_ETH_FILTER_DELETE:
8995                 ret = i40e_ethertype_filter_set(pf,
8996                         (struct rte_eth_ethertype_filter *)arg,
8997                         FALSE);
8998                 break;
8999         default:
9000                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9001                 ret = -ENOSYS;
9002                 break;
9003         }
9004         return ret;
9005 }
9006
9007 static int
9008 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9009                      enum rte_filter_type filter_type,
9010                      enum rte_filter_op filter_op,
9011                      void *arg)
9012 {
9013         int ret = 0;
9014
9015         if (dev == NULL)
9016                 return -EINVAL;
9017
9018         switch (filter_type) {
9019         case RTE_ETH_FILTER_NONE:
9020                 /* For global configuration */
9021                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9022                 break;
9023         case RTE_ETH_FILTER_HASH:
9024                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9025                 break;
9026         case RTE_ETH_FILTER_MACVLAN:
9027                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9028                 break;
9029         case RTE_ETH_FILTER_ETHERTYPE:
9030                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9031                 break;
9032         case RTE_ETH_FILTER_TUNNEL:
9033                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9034                 break;
9035         case RTE_ETH_FILTER_FDIR:
9036                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9037                 break;
9038         case RTE_ETH_FILTER_GENERIC:
9039                 if (filter_op != RTE_ETH_FILTER_GET)
9040                         return -EINVAL;
9041                 *(const void **)arg = &i40e_flow_ops;
9042                 break;
9043         default:
9044                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9045                                                         filter_type);
9046                 ret = -EINVAL;
9047                 break;
9048         }
9049
9050         return ret;
9051 }
9052
9053 /*
9054  * Check and enable Extended Tag.
9055  * Enabling Extended Tag is important for 40G performance.
9056  */
9057 static void
9058 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9059 {
9060         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9061         uint32_t buf = 0;
9062         int ret;
9063
9064         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9065                                       PCI_DEV_CAP_REG);
9066         if (ret < 0) {
9067                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9068                             PCI_DEV_CAP_REG);
9069                 return;
9070         }
9071         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9072                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9073                 return;
9074         }
9075
9076         buf = 0;
9077         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9078                                       PCI_DEV_CTRL_REG);
9079         if (ret < 0) {
9080                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9081                             PCI_DEV_CTRL_REG);
9082                 return;
9083         }
9084         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9085                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9086                 return;
9087         }
9088         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9089         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9090                                        PCI_DEV_CTRL_REG);
9091         if (ret < 0) {
9092                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9093                             PCI_DEV_CTRL_REG);
9094                 return;
9095         }
9096 }
9097
9098 /*
9099  * As some registers wouldn't be reset unless a global hardware reset,
9100  * hardware initialization is needed to put those registers into an
9101  * expected initial state.
9102  */
9103 static void
9104 i40e_hw_init(struct rte_eth_dev *dev)
9105 {
9106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9107
9108         i40e_enable_extended_tag(dev);
9109
9110         /* clear the PF Queue Filter control register */
9111         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9112
9113         /* Disable symmetric hash per port */
9114         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9115 }
9116
9117 enum i40e_filter_pctype
9118 i40e_flowtype_to_pctype(uint16_t flow_type)
9119 {
9120         static const enum i40e_filter_pctype pctype_table[] = {
9121                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9122                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9123                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9124                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9125                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9126                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9127                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9128                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9129                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9130                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9131                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9132                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9133                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9134                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9135                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9136                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9137                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9138                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9139                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9140         };
9141
9142         return pctype_table[flow_type];
9143 }
9144
9145 uint16_t
9146 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9147 {
9148         static const uint16_t flowtype_table[] = {
9149                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9150                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9151                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9152                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9153                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9154                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9155                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9156                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9157                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9158                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9159                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9160                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9161                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9162                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9163                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9164                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9165                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9166                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9167                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9168                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9169                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9170                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9171                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9172                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9173                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9174                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9175                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9176                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9177                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9178                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9179                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9180         };
9181
9182         return flowtype_table[pctype];
9183 }
9184
9185 /*
9186  * On X710, performance number is far from the expectation on recent firmware
9187  * versions; on XL710, performance number is also far from the expectation on
9188  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9189  * mode is enabled and port MAC address is equal to the packet destination MAC
9190  * address. The fix for this issue may not be integrated in the following
9191  * firmware version. So the workaround in software driver is needed. It needs
9192  * to modify the initial values of 3 internal only registers for both X710 and
9193  * XL710. Note that the values for X710 or XL710 could be different, and the
9194  * workaround can be removed when it is fixed in firmware in the future.
9195  */
9196
9197 /* For both X710 and XL710 */
9198 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9199 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9200 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9201
9202 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9203 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9204
9205 /* For X722 */
9206 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9207 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9208
9209 /* For X710 */
9210 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9211 /* For XL710 */
9212 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9213 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9214
9215 static int
9216 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9217 {
9218         enum i40e_status_code status;
9219         struct i40e_aq_get_phy_abilities_resp phy_ab;
9220         int ret = -ENOTSUP;
9221
9222         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9223                                               NULL);
9224
9225         if (status)
9226                 return ret;
9227
9228         return 0;
9229 }
9230
9231 static void
9232 i40e_configure_registers(struct i40e_hw *hw)
9233 {
9234         static struct {
9235                 uint32_t addr;
9236                 uint64_t val;
9237         } reg_table[] = {
9238                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9239                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9240                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9241         };
9242         uint64_t reg;
9243         uint32_t i;
9244         int ret;
9245
9246         for (i = 0; i < RTE_DIM(reg_table); i++) {
9247                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9248                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9249                                 reg_table[i].val =
9250                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9251                         else /* For X710/XL710/XXV710 */
9252                                 if (hw->aq.fw_maj_ver < 6)
9253                                         reg_table[i].val =
9254                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9255                                 else
9256                                         reg_table[i].val =
9257                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9258                 }
9259
9260                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9261                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9262                                 reg_table[i].val =
9263                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9264                         else /* For X710/XL710/XXV710 */
9265                                 reg_table[i].val =
9266                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9267                 }
9268
9269                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9270                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9271                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9272                                 reg_table[i].val =
9273                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9274                         else /* For X710 */
9275                                 reg_table[i].val =
9276                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9277                 }
9278
9279                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9280                                                         &reg, NULL);
9281                 if (ret < 0) {
9282                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9283                                                         reg_table[i].addr);
9284                         break;
9285                 }
9286                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9287                                                 reg_table[i].addr, reg);
9288                 if (reg == reg_table[i].val)
9289                         continue;
9290
9291                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9292                                                 reg_table[i].val, NULL);
9293                 if (ret < 0) {
9294                         PMD_DRV_LOG(ERR,
9295                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9296                                 reg_table[i].val, reg_table[i].addr);
9297                         break;
9298                 }
9299                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9300                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9301         }
9302 }
9303
9304 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9305 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9306 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9307 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9308 static int
9309 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9310 {
9311         uint32_t reg;
9312         int ret;
9313
9314         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9315                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9316                 return -EINVAL;
9317         }
9318
9319         /* Configure for double VLAN RX stripping */
9320         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9321         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9322                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9323                 ret = i40e_aq_debug_write_register(hw,
9324                                                    I40E_VSI_TSR(vsi->vsi_id),
9325                                                    reg, NULL);
9326                 if (ret < 0) {
9327                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9328                                     vsi->vsi_id);
9329                         return I40E_ERR_CONFIG;
9330                 }
9331         }
9332
9333         /* Configure for double VLAN TX insertion */
9334         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9335         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9336                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9337                 ret = i40e_aq_debug_write_register(hw,
9338                                                    I40E_VSI_L2TAGSTXVALID(
9339                                                    vsi->vsi_id), reg, NULL);
9340                 if (ret < 0) {
9341                         PMD_DRV_LOG(ERR,
9342                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9343                                 vsi->vsi_id);
9344                         return I40E_ERR_CONFIG;
9345                 }
9346         }
9347
9348         return 0;
9349 }
9350
9351 /**
9352  * i40e_aq_add_mirror_rule
9353  * @hw: pointer to the hardware structure
9354  * @seid: VEB seid to add mirror rule to
9355  * @dst_id: destination vsi seid
9356  * @entries: Buffer which contains the entities to be mirrored
9357  * @count: number of entities contained in the buffer
9358  * @rule_id:the rule_id of the rule to be added
9359  *
9360  * Add a mirror rule for a given veb.
9361  *
9362  **/
9363 static enum i40e_status_code
9364 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9365                         uint16_t seid, uint16_t dst_id,
9366                         uint16_t rule_type, uint16_t *entries,
9367                         uint16_t count, uint16_t *rule_id)
9368 {
9369         struct i40e_aq_desc desc;
9370         struct i40e_aqc_add_delete_mirror_rule cmd;
9371         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9372                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9373                 &desc.params.raw;
9374         uint16_t buff_len;
9375         enum i40e_status_code status;
9376
9377         i40e_fill_default_direct_cmd_desc(&desc,
9378                                           i40e_aqc_opc_add_mirror_rule);
9379         memset(&cmd, 0, sizeof(cmd));
9380
9381         buff_len = sizeof(uint16_t) * count;
9382         desc.datalen = rte_cpu_to_le_16(buff_len);
9383         if (buff_len > 0)
9384                 desc.flags |= rte_cpu_to_le_16(
9385                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9386         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9387                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9388         cmd.num_entries = rte_cpu_to_le_16(count);
9389         cmd.seid = rte_cpu_to_le_16(seid);
9390         cmd.destination = rte_cpu_to_le_16(dst_id);
9391
9392         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9393         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9394         PMD_DRV_LOG(INFO,
9395                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9396                 hw->aq.asq_last_status, resp->rule_id,
9397                 resp->mirror_rules_used, resp->mirror_rules_free);
9398         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9399
9400         return status;
9401 }
9402
9403 /**
9404  * i40e_aq_del_mirror_rule
9405  * @hw: pointer to the hardware structure
9406  * @seid: VEB seid to add mirror rule to
9407  * @entries: Buffer which contains the entities to be mirrored
9408  * @count: number of entities contained in the buffer
9409  * @rule_id:the rule_id of the rule to be delete
9410  *
9411  * Delete a mirror rule for a given veb.
9412  *
9413  **/
9414 static enum i40e_status_code
9415 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9416                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9417                 uint16_t count, uint16_t rule_id)
9418 {
9419         struct i40e_aq_desc desc;
9420         struct i40e_aqc_add_delete_mirror_rule cmd;
9421         uint16_t buff_len = 0;
9422         enum i40e_status_code status;
9423         void *buff = NULL;
9424
9425         i40e_fill_default_direct_cmd_desc(&desc,
9426                                           i40e_aqc_opc_delete_mirror_rule);
9427         memset(&cmd, 0, sizeof(cmd));
9428         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9429                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9430                                                           I40E_AQ_FLAG_RD));
9431                 cmd.num_entries = count;
9432                 buff_len = sizeof(uint16_t) * count;
9433                 desc.datalen = rte_cpu_to_le_16(buff_len);
9434                 buff = (void *)entries;
9435         } else
9436                 /* rule id is filled in destination field for deleting mirror rule */
9437                 cmd.destination = rte_cpu_to_le_16(rule_id);
9438
9439         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9440                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9441         cmd.seid = rte_cpu_to_le_16(seid);
9442
9443         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9444         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9445
9446         return status;
9447 }
9448
9449 /**
9450  * i40e_mirror_rule_set
9451  * @dev: pointer to the hardware structure
9452  * @mirror_conf: mirror rule info
9453  * @sw_id: mirror rule's sw_id
9454  * @on: enable/disable
9455  *
9456  * set a mirror rule.
9457  *
9458  **/
9459 static int
9460 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9461                         struct rte_eth_mirror_conf *mirror_conf,
9462                         uint8_t sw_id, uint8_t on)
9463 {
9464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9466         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9467         struct i40e_mirror_rule *parent = NULL;
9468         uint16_t seid, dst_seid, rule_id;
9469         uint16_t i, j = 0;
9470         int ret;
9471
9472         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9473
9474         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9475                 PMD_DRV_LOG(ERR,
9476                         "mirror rule can not be configured without veb or vfs.");
9477                 return -ENOSYS;
9478         }
9479         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9480                 PMD_DRV_LOG(ERR, "mirror table is full.");
9481                 return -ENOSPC;
9482         }
9483         if (mirror_conf->dst_pool > pf->vf_num) {
9484                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9485                                  mirror_conf->dst_pool);
9486                 return -EINVAL;
9487         }
9488
9489         seid = pf->main_vsi->veb->seid;
9490
9491         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9492                 if (sw_id <= it->index) {
9493                         mirr_rule = it;
9494                         break;
9495                 }
9496                 parent = it;
9497         }
9498         if (mirr_rule && sw_id == mirr_rule->index) {
9499                 if (on) {
9500                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9501                         return -EEXIST;
9502                 } else {
9503                         ret = i40e_aq_del_mirror_rule(hw, seid,
9504                                         mirr_rule->rule_type,
9505                                         mirr_rule->entries,
9506                                         mirr_rule->num_entries, mirr_rule->id);
9507                         if (ret < 0) {
9508                                 PMD_DRV_LOG(ERR,
9509                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9510                                         ret, hw->aq.asq_last_status);
9511                                 return -ENOSYS;
9512                         }
9513                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9514                         rte_free(mirr_rule);
9515                         pf->nb_mirror_rule--;
9516                         return 0;
9517                 }
9518         } else if (!on) {
9519                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9520                 return -ENOENT;
9521         }
9522
9523         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9524                                 sizeof(struct i40e_mirror_rule) , 0);
9525         if (!mirr_rule) {
9526                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9527                 return I40E_ERR_NO_MEMORY;
9528         }
9529         switch (mirror_conf->rule_type) {
9530         case ETH_MIRROR_VLAN:
9531                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9532                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9533                                 mirr_rule->entries[j] =
9534                                         mirror_conf->vlan.vlan_id[i];
9535                                 j++;
9536                         }
9537                 }
9538                 if (j == 0) {
9539                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9540                         rte_free(mirr_rule);
9541                         return -EINVAL;
9542                 }
9543                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9544                 break;
9545         case ETH_MIRROR_VIRTUAL_POOL_UP:
9546         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9547                 /* check if the specified pool bit is out of range */
9548                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9549                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9550                         rte_free(mirr_rule);
9551                         return -EINVAL;
9552                 }
9553                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9554                         if (mirror_conf->pool_mask & (1ULL << i)) {
9555                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9556                                 j++;
9557                         }
9558                 }
9559                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9560                         /* add pf vsi to entries */
9561                         mirr_rule->entries[j] = pf->main_vsi_seid;
9562                         j++;
9563                 }
9564                 if (j == 0) {
9565                         PMD_DRV_LOG(ERR, "pool is not specified.");
9566                         rte_free(mirr_rule);
9567                         return -EINVAL;
9568                 }
9569                 /* egress and ingress in aq commands means from switch but not port */
9570                 mirr_rule->rule_type =
9571                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9572                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9573                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9574                 break;
9575         case ETH_MIRROR_UPLINK_PORT:
9576                 /* egress and ingress in aq commands means from switch but not port*/
9577                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9578                 break;
9579         case ETH_MIRROR_DOWNLINK_PORT:
9580                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9581                 break;
9582         default:
9583                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9584                         mirror_conf->rule_type);
9585                 rte_free(mirr_rule);
9586                 return -EINVAL;
9587         }
9588
9589         /* If the dst_pool is equal to vf_num, consider it as PF */
9590         if (mirror_conf->dst_pool == pf->vf_num)
9591                 dst_seid = pf->main_vsi_seid;
9592         else
9593                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9594
9595         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9596                                       mirr_rule->rule_type, mirr_rule->entries,
9597                                       j, &rule_id);
9598         if (ret < 0) {
9599                 PMD_DRV_LOG(ERR,
9600                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9601                         ret, hw->aq.asq_last_status);
9602                 rte_free(mirr_rule);
9603                 return -ENOSYS;
9604         }
9605
9606         mirr_rule->index = sw_id;
9607         mirr_rule->num_entries = j;
9608         mirr_rule->id = rule_id;
9609         mirr_rule->dst_vsi_seid = dst_seid;
9610
9611         if (parent)
9612                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9613         else
9614                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9615
9616         pf->nb_mirror_rule++;
9617         return 0;
9618 }
9619
9620 /**
9621  * i40e_mirror_rule_reset
9622  * @dev: pointer to the device
9623  * @sw_id: mirror rule's sw_id
9624  *
9625  * reset a mirror rule.
9626  *
9627  **/
9628 static int
9629 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9630 {
9631         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9633         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9634         uint16_t seid;
9635         int ret;
9636
9637         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9638
9639         seid = pf->main_vsi->veb->seid;
9640
9641         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9642                 if (sw_id == it->index) {
9643                         mirr_rule = it;
9644                         break;
9645                 }
9646         }
9647         if (mirr_rule) {
9648                 ret = i40e_aq_del_mirror_rule(hw, seid,
9649                                 mirr_rule->rule_type,
9650                                 mirr_rule->entries,
9651                                 mirr_rule->num_entries, mirr_rule->id);
9652                 if (ret < 0) {
9653                         PMD_DRV_LOG(ERR,
9654                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9655                                 ret, hw->aq.asq_last_status);
9656                         return -ENOSYS;
9657                 }
9658                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9659                 rte_free(mirr_rule);
9660                 pf->nb_mirror_rule--;
9661         } else {
9662                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9663                 return -ENOENT;
9664         }
9665         return 0;
9666 }
9667
9668 static uint64_t
9669 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9670 {
9671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9672         uint64_t systim_cycles;
9673
9674         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9675         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9676                         << 32;
9677
9678         return systim_cycles;
9679 }
9680
9681 static uint64_t
9682 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9683 {
9684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9685         uint64_t rx_tstamp;
9686
9687         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9688         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9689                         << 32;
9690
9691         return rx_tstamp;
9692 }
9693
9694 static uint64_t
9695 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9696 {
9697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9698         uint64_t tx_tstamp;
9699
9700         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9701         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9702                         << 32;
9703
9704         return tx_tstamp;
9705 }
9706
9707 static void
9708 i40e_start_timecounters(struct rte_eth_dev *dev)
9709 {
9710         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9711         struct i40e_adapter *adapter =
9712                         (struct i40e_adapter *)dev->data->dev_private;
9713         struct rte_eth_link link;
9714         uint32_t tsync_inc_l;
9715         uint32_t tsync_inc_h;
9716
9717         /* Get current link speed. */
9718         memset(&link, 0, sizeof(link));
9719         i40e_dev_link_update(dev, 1);
9720         rte_i40e_dev_atomic_read_link_status(dev, &link);
9721
9722         switch (link.link_speed) {
9723         case ETH_SPEED_NUM_40G:
9724                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9725                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9726                 break;
9727         case ETH_SPEED_NUM_10G:
9728                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9729                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9730                 break;
9731         case ETH_SPEED_NUM_1G:
9732                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9733                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9734                 break;
9735         default:
9736                 tsync_inc_l = 0x0;
9737                 tsync_inc_h = 0x0;
9738         }
9739
9740         /* Set the timesync increment value. */
9741         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9742         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9743
9744         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9745         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9746         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9747
9748         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9749         adapter->systime_tc.cc_shift = 0;
9750         adapter->systime_tc.nsec_mask = 0;
9751
9752         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9753         adapter->rx_tstamp_tc.cc_shift = 0;
9754         adapter->rx_tstamp_tc.nsec_mask = 0;
9755
9756         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9757         adapter->tx_tstamp_tc.cc_shift = 0;
9758         adapter->tx_tstamp_tc.nsec_mask = 0;
9759 }
9760
9761 static int
9762 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9763 {
9764         struct i40e_adapter *adapter =
9765                         (struct i40e_adapter *)dev->data->dev_private;
9766
9767         adapter->systime_tc.nsec += delta;
9768         adapter->rx_tstamp_tc.nsec += delta;
9769         adapter->tx_tstamp_tc.nsec += delta;
9770
9771         return 0;
9772 }
9773
9774 static int
9775 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9776 {
9777         uint64_t ns;
9778         struct i40e_adapter *adapter =
9779                         (struct i40e_adapter *)dev->data->dev_private;
9780
9781         ns = rte_timespec_to_ns(ts);
9782
9783         /* Set the timecounters to a new value. */
9784         adapter->systime_tc.nsec = ns;
9785         adapter->rx_tstamp_tc.nsec = ns;
9786         adapter->tx_tstamp_tc.nsec = ns;
9787
9788         return 0;
9789 }
9790
9791 static int
9792 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9793 {
9794         uint64_t ns, systime_cycles;
9795         struct i40e_adapter *adapter =
9796                         (struct i40e_adapter *)dev->data->dev_private;
9797
9798         systime_cycles = i40e_read_systime_cyclecounter(dev);
9799         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9800         *ts = rte_ns_to_timespec(ns);
9801
9802         return 0;
9803 }
9804
9805 static int
9806 i40e_timesync_enable(struct rte_eth_dev *dev)
9807 {
9808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9809         uint32_t tsync_ctl_l;
9810         uint32_t tsync_ctl_h;
9811
9812         /* Stop the timesync system time. */
9813         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9814         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9815         /* Reset the timesync system time value. */
9816         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9817         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9818
9819         i40e_start_timecounters(dev);
9820
9821         /* Clear timesync registers. */
9822         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9823         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9824         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9825         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9826         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9827         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9828
9829         /* Enable timestamping of PTP packets. */
9830         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9831         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9832
9833         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9834         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9835         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9836
9837         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9838         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9839
9840         return 0;
9841 }
9842
9843 static int
9844 i40e_timesync_disable(struct rte_eth_dev *dev)
9845 {
9846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9847         uint32_t tsync_ctl_l;
9848         uint32_t tsync_ctl_h;
9849
9850         /* Disable timestamping of transmitted PTP packets. */
9851         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9852         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9853
9854         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9855         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9856
9857         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9858         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9859
9860         /* Reset the timesync increment value. */
9861         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9862         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9863
9864         return 0;
9865 }
9866
9867 static int
9868 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9869                                 struct timespec *timestamp, uint32_t flags)
9870 {
9871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9872         struct i40e_adapter *adapter =
9873                 (struct i40e_adapter *)dev->data->dev_private;
9874
9875         uint32_t sync_status;
9876         uint32_t index = flags & 0x03;
9877         uint64_t rx_tstamp_cycles;
9878         uint64_t ns;
9879
9880         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9881         if ((sync_status & (1 << index)) == 0)
9882                 return -EINVAL;
9883
9884         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9885         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9886         *timestamp = rte_ns_to_timespec(ns);
9887
9888         return 0;
9889 }
9890
9891 static int
9892 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9893                                 struct timespec *timestamp)
9894 {
9895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9896         struct i40e_adapter *adapter =
9897                 (struct i40e_adapter *)dev->data->dev_private;
9898
9899         uint32_t sync_status;
9900         uint64_t tx_tstamp_cycles;
9901         uint64_t ns;
9902
9903         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9904         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9905                 return -EINVAL;
9906
9907         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9908         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9909         *timestamp = rte_ns_to_timespec(ns);
9910
9911         return 0;
9912 }
9913
9914 /*
9915  * i40e_parse_dcb_configure - parse dcb configure from user
9916  * @dev: the device being configured
9917  * @dcb_cfg: pointer of the result of parse
9918  * @*tc_map: bit map of enabled traffic classes
9919  *
9920  * Returns 0 on success, negative value on failure
9921  */
9922 static int
9923 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9924                          struct i40e_dcbx_config *dcb_cfg,
9925                          uint8_t *tc_map)
9926 {
9927         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9928         uint8_t i, tc_bw, bw_lf;
9929
9930         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9931
9932         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9933         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9934                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9935                 return -EINVAL;
9936         }
9937
9938         /* assume each tc has the same bw */
9939         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9940         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9941                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9942         /* to ensure the sum of tcbw is equal to 100 */
9943         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9944         for (i = 0; i < bw_lf; i++)
9945                 dcb_cfg->etscfg.tcbwtable[i]++;
9946
9947         /* assume each tc has the same Transmission Selection Algorithm */
9948         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9949                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9950
9951         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9952                 dcb_cfg->etscfg.prioritytable[i] =
9953                                 dcb_rx_conf->dcb_tc[i];
9954
9955         /* FW needs one App to configure HW */
9956         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9957         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9958         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9959         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9960
9961         if (dcb_rx_conf->nb_tcs == 0)
9962                 *tc_map = 1; /* tc0 only */
9963         else
9964                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9965
9966         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9967                 dcb_cfg->pfc.willing = 0;
9968                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9969                 dcb_cfg->pfc.pfcenable = *tc_map;
9970         }
9971         return 0;
9972 }
9973
9974
9975 static enum i40e_status_code
9976 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9977                               struct i40e_aqc_vsi_properties_data *info,
9978                               uint8_t enabled_tcmap)
9979 {
9980         enum i40e_status_code ret;
9981         int i, total_tc = 0;
9982         uint16_t qpnum_per_tc, bsf, qp_idx;
9983         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9984         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9985         uint16_t used_queues;
9986
9987         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9988         if (ret != I40E_SUCCESS)
9989                 return ret;
9990
9991         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9992                 if (enabled_tcmap & (1 << i))
9993                         total_tc++;
9994         }
9995         if (total_tc == 0)
9996                 total_tc = 1;
9997         vsi->enabled_tc = enabled_tcmap;
9998
9999         /* different VSI has different queues assigned */
10000         if (vsi->type == I40E_VSI_MAIN)
10001                 used_queues = dev_data->nb_rx_queues -
10002                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10003         else if (vsi->type == I40E_VSI_VMDQ2)
10004                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10005         else {
10006                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10007                 return I40E_ERR_NO_AVAILABLE_VSI;
10008         }
10009
10010         qpnum_per_tc = used_queues / total_tc;
10011         /* Number of queues per enabled TC */
10012         if (qpnum_per_tc == 0) {
10013                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10014                 return I40E_ERR_INVALID_QP_ID;
10015         }
10016         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10017                                 I40E_MAX_Q_PER_TC);
10018         bsf = rte_bsf32(qpnum_per_tc);
10019
10020         /**
10021          * Configure TC and queue mapping parameters, for enabled TC,
10022          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10023          * default queue will serve it.
10024          */
10025         qp_idx = 0;
10026         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10027                 if (vsi->enabled_tc & (1 << i)) {
10028                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10029                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10030                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10031                         qp_idx += qpnum_per_tc;
10032                 } else
10033                         info->tc_mapping[i] = 0;
10034         }
10035
10036         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10037         if (vsi->type == I40E_VSI_SRIOV) {
10038                 info->mapping_flags |=
10039                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10040                 for (i = 0; i < vsi->nb_qps; i++)
10041                         info->queue_mapping[i] =
10042                                 rte_cpu_to_le_16(vsi->base_queue + i);
10043         } else {
10044                 info->mapping_flags |=
10045                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10046                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10047         }
10048         info->valid_sections |=
10049                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10050
10051         return I40E_SUCCESS;
10052 }
10053
10054 /*
10055  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10056  * @veb: VEB to be configured
10057  * @tc_map: enabled TC bitmap
10058  *
10059  * Returns 0 on success, negative value on failure
10060  */
10061 static enum i40e_status_code
10062 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10063 {
10064         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10065         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10066         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10067         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10068         enum i40e_status_code ret = I40E_SUCCESS;
10069         int i;
10070         uint32_t bw_max;
10071
10072         /* Check if enabled_tc is same as existing or new TCs */
10073         if (veb->enabled_tc == tc_map)
10074                 return ret;
10075
10076         /* configure tc bandwidth */
10077         memset(&veb_bw, 0, sizeof(veb_bw));
10078         veb_bw.tc_valid_bits = tc_map;
10079         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10080         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10081                 if (tc_map & BIT_ULL(i))
10082                         veb_bw.tc_bw_share_credits[i] = 1;
10083         }
10084         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10085                                                    &veb_bw, NULL);
10086         if (ret) {
10087                 PMD_INIT_LOG(ERR,
10088                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10089                         hw->aq.asq_last_status);
10090                 return ret;
10091         }
10092
10093         memset(&ets_query, 0, sizeof(ets_query));
10094         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10095                                                    &ets_query, NULL);
10096         if (ret != I40E_SUCCESS) {
10097                 PMD_DRV_LOG(ERR,
10098                         "Failed to get switch_comp ETS configuration %u",
10099                         hw->aq.asq_last_status);
10100                 return ret;
10101         }
10102         memset(&bw_query, 0, sizeof(bw_query));
10103         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10104                                                   &bw_query, NULL);
10105         if (ret != I40E_SUCCESS) {
10106                 PMD_DRV_LOG(ERR,
10107                         "Failed to get switch_comp bandwidth configuration %u",
10108                         hw->aq.asq_last_status);
10109                 return ret;
10110         }
10111
10112         /* store and print out BW info */
10113         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10114         veb->bw_info.bw_max = ets_query.tc_bw_max;
10115         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10116         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10117         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10118                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10119                      I40E_16_BIT_WIDTH);
10120         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10121                 veb->bw_info.bw_ets_share_credits[i] =
10122                                 bw_query.tc_bw_share_credits[i];
10123                 veb->bw_info.bw_ets_credits[i] =
10124                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10125                 /* 4 bits per TC, 4th bit is reserved */
10126                 veb->bw_info.bw_ets_max[i] =
10127                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10128                                   RTE_LEN2MASK(3, uint8_t));
10129                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10130                             veb->bw_info.bw_ets_share_credits[i]);
10131                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10132                             veb->bw_info.bw_ets_credits[i]);
10133                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10134                             veb->bw_info.bw_ets_max[i]);
10135         }
10136
10137         veb->enabled_tc = tc_map;
10138
10139         return ret;
10140 }
10141
10142
10143 /*
10144  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10145  * @vsi: VSI to be configured
10146  * @tc_map: enabled TC bitmap
10147  *
10148  * Returns 0 on success, negative value on failure
10149  */
10150 static enum i40e_status_code
10151 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10152 {
10153         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10154         struct i40e_vsi_context ctxt;
10155         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10156         enum i40e_status_code ret = I40E_SUCCESS;
10157         int i;
10158
10159         /* Check if enabled_tc is same as existing or new TCs */
10160         if (vsi->enabled_tc == tc_map)
10161                 return ret;
10162
10163         /* configure tc bandwidth */
10164         memset(&bw_data, 0, sizeof(bw_data));
10165         bw_data.tc_valid_bits = tc_map;
10166         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10167         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10168                 if (tc_map & BIT_ULL(i))
10169                         bw_data.tc_bw_credits[i] = 1;
10170         }
10171         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10172         if (ret) {
10173                 PMD_INIT_LOG(ERR,
10174                         "AQ command Config VSI BW allocation per TC failed = %d",
10175                         hw->aq.asq_last_status);
10176                 goto out;
10177         }
10178         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10179                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10180
10181         /* Update Queue Pairs Mapping for currently enabled UPs */
10182         ctxt.seid = vsi->seid;
10183         ctxt.pf_num = hw->pf_id;
10184         ctxt.vf_num = 0;
10185         ctxt.uplink_seid = vsi->uplink_seid;
10186         ctxt.info = vsi->info;
10187         i40e_get_cap(hw);
10188         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10189         if (ret)
10190                 goto out;
10191
10192         /* Update the VSI after updating the VSI queue-mapping information */
10193         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10194         if (ret) {
10195                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10196                         hw->aq.asq_last_status);
10197                 goto out;
10198         }
10199         /* update the local VSI info with updated queue map */
10200         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10201                                         sizeof(vsi->info.tc_mapping));
10202         (void)rte_memcpy(&vsi->info.queue_mapping,
10203                         &ctxt.info.queue_mapping,
10204                 sizeof(vsi->info.queue_mapping));
10205         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10206         vsi->info.valid_sections = 0;
10207
10208         /* query and update current VSI BW information */
10209         ret = i40e_vsi_get_bw_config(vsi);
10210         if (ret) {
10211                 PMD_INIT_LOG(ERR,
10212                          "Failed updating vsi bw info, err %s aq_err %s",
10213                          i40e_stat_str(hw, ret),
10214                          i40e_aq_str(hw, hw->aq.asq_last_status));
10215                 goto out;
10216         }
10217
10218         vsi->enabled_tc = tc_map;
10219
10220 out:
10221         return ret;
10222 }
10223
10224 /*
10225  * i40e_dcb_hw_configure - program the dcb setting to hw
10226  * @pf: pf the configuration is taken on
10227  * @new_cfg: new configuration
10228  * @tc_map: enabled TC bitmap
10229  *
10230  * Returns 0 on success, negative value on failure
10231  */
10232 static enum i40e_status_code
10233 i40e_dcb_hw_configure(struct i40e_pf *pf,
10234                       struct i40e_dcbx_config *new_cfg,
10235                       uint8_t tc_map)
10236 {
10237         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10238         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10239         struct i40e_vsi *main_vsi = pf->main_vsi;
10240         struct i40e_vsi_list *vsi_list;
10241         enum i40e_status_code ret;
10242         int i;
10243         uint32_t val;
10244
10245         /* Use the FW API if FW > v4.4*/
10246         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10247               (hw->aq.fw_maj_ver >= 5))) {
10248                 PMD_INIT_LOG(ERR,
10249                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10250                 return I40E_ERR_FIRMWARE_API_VERSION;
10251         }
10252
10253         /* Check if need reconfiguration */
10254         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10255                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10256                 return I40E_SUCCESS;
10257         }
10258
10259         /* Copy the new config to the current config */
10260         *old_cfg = *new_cfg;
10261         old_cfg->etsrec = old_cfg->etscfg;
10262         ret = i40e_set_dcb_config(hw);
10263         if (ret) {
10264                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10265                          i40e_stat_str(hw, ret),
10266                          i40e_aq_str(hw, hw->aq.asq_last_status));
10267                 return ret;
10268         }
10269         /* set receive Arbiter to RR mode and ETS scheme by default */
10270         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10271                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10272                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10273                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10274                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10275                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10276                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10277                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10278                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10279                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10280                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10281                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10282                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10283         }
10284         /* get local mib to check whether it is configured correctly */
10285         /* IEEE mode */
10286         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10287         /* Get Local DCB Config */
10288         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10289                                      &hw->local_dcbx_config);
10290
10291         /* if Veb is created, need to update TC of it at first */
10292         if (main_vsi->veb) {
10293                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10294                 if (ret)
10295                         PMD_INIT_LOG(WARNING,
10296                                  "Failed configuring TC for VEB seid=%d",
10297                                  main_vsi->veb->seid);
10298         }
10299         /* Update each VSI */
10300         i40e_vsi_config_tc(main_vsi, tc_map);
10301         if (main_vsi->veb) {
10302                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10303                         /* Beside main VSI and VMDQ VSIs, only enable default
10304                          * TC for other VSIs
10305                          */
10306                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10307                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10308                                                          tc_map);
10309                         else
10310                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10311                                                          I40E_DEFAULT_TCMAP);
10312                         if (ret)
10313                                 PMD_INIT_LOG(WARNING,
10314                                         "Failed configuring TC for VSI seid=%d",
10315                                         vsi_list->vsi->seid);
10316                         /* continue */
10317                 }
10318         }
10319         return I40E_SUCCESS;
10320 }
10321
10322 /*
10323  * i40e_dcb_init_configure - initial dcb config
10324  * @dev: device being configured
10325  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10326  *
10327  * Returns 0 on success, negative value on failure
10328  */
10329 static int
10330 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10331 {
10332         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10334         int i, ret = 0;
10335
10336         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10337                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10338                 return -ENOTSUP;
10339         }
10340
10341         /* DCB initialization:
10342          * Update DCB configuration from the Firmware and configure
10343          * LLDP MIB change event.
10344          */
10345         if (sw_dcb == TRUE) {
10346                 ret = i40e_init_dcb(hw);
10347                 /* If lldp agent is stopped, the return value from
10348                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10349                  * adminq status. Otherwise, it should return success.
10350                  */
10351                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10352                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10353                         memset(&hw->local_dcbx_config, 0,
10354                                 sizeof(struct i40e_dcbx_config));
10355                         /* set dcb default configuration */
10356                         hw->local_dcbx_config.etscfg.willing = 0;
10357                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10358                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10359                         hw->local_dcbx_config.etscfg.tsatable[0] =
10360                                                 I40E_IEEE_TSA_ETS;
10361                         /* all UPs mapping to TC0 */
10362                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10363                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10364                         hw->local_dcbx_config.etsrec =
10365                                 hw->local_dcbx_config.etscfg;
10366                         hw->local_dcbx_config.pfc.willing = 0;
10367                         hw->local_dcbx_config.pfc.pfccap =
10368                                                 I40E_MAX_TRAFFIC_CLASS;
10369                         /* FW needs one App to configure HW */
10370                         hw->local_dcbx_config.numapps = 1;
10371                         hw->local_dcbx_config.app[0].selector =
10372                                                 I40E_APP_SEL_ETHTYPE;
10373                         hw->local_dcbx_config.app[0].priority = 3;
10374                         hw->local_dcbx_config.app[0].protocolid =
10375                                                 I40E_APP_PROTOID_FCOE;
10376                         ret = i40e_set_dcb_config(hw);
10377                         if (ret) {
10378                                 PMD_INIT_LOG(ERR,
10379                                         "default dcb config fails. err = %d, aq_err = %d.",
10380                                         ret, hw->aq.asq_last_status);
10381                                 return -ENOSYS;
10382                         }
10383                 } else {
10384                         PMD_INIT_LOG(ERR,
10385                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10386                                 ret, hw->aq.asq_last_status);
10387                         return -ENOTSUP;
10388                 }
10389         } else {
10390                 ret = i40e_aq_start_lldp(hw, NULL);
10391                 if (ret != I40E_SUCCESS)
10392                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10393
10394                 ret = i40e_init_dcb(hw);
10395                 if (!ret) {
10396                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10397                                 PMD_INIT_LOG(ERR,
10398                                         "HW doesn't support DCBX offload.");
10399                                 return -ENOTSUP;
10400                         }
10401                 } else {
10402                         PMD_INIT_LOG(ERR,
10403                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10404                                 ret, hw->aq.asq_last_status);
10405                         return -ENOTSUP;
10406                 }
10407         }
10408         return 0;
10409 }
10410
10411 /*
10412  * i40e_dcb_setup - setup dcb related config
10413  * @dev: device being configured
10414  *
10415  * Returns 0 on success, negative value on failure
10416  */
10417 static int
10418 i40e_dcb_setup(struct rte_eth_dev *dev)
10419 {
10420         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10421         struct i40e_dcbx_config dcb_cfg;
10422         uint8_t tc_map = 0;
10423         int ret = 0;
10424
10425         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10426                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10427                 return -ENOTSUP;
10428         }
10429
10430         if (pf->vf_num != 0)
10431                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10432
10433         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10434         if (ret) {
10435                 PMD_INIT_LOG(ERR, "invalid dcb config");
10436                 return -EINVAL;
10437         }
10438         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10439         if (ret) {
10440                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10441                 return -ENOSYS;
10442         }
10443
10444         return 0;
10445 }
10446
10447 static int
10448 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10449                       struct rte_eth_dcb_info *dcb_info)
10450 {
10451         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10452         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10453         struct i40e_vsi *vsi = pf->main_vsi;
10454         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10455         uint16_t bsf, tc_mapping;
10456         int i, j = 0;
10457
10458         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10459                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10460         else
10461                 dcb_info->nb_tcs = 1;
10462         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10463                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10464         for (i = 0; i < dcb_info->nb_tcs; i++)
10465                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10466
10467         /* get queue mapping if vmdq is disabled */
10468         if (!pf->nb_cfg_vmdq_vsi) {
10469                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10470                         if (!(vsi->enabled_tc & (1 << i)))
10471                                 continue;
10472                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10473                         dcb_info->tc_queue.tc_rxq[j][i].base =
10474                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10475                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10476                         dcb_info->tc_queue.tc_txq[j][i].base =
10477                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10478                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10479                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10480                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10481                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10482                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10483                 }
10484                 return 0;
10485         }
10486
10487         /* get queue mapping if vmdq is enabled */
10488         do {
10489                 vsi = pf->vmdq[j].vsi;
10490                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10491                         if (!(vsi->enabled_tc & (1 << i)))
10492                                 continue;
10493                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10494                         dcb_info->tc_queue.tc_rxq[j][i].base =
10495                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10496                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10497                         dcb_info->tc_queue.tc_txq[j][i].base =
10498                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10499                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10500                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10501                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10502                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10503                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10504                 }
10505                 j++;
10506         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10507         return 0;
10508 }
10509
10510 static int
10511 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10512 {
10513         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10514         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10516         uint16_t interval =
10517                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10518         uint16_t msix_intr;
10519
10520         msix_intr = intr_handle->intr_vec[queue_id];
10521         if (msix_intr == I40E_MISC_VEC_ID)
10522                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10523                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10524                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10525                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10526                                (interval <<
10527                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10528         else
10529                 I40E_WRITE_REG(hw,
10530                                I40E_PFINT_DYN_CTLN(msix_intr -
10531                                                    I40E_RX_VEC_START),
10532                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10533                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10534                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10535                                (interval <<
10536                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10537
10538         I40E_WRITE_FLUSH(hw);
10539         rte_intr_enable(&pci_dev->intr_handle);
10540
10541         return 0;
10542 }
10543
10544 static int
10545 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10546 {
10547         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10549         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10550         uint16_t msix_intr;
10551
10552         msix_intr = intr_handle->intr_vec[queue_id];
10553         if (msix_intr == I40E_MISC_VEC_ID)
10554                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10555         else
10556                 I40E_WRITE_REG(hw,
10557                                I40E_PFINT_DYN_CTLN(msix_intr -
10558                                                    I40E_RX_VEC_START),
10559                                0);
10560         I40E_WRITE_FLUSH(hw);
10561
10562         return 0;
10563 }
10564
10565 static int i40e_get_regs(struct rte_eth_dev *dev,
10566                          struct rte_dev_reg_info *regs)
10567 {
10568         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10569         uint32_t *ptr_data = regs->data;
10570         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10571         const struct i40e_reg_info *reg_info;
10572
10573         if (ptr_data == NULL) {
10574                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10575                 regs->width = sizeof(uint32_t);
10576                 return 0;
10577         }
10578
10579         /* The first few registers have to be read using AQ operations */
10580         reg_idx = 0;
10581         while (i40e_regs_adminq[reg_idx].name) {
10582                 reg_info = &i40e_regs_adminq[reg_idx++];
10583                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10584                         for (arr_idx2 = 0;
10585                                         arr_idx2 <= reg_info->count2;
10586                                         arr_idx2++) {
10587                                 reg_offset = arr_idx * reg_info->stride1 +
10588                                         arr_idx2 * reg_info->stride2;
10589                                 reg_offset += reg_info->base_addr;
10590                                 ptr_data[reg_offset >> 2] =
10591                                         i40e_read_rx_ctl(hw, reg_offset);
10592                         }
10593         }
10594
10595         /* The remaining registers can be read using primitives */
10596         reg_idx = 0;
10597         while (i40e_regs_others[reg_idx].name) {
10598                 reg_info = &i40e_regs_others[reg_idx++];
10599                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10600                         for (arr_idx2 = 0;
10601                                         arr_idx2 <= reg_info->count2;
10602                                         arr_idx2++) {
10603                                 reg_offset = arr_idx * reg_info->stride1 +
10604                                         arr_idx2 * reg_info->stride2;
10605                                 reg_offset += reg_info->base_addr;
10606                                 ptr_data[reg_offset >> 2] =
10607                                         I40E_READ_REG(hw, reg_offset);
10608                         }
10609         }
10610
10611         return 0;
10612 }
10613
10614 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10615 {
10616         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10617
10618         /* Convert word count to byte count */
10619         return hw->nvm.sr_size << 1;
10620 }
10621
10622 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10623                            struct rte_dev_eeprom_info *eeprom)
10624 {
10625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10626         uint16_t *data = eeprom->data;
10627         uint16_t offset, length, cnt_words;
10628         int ret_code;
10629
10630         offset = eeprom->offset >> 1;
10631         length = eeprom->length >> 1;
10632         cnt_words = length;
10633
10634         if (offset > hw->nvm.sr_size ||
10635                 offset + length > hw->nvm.sr_size) {
10636                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10637                 return -EINVAL;
10638         }
10639
10640         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10641
10642         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10643         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10644                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10645                 return -EIO;
10646         }
10647
10648         return 0;
10649 }
10650
10651 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10652                                       struct ether_addr *mac_addr)
10653 {
10654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10655
10656         if (!is_valid_assigned_ether_addr(mac_addr)) {
10657                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10658                 return;
10659         }
10660
10661         /* Flags: 0x3 updates port address */
10662         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10663 }
10664
10665 static int
10666 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10667 {
10668         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10669         struct rte_eth_dev_data *dev_data = pf->dev_data;
10670         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10671         int ret = 0;
10672
10673         /* check if mtu is within the allowed range */
10674         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10675                 return -EINVAL;
10676
10677         /* mtu setting is forbidden if port is start */
10678         if (dev_data->dev_started) {
10679                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10680                             dev_data->port_id);
10681                 return -EBUSY;
10682         }
10683
10684         if (frame_size > ETHER_MAX_LEN)
10685                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10686         else
10687                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10688
10689         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10690
10691         return ret;
10692 }
10693
10694 /* Restore ethertype filter */
10695 static void
10696 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10697 {
10698         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10699         struct i40e_ethertype_filter_list
10700                 *ethertype_list = &pf->ethertype.ethertype_list;
10701         struct i40e_ethertype_filter *f;
10702         struct i40e_control_filter_stats stats;
10703         uint16_t flags;
10704
10705         TAILQ_FOREACH(f, ethertype_list, rules) {
10706                 flags = 0;
10707                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10708                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10709                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10710                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10711                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10712
10713                 memset(&stats, 0, sizeof(stats));
10714                 i40e_aq_add_rem_control_packet_filter(hw,
10715                                             f->input.mac_addr.addr_bytes,
10716                                             f->input.ether_type,
10717                                             flags, pf->main_vsi->seid,
10718                                             f->queue, 1, &stats, NULL);
10719         }
10720         PMD_DRV_LOG(INFO, "Ethertype filter:"
10721                     " mac_etype_used = %u, etype_used = %u,"
10722                     " mac_etype_free = %u, etype_free = %u",
10723                     stats.mac_etype_used, stats.etype_used,
10724                     stats.mac_etype_free, stats.etype_free);
10725 }
10726
10727 /* Restore tunnel filter */
10728 static void
10729 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10730 {
10731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10732         struct i40e_vsi *vsi;
10733         struct i40e_pf_vf *vf;
10734         struct i40e_tunnel_filter_list
10735                 *tunnel_list = &pf->tunnel.tunnel_list;
10736         struct i40e_tunnel_filter *f;
10737         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10738         bool big_buffer = 0;
10739
10740         TAILQ_FOREACH(f, tunnel_list, rules) {
10741                 if (!f->is_to_vf)
10742                         vsi = pf->main_vsi;
10743                 else {
10744                         vf = &pf->vfs[f->vf_id];
10745                         vsi = vf->vsi;
10746                 }
10747                 memset(&cld_filter, 0, sizeof(cld_filter));
10748                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10749                         (struct ether_addr *)&cld_filter.element.outer_mac);
10750                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10751                         (struct ether_addr *)&cld_filter.element.inner_mac);
10752                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10753                 cld_filter.element.flags = f->input.flags;
10754                 cld_filter.element.tenant_id = f->input.tenant_id;
10755                 cld_filter.element.queue_number = f->queue;
10756                 rte_memcpy(cld_filter.general_fields,
10757                            f->input.general_fields,
10758                            sizeof(f->input.general_fields));
10759
10760                 if (((f->input.flags &
10761                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10762                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10763                     ((f->input.flags &
10764                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10765                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10766                     ((f->input.flags &
10767                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10768                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10769                         big_buffer = 1;
10770
10771                 if (big_buffer)
10772                         i40e_aq_add_cloud_filters_big_buffer(hw,
10773                                              vsi->seid, &cld_filter, 1);
10774                 else
10775                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10776                                                   &cld_filter.element, 1);
10777         }
10778 }
10779
10780 static void
10781 i40e_filter_restore(struct i40e_pf *pf)
10782 {
10783         i40e_ethertype_filter_restore(pf);
10784         i40e_tunnel_filter_restore(pf);
10785         i40e_fdir_filter_restore(pf);
10786 }
10787
10788 static bool
10789 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10790 {
10791         if (strcmp(dev->data->drv_name,
10792                    drv->driver.name))
10793                 return false;
10794
10795         return true;
10796 }
10797
10798 bool
10799 is_i40e_supported(struct rte_eth_dev *dev)
10800 {
10801         return is_device_supported(dev, &rte_i40e_pmd);
10802 }
10803
10804 /* Create a QinQ cloud filter
10805  *
10806  * The Fortville NIC has limited resources for tunnel filters,
10807  * so we can only reuse existing filters.
10808  *
10809  * In step 1 we define which Field Vector fields can be used for
10810  * filter types.
10811  * As we do not have the inner tag defined as a field,
10812  * we have to define it first, by reusing one of L1 entries.
10813  *
10814  * In step 2 we are replacing one of existing filter types with
10815  * a new one for QinQ.
10816  * As we reusing L1 and replacing L2, some of the default filter
10817  * types will disappear,which depends on L1 and L2 entries we reuse.
10818  *
10819  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10820  *
10821  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10822  *              later when we define the cloud filter.
10823  *      a.      Valid_flags.replace_cloud = 0
10824  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10825  *      c.      New_filter = 0x10
10826  *      d.      TR bit = 0xff (optional, not used here)
10827  *      e.      Buffer – 2 entries:
10828  *              i.      Byte 0 = 8 (outer vlan FV index).
10829  *                      Byte 1 = 0 (rsv)
10830  *                      Byte 2-3 = 0x0fff
10831  *              ii.     Byte 0 = 37 (inner vlan FV index).
10832  *                      Byte 1 =0 (rsv)
10833  *                      Byte 2-3 = 0x0fff
10834  *
10835  * Step 2:
10836  * 2.   Create cloud filter using two L1 filters entries: stag and
10837  *              new filter(outer vlan+ inner vlan)
10838  *      a.      Valid_flags.replace_cloud = 1
10839  *      b.      Old_filter = 1 (instead of outer IP)
10840  *      c.      New_filter = 0x10
10841  *      d.      Buffer – 2 entries:
10842  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10843  *                      Byte 1-3 = 0 (rsv)
10844  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10845  *                      Byte 9-11 = 0 (rsv)
10846  */
10847 static int
10848 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10849 {
10850         int ret = -ENOTSUP;
10851         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10852         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10853         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10854
10855         /* Init */
10856         memset(&filter_replace, 0,
10857                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10858         memset(&filter_replace_buf, 0,
10859                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10860
10861         /* create L1 filter */
10862         filter_replace.old_filter_type =
10863                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10864         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10865         filter_replace.tr_bit = 0;
10866
10867         /* Prepare the buffer, 2 entries */
10868         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10869         filter_replace_buf.data[0] |=
10870                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10871         /* Field Vector 12b mask */
10872         filter_replace_buf.data[2] = 0xff;
10873         filter_replace_buf.data[3] = 0x0f;
10874         filter_replace_buf.data[4] =
10875                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10876         filter_replace_buf.data[4] |=
10877                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10878         /* Field Vector 12b mask */
10879         filter_replace_buf.data[6] = 0xff;
10880         filter_replace_buf.data[7] = 0x0f;
10881         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10882                         &filter_replace_buf);
10883         if (ret != I40E_SUCCESS)
10884                 return ret;
10885
10886         /* Apply the second L2 cloud filter */
10887         memset(&filter_replace, 0,
10888                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10889         memset(&filter_replace_buf, 0,
10890                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10891
10892         /* create L2 filter, input for L2 filter will be L1 filter  */
10893         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10894         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10895         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10896
10897         /* Prepare the buffer, 2 entries */
10898         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10899         filter_replace_buf.data[0] |=
10900                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10901         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10902         filter_replace_buf.data[4] |=
10903                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10904         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10905                         &filter_replace_buf);
10906         return ret;
10907 }
10908
10909 RTE_INIT(i40e_init_log);
10910 static void
10911 i40e_init_log(void)
10912 {
10913         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10914         if (i40e_logtype_init >= 0)
10915                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10916         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10917         if (i40e_logtype_driver >= 0)
10918                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10919 }