drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control enable fwd bit */
  87 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  88
  89 /* Receive Packet Buffer size */
  90 #define I40E_RXPBSIZE (968 * 1024)
  91
  92 /* Kilobytes shift */
  93 #define I40E_KILOSHIFT 10
  94
  95 /* Flow control default high water */
  96 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  97
  98 /* Flow control default low water */
  99 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(
 377                 __rte_unused struct rte_intr_handle *handle, void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 426                                                      uint16_t seid,
 427                                                      uint16_t rule_type,
 428                                                      uint16_t *entries,
 429                                                      uint16_t count,
 430                                                      uint16_t rule_id);
 431 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 432                         struct rte_eth_mirror_conf *mirror_conf,
 433                         uint8_t sw_id, uint8_t on);
 434 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 435
 436 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 437 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 438 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 439                                            struct timespec *timestamp,
 440                                            uint32_t flags);
 441 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 442                                            struct timespec *timestamp);
 443 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 444
 445 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 446
 447 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 448                                    struct timespec *timestamp);
 449 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 450                                     const struct timespec *timestamp);
 451
 452 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 453                                          uint16_t queue_id);
 454 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 455                                           uint16_t queue_id);
 456
 457 static int i40e_get_regs(struct rte_eth_dev *dev,
 458                          struct rte_dev_reg_info *regs);
 459
 460 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 461
 462 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 463                            struct rte_dev_eeprom_info *eeprom);
 464
 465 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 466                                       struct ether_addr *mac_addr);
 467
 468 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 469 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 470
 471 static const struct rte_pci_id pci_id_i40e_map[] = {
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 486         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 487         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 488         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 489         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 490         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 491         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 492         { .vendor_id = 0, /* sentinel */ },
 493 };
 494
 495 static const struct eth_dev_ops i40e_eth_dev_ops = {
 496         .dev_configure                = i40e_dev_configure,
 497         .dev_start                    = i40e_dev_start,
 498         .dev_stop                     = i40e_dev_stop,
 499         .dev_close                    = i40e_dev_close,
 500         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 501         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 502         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 503         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 504         .dev_set_link_up              = i40e_dev_set_link_up,
 505         .dev_set_link_down            = i40e_dev_set_link_down,
 506         .link_update                  = i40e_dev_link_update,
 507         .stats_get                    = i40e_dev_stats_get,
 508         .xstats_get                   = i40e_dev_xstats_get,
 509         .xstats_get_names             = i40e_dev_xstats_get_names,
 510         .stats_reset                  = i40e_dev_stats_reset,
 511         .xstats_reset                 = i40e_dev_stats_reset,
 512         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 513         .dev_infos_get                = i40e_dev_info_get,
 514         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 515         .vlan_filter_set              = i40e_vlan_filter_set,
 516         .vlan_tpid_set                = i40e_vlan_tpid_set,
 517         .vlan_offload_set             = i40e_vlan_offload_set,
 518         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 519         .vlan_pvid_set                = i40e_vlan_pvid_set,
 520         .rx_queue_start               = i40e_dev_rx_queue_start,
 521         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 522         .tx_queue_start               = i40e_dev_tx_queue_start,
 523         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 524         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 525         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 526         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 527         .rx_queue_release             = i40e_dev_rx_queue_release,
 528         .rx_queue_count               = i40e_dev_rx_queue_count,
 529         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 530         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 531         .tx_queue_release             = i40e_dev_tx_queue_release,
 532         .dev_led_on                   = i40e_dev_led_on,
 533         .dev_led_off                  = i40e_dev_led_off,
 534         .flow_ctrl_get                = i40e_flow_ctrl_get,
 535         .flow_ctrl_set                = i40e_flow_ctrl_set,
 536         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 537         .mac_addr_add                 = i40e_macaddr_add,
 538         .mac_addr_remove              = i40e_macaddr_remove,
 539         .reta_update                  = i40e_dev_rss_reta_update,
 540         .reta_query                   = i40e_dev_rss_reta_query,
 541         .rss_hash_update              = i40e_dev_rss_hash_update,
 542         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 543         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 544         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 545         .filter_ctrl                  = i40e_dev_filter_ctrl,
 546         .rxq_info_get                 = i40e_rxq_info_get,
 547         .txq_info_get                 = i40e_txq_info_get,
 548         .mirror_rule_set              = i40e_mirror_rule_set,
 549         .mirror_rule_reset            = i40e_mirror_rule_reset,
 550         .timesync_enable              = i40e_timesync_enable,
 551         .timesync_disable             = i40e_timesync_disable,
 552         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 553         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 554         .get_dcb_info                 = i40e_dev_get_dcb_info,
 555         .timesync_adjust_time         = i40e_timesync_adjust_time,
 556         .timesync_read_time           = i40e_timesync_read_time,
 557         .timesync_write_time          = i40e_timesync_write_time,
 558         .get_reg                      = i40e_get_regs,
 559         .get_eeprom_length            = i40e_get_eeprom_length,
 560         .get_eeprom                   = i40e_get_eeprom,
 561         .mac_addr_set                 = i40e_set_default_mac_addr,
 562         .mtu_set                      = i40e_dev_mtu_set,
 563 };
 564
 565 /* store statistics names and its offset in stats structure */
 566 struct rte_i40e_xstats_name_off {
 567         char name[RTE_ETH_XSTATS_NAME_SIZE];
 568         unsigned offset;
 569 };
 570
 571 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 572         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 573         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 574         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 575         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 576         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 577                 rx_unknown_protocol)},
 578         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 579         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 580         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 581         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 582 };
 583
 584 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 585                 sizeof(rte_i40e_stats_strings[0]))
 586
 587 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 588         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 589                 tx_dropped_link_down)},
 590         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 591         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 592                 illegal_bytes)},
 593         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 594         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 595                 mac_local_faults)},
 596         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 597                 mac_remote_faults)},
 598         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 599                 rx_length_errors)},
 600         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 601         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 602         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 603         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 604         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 605         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 606                 rx_size_127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 608                 rx_size_255)},
 609         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 610                 rx_size_511)},
 611         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 612                 rx_size_1023)},
 613         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 614                 rx_size_1522)},
 615         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 616                 rx_size_big)},
 617         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 618                 rx_undersize)},
 619         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 620                 rx_oversize)},
 621         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 622                 mac_short_packet_dropped)},
 623         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 624                 rx_fragments)},
 625         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 626         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 627         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 628                 tx_size_127)},
 629         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 630                 tx_size_255)},
 631         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 632                 tx_size_511)},
 633         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 634                 tx_size_1023)},
 635         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 636                 tx_size_1522)},
 637         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 638                 tx_size_big)},
 639         {"rx_flow_director_atr_match_packets",
 640                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 641         {"rx_flow_director_sb_match_packets",
 642                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 643         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 644                 tx_lpi_status)},
 645         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 646                 rx_lpi_status)},
 647         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 648                 tx_lpi_count)},
 649         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 650                 rx_lpi_count)},
 651 };
 652
 653 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 654                 sizeof(rte_i40e_hw_port_strings[0]))
 655
 656 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 657         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_rx)},
 659         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 660                 priority_xoff_rx)},
 661 };
 662
 663 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 664                 sizeof(rte_i40e_rxq_prio_strings[0]))
 665
 666 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 667         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 668                 priority_xon_tx)},
 669         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 670                 priority_xoff_tx)},
 671         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 672                 priority_xon_2_xoff)},
 673 };
 674
 675 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 676                 sizeof(rte_i40e_txq_prio_strings[0]))
 677
 678 static struct eth_driver rte_i40e_pmd = {
 679         .pci_drv = {
 680                 .id_table = pci_id_i40e_map,
 681                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 682                         RTE_PCI_DRV_DETACHABLE,
 683                 .probe = rte_eth_dev_pci_probe,
 684                 .remove = rte_eth_dev_pci_remove,
 685         },
 686         .eth_dev_init = eth_i40e_dev_init,
 687         .eth_dev_uninit = eth_i40e_dev_uninit,
 688         .dev_private_size = sizeof(struct i40e_adapter),
 689 };
 690
 691 static inline int
 692 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 693                                      struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = link;
 696         struct rte_eth_link *src = &(dev->data->dev_link);
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 static inline int
 706 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 707                                       struct rte_eth_link *link)
 708 {
 709         struct rte_eth_link *dst = &(dev->data->dev_link);
 710         struct rte_eth_link *src = link;
 711
 712         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 713                                         *(uint64_t *)src) == 0)
 714                 return -1;
 715
 716         return 0;
 717 }
 718
 719 static inline void
 720 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 721 {
 722         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 723         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 724                     "with value 0x%08x",
 725                     reg_addr, reg_val);
 726 }
 727
 728 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 729 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 730
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737
 738 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 739 {
 740         /*
 741          * Force global configuration for flexible payload
 742          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 743          * This should be removed from code once proper
 744          * configuration API is added to avoid configuration conflicts
 745          * between ports of the same device.
 746          */
 747         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 750         i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
 751
 752         /*
 753          * Initialize registers for parsing packet type of QinQ
 754          * This should be removed from code once proper
 755          * configuration API is added to avoid configuration conflicts
 756          * between ports of the same device.
 757          */
 758         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 759         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 760         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 761 }
 762
 763 static inline void i40e_config_automask(struct i40e_pf *pf)
 764 {
 765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 766         uint32_t val;
 767
 768         /* INTENA flag is not auto-cleared for interrupt */
 769         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 770         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 771                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 772
 773         /* If support multi-driver, PF will use INT0. */
 774         if (!pf->support_multi_driver)
 775                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 776
 777         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 778 }
 779
 780 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 781
 782 /*
 783  * Add a ethertype filter to drop all flow control frames transmitted
 784  * from VSIs.
 785 */
 786 static void
 787 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 788 {
 789         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 790         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 791                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 792                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 793         int ret;
 794
 795         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 796                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 797                                 pf->main_vsi_seid, 0,
 798                                 TRUE, NULL, NULL);
 799         if (ret)
 800                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 801                                   " frames from VSIs.");
 802 }
 803
 804 static int
 805 floating_veb_list_handler(__rte_unused const char *key,
 806                           const char *floating_veb_value,
 807                           void *opaque)
 808 {
 809         int idx = 0;
 810         unsigned int count = 0;
 811         char *end = NULL;
 812         int min, max;
 813         bool *vf_floating_veb = opaque;
 814
 815         while (isblank(*floating_veb_value))
 816                 floating_veb_value++;
 817
 818         /* Reset floating VEB configuration for VFs */
 819         for (idx = 0; idx < I40E_MAX_VF; idx++)
 820                 vf_floating_veb[idx] = false;
 821
 822         min = I40E_MAX_VF;
 823         do {
 824                 while (isblank(*floating_veb_value))
 825                         floating_veb_value++;
 826                 if (*floating_veb_value == '\0')
 827                         return -1;
 828                 errno = 0;
 829                 idx = strtoul(floating_veb_value, &end, 10);
 830                 if (errno || end == NULL)
 831                         return -1;
 832                 while (isblank(*end))
 833                         end++;
 834                 if (*end == '-') {
 835                         min = idx;
 836                 } else if ((*end == ';') || (*end == '\0')) {
 837                         max = idx;
 838                         if (min == I40E_MAX_VF)
 839                                 min = idx;
 840                         if (max >= I40E_MAX_VF)
 841                                 max = I40E_MAX_VF - 1;
 842                         for (idx = min; idx <= max; idx++) {
 843                                 vf_floating_veb[idx] = true;
 844                                 count++;
 845                         }
 846                         min = I40E_MAX_VF;
 847                 } else {
 848                         return -1;
 849                 }
 850                 floating_veb_value = end + 1;
 851         } while (*end != '\0');
 852
 853         if (count == 0)
 854                 return -1;
 855
 856         return 0;
 857 }
 858
 859 static void
 860 config_vf_floating_veb(struct rte_devargs *devargs,
 861                        uint16_t floating_veb,
 862                        bool *vf_floating_veb)
 863 {
 864         struct rte_kvargs *kvlist;
 865         int i;
 866         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 867
 868         if (!floating_veb)
 869                 return;
 870         /* All the VFs attach to the floating VEB by default
 871          * when the floating VEB is enabled.
 872          */
 873         for (i = 0; i < I40E_MAX_VF; i++)
 874                 vf_floating_veb[i] = true;
 875
 876         if (devargs == NULL)
 877                 return;
 878
 879         kvlist = rte_kvargs_parse(devargs->args, NULL);
 880         if (kvlist == NULL)
 881                 return;
 882
 883         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 884                 rte_kvargs_free(kvlist);
 885                 return;
 886         }
 887         /* When the floating_veb_list parameter exists, all the VFs
 888          * will attach to the legacy VEB firstly, then configure VFs
 889          * to the floating VEB according to the floating_veb_list.
 890          */
 891         if (rte_kvargs_process(kvlist, floating_veb_list,
 892                                floating_veb_list_handler,
 893                                vf_floating_veb) < 0) {
 894                 rte_kvargs_free(kvlist);
 895                 return;
 896         }
 897         rte_kvargs_free(kvlist);
 898 }
 899
 900 static int
 901 i40e_check_floating_handler(__rte_unused const char *key,
 902                             const char *value,
 903                             __rte_unused void *opaque)
 904 {
 905         if (strcmp(value, "1"))
 906                 return -1;
 907
 908         return 0;
 909 }
 910
 911 static int
 912 is_floating_veb_supported(struct rte_devargs *devargs)
 913 {
 914         struct rte_kvargs *kvlist;
 915         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 916
 917         if (devargs == NULL)
 918                 return 0;
 919
 920         kvlist = rte_kvargs_parse(devargs->args, NULL);
 921         if (kvlist == NULL)
 922                 return 0;
 923
 924         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 925                 rte_kvargs_free(kvlist);
 926                 return 0;
 927         }
 928         /* Floating VEB is enabled when there's key-value:
 929          * enable_floating_veb=1
 930          */
 931         if (rte_kvargs_process(kvlist, floating_veb_key,
 932                                i40e_check_floating_handler, NULL) < 0) {
 933                 rte_kvargs_free(kvlist);
 934                 return 0;
 935         }
 936         rte_kvargs_free(kvlist);
 937
 938         return 1;
 939 }
 940
 941 static void
 942 config_floating_veb(struct rte_eth_dev *dev)
 943 {
 944         struct rte_pci_device *pci_dev = dev->pci_dev;
 945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 946         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947
 948         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 949
 950         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 951                 pf->floating_veb =
 952                         is_floating_veb_supported(pci_dev->device.devargs);
 953                 config_vf_floating_veb(pci_dev->device.devargs,
 954                                        pf->floating_veb,
 955                                        pf->floating_veb_list);
 956         } else {
 957                 pf->floating_veb = false;
 958         }
 959 }
 960
 961 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 962 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 963
 964 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
 965 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
 966                               ETH_I40E_SUPPORT_MULTI_DRIVER "=0|1");
 967
 968 static int
 969 i40e_parse_multi_drv_handler(__rte_unused const char *key,
 970                               const char *value,
 971                               void *opaque)
 972 {
 973         struct i40e_pf *pf;
 974         unsigned long support_multi_driver;
 975         char *end;
 976
 977         pf = (struct i40e_pf *)opaque;
 978
 979         errno = 0;
 980         support_multi_driver = strtoul(value, &end, 10);
 981         if (errno != 0 || end == value || *end != 0) {
 982                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
 983                 return -(EINVAL);
 984         }
 985
 986         if (support_multi_driver == 1 || support_multi_driver == 0)
 987                 pf->support_multi_driver = (bool)support_multi_driver;
 988         else
 989                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
 990                             "enable global configuration by default."
 991                             ETH_I40E_SUPPORT_MULTI_DRIVER);
 992         return 0;
 993 }
 994
 995 static int
 996 i40e_support_multi_driver(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct rte_pci_device *pci_dev = dev->pci_dev;
1000         static const char *valid_keys[] = {
1001                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1002         struct rte_kvargs *kvlist;
1003
1004         /* Enable global configuration by default */
1005         pf->support_multi_driver = false;
1006
1007         if (!pci_dev->device.devargs)
1008                 return 0;
1009
1010         kvlist = rte_kvargs_parse(pci_dev->device.devargs->args, valid_keys);
1011         if (!kvlist)
1012                 return -EINVAL;
1013
1014         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1015                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1016                             "the first invalid or last valid one is used !",
1017                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1018
1019         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1020                                i40e_parse_multi_drv_handler, pf) < 0) {
1021                 rte_kvargs_free(kvlist);
1022                 return -EINVAL;
1023         }
1024
1025         rte_kvargs_free(kvlist);
1026         return 0;
1027 }
1028
1029 static int
1030 eth_i40e_dev_init(struct rte_eth_dev *dev)
1031 {
1032         struct rte_pci_device *pci_dev;
1033         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1034         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1035         struct i40e_vsi *vsi;
1036         int ret;
1037         uint32_t len;
1038         uint8_t aq_fail = 0;
1039
1040         PMD_INIT_FUNC_TRACE();
1041
1042         dev->dev_ops = &i40e_eth_dev_ops;
1043         dev->rx_pkt_burst = i40e_recv_pkts;
1044         dev->tx_pkt_burst = i40e_xmit_pkts;
1045
1046         /* for secondary processes, we don't initialise any further as primary
1047          * has already done this work. Only check we don't need a different
1048          * RX function */
1049         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1050                 i40e_set_rx_function(dev);
1051                 i40e_set_tx_function(dev);
1052                 return 0;
1053         }
1054         pci_dev = dev->pci_dev;
1055
1056         rte_eth_copy_pci_info(dev, pci_dev);
1057
1058         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1059         pf->adapter->eth_dev = dev;
1060         pf->dev_data = dev->data;
1061
1062         hw->back = I40E_PF_TO_ADAPTER(pf);
1063         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1064         if (!hw->hw_addr) {
1065                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1066                              "as address is NULL");
1067                 return -ENODEV;
1068         }
1069
1070         hw->vendor_id = pci_dev->id.vendor_id;
1071         hw->device_id = pci_dev->id.device_id;
1072         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1073         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1074         hw->bus.device = pci_dev->addr.devid;
1075         hw->bus.func = pci_dev->addr.function;
1076         hw->adapter_stopped = 0;
1077
1078         /* Check if need to support multi-driver */
1079         i40e_support_multi_driver(dev);
1080
1081         /* Make sure all is clean before doing PF reset */
1082         i40e_clear_hw(hw);
1083
1084         /* Initialize the hardware */
1085         i40e_hw_init(dev);
1086
1087         /* Reset here to make sure all is clean for each PF */
1088         ret = i40e_pf_reset(hw);
1089         if (ret) {
1090                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1091                 return ret;
1092         }
1093
1094         /* Initialize the shared code (base driver) */
1095         ret = i40e_init_shared_code(hw);
1096         if (ret) {
1097                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1098                 return ret;
1099         }
1100
1101         i40e_config_automask(pf);
1102
1103         /*
1104          * To work around the NVM issue, initialize registers
1105          * for flexible payload and packet type of QinQ by
1106          * software. It should be removed once issues are fixed
1107          * in NVM.
1108          */
1109         if (!pf->support_multi_driver)
1110                 i40e_GLQF_reg_init(hw);
1111
1112         /* Initialize the input set for filters (hash and fd) to default value */
1113         i40e_filter_input_set_init(pf);
1114
1115         /* Initialize the parameters for adminq */
1116         i40e_init_adminq_parameter(hw);
1117         ret = i40e_init_adminq(hw);
1118         if (ret != I40E_SUCCESS) {
1119                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1120                 return -EIO;
1121         }
1122         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1123                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1124                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1125                      ((hw->nvm.version >> 12) & 0xf),
1126                      ((hw->nvm.version >> 4) & 0xff),
1127                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1128
1129         /* Need the special FW version to support floating VEB */
1130         config_floating_veb(dev);
1131         /* Clear PXE mode */
1132         i40e_clear_pxe_mode(hw);
1133         ret = i40e_dev_sync_phy_type(hw);
1134         if (ret) {
1135                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1136                 goto err_sync_phy_type;
1137         }
1138         /*
1139          * On X710, performance number is far from the expectation on recent
1140          * firmware versions. The fix for this issue may not be integrated in
1141          * the following firmware version. So the workaround in software driver
1142          * is needed. It needs to modify the initial values of 3 internal only
1143          * registers. Note that the workaround can be removed when it is fixed
1144          * in firmware in the future.
1145          */
1146         i40e_configure_registers(hw);
1147
1148         /* Get hw capabilities */
1149         ret = i40e_get_cap(hw);
1150         if (ret != I40E_SUCCESS) {
1151                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1152                 goto err_get_capabilities;
1153         }
1154
1155         /* Initialize parameters for PF */
1156         ret = i40e_pf_parameter_init(dev);
1157         if (ret != 0) {
1158                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1159                 goto err_parameter_init;
1160         }
1161
1162         /* Initialize the queue management */
1163         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1164         if (ret < 0) {
1165                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1166                 goto err_qp_pool_init;
1167         }
1168         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1169                                 hw->func_caps.num_msix_vectors - 1);
1170         if (ret < 0) {
1171                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1172                 goto err_msix_pool_init;
1173         }
1174
1175         /* Initialize lan hmc */
1176         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1177                                 hw->func_caps.num_rx_qp, 0, 0);
1178         if (ret != I40E_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1180                 goto err_init_lan_hmc;
1181         }
1182
1183         /* Configure lan hmc */
1184         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1185         if (ret != I40E_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1187                 goto err_configure_lan_hmc;
1188         }
1189
1190         /* Get and check the mac address */
1191         i40e_get_mac_addr(hw, hw->mac.addr);
1192         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1193                 PMD_INIT_LOG(ERR, "mac address is not valid");
1194                 ret = -EIO;
1195                 goto err_get_mac_addr;
1196         }
1197         /* Copy the permanent MAC address */
1198         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1199                         (struct ether_addr *) hw->mac.perm_addr);
1200
1201         /* Disable flow control */
1202         hw->fc.requested_mode = I40E_FC_NONE;
1203         i40e_set_fc(hw, &aq_fail, TRUE);
1204
1205         /* Set the global registers with default ether type value */
1206         if (!pf->support_multi_driver) {
1207                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1208                                          ETHER_TYPE_VLAN);
1209                 if (ret != I40E_SUCCESS) {
1210                         PMD_INIT_LOG(ERR, "Failed to set the default outer "
1211                                      "VLAN ether type");
1212                         goto err_setup_pf_switch;
1213                 }
1214         }
1215
1216         /* PF setup, which includes VSI setup */
1217         ret = i40e_pf_setup(pf);
1218         if (ret) {
1219                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* reset all stats of the device, including pf and main vsi */
1224         i40e_dev_stats_reset(dev);
1225
1226         vsi = pf->main_vsi;
1227
1228         /* Disable double vlan by default */
1229         i40e_vsi_config_double_vlan(vsi, FALSE);
1230
1231         /* Disable S-TAG identification when floating_veb is disabled */
1232         if (!pf->floating_veb) {
1233                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1234                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1235                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1236                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1237                 }
1238         }
1239
1240         if (!vsi->max_macaddrs)
1241                 len = ETHER_ADDR_LEN;
1242         else
1243                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1244
1245         /* Should be after VSI initialized */
1246         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1247         if (!dev->data->mac_addrs) {
1248                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1249                                         "for storing mac address");
1250                 goto err_mac_alloc;
1251         }
1252         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1253                                         &dev->data->mac_addrs[0]);
1254
1255         /* initialize pf host driver to setup SRIOV resource if applicable */
1256         i40e_pf_host_init(dev);
1257
1258         /* register callback func to eal lib */
1259         rte_intr_callback_register(&(pci_dev->intr_handle),
1260                 i40e_dev_interrupt_handler, (void *)dev);
1261
1262         /* configure and enable device interrupt */
1263         i40e_pf_config_irq0(hw, TRUE);
1264         i40e_pf_enable_irq0(hw);
1265
1266         /* enable uio intr after callback register */
1267         rte_intr_enable(&(pci_dev->intr_handle));
1268         /*
1269          * Add an ethertype filter to drop all flow control frames transmitted
1270          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1271          * frames to wire.
1272          */
1273         i40e_add_tx_flow_control_drop_filter(pf);
1274
1275         /* Set the max frame size to 0x2600 by default,
1276          * in case other drivers changed the default value.
1277          */
1278         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1279
1280         /* initialize mirror rule list */
1281         TAILQ_INIT(&pf->mirror_list);
1282
1283         /* Init dcb to sw mode by default */
1284         ret = i40e_dcb_init_configure(dev, TRUE);
1285         if (ret != I40E_SUCCESS) {
1286                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1287                 pf->flags &= ~I40E_FLAG_DCB;
1288         }
1289
1290         return 0;
1291
1292 err_mac_alloc:
1293         i40e_vsi_release(pf->main_vsi);
1294 err_setup_pf_switch:
1295 err_get_mac_addr:
1296 err_configure_lan_hmc:
1297         (void)i40e_shutdown_lan_hmc(hw);
1298 err_init_lan_hmc:
1299         i40e_res_pool_destroy(&pf->msix_pool);
1300 err_msix_pool_init:
1301         i40e_res_pool_destroy(&pf->qp_pool);
1302 err_qp_pool_init:
1303 err_parameter_init:
1304 err_get_capabilities:
1305 err_sync_phy_type:
1306         (void)i40e_shutdown_adminq(hw);
1307
1308         return ret;
1309 }
1310
1311 static int
1312 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1313 {
1314         struct rte_pci_device *pci_dev;
1315         struct i40e_hw *hw;
1316         struct i40e_filter_control_settings settings;
1317         int ret;
1318         uint8_t aq_fail = 0;
1319         int retries = 0;
1320
1321         PMD_INIT_FUNC_TRACE();
1322
1323         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1324                 return 0;
1325
1326         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327         pci_dev = dev->pci_dev;
1328
1329         if (hw->adapter_stopped == 0)
1330                 i40e_dev_close(dev);
1331
1332         dev->dev_ops = NULL;
1333         dev->rx_pkt_burst = NULL;
1334         dev->tx_pkt_burst = NULL;
1335
1336         /* Clear PXE mode */
1337         i40e_clear_pxe_mode(hw);
1338
1339         /* Unconfigure filter control */
1340         memset(&settings, 0, sizeof(settings));
1341         ret = i40e_set_filter_control(hw, &settings);
1342         if (ret)
1343                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1344                                         ret);
1345
1346         /* Disable flow control */
1347         hw->fc.requested_mode = I40E_FC_NONE;
1348         i40e_set_fc(hw, &aq_fail, TRUE);
1349
1350         /* uninitialize pf host driver */
1351         i40e_pf_host_uninit(dev);
1352
1353         rte_free(dev->data->mac_addrs);
1354         dev->data->mac_addrs = NULL;
1355
1356         /* disable uio intr before callback unregister */
1357         rte_intr_disable(&(pci_dev->intr_handle));
1358
1359         /* unregister callback func to eal lib */
1360         do {
1361                 ret = rte_intr_callback_unregister(&(pci_dev->intr_handle),
1362                                 i40e_dev_interrupt_handler, (void *)dev);
1363                 if (ret >= 0) {
1364                         break;
1365                 } else if (ret != -EAGAIN) {
1366                         PMD_INIT_LOG(ERR,
1367                                  "intr callback unregister failed: %d",
1368                                  ret);
1369                         return ret;
1370                 }
1371                 i40e_msec_delay(500);
1372         } while (retries++ < 5);
1373
1374         return 0;
1375 }
1376
1377 static int
1378 i40e_dev_configure(struct rte_eth_dev *dev)
1379 {
1380         struct i40e_adapter *ad =
1381                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1382         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1383         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1384         int i, ret;
1385
1386         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1387          * bulk allocation or vector Rx preconditions we will reset it.
1388          */
1389         ad->rx_bulk_alloc_allowed = true;
1390         ad->rx_vec_allowed = true;
1391         ad->tx_simple_allowed = true;
1392         ad->tx_vec_allowed = true;
1393
1394         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1395                 ret = i40e_fdir_setup(pf);
1396                 if (ret != I40E_SUCCESS) {
1397                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1398                         return -ENOTSUP;
1399                 }
1400                 ret = i40e_fdir_configure(dev);
1401                 if (ret < 0) {
1402                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1403                         goto err;
1404                 }
1405         } else
1406                 i40e_fdir_teardown(pf);
1407
1408         ret = i40e_dev_init_vlan(dev);
1409         if (ret < 0)
1410                 goto err;
1411
1412         /* VMDQ setup.
1413          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1414          *  RSS setting have different requirements.
1415          *  General PMD driver call sequence are NIC init, configure,
1416          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1417          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1418          *  applicable. So, VMDQ setting has to be done before
1419          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1420          *  For RSS setting, it will try to calculate actual configured RX queue
1421          *  number, which will be available after rx_queue_setup(). dev_start()
1422          *  function is good to place RSS setup.
1423          */
1424         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1425                 ret = i40e_vmdq_setup(dev);
1426                 if (ret)
1427                         goto err;
1428         }
1429
1430         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1431                 ret = i40e_dcb_setup(dev);
1432                 if (ret) {
1433                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1434                         goto err_dcb;
1435                 }
1436         }
1437
1438         return 0;
1439
1440 err_dcb:
1441         /* need to release vmdq resource if exists */
1442         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1443                 i40e_vsi_release(pf->vmdq[i].vsi);
1444                 pf->vmdq[i].vsi = NULL;
1445         }
1446         rte_free(pf->vmdq);
1447         pf->vmdq = NULL;
1448 err:
1449         /* need to release fdir resource if exists */
1450         i40e_fdir_teardown(pf);
1451         return ret;
1452 }
1453
1454 void
1455 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1456 {
1457         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1458         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1459         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1460         uint16_t msix_vect = vsi->msix_intr;
1461         uint16_t i;
1462
1463         for (i = 0; i < vsi->nb_qps; i++) {
1464                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1465                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1466                 rte_wmb();
1467         }
1468
1469         if (vsi->type != I40E_VSI_SRIOV) {
1470                 if (!rte_intr_allow_others(intr_handle)) {
1471                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1472                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1473                         I40E_WRITE_REG(hw,
1474                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1475                                        0);
1476                 } else {
1477                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1478                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1479                         I40E_WRITE_REG(hw,
1480                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1481                                                        msix_vect - 1), 0);
1482                 }
1483         } else {
1484                 uint32_t reg;
1485                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1486                         vsi->user_param + (msix_vect - 1);
1487
1488                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1489                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1490         }
1491         I40E_WRITE_FLUSH(hw);
1492 }
1493
1494 static void
1495 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1496                        int base_queue, int nb_queue)
1497 {
1498         int i;
1499         uint32_t val;
1500         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1501         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1502
1503         /* Bind all RX queues to allocated MSIX interrupt */
1504         for (i = 0; i < nb_queue; i++) {
1505                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1506                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1507                         ((base_queue + i + 1) <<
1508                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1509                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1510                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1511
1512                 if (i == nb_queue - 1)
1513                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1514                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1515         }
1516
1517         /* Write first RX queue to Link list register as the head element */
1518         if (vsi->type != I40E_VSI_SRIOV) {
1519                 uint16_t interval =
1520                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL,
1521                                                pf->support_multi_driver);
1522
1523                 if (msix_vect == I40E_MISC_VEC_ID) {
1524                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1525                                        (base_queue <<
1526                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1527                                        (0x0 <<
1528                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1529                         I40E_WRITE_REG(hw,
1530                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1531                                        interval);
1532                 } else {
1533                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1534                                        (base_queue <<
1535                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1536                                        (0x0 <<
1537                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1538                         I40E_WRITE_REG(hw,
1539                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1540                                                        msix_vect - 1),
1541                                        interval);
1542                 }
1543         } else {
1544                 uint32_t reg;
1545
1546                 if (msix_vect == I40E_MISC_VEC_ID) {
1547                         I40E_WRITE_REG(hw,
1548                                        I40E_VPINT_LNKLST0(vsi->user_param),
1549                                        (base_queue <<
1550                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1551                                        (0x0 <<
1552                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1553                 } else {
1554                         /* num_msix_vectors_vf needs to minus irq0 */
1555                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1556                                 vsi->user_param + (msix_vect - 1);
1557
1558                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1559                                        (base_queue <<
1560                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1561                                        (0x0 <<
1562                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1563                 }
1564         }
1565
1566         I40E_WRITE_FLUSH(hw);
1567 }
1568
1569 void
1570 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1571 {
1572         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1573         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1574         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1575         uint16_t msix_vect = vsi->msix_intr;
1576         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1577         uint16_t queue_idx = 0;
1578         int record = 0;
1579         int i;
1580
1581         for (i = 0; i < vsi->nb_qps; i++) {
1582                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1583                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1584         }
1585
1586         /* VF bind interrupt */
1587         if (vsi->type == I40E_VSI_SRIOV) {
1588                 __vsi_queues_bind_intr(vsi, msix_vect,
1589                                        vsi->base_queue, vsi->nb_qps);
1590                 return;
1591         }
1592
1593         /* PF & VMDq bind interrupt */
1594         if (rte_intr_dp_is_en(intr_handle)) {
1595                 if (vsi->type == I40E_VSI_MAIN) {
1596                         queue_idx = 0;
1597                         record = 1;
1598                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1599                         struct i40e_vsi *main_vsi =
1600                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1601                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1602                         record = 1;
1603                 }
1604         }
1605
1606         for (i = 0; i < vsi->nb_used_qps; i++) {
1607                 if (nb_msix <= 1) {
1608                         if (!rte_intr_allow_others(intr_handle))
1609                                 /* allow to share MISC_VEC_ID */
1610                                 msix_vect = I40E_MISC_VEC_ID;
1611
1612                         /* no enough msix_vect, map all to one */
1613                         __vsi_queues_bind_intr(vsi, msix_vect,
1614                                                vsi->base_queue + i,
1615                                                vsi->nb_used_qps - i);
1616                         for (; !!record && i < vsi->nb_used_qps; i++)
1617                                 intr_handle->intr_vec[queue_idx + i] =
1618                                         msix_vect;
1619                         break;
1620                 }
1621                 /* 1:1 queue/msix_vect mapping */
1622                 __vsi_queues_bind_intr(vsi, msix_vect,
1623                                        vsi->base_queue + i, 1);
1624                 if (!!record)
1625                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1626
1627                 msix_vect++;
1628                 nb_msix--;
1629         }
1630 }
1631
1632 static void
1633 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1634 {
1635         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1636         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1638         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1639         uint16_t msix_intr, i;
1640
1641         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1642                 for (i = 0; i < vsi->nb_msix; i++) {
1643                         msix_intr = vsi->msix_intr + i;
1644                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1645                                        I40E_PFINT_DYN_CTLN_INTENA_MASK |
1646                                        I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1647                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1648                 }
1649         else
1650                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1651                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1652                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1653                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1654
1655         I40E_WRITE_FLUSH(hw);
1656 }
1657
1658 static void
1659 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1660 {
1661         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1662         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1663         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1664         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1665         uint16_t msix_intr, i;
1666
1667         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1668                 for (i = 0; i < vsi->nb_msix; i++) {
1669                         msix_intr = vsi->msix_intr + i;
1670                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1671                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1672                 }
1673         else
1674                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1675                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1676
1677         I40E_WRITE_FLUSH(hw);
1678 }
1679
1680 static inline uint8_t
1681 i40e_parse_link_speeds(uint16_t link_speeds)
1682 {
1683         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1684
1685         if (link_speeds & ETH_LINK_SPEED_40G)
1686                 link_speed |= I40E_LINK_SPEED_40GB;
1687         if (link_speeds & ETH_LINK_SPEED_25G)
1688                 link_speed |= I40E_LINK_SPEED_25GB;
1689         if (link_speeds & ETH_LINK_SPEED_20G)
1690                 link_speed |= I40E_LINK_SPEED_20GB;
1691         if (link_speeds & ETH_LINK_SPEED_10G)
1692                 link_speed |= I40E_LINK_SPEED_10GB;
1693         if (link_speeds & ETH_LINK_SPEED_1G)
1694                 link_speed |= I40E_LINK_SPEED_1GB;
1695         if (link_speeds & ETH_LINK_SPEED_100M)
1696                 link_speed |= I40E_LINK_SPEED_100MB;
1697
1698         return link_speed;
1699 }
1700
1701 static int
1702 i40e_phy_conf_link(struct i40e_hw *hw,
1703                    uint8_t abilities,
1704                    uint8_t force_speed,
1705                    bool is_up)
1706 {
1707         enum i40e_status_code status;
1708         struct i40e_aq_get_phy_abilities_resp phy_ab;
1709         struct i40e_aq_set_phy_config phy_conf;
1710         enum i40e_aq_phy_type cnt;
1711         uint8_t avail_speed;
1712         uint32_t phy_type_mask = 0;
1713
1714         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1715                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1716                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1717                         I40E_AQ_PHY_FLAG_LOW_POWER;
1718         int ret = -ENOTSUP;
1719
1720         /* To get phy capabilities of available speeds. */
1721         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
1722                                               NULL);
1723         if (status) {
1724                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
1725                                 status);
1726                 return ret;
1727         }
1728         avail_speed = phy_ab.link_speed;
1729
1730         /* To get the current phy config. */
1731         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1732                                               NULL);
1733         if (status) {
1734                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
1735                                 status);
1736                 return ret;
1737         }
1738
1739         /* If link needs to go up and it is in autoneg mode the speed is OK,
1740          * no need to set up again.
1741          */
1742         if (is_up && phy_ab.phy_type != 0 &&
1743                      abilities & I40E_AQ_PHY_AN_ENABLED &&
1744                      phy_ab.link_speed != 0)
1745                 return I40E_SUCCESS;
1746
1747         memset(&phy_conf, 0, sizeof(phy_conf));
1748
1749         /* bits 0-2 use the values from get_phy_abilities_resp */
1750         abilities &= ~mask;
1751         abilities |= phy_ab.abilities & mask;
1752
1753         phy_conf.abilities = abilities;
1754
1755         /* If link needs to go up, but the force speed is not supported,
1756          * Warn users and config the default available speeds.
1757          */
1758         if (is_up && !(force_speed & avail_speed)) {
1759                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
1760                 phy_conf.link_speed = avail_speed;
1761         } else {
1762                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
1763         }
1764
1765         /* PHY type mask needs to include each type except PHY type extension */
1766         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
1767                 phy_type_mask |= 1 << cnt;
1768
1769         /* use get_phy_abilities_resp value for the rest */
1770         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1771         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1772                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1773                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1774         phy_conf.fec_config = phy_ab.mod_type_ext;
1775         phy_conf.eee_capability = phy_ab.eee_capability;
1776         phy_conf.eeer = phy_ab.eeer_val;
1777         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1778
1779         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1780                     phy_ab.abilities, phy_ab.link_speed);
1781         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1782                     phy_conf.abilities, phy_conf.link_speed);
1783
1784         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1785         if (status)
1786                 return ret;
1787
1788         return I40E_SUCCESS;
1789 }
1790
1791 static int
1792 i40e_apply_link_speed(struct rte_eth_dev *dev)
1793 {
1794         uint8_t speed;
1795         uint8_t abilities = 0;
1796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797         struct rte_eth_conf *conf = &dev->data->dev_conf;
1798
1799         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
1800                 conf->link_speeds = ETH_LINK_SPEED_40G |
1801                                     ETH_LINK_SPEED_25G |
1802                                     ETH_LINK_SPEED_20G |
1803                                     ETH_LINK_SPEED_10G |
1804                                     ETH_LINK_SPEED_1G |
1805                                     ETH_LINK_SPEED_100M;
1806         }
1807         speed = i40e_parse_link_speeds(conf->link_speeds);
1808         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
1809                      I40E_AQ_PHY_AN_ENABLED |
1810                      I40E_AQ_PHY_LINK_ENABLED;
1811
1812         return i40e_phy_conf_link(hw, abilities, speed, true);
1813 }
1814
1815 static int
1816 i40e_dev_start(struct rte_eth_dev *dev)
1817 {
1818         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820         struct i40e_vsi *main_vsi = pf->main_vsi;
1821         int ret, i;
1822         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1823         uint32_t intr_vector = 0;
1824
1825         hw->adapter_stopped = 0;
1826
1827         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1828                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1829                              dev->data->port_id);
1830                 return -EINVAL;
1831         }
1832
1833         rte_intr_disable(intr_handle);
1834
1835         if ((rte_intr_cap_multiple(intr_handle) ||
1836              !RTE_ETH_DEV_SRIOV(dev).active) &&
1837             dev->data->dev_conf.intr_conf.rxq != 0) {
1838                 intr_vector = dev->data->nb_rx_queues;
1839                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1840                         return -1;
1841         }
1842
1843         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1844                 intr_handle->intr_vec =
1845                         rte_zmalloc("intr_vec",
1846                                     dev->data->nb_rx_queues * sizeof(int),
1847                                     0);
1848                 if (!intr_handle->intr_vec) {
1849                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1850                                      " intr_vec\n", dev->data->nb_rx_queues);
1851                         return -ENOMEM;
1852                 }
1853         }
1854
1855         /* Initialize VSI */
1856         ret = i40e_dev_rxtx_init(pf);
1857         if (ret != I40E_SUCCESS) {
1858                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1859                 goto err_up;
1860         }
1861
1862         /* Map queues with MSIX interrupt */
1863         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1864                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1865         i40e_vsi_queues_bind_intr(main_vsi);
1866         i40e_vsi_enable_queues_intr(main_vsi);
1867
1868         /* Map VMDQ VSI queues with MSIX interrupt */
1869         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1870                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1871                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1872                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1873         }
1874
1875         /* enable FDIR MSIX interrupt */
1876         if (pf->fdir.fdir_vsi) {
1877                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1878                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1879         }
1880
1881         /* Enable all queues which have been configured */
1882         ret = i40e_dev_switch_queues(pf, TRUE);
1883         if (ret != I40E_SUCCESS) {
1884                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1885                 goto err_up;
1886         }
1887
1888         /* Enable receiving broadcast packets */
1889         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1890         if (ret != I40E_SUCCESS)
1891                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1892
1893         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1894                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1895                                                 true, NULL);
1896                 if (ret != I40E_SUCCESS)
1897                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1898         }
1899
1900         /* Apply link configure */
1901         ret = i40e_apply_link_speed(dev);
1902         if (I40E_SUCCESS != ret) {
1903                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1904                 goto err_up;
1905         }
1906
1907         if (!rte_intr_allow_others(intr_handle)) {
1908                 rte_intr_callback_unregister(intr_handle,
1909                                              i40e_dev_interrupt_handler,
1910                                              (void *)dev);
1911                 /* configure and enable device interrupt */
1912                 i40e_pf_config_irq0(hw, FALSE);
1913                 i40e_pf_enable_irq0(hw);
1914
1915                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1916                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1917                                      " no intr multiplex\n");
1918         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1919                 ret = i40e_aq_set_phy_int_mask(hw,
1920                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1921                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1922                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1923                 if (ret != I40E_SUCCESS)
1924                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1925
1926                 /* Call get_link_info aq commond to enable LSE */
1927                 i40e_dev_link_update(dev, 0);
1928         }
1929
1930         /* enable uio intr after callback register */
1931         rte_intr_enable(intr_handle);
1932
1933         return I40E_SUCCESS;
1934
1935 err_up:
1936         i40e_dev_switch_queues(pf, FALSE);
1937         i40e_dev_clear_queues(dev);
1938
1939         return ret;
1940 }
1941
1942 static void
1943 i40e_dev_stop(struct rte_eth_dev *dev)
1944 {
1945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1946         struct i40e_vsi *main_vsi = pf->main_vsi;
1947         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1948         int i;
1949
1950         /* Disable all queues */
1951         i40e_dev_switch_queues(pf, FALSE);
1952
1953         /* un-map queues with interrupt registers */
1954         i40e_vsi_disable_queues_intr(main_vsi);
1955         i40e_vsi_queues_unbind_intr(main_vsi);
1956
1957         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1958                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1959                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1960         }
1961
1962         if (pf->fdir.fdir_vsi) {
1963                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1964                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1965         }
1966         /* Clear all queues and release memory */
1967         i40e_dev_clear_queues(dev);
1968
1969         /* Set link down */
1970         i40e_dev_set_link_down(dev);
1971
1972         if (!rte_intr_allow_others(intr_handle))
1973                 /* resume to the default handler */
1974                 rte_intr_callback_register(intr_handle,
1975                                            i40e_dev_interrupt_handler,
1976                                            (void *)dev);
1977
1978         /* Clean datapath event and queue/vec mapping */
1979         rte_intr_efd_disable(intr_handle);
1980         if (intr_handle->intr_vec) {
1981                 rte_free(intr_handle->intr_vec);
1982                 intr_handle->intr_vec = NULL;
1983         }
1984 }
1985
1986 static void
1987 i40e_dev_close(struct rte_eth_dev *dev)
1988 {
1989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         struct i40e_mirror_rule *p_mirror;
1992         uint32_t reg;
1993         int i;
1994         int ret;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         i40e_dev_stop(dev);
1999         hw->adapter_stopped = 1;
2000
2001         /* Remove all mirror rules */
2002         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2003                 ret = i40e_aq_del_mirror_rule(hw,
2004                                               pf->main_vsi->veb->seid,
2005                                               p_mirror->rule_type,
2006                                               p_mirror->entries,
2007                                               p_mirror->num_entries,
2008                                               p_mirror->id);
2009                 if (ret < 0)
2010                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2011                                     "status = %d, aq_err = %d.", ret,
2012                                     hw->aq.asq_last_status);
2013
2014                 /* remove mirror software resource anyway */
2015                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2016                 rte_free(p_mirror);
2017                 pf->nb_mirror_rule--;
2018         }
2019
2020         i40e_dev_free_queues(dev);
2021
2022         /* Disable interrupt */
2023         i40e_pf_disable_irq0(hw);
2024         rte_intr_disable(&(dev->pci_dev->intr_handle));
2025
2026         i40e_fdir_teardown(pf);
2027
2028         /* shutdown and destroy the HMC */
2029         i40e_shutdown_lan_hmc(hw);
2030
2031         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2032                 i40e_vsi_release(pf->vmdq[i].vsi);
2033                 pf->vmdq[i].vsi = NULL;
2034         }
2035         rte_free(pf->vmdq);
2036         pf->vmdq = NULL;
2037
2038         /* release all the existing VSIs and VEBs */
2039         i40e_vsi_release(pf->main_vsi);
2040
2041         /* shutdown the adminq */
2042         i40e_aq_queue_shutdown(hw, true);
2043         i40e_shutdown_adminq(hw);
2044
2045         i40e_res_pool_destroy(&pf->qp_pool);
2046         i40e_res_pool_destroy(&pf->msix_pool);
2047
2048         /* force a PF reset to clean anything leftover */
2049         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2050         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2051                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2052         I40E_WRITE_FLUSH(hw);
2053 }
2054
2055 static void
2056 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2057 {
2058         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         struct i40e_vsi *vsi = pf->main_vsi;
2061         int status;
2062
2063         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2064                                                      true, NULL, true);
2065         if (status != I40E_SUCCESS)
2066                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2067
2068         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2069                                                         TRUE, NULL);
2070         if (status != I40E_SUCCESS)
2071                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2072
2073 }
2074
2075 static void
2076 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2077 {
2078         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         struct i40e_vsi *vsi = pf->main_vsi;
2081         int status;
2082
2083         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2084                                                      false, NULL, true);
2085         if (status != I40E_SUCCESS)
2086                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2087
2088         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2089                                                         false, NULL);
2090         if (status != I40E_SUCCESS)
2091                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2092 }
2093
2094 static void
2095 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2096 {
2097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2098         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         struct i40e_vsi *vsi = pf->main_vsi;
2100         int ret;
2101
2102         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2103         if (ret != I40E_SUCCESS)
2104                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2105 }
2106
2107 static void
2108 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2109 {
2110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2111         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112         struct i40e_vsi *vsi = pf->main_vsi;
2113         int ret;
2114
2115         if (dev->data->promiscuous == 1)
2116                 return; /* must remain in all_multicast mode */
2117
2118         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2119                                 vsi->seid, FALSE, NULL);
2120         if (ret != I40E_SUCCESS)
2121                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2122 }
2123
2124 /*
2125  * Set device link up.
2126  */
2127 static int
2128 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2129 {
2130         /* re-apply link speed setting */
2131         return i40e_apply_link_speed(dev);
2132 }
2133
2134 /*
2135  * Set device link down.
2136  */
2137 static int
2138 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2139 {
2140         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2141         uint8_t abilities = 0;
2142         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143
2144         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2145         return i40e_phy_conf_link(hw, abilities, speed, false);
2146 }
2147
2148 static inline void __attribute__((always_inline))
2149 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2150 {
2151 /* Link status registers and values*/
2152 #define I40E_PRTMAC_LINKSTA             0x001E2420
2153 #define I40E_REG_LINK_UP                0x40000080
2154 #define I40E_PRTMAC_MACC                0x001E24E0
2155 #define I40E_REG_MACC_25GB              0x00020000
2156 #define I40E_REG_SPEED_MASK             0x38000000
2157 #define I40E_REG_SPEED_100MB            0x00000000
2158 #define I40E_REG_SPEED_1GB              0x08000000
2159 #define I40E_REG_SPEED_10GB             0x10000000
2160 #define I40E_REG_SPEED_20GB             0x20000000
2161 #define I40E_REG_SPEED_25_40GB          0x18000000
2162         uint32_t link_speed;
2163         uint32_t reg_val;
2164
2165         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2166         link_speed = reg_val & I40E_REG_SPEED_MASK;
2167         reg_val &= I40E_REG_LINK_UP;
2168         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2169
2170         if (unlikely(link->link_status == 0))
2171                 return;
2172
2173         /* Parse the link status */
2174         switch (link_speed) {
2175         case I40E_REG_SPEED_100MB:
2176                 link->link_speed = ETH_SPEED_NUM_100M;
2177                 break;
2178         case I40E_REG_SPEED_1GB:
2179                 link->link_speed = ETH_SPEED_NUM_1G;
2180                 break;
2181         case I40E_REG_SPEED_10GB:
2182                 link->link_speed = ETH_SPEED_NUM_10G;
2183                 break;
2184         case I40E_REG_SPEED_20GB:
2185                 link->link_speed = ETH_SPEED_NUM_20G;
2186                 break;
2187         case I40E_REG_SPEED_25_40GB:
2188                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2189
2190                 if (reg_val & I40E_REG_MACC_25GB)
2191                         link->link_speed = ETH_SPEED_NUM_25G;
2192                 else
2193                         link->link_speed = ETH_SPEED_NUM_40G;
2194
2195                 break;
2196         default:
2197                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2198                 break;
2199         }
2200 }
2201
2202 static inline void __attribute__((always_inline))
2203 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2204         bool enable_lse)
2205 {
2206 #define CHECK_INTERVAL             100  /* 100ms */
2207 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2208         uint32_t rep_cnt = MAX_REPEAT_TIME;
2209         struct i40e_link_status link_status;
2210         int status;
2211
2212         memset(&link_status, 0, sizeof(link_status));
2213
2214         do {
2215                 /* Get link status information from hardware */
2216                 status = i40e_aq_get_link_info(hw, enable_lse,
2217                                                 &link_status, NULL);
2218                 if (unlikely(status != I40E_SUCCESS)) {
2219                         link->link_speed = ETH_SPEED_NUM_100M;
2220                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2221                         PMD_DRV_LOG(ERR, "Failed to get link info");
2222                         return;
2223                 }
2224
2225                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2226                 if (unlikely(link->link_status != 0))
2227                         break;
2228
2229                 rte_delay_ms(CHECK_INTERVAL);
2230         } while (--rep_cnt);
2231
2232         /* Parse the link status */
2233         switch (link_status.link_speed) {
2234         case I40E_LINK_SPEED_100MB:
2235                 link->link_speed = ETH_SPEED_NUM_100M;
2236                 break;
2237         case I40E_LINK_SPEED_1GB:
2238                 link->link_speed = ETH_SPEED_NUM_1G;
2239                 break;
2240         case I40E_LINK_SPEED_10GB:
2241                 link->link_speed = ETH_SPEED_NUM_10G;
2242                 break;
2243         case I40E_LINK_SPEED_20GB:
2244                 link->link_speed = ETH_SPEED_NUM_20G;
2245                 break;
2246         case I40E_LINK_SPEED_25GB:
2247                 link->link_speed = ETH_SPEED_NUM_25G;
2248                 break;
2249         case I40E_LINK_SPEED_40GB:
2250                 link->link_speed = ETH_SPEED_NUM_40G;
2251                 break;
2252         default:
2253                 link->link_speed = ETH_SPEED_NUM_100M;
2254                 break;
2255         }
2256 }
2257
2258 int
2259 i40e_dev_link_update(struct rte_eth_dev *dev,
2260                      int wait_to_complete)
2261 {
2262         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263         struct rte_eth_link link, old;
2264         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2265
2266         memset(&link, 0, sizeof(link));
2267         memset(&old, 0, sizeof(old));
2268
2269         rte_i40e_dev_atomic_read_link_status(dev, &old);
2270
2271         /* i40e uses full duplex only */
2272         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2273         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2274                         ETH_LINK_SPEED_FIXED);
2275
2276         if (!wait_to_complete)
2277                 update_link_no_wait(hw, &link);
2278         else
2279                 update_link_wait(hw, &link, enable_lse);
2280
2281         rte_i40e_dev_atomic_write_link_status(dev, &link);
2282         if (link.link_status == old.link_status)
2283                 return -1;
2284
2285         i40e_notify_all_vfs_link_status(dev);
2286
2287         return 0;
2288 }
2289
2290 /* Get all the statistics of a VSI */
2291 void
2292 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2293 {
2294         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2295         struct i40e_eth_stats *nes = &vsi->eth_stats;
2296         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2297         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2298
2299         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2300                             vsi->offset_loaded, &oes->rx_bytes,
2301                             &nes->rx_bytes);
2302         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2303                             vsi->offset_loaded, &oes->rx_unicast,
2304                             &nes->rx_unicast);
2305         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2306                             vsi->offset_loaded, &oes->rx_multicast,
2307                             &nes->rx_multicast);
2308         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2309                             vsi->offset_loaded, &oes->rx_broadcast,
2310                             &nes->rx_broadcast);
2311         /* exclude CRC bytes */
2312         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2313                 nes->rx_broadcast) * ETHER_CRC_LEN;
2314
2315         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2316                             &oes->rx_discards, &nes->rx_discards);
2317         /* GLV_REPC not supported */
2318         /* GLV_RMPC not supported */
2319         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2320                             &oes->rx_unknown_protocol,
2321                             &nes->rx_unknown_protocol);
2322         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2323                             vsi->offset_loaded, &oes->tx_bytes,
2324                             &nes->tx_bytes);
2325         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2326                             vsi->offset_loaded, &oes->tx_unicast,
2327                             &nes->tx_unicast);
2328         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2329                             vsi->offset_loaded, &oes->tx_multicast,
2330                             &nes->tx_multicast);
2331         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2332                             vsi->offset_loaded,  &oes->tx_broadcast,
2333                             &nes->tx_broadcast);
2334         /* exclude CRC bytes */
2335         nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2336                 nes->tx_broadcast) * ETHER_CRC_LEN;
2337         /* GLV_TDPC not supported */
2338         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2339                             &oes->tx_errors, &nes->tx_errors);
2340         vsi->offset_loaded = true;
2341
2342         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2343                     vsi->vsi_id);
2344         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2345         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2346         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2347         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2348         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2349         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2350                     nes->rx_unknown_protocol);
2351         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2352         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2353         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2354         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2355         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2356         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2357         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2358                     vsi->vsi_id);
2359 }
2360
2361 static void
2362 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2363 {
2364         unsigned int i;
2365         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2366         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2367
2368         /* Get rx/tx bytes of internal transfer packets */
2369         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2370                         I40E_GLV_GORCL(hw->port),
2371                         pf->offset_loaded,
2372                         &pf->internal_rx_bytes_offset,
2373                         &pf->internal_rx_bytes);
2374
2375         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2376                         I40E_GLV_GOTCL(hw->port),
2377                         pf->offset_loaded,
2378                         &pf->internal_tx_bytes_offset,
2379                         &pf->internal_tx_bytes);
2380
2381         /* Get statistics of struct i40e_eth_stats */
2382         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2383                             I40E_GLPRT_GORCL(hw->port),
2384                             pf->offset_loaded, &os->eth.rx_bytes,
2385                             &ns->eth.rx_bytes);
2386         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2387                             I40E_GLPRT_UPRCL(hw->port),
2388                             pf->offset_loaded, &os->eth.rx_unicast,
2389                             &ns->eth.rx_unicast);
2390         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2391                             I40E_GLPRT_MPRCL(hw->port),
2392                             pf->offset_loaded, &os->eth.rx_multicast,
2393                             &ns->eth.rx_multicast);
2394         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2395                             I40E_GLPRT_BPRCL(hw->port),
2396                             pf->offset_loaded, &os->eth.rx_broadcast,
2397                             &ns->eth.rx_broadcast);
2398         /* Workaround: CRC size should not be included in byte statistics,
2399          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2400          */
2401         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2402                 ns->eth.rx_broadcast) * ETHER_CRC_LEN + pf->internal_rx_bytes;
2403
2404         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2405                             pf->offset_loaded, &os->eth.rx_discards,
2406                             &ns->eth.rx_discards);
2407         /* GLPRT_REPC not supported */
2408         /* GLPRT_RMPC not supported */
2409         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2410                             pf->offset_loaded,
2411                             &os->eth.rx_unknown_protocol,
2412                             &ns->eth.rx_unknown_protocol);
2413         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2414                             I40E_GLPRT_GOTCL(hw->port),
2415                             pf->offset_loaded, &os->eth.tx_bytes,
2416                             &ns->eth.tx_bytes);
2417         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2418                             I40E_GLPRT_UPTCL(hw->port),
2419                             pf->offset_loaded, &os->eth.tx_unicast,
2420                             &ns->eth.tx_unicast);
2421         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2422                             I40E_GLPRT_MPTCL(hw->port),
2423                             pf->offset_loaded, &os->eth.tx_multicast,
2424                             &ns->eth.tx_multicast);
2425         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2426                             I40E_GLPRT_BPTCL(hw->port),
2427                             pf->offset_loaded, &os->eth.tx_broadcast,
2428                             &ns->eth.tx_broadcast);
2429         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2430                 ns->eth.tx_broadcast) * ETHER_CRC_LEN + pf->internal_tx_bytes;
2431         /* GLPRT_TEPC not supported */
2432
2433         /* additional port specific stats */
2434         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2435                             pf->offset_loaded, &os->tx_dropped_link_down,
2436                             &ns->tx_dropped_link_down);
2437         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2438                             pf->offset_loaded, &os->crc_errors,
2439                             &ns->crc_errors);
2440         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2441                             pf->offset_loaded, &os->illegal_bytes,
2442                             &ns->illegal_bytes);
2443         /* GLPRT_ERRBC not supported */
2444         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2445                             pf->offset_loaded, &os->mac_local_faults,
2446                             &ns->mac_local_faults);
2447         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2448                             pf->offset_loaded, &os->mac_remote_faults,
2449                             &ns->mac_remote_faults);
2450         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2451                             pf->offset_loaded, &os->rx_length_errors,
2452                             &ns->rx_length_errors);
2453         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2454                             pf->offset_loaded, &os->link_xon_rx,
2455                             &ns->link_xon_rx);
2456         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2457                             pf->offset_loaded, &os->link_xoff_rx,
2458                             &ns->link_xoff_rx);
2459         for (i = 0; i < 8; i++) {
2460                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2461                                     pf->offset_loaded,
2462                                     &os->priority_xon_rx[i],
2463                                     &ns->priority_xon_rx[i]);
2464                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2465                                     pf->offset_loaded,
2466                                     &os->priority_xoff_rx[i],
2467                                     &ns->priority_xoff_rx[i]);
2468         }
2469         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2470                             pf->offset_loaded, &os->link_xon_tx,
2471                             &ns->link_xon_tx);
2472         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2473                             pf->offset_loaded, &os->link_xoff_tx,
2474                             &ns->link_xoff_tx);
2475         for (i = 0; i < 8; i++) {
2476                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2477                                     pf->offset_loaded,
2478                                     &os->priority_xon_tx[i],
2479                                     &ns->priority_xon_tx[i]);
2480                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2481                                     pf->offset_loaded,
2482                                     &os->priority_xoff_tx[i],
2483                                     &ns->priority_xoff_tx[i]);
2484                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2485                                     pf->offset_loaded,
2486                                     &os->priority_xon_2_xoff[i],
2487                                     &ns->priority_xon_2_xoff[i]);
2488         }
2489         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2490                             I40E_GLPRT_PRC64L(hw->port),
2491                             pf->offset_loaded, &os->rx_size_64,
2492                             &ns->rx_size_64);
2493         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2494                             I40E_GLPRT_PRC127L(hw->port),
2495                             pf->offset_loaded, &os->rx_size_127,
2496                             &ns->rx_size_127);
2497         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2498                             I40E_GLPRT_PRC255L(hw->port),
2499                             pf->offset_loaded, &os->rx_size_255,
2500                             &ns->rx_size_255);
2501         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2502                             I40E_GLPRT_PRC511L(hw->port),
2503                             pf->offset_loaded, &os->rx_size_511,
2504                             &ns->rx_size_511);
2505         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2506                             I40E_GLPRT_PRC1023L(hw->port),
2507                             pf->offset_loaded, &os->rx_size_1023,
2508                             &ns->rx_size_1023);
2509         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2510                             I40E_GLPRT_PRC1522L(hw->port),
2511                             pf->offset_loaded, &os->rx_size_1522,
2512                             &ns->rx_size_1522);
2513         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2514                             I40E_GLPRT_PRC9522L(hw->port),
2515                             pf->offset_loaded, &os->rx_size_big,
2516                             &ns->rx_size_big);
2517         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2518                             pf->offset_loaded, &os->rx_undersize,
2519                             &ns->rx_undersize);
2520         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2521                             pf->offset_loaded, &os->rx_fragments,
2522                             &ns->rx_fragments);
2523         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2524                             pf->offset_loaded, &os->rx_oversize,
2525                             &ns->rx_oversize);
2526         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2527                             pf->offset_loaded, &os->rx_jabber,
2528                             &ns->rx_jabber);
2529         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2530                             I40E_GLPRT_PTC64L(hw->port),
2531                             pf->offset_loaded, &os->tx_size_64,
2532                             &ns->tx_size_64);
2533         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2534                             I40E_GLPRT_PTC127L(hw->port),
2535                             pf->offset_loaded, &os->tx_size_127,
2536                             &ns->tx_size_127);
2537         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2538                             I40E_GLPRT_PTC255L(hw->port),
2539                             pf->offset_loaded, &os->tx_size_255,
2540                             &ns->tx_size_255);
2541         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2542                             I40E_GLPRT_PTC511L(hw->port),
2543                             pf->offset_loaded, &os->tx_size_511,
2544                             &ns->tx_size_511);
2545         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2546                             I40E_GLPRT_PTC1023L(hw->port),
2547                             pf->offset_loaded, &os->tx_size_1023,
2548                             &ns->tx_size_1023);
2549         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2550                             I40E_GLPRT_PTC1522L(hw->port),
2551                             pf->offset_loaded, &os->tx_size_1522,
2552                             &ns->tx_size_1522);
2553         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2554                             I40E_GLPRT_PTC9522L(hw->port),
2555                             pf->offset_loaded, &os->tx_size_big,
2556                             &ns->tx_size_big);
2557         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2558                            pf->offset_loaded,
2559                            &os->fd_sb_match, &ns->fd_sb_match);
2560         /* GLPRT_MSPDC not supported */
2561         /* GLPRT_XEC not supported */
2562
2563         pf->offset_loaded = true;
2564
2565         if (pf->main_vsi)
2566                 i40e_update_vsi_stats(pf->main_vsi);
2567 }
2568
2569 /* Get all statistics of a port */
2570 static void
2571 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2572 {
2573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2574         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2576         unsigned i;
2577
2578         /* call read registers - updates values, now write them to struct */
2579         i40e_read_stats_registers(pf, hw);
2580
2581         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2582                         pf->main_vsi->eth_stats.rx_multicast +
2583                         pf->main_vsi->eth_stats.rx_broadcast -
2584                         pf->main_vsi->eth_stats.rx_discards;
2585         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2586                         pf->main_vsi->eth_stats.tx_multicast +
2587                         pf->main_vsi->eth_stats.tx_broadcast;
2588         stats->ibytes   = ns->eth.rx_bytes;
2589         stats->obytes   = ns->eth.tx_bytes;
2590         stats->oerrors  = ns->eth.tx_errors +
2591                         pf->main_vsi->eth_stats.tx_errors;
2592
2593         /* Rx Errors */
2594         stats->imissed  = ns->eth.rx_discards +
2595                         pf->main_vsi->eth_stats.rx_discards;
2596         stats->ierrors  = ns->crc_errors +
2597                         ns->rx_length_errors + ns->rx_undersize +
2598                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2599
2600         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2601         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2602         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2603         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2604         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2605         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2606         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2607                     ns->eth.rx_unknown_protocol);
2608         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2609         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2610         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2611         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2612         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2613         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2614
2615         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2616                     ns->tx_dropped_link_down);
2617         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2618         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2619                     ns->illegal_bytes);
2620         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2621         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2622                     ns->mac_local_faults);
2623         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2624                     ns->mac_remote_faults);
2625         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2626                     ns->rx_length_errors);
2627         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2628         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2629         for (i = 0; i < 8; i++) {
2630                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2631                                 i, ns->priority_xon_rx[i]);
2632                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2633                                 i, ns->priority_xoff_rx[i]);
2634         }
2635         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2636         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2637         for (i = 0; i < 8; i++) {
2638                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2639                                 i, ns->priority_xon_tx[i]);
2640                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2641                                 i, ns->priority_xoff_tx[i]);
2642                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2643                                 i, ns->priority_xon_2_xoff[i]);
2644         }
2645         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2646         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2647         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2648         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2649         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2650         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2651         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2652         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2653         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2654         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2655         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2656         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2657         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2658         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2659         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2660         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2661         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2662         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2663         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2664                         ns->mac_short_packet_dropped);
2665         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2666                     ns->checksum_error);
2667         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2668         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2669 }
2670
2671 /* Reset the statistics */
2672 static void
2673 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2674 {
2675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677
2678         /* Mark PF and VSI stats to update the offset, aka "reset" */
2679         pf->offset_loaded = false;
2680         if (pf->main_vsi)
2681                 pf->main_vsi->offset_loaded = false;
2682
2683         /* read the stats, reading current register values into offset */
2684         i40e_read_stats_registers(pf, hw);
2685 }
2686
2687 static uint32_t
2688 i40e_xstats_calc_num(void)
2689 {
2690         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2691                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2692                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2693 }
2694
2695 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2696                                      struct rte_eth_xstat_name *xstats_names,
2697                                      __rte_unused unsigned limit)
2698 {
2699         unsigned count = 0;
2700         unsigned i, prio;
2701
2702         if (xstats_names == NULL)
2703                 return i40e_xstats_calc_num();
2704
2705         /* Note: limit checked in rte_eth_xstats_names() */
2706
2707         /* Get stats from i40e_eth_stats struct */
2708         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2709                 snprintf(xstats_names[count].name,
2710                          sizeof(xstats_names[count].name),
2711                          "%s", rte_i40e_stats_strings[i].name);
2712                 count++;
2713         }
2714
2715         /* Get individiual stats from i40e_hw_port struct */
2716         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2717                 snprintf(xstats_names[count].name,
2718                         sizeof(xstats_names[count].name),
2719                          "%s", rte_i40e_hw_port_strings[i].name);
2720                 count++;
2721         }
2722
2723         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2724                 for (prio = 0; prio < 8; prio++) {
2725                         snprintf(xstats_names[count].name,
2726                                  sizeof(xstats_names[count].name),
2727                                  "rx_priority%u_%s", prio,
2728                                  rte_i40e_rxq_prio_strings[i].name);
2729                         count++;
2730                 }
2731         }
2732
2733         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2734                 for (prio = 0; prio < 8; prio++) {
2735                         snprintf(xstats_names[count].name,
2736                                  sizeof(xstats_names[count].name),
2737                                  "tx_priority%u_%s", prio,
2738                                  rte_i40e_txq_prio_strings[i].name);
2739                         count++;
2740                 }
2741         }
2742         return count;
2743 }
2744
2745 static int
2746 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2747                     unsigned n)
2748 {
2749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751         unsigned i, count, prio;
2752         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2753
2754         count = i40e_xstats_calc_num();
2755         if (n < count)
2756                 return count;
2757
2758         i40e_read_stats_registers(pf, hw);
2759
2760         if (xstats == NULL)
2761                 return 0;
2762
2763         count = 0;
2764
2765         /* Get stats from i40e_eth_stats struct */
2766         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2767                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2768                         rte_i40e_stats_strings[i].offset);
2769                 xstats[count].id = count;
2770                 count++;
2771         }
2772
2773         /* Get individiual stats from i40e_hw_port struct */
2774         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2775                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2776                         rte_i40e_hw_port_strings[i].offset);
2777                 xstats[count].id = count;
2778                 count++;
2779         }
2780
2781         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2782                 for (prio = 0; prio < 8; prio++) {
2783                         xstats[count].value =
2784                                 *(uint64_t *)(((char *)hw_stats) +
2785                                 rte_i40e_rxq_prio_strings[i].offset +
2786                                 (sizeof(uint64_t) * prio));
2787                         xstats[count].id = count;
2788                         count++;
2789                 }
2790         }
2791
2792         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2793                 for (prio = 0; prio < 8; prio++) {
2794                         xstats[count].value =
2795                                 *(uint64_t *)(((char *)hw_stats) +
2796                                 rte_i40e_txq_prio_strings[i].offset +
2797                                 (sizeof(uint64_t) * prio));
2798                         xstats[count].id = count;
2799                         count++;
2800                 }
2801         }
2802
2803         return count;
2804 }
2805
2806 static int
2807 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2808                                  __rte_unused uint16_t queue_id,
2809                                  __rte_unused uint8_t stat_idx,
2810                                  __rte_unused uint8_t is_rx)
2811 {
2812         PMD_INIT_FUNC_TRACE();
2813
2814         return -ENOSYS;
2815 }
2816
2817 static void
2818 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2819 {
2820         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822         struct i40e_vsi *vsi = pf->main_vsi;
2823
2824         dev_info->max_rx_queues = vsi->nb_qps;
2825         dev_info->max_tx_queues = vsi->nb_qps;
2826         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2827         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2828         dev_info->max_mac_addrs = vsi->max_macaddrs;
2829         dev_info->max_vfs = dev->pci_dev->max_vfs;
2830         dev_info->rx_offload_capa =
2831                 DEV_RX_OFFLOAD_VLAN_STRIP |
2832                 DEV_RX_OFFLOAD_QINQ_STRIP |
2833                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2834                 DEV_RX_OFFLOAD_UDP_CKSUM |
2835                 DEV_RX_OFFLOAD_TCP_CKSUM;
2836         dev_info->tx_offload_capa =
2837                 DEV_TX_OFFLOAD_VLAN_INSERT |
2838                 DEV_TX_OFFLOAD_QINQ_INSERT |
2839                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2840                 DEV_TX_OFFLOAD_UDP_CKSUM |
2841                 DEV_TX_OFFLOAD_TCP_CKSUM |
2842                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2843                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2844                 DEV_TX_OFFLOAD_TCP_TSO |
2845                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2846                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2847                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2848                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2849         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2850                                                 sizeof(uint32_t);
2851         dev_info->reta_size = pf->hash_lut_size;
2852         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2853
2854         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2855                 .rx_thresh = {
2856                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2857                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2858                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2859                 },
2860                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2861                 .rx_drop_en = 0,
2862         };
2863
2864         dev_info->default_txconf = (struct rte_eth_txconf) {
2865                 .tx_thresh = {
2866                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2867                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2868                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2869                 },
2870                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2871                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2872                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2873                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2874         };
2875
2876         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2877                 .nb_max = I40E_MAX_RING_DESC,
2878                 .nb_min = I40E_MIN_RING_DESC,
2879                 .nb_align = I40E_ALIGN_RING_DESC,
2880         };
2881
2882         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2883                 .nb_max = I40E_MAX_RING_DESC,
2884                 .nb_min = I40E_MIN_RING_DESC,
2885                 .nb_align = I40E_ALIGN_RING_DESC,
2886         };
2887
2888         if (pf->flags & I40E_FLAG_VMDQ) {
2889                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2890                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2891                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2892                                                 pf->max_nb_vmdq_vsi;
2893                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2894                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2895                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2896         }
2897
2898         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2899                 /* For XL710 */
2900                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2901         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2902                 /* For XXV710 */
2903                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2904         else
2905                 /* For X710 */
2906                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2907 }
2908
2909 static int
2910 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2911 {
2912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2913         struct i40e_vsi *vsi = pf->main_vsi;
2914         PMD_INIT_FUNC_TRACE();
2915
2916         if (on)
2917                 return i40e_vsi_add_vlan(vsi, vlan_id);
2918         else
2919                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2920 }
2921
2922 static int
2923 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2924                    enum rte_vlan_type vlan_type,
2925                    uint16_t tpid)
2926 {
2927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2929         uint64_t reg_r = 0, reg_w = 0;
2930         uint16_t reg_id = 0;
2931         int ret = 0;
2932         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2933
2934         if (pf->support_multi_driver) {
2935                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
2936                 return -ENOTSUP;
2937         }
2938
2939         switch (vlan_type) {
2940         case ETH_VLAN_TYPE_OUTER:
2941                 if (qinq)
2942                         reg_id = 2;
2943                 else
2944                         reg_id = 3;
2945                 break;
2946         case ETH_VLAN_TYPE_INNER:
2947                 if (qinq)
2948                         reg_id = 3;
2949                 else {
2950                         ret = -EINVAL;
2951                         PMD_DRV_LOG(ERR,
2952                                 "Unsupported vlan type in single vlan.\n");
2953                         return ret;
2954                 }
2955                 break;
2956         default:
2957                 ret = -EINVAL;
2958                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2959                 return ret;
2960         }
2961         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2962                                           &reg_r, NULL);
2963         if (ret != I40E_SUCCESS) {
2964                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2965                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2966                 ret = -EIO;
2967                 return ret;
2968         }
2969         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2970                     "0x%08"PRIx64"", reg_id, reg_r);
2971
2972         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2973         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2974         if (reg_r == reg_w) {
2975                 ret = 0;
2976                 PMD_DRV_LOG(DEBUG, "No need to write");
2977                 return ret;
2978         }
2979
2980         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2981                                            reg_w, NULL);
2982         if (ret != I40E_SUCCESS) {
2983                 ret = -EIO;
2984                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2985                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2986                 return ret;
2987         }
2988         PMD_DRV_LOG(DEBUG,
2989                     "Global register 0x%08x is changed with value 0x%08x",
2990                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
2991
2992         i40e_global_cfg_warning(I40E_WARNING_TPID);
2993
2994         return ret;
2995 }
2996
2997 static void
2998 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2999 {
3000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3001         struct i40e_vsi *vsi = pf->main_vsi;
3002
3003         if (mask & ETH_VLAN_FILTER_MASK) {
3004                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3005                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3006                 else
3007                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3008         }
3009
3010         if (mask & ETH_VLAN_STRIP_MASK) {
3011                 /* Enable or disable VLAN stripping */
3012                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3013                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3014                 else
3015                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3016         }
3017
3018         if (mask & ETH_VLAN_EXTEND_MASK) {
3019                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3020                         i40e_vsi_config_double_vlan(vsi, TRUE);
3021                         /* Set global registers with default ether type value */
3022                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3023                                            ETHER_TYPE_VLAN);
3024                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3025                                            ETHER_TYPE_VLAN);
3026                 }
3027                 else
3028                         i40e_vsi_config_double_vlan(vsi, FALSE);
3029         }
3030 }
3031
3032 static void
3033 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3034                           __rte_unused uint16_t queue,
3035                           __rte_unused int on)
3036 {
3037         PMD_INIT_FUNC_TRACE();
3038 }
3039
3040 static int
3041 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3042 {
3043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3044         struct i40e_vsi *vsi = pf->main_vsi;
3045         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3046         struct i40e_vsi_vlan_pvid_info info;
3047
3048         memset(&info, 0, sizeof(info));
3049         info.on = on;
3050         if (info.on)
3051                 info.config.pvid = pvid;
3052         else {
3053                 info.config.reject.tagged =
3054                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3055                 info.config.reject.untagged =
3056                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3057         }
3058
3059         return i40e_vsi_vlan_pvid_set(vsi, &info);
3060 }
3061
3062 static int
3063 i40e_dev_led_on(struct rte_eth_dev *dev)
3064 {
3065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066         uint32_t mode = i40e_led_get(hw);
3067
3068         if (mode == 0)
3069                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3070
3071         return 0;
3072 }
3073
3074 static int
3075 i40e_dev_led_off(struct rte_eth_dev *dev)
3076 {
3077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078         uint32_t mode = i40e_led_get(hw);
3079
3080         if (mode != 0)
3081                 i40e_led_set(hw, 0, false);
3082
3083         return 0;
3084 }
3085
3086 static int
3087 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3088 {
3089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3091
3092         fc_conf->pause_time = pf->fc_conf.pause_time;
3093
3094         /* read out from register, in case they are modified by other port */
3095         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3096                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3097         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3098                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3099
3100         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3101         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3102
3103          /* Return current mode according to actual setting*/
3104         switch (hw->fc.current_mode) {
3105         case I40E_FC_FULL:
3106                 fc_conf->mode = RTE_FC_FULL;
3107                 break;
3108         case I40E_FC_TX_PAUSE:
3109                 fc_conf->mode = RTE_FC_TX_PAUSE;
3110                 break;
3111         case I40E_FC_RX_PAUSE:
3112                 fc_conf->mode = RTE_FC_RX_PAUSE;
3113                 break;
3114         case I40E_FC_NONE:
3115         default:
3116                 fc_conf->mode = RTE_FC_NONE;
3117         };
3118
3119         return 0;
3120 }
3121
3122 static int
3123 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3124 {
3125         uint32_t mflcn_reg, fctrl_reg, reg;
3126         uint32_t max_high_water;
3127         uint8_t i, aq_failure;
3128         int err;
3129         struct i40e_hw *hw;
3130         struct i40e_pf *pf;
3131         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3132                 [RTE_FC_NONE] = I40E_FC_NONE,
3133                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3134                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3135                 [RTE_FC_FULL] = I40E_FC_FULL
3136         };
3137
3138         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3139
3140         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3141         if ((fc_conf->high_water > max_high_water) ||
3142                         (fc_conf->high_water < fc_conf->low_water)) {
3143                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3144                         "High_water must <= %d.", max_high_water);
3145                 return -EINVAL;
3146         }
3147
3148         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3150         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3151
3152         pf->fc_conf.pause_time = fc_conf->pause_time;
3153         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3154         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3155
3156         PMD_INIT_FUNC_TRACE();
3157
3158         /* All the link flow control related enable/disable register
3159          * configuration is handle by the F/W
3160          */
3161         err = i40e_set_fc(hw, &aq_failure, true);
3162         if (err < 0)
3163                 return -ENOSYS;
3164
3165         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3166                 /* Configure flow control refresh threshold,
3167                  * the value for stat_tx_pause_refresh_timer[8]
3168                  * is used for global pause operation.
3169                  */
3170
3171                 I40E_WRITE_REG(hw,
3172                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3173                                pf->fc_conf.pause_time);
3174
3175                 /* configure the timer value included in transmitted pause
3176                  * frame,
3177                  * the value for stat_tx_pause_quanta[8] is used for global
3178                  * pause operation
3179                  */
3180                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3181                                pf->fc_conf.pause_time);
3182
3183                 fctrl_reg = I40E_READ_REG(hw,
3184                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3185
3186                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3187                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3188                 else
3189                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3190
3191                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3192                                fctrl_reg);
3193         } else {
3194                 /* Configure pause time (2 TCs per register) */
3195                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3196                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3197                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3198
3199                 /* Configure flow control refresh threshold value */
3200                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3201                                pf->fc_conf.pause_time / 2);
3202
3203                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3204
3205                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3206                  *depending on configuration
3207                  */
3208                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3209                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3210                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3211                 } else {
3212                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3213                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3214                 }
3215
3216                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3217         }
3218
3219         if (!pf->support_multi_driver) {
3220                 /* config water marker both based on the packets and bytes */
3221                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3222                                 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3223                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3224                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3225                                 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3226                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3227                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3228                                  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3229                                  << I40E_KILOSHIFT);
3230                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3231                                   pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3232                                   << I40E_KILOSHIFT);
3233                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3234         } else {
3235                 PMD_DRV_LOG(ERR,
3236                             "Water marker configuration is not supported.");
3237         }
3238
3239         I40E_WRITE_FLUSH(hw);
3240
3241         return 0;
3242 }
3243
3244 static int
3245 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3246                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3247 {
3248         PMD_INIT_FUNC_TRACE();
3249
3250         return -ENOSYS;
3251 }
3252
3253 /* Add a MAC address, and update filters */
3254 static void
3255 i40e_macaddr_add(struct rte_eth_dev *dev,
3256                  struct ether_addr *mac_addr,
3257                  __rte_unused uint32_t index,
3258                  uint32_t pool)
3259 {
3260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3261         struct i40e_mac_filter_info mac_filter;
3262         struct i40e_vsi *vsi;
3263         int ret;
3264
3265         /* If VMDQ not enabled or configured, return */
3266         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3267                           !pf->nb_cfg_vmdq_vsi)) {
3268                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3269                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3270                         pool);
3271                 return;
3272         }
3273
3274         if (pool > pf->nb_cfg_vmdq_vsi) {
3275                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3276                                 pool, pf->nb_cfg_vmdq_vsi);
3277                 return;
3278         }
3279
3280         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3281         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3282                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3283         else
3284                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3285
3286         if (pool == 0)
3287                 vsi = pf->main_vsi;
3288         else
3289                 vsi = pf->vmdq[pool - 1].vsi;
3290
3291         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3292         if (ret != I40E_SUCCESS) {
3293                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3294                 return;
3295         }
3296 }
3297
3298 /* Remove a MAC address, and update filters */
3299 static void
3300 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3301 {
3302         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3303         struct i40e_vsi *vsi;
3304         struct rte_eth_dev_data *data = dev->data;
3305         struct ether_addr *macaddr;
3306         int ret;
3307         uint32_t i;
3308         uint64_t pool_sel;
3309
3310         macaddr = &(data->mac_addrs[index]);
3311
3312         pool_sel = dev->data->mac_pool_sel[index];
3313
3314         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3315                 if (pool_sel & (1ULL << i)) {
3316                         if (i == 0)
3317                                 vsi = pf->main_vsi;
3318                         else {
3319                                 /* No VMDQ pool enabled or configured */
3320                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3321                                         (i > pf->nb_cfg_vmdq_vsi)) {
3322                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3323                                                         "/configured");
3324                                         return;
3325                                 }
3326                                 vsi = pf->vmdq[i - 1].vsi;
3327                         }
3328                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3329
3330                         if (ret) {
3331                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3332                                 return;
3333                         }
3334                 }
3335         }
3336 }
3337
3338 /* Set perfect match or hash match of MAC and VLAN for a VF */
3339 static int
3340 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3341                  struct rte_eth_mac_filter *filter,
3342                  bool add)
3343 {
3344         struct i40e_hw *hw;
3345         struct i40e_mac_filter_info mac_filter;
3346         struct ether_addr old_mac;
3347         struct ether_addr *new_mac;
3348         struct i40e_pf_vf *vf = NULL;
3349         uint16_t vf_id;
3350         int ret;
3351
3352         if (pf == NULL) {
3353                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3354                 return -EINVAL;
3355         }
3356         hw = I40E_PF_TO_HW(pf);
3357
3358         if (filter == NULL) {
3359                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3360                 return -EINVAL;
3361         }
3362
3363         new_mac = &filter->mac_addr;
3364
3365         if (is_zero_ether_addr(new_mac)) {
3366                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3367                 return -EINVAL;
3368         }
3369
3370         vf_id = filter->dst_id;
3371
3372         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3373                 PMD_DRV_LOG(ERR, "Invalid argument.");
3374                 return -EINVAL;
3375         }
3376         vf = &pf->vfs[vf_id];
3377
3378         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3379                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3380                 return -EINVAL;
3381         }
3382
3383         if (add) {
3384                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3385                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3386                                 ETHER_ADDR_LEN);
3387                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3388                                  ETHER_ADDR_LEN);
3389
3390                 mac_filter.filter_type = filter->filter_type;
3391                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3392                 if (ret != I40E_SUCCESS) {
3393                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3394                         return -1;
3395                 }
3396                 ether_addr_copy(new_mac, &pf->dev_addr);
3397         } else {
3398                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3399                                 ETHER_ADDR_LEN);
3400                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3401                 if (ret != I40E_SUCCESS) {
3402                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3403                         return -1;
3404                 }
3405
3406                 /* Clear device address as it has been removed */
3407                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3408                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3409         }
3410
3411         return 0;
3412 }
3413
3414 /* MAC filter handle */
3415 static int
3416 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3417                 void *arg)
3418 {
3419         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3420         struct rte_eth_mac_filter *filter;
3421         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3422         int ret = I40E_NOT_SUPPORTED;
3423
3424         filter = (struct rte_eth_mac_filter *)(arg);
3425
3426         switch (filter_op) {
3427         case RTE_ETH_FILTER_NOP:
3428                 ret = I40E_SUCCESS;
3429                 break;
3430         case RTE_ETH_FILTER_ADD:
3431                 i40e_pf_disable_irq0(hw);
3432                 if (filter->is_vf)
3433                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3434                 i40e_pf_enable_irq0(hw);
3435                 break;
3436         case RTE_ETH_FILTER_DELETE:
3437                 i40e_pf_disable_irq0(hw);
3438                 if (filter->is_vf)
3439                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3440                 i40e_pf_enable_irq0(hw);
3441                 break;
3442         default:
3443                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3444                 ret = I40E_ERR_PARAM;
3445                 break;
3446         }
3447
3448         return ret;
3449 }
3450
3451 static int
3452 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3453 {
3454         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3455         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3456         int ret;
3457
3458         if (!lut)
3459                 return -EINVAL;
3460
3461         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3462                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3463                                           lut, lut_size);
3464                 if (ret) {
3465                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3466                         return ret;
3467                 }
3468         } else {
3469                 uint32_t *lut_dw = (uint32_t *)lut;
3470                 uint16_t i, lut_size_dw = lut_size / 4;
3471
3472                 for (i = 0; i < lut_size_dw; i++)
3473                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3474         }
3475
3476         return 0;
3477 }
3478
3479 static int
3480 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3481 {
3482         struct i40e_pf *pf;
3483         struct i40e_hw *hw;
3484         int ret;
3485
3486         if (!vsi || !lut)
3487                 return -EINVAL;
3488
3489         pf = I40E_VSI_TO_PF(vsi);
3490         hw = I40E_VSI_TO_HW(vsi);
3491
3492         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3493                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3494                                           lut, lut_size);
3495                 if (ret) {
3496                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3497                         return ret;
3498                 }
3499         } else {
3500                 uint32_t *lut_dw = (uint32_t *)lut;
3501                 uint16_t i, lut_size_dw = lut_size / 4;
3502
3503                 for (i = 0; i < lut_size_dw; i++)
3504                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3505                 I40E_WRITE_FLUSH(hw);
3506         }
3507
3508         return 0;
3509 }
3510
3511 static int
3512 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3513                          struct rte_eth_rss_reta_entry64 *reta_conf,
3514                          uint16_t reta_size)
3515 {
3516         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3517         uint16_t i, lut_size = pf->hash_lut_size;
3518         uint16_t idx, shift;
3519         uint8_t *lut;
3520         int ret;
3521
3522         if (reta_size != lut_size ||
3523                 reta_size > ETH_RSS_RETA_SIZE_512) {
3524                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3525                         "(%d) doesn't match the number hardware can supported "
3526                                         "(%d)\n", reta_size, lut_size);
3527                 return -EINVAL;
3528         }
3529
3530         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3531         if (!lut) {
3532                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3533                 return -ENOMEM;
3534         }
3535         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3536         if (ret)
3537                 goto out;
3538         for (i = 0; i < reta_size; i++) {
3539                 idx = i / RTE_RETA_GROUP_SIZE;
3540                 shift = i % RTE_RETA_GROUP_SIZE;
3541                 if (reta_conf[idx].mask & (1ULL << shift))
3542                         lut[i] = reta_conf[idx].reta[shift];
3543         }
3544         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3545
3546 out:
3547         rte_free(lut);
3548
3549         return ret;
3550 }
3551
3552 static int
3553 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3554                         struct rte_eth_rss_reta_entry64 *reta_conf,
3555                         uint16_t reta_size)
3556 {
3557         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3558         uint16_t i, lut_size = pf->hash_lut_size;
3559         uint16_t idx, shift;
3560         uint8_t *lut;
3561         int ret;
3562
3563         if (reta_size != lut_size ||
3564                 reta_size > ETH_RSS_RETA_SIZE_512) {
3565                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3566                         "(%d) doesn't match the number hardware can supported "
3567                                         "(%d)\n", reta_size, lut_size);
3568                 return -EINVAL;
3569         }
3570
3571         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3572         if (!lut) {
3573                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3574                 return -ENOMEM;
3575         }
3576
3577         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3578         if (ret)
3579                 goto out;
3580         for (i = 0; i < reta_size; i++) {
3581                 idx = i / RTE_RETA_GROUP_SIZE;
3582                 shift = i % RTE_RETA_GROUP_SIZE;
3583                 if (reta_conf[idx].mask & (1ULL << shift))
3584                         reta_conf[idx].reta[shift] = lut[i];
3585         }
3586
3587 out:
3588         rte_free(lut);
3589
3590         return ret;
3591 }
3592
3593 /**
3594  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3595  * @hw:   pointer to the HW structure
3596  * @mem:  pointer to mem struct to fill out
3597  * @size: size of memory requested
3598  * @alignment: what to align the allocation to
3599  **/
3600 enum i40e_status_code
3601 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3602                         struct i40e_dma_mem *mem,
3603                         u64 size,
3604                         u32 alignment)
3605 {
3606         const struct rte_memzone *mz = NULL;
3607         char z_name[RTE_MEMZONE_NAMESIZE];
3608
3609         if (!mem)
3610                 return I40E_ERR_PARAM;
3611
3612         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3613         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3614                                          alignment, RTE_PGSIZE_2M);
3615         if (!mz)
3616                 return I40E_ERR_NO_MEMORY;
3617
3618         mem->size = size;
3619         mem->va = mz->addr;
3620         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3621         mem->zone = (const void *)mz;
3622         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3623                     "%"PRIu64, mz->name, mem->pa);
3624
3625         return I40E_SUCCESS;
3626 }
3627
3628 /**
3629  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3630  * @hw:   pointer to the HW structure
3631  * @mem:  ptr to mem struct to free
3632  **/
3633 enum i40e_status_code
3634 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3635                     struct i40e_dma_mem *mem)
3636 {
3637         if (!mem)
3638                 return I40E_ERR_PARAM;
3639
3640         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3641                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3642                     mem->pa);
3643         rte_memzone_free((const struct rte_memzone *)mem->zone);
3644         mem->zone = NULL;
3645         mem->va = NULL;
3646         mem->pa = (u64)0;
3647
3648         return I40E_SUCCESS;
3649 }
3650
3651 /**
3652  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3653  * @hw:   pointer to the HW structure
3654  * @mem:  pointer to mem struct to fill out
3655  * @size: size of memory requested
3656  **/
3657 enum i40e_status_code
3658 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3659                          struct i40e_virt_mem *mem,
3660                          u32 size)
3661 {
3662         if (!mem)
3663                 return I40E_ERR_PARAM;
3664
3665         mem->size = size;
3666         mem->va = rte_zmalloc("i40e", size, 0);
3667
3668         if (mem->va)
3669                 return I40E_SUCCESS;
3670         else
3671                 return I40E_ERR_NO_MEMORY;
3672 }
3673
3674 /**
3675  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3676  * @hw:   pointer to the HW structure
3677  * @mem:  pointer to mem struct to free
3678  **/
3679 enum i40e_status_code
3680 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3681                      struct i40e_virt_mem *mem)
3682 {
3683         if (!mem)
3684                 return I40E_ERR_PARAM;
3685
3686         rte_free(mem->va);
3687         mem->va = NULL;
3688
3689         return I40E_SUCCESS;
3690 }
3691
3692 void
3693 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3694 {
3695         rte_spinlock_init(&sp->spinlock);
3696 }
3697
3698 void
3699 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3700 {
3701         rte_spinlock_lock(&sp->spinlock);
3702 }
3703
3704 void
3705 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3706 {
3707         rte_spinlock_unlock(&sp->spinlock);
3708 }
3709
3710 void
3711 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3712 {
3713         return;
3714 }
3715
3716 /**
3717  * Get the hardware capabilities, which will be parsed
3718  * and saved into struct i40e_hw.
3719  */
3720 static int
3721 i40e_get_cap(struct i40e_hw *hw)
3722 {
3723         struct i40e_aqc_list_capabilities_element_resp *buf;
3724         uint16_t len, size = 0;
3725         int ret;
3726
3727         /* Calculate a huge enough buff for saving response data temporarily */
3728         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3729                                                 I40E_MAX_CAP_ELE_NUM;
3730         buf = rte_zmalloc("i40e", len, 0);
3731         if (!buf) {
3732                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3733                 return I40E_ERR_NO_MEMORY;
3734         }
3735
3736         /* Get, parse the capabilities and save it to hw */
3737         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3738                         i40e_aqc_opc_list_func_capabilities, NULL);
3739         if (ret != I40E_SUCCESS)
3740                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3741
3742         /* Free the temporary buffer after being used */
3743         rte_free(buf);
3744
3745         return ret;
3746 }
3747
3748 static int
3749 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3750 {
3751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3752         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3753         uint16_t qp_count = 0, vsi_count = 0;
3754
3755         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3756                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3757                 return -EINVAL;
3758         }
3759         /* Add the parameter init for LFC */
3760         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3761         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3762         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3763
3764         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3765         pf->max_num_vsi = hw->func_caps.num_vsis;
3766         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3767         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3768         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3769
3770         /* FDir queue/VSI allocation */
3771         pf->fdir_qp_offset = 0;
3772         if (hw->func_caps.fd) {
3773                 pf->flags |= I40E_FLAG_FDIR;
3774                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3775         } else {
3776                 pf->fdir_nb_qps = 0;
3777         }
3778         qp_count += pf->fdir_nb_qps;
3779         vsi_count += 1;
3780
3781         /* LAN queue/VSI allocation */
3782         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3783         if (!hw->func_caps.rss) {
3784                 pf->lan_nb_qps = 1;
3785         } else {
3786                 pf->flags |= I40E_FLAG_RSS;
3787                 if (hw->mac.type == I40E_MAC_X722)
3788                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3789                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3790         }
3791         qp_count += pf->lan_nb_qps;
3792         vsi_count += 1;
3793
3794         /* VF queue/VSI allocation */
3795         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3796         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3797                 pf->flags |= I40E_FLAG_SRIOV;
3798                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3799                 pf->vf_num = dev->pci_dev->max_vfs;
3800                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3801                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3802                             pf->vf_nb_qps * pf->vf_num);
3803         } else {
3804                 pf->vf_nb_qps = 0;
3805                 pf->vf_num = 0;
3806         }
3807         qp_count += pf->vf_nb_qps * pf->vf_num;
3808         vsi_count += pf->vf_num;
3809
3810         /* VMDq queue/VSI allocation */
3811         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3812         pf->vmdq_nb_qps = 0;
3813         pf->max_nb_vmdq_vsi = 0;
3814         if (hw->func_caps.vmdq) {
3815                 if (qp_count < hw->func_caps.num_tx_qp &&
3816                         vsi_count < hw->func_caps.num_vsis) {
3817                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3818                                 qp_count) / pf->vmdq_nb_qp_max;
3819
3820                         /* Limit the maximum number of VMDq vsi to the maximum
3821                          * ethdev can support
3822                          */
3823                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3824                                 hw->func_caps.num_vsis - vsi_count);
3825                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3826                                 ETH_64_POOLS);
3827                         if (pf->max_nb_vmdq_vsi) {
3828                                 pf->flags |= I40E_FLAG_VMDQ;
3829                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3830                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3831                                             "per VMDQ VSI, in total %u queues",
3832                                             pf->max_nb_vmdq_vsi,
3833                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3834                                             pf->max_nb_vmdq_vsi);
3835                         } else {
3836                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3837                                             "VMDq");
3838                         }
3839                 } else {
3840                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3841                 }
3842         }
3843         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3844         vsi_count += pf->max_nb_vmdq_vsi;
3845
3846         if (hw->func_caps.dcb)
3847                 pf->flags |= I40E_FLAG_DCB;
3848
3849         if (qp_count > hw->func_caps.num_tx_qp) {
3850                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3851                             "the hardware maximum %u", qp_count,
3852                             hw->func_caps.num_tx_qp);
3853                 return -EINVAL;
3854         }
3855         if (vsi_count > hw->func_caps.num_vsis) {
3856                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3857                             "the hardware maximum %u", vsi_count,
3858                             hw->func_caps.num_vsis);
3859                 return -EINVAL;
3860         }
3861
3862         return 0;
3863 }
3864
3865 static int
3866 i40e_pf_get_switch_config(struct i40e_pf *pf)
3867 {
3868         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3869         struct i40e_aqc_get_switch_config_resp *switch_config;
3870         struct i40e_aqc_switch_config_element_resp *element;
3871         uint16_t start_seid = 0, num_reported;
3872         int ret;
3873
3874         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3875                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3876         if (!switch_config) {
3877                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3878                 return -ENOMEM;
3879         }
3880
3881         /* Get the switch configurations */
3882         ret = i40e_aq_get_switch_config(hw, switch_config,
3883                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3884         if (ret != I40E_SUCCESS) {
3885                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3886                 goto fail;
3887         }
3888         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3889         if (num_reported != 1) { /* The number should be 1 */
3890                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3891                 goto fail;
3892         }
3893
3894         /* Parse the switch configuration elements */
3895         element = &(switch_config->element[0]);
3896         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3897                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3898                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3899         } else
3900                 PMD_DRV_LOG(INFO, "Unknown element type");
3901
3902 fail:
3903         rte_free(switch_config);
3904
3905         return ret;
3906 }
3907
3908 static int
3909 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3910                         uint32_t num)
3911 {
3912         struct pool_entry *entry;
3913
3914         if (pool == NULL || num == 0)
3915                 return -EINVAL;
3916
3917         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3918         if (entry == NULL) {
3919                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3920                 return -ENOMEM;
3921         }
3922
3923         /* queue heap initialize */
3924         pool->num_free = num;
3925         pool->num_alloc = 0;
3926         pool->base = base;
3927         LIST_INIT(&pool->alloc_list);
3928         LIST_INIT(&pool->free_list);
3929
3930         /* Initialize element  */
3931         entry->base = 0;
3932         entry->len = num;
3933
3934         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3935         return 0;
3936 }
3937
3938 static void
3939 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3940 {
3941         struct pool_entry *entry, *next_entry;
3942
3943         if (pool == NULL)
3944                 return;
3945
3946         for (entry = LIST_FIRST(&pool->alloc_list);
3947                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3948                         entry = next_entry) {
3949                 LIST_REMOVE(entry, next);
3950                 rte_free(entry);
3951         }
3952
3953         for (entry = LIST_FIRST(&pool->free_list);
3954                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3955                         entry = next_entry) {
3956                 LIST_REMOVE(entry, next);
3957                 rte_free(entry);
3958         }
3959
3960         pool->num_free = 0;
3961         pool->num_alloc = 0;
3962         pool->base = 0;
3963         LIST_INIT(&pool->alloc_list);
3964         LIST_INIT(&pool->free_list);
3965 }
3966
3967 static int
3968 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3969                        uint32_t base)
3970 {
3971         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3972         uint32_t pool_offset;
3973         int insert;
3974
3975         if (pool == NULL) {
3976                 PMD_DRV_LOG(ERR, "Invalid parameter");
3977                 return -EINVAL;
3978         }
3979
3980         pool_offset = base - pool->base;
3981         /* Lookup in alloc list */
3982         LIST_FOREACH(entry, &pool->alloc_list, next) {
3983                 if (entry->base == pool_offset) {
3984                         valid_entry = entry;
3985                         LIST_REMOVE(entry, next);
3986                         break;
3987                 }
3988         }
3989
3990         /* Not find, return */
3991         if (valid_entry == NULL) {
3992                 PMD_DRV_LOG(ERR, "Failed to find entry");
3993                 return -EINVAL;
3994         }
3995
3996         /**
3997          * Found it, move it to free list  and try to merge.
3998          * In order to make merge easier, always sort it by qbase.
3999          * Find adjacent prev and last entries.
4000          */
4001         prev = next = NULL;
4002         LIST_FOREACH(entry, &pool->free_list, next) {
4003                 if (entry->base > valid_entry->base) {
4004                         next = entry;
4005                         break;
4006                 }
4007                 prev = entry;
4008         }
4009
4010         insert = 0;
4011         /* Try to merge with next one*/
4012         if (next != NULL) {
4013                 /* Merge with next one */
4014                 if (valid_entry->base + valid_entry->len == next->base) {
4015                         next->base = valid_entry->base;
4016                         next->len += valid_entry->len;
4017                         rte_free(valid_entry);
4018                         valid_entry = next;
4019                         insert = 1;
4020                 }
4021         }
4022
4023         if (prev != NULL) {
4024                 /* Merge with previous one */
4025                 if (prev->base + prev->len == valid_entry->base) {
4026                         prev->len += valid_entry->len;
4027                         /* If it merge with next one, remove next node */
4028                         if (insert == 1) {
4029                                 LIST_REMOVE(valid_entry, next);
4030                                 rte_free(valid_entry);
4031                         } else {
4032                                 rte_free(valid_entry);
4033                                 insert = 1;
4034                         }
4035                 }
4036         }
4037
4038         /* Not find any entry to merge, insert */
4039         if (insert == 0) {
4040                 if (prev != NULL)
4041                         LIST_INSERT_AFTER(prev, valid_entry, next);
4042                 else if (next != NULL)
4043                         LIST_INSERT_BEFORE(next, valid_entry, next);
4044                 else /* It's empty list, insert to head */
4045                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4046         }
4047
4048         pool->num_free += valid_entry->len;
4049         pool->num_alloc -= valid_entry->len;
4050
4051         return 0;
4052 }
4053
4054 static int
4055 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4056                        uint16_t num)
4057 {
4058         struct pool_entry *entry, *valid_entry;
4059
4060         if (pool == NULL || num == 0) {
4061                 PMD_DRV_LOG(ERR, "Invalid parameter");
4062                 return -EINVAL;
4063         }
4064
4065         if (pool->num_free < num) {
4066                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4067                             num, pool->num_free);
4068                 return -ENOMEM;
4069         }
4070
4071         valid_entry = NULL;
4072         /* Lookup  in free list and find most fit one */
4073         LIST_FOREACH(entry, &pool->free_list, next) {
4074                 if (entry->len >= num) {
4075                         /* Find best one */
4076                         if (entry->len == num) {
4077                                 valid_entry = entry;
4078                                 break;
4079                         }
4080                         if (valid_entry == NULL || valid_entry->len > entry->len)
4081                                 valid_entry = entry;
4082                 }
4083         }
4084
4085         /* Not find one to satisfy the request, return */
4086         if (valid_entry == NULL) {
4087                 PMD_DRV_LOG(ERR, "No valid entry found");
4088                 return -ENOMEM;
4089         }
4090         /**
4091          * The entry have equal queue number as requested,
4092          * remove it from alloc_list.
4093          */
4094         if (valid_entry->len == num) {
4095                 LIST_REMOVE(valid_entry, next);
4096         } else {
4097                 /**
4098                  * The entry have more numbers than requested,
4099                  * create a new entry for alloc_list and minus its
4100                  * queue base and number in free_list.
4101                  */
4102                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4103                 if (entry == NULL) {
4104                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4105                                     "resource pool");
4106                         return -ENOMEM;
4107                 }
4108                 entry->base = valid_entry->base;
4109                 entry->len = num;
4110                 valid_entry->base += num;
4111                 valid_entry->len -= num;
4112                 valid_entry = entry;
4113         }
4114
4115         /* Insert it into alloc list, not sorted */
4116         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4117
4118         pool->num_free -= valid_entry->len;
4119         pool->num_alloc += valid_entry->len;
4120
4121         return valid_entry->base + pool->base;
4122 }
4123
4124 /**
4125  * bitmap_is_subset - Check whether src2 is subset of src1
4126  **/
4127 static inline int
4128 bitmap_is_subset(uint8_t src1, uint8_t src2)
4129 {
4130         return !((src1 ^ src2) & src2);
4131 }
4132
4133 static enum i40e_status_code
4134 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4135 {
4136         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4137
4138         /* If DCB is not supported, only default TC is supported */
4139         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4140                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4141                 return I40E_NOT_SUPPORTED;
4142         }
4143
4144         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4145                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4146                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4147                             enabled_tcmap);
4148                 return I40E_NOT_SUPPORTED;
4149         }
4150         return I40E_SUCCESS;
4151 }
4152
4153 int
4154 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4155                                 struct i40e_vsi_vlan_pvid_info *info)
4156 {
4157         struct i40e_hw *hw;
4158         struct i40e_vsi_context ctxt;
4159         uint8_t vlan_flags = 0;
4160         int ret;
4161
4162         if (vsi == NULL || info == NULL) {
4163                 PMD_DRV_LOG(ERR, "invalid parameters");
4164                 return I40E_ERR_PARAM;
4165         }
4166
4167         if (info->on) {
4168                 vsi->info.pvid = info->config.pvid;
4169                 /**
4170                  * If insert pvid is enabled, only tagged pkts are
4171                  * allowed to be sent out.
4172                  */
4173                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4174                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4175         } else {
4176                 vsi->info.pvid = 0;
4177                 if (info->config.reject.tagged == 0)
4178                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4179
4180                 if (info->config.reject.untagged == 0)
4181                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4182         }
4183         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4184                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4185         vsi->info.port_vlan_flags |= vlan_flags;
4186         vsi->info.valid_sections =
4187                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4188         memset(&ctxt, 0, sizeof(ctxt));
4189         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4190         ctxt.seid = vsi->seid;
4191
4192         hw = I40E_VSI_TO_HW(vsi);
4193         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4194         if (ret != I40E_SUCCESS)
4195                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4196
4197         return ret;
4198 }
4199
4200 static int
4201 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4202 {
4203         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4204         int i, ret;
4205         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4206
4207         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4208         if (ret != I40E_SUCCESS)
4209                 return ret;
4210
4211         if (!vsi->seid) {
4212                 PMD_DRV_LOG(ERR, "seid not valid");
4213                 return -EINVAL;
4214         }
4215
4216         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4217         tc_bw_data.tc_valid_bits = enabled_tcmap;
4218         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4219                 tc_bw_data.tc_bw_credits[i] =
4220                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4221
4222         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4223         if (ret != I40E_SUCCESS) {
4224                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4225                 return ret;
4226         }
4227
4228         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4229                                         sizeof(vsi->info.qs_handle));
4230         return I40E_SUCCESS;
4231 }
4232
4233 static enum i40e_status_code
4234 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4235                                  struct i40e_aqc_vsi_properties_data *info,
4236                                  uint8_t enabled_tcmap)
4237 {
4238         enum i40e_status_code ret;
4239         int i, total_tc = 0;
4240         uint16_t qpnum_per_tc, bsf, qp_idx;
4241
4242         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4243         if (ret != I40E_SUCCESS)
4244                 return ret;
4245
4246         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4247                 if (enabled_tcmap & (1 << i))
4248                         total_tc++;
4249         if (total_tc == 0)
4250                 total_tc = 1;
4251         vsi->enabled_tc = enabled_tcmap;
4252
4253         /* Number of queues per enabled TC */
4254         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4255         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4256         bsf = rte_bsf32(qpnum_per_tc);
4257
4258         /* Adjust the queue number to actual queues that can be applied */
4259         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4260                 vsi->nb_qps = qpnum_per_tc * total_tc;
4261
4262         /**
4263          * Configure TC and queue mapping parameters, for enabled TC,
4264          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4265          * default queue will serve it.
4266          */
4267         qp_idx = 0;
4268         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4269                 if (vsi->enabled_tc & (1 << i)) {
4270                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4271                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4272                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4273                         qp_idx += qpnum_per_tc;
4274                 } else
4275                         info->tc_mapping[i] = 0;
4276         }
4277
4278         /* Associate queue number with VSI */
4279         if (vsi->type == I40E_VSI_SRIOV) {
4280                 info->mapping_flags |=
4281                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4282                 for (i = 0; i < vsi->nb_qps; i++)
4283                         info->queue_mapping[i] =
4284                                 rte_cpu_to_le_16(vsi->base_queue + i);
4285         } else {
4286                 info->mapping_flags |=
4287                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4288                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4289         }
4290         info->valid_sections |=
4291                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4292
4293         return I40E_SUCCESS;
4294 }
4295
4296 static int
4297 i40e_veb_release(struct i40e_veb *veb)
4298 {
4299         struct i40e_vsi *vsi;
4300         struct i40e_hw *hw;
4301
4302         if (veb == NULL)
4303                 return -EINVAL;
4304
4305         if (!TAILQ_EMPTY(&veb->head)) {
4306                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4307                 return -EACCES;
4308         }
4309         /* associate_vsi field is NULL for floating VEB */
4310         if (veb->associate_vsi != NULL) {
4311                 vsi = veb->associate_vsi;
4312                 hw = I40E_VSI_TO_HW(vsi);
4313
4314                 vsi->uplink_seid = veb->uplink_seid;
4315                 vsi->veb = NULL;
4316         } else {
4317                 veb->associate_pf->main_vsi->floating_veb = NULL;
4318                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4319         }
4320
4321         i40e_aq_delete_element(hw, veb->seid, NULL);
4322         rte_free(veb);
4323         return I40E_SUCCESS;
4324 }
4325
4326 /* Setup a veb */
4327 static struct i40e_veb *
4328 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4329 {
4330         struct i40e_veb *veb;
4331         int ret;
4332         struct i40e_hw *hw;
4333
4334         if (pf == NULL) {
4335                 PMD_DRV_LOG(ERR,
4336                             "veb setup failed, associated PF shouldn't null");
4337                 return NULL;
4338         }
4339         hw = I40E_PF_TO_HW(pf);
4340
4341         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4342         if (!veb) {
4343                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4344                 goto fail;
4345         }
4346
4347         veb->associate_vsi = vsi;
4348         veb->associate_pf = pf;
4349         TAILQ_INIT(&veb->head);
4350         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4351
4352         /* create floating veb if vsi is NULL */
4353         if (vsi != NULL) {
4354                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4355                                       I40E_DEFAULT_TCMAP, false,
4356                                       &veb->seid, false, NULL);
4357         } else {
4358                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4359                                       true, &veb->seid, false, NULL);
4360         }
4361
4362         if (ret != I40E_SUCCESS) {
4363                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4364                             hw->aq.asq_last_status);
4365                 goto fail;
4366         }
4367         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4368
4369         /* get statistics index */
4370         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4371                                 &veb->stats_idx, NULL, NULL, NULL);
4372         if (ret != I40E_SUCCESS) {
4373                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4374                             hw->aq.asq_last_status);
4375                 goto fail;
4376         }
4377         /* Get VEB bandwidth, to be implemented */
4378         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4379         if (vsi)
4380                 vsi->uplink_seid = veb->seid;
4381
4382         return veb;
4383 fail:
4384         rte_free(veb);
4385         return NULL;
4386 }
4387
4388 int
4389 i40e_vsi_release(struct i40e_vsi *vsi)
4390 {
4391         struct i40e_pf *pf;
4392         struct i40e_hw *hw;
4393         struct i40e_vsi_list *vsi_list;
4394         void *temp;
4395         int ret;
4396         struct i40e_mac_filter *f;
4397         uint16_t user_param;
4398
4399         if (!vsi)
4400                 return I40E_SUCCESS;
4401
4402         if (!vsi->adapter)
4403                 return -EFAULT;
4404
4405         user_param = vsi->user_param;
4406
4407         pf = I40E_VSI_TO_PF(vsi);
4408         hw = I40E_VSI_TO_HW(vsi);
4409
4410         /* VSI has child to attach, release child first */
4411         if (vsi->veb) {
4412                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4413                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4414                                 return -1;
4415                 }
4416                 i40e_veb_release(vsi->veb);
4417         }
4418
4419         if (vsi->floating_veb) {
4420                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4421                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4422                                 return -1;
4423                 }
4424         }
4425
4426         /* Remove all macvlan filters of the VSI */
4427         i40e_vsi_remove_all_macvlan_filter(vsi);
4428         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4429                 rte_free(f);
4430
4431         if (vsi->type != I40E_VSI_MAIN &&
4432             ((vsi->type != I40E_VSI_SRIOV) ||
4433             !pf->floating_veb_list[user_param])) {
4434                 /* Remove vsi from parent's sibling list */
4435                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4436                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4437                         return I40E_ERR_PARAM;
4438                 }
4439                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4440                                 &vsi->sib_vsi_list, list);
4441
4442                 /* Remove all switch element of the VSI */
4443                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4444                 if (ret != I40E_SUCCESS)
4445                         PMD_DRV_LOG(ERR, "Failed to delete element");
4446         }
4447
4448         if ((vsi->type == I40E_VSI_SRIOV) &&
4449             pf->floating_veb_list[user_param]) {
4450                 /* Remove vsi from parent's sibling list */
4451                 if (vsi->parent_vsi == NULL ||
4452                     vsi->parent_vsi->floating_veb == NULL) {
4453                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4454                         return I40E_ERR_PARAM;
4455                 }
4456                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4457                              &vsi->sib_vsi_list, list);
4458
4459                 /* Remove all switch element of the VSI */
4460                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4461                 if (ret != I40E_SUCCESS)
4462                         PMD_DRV_LOG(ERR, "Failed to delete element");
4463         }
4464
4465         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4466
4467         if (vsi->type != I40E_VSI_SRIOV)
4468                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4469         rte_free(vsi);
4470
4471         return I40E_SUCCESS;
4472 }
4473
4474 static int
4475 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4476 {
4477         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4478         struct i40e_aqc_remove_macvlan_element_data def_filter;
4479         struct i40e_mac_filter_info filter;
4480         int ret;
4481
4482         if (vsi->type != I40E_VSI_MAIN)
4483                 return I40E_ERR_CONFIG;
4484         memset(&def_filter, 0, sizeof(def_filter));
4485         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4486                                         ETH_ADDR_LEN);
4487         def_filter.vlan_tag = 0;
4488         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4489                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4490         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4491         if (ret != I40E_SUCCESS) {
4492                 struct i40e_mac_filter *f;
4493                 struct ether_addr *mac;
4494
4495                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4496                             "macvlan filter");
4497                 /* It needs to add the permanent mac into mac list */
4498                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4499                 if (f == NULL) {
4500                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4501                         return I40E_ERR_NO_MEMORY;
4502                 }
4503                 mac = &f->mac_info.mac_addr;
4504                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4505                                 ETH_ADDR_LEN);
4506                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4507                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4508                 vsi->mac_num++;
4509
4510                 return ret;
4511         }
4512         (void)rte_memcpy(&filter.mac_addr,
4513                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4514         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4515         return i40e_vsi_add_mac(vsi, &filter);
4516 }
4517
4518 /*
4519  * i40e_vsi_get_bw_config - Query VSI BW Information
4520  * @vsi: the VSI to be queried
4521  *
4522  * Returns 0 on success, negative value on failure
4523  */
4524 static enum i40e_status_code
4525 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4526 {
4527         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4528         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4529         struct i40e_hw *hw = &vsi->adapter->hw;
4530         i40e_status ret;
4531         int i;
4532         uint32_t bw_max;
4533
4534         memset(&bw_config, 0, sizeof(bw_config));
4535         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4536         if (ret != I40E_SUCCESS) {
4537                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4538                             hw->aq.asq_last_status);
4539                 return ret;
4540         }
4541
4542         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4543         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4544                                         &ets_sla_config, NULL);
4545         if (ret != I40E_SUCCESS) {
4546                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4547                             "configuration %u", hw->aq.asq_last_status);
4548                 return ret;
4549         }
4550
4551         /* store and print out BW info */
4552         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4553         vsi->bw_info.bw_max = bw_config.max_bw;
4554         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4555         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4556         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4557                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4558                      I40E_16_BIT_WIDTH);
4559         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4560                 vsi->bw_info.bw_ets_share_credits[i] =
4561                                 ets_sla_config.share_credits[i];
4562                 vsi->bw_info.bw_ets_credits[i] =
4563                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4564                 /* 4 bits per TC, 4th bit is reserved */
4565                 vsi->bw_info.bw_ets_max[i] =
4566                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4567                                   RTE_LEN2MASK(3, uint8_t));
4568                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4569                             vsi->bw_info.bw_ets_share_credits[i]);
4570                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4571                             vsi->bw_info.bw_ets_credits[i]);
4572                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4573                             vsi->bw_info.bw_ets_max[i]);
4574         }
4575
4576         return I40E_SUCCESS;
4577 }
4578
4579 /* i40e_enable_pf_lb
4580  * @pf: pointer to the pf structure
4581  *
4582  * allow loopback on pf
4583  */
4584 static inline void
4585 i40e_enable_pf_lb(struct i40e_pf *pf)
4586 {
4587         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4588         struct i40e_vsi_context ctxt;
4589         int ret;
4590
4591         /* Use the FW API if FW >= v5.0 */
4592         if (hw->aq.fw_maj_ver < 5) {
4593                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4594                 return;
4595         }
4596
4597         memset(&ctxt, 0, sizeof(ctxt));
4598         ctxt.seid = pf->main_vsi_seid;
4599         ctxt.pf_num = hw->pf_id;
4600         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4601         if (ret) {
4602                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4603                             ret, hw->aq.asq_last_status);
4604                 return;
4605         }
4606         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4607         ctxt.info.valid_sections =
4608                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4609         ctxt.info.switch_id |=
4610                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4611
4612         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4613         if (ret)
4614                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4615                             hw->aq.asq_last_status);
4616 }
4617
4618 /* Setup a VSI */
4619 struct i40e_vsi *
4620 i40e_vsi_setup(struct i40e_pf *pf,
4621                enum i40e_vsi_type type,
4622                struct i40e_vsi *uplink_vsi,
4623                uint16_t user_param)
4624 {
4625         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4626         struct i40e_vsi *vsi;
4627         struct i40e_mac_filter_info filter;
4628         int ret;
4629         struct i40e_vsi_context ctxt;
4630         struct ether_addr broadcast =
4631                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4632
4633         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4634             uplink_vsi == NULL) {
4635                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4636                             "VSI link shouldn't be NULL");
4637                 return NULL;
4638         }
4639
4640         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4641                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4642                             "uplink VSI should be NULL");
4643                 return NULL;
4644         }
4645
4646         /* two situations
4647          * 1.type is not MAIN and uplink vsi is not NULL
4648          * If uplink vsi didn't setup VEB, create one first under veb field
4649          * 2.type is SRIOV and the uplink is NULL
4650          * If floating VEB is NULL, create one veb under floating veb field
4651          */
4652
4653         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4654             uplink_vsi->veb == NULL) {
4655                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4656
4657                 if (uplink_vsi->veb == NULL) {
4658                         PMD_DRV_LOG(ERR, "VEB setup failed");
4659                         return NULL;
4660                 }
4661                 /* set ALLOWLOOPBACk on pf, when veb is created */
4662                 i40e_enable_pf_lb(pf);
4663         }
4664
4665         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4666             pf->main_vsi->floating_veb == NULL) {
4667                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4668
4669                 if (pf->main_vsi->floating_veb == NULL) {
4670                         PMD_DRV_LOG(ERR, "VEB setup failed");
4671                         return NULL;
4672                 }
4673         }
4674
4675         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4676         if (!vsi) {
4677                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4678                 return NULL;
4679         }
4680         TAILQ_INIT(&vsi->mac_list);
4681         vsi->type = type;
4682         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4683         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4684         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4685         vsi->user_param = user_param;
4686         /* Allocate queues */
4687         switch (vsi->type) {
4688         case I40E_VSI_MAIN  :
4689                 vsi->nb_qps = pf->lan_nb_qps;
4690                 break;
4691         case I40E_VSI_SRIOV :
4692                 vsi->nb_qps = pf->vf_nb_qps;
4693                 break;
4694         case I40E_VSI_VMDQ2:
4695                 vsi->nb_qps = pf->vmdq_nb_qps;
4696                 break;
4697         case I40E_VSI_FDIR:
4698                 vsi->nb_qps = pf->fdir_nb_qps;
4699                 break;
4700         default:
4701                 goto fail_mem;
4702         }
4703         /*
4704          * The filter status descriptor is reported in rx queue 0,
4705          * while the tx queue for fdir filter programming has no
4706          * such constraints, can be non-zero queues.
4707          * To simplify it, choose FDIR vsi use queue 0 pair.
4708          * To make sure it will use queue 0 pair, queue allocation
4709          * need be done before this function is called
4710          */
4711         if (type != I40E_VSI_FDIR) {
4712                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4713                         if (ret < 0) {
4714                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4715                                                 vsi->seid, ret);
4716                                 goto fail_mem;
4717                         }
4718                         vsi->base_queue = ret;
4719         } else
4720                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4721
4722         /* VF has MSIX interrupt in VF range, don't allocate here */
4723         if (type == I40E_VSI_MAIN) {
4724                 if (pf->support_multi_driver) {
4725                         /* If support multi-driver, need to use INT0 instead of
4726                          * allocating from msix pool. The Msix pool is init from
4727                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
4728                          * to 1 without calling i40e_res_pool_alloc.
4729                          */
4730                         vsi->msix_intr = 0;
4731                         vsi->nb_msix = 1;
4732                 } else {
4733                         ret = i40e_res_pool_alloc(&pf->msix_pool,
4734                                                   RTE_MIN(vsi->nb_qps,
4735                                                      RTE_MAX_RXTX_INTR_VEC_ID));
4736                         if (ret < 0) {
4737                                 PMD_DRV_LOG(ERR,
4738                                             "VSI MAIN %d get heap failed %d",
4739                                             vsi->seid, ret);
4740                                 goto fail_queue_alloc;
4741                         }
4742                         vsi->msix_intr = ret;
4743                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
4744                                                RTE_MAX_RXTX_INTR_VEC_ID);
4745                 }
4746         } else if (type != I40E_VSI_SRIOV) {
4747                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4748                 if (ret < 0) {
4749                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4750                         goto fail_queue_alloc;
4751                 }
4752                 vsi->msix_intr = ret;
4753                 vsi->nb_msix = 1;
4754         } else {
4755                 vsi->msix_intr = 0;
4756                 vsi->nb_msix = 0;
4757         }
4758
4759         /* Add VSI */
4760         if (type == I40E_VSI_MAIN) {
4761                 /* For main VSI, no need to add since it's default one */
4762                 vsi->uplink_seid = pf->mac_seid;
4763                 vsi->seid = pf->main_vsi_seid;
4764                 /* Bind queues with specific MSIX interrupt */
4765                 /**
4766                  * Needs 2 interrupt at least, one for misc cause which will
4767                  * enabled from OS side, Another for queues binding the
4768                  * interrupt from device side only.
4769                  */
4770
4771                 /* Get default VSI parameters from hardware */
4772                 memset(&ctxt, 0, sizeof(ctxt));
4773                 ctxt.seid = vsi->seid;
4774                 ctxt.pf_num = hw->pf_id;
4775                 ctxt.uplink_seid = vsi->uplink_seid;
4776                 ctxt.vf_num = 0;
4777                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4778                 if (ret != I40E_SUCCESS) {
4779                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4780                         goto fail_msix_alloc;
4781                 }
4782                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4783                         sizeof(struct i40e_aqc_vsi_properties_data));
4784                 vsi->vsi_id = ctxt.vsi_number;
4785                 vsi->info.valid_sections = 0;
4786
4787                 /* Configure tc, enabled TC0 only */
4788                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4789                         I40E_SUCCESS) {
4790                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4791                         goto fail_msix_alloc;
4792                 }
4793
4794                 /* TC, queue mapping */
4795                 memset(&ctxt, 0, sizeof(ctxt));
4796                 vsi->info.valid_sections |=
4797                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4798                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4799                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4800                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4801                         sizeof(struct i40e_aqc_vsi_properties_data));
4802                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4803                                                 I40E_DEFAULT_TCMAP);
4804                 if (ret != I40E_SUCCESS) {
4805                         PMD_DRV_LOG(ERR, "Failed to configure "
4806                                     "TC queue mapping");
4807                         goto fail_msix_alloc;
4808                 }
4809                 ctxt.seid = vsi->seid;
4810                 ctxt.pf_num = hw->pf_id;
4811                 ctxt.uplink_seid = vsi->uplink_seid;
4812                 ctxt.vf_num = 0;
4813
4814                 /* Update VSI parameters */
4815                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4816                 if (ret != I40E_SUCCESS) {
4817                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4818                         goto fail_msix_alloc;
4819                 }
4820
4821                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4822                                                 sizeof(vsi->info.tc_mapping));
4823                 (void)rte_memcpy(&vsi->info.queue_mapping,
4824                                 &ctxt.info.queue_mapping,
4825                         sizeof(vsi->info.queue_mapping));
4826                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4827                 vsi->info.valid_sections = 0;
4828
4829                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4830                                 ETH_ADDR_LEN);
4831
4832                 /**
4833                  * Updating default filter settings are necessary to prevent
4834                  * reception of tagged packets.
4835                  * Some old firmware configurations load a default macvlan
4836                  * filter which accepts both tagged and untagged packets.
4837                  * The updating is to use a normal filter instead if needed.
4838                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4839                  * The firmware with correct configurations load the default
4840                  * macvlan filter which is expected and cannot be removed.
4841                  */
4842                 i40e_update_default_filter_setting(vsi);
4843                 i40e_config_qinq(hw, vsi);
4844         } else if (type == I40E_VSI_SRIOV) {
4845                 memset(&ctxt, 0, sizeof(ctxt));
4846                 /**
4847                  * For other VSI, the uplink_seid equals to uplink VSI's
4848                  * uplink_seid since they share same VEB
4849                  */
4850                 if (uplink_vsi == NULL)
4851                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4852                 else
4853                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4854                 ctxt.pf_num = hw->pf_id;
4855                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4856                 ctxt.uplink_seid = vsi->uplink_seid;
4857                 ctxt.connection_type = 0x1;
4858                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4859
4860                 /* Use the VEB configuration if FW >= v5.0 */
4861                 if (hw->aq.fw_maj_ver >= 5) {
4862                         /* Configure switch ID */
4863                         ctxt.info.valid_sections |=
4864                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4865                         ctxt.info.switch_id =
4866                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4867                 }
4868
4869                 /* Configure port/vlan */
4870                 ctxt.info.valid_sections |=
4871                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4872                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4873                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4874                                                 I40E_DEFAULT_TCMAP);
4875                 if (ret != I40E_SUCCESS) {
4876                         PMD_DRV_LOG(ERR, "Failed to configure "
4877                                     "TC queue mapping");
4878                         goto fail_msix_alloc;
4879                 }
4880                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4881                 ctxt.info.valid_sections |=
4882                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4883                 /**
4884                  * Since VSI is not created yet, only configure parameter,
4885                  * will add vsi below.
4886                  */
4887
4888                 i40e_config_qinq(hw, vsi);
4889         } else if (type == I40E_VSI_VMDQ2) {
4890                 memset(&ctxt, 0, sizeof(ctxt));
4891                 /*
4892                  * For other VSI, the uplink_seid equals to uplink VSI's
4893                  * uplink_seid since they share same VEB
4894                  */
4895                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4896                 ctxt.pf_num = hw->pf_id;
4897                 ctxt.vf_num = 0;
4898                 ctxt.uplink_seid = vsi->uplink_seid;
4899                 ctxt.connection_type = 0x1;
4900                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4901
4902                 ctxt.info.valid_sections |=
4903                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4904                 /* user_param carries flag to enable loop back */
4905                 if (user_param) {
4906                         ctxt.info.switch_id =
4907                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4908                         ctxt.info.switch_id |=
4909                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4910                 }
4911
4912                 /* Configure port/vlan */
4913                 ctxt.info.valid_sections |=
4914                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4915                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4916                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4917                                                 I40E_DEFAULT_TCMAP);
4918                 if (ret != I40E_SUCCESS) {
4919                         PMD_DRV_LOG(ERR, "Failed to configure "
4920                                         "TC queue mapping");
4921                         goto fail_msix_alloc;
4922                 }
4923                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4924                 ctxt.info.valid_sections |=
4925                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4926         } else if (type == I40E_VSI_FDIR) {
4927                 memset(&ctxt, 0, sizeof(ctxt));
4928                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4929                 ctxt.pf_num = hw->pf_id;
4930                 ctxt.vf_num = 0;
4931                 ctxt.uplink_seid = vsi->uplink_seid;
4932                 ctxt.connection_type = 0x1;     /* regular data port */
4933                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4934                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4935                                                 I40E_DEFAULT_TCMAP);
4936                 if (ret != I40E_SUCCESS) {
4937                         PMD_DRV_LOG(ERR, "Failed to configure "
4938                                         "TC queue mapping.");
4939                         goto fail_msix_alloc;
4940                 }
4941                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4942                 ctxt.info.valid_sections |=
4943                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4944         } else {
4945                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4946                 goto fail_msix_alloc;
4947         }
4948
4949         if (vsi->type != I40E_VSI_MAIN) {
4950                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4951                 if (ret != I40E_SUCCESS) {
4952                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4953                                     hw->aq.asq_last_status);
4954                         goto fail_msix_alloc;
4955                 }
4956                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4957                 vsi->info.valid_sections = 0;
4958                 vsi->seid = ctxt.seid;
4959                 vsi->vsi_id = ctxt.vsi_number;
4960                 vsi->sib_vsi_list.vsi = vsi;
4961                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4962                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4963                                           &vsi->sib_vsi_list, list);
4964                 } else {
4965                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4966                                           &vsi->sib_vsi_list, list);
4967                 }
4968         }
4969
4970         /* MAC/VLAN configuration */
4971         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4972         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4973
4974         ret = i40e_vsi_add_mac(vsi, &filter);
4975         if (ret != I40E_SUCCESS) {
4976                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4977                 goto fail_msix_alloc;
4978         }
4979
4980         /* Get VSI BW information */
4981         i40e_vsi_get_bw_config(vsi);
4982         return vsi;
4983 fail_msix_alloc:
4984         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4985 fail_queue_alloc:
4986         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4987 fail_mem:
4988         rte_free(vsi);
4989         return NULL;
4990 }
4991
4992 /* Configure vlan filter on or off */
4993 int
4994 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4995 {
4996         int i, num;
4997         struct i40e_mac_filter *f;
4998         void *temp;
4999         struct i40e_mac_filter_info *mac_filter;
5000         enum rte_mac_filter_type desired_filter;
5001         int ret = I40E_SUCCESS;
5002
5003         if (on) {
5004                 /* Filter to match MAC and VLAN */
5005                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5006         } else {
5007                 /* Filter to match only MAC */
5008                 desired_filter = RTE_MAC_PERFECT_MATCH;
5009         }
5010
5011         num = vsi->mac_num;
5012
5013         mac_filter = rte_zmalloc("mac_filter_info_data",
5014                                  num * sizeof(*mac_filter), 0);
5015         if (mac_filter == NULL) {
5016                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5017                 return I40E_ERR_NO_MEMORY;
5018         }
5019
5020         i = 0;
5021
5022         /* Remove all existing mac */
5023         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5024                 mac_filter[i] = f->mac_info;
5025                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5026                 if (ret) {
5027                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5028                                     on ? "enable" : "disable");
5029                         goto DONE;
5030                 }
5031                 i++;
5032         }
5033
5034         /* Override with new filter */
5035         for (i = 0; i < num; i++) {
5036                 mac_filter[i].filter_type = desired_filter;
5037                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5038                 if (ret) {
5039                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5040                                     on ? "enable" : "disable");
5041                         goto DONE;
5042                 }
5043         }
5044
5045 DONE:
5046         rte_free(mac_filter);
5047         return ret;
5048 }
5049
5050 /* Configure vlan stripping on or off */
5051 int
5052 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5053 {
5054         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5055         struct i40e_vsi_context ctxt;
5056         uint8_t vlan_flags;
5057         int ret = I40E_SUCCESS;
5058
5059         /* Check if it has been already on or off */
5060         if (vsi->info.valid_sections &
5061                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5062                 if (on) {
5063                         if ((vsi->info.port_vlan_flags &
5064                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5065                                 return 0; /* already on */
5066                 } else {
5067                         if ((vsi->info.port_vlan_flags &
5068                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5069                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5070                                 return 0; /* already off */
5071                 }
5072         }
5073
5074         if (on)
5075                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5076         else
5077                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5078         vsi->info.valid_sections =
5079                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5080         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5081         vsi->info.port_vlan_flags |= vlan_flags;
5082         ctxt.seid = vsi->seid;
5083         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5084         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5085         if (ret)
5086                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5087                             on ? "enable" : "disable");
5088
5089         return ret;
5090 }
5091
5092 static int
5093 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5094 {
5095         struct rte_eth_dev_data *data = dev->data;
5096         int ret;
5097         int mask = 0;
5098
5099         /* Apply vlan offload setting */
5100         mask = ETH_VLAN_STRIP_MASK |
5101                ETH_VLAN_FILTER_MASK |
5102                ETH_VLAN_EXTEND_MASK;
5103         i40e_vlan_offload_set(dev, mask);
5104
5105         /* Apply pvid setting */
5106         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5107                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5108         if (ret)
5109                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5110
5111         return ret;
5112 }
5113
5114 static int
5115 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5116 {
5117         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5118
5119         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5120 }
5121
5122 static int
5123 i40e_update_flow_control(struct i40e_hw *hw)
5124 {
5125 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5126         struct i40e_link_status link_status;
5127         uint32_t rxfc = 0, txfc = 0, reg;
5128         uint8_t an_info;
5129         int ret;
5130
5131         memset(&link_status, 0, sizeof(link_status));
5132         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5133         if (ret != I40E_SUCCESS) {
5134                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5135                 goto write_reg; /* Disable flow control */
5136         }
5137
5138         an_info = hw->phy.link_info.an_info;
5139         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5140                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5141                 ret = I40E_ERR_NOT_READY;
5142                 goto write_reg; /* Disable flow control */
5143         }
5144         /**
5145          * If link auto negotiation is enabled, flow control needs to
5146          * be configured according to it
5147          */
5148         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5149         case I40E_LINK_PAUSE_RXTX:
5150                 rxfc = 1;
5151                 txfc = 1;
5152                 hw->fc.current_mode = I40E_FC_FULL;
5153                 break;
5154         case I40E_AQ_LINK_PAUSE_RX:
5155                 rxfc = 1;
5156                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5157                 break;
5158         case I40E_AQ_LINK_PAUSE_TX:
5159                 txfc = 1;
5160                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5161                 break;
5162         default:
5163                 hw->fc.current_mode = I40E_FC_NONE;
5164                 break;
5165         }
5166
5167 write_reg:
5168         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5169                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5170         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5171         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5172         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5173         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5174
5175         return ret;
5176 }
5177
5178 /* PF setup */
5179 static int
5180 i40e_pf_setup(struct i40e_pf *pf)
5181 {
5182         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5183         struct i40e_filter_control_settings settings;
5184         struct i40e_vsi *vsi;
5185         int ret;
5186
5187         /* Clear all stats counters */
5188         pf->offset_loaded = FALSE;
5189         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5190         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5191         pf->internal_rx_bytes = 0;
5192         pf->internal_tx_bytes = 0;
5193         pf->internal_rx_bytes_offset = 0;
5194         pf->internal_tx_bytes_offset = 0;
5195
5196         ret = i40e_pf_get_switch_config(pf);
5197         if (ret != I40E_SUCCESS) {
5198                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5199                 return ret;
5200         }
5201         if (pf->flags & I40E_FLAG_FDIR) {
5202                 /* make queue allocated first, let FDIR use queue pair 0*/
5203                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5204                 if (ret != I40E_FDIR_QUEUE_ID) {
5205                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5206                                     " ret =%d", ret);
5207                         pf->flags &= ~I40E_FLAG_FDIR;
5208                 }
5209         }
5210         /*  main VSI setup */
5211         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5212         if (!vsi) {
5213                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5214                 return I40E_ERR_NOT_READY;
5215         }
5216         pf->main_vsi = vsi;
5217
5218         /* Configure filter control */
5219         memset(&settings, 0, sizeof(settings));
5220         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5221                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5222         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5223                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5224         else {
5225                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5226                                                 hw->func_caps.rss_table_size);
5227                 return I40E_ERR_PARAM;
5228         }
5229         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5230                         "size: %u\n", hw->func_caps.rss_table_size);
5231         pf->hash_lut_size = hw->func_caps.rss_table_size;
5232
5233         /* Enable ethtype and macvlan filters */
5234         settings.enable_ethtype = TRUE;
5235         settings.enable_macvlan = TRUE;
5236         ret = i40e_set_filter_control(hw, &settings);
5237         if (ret)
5238                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5239                                                                 ret);
5240
5241         /* Update flow control according to the auto negotiation */
5242         i40e_update_flow_control(hw);
5243
5244         return I40E_SUCCESS;
5245 }
5246
5247 int
5248 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5249 {
5250         uint32_t reg;
5251         uint16_t j;
5252
5253         /**
5254          * Set or clear TX Queue Disable flags,
5255          * which is required by hardware.
5256          */
5257         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5258         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5259
5260         /* Wait until the request is finished */
5261         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5262                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5263                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5264                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5265                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5266                                                         & 0x1))) {
5267                         break;
5268                 }
5269         }
5270         if (on) {
5271                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5272                         return I40E_SUCCESS; /* already on, skip next steps */
5273
5274                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5275                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5276         } else {
5277                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5278                         return I40E_SUCCESS; /* already off, skip next steps */
5279                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5280         }
5281         /* Write the register */
5282         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5283         /* Check the result */
5284         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5285                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5286                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5287                 if (on) {
5288                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5289                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5290                                 break;
5291                 } else {
5292                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5293                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5294                                 break;
5295                 }
5296         }
5297         /* Check if it is timeout */
5298         if (j >= I40E_CHK_Q_ENA_COUNT) {
5299                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5300                             (on ? "enable" : "disable"), q_idx);
5301                 return I40E_ERR_TIMEOUT;
5302         }
5303
5304         return I40E_SUCCESS;
5305 }
5306
5307 /* Swith on or off the tx queues */
5308 static int
5309 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5310 {
5311         struct rte_eth_dev_data *dev_data = pf->dev_data;
5312         struct i40e_tx_queue *txq;
5313         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5314         uint16_t i;
5315         int ret;
5316
5317         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5318                 txq = dev_data->tx_queues[i];
5319                 /* Don't operate the queue if not configured or
5320                  * if starting only per queue */
5321                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5322                         continue;
5323                 if (on)
5324                         ret = i40e_dev_tx_queue_start(dev, i);
5325                 else
5326                         ret = i40e_dev_tx_queue_stop(dev, i);
5327                 if ( ret != I40E_SUCCESS)
5328                         return ret;
5329         }
5330
5331         return I40E_SUCCESS;
5332 }
5333
5334 int
5335 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5336 {
5337         uint32_t reg;
5338         uint16_t j;
5339
5340         /* Wait until the request is finished */
5341         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5342                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5343                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5344                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5345                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5346                         break;
5347         }
5348
5349         if (on) {
5350                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5351                         return I40E_SUCCESS; /* Already on, skip next steps */
5352                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5353         } else {
5354                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5355                         return I40E_SUCCESS; /* Already off, skip next steps */
5356                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5357         }
5358
5359         /* Write the register */
5360         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5361         /* Check the result */
5362         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5363                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5364                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5365                 if (on) {
5366                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5367                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5368                                 break;
5369                 } else {
5370                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5371                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5372                                 break;
5373                 }
5374         }
5375
5376         /* Check if it is timeout */
5377         if (j >= I40E_CHK_Q_ENA_COUNT) {
5378                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5379                             (on ? "enable" : "disable"), q_idx);
5380                 return I40E_ERR_TIMEOUT;
5381         }
5382
5383         return I40E_SUCCESS;
5384 }
5385 /* Switch on or off the rx queues */
5386 static int
5387 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5388 {
5389         struct rte_eth_dev_data *dev_data = pf->dev_data;
5390         struct i40e_rx_queue *rxq;
5391         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5392         uint16_t i;
5393         int ret;
5394
5395         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5396                 rxq = dev_data->rx_queues[i];
5397                 /* Don't operate the queue if not configured or
5398                  * if starting only per queue */
5399                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5400                         continue;
5401                 if (on)
5402                         ret = i40e_dev_rx_queue_start(dev, i);
5403                 else
5404                         ret = i40e_dev_rx_queue_stop(dev, i);
5405                 if (ret != I40E_SUCCESS)
5406                         return ret;
5407         }
5408
5409         return I40E_SUCCESS;
5410 }
5411
5412 /* Switch on or off all the rx/tx queues */
5413 int
5414 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5415 {
5416         int ret;
5417
5418         if (on) {
5419                 /* enable rx queues before enabling tx queues */
5420                 ret = i40e_dev_switch_rx_queues(pf, on);
5421                 if (ret) {
5422                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5423                         return ret;
5424                 }
5425                 ret = i40e_dev_switch_tx_queues(pf, on);
5426         } else {
5427                 /* Stop tx queues before stopping rx queues */
5428                 ret = i40e_dev_switch_tx_queues(pf, on);
5429                 if (ret) {
5430                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5431                         return ret;
5432                 }
5433                 ret = i40e_dev_switch_rx_queues(pf, on);
5434         }
5435
5436         return ret;
5437 }
5438
5439 /* Initialize VSI for TX */
5440 static int
5441 i40e_dev_tx_init(struct i40e_pf *pf)
5442 {
5443         struct rte_eth_dev_data *data = pf->dev_data;
5444         uint16_t i;
5445         uint32_t ret = I40E_SUCCESS;
5446         struct i40e_tx_queue *txq;
5447
5448         for (i = 0; i < data->nb_tx_queues; i++) {
5449                 txq = data->tx_queues[i];
5450                 if (!txq || !txq->q_set)
5451                         continue;
5452                 ret = i40e_tx_queue_init(txq);
5453                 if (ret != I40E_SUCCESS)
5454                         break;
5455         }
5456         if (ret == I40E_SUCCESS)
5457                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5458                                      ->eth_dev);
5459
5460         return ret;
5461 }
5462
5463 /* Initialize VSI for RX */
5464 static int
5465 i40e_dev_rx_init(struct i40e_pf *pf)
5466 {
5467         struct rte_eth_dev_data *data = pf->dev_data;
5468         int ret = I40E_SUCCESS;
5469         uint16_t i;
5470         struct i40e_rx_queue *rxq;
5471
5472         i40e_pf_config_mq_rx(pf);
5473         for (i = 0; i < data->nb_rx_queues; i++) {
5474                 rxq = data->rx_queues[i];
5475                 if (!rxq || !rxq->q_set)
5476                         continue;
5477
5478                 ret = i40e_rx_queue_init(rxq);
5479                 if (ret != I40E_SUCCESS) {
5480                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5481                                     "initialization");
5482                         break;
5483                 }
5484         }
5485         if (ret == I40E_SUCCESS)
5486                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5487                                      ->eth_dev);
5488
5489         return ret;
5490 }
5491
5492 static int
5493 i40e_dev_rxtx_init(struct i40e_pf *pf)
5494 {
5495         int err;
5496
5497         err = i40e_dev_tx_init(pf);
5498         if (err) {
5499                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5500                 return err;
5501         }
5502         err = i40e_dev_rx_init(pf);
5503         if (err) {
5504                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5505                 return err;
5506         }
5507
5508         return err;
5509 }
5510
5511 static int
5512 i40e_vmdq_setup(struct rte_eth_dev *dev)
5513 {
5514         struct rte_eth_conf *conf = &dev->data->dev_conf;
5515         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5516         int i, err, conf_vsis, j, loop;
5517         struct i40e_vsi *vsi;
5518         struct i40e_vmdq_info *vmdq_info;
5519         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5520         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5521
5522         /*
5523          * Disable interrupt to avoid message from VF. Furthermore, it will
5524          * avoid race condition in VSI creation/destroy.
5525          */
5526         i40e_pf_disable_irq0(hw);
5527
5528         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5529                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5530                 return -ENOTSUP;
5531         }
5532
5533         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5534         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5535                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5536                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5537                         pf->max_nb_vmdq_vsi);
5538                 return -ENOTSUP;
5539         }
5540
5541         if (pf->vmdq != NULL) {
5542                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5543                 return 0;
5544         }
5545
5546         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5547                                 sizeof(*vmdq_info) * conf_vsis, 0);
5548
5549         if (pf->vmdq == NULL) {
5550                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5551                 return -ENOMEM;
5552         }
5553
5554         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5555
5556         /* Create VMDQ VSI */
5557         for (i = 0; i < conf_vsis; i++) {
5558                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5559                                 vmdq_conf->enable_loop_back);
5560                 if (vsi == NULL) {
5561                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5562                         err = -1;
5563                         goto err_vsi_setup;
5564                 }
5565                 vmdq_info = &pf->vmdq[i];
5566                 vmdq_info->pf = pf;
5567                 vmdq_info->vsi = vsi;
5568         }
5569         pf->nb_cfg_vmdq_vsi = conf_vsis;
5570
5571         /* Configure Vlan */
5572         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5573         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5574                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5575                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5576                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5577                                         vmdq_conf->pool_map[i].vlan_id, j);
5578
5579                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5580                                                 vmdq_conf->pool_map[i].vlan_id);
5581                                 if (err) {
5582                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5583                                         err = -1;
5584                                         goto err_vsi_setup;
5585                                 }
5586                         }
5587                 }
5588         }
5589
5590         i40e_pf_enable_irq0(hw);
5591
5592         return 0;
5593
5594 err_vsi_setup:
5595         for (i = 0; i < conf_vsis; i++)
5596                 if (pf->vmdq[i].vsi == NULL)
5597                         break;
5598                 else
5599                         i40e_vsi_release(pf->vmdq[i].vsi);
5600
5601         rte_free(pf->vmdq);
5602         pf->vmdq = NULL;
5603         i40e_pf_enable_irq0(hw);
5604         return err;
5605 }
5606
5607 static void
5608 i40e_stat_update_32(struct i40e_hw *hw,
5609                    uint32_t reg,
5610                    bool offset_loaded,
5611                    uint64_t *offset,
5612                    uint64_t *stat)
5613 {
5614         uint64_t new_data;
5615
5616         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5617         if (!offset_loaded)
5618                 *offset = new_data;
5619
5620         if (new_data >= *offset)
5621                 *stat = (uint64_t)(new_data - *offset);
5622         else
5623                 *stat = (uint64_t)((new_data +
5624                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5625 }
5626
5627 static void
5628 i40e_stat_update_48(struct i40e_hw *hw,
5629                    uint32_t hireg,
5630                    uint32_t loreg,
5631                    bool offset_loaded,
5632                    uint64_t *offset,
5633                    uint64_t *stat)
5634 {
5635         uint64_t new_data;
5636
5637         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5638         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5639                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5640
5641         if (!offset_loaded)
5642                 *offset = new_data;
5643
5644         if (new_data >= *offset)
5645                 *stat = new_data - *offset;
5646         else
5647                 *stat = (uint64_t)((new_data +
5648                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5649
5650         *stat &= I40E_48_BIT_MASK;
5651 }
5652
5653 /* Disable IRQ0 */
5654 void
5655 i40e_pf_disable_irq0(struct i40e_hw *hw)
5656 {
5657         /* Disable all interrupt types */
5658         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5659                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5660         I40E_WRITE_FLUSH(hw);
5661 }
5662
5663 /* Enable IRQ0 */
5664 void
5665 i40e_pf_enable_irq0(struct i40e_hw *hw)
5666 {
5667         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5668                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5669                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5670                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5671         I40E_WRITE_FLUSH(hw);
5672 }
5673
5674 static void
5675 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5676 {
5677         /* read pending request and disable first */
5678         i40e_pf_disable_irq0(hw);
5679         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5680         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5681                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5682
5683         if (no_queue)
5684                 /* Link no queues with irq0 */
5685                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5686                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5687 }
5688
5689 static void
5690 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5691 {
5692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5694         int i;
5695         uint16_t abs_vf_id;
5696         uint32_t index, offset, val;
5697
5698         if (!pf->vfs)
5699                 return;
5700         /**
5701          * Try to find which VF trigger a reset, use absolute VF id to access
5702          * since the reg is global register.
5703          */
5704         for (i = 0; i < pf->vf_num; i++) {
5705                 abs_vf_id = hw->func_caps.vf_base_id + i;
5706                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5707                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5708                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5709                 /* VFR event occured */
5710                 if (val & (0x1 << offset)) {
5711                         int ret;
5712
5713                         /* Clear the event first */
5714                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5715                                                         (0x1 << offset));
5716                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5717                         /**
5718                          * Only notify a VF reset event occured,
5719                          * don't trigger another SW reset
5720                          */
5721                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5722                         if (ret != I40E_SUCCESS)
5723                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5724                 }
5725         }
5726 }
5727
5728 static void
5729 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5730 {
5731         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5732         struct i40e_virtchnl_pf_event event;
5733         int i;
5734
5735         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5736         event.event_data.link_event.link_status =
5737                 dev->data->dev_link.link_status;
5738         event.event_data.link_event.link_speed =
5739                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5740
5741         for (i = 0; i < pf->vf_num; i++)
5742                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5743                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5744 }
5745
5746 static void
5747 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5748 {
5749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750         struct i40e_arq_event_info info;
5751         uint16_t pending, opcode;
5752         int ret;
5753
5754         info.buf_len = I40E_AQ_BUF_SZ;
5755         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5756         if (!info.msg_buf) {
5757                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5758                 return;
5759         }
5760
5761         pending = 1;
5762         while (pending) {
5763                 ret = i40e_clean_arq_element(hw, &info, &pending);
5764
5765                 if (ret != I40E_SUCCESS) {
5766                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5767                                     "aq_err: %u", hw->aq.asq_last_status);
5768                         break;
5769                 }
5770                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5771
5772                 switch (opcode) {
5773                 case i40e_aqc_opc_send_msg_to_pf:
5774                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5775                         i40e_pf_host_handle_vf_msg(dev,
5776                                         rte_le_to_cpu_16(info.desc.retval),
5777                                         rte_le_to_cpu_32(info.desc.cookie_high),
5778                                         rte_le_to_cpu_32(info.desc.cookie_low),
5779                                         info.msg_buf,
5780                                         info.msg_len);
5781                         break;
5782                 case i40e_aqc_opc_get_link_status:
5783                         ret = i40e_dev_link_update(dev, 0);
5784                         if (!ret)
5785                                 _rte_eth_dev_callback_process(dev,
5786                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5787                         break;
5788                 default:
5789                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5790                                     opcode);
5791                         break;
5792                 }
5793         }
5794         rte_free(info.msg_buf);
5795 }
5796
5797 /**
5798  * Interrupt handler triggered by NIC  for handling
5799  * specific interrupt.
5800  *
5801  * @param handle
5802  *  Pointer to interrupt handle.
5803  * @param param
5804  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5805  *
5806  * @return
5807  *  void
5808  */
5809 static void
5810 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5811                            void *param)
5812 {
5813         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5815         uint32_t icr0;
5816
5817         /* Disable interrupt */
5818         i40e_pf_disable_irq0(hw);
5819
5820         /* read out interrupt causes */
5821         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5822
5823         /* No interrupt event indicated */
5824         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5825                 PMD_DRV_LOG(INFO, "No interrupt event");
5826                 goto done;
5827         }
5828 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5829         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5830                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5831         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5832                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5833         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5834                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5835         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5836                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5837         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5838                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5839         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5840                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5841         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5842                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5843 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5844
5845         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5846                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5847                 i40e_dev_handle_vfr_event(dev);
5848         }
5849         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5850                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5851                 i40e_dev_handle_aq_msg(dev);
5852         }
5853
5854 done:
5855         /* Enable interrupt */
5856         i40e_pf_enable_irq0(hw);
5857         rte_intr_enable(&(dev->pci_dev->intr_handle));
5858 }
5859
5860 static int
5861 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5862                          struct i40e_macvlan_filter *filter,
5863                          int total)
5864 {
5865         int ele_num, ele_buff_size;
5866         int num, actual_num, i;
5867         uint16_t flags;
5868         int ret = I40E_SUCCESS;
5869         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5870         struct i40e_aqc_add_macvlan_element_data *req_list;
5871
5872         if (filter == NULL  || total == 0)
5873                 return I40E_ERR_PARAM;
5874         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5875         ele_buff_size = hw->aq.asq_buf_size;
5876
5877         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5878         if (req_list == NULL) {
5879                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5880                 return I40E_ERR_NO_MEMORY;
5881         }
5882
5883         num = 0;
5884         do {
5885                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5886                 memset(req_list, 0, ele_buff_size);
5887
5888                 for (i = 0; i < actual_num; i++) {
5889                         (void)rte_memcpy(req_list[i].mac_addr,
5890                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5891                         req_list[i].vlan_tag =
5892                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5893
5894                         switch (filter[num + i].filter_type) {
5895                         case RTE_MAC_PERFECT_MATCH:
5896                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5897                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5898                                 break;
5899                         case RTE_MACVLAN_PERFECT_MATCH:
5900                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5901                                 break;
5902                         case RTE_MAC_HASH_MATCH:
5903                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5904                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5905                                 break;
5906                         case RTE_MACVLAN_HASH_MATCH:
5907                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5908                                 break;
5909                         default:
5910                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5911                                 ret = I40E_ERR_PARAM;
5912                                 goto DONE;
5913                         }
5914
5915                         req_list[i].queue_number = 0;
5916
5917                         req_list[i].flags = rte_cpu_to_le_16(flags);
5918                 }
5919
5920                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5921                                                 actual_num, NULL);
5922                 if (ret != I40E_SUCCESS) {
5923                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5924                         goto DONE;
5925                 }
5926                 num += actual_num;
5927         } while (num < total);
5928
5929 DONE:
5930         rte_free(req_list);
5931         return ret;
5932 }
5933
5934 static int
5935 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5936                             struct i40e_macvlan_filter *filter,
5937                             int total)
5938 {
5939         int ele_num, ele_buff_size;
5940         int num, actual_num, i;
5941         uint16_t flags;
5942         int ret = I40E_SUCCESS;
5943         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5944         struct i40e_aqc_remove_macvlan_element_data *req_list;
5945
5946         if (filter == NULL  || total == 0)
5947                 return I40E_ERR_PARAM;
5948
5949         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5950         ele_buff_size = hw->aq.asq_buf_size;
5951
5952         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5953         if (req_list == NULL) {
5954                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5955                 return I40E_ERR_NO_MEMORY;
5956         }
5957
5958         num = 0;
5959         do {
5960                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5961                 memset(req_list, 0, ele_buff_size);
5962
5963                 for (i = 0; i < actual_num; i++) {
5964                         (void)rte_memcpy(req_list[i].mac_addr,
5965                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5966                         req_list[i].vlan_tag =
5967                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5968
5969                         switch (filter[num + i].filter_type) {
5970                         case RTE_MAC_PERFECT_MATCH:
5971                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5972                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5973                                 break;
5974                         case RTE_MACVLAN_PERFECT_MATCH:
5975                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5976                                 break;
5977                         case RTE_MAC_HASH_MATCH:
5978                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5979                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5980                                 break;
5981                         case RTE_MACVLAN_HASH_MATCH:
5982                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5983                                 break;
5984                         default:
5985                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5986                                 ret = I40E_ERR_PARAM;
5987                                 goto DONE;
5988                         }
5989                         req_list[i].flags = rte_cpu_to_le_16(flags);
5990                 }
5991
5992                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5993                                                 actual_num, NULL);
5994                 if (ret != I40E_SUCCESS) {
5995                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5996                         goto DONE;
5997                 }
5998                 num += actual_num;
5999         } while (num < total);
6000
6001 DONE:
6002         rte_free(req_list);
6003         return ret;
6004 }
6005
6006 /* Find out specific MAC filter */
6007 static struct i40e_mac_filter *
6008 i40e_find_mac_filter(struct i40e_vsi *vsi,
6009                          struct ether_addr *macaddr)
6010 {
6011         struct i40e_mac_filter *f;
6012
6013         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6014                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6015                         return f;
6016         }
6017
6018         return NULL;
6019 }
6020
6021 static bool
6022 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6023                          uint16_t vlan_id)
6024 {
6025         uint32_t vid_idx, vid_bit;
6026
6027         if (vlan_id > ETH_VLAN_ID_MAX)
6028                 return 0;
6029
6030         vid_idx = I40E_VFTA_IDX(vlan_id);
6031         vid_bit = I40E_VFTA_BIT(vlan_id);
6032
6033         if (vsi->vfta[vid_idx] & vid_bit)
6034                 return 1;
6035         else
6036                 return 0;
6037 }
6038
6039 static void
6040 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6041                          uint16_t vlan_id, bool on)
6042 {
6043         uint32_t vid_idx, vid_bit;
6044
6045         if (vlan_id > ETH_VLAN_ID_MAX)
6046                 return;
6047
6048         vid_idx = I40E_VFTA_IDX(vlan_id);
6049         vid_bit = I40E_VFTA_BIT(vlan_id);
6050
6051         if (on)
6052                 vsi->vfta[vid_idx] |= vid_bit;
6053         else
6054                 vsi->vfta[vid_idx] &= ~vid_bit;
6055 }
6056
6057 /**
6058  * Find all vlan options for specific mac addr,
6059  * return with actual vlan found.
6060  */
6061 static inline int
6062 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6063                            struct i40e_macvlan_filter *mv_f,
6064                            int num, struct ether_addr *addr)
6065 {
6066         int i;
6067         uint32_t j, k;
6068
6069         /**
6070          * Not to use i40e_find_vlan_filter to decrease the loop time,
6071          * although the code looks complex.
6072           */
6073         if (num < vsi->vlan_num)
6074                 return I40E_ERR_PARAM;
6075
6076         i = 0;
6077         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6078                 if (vsi->vfta[j]) {
6079                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6080                                 if (vsi->vfta[j] & (1 << k)) {
6081                                         if (i > num - 1) {
6082                                                 PMD_DRV_LOG(ERR, "vlan number "
6083                                                             "not match");
6084                                                 return I40E_ERR_PARAM;
6085                                         }
6086                                         (void)rte_memcpy(&mv_f[i].macaddr,
6087                                                         addr, ETH_ADDR_LEN);
6088                                         mv_f[i].vlan_id =
6089                                                 j * I40E_UINT32_BIT_SIZE + k;
6090                                         i++;
6091                                 }
6092                         }
6093                 }
6094         }
6095         return I40E_SUCCESS;
6096 }
6097
6098 static inline int
6099 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6100                            struct i40e_macvlan_filter *mv_f,
6101                            int num,
6102                            uint16_t vlan)
6103 {
6104         int i = 0;
6105         struct i40e_mac_filter *f;
6106
6107         if (num < vsi->mac_num)
6108                 return I40E_ERR_PARAM;
6109
6110         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6111                 if (i > num - 1) {
6112                         PMD_DRV_LOG(ERR, "buffer number not match");
6113                         return I40E_ERR_PARAM;
6114                 }
6115                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6116                                 ETH_ADDR_LEN);
6117                 mv_f[i].vlan_id = vlan;
6118                 mv_f[i].filter_type = f->mac_info.filter_type;
6119                 i++;
6120         }
6121
6122         return I40E_SUCCESS;
6123 }
6124
6125 static int
6126 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6127 {
6128         int i, j, num;
6129         struct i40e_mac_filter *f;
6130         struct i40e_macvlan_filter *mv_f;
6131         int ret = I40E_SUCCESS;
6132
6133         if (vsi == NULL || vsi->mac_num == 0)
6134                 return I40E_ERR_PARAM;
6135
6136         /* Case that no vlan is set */
6137         if (vsi->vlan_num == 0)
6138                 num = vsi->mac_num;
6139         else
6140                 num = vsi->mac_num * vsi->vlan_num;
6141
6142         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6143         if (mv_f == NULL) {
6144                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6145                 return I40E_ERR_NO_MEMORY;
6146         }
6147
6148         i = 0;
6149         if (vsi->vlan_num == 0) {
6150                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6151                         (void)rte_memcpy(&mv_f[i].macaddr,
6152                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6153                         mv_f[i].filter_type = f->mac_info.filter_type;
6154                         mv_f[i].vlan_id = 0;
6155                         i++;
6156                 }
6157         } else {
6158                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6159                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6160                                         vsi->vlan_num, &f->mac_info.mac_addr);
6161                         if (ret != I40E_SUCCESS)
6162                                 goto DONE;
6163                         for (j = i; j < i + vsi->vlan_num; j++)
6164                                 mv_f[j].filter_type = f->mac_info.filter_type;
6165                         i += vsi->vlan_num;
6166                 }
6167         }
6168
6169         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6170 DONE:
6171         rte_free(mv_f);
6172
6173         return ret;
6174 }
6175
6176 int
6177 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6178 {
6179         struct i40e_macvlan_filter *mv_f;
6180         int mac_num;
6181         int ret = I40E_SUCCESS;
6182
6183         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6184                 return I40E_ERR_PARAM;
6185
6186         /* If it's already set, just return */
6187         if (i40e_find_vlan_filter(vsi,vlan))
6188                 return I40E_SUCCESS;
6189
6190         mac_num = vsi->mac_num;
6191
6192         if (mac_num == 0) {
6193                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6194                 return I40E_ERR_PARAM;
6195         }
6196
6197         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6198
6199         if (mv_f == NULL) {
6200                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6201                 return I40E_ERR_NO_MEMORY;
6202         }
6203
6204         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6205
6206         if (ret != I40E_SUCCESS)
6207                 goto DONE;
6208
6209         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6210
6211         if (ret != I40E_SUCCESS)
6212                 goto DONE;
6213
6214         i40e_set_vlan_filter(vsi, vlan, 1);
6215
6216         vsi->vlan_num++;
6217         ret = I40E_SUCCESS;
6218 DONE:
6219         rte_free(mv_f);
6220         return ret;
6221 }
6222
6223 int
6224 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6225 {
6226         struct i40e_macvlan_filter *mv_f;
6227         int mac_num;
6228         int ret = I40E_SUCCESS;
6229
6230         /**
6231          * Vlan 0 is the generic filter for untagged packets
6232          * and can't be removed.
6233          */
6234         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6235                 return I40E_ERR_PARAM;
6236
6237         /* If can't find it, just return */
6238         if (!i40e_find_vlan_filter(vsi, vlan))
6239                 return I40E_ERR_PARAM;
6240
6241         mac_num = vsi->mac_num;
6242
6243         if (mac_num == 0) {
6244                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6245                 return I40E_ERR_PARAM;
6246         }
6247
6248         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6249
6250         if (mv_f == NULL) {
6251                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6252                 return I40E_ERR_NO_MEMORY;
6253         }
6254
6255         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6256
6257         if (ret != I40E_SUCCESS)
6258                 goto DONE;
6259
6260         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6261
6262         if (ret != I40E_SUCCESS)
6263                 goto DONE;
6264
6265         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6266         if (vsi->vlan_num == 1) {
6267                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6268                 if (ret != I40E_SUCCESS)
6269                         goto DONE;
6270
6271                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6272                 if (ret != I40E_SUCCESS)
6273                         goto DONE;
6274         }
6275
6276         i40e_set_vlan_filter(vsi, vlan, 0);
6277
6278         vsi->vlan_num--;
6279         ret = I40E_SUCCESS;
6280 DONE:
6281         rte_free(mv_f);
6282         return ret;
6283 }
6284
6285 int
6286 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6287 {
6288         struct i40e_mac_filter *f;
6289         struct i40e_macvlan_filter *mv_f;
6290         int i, vlan_num = 0;
6291         int ret = I40E_SUCCESS;
6292
6293         /* If it's add and we've config it, return */
6294         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6295         if (f != NULL)
6296                 return I40E_SUCCESS;
6297         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6298                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6299
6300                 /**
6301                  * If vlan_num is 0, that's the first time to add mac,
6302                  * set mask for vlan_id 0.
6303                  */
6304                 if (vsi->vlan_num == 0) {
6305                         i40e_set_vlan_filter(vsi, 0, 1);
6306                         vsi->vlan_num = 1;
6307                 }
6308                 vlan_num = vsi->vlan_num;
6309         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6310                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6311                 vlan_num = 1;
6312
6313         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6314         if (mv_f == NULL) {
6315                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6316                 return I40E_ERR_NO_MEMORY;
6317         }
6318
6319         for (i = 0; i < vlan_num; i++) {
6320                 mv_f[i].filter_type = mac_filter->filter_type;
6321                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6322                                 ETH_ADDR_LEN);
6323         }
6324
6325         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6326                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6327                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6328                                         &mac_filter->mac_addr);
6329                 if (ret != I40E_SUCCESS)
6330                         goto DONE;
6331         }
6332
6333         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6334         if (ret != I40E_SUCCESS)
6335                 goto DONE;
6336
6337         /* Add the mac addr into mac list */
6338         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6339         if (f == NULL) {
6340                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6341                 ret = I40E_ERR_NO_MEMORY;
6342                 goto DONE;
6343         }
6344         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6345                         ETH_ADDR_LEN);
6346         f->mac_info.filter_type = mac_filter->filter_type;
6347         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6348         vsi->mac_num++;
6349
6350         ret = I40E_SUCCESS;
6351 DONE:
6352         rte_free(mv_f);
6353
6354         return ret;
6355 }
6356
6357 int
6358 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6359 {
6360         struct i40e_mac_filter *f;
6361         struct i40e_macvlan_filter *mv_f;
6362         int i, vlan_num;
6363         enum rte_mac_filter_type filter_type;
6364         int ret = I40E_SUCCESS;
6365
6366         /* Can't find it, return an error */
6367         f = i40e_find_mac_filter(vsi, addr);
6368         if (f == NULL)
6369                 return I40E_ERR_PARAM;
6370
6371         vlan_num = vsi->vlan_num;
6372         filter_type = f->mac_info.filter_type;
6373         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6374                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6375                 if (vlan_num == 0) {
6376                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6377                         return I40E_ERR_PARAM;
6378                 }
6379         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6380                         filter_type == RTE_MAC_HASH_MATCH)
6381                 vlan_num = 1;
6382
6383         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6384         if (mv_f == NULL) {
6385                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6386                 return I40E_ERR_NO_MEMORY;
6387         }
6388
6389         for (i = 0; i < vlan_num; i++) {
6390                 mv_f[i].filter_type = filter_type;
6391                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6392                                 ETH_ADDR_LEN);
6393         }
6394         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6395                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6396                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6397                 if (ret != I40E_SUCCESS)
6398                         goto DONE;
6399         }
6400
6401         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6402         if (ret != I40E_SUCCESS)
6403                 goto DONE;
6404
6405         /* Remove the mac addr into mac list */
6406         TAILQ_REMOVE(&vsi->mac_list, f, next);
6407         rte_free(f);
6408         vsi->mac_num--;
6409
6410         ret = I40E_SUCCESS;
6411 DONE:
6412         rte_free(mv_f);
6413         return ret;
6414 }
6415
6416 /* Configure hash enable flags for RSS */
6417 uint64_t
6418 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6419 {
6420         uint64_t hena = 0;
6421
6422         if (!flags)
6423                 return hena;
6424
6425         if (flags & ETH_RSS_FRAG_IPV4)
6426                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6427         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6428                 if (type == I40E_MAC_X722) {
6429                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6430                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6431                 } else
6432                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6433         }
6434         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6435                 if (type == I40E_MAC_X722) {
6436                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6437                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6438                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6439                 } else
6440                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6441         }
6442         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6443                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6444         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6445                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6446         if (flags & ETH_RSS_FRAG_IPV6)
6447                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6448         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6449                 if (type == I40E_MAC_X722) {
6450                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6451                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6452                 } else
6453                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6454         }
6455         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6456                 if (type == I40E_MAC_X722) {
6457                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6458                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6459                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6460                 } else
6461                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6462         }
6463         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6464                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6465         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6466                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6467         if (flags & ETH_RSS_L2_PAYLOAD)
6468                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6469
6470         return hena;
6471 }
6472
6473 /* Parse the hash enable flags */
6474 uint64_t
6475 i40e_parse_hena(uint64_t flags)
6476 {
6477         uint64_t rss_hf = 0;
6478
6479         if (!flags)
6480                 return rss_hf;
6481         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6482                 rss_hf |= ETH_RSS_FRAG_IPV4;
6483         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6484                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6485 #ifdef X722_SUPPORT
6486         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6487                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6488 #endif
6489         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6490                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6491 #ifdef X722_SUPPORT
6492         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6493                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6494         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6495                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6496 #endif
6497         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6498                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6499         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6500                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6501         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6502                 rss_hf |= ETH_RSS_FRAG_IPV6;
6503         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6504                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6505 #ifdef X722_SUPPORT
6506         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6507                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6508 #endif
6509         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6510                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6511 #ifdef X722_SUPPORT
6512         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6513                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6514         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6515                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6516 #endif
6517         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6518                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6519         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6520                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6521         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6522                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6523
6524         return rss_hf;
6525 }
6526
6527 /* Disable RSS */
6528 static void
6529 i40e_pf_disable_rss(struct i40e_pf *pf)
6530 {
6531         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6532         uint64_t hena;
6533
6534         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6535         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6536         if (hw->mac.type == I40E_MAC_X722)
6537                 hena &= ~I40E_RSS_HENA_ALL_X722;
6538         else
6539                 hena &= ~I40E_RSS_HENA_ALL;
6540         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6541         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6542         I40E_WRITE_FLUSH(hw);
6543 }
6544
6545 static int
6546 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6547 {
6548         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6549         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6550         int ret = 0;
6551
6552         if (!key || key_len == 0) {
6553                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6554                 return 0;
6555         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6556                 sizeof(uint32_t)) {
6557                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6558                 return -EINVAL;
6559         }
6560
6561         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6562                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6563                         (struct i40e_aqc_get_set_rss_key_data *)key;
6564
6565                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6566                 if (ret)
6567                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6568                                      "via AQ");
6569         } else {
6570                 uint32_t *hash_key = (uint32_t *)key;
6571                 uint16_t i;
6572
6573                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6574                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6575                 I40E_WRITE_FLUSH(hw);
6576         }
6577
6578         return ret;
6579 }
6580
6581 static int
6582 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6583 {
6584         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6585         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6586         int ret;
6587
6588         if (!key || !key_len)
6589                 return -EINVAL;
6590
6591         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6592                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6593                         (struct i40e_aqc_get_set_rss_key_data *)key);
6594                 if (ret) {
6595                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6596                         return ret;
6597                 }
6598         } else {
6599                 uint32_t *key_dw = (uint32_t *)key;
6600                 uint16_t i;
6601
6602                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6603                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6604         }
6605         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6606
6607         return 0;
6608 }
6609
6610 static int
6611 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6612 {
6613         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6614         uint64_t rss_hf;
6615         uint64_t hena;
6616         int ret;
6617
6618         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6619                                rss_conf->rss_key_len);
6620         if (ret)
6621                 return ret;
6622
6623         rss_hf = rss_conf->rss_hf;
6624         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6625         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6626         if (hw->mac.type == I40E_MAC_X722)
6627                 hena &= ~I40E_RSS_HENA_ALL_X722;
6628         else
6629                 hena &= ~I40E_RSS_HENA_ALL;
6630         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6631         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6632         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6633         I40E_WRITE_FLUSH(hw);
6634
6635         return 0;
6636 }
6637
6638 static int
6639 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6640                          struct rte_eth_rss_conf *rss_conf)
6641 {
6642         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6643         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6644         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6645         uint64_t hena;
6646
6647         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6648         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6649         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6650                  ? I40E_RSS_HENA_ALL_X722
6651                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6652                 if (rss_hf != 0) /* Enable RSS */
6653                         return -EINVAL;
6654                 return 0; /* Nothing to do */
6655         }
6656         /* RSS enabled */
6657         if (rss_hf == 0) /* Disable RSS */
6658                 return -EINVAL;
6659
6660         return i40e_hw_rss_hash_set(pf, rss_conf);
6661 }
6662
6663 static int
6664 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6665                            struct rte_eth_rss_conf *rss_conf)
6666 {
6667         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6668         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6669         uint64_t hena;
6670
6671         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6672                          &rss_conf->rss_key_len);
6673
6674         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6675         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6676         rss_conf->rss_hf = i40e_parse_hena(hena);
6677
6678         return 0;
6679 }
6680
6681 static int
6682 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6683 {
6684         switch (filter_type) {
6685         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6686                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6687                 break;
6688         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6689                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6690                 break;
6691         case RTE_TUNNEL_FILTER_IMAC_TENID:
6692                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6693                 break;
6694         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6695                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6696                 break;
6697         case ETH_TUNNEL_FILTER_IMAC:
6698                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6699                 break;
6700         case ETH_TUNNEL_FILTER_OIP:
6701                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6702                 break;
6703         case ETH_TUNNEL_FILTER_IIP:
6704                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6705                 break;
6706         default:
6707                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6708                 return -EINVAL;
6709         }
6710
6711         return 0;
6712 }
6713
6714 static int
6715 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6716                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6717                         uint8_t add)
6718 {
6719         uint16_t ip_type;
6720         uint32_t ipv4_addr, ipv4_addr_le;
6721         uint8_t i, tun_type = 0;
6722         /* internal varialbe to convert ipv6 byte order */
6723         uint32_t convert_ipv6[4];
6724         int val, ret = 0;
6725         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6726         struct i40e_vsi *vsi = pf->main_vsi;
6727         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6728         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6729
6730         cld_filter = rte_zmalloc("tunnel_filter",
6731                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6732                 0);
6733
6734         if (NULL == cld_filter) {
6735                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6736                 return -EINVAL;
6737         }
6738         pfilter = cld_filter;
6739
6740         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6741         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6742
6743         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6744         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6745                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6746                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6747                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
6748                 rte_memcpy(&pfilter->ipaddr.v4.data,
6749                                 &ipv4_addr_le,
6750                                 sizeof(pfilter->ipaddr.v4.data));
6751         } else {
6752                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6753                 for (i = 0; i < 4; i++) {
6754                         convert_ipv6[i] =
6755                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6756                 }
6757                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6758                                 sizeof(pfilter->ipaddr.v6.data));
6759         }
6760
6761         /* check tunneled type */
6762         switch (tunnel_filter->tunnel_type) {
6763         case RTE_TUNNEL_TYPE_VXLAN:
6764                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6765                 break;
6766         case RTE_TUNNEL_TYPE_NVGRE:
6767                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6768                 break;
6769         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6770                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6771                 break;
6772         default:
6773                 /* Other tunnel types is not supported. */
6774                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6775                 rte_free(cld_filter);
6776                 return -EINVAL;
6777         }
6778
6779         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6780                                                 &pfilter->flags);
6781         if (val < 0) {
6782                 rte_free(cld_filter);
6783                 return -EINVAL;
6784         }
6785
6786         pfilter->flags |= rte_cpu_to_le_16(
6787                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6788                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6789         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6790         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6791
6792         if (add)
6793                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6794         else
6795                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6796                                                 cld_filter, 1);
6797
6798         rte_free(cld_filter);
6799         return ret;
6800 }
6801
6802 static int
6803 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6804 {
6805         uint8_t i;
6806
6807         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6808                 if (pf->vxlan_ports[i] == port)
6809                         return i;
6810         }
6811
6812         return -1;
6813 }
6814
6815 static int
6816 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6817 {
6818         int  idx, ret;
6819         uint8_t filter_idx;
6820         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6821
6822         idx = i40e_get_vxlan_port_idx(pf, port);
6823
6824         /* Check if port already exists */
6825         if (idx >= 0) {
6826                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6827                 return -EINVAL;
6828         }
6829
6830         /* Now check if there is space to add the new port */
6831         idx = i40e_get_vxlan_port_idx(pf, 0);
6832         if (idx < 0) {
6833                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6834                         "not adding port %d", port);
6835                 return -ENOSPC;
6836         }
6837
6838         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6839                                         &filter_idx, NULL);
6840         if (ret < 0) {
6841                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6842                 return -1;
6843         }
6844
6845         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6846                          port,  filter_idx);
6847
6848         /* New port: add it and mark its index in the bitmap */
6849         pf->vxlan_ports[idx] = port;
6850         pf->vxlan_bitmap |= (1 << idx);
6851
6852         if (!(pf->flags & I40E_FLAG_VXLAN))
6853                 pf->flags |= I40E_FLAG_VXLAN;
6854
6855         return 0;
6856 }
6857
6858 static int
6859 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6860 {
6861         int idx;
6862         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6863
6864         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6865                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6866                 return -EINVAL;
6867         }
6868
6869         idx = i40e_get_vxlan_port_idx(pf, port);
6870
6871         if (idx < 0) {
6872                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6873                 return -EINVAL;
6874         }
6875
6876         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6877                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6878                 return -1;
6879         }
6880
6881         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6882                         port, idx);
6883
6884         pf->vxlan_ports[idx] = 0;
6885         pf->vxlan_bitmap &= ~(1 << idx);
6886
6887         if (!pf->vxlan_bitmap)
6888                 pf->flags &= ~I40E_FLAG_VXLAN;
6889
6890         return 0;
6891 }
6892
6893 /* Add UDP tunneling port */
6894 static int
6895 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6896                              struct rte_eth_udp_tunnel *udp_tunnel)
6897 {
6898         int ret = 0;
6899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6900
6901         if (udp_tunnel == NULL)
6902                 return -EINVAL;
6903
6904         switch (udp_tunnel->prot_type) {
6905         case RTE_TUNNEL_TYPE_VXLAN:
6906                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6907                 break;
6908
6909         case RTE_TUNNEL_TYPE_GENEVE:
6910         case RTE_TUNNEL_TYPE_TEREDO:
6911                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6912                 ret = -1;
6913                 break;
6914
6915         default:
6916                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6917                 ret = -1;
6918                 break;
6919         }
6920
6921         return ret;
6922 }
6923
6924 /* Remove UDP tunneling port */
6925 static int
6926 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6927                              struct rte_eth_udp_tunnel *udp_tunnel)
6928 {
6929         int ret = 0;
6930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6931
6932         if (udp_tunnel == NULL)
6933                 return -EINVAL;
6934
6935         switch (udp_tunnel->prot_type) {
6936         case RTE_TUNNEL_TYPE_VXLAN:
6937                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6938                 break;
6939         case RTE_TUNNEL_TYPE_GENEVE:
6940         case RTE_TUNNEL_TYPE_TEREDO:
6941                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6942                 ret = -1;
6943                 break;
6944         default:
6945                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6946                 ret = -1;
6947                 break;
6948         }
6949
6950         return ret;
6951 }
6952
6953 /* Calculate the maximum number of contiguous PF queues that are configured */
6954 static int
6955 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6956 {
6957         struct rte_eth_dev_data *data = pf->dev_data;
6958         int i, num;
6959         struct i40e_rx_queue *rxq;
6960
6961         num = 0;
6962         for (i = 0; i < pf->lan_nb_qps; i++) {
6963                 rxq = data->rx_queues[i];
6964                 if (rxq && rxq->q_set)
6965                         num++;
6966                 else
6967                         break;
6968         }
6969
6970         return num;
6971 }
6972
6973 /* Configure RSS */
6974 static int
6975 i40e_pf_config_rss(struct i40e_pf *pf)
6976 {
6977         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6978         struct rte_eth_rss_conf rss_conf;
6979         uint32_t i, lut = 0;
6980         uint16_t j, num;
6981
6982         /*
6983          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6984          * It's necessary to calulate the actual PF queues that are configured.
6985          */
6986         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6987                 num = i40e_pf_calc_configured_queues_num(pf);
6988         else
6989                 num = pf->dev_data->nb_rx_queues;
6990
6991         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6992         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6993                         num);
6994
6995         if (num == 0) {
6996                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6997                 return -ENOTSUP;
6998         }
6999
7000         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7001                 if (j == num)
7002                         j = 0;
7003                 lut = (lut << 8) | (j & ((0x1 <<
7004                         hw->func_caps.rss_table_entry_width) - 1));
7005                 if ((i & 3) == 3)
7006                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7007         }
7008
7009         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7010         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7011                 i40e_pf_disable_rss(pf);
7012                 return 0;
7013         }
7014         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7015                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7016                 /* Random default keys */
7017                 static uint32_t rss_key_default[] = {0x6b793944,
7018                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7019                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7020                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7021
7022                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7023                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7024                                                         sizeof(uint32_t);
7025         }
7026
7027         return i40e_hw_rss_hash_set(pf, &rss_conf);
7028 }
7029
7030 static int
7031 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7032                                struct rte_eth_tunnel_filter_conf *filter)
7033 {
7034         if (pf == NULL || filter == NULL) {
7035                 PMD_DRV_LOG(ERR, "Invalid parameter");
7036                 return -EINVAL;
7037         }
7038
7039         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7040                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7041                 return -EINVAL;
7042         }
7043
7044         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7045                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7046                 return -EINVAL;
7047         }
7048
7049         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7050                 (is_zero_ether_addr(&filter->outer_mac))) {
7051                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7052                 return -EINVAL;
7053         }
7054
7055         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7056                 (is_zero_ether_addr(&filter->inner_mac))) {
7057                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7058                 return -EINVAL;
7059         }
7060
7061         return 0;
7062 }
7063
7064 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7065 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7066 static int
7067 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7068 {
7069         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7070         uint32_t val, reg;
7071         int ret = -EINVAL;
7072
7073         if (pf->support_multi_driver) {
7074                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
7075                 return -ENOTSUP;
7076         }
7077
7078         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7079         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7080
7081         if (len == 3) {
7082                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7083         } else if (len == 4) {
7084                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7085         } else {
7086                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7087                 return ret;
7088         }
7089
7090         if (reg != val) {
7091                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7092                                                    reg, NULL);
7093                 if (ret != 0)
7094                         return ret;
7095                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
7096                             "with value 0x%08x",
7097                             I40E_GL_PRS_FVBM(2), reg);
7098                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
7099         } else {
7100                 ret = 0;
7101         }
7102         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7103                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7104
7105         return ret;
7106 }
7107
7108 static int
7109 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7110 {
7111         int ret = -EINVAL;
7112
7113         if (!hw || !cfg)
7114                 return -EINVAL;
7115
7116         switch (cfg->cfg_type) {
7117         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7118                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7119                 break;
7120         default:
7121                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7122                 break;
7123         }
7124
7125         return ret;
7126 }
7127
7128 static int
7129 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7130                                enum rte_filter_op filter_op,
7131                                void *arg)
7132 {
7133         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7134         int ret = I40E_ERR_PARAM;
7135
7136         switch (filter_op) {
7137         case RTE_ETH_FILTER_SET:
7138                 ret = i40e_dev_global_config_set(hw,
7139                         (struct rte_eth_global_cfg *)arg);
7140                 break;
7141         default:
7142                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7143                 break;
7144         }
7145
7146         return ret;
7147 }
7148
7149 static int
7150 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7151                           enum rte_filter_op filter_op,
7152                           void *arg)
7153 {
7154         struct rte_eth_tunnel_filter_conf *filter;
7155         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7156         int ret = I40E_SUCCESS;
7157
7158         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7159
7160         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7161                 return I40E_ERR_PARAM;
7162
7163         switch (filter_op) {
7164         case RTE_ETH_FILTER_NOP:
7165                 if (!(pf->flags & I40E_FLAG_VXLAN))
7166                         ret = I40E_NOT_SUPPORTED;
7167                 break;
7168         case RTE_ETH_FILTER_ADD:
7169                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7170                 break;
7171         case RTE_ETH_FILTER_DELETE:
7172                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7173                 break;
7174         default:
7175                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7176                 ret = I40E_ERR_PARAM;
7177                 break;
7178         }
7179
7180         return ret;
7181 }
7182
7183 static int
7184 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7185 {
7186         int ret = 0;
7187         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7188
7189         /* RSS setup */
7190         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7191                 ret = i40e_pf_config_rss(pf);
7192         else
7193                 i40e_pf_disable_rss(pf);
7194
7195         return ret;
7196 }
7197
7198 /* Get the symmetric hash enable configurations per port */
7199 static void
7200 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7201 {
7202         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7203
7204         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7205 }
7206
7207 /* Set the symmetric hash enable configurations per port */
7208 static void
7209 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7210 {
7211         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7212
7213         if (enable > 0) {
7214                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7215                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7216                                                         "been enabled");
7217                         return;
7218                 }
7219                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7220         } else {
7221                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7222                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7223                                                         "been disabled");
7224                         return;
7225                 }
7226                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7227         }
7228         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7229         I40E_WRITE_FLUSH(hw);
7230 }
7231
7232 /*
7233  * Get global configurations of hash function type and symmetric hash enable
7234  * per flow type (pctype). Note that global configuration means it affects all
7235  * the ports on the same NIC.
7236  */
7237 static int
7238 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7239                                    struct rte_eth_hash_global_conf *g_cfg)
7240 {
7241         uint32_t reg, mask = I40E_FLOW_TYPES;
7242         uint16_t i;
7243         enum i40e_filter_pctype pctype;
7244
7245         memset(g_cfg, 0, sizeof(*g_cfg));
7246         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7247         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7248                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7249         else
7250                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7251         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7252                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7253
7254         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7255                 if (!(mask & (1UL << i)))
7256                         continue;
7257                 mask &= ~(1UL << i);
7258                 /* Bit set indicats the coresponding flow type is supported */
7259                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7260                 /* if flowtype is invalid, continue */
7261                 if (!I40E_VALID_FLOW(i))
7262                         continue;
7263                 pctype = i40e_flowtype_to_pctype(i);
7264                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7265                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7266                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7267         }
7268
7269         return 0;
7270 }
7271
7272 static int
7273 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7274 {
7275         uint32_t i;
7276         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7277
7278         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7279                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7280                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7281                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7282                                                 g_cfg->hash_func);
7283                 return -EINVAL;
7284         }
7285
7286         /*
7287          * As i40e supports less than 32 flow types, only first 32 bits need to
7288          * be checked.
7289          */
7290         mask0 = g_cfg->valid_bit_mask[0];
7291         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7292                 if (i == 0) {
7293                         /* Check if any unsupported flow type configured */
7294                         if ((mask0 | i40e_mask) ^ i40e_mask)
7295                                 goto mask_err;
7296                 } else {
7297                         if (g_cfg->valid_bit_mask[i])
7298                                 goto mask_err;
7299                 }
7300         }
7301
7302         return 0;
7303
7304 mask_err:
7305         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7306
7307         return -EINVAL;
7308 }
7309
7310 /*
7311  * Set global configurations of hash function type and symmetric hash enable
7312  * per flow type (pctype). Note any modifying global configuration will affect
7313  * all the ports on the same NIC.
7314  */
7315 static int
7316 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7317                                    struct rte_eth_hash_global_conf *g_cfg)
7318 {
7319         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7320         int ret;
7321         uint16_t i;
7322         uint32_t reg;
7323         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7324         enum i40e_filter_pctype pctype;
7325
7326         if (pf->support_multi_driver) {
7327                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
7328                 return -ENOTSUP;
7329         }
7330
7331         /* Check the input parameters */
7332         ret = i40e_hash_global_config_check(g_cfg);
7333         if (ret < 0)
7334                 return ret;
7335
7336         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7337                 if (!(mask0 & (1UL << i)))
7338                         continue;
7339                 mask0 &= ~(1UL << i);
7340                 /* if flowtype is invalid, continue */
7341                 if (!I40E_VALID_FLOW(i))
7342                         continue;
7343                 pctype = i40e_flowtype_to_pctype(i);
7344                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7345                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7346                 if (hw->mac.type == I40E_MAC_X722) {
7347                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7348                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7349                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7350                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7351                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7352                                   reg);
7353                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7354                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7355                                   reg);
7356                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7357                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7358                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7359                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7360                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7361                                   reg);
7362                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7363                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7364                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7365                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7366                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7367                                   reg);
7368                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7369                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7370                                   reg);
7371                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7372                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7373                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7374                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7375                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7376                                   reg);
7377                         } else {
7378                                 i40e_write_global_rx_ctl(hw,
7379                                                          I40E_GLQF_HSYM(pctype),
7380                                                          reg);
7381                         }
7382                 } else {
7383                         i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7384                                                  reg);
7385                 }
7386                 i40e_global_cfg_warning(I40E_WARNING_HSYM);
7387         }
7388
7389         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7390         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7391                 /* Toeplitz */
7392                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7393                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7394                                                                 "Toeplitz");
7395                         goto out;
7396                 }
7397                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7398         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7399                 /* Simple XOR */
7400                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7401                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7402                                                         "Simple XOR");
7403                         goto out;
7404                 }
7405                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7406         } else
7407                 /* Use the default, and keep it as it is */
7408                 goto out;
7409
7410         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
7411         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
7412
7413 out:
7414         I40E_WRITE_FLUSH(hw);
7415
7416         return 0;
7417 }
7418
7419 /**
7420  * Valid input sets for hash and flow director filters per PCTYPE
7421  */
7422 static uint64_t
7423 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7424                 enum rte_filter_type filter)
7425 {
7426         uint64_t valid;
7427
7428         static const uint64_t valid_hash_inset_table[] = {
7429                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7430                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7431                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7432                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7433                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7434                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7435                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7436                         I40E_INSET_FLEX_PAYLOAD,
7437                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7438                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7439                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7440                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7441                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7442                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7443                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7444                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7445                         I40E_INSET_FLEX_PAYLOAD,
7446 #ifdef X722_SUPPORT
7447                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7448                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7449                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7450                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7451                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7452                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7453                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7454                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7455                         I40E_INSET_FLEX_PAYLOAD,
7456                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7457                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7458                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7459                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7460                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7461                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7462                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7463                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7464                         I40E_INSET_FLEX_PAYLOAD,
7465 #endif
7466                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7467                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7468                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7469                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7470                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7471                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7472                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7473                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7474                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7475 #ifdef X722_SUPPORT
7476                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7477                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7478                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7479                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7480                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7481                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7482                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7483                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7484                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7485 #endif
7486                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7487                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7488                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7489                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7490                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7491                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7492                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7493                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7494                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7495                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7496                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7497                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7498                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7499                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7500                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7501                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7502                         I40E_INSET_FLEX_PAYLOAD,
7503                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7504                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7505                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7506                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7507                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7508                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7509                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7510                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7511                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7512                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7513                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7514                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7515                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7516                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7517                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7518                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7519 #ifdef X722_SUPPORT
7520                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7521                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7522                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7523                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7524                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7525                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7526                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7527                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7528                         I40E_INSET_FLEX_PAYLOAD,
7529                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7530                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7531                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7532                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7533                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7534                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7535                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7536                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7537                         I40E_INSET_FLEX_PAYLOAD,
7538 #endif
7539                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7540                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7541                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7542                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7543                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7544                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7545                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7546                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7547                         I40E_INSET_FLEX_PAYLOAD,
7548 #ifdef X722_SUPPORT
7549                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7550                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7551                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7552                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7553                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7554                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7555                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7556                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7557                         I40E_INSET_FLEX_PAYLOAD,
7558 #endif
7559                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7560                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7561                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7562                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7563                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7564                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7565                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7566                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7567                         I40E_INSET_FLEX_PAYLOAD,
7568                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7569                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7570                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7571                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7572                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7573                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7574                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7575                         I40E_INSET_FLEX_PAYLOAD,
7576                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7577                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7578                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7579                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7580                         I40E_INSET_FLEX_PAYLOAD,
7581         };
7582
7583         /**
7584          * Flow director supports only fields defined in
7585          * union rte_eth_fdir_flow.
7586          */
7587         static const uint64_t valid_fdir_inset_table[] = {
7588                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7589                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7590                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7591                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7592                 I40E_INSET_IPV4_TTL,
7593                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7594                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7595                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7596                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7597                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7598 #ifdef X722_SUPPORT
7599                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7600                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7601                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7602                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7603                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7604                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7605                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7606                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7607                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7608                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7609 #endif
7610                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7611                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7612                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7613                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7614                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7615 #ifdef X722_SUPPORT
7616                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7617                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7618                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7619                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7620                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7621 #endif
7622                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7623                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7624                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7625                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7626                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7627                 I40E_INSET_SCTP_VT,
7628                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7629                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7630                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7631                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7632                 I40E_INSET_IPV4_TTL,
7633                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7634                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7635                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7636                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7637                 I40E_INSET_IPV6_HOP_LIMIT,
7638                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7639                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7640                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7641                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7642                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7643 #ifdef X722_SUPPORT
7644                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7645                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7646                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7647                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7648                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7649                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7650                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7651                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7652                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7653                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7654 #endif
7655                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7656                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7657                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7658                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7659                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7660 #ifdef X722_SUPPORT
7661                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7662                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7663                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7664                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7665                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7666 #endif
7667                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7668                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7669                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7670                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7671                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7672                 I40E_INSET_SCTP_VT,
7673                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7674                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7675                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7676                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7677                 I40E_INSET_IPV6_HOP_LIMIT,
7678                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7679                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7680                 I40E_INSET_LAST_ETHER_TYPE,
7681         };
7682
7683         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7684                 return 0;
7685         if (filter == RTE_ETH_FILTER_HASH)
7686                 valid = valid_hash_inset_table[pctype];
7687         else
7688                 valid = valid_fdir_inset_table[pctype];
7689
7690         return valid;
7691 }
7692
7693 /**
7694  * Validate if the input set is allowed for a specific PCTYPE
7695  */
7696 static int
7697 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7698                 enum rte_filter_type filter, uint64_t inset)
7699 {
7700         uint64_t valid;
7701
7702         valid = i40e_get_valid_input_set(pctype, filter);
7703         if (inset & (~valid))
7704                 return -EINVAL;
7705
7706         return 0;
7707 }
7708
7709 /* default input set fields combination per pctype */
7710 static uint64_t
7711 i40e_get_default_input_set(uint16_t pctype)
7712 {
7713         static const uint64_t default_inset_table[] = {
7714                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7715                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7716                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7717                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7718                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7719 #ifdef X722_SUPPORT
7720                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7721                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7722                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7723                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7724                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7725                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7726 #endif
7727                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7728                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7729                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7730 #ifdef X722_SUPPORT
7731                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7732                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7733                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7734 #endif
7735                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7736                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7737                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7738                         I40E_INSET_SCTP_VT,
7739                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7740                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7741                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7742                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7743                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7744                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7745                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7746 #ifdef X722_SUPPORT
7747                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7748                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7749                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7750                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7751                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7752                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7753 #endif
7754                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7755                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7756                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7757 #ifdef X722_SUPPORT
7758                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7759                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7760                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7761 #endif
7762                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7763                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7764                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7765                         I40E_INSET_SCTP_VT,
7766                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7767                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7768                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7769                         I40E_INSET_LAST_ETHER_TYPE,
7770         };
7771
7772         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7773                 return 0;
7774
7775         return default_inset_table[pctype];
7776 }
7777
7778 /**
7779  * Parse the input set from index to logical bit masks
7780  */
7781 static int
7782 i40e_parse_input_set(uint64_t *inset,
7783                      enum i40e_filter_pctype pctype,
7784                      enum rte_eth_input_set_field *field,
7785                      uint16_t size)
7786 {
7787         uint16_t i, j;
7788         int ret = -EINVAL;
7789
7790         static const struct {
7791                 enum rte_eth_input_set_field field;
7792                 uint64_t inset;
7793         } inset_convert_table[] = {
7794                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7795                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7796                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7797                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7798                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7799                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7800                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7801                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7802                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7803                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7804                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7805                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7806                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7807                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7808                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7809                         I40E_INSET_IPV6_NEXT_HDR},
7810                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7811                         I40E_INSET_IPV6_HOP_LIMIT},
7812                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7813                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7814                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7815                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7816                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7817                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7818                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7819                         I40E_INSET_SCTP_VT},
7820                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7821                         I40E_INSET_TUNNEL_DMAC},
7822                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7823                         I40E_INSET_VLAN_TUNNEL},
7824                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7825                         I40E_INSET_TUNNEL_ID},
7826                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7827                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7828                         I40E_INSET_FLEX_PAYLOAD_W1},
7829                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7830                         I40E_INSET_FLEX_PAYLOAD_W2},
7831                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7832                         I40E_INSET_FLEX_PAYLOAD_W3},
7833                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7834                         I40E_INSET_FLEX_PAYLOAD_W4},
7835                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7836                         I40E_INSET_FLEX_PAYLOAD_W5},
7837                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7838                         I40E_INSET_FLEX_PAYLOAD_W6},
7839                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7840                         I40E_INSET_FLEX_PAYLOAD_W7},
7841                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7842                         I40E_INSET_FLEX_PAYLOAD_W8},
7843         };
7844
7845         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7846                 return ret;
7847
7848         /* Only one item allowed for default or all */
7849         if (size == 1) {
7850                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7851                         *inset = i40e_get_default_input_set(pctype);
7852                         return 0;
7853                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7854                         *inset = I40E_INSET_NONE;
7855                         return 0;
7856                 }
7857         }
7858
7859         for (i = 0, *inset = 0; i < size; i++) {
7860                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7861                         if (field[i] == inset_convert_table[j].field) {
7862                                 *inset |= inset_convert_table[j].inset;
7863                                 break;
7864                         }
7865                 }
7866
7867                 /* It contains unsupported input set, return immediately */
7868                 if (j == RTE_DIM(inset_convert_table))
7869                         return ret;
7870         }
7871
7872         return 0;
7873 }
7874
7875 /**
7876  * Translate the input set from bit masks to register aware bit masks
7877  * and vice versa
7878  */
7879 static uint64_t
7880 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7881 {
7882         uint64_t val = 0;
7883         uint16_t i;
7884
7885         struct inset_map {
7886                 uint64_t inset;
7887                 uint64_t inset_reg;
7888         };
7889
7890         static const struct inset_map inset_map_common[] = {
7891                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7892                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7893                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7894                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7895                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7896                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7897                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7898                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7899                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7900                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7901                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7902                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7903                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7904                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7905                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7906                 {I40E_INSET_TUNNEL_DMAC,
7907                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7908                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7909                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7910                 {I40E_INSET_TUNNEL_SRC_PORT,
7911                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7912                 {I40E_INSET_TUNNEL_DST_PORT,
7913                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7914                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7915                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7916                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7917                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7918                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7919                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7920                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7921                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7922                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7923         };
7924
7925     /* some different registers map in x722*/
7926         static const struct inset_map inset_map_diff_x722[] = {
7927                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7928                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7929                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7930                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7931         };
7932
7933         static const struct inset_map inset_map_diff_not_x722[] = {
7934                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7935                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7936                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7937                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7938         };
7939
7940         if (input == 0)
7941                 return val;
7942
7943         /* Translate input set to register aware inset */
7944         if (type == I40E_MAC_X722) {
7945                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7946                         if (input & inset_map_diff_x722[i].inset)
7947                                 val |= inset_map_diff_x722[i].inset_reg;
7948                 }
7949         } else {
7950                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7951                         if (input & inset_map_diff_not_x722[i].inset)
7952                                 val |= inset_map_diff_not_x722[i].inset_reg;
7953                 }
7954         }
7955
7956         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7957                 if (input & inset_map_common[i].inset)
7958                         val |= inset_map_common[i].inset_reg;
7959         }
7960
7961         return val;
7962 }
7963
7964 static int
7965 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7966 {
7967         uint8_t i, idx = 0;
7968         uint64_t inset_need_mask = inset;
7969
7970         static const struct {
7971                 uint64_t inset;
7972                 uint32_t mask;
7973         } inset_mask_map[] = {
7974                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7975                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7976                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7977                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7978                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7979                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7980                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7981                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7982         };
7983
7984         if (!inset || !mask || !nb_elem)
7985                 return 0;
7986
7987         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7988                 /* Clear the inset bit, if no MASK is required,
7989                  * for example proto + ttl
7990                  */
7991                 if ((inset & inset_mask_map[i].inset) ==
7992                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7993                         inset_need_mask &= ~inset_mask_map[i].inset;
7994                 if (!inset_need_mask)
7995                         return 0;
7996         }
7997         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7998                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7999                     inset_mask_map[i].inset) {
8000                         if (idx >= nb_elem) {
8001                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8002                                 return -EINVAL;
8003                         }
8004                         mask[idx] = inset_mask_map[i].mask;
8005                         idx++;
8006                 }
8007         }
8008
8009         return idx;
8010 }
8011
8012 static void
8013 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8014 {
8015         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8016
8017         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
8018         if (reg != val)
8019                 i40e_write_rx_ctl(hw, addr, val);
8020         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
8021                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8022 }
8023
8024 static void
8025 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8026 {
8027         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8028
8029         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8030         if (reg != val)
8031                 i40e_write_global_rx_ctl(hw, addr, val);
8032         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8033                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8034 }
8035
8036 static void
8037 i40e_filter_input_set_init(struct i40e_pf *pf)
8038 {
8039         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8040         enum i40e_filter_pctype pctype;
8041         uint64_t input_set, inset_reg;
8042         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8043         int num, i;
8044
8045         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8046              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8047                 if (hw->mac.type == I40E_MAC_X722) {
8048                         if (!I40E_VALID_PCTYPE_X722(pctype))
8049                                 continue;
8050                 } else {
8051                         if (!I40E_VALID_PCTYPE(pctype))
8052                                 continue;
8053                 }
8054
8055                 input_set = i40e_get_default_input_set(pctype);
8056
8057                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8058                                                    I40E_INSET_MASK_NUM_REG);
8059                 if (num < 0)
8060                         return;
8061
8062                 if (pf->support_multi_driver && num > 0) {
8063                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
8064                         return;
8065                 }
8066
8067                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8068                                         input_set);
8069
8070                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8071                                       (uint32_t)(inset_reg & UINT32_MAX));
8072                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8073                                      (uint32_t)((inset_reg >>
8074                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8075                 if (!pf->support_multi_driver) {
8076                         i40e_check_write_global_reg(hw,
8077                                             I40E_GLQF_HASH_INSET(0, pctype),
8078                                             (uint32_t)(inset_reg & UINT32_MAX));
8079                         i40e_check_write_global_reg(hw,
8080                                             I40E_GLQF_HASH_INSET(1, pctype),
8081                                             (uint32_t)((inset_reg >>
8082                                             I40E_32_BIT_WIDTH) & UINT32_MAX));
8083
8084                         for (i = 0; i < num; i++) {
8085                                 i40e_check_write_global_reg(hw,
8086                                                     I40E_GLQF_FD_MSK(i, pctype),
8087                                                     mask_reg[i]);
8088                                 i40e_check_write_global_reg(hw,
8089                                                   I40E_GLQF_HASH_MSK(i, pctype),
8090                                                   mask_reg[i]);
8091                         }
8092                         /*clear unused mask registers of the pctype */
8093                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8094                                 i40e_check_write_global_reg(hw,
8095                                                     I40E_GLQF_FD_MSK(i, pctype),
8096                                                     0);
8097                                 i40e_check_write_global_reg(hw,
8098                                                   I40E_GLQF_HASH_MSK(i, pctype),
8099                                                     0);
8100                         }
8101                 } else {
8102                         PMD_DRV_LOG(ERR,
8103                                     "Input set setting is not supported.");
8104                 }
8105                 I40E_WRITE_FLUSH(hw);
8106
8107                 /* store the default input set */
8108                 if (!pf->support_multi_driver)
8109                         pf->hash_input_set[pctype] = input_set;
8110                 pf->fdir.input_set[pctype] = input_set;
8111         }
8112
8113         if (!pf->support_multi_driver) {
8114                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
8115                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
8116                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
8117         }
8118 }
8119
8120 int
8121 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8122                          struct rte_eth_input_set_conf *conf)
8123 {
8124         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8125         enum i40e_filter_pctype pctype;
8126         uint64_t input_set, inset_reg = 0;
8127         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8128         int ret, i, num;
8129
8130         if (pf->support_multi_driver) {
8131                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
8132                 return -ENOTSUP;
8133         }
8134
8135         if (!conf) {
8136                 PMD_DRV_LOG(ERR, "Invalid pointer");
8137                 return -EFAULT;
8138         }
8139         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8140             conf->op != RTE_ETH_INPUT_SET_ADD) {
8141                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8142                 return -EINVAL;
8143         }
8144
8145         if (!I40E_VALID_FLOW(conf->flow_type)) {
8146                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8147                 return -EINVAL;
8148         }
8149
8150         if (hw->mac.type == I40E_MAC_X722) {
8151                 /* get translated pctype value in fd pctype register */
8152                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8153                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8154                         conf->flow_type)));
8155         } else
8156                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8157
8158         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8159                                    conf->inset_size);
8160         if (ret) {
8161                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8162                 return -EINVAL;
8163         }
8164         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8165                                     input_set) != 0) {
8166                 PMD_DRV_LOG(ERR, "Invalid input set");
8167                 return -EINVAL;
8168         }
8169         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8170                 /* get inset value in register */
8171                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8172                 inset_reg <<= I40E_32_BIT_WIDTH;
8173                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8174                 input_set |= pf->hash_input_set[pctype];
8175         }
8176         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8177                                            I40E_INSET_MASK_NUM_REG);
8178         if (num < 0)
8179                 return -EINVAL;
8180
8181         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8182
8183         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8184                                     (uint32_t)(inset_reg & UINT32_MAX));
8185         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8186                                     (uint32_t)((inset_reg >>
8187                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
8188         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
8189
8190         for (i = 0; i < num; i++)
8191                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8192                                             mask_reg[i]);
8193         /*clear unused mask registers of the pctype */
8194         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8195                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8196                                             0);
8197         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
8198         I40E_WRITE_FLUSH(hw);
8199
8200         pf->hash_input_set[pctype] = input_set;
8201         return 0;
8202 }
8203
8204 int
8205 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8206                          struct rte_eth_input_set_conf *conf)
8207 {
8208         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8209         enum i40e_filter_pctype pctype;
8210         uint64_t input_set, inset_reg = 0;
8211         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8212         int ret, i, num;
8213
8214         if (!hw || !conf) {
8215                 PMD_DRV_LOG(ERR, "Invalid pointer");
8216                 return -EFAULT;
8217         }
8218         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8219             conf->op != RTE_ETH_INPUT_SET_ADD) {
8220                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8221                 return -EINVAL;
8222         }
8223
8224         if (!I40E_VALID_FLOW(conf->flow_type)) {
8225                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8226                 return -EINVAL;
8227         }
8228
8229         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8230
8231         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8232                                    conf->inset_size);
8233         if (ret) {
8234                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8235                 return -EINVAL;
8236         }
8237         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8238                                     input_set) != 0) {
8239                 PMD_DRV_LOG(ERR, "Invalid input set");
8240                 return -EINVAL;
8241         }
8242
8243         /* get inset value in register */
8244         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8245         inset_reg <<= I40E_32_BIT_WIDTH;
8246         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8247
8248         /* Can not change the inset reg for flex payload for fdir,
8249          * it is done by writing I40E_PRTQF_FD_FLXINSET
8250          * in i40e_set_flex_mask_on_pctype.
8251          */
8252         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8253                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8254         else
8255                 input_set |= pf->fdir.input_set[pctype];
8256         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8257                                            I40E_INSET_MASK_NUM_REG);
8258         if (num < 0)
8259                 return -EINVAL;
8260
8261         if (pf->support_multi_driver && num > 0) {
8262                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
8263                 return -ENOTSUP;
8264         }
8265
8266         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8267
8268         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8269                               (uint32_t)(inset_reg & UINT32_MAX));
8270         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8271                              (uint32_t)((inset_reg >>
8272                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8273
8274         if (!pf->support_multi_driver) {
8275                 for (i = 0; i < num; i++)
8276                         i40e_check_write_global_reg(hw,
8277                                                     I40E_GLQF_FD_MSK(i, pctype),
8278                                                     mask_reg[i]);
8279                 /*clear unused mask registers of the pctype */
8280                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8281                         i40e_check_write_global_reg(hw,
8282                                                     I40E_GLQF_FD_MSK(i, pctype),
8283                                                     0);
8284                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
8285         } else {
8286                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
8287         }
8288         I40E_WRITE_FLUSH(hw);
8289
8290         pf->fdir.input_set[pctype] = input_set;
8291         return 0;
8292 }
8293
8294 static int
8295 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8296 {
8297         int ret = 0;
8298
8299         if (!hw || !info) {
8300                 PMD_DRV_LOG(ERR, "Invalid pointer");
8301                 return -EFAULT;
8302         }
8303
8304         switch (info->info_type) {
8305         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8306                 i40e_get_symmetric_hash_enable_per_port(hw,
8307                                         &(info->info.enable));
8308                 break;
8309         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8310                 ret = i40e_get_hash_filter_global_config(hw,
8311                                 &(info->info.global_conf));
8312                 break;
8313         default:
8314                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8315                                                         info->info_type);
8316                 ret = -EINVAL;
8317                 break;
8318         }
8319
8320         return ret;
8321 }
8322
8323 static int
8324 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8325 {
8326         int ret = 0;
8327
8328         if (!hw || !info) {
8329                 PMD_DRV_LOG(ERR, "Invalid pointer");
8330                 return -EFAULT;
8331         }
8332
8333         switch (info->info_type) {
8334         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8335                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8336                 break;
8337         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8338                 ret = i40e_set_hash_filter_global_config(hw,
8339                                 &(info->info.global_conf));
8340                 break;
8341         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8342                 ret = i40e_hash_filter_inset_select(hw,
8343                                                &(info->info.input_set_conf));
8344                 break;
8345
8346         default:
8347                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8348                                                         info->info_type);
8349                 ret = -EINVAL;
8350                 break;
8351         }
8352
8353         return ret;
8354 }
8355
8356 /* Operations for hash function */
8357 static int
8358 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8359                       enum rte_filter_op filter_op,
8360                       void *arg)
8361 {
8362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8363         int ret = 0;
8364
8365         switch (filter_op) {
8366         case RTE_ETH_FILTER_NOP:
8367                 break;
8368         case RTE_ETH_FILTER_GET:
8369                 ret = i40e_hash_filter_get(hw,
8370                         (struct rte_eth_hash_filter_info *)arg);
8371                 break;
8372         case RTE_ETH_FILTER_SET:
8373                 ret = i40e_hash_filter_set(hw,
8374                         (struct rte_eth_hash_filter_info *)arg);
8375                 break;
8376         default:
8377                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8378                                                                 filter_op);
8379                 ret = -ENOTSUP;
8380                 break;
8381         }
8382
8383         return ret;
8384 }
8385
8386 /*
8387  * Configure ethertype filter, which can director packet by filtering
8388  * with mac address and ether_type or only ether_type
8389  */
8390 static int
8391 i40e_ethertype_filter_set(struct i40e_pf *pf,
8392                         struct rte_eth_ethertype_filter *filter,
8393                         bool add)
8394 {
8395         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8396         struct i40e_control_filter_stats stats;
8397         uint16_t flags = 0;
8398         int ret;
8399
8400         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8401                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8402                 return -EINVAL;
8403         }
8404         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8405                 filter->ether_type == ETHER_TYPE_IPv6) {
8406                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8407                         " control packet filter.", filter->ether_type);
8408                 return -EINVAL;
8409         }
8410         if (filter->ether_type == ETHER_TYPE_VLAN)
8411                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8412                         " not supported.");
8413
8414         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8415                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8416         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8417                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8418         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8419
8420         memset(&stats, 0, sizeof(stats));
8421         ret = i40e_aq_add_rem_control_packet_filter(hw,
8422                         filter->mac_addr.addr_bytes,
8423                         filter->ether_type, flags,
8424                         pf->main_vsi->seid,
8425                         filter->queue, add, &stats, NULL);
8426
8427         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8428                          " mac_etype_used = %u, etype_used = %u,"
8429                          " mac_etype_free = %u, etype_free = %u\n",
8430                          ret, stats.mac_etype_used, stats.etype_used,
8431                          stats.mac_etype_free, stats.etype_free);
8432         if (ret < 0)
8433                 return -ENOSYS;
8434         return 0;
8435 }
8436
8437 /*
8438  * Handle operations for ethertype filter.
8439  */
8440 static int
8441 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8442                                 enum rte_filter_op filter_op,
8443                                 void *arg)
8444 {
8445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8446         int ret = 0;
8447
8448         if (filter_op == RTE_ETH_FILTER_NOP)
8449                 return ret;
8450
8451         if (arg == NULL) {
8452                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8453                             filter_op);
8454                 return -EINVAL;
8455         }
8456
8457         switch (filter_op) {
8458         case RTE_ETH_FILTER_ADD:
8459                 ret = i40e_ethertype_filter_set(pf,
8460                         (struct rte_eth_ethertype_filter *)arg,
8461                         TRUE);
8462                 break;
8463         case RTE_ETH_FILTER_DELETE:
8464                 ret = i40e_ethertype_filter_set(pf,
8465                         (struct rte_eth_ethertype_filter *)arg,
8466                         FALSE);
8467                 break;
8468         default:
8469                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8470                 ret = -ENOSYS;
8471                 break;
8472         }
8473         return ret;
8474 }
8475
8476 static int
8477 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8478                      enum rte_filter_type filter_type,
8479                      enum rte_filter_op filter_op,
8480                      void *arg)
8481 {
8482         int ret = 0;
8483
8484         if (dev == NULL)
8485                 return -EINVAL;
8486
8487         switch (filter_type) {
8488         case RTE_ETH_FILTER_NONE:
8489                 /* For global configuration */
8490                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8491                 break;
8492         case RTE_ETH_FILTER_HASH:
8493                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8494                 break;
8495         case RTE_ETH_FILTER_MACVLAN:
8496                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8497                 break;
8498         case RTE_ETH_FILTER_ETHERTYPE:
8499                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8500                 break;
8501         case RTE_ETH_FILTER_TUNNEL:
8502                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8503                 break;
8504         case RTE_ETH_FILTER_FDIR:
8505                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8506                 break;
8507         default:
8508                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8509                                                         filter_type);
8510                 ret = -EINVAL;
8511                 break;
8512         }
8513
8514         return ret;
8515 }
8516
8517 /*
8518  * Check and enable Extended Tag.
8519  * Enabling Extended Tag is important for 40G performance.
8520  */
8521 static void
8522 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8523 {
8524         uint32_t buf = 0;
8525         int ret;
8526
8527         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8528                                       PCI_DEV_CAP_REG);
8529         if (ret < 0) {
8530                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8531                             PCI_DEV_CAP_REG);
8532                 return;
8533         }
8534         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8535                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8536                 return;
8537         }
8538
8539         buf = 0;
8540         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8541                                       PCI_DEV_CTRL_REG);
8542         if (ret < 0) {
8543                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8544                             PCI_DEV_CTRL_REG);
8545                 return;
8546         }
8547         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8548                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8549                 return;
8550         }
8551         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8552         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8553                                        PCI_DEV_CTRL_REG);
8554         if (ret < 0) {
8555                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8556                             PCI_DEV_CTRL_REG);
8557                 return;
8558         }
8559 }
8560
8561 /*
8562  * As some registers wouldn't be reset unless a global hardware reset,
8563  * hardware initialization is needed to put those registers into an
8564  * expected initial state.
8565  */
8566 static void
8567 i40e_hw_init(struct rte_eth_dev *dev)
8568 {
8569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8570
8571         i40e_enable_extended_tag(dev);
8572
8573         /* clear the PF Queue Filter control register */
8574         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8575
8576         /* Disable symmetric hash per port */
8577         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8578 }
8579
8580 enum i40e_filter_pctype
8581 i40e_flowtype_to_pctype(uint16_t flow_type)
8582 {
8583         static const enum i40e_filter_pctype pctype_table[] = {
8584                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8585                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8586                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8587                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8588                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8589                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8590                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8591                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8592                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8593                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8594                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8595                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8596                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8597                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8598                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8599                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8600                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8601                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8602                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8603         };
8604
8605         return pctype_table[flow_type];
8606 }
8607
8608 uint16_t
8609 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8610 {
8611         static const uint16_t flowtype_table[] = {
8612                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8613                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8614                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8615 #ifdef X722_SUPPORT
8616                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8617                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8618                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8619                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8620 #endif
8621                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8622                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8623 #ifdef X722_SUPPORT
8624                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8625                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8626 #endif
8627                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8628                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8629                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8630                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8631                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8632                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8633                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8634 #ifdef X722_SUPPORT
8635                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8636                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8637                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8638                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8639 #endif
8640                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8641                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8642 #ifdef X722_SUPPORT
8643                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8644                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8645 #endif
8646                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8647                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8648                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8649                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8650                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8651         };
8652
8653         return flowtype_table[pctype];
8654 }
8655
8656 /*
8657  * On X710, performance number is far from the expectation on recent firmware
8658  * versions; on XL710, performance number is also far from the expectation on
8659  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8660  * mode is enabled and port MAC address is equal to the packet destination MAC
8661  * address. The fix for this issue may not be integrated in the following
8662  * firmware version. So the workaround in software driver is needed. It needs
8663  * to modify the initial values of 3 internal only registers for both X710 and
8664  * XL710. Note that the values for X710 or XL710 could be different, and the
8665  * workaround can be removed when it is fixed in firmware in the future.
8666  */
8667
8668 /* For both X710 and XL710 */
8669 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
8670 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
8671 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
8672
8673 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8674 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8675
8676 /* For X722 */
8677 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8678 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8679
8680 /* For X710 */
8681 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8682 /* For XL710 */
8683 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8684 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8685
8686 /*
8687  * GL_SWR_PM_UP_THR:
8688  * The value is not impacted from the link speed, its value is set according
8689  * to the total number of ports for a better pipe-monitor configuration.
8690  */
8691 static bool
8692 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
8693 {
8694 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
8695                 .device_id = (dev),   \
8696                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
8697
8698 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
8699                 .device_id = (dev),   \
8700                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
8701
8702         static const struct {
8703                 uint16_t device_id;
8704                 uint32_t val;
8705         } swr_pm_table[] = {
8706                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
8707                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
8708                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
8709                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
8710
8711                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
8712                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
8713                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
8714                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
8715                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
8716                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
8717                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
8718         };
8719         uint32_t i;
8720
8721         if (value == NULL) {
8722                 PMD_DRV_LOG(ERR, "value is NULL");
8723                 return false;
8724         }
8725
8726         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
8727                 if (hw->device_id == swr_pm_table[i].device_id) {
8728                         *value = swr_pm_table[i].val;
8729
8730                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
8731                                     "value - 0x%08x",
8732                                     hw->device_id, *value);
8733                         return true;
8734                 }
8735         }
8736
8737         return false;
8738 }
8739
8740 static int
8741 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8742 {
8743         enum i40e_status_code status;
8744         struct i40e_aq_get_phy_abilities_resp phy_ab;
8745         int ret = -ENOTSUP;
8746
8747         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8748                                               NULL);
8749
8750         if (status)
8751                 return ret;
8752
8753         return 0;
8754 }
8755
8756 static void
8757 i40e_configure_registers(struct i40e_hw *hw)
8758 {
8759         static struct {
8760                 uint32_t addr;
8761                 uint64_t val;
8762         } reg_table[] = {
8763                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8764                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8765                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8766         };
8767         uint64_t reg;
8768         uint32_t i;
8769         int ret;
8770
8771         for (i = 0; i < RTE_DIM(reg_table); i++) {
8772                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8773                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8774                                 reg_table[i].val =
8775                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8776                         else /* For X710/XL710/XXV710 */
8777                                 if (hw->aq.fw_maj_ver < 6)
8778                                         reg_table[i].val =
8779                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
8780                                 else
8781                                         reg_table[i].val =
8782                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
8783                 }
8784
8785                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8786                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8787                                 reg_table[i].val =
8788                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8789                         else /* For X710/XL710/XXV710 */
8790                                 reg_table[i].val =
8791                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8792                 }
8793
8794                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8795                         uint32_t cfg_val;
8796
8797                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
8798                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
8799                                             "GL_SWR_PM_UP_THR value fixup",
8800                                             hw->device_id);
8801                                 continue;
8802                         }
8803
8804                         reg_table[i].val = cfg_val;
8805                 }
8806
8807                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8808                                                         &reg, NULL);
8809                 if (ret < 0) {
8810                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8811                                                         reg_table[i].addr);
8812                         break;
8813                 }
8814                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8815                                                 reg_table[i].addr, reg);
8816                 if (reg == reg_table[i].val)
8817                         continue;
8818
8819                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8820                                                 reg_table[i].val, NULL);
8821                 if (ret < 0) {
8822                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8823                                 "address of 0x%"PRIx32, reg_table[i].val,
8824                                                         reg_table[i].addr);
8825                         break;
8826                 }
8827                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8828                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8829         }
8830 }
8831
8832 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8833 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8834 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8835 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8836 static int
8837 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8838 {
8839         uint32_t reg;
8840         int ret;
8841
8842         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8843                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8844                 return -EINVAL;
8845         }
8846
8847         /* Configure for double VLAN RX stripping */
8848         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8849         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8850                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8851                 ret = i40e_aq_debug_write_register(hw,
8852                                                    I40E_VSI_TSR(vsi->vsi_id),
8853                                                    reg, NULL);
8854                 if (ret < 0) {
8855                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8856                                     vsi->vsi_id);
8857                         return I40E_ERR_CONFIG;
8858                 }
8859         }
8860
8861         /* Configure for double VLAN TX insertion */
8862         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8863         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8864                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8865                 ret = i40e_aq_debug_write_register(hw,
8866                                                    I40E_VSI_L2TAGSTXVALID(
8867                                                    vsi->vsi_id), reg, NULL);
8868                 if (ret < 0) {
8869                         PMD_DRV_LOG(ERR, "Failed to update "
8870                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8871                         return I40E_ERR_CONFIG;
8872                 }
8873         }
8874
8875         return 0;
8876 }
8877
8878 /**
8879  * i40e_aq_add_mirror_rule
8880  * @hw: pointer to the hardware structure
8881  * @seid: VEB seid to add mirror rule to
8882  * @dst_id: destination vsi seid
8883  * @entries: Buffer which contains the entities to be mirrored
8884  * @count: number of entities contained in the buffer
8885  * @rule_id:the rule_id of the rule to be added
8886  *
8887  * Add a mirror rule for a given veb.
8888  *
8889  **/
8890 static enum i40e_status_code
8891 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8892                         uint16_t seid, uint16_t dst_id,
8893                         uint16_t rule_type, uint16_t *entries,
8894                         uint16_t count, uint16_t *rule_id)
8895 {
8896         struct i40e_aq_desc desc;
8897         struct i40e_aqc_add_delete_mirror_rule cmd;
8898         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8899                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8900                 &desc.params.raw;
8901         uint16_t buff_len;
8902         enum i40e_status_code status;
8903
8904         i40e_fill_default_direct_cmd_desc(&desc,
8905                                           i40e_aqc_opc_add_mirror_rule);
8906         memset(&cmd, 0, sizeof(cmd));
8907
8908         buff_len = sizeof(uint16_t) * count;
8909         desc.datalen = rte_cpu_to_le_16(buff_len);
8910         if (buff_len > 0)
8911                 desc.flags |= rte_cpu_to_le_16(
8912                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8913         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8914                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8915         cmd.num_entries = rte_cpu_to_le_16(count);
8916         cmd.seid = rte_cpu_to_le_16(seid);
8917         cmd.destination = rte_cpu_to_le_16(dst_id);
8918
8919         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8920         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8921         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8922                          "rule_id = %u"
8923                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8924                          hw->aq.asq_last_status, resp->rule_id,
8925                          resp->mirror_rules_used, resp->mirror_rules_free);
8926         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8927
8928         return status;
8929 }
8930
8931 /**
8932  * i40e_aq_del_mirror_rule
8933  * @hw: pointer to the hardware structure
8934  * @seid: VEB seid to add mirror rule to
8935  * @entries: Buffer which contains the entities to be mirrored
8936  * @count: number of entities contained in the buffer
8937  * @rule_id:the rule_id of the rule to be delete
8938  *
8939  * Delete a mirror rule for a given veb.
8940  *
8941  **/
8942 static enum i40e_status_code
8943 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8944                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8945                 uint16_t count, uint16_t rule_id)
8946 {
8947         struct i40e_aq_desc desc;
8948         struct i40e_aqc_add_delete_mirror_rule cmd;
8949         uint16_t buff_len = 0;
8950         enum i40e_status_code status;
8951         void *buff = NULL;
8952
8953         i40e_fill_default_direct_cmd_desc(&desc,
8954                                           i40e_aqc_opc_delete_mirror_rule);
8955         memset(&cmd, 0, sizeof(cmd));
8956         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8957                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8958                                                           I40E_AQ_FLAG_RD));
8959                 cmd.num_entries = count;
8960                 buff_len = sizeof(uint16_t) * count;
8961                 desc.datalen = rte_cpu_to_le_16(buff_len);
8962                 buff = (void *)entries;
8963         } else
8964                 /* rule id is filled in destination field for deleting mirror rule */
8965                 cmd.destination = rte_cpu_to_le_16(rule_id);
8966
8967         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8968                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8969         cmd.seid = rte_cpu_to_le_16(seid);
8970
8971         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8972         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8973
8974         return status;
8975 }
8976
8977 /**
8978  * i40e_mirror_rule_set
8979  * @dev: pointer to the hardware structure
8980  * @mirror_conf: mirror rule info
8981  * @sw_id: mirror rule's sw_id
8982  * @on: enable/disable
8983  *
8984  * set a mirror rule.
8985  *
8986  **/
8987 static int
8988 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8989                         struct rte_eth_mirror_conf *mirror_conf,
8990                         uint8_t sw_id, uint8_t on)
8991 {
8992         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8993         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8994         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8995         struct i40e_mirror_rule *parent = NULL;
8996         uint16_t seid, dst_seid, rule_id;
8997         uint16_t i, j = 0;
8998         int ret;
8999
9000         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9001
9002         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9003                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
9004                         " without veb or vfs.");
9005                 return -ENOSYS;
9006         }
9007         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9008                 PMD_DRV_LOG(ERR, "mirror table is full.");
9009                 return -ENOSPC;
9010         }
9011         if (mirror_conf->dst_pool > pf->vf_num) {
9012                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9013                                  mirror_conf->dst_pool);
9014                 return -EINVAL;
9015         }
9016
9017         seid = pf->main_vsi->veb->seid;
9018
9019         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9020                 if (sw_id <= it->index) {
9021                         mirr_rule = it;
9022                         break;
9023                 }
9024                 parent = it;
9025         }
9026         if (mirr_rule && sw_id == mirr_rule->index) {
9027                 if (on) {
9028                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9029                         return -EEXIST;
9030                 } else {
9031                         ret = i40e_aq_del_mirror_rule(hw, seid,
9032                                         mirr_rule->rule_type,
9033                                         mirr_rule->entries,
9034                                         mirr_rule->num_entries, mirr_rule->id);
9035                         if (ret < 0) {
9036                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9037                                                    " ret = %d, aq_err = %d.",
9038                                                    ret, hw->aq.asq_last_status);
9039                                 return -ENOSYS;
9040                         }
9041                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9042                         rte_free(mirr_rule);
9043                         pf->nb_mirror_rule--;
9044                         return 0;
9045                 }
9046         } else if (!on) {
9047                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9048                 return -ENOENT;
9049         }
9050
9051         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9052                                 sizeof(struct i40e_mirror_rule) , 0);
9053         if (!mirr_rule) {
9054                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9055                 return I40E_ERR_NO_MEMORY;
9056         }
9057         switch (mirror_conf->rule_type) {
9058         case ETH_MIRROR_VLAN:
9059                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9060                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9061                                 mirr_rule->entries[j] =
9062                                         mirror_conf->vlan.vlan_id[i];
9063                                 j++;
9064                         }
9065                 }
9066                 if (j == 0) {
9067                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9068                         rte_free(mirr_rule);
9069                         return -EINVAL;
9070                 }
9071                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9072                 break;
9073         case ETH_MIRROR_VIRTUAL_POOL_UP:
9074         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9075                 /* check if the specified pool bit is out of range */
9076                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9077                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9078                         rte_free(mirr_rule);
9079                         return -EINVAL;
9080                 }
9081                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9082                         if (mirror_conf->pool_mask & (1ULL << i)) {
9083                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9084                                 j++;
9085                         }
9086                 }
9087                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9088                         /* add pf vsi to entries */
9089                         mirr_rule->entries[j] = pf->main_vsi_seid;
9090                         j++;
9091                 }
9092                 if (j == 0) {
9093                         PMD_DRV_LOG(ERR, "pool is not specified.");
9094                         rte_free(mirr_rule);
9095                         return -EINVAL;
9096                 }
9097                 /* egress and ingress in aq commands means from switch but not port */
9098                 mirr_rule->rule_type =
9099                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9100                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9101                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9102                 break;
9103         case ETH_MIRROR_UPLINK_PORT:
9104                 /* egress and ingress in aq commands means from switch but not port*/
9105                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9106                 break;
9107         case ETH_MIRROR_DOWNLINK_PORT:
9108                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9109                 break;
9110         default:
9111                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9112                         mirror_conf->rule_type);
9113                 rte_free(mirr_rule);
9114                 return -EINVAL;
9115         }
9116
9117         /* If the dst_pool is equal to vf_num, consider it as PF */
9118         if (mirror_conf->dst_pool == pf->vf_num)
9119                 dst_seid = pf->main_vsi_seid;
9120         else
9121                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9122
9123         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9124                                       mirr_rule->rule_type, mirr_rule->entries,
9125                                       j, &rule_id);
9126         if (ret < 0) {
9127                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9128                                    " ret = %d, aq_err = %d.",
9129                                    ret, hw->aq.asq_last_status);
9130                 rte_free(mirr_rule);
9131                 return -ENOSYS;
9132         }
9133
9134         mirr_rule->index = sw_id;
9135         mirr_rule->num_entries = j;
9136         mirr_rule->id = rule_id;
9137         mirr_rule->dst_vsi_seid = dst_seid;
9138
9139         if (parent)
9140                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9141         else
9142                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9143
9144         pf->nb_mirror_rule++;
9145         return 0;
9146 }
9147
9148 /**
9149  * i40e_mirror_rule_reset
9150  * @dev: pointer to the device
9151  * @sw_id: mirror rule's sw_id
9152  *
9153  * reset a mirror rule.
9154  *
9155  **/
9156 static int
9157 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9158 {
9159         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9160         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9161         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9162         uint16_t seid;
9163         int ret;
9164
9165         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9166
9167         seid = pf->main_vsi->veb->seid;
9168
9169         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9170                 if (sw_id == it->index) {
9171                         mirr_rule = it;
9172                         break;
9173                 }
9174         }
9175         if (mirr_rule) {
9176                 ret = i40e_aq_del_mirror_rule(hw, seid,
9177                                 mirr_rule->rule_type,
9178                                 mirr_rule->entries,
9179                                 mirr_rule->num_entries, mirr_rule->id);
9180                 if (ret < 0) {
9181                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9182                                            " status = %d, aq_err = %d.",
9183                                            ret, hw->aq.asq_last_status);
9184                         return -ENOSYS;
9185                 }
9186                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9187                 rte_free(mirr_rule);
9188                 pf->nb_mirror_rule--;
9189         } else {
9190                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9191                 return -ENOENT;
9192         }
9193         return 0;
9194 }
9195
9196 static uint64_t
9197 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9198 {
9199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9200         uint64_t systim_cycles;
9201
9202         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9203         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9204                         << 32;
9205
9206         return systim_cycles;
9207 }
9208
9209 static uint64_t
9210 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9211 {
9212         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9213         uint64_t rx_tstamp;
9214
9215         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9216         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9217                         << 32;
9218
9219         return rx_tstamp;
9220 }
9221
9222 static uint64_t
9223 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9224 {
9225         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9226         uint64_t tx_tstamp;
9227
9228         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9229         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9230                         << 32;
9231
9232         return tx_tstamp;
9233 }
9234
9235 static void
9236 i40e_start_timecounters(struct rte_eth_dev *dev)
9237 {
9238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9239         struct i40e_adapter *adapter =
9240                         (struct i40e_adapter *)dev->data->dev_private;
9241         struct rte_eth_link link;
9242         uint32_t tsync_inc_l;
9243         uint32_t tsync_inc_h;
9244
9245         /* Get current link speed. */
9246         memset(&link, 0, sizeof(link));
9247         i40e_dev_link_update(dev, 1);
9248         rte_i40e_dev_atomic_read_link_status(dev, &link);
9249
9250         switch (link.link_speed) {
9251         case ETH_SPEED_NUM_40G:
9252                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9253                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9254                 break;
9255         case ETH_SPEED_NUM_10G:
9256                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9257                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9258                 break;
9259         case ETH_SPEED_NUM_1G:
9260                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9261                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9262                 break;
9263         default:
9264                 tsync_inc_l = 0x0;
9265                 tsync_inc_h = 0x0;
9266         }
9267
9268         /* Set the timesync increment value. */
9269         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9270         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9271
9272         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9273         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9274         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9275
9276         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9277         adapter->systime_tc.cc_shift = 0;
9278         adapter->systime_tc.nsec_mask = 0;
9279
9280         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9281         adapter->rx_tstamp_tc.cc_shift = 0;
9282         adapter->rx_tstamp_tc.nsec_mask = 0;
9283
9284         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9285         adapter->tx_tstamp_tc.cc_shift = 0;
9286         adapter->tx_tstamp_tc.nsec_mask = 0;
9287 }
9288
9289 static int
9290 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9291 {
9292         struct i40e_adapter *adapter =
9293                         (struct i40e_adapter *)dev->data->dev_private;
9294
9295         adapter->systime_tc.nsec += delta;
9296         adapter->rx_tstamp_tc.nsec += delta;
9297         adapter->tx_tstamp_tc.nsec += delta;
9298
9299         return 0;
9300 }
9301
9302 static int
9303 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9304 {
9305         uint64_t ns;
9306         struct i40e_adapter *adapter =
9307                         (struct i40e_adapter *)dev->data->dev_private;
9308
9309         ns = rte_timespec_to_ns(ts);
9310
9311         /* Set the timecounters to a new value. */
9312         adapter->systime_tc.nsec = ns;
9313         adapter->rx_tstamp_tc.nsec = ns;
9314         adapter->tx_tstamp_tc.nsec = ns;
9315
9316         return 0;
9317 }
9318
9319 static int
9320 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9321 {
9322         uint64_t ns, systime_cycles;
9323         struct i40e_adapter *adapter =
9324                         (struct i40e_adapter *)dev->data->dev_private;
9325
9326         systime_cycles = i40e_read_systime_cyclecounter(dev);
9327         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9328         *ts = rte_ns_to_timespec(ns);
9329
9330         return 0;
9331 }
9332
9333 static int
9334 i40e_timesync_enable(struct rte_eth_dev *dev)
9335 {
9336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9337         uint32_t tsync_ctl_l;
9338         uint32_t tsync_ctl_h;
9339
9340         /* Stop the timesync system time. */
9341         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9342         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9343         /* Reset the timesync system time value. */
9344         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9345         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9346
9347         i40e_start_timecounters(dev);
9348
9349         /* Clear timesync registers. */
9350         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9351         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9352         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9353         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9354         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9355         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9356
9357         /* Enable timestamping of PTP packets. */
9358         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9359         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9360
9361         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9362         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9363         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9364
9365         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9366         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9367
9368         return 0;
9369 }
9370
9371 static int
9372 i40e_timesync_disable(struct rte_eth_dev *dev)
9373 {
9374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9375         uint32_t tsync_ctl_l;
9376         uint32_t tsync_ctl_h;
9377
9378         /* Disable timestamping of transmitted PTP packets. */
9379         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9380         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9381
9382         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9383         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9384
9385         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9386         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9387
9388         /* Reset the timesync increment value. */
9389         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9390         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9391
9392         return 0;
9393 }
9394
9395 static int
9396 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9397                                 struct timespec *timestamp, uint32_t flags)
9398 {
9399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9400         struct i40e_adapter *adapter =
9401                 (struct i40e_adapter *)dev->data->dev_private;
9402
9403         uint32_t sync_status;
9404         uint32_t index = flags & 0x03;
9405         uint64_t rx_tstamp_cycles;
9406         uint64_t ns;
9407
9408         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9409         if ((sync_status & (1 << index)) == 0)
9410                 return -EINVAL;
9411
9412         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9413         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9414         *timestamp = rte_ns_to_timespec(ns);
9415
9416         return 0;
9417 }
9418
9419 static int
9420 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9421                                 struct timespec *timestamp)
9422 {
9423         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9424         struct i40e_adapter *adapter =
9425                 (struct i40e_adapter *)dev->data->dev_private;
9426
9427         uint32_t sync_status;
9428         uint64_t tx_tstamp_cycles;
9429         uint64_t ns;
9430
9431         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9432         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9433                 return -EINVAL;
9434
9435         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9436         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9437         *timestamp = rte_ns_to_timespec(ns);
9438
9439         return 0;
9440 }
9441
9442 /*
9443  * i40e_parse_dcb_configure - parse dcb configure from user
9444  * @dev: the device being configured
9445  * @dcb_cfg: pointer of the result of parse
9446  * @*tc_map: bit map of enabled traffic classes
9447  *
9448  * Returns 0 on success, negative value on failure
9449  */
9450 static int
9451 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9452                          struct i40e_dcbx_config *dcb_cfg,
9453                          uint8_t *tc_map)
9454 {
9455         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9456         uint8_t i, tc_bw, bw_lf;
9457
9458         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9459
9460         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9461         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9462                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9463                 return -EINVAL;
9464         }
9465
9466         /* assume each tc has the same bw */
9467         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9468         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9469                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9470         /* to ensure the sum of tcbw is equal to 100 */
9471         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9472         for (i = 0; i < bw_lf; i++)
9473                 dcb_cfg->etscfg.tcbwtable[i]++;
9474
9475         /* assume each tc has the same Transmission Selection Algorithm */
9476         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9477                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9478
9479         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9480                 dcb_cfg->etscfg.prioritytable[i] =
9481                                 dcb_rx_conf->dcb_tc[i];
9482
9483         /* FW needs one App to configure HW */
9484         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9485         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9486         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9487         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9488
9489         if (dcb_rx_conf->nb_tcs == 0)
9490                 *tc_map = 1; /* tc0 only */
9491         else
9492                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9493
9494         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9495                 dcb_cfg->pfc.willing = 0;
9496                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9497                 dcb_cfg->pfc.pfcenable = *tc_map;
9498         }
9499         return 0;
9500 }
9501
9502
9503 static enum i40e_status_code
9504 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9505                               struct i40e_aqc_vsi_properties_data *info,
9506                               uint8_t enabled_tcmap)
9507 {
9508         enum i40e_status_code ret;
9509         int i, total_tc = 0;
9510         uint16_t qpnum_per_tc, bsf, qp_idx;
9511         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9512         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9513         uint16_t used_queues;
9514
9515         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9516         if (ret != I40E_SUCCESS)
9517                 return ret;
9518
9519         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9520                 if (enabled_tcmap & (1 << i))
9521                         total_tc++;
9522         }
9523         if (total_tc == 0)
9524                 total_tc = 1;
9525         vsi->enabled_tc = enabled_tcmap;
9526
9527         /* different VSI has different queues assigned */
9528         if (vsi->type == I40E_VSI_MAIN)
9529                 used_queues = dev_data->nb_rx_queues -
9530                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9531         else if (vsi->type == I40E_VSI_VMDQ2)
9532                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9533         else {
9534                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9535                 return I40E_ERR_NO_AVAILABLE_VSI;
9536         }
9537
9538         qpnum_per_tc = used_queues / total_tc;
9539         /* Number of queues per enabled TC */
9540         if (qpnum_per_tc == 0) {
9541                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9542                 return I40E_ERR_INVALID_QP_ID;
9543         }
9544         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9545                                 I40E_MAX_Q_PER_TC);
9546         bsf = rte_bsf32(qpnum_per_tc);
9547
9548         /**
9549          * Configure TC and queue mapping parameters, for enabled TC,
9550          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9551          * default queue will serve it.
9552          */
9553         qp_idx = 0;
9554         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9555                 if (vsi->enabled_tc & (1 << i)) {
9556                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9557                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9558                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9559                         qp_idx += qpnum_per_tc;
9560                 } else
9561                         info->tc_mapping[i] = 0;
9562         }
9563
9564         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9565         if (vsi->type == I40E_VSI_SRIOV) {
9566                 info->mapping_flags |=
9567                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9568                 for (i = 0; i < vsi->nb_qps; i++)
9569                         info->queue_mapping[i] =
9570                                 rte_cpu_to_le_16(vsi->base_queue + i);
9571         } else {
9572                 info->mapping_flags |=
9573                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9574                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9575         }
9576         info->valid_sections |=
9577                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9578
9579         return I40E_SUCCESS;
9580 }
9581
9582 /*
9583  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9584  * @veb: VEB to be configured
9585  * @tc_map: enabled TC bitmap
9586  *
9587  * Returns 0 on success, negative value on failure
9588  */
9589 static enum i40e_status_code
9590 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9591 {
9592         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9593         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9594         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9595         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9596         enum i40e_status_code ret = I40E_SUCCESS;
9597         int i;
9598         uint32_t bw_max;
9599
9600         /* Check if enabled_tc is same as existing or new TCs */
9601         if (veb->enabled_tc == tc_map)
9602                 return ret;
9603
9604         /* configure tc bandwidth */
9605         memset(&veb_bw, 0, sizeof(veb_bw));
9606         veb_bw.tc_valid_bits = tc_map;
9607         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9608         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9609                 if (tc_map & BIT_ULL(i))
9610                         veb_bw.tc_bw_share_credits[i] = 1;
9611         }
9612         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9613                                                    &veb_bw, NULL);
9614         if (ret) {
9615                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9616                                   " per TC failed = %d",
9617                                   hw->aq.asq_last_status);
9618                 return ret;
9619         }
9620
9621         memset(&ets_query, 0, sizeof(ets_query));
9622         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9623                                                    &ets_query, NULL);
9624         if (ret != I40E_SUCCESS) {
9625                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9626                                  " configuration %u", hw->aq.asq_last_status);
9627                 return ret;
9628         }
9629         memset(&bw_query, 0, sizeof(bw_query));
9630         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9631                                                   &bw_query, NULL);
9632         if (ret != I40E_SUCCESS) {
9633                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9634                                  " configuration %u", hw->aq.asq_last_status);
9635                 return ret;
9636         }
9637
9638         /* store and print out BW info */
9639         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9640         veb->bw_info.bw_max = ets_query.tc_bw_max;
9641         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9642         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9643         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9644                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9645                      I40E_16_BIT_WIDTH);
9646         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9647                 veb->bw_info.bw_ets_share_credits[i] =
9648                                 bw_query.tc_bw_share_credits[i];
9649                 veb->bw_info.bw_ets_credits[i] =
9650                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9651                 /* 4 bits per TC, 4th bit is reserved */
9652                 veb->bw_info.bw_ets_max[i] =
9653                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9654                                   RTE_LEN2MASK(3, uint8_t));
9655                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9656                             veb->bw_info.bw_ets_share_credits[i]);
9657                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9658                             veb->bw_info.bw_ets_credits[i]);
9659                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9660                             veb->bw_info.bw_ets_max[i]);
9661         }
9662
9663         veb->enabled_tc = tc_map;
9664
9665         return ret;
9666 }
9667
9668
9669 /*
9670  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9671  * @vsi: VSI to be configured
9672  * @tc_map: enabled TC bitmap
9673  *
9674  * Returns 0 on success, negative value on failure
9675  */
9676 static enum i40e_status_code
9677 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9678 {
9679         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9680         struct i40e_vsi_context ctxt;
9681         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9682         enum i40e_status_code ret = I40E_SUCCESS;
9683         int i;
9684
9685         /* Check if enabled_tc is same as existing or new TCs */
9686         if (vsi->enabled_tc == tc_map)
9687                 return ret;
9688
9689         /* configure tc bandwidth */
9690         memset(&bw_data, 0, sizeof(bw_data));
9691         bw_data.tc_valid_bits = tc_map;
9692         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9693         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9694                 if (tc_map & BIT_ULL(i))
9695                         bw_data.tc_bw_credits[i] = 1;
9696         }
9697         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9698         if (ret) {
9699                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9700                         " per TC failed = %d",
9701                         hw->aq.asq_last_status);
9702                 goto out;
9703         }
9704         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9705                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9706
9707         /* Update Queue Pairs Mapping for currently enabled UPs */
9708         ctxt.seid = vsi->seid;
9709         ctxt.pf_num = hw->pf_id;
9710         ctxt.vf_num = 0;
9711         ctxt.uplink_seid = vsi->uplink_seid;
9712         ctxt.info = vsi->info;
9713         i40e_get_cap(hw);
9714         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9715         if (ret)
9716                 goto out;
9717
9718         /* Update the VSI after updating the VSI queue-mapping information */
9719         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9720         if (ret) {
9721                 PMD_INIT_LOG(ERR, "Failed to configure "
9722                             "TC queue mapping = %d",
9723                             hw->aq.asq_last_status);
9724                 goto out;
9725         }
9726         /* update the local VSI info with updated queue map */
9727         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9728                                         sizeof(vsi->info.tc_mapping));
9729         (void)rte_memcpy(&vsi->info.queue_mapping,
9730                         &ctxt.info.queue_mapping,
9731                 sizeof(vsi->info.queue_mapping));
9732         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9733         vsi->info.valid_sections = 0;
9734
9735         /* query and update current VSI BW information */
9736         ret = i40e_vsi_get_bw_config(vsi);
9737         if (ret) {
9738                 PMD_INIT_LOG(ERR,
9739                          "Failed updating vsi bw info, err %s aq_err %s",
9740                          i40e_stat_str(hw, ret),
9741                          i40e_aq_str(hw, hw->aq.asq_last_status));
9742                 goto out;
9743         }
9744
9745         vsi->enabled_tc = tc_map;
9746
9747 out:
9748         return ret;
9749 }
9750
9751 /*
9752  * i40e_dcb_hw_configure - program the dcb setting to hw
9753  * @pf: pf the configuration is taken on
9754  * @new_cfg: new configuration
9755  * @tc_map: enabled TC bitmap
9756  *
9757  * Returns 0 on success, negative value on failure
9758  */
9759 static enum i40e_status_code
9760 i40e_dcb_hw_configure(struct i40e_pf *pf,
9761                       struct i40e_dcbx_config *new_cfg,
9762                       uint8_t tc_map)
9763 {
9764         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9765         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9766         struct i40e_vsi *main_vsi = pf->main_vsi;
9767         struct i40e_vsi_list *vsi_list;
9768         enum i40e_status_code ret;
9769         int i;
9770         uint32_t val;
9771
9772         /* Use the FW API if FW > v4.4*/
9773         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9774               (hw->aq.fw_maj_ver >= 5))) {
9775                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9776                                   " to configure DCB");
9777                 return I40E_ERR_FIRMWARE_API_VERSION;
9778         }
9779
9780         /* Check if need reconfiguration */
9781         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9782                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9783                 return I40E_SUCCESS;
9784         }
9785
9786         /* Copy the new config to the current config */
9787         *old_cfg = *new_cfg;
9788         old_cfg->etsrec = old_cfg->etscfg;
9789         ret = i40e_set_dcb_config(hw);
9790         if (ret) {
9791                 PMD_INIT_LOG(ERR,
9792                          "Set DCB Config failed, err %s aq_err %s\n",
9793                          i40e_stat_str(hw, ret),
9794                          i40e_aq_str(hw, hw->aq.asq_last_status));
9795                 return ret;
9796         }
9797         /* set receive Arbiter to RR mode and ETS scheme by default */
9798         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9799                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9800                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9801                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9802                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9803                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9804                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9805                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9806                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9807                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9808                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9809                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9810                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9811         }
9812         /* get local mib to check whether it is configured correctly */
9813         /* IEEE mode */
9814         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9815         /* Get Local DCB Config */
9816         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9817                                      &hw->local_dcbx_config);
9818
9819         /* if Veb is created, need to update TC of it at first */
9820         if (main_vsi->veb) {
9821                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9822                 if (ret)
9823                         PMD_INIT_LOG(WARNING,
9824                                  "Failed configuring TC for VEB seid=%d\n",
9825                                  main_vsi->veb->seid);
9826         }
9827         /* Update each VSI */
9828         i40e_vsi_config_tc(main_vsi, tc_map);
9829         if (main_vsi->veb) {
9830                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9831                         /* Beside main VSI and VMDQ VSIs, only enable default
9832                          * TC for other VSIs
9833                          */
9834                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9835                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9836                                                          tc_map);
9837                         else
9838                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9839                                                          I40E_DEFAULT_TCMAP);
9840                         if (ret)
9841                                 PMD_INIT_LOG(WARNING,
9842                                          "Failed configuring TC for VSI seid=%d\n",
9843                                          vsi_list->vsi->seid);
9844                         /* continue */
9845                 }
9846         }
9847         return I40E_SUCCESS;
9848 }
9849
9850 /*
9851  * i40e_dcb_init_configure - initial dcb config
9852  * @dev: device being configured
9853  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9854  *
9855  * Returns 0 on success, negative value on failure
9856  */
9857 static int
9858 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9859 {
9860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9862         int ret = 0;
9863
9864         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9865                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9866                 return -ENOTSUP;
9867         }
9868
9869         /* DCB initialization:
9870          * Update DCB configuration from the Firmware and configure
9871          * LLDP MIB change event.
9872          */
9873         if (sw_dcb == TRUE) {
9874                 ret = i40e_init_dcb(hw);
9875                 /* If lldp agent is stopped, the return value from
9876                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9877                  * adminq status. Otherwise, it should return success.
9878                  */
9879                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9880                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9881                         memset(&hw->local_dcbx_config, 0,
9882                                 sizeof(struct i40e_dcbx_config));
9883                         /* set dcb default configuration */
9884                         hw->local_dcbx_config.etscfg.willing = 0;
9885                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9886                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9887                         hw->local_dcbx_config.etscfg.tsatable[0] =
9888                                                 I40E_IEEE_TSA_ETS;
9889                         hw->local_dcbx_config.etsrec =
9890                                 hw->local_dcbx_config.etscfg;
9891                         hw->local_dcbx_config.pfc.willing = 0;
9892                         hw->local_dcbx_config.pfc.pfccap =
9893                                                 I40E_MAX_TRAFFIC_CLASS;
9894                         /* FW needs one App to configure HW */
9895                         hw->local_dcbx_config.numapps = 1;
9896                         hw->local_dcbx_config.app[0].selector =
9897                                                 I40E_APP_SEL_ETHTYPE;
9898                         hw->local_dcbx_config.app[0].priority = 3;
9899                         hw->local_dcbx_config.app[0].protocolid =
9900                                                 I40E_APP_PROTOID_FCOE;
9901                         ret = i40e_set_dcb_config(hw);
9902                         if (ret) {
9903                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9904                                         " err = %d, aq_err = %d.", ret,
9905                                           hw->aq.asq_last_status);
9906                                 return -ENOSYS;
9907                         }
9908                 } else {
9909                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9910                                           " err = %d, aq_err = %d.", ret,
9911                                           hw->aq.asq_last_status);
9912                         return -ENOTSUP;
9913                 }
9914         } else {
9915                 ret = i40e_aq_start_lldp(hw, NULL);
9916                 if (ret != I40E_SUCCESS)
9917                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9918
9919                 ret = i40e_init_dcb(hw);
9920                 if (!ret) {
9921                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9922                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9923                                                   " DCBX offload.");
9924                                 return -ENOTSUP;
9925                         }
9926                 } else {
9927                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9928                                           " aq_err = %d.", ret,
9929                                           hw->aq.asq_last_status);
9930                         return -ENOTSUP;
9931                 }
9932         }
9933         return 0;
9934 }
9935
9936 /*
9937  * i40e_dcb_setup - setup dcb related config
9938  * @dev: device being configured
9939  *
9940  * Returns 0 on success, negative value on failure
9941  */
9942 static int
9943 i40e_dcb_setup(struct rte_eth_dev *dev)
9944 {
9945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9946         struct i40e_dcbx_config dcb_cfg;
9947         uint8_t tc_map = 0;
9948         int ret = 0;
9949
9950         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9951                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9952                 return -ENOTSUP;
9953         }
9954
9955         if (pf->vf_num != 0)
9956                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9957
9958         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9959         if (ret) {
9960                 PMD_INIT_LOG(ERR, "invalid dcb config");
9961                 return -EINVAL;
9962         }
9963         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9964         if (ret) {
9965                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9966                 return -ENOSYS;
9967         }
9968
9969         return 0;
9970 }
9971
9972 static int
9973 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9974                       struct rte_eth_dcb_info *dcb_info)
9975 {
9976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9978         struct i40e_vsi *vsi = pf->main_vsi;
9979         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9980         uint16_t bsf, tc_mapping;
9981         int i, j = 0;
9982
9983         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9984                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9985         else
9986                 dcb_info->nb_tcs = 1;
9987         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9988                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9989         for (i = 0; i < dcb_info->nb_tcs; i++)
9990                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9991
9992         /* get queue mapping if vmdq is disabled */
9993         if (!pf->nb_cfg_vmdq_vsi) {
9994                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9995                         if (!(vsi->enabled_tc & (1 << i)))
9996                                 continue;
9997                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9998                         dcb_info->tc_queue.tc_rxq[j][i].base =
9999                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10000                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10001                         dcb_info->tc_queue.tc_txq[j][i].base =
10002                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10003                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10004                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10005                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10006                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10007                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10008                 }
10009                 return 0;
10010         }
10011
10012         /* get queue mapping if vmdq is enabled */
10013         do {
10014                 vsi = pf->vmdq[j].vsi;
10015                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10016                         if (!(vsi->enabled_tc & (1 << i)))
10017                                 continue;
10018                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10019                         dcb_info->tc_queue.tc_rxq[j][i].base =
10020                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10021                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10022                         dcb_info->tc_queue.tc_txq[j][i].base =
10023                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10024                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10025                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10026                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10027                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10028                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10029                 }
10030                 j++;
10031         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10032         return 0;
10033 }
10034
10035 static int
10036 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10037 {
10038         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
10039         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10040         uint16_t msix_intr;
10041
10042         msix_intr = intr_handle->intr_vec[queue_id];
10043         if (msix_intr == I40E_MISC_VEC_ID)
10044                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10045                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
10046                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
10047                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
10048         else
10049                 I40E_WRITE_REG(hw,
10050                                I40E_PFINT_DYN_CTLN(msix_intr -
10051                                                    I40E_RX_VEC_START),
10052                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10053                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10054                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
10055
10056         I40E_WRITE_FLUSH(hw);
10057         rte_intr_enable(&dev->pci_dev->intr_handle);
10058
10059         return 0;
10060 }
10061
10062 static int
10063 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10064 {
10065         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
10066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10067         uint16_t msix_intr;
10068
10069         msix_intr = intr_handle->intr_vec[queue_id];
10070         if (msix_intr == I40E_MISC_VEC_ID)
10071                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10072                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
10073         else
10074                 I40E_WRITE_REG(hw,
10075                                I40E_PFINT_DYN_CTLN(msix_intr -
10076                                                    I40E_RX_VEC_START),
10077                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
10078         I40E_WRITE_FLUSH(hw);
10079
10080         return 0;
10081 }
10082
10083 static int i40e_get_regs(struct rte_eth_dev *dev,
10084                          struct rte_dev_reg_info *regs)
10085 {
10086         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10087         uint32_t *ptr_data = regs->data;
10088         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10089         const struct i40e_reg_info *reg_info;
10090
10091         if (ptr_data == NULL) {
10092                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10093                 regs->width = sizeof(uint32_t);
10094                 return 0;
10095         }
10096
10097         /* The first few registers have to be read using AQ operations */
10098         reg_idx = 0;
10099         while (i40e_regs_adminq[reg_idx].name) {
10100                 reg_info = &i40e_regs_adminq[reg_idx++];
10101                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10102                         for (arr_idx2 = 0;
10103                                         arr_idx2 <= reg_info->count2;
10104                                         arr_idx2++) {
10105                                 reg_offset = arr_idx * reg_info->stride1 +
10106                                         arr_idx2 * reg_info->stride2;
10107                                 reg_offset += reg_info->base_addr;
10108                                 ptr_data[reg_offset >> 2] =
10109                                         i40e_read_rx_ctl(hw, reg_offset);
10110                         }
10111         }
10112
10113         /* The remaining registers can be read using primitives */
10114         reg_idx = 0;
10115         while (i40e_regs_others[reg_idx].name) {
10116                 reg_info = &i40e_regs_others[reg_idx++];
10117                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10118                         for (arr_idx2 = 0;
10119                                         arr_idx2 <= reg_info->count2;
10120                                         arr_idx2++) {
10121                                 reg_offset = arr_idx * reg_info->stride1 +
10122                                         arr_idx2 * reg_info->stride2;
10123                                 reg_offset += reg_info->base_addr;
10124                                 ptr_data[reg_offset >> 2] =
10125                                         I40E_READ_REG(hw, reg_offset);
10126                         }
10127         }
10128
10129         return 0;
10130 }
10131
10132 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10133 {
10134         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10135
10136         /* Convert word count to byte count */
10137         return hw->nvm.sr_size << 1;
10138 }
10139
10140 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10141                            struct rte_dev_eeprom_info *eeprom)
10142 {
10143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10144         uint16_t *data = eeprom->data;
10145         uint16_t offset, length, cnt_words;
10146         int ret_code;
10147
10148         offset = eeprom->offset >> 1;
10149         length = eeprom->length >> 1;
10150         cnt_words = length;
10151
10152         if (offset > hw->nvm.sr_size ||
10153                 offset + length > hw->nvm.sr_size) {
10154                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10155                 return -EINVAL;
10156         }
10157
10158         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10159
10160         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10161         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10162                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10163                 return -EIO;
10164         }
10165
10166         return 0;
10167 }
10168
10169 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10170                                       struct ether_addr *mac_addr)
10171 {
10172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10174         struct i40e_vsi *vsi = pf->main_vsi;
10175         struct i40e_mac_filter_info mac_filter;
10176         struct i40e_mac_filter *f;
10177         int ret;
10178
10179         if (!is_valid_assigned_ether_addr(mac_addr)) {
10180                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10181                 return;
10182         }
10183
10184         TAILQ_FOREACH(f, &vsi->mac_list, next) {
10185                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
10186                         break;
10187         }
10188
10189         if (f == NULL) {
10190                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
10191                 return;
10192         }
10193
10194         mac_filter = f->mac_info;
10195         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
10196         if (ret != I40E_SUCCESS) {
10197                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
10198                 return;
10199         }
10200         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
10201         ret = i40e_vsi_add_mac(vsi, &mac_filter);
10202         if (ret != I40E_SUCCESS) {
10203                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
10204                 return;
10205         }
10206         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
10207
10208         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
10209                                   mac_addr->addr_bytes, NULL);
10210 }
10211
10212 static int
10213 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10214 {
10215         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10216         struct rte_eth_dev_data *dev_data = pf->dev_data;
10217         uint32_t frame_size = mtu + ETHER_HDR_LEN
10218                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10219         int ret = 0;
10220
10221         /* check if mtu is within the allowed range */
10222         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10223                 return -EINVAL;
10224
10225         /* mtu setting is forbidden if port is start */
10226         if (dev_data->dev_started) {
10227                 PMD_DRV_LOG(ERR,
10228                             "port %d must be stopped before configuration\n",
10229                             dev_data->port_id);
10230                 return -EBUSY;
10231         }
10232
10233         if (frame_size > ETHER_MAX_LEN)
10234                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10235         else
10236                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10237
10238         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10239
10240         return ret;
10241 }