drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and inteval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518 };
 519
 520 /* store statistics names and its offset in stats structure */
 521 struct rte_i40e_xstats_name_off {
 522         char name[RTE_ETH_XSTATS_NAME_SIZE];
 523         unsigned offset;
 524 };
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 527         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 528         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 529         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 530         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 531         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 532                 rx_unknown_protocol)},
 533         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 534         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 535         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 536         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 537 };
 538
 539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 540                 sizeof(rte_i40e_stats_strings[0]))
 541
 542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 543         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 544                 tx_dropped_link_down)},
 545         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 546         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 547                 illegal_bytes)},
 548         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 549         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_local_faults)},
 551         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 552                 mac_remote_faults)},
 553         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 554                 rx_length_errors)},
 555         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 556         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 557         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 558         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 559         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 560         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_127)},
 562         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_255)},
 564         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_511)},
 566         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1023)},
 568         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_1522)},
 570         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_big)},
 572         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_undersize)},
 574         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_oversize)},
 576         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 577                 mac_short_packet_dropped)},
 578         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_fragments)},
 580         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 581         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 582         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_127)},
 584         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_255)},
 586         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_511)},
 588         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1023)},
 590         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_1522)},
 592         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_big)},
 594         {"rx_flow_director_atr_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 596         {"rx_flow_director_sb_match_packets",
 597                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 598         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_status)},
 600         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_status)},
 602         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 tx_lpi_count)},
 604         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 605                 rx_lpi_count)},
 606 };
 607
 608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 609                 sizeof(rte_i40e_hw_port_strings[0]))
 610
 611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 612         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xon_rx)},
 614         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 615                 priority_xoff_rx)},
 616 };
 617
 618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 619                 sizeof(rte_i40e_rxq_prio_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_tx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_tx)},
 626         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xon_2_xoff)},
 628 };
 629
 630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 631                 sizeof(rte_i40e_txq_prio_strings[0]))
 632
 633 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 634         struct rte_pci_device *pci_dev)
 635 {
 636         return rte_eth_dev_pci_generic_probe(pci_dev,
 637                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 638 }
 639
 640 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 641 {
 642         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 643 }
 644
 645 static struct rte_pci_driver rte_i40e_pmd = {
 646         .id_table = pci_id_i40e_map,
 647         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 648         .probe = eth_i40e_pci_probe,
 649         .remove = eth_i40e_pci_remove,
 650 };
 651
 652 static inline int
 653 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 654                                      struct rte_eth_link *link)
 655 {
 656         struct rte_eth_link *dst = link;
 657         struct rte_eth_link *src = &(dev->data->dev_link);
 658
 659         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 660                                         *(uint64_t *)src) == 0)
 661                 return -1;
 662
 663         return 0;
 664 }
 665
 666 static inline int
 667 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 668                                       struct rte_eth_link *link)
 669 {
 670         struct rte_eth_link *dst = &(dev->data->dev_link);
 671         struct rte_eth_link *src = link;
 672
 673         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 674                                         *(uint64_t *)src) == 0)
 675                 return -1;
 676
 677         return 0;
 678 }
 679
 680 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 681 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 682 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 683
 684 #ifndef I40E_GLQF_ORT
 685 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 686 #endif
 687 #ifndef I40E_GLQF_PIT
 688 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 689 #endif
 690 #ifndef I40E_GLQF_L3_MAP
 691 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 692 #endif
 693
 694 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 695 {
 696         /*
 697          * Initialize registers for flexible payload, which should be set by NVM.
 698          * This should be removed from code once it is fixed in NVM.
 699          */
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 710         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 712
 713         /* Initialize registers for parsing packet type of QinQ */
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 715         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 716 }
 717
 718 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 719
 720 /*
 721  * Add a ethertype filter to drop all flow control frames transmitted
 722  * from VSIs.
 723 */
 724 static void
 725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 726 {
 727         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 728         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 729                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 731         int ret;
 732
 733         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 734                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 735                                 pf->main_vsi_seid, 0,
 736                                 TRUE, NULL, NULL);
 737         if (ret)
 738                 PMD_INIT_LOG(ERR,
 739                         "Failed to add filter to drop flow control frames from VSIs.");
 740 }
 741
 742 static int
 743 floating_veb_list_handler(__rte_unused const char *key,
 744                           const char *floating_veb_value,
 745                           void *opaque)
 746 {
 747         int idx = 0;
 748         unsigned int count = 0;
 749         char *end = NULL;
 750         int min, max;
 751         bool *vf_floating_veb = opaque;
 752
 753         while (isblank(*floating_veb_value))
 754                 floating_veb_value++;
 755
 756         /* Reset floating VEB configuration for VFs */
 757         for (idx = 0; idx < I40E_MAX_VF; idx++)
 758                 vf_floating_veb[idx] = false;
 759
 760         min = I40E_MAX_VF;
 761         do {
 762                 while (isblank(*floating_veb_value))
 763                         floating_veb_value++;
 764                 if (*floating_veb_value == '\0')
 765                         return -1;
 766                 errno = 0;
 767                 idx = strtoul(floating_veb_value, &end, 10);
 768                 if (errno || end == NULL)
 769                         return -1;
 770                 while (isblank(*end))
 771                         end++;
 772                 if (*end == '-') {
 773                         min = idx;
 774                 } else if ((*end == ';') || (*end == '\0')) {
 775                         max = idx;
 776                         if (min == I40E_MAX_VF)
 777                                 min = idx;
 778                         if (max >= I40E_MAX_VF)
 779                                 max = I40E_MAX_VF - 1;
 780                         for (idx = min; idx <= max; idx++) {
 781                                 vf_floating_veb[idx] = true;
 782                                 count++;
 783                         }
 784                         min = I40E_MAX_VF;
 785                 } else {
 786                         return -1;
 787                 }
 788                 floating_veb_value = end + 1;
 789         } while (*end != '\0');
 790
 791         if (count == 0)
 792                 return -1;
 793
 794         return 0;
 795 }
 796
 797 static void
 798 config_vf_floating_veb(struct rte_devargs *devargs,
 799                        uint16_t floating_veb,
 800                        bool *vf_floating_veb)
 801 {
 802         struct rte_kvargs *kvlist;
 803         int i;
 804         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 805
 806         if (!floating_veb)
 807                 return;
 808         /* All the VFs attach to the floating VEB by default
 809          * when the floating VEB is enabled.
 810          */
 811         for (i = 0; i < I40E_MAX_VF; i++)
 812                 vf_floating_veb[i] = true;
 813
 814         if (devargs == NULL)
 815                 return;
 816
 817         kvlist = rte_kvargs_parse(devargs->args, NULL);
 818         if (kvlist == NULL)
 819                 return;
 820
 821         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 822                 rte_kvargs_free(kvlist);
 823                 return;
 824         }
 825         /* When the floating_veb_list parameter exists, all the VFs
 826          * will attach to the legacy VEB firstly, then configure VFs
 827          * to the floating VEB according to the floating_veb_list.
 828          */
 829         if (rte_kvargs_process(kvlist, floating_veb_list,
 830                                floating_veb_list_handler,
 831                                vf_floating_veb) < 0) {
 832                 rte_kvargs_free(kvlist);
 833                 return;
 834         }
 835         rte_kvargs_free(kvlist);
 836 }
 837
 838 static int
 839 i40e_check_floating_handler(__rte_unused const char *key,
 840                             const char *value,
 841                             __rte_unused void *opaque)
 842 {
 843         if (strcmp(value, "1"))
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 static int
 850 is_floating_veb_supported(struct rte_devargs *devargs)
 851 {
 852         struct rte_kvargs *kvlist;
 853         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 854
 855         if (devargs == NULL)
 856                 return 0;
 857
 858         kvlist = rte_kvargs_parse(devargs->args, NULL);
 859         if (kvlist == NULL)
 860                 return 0;
 861
 862         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 863                 rte_kvargs_free(kvlist);
 864                 return 0;
 865         }
 866         /* Floating VEB is enabled when there's key-value:
 867          * enable_floating_veb=1
 868          */
 869         if (rte_kvargs_process(kvlist, floating_veb_key,
 870                                i40e_check_floating_handler, NULL) < 0) {
 871                 rte_kvargs_free(kvlist);
 872                 return 0;
 873         }
 874         rte_kvargs_free(kvlist);
 875
 876         return 1;
 877 }
 878
 879 static void
 880 config_floating_veb(struct rte_eth_dev *dev)
 881 {
 882         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 885
 886         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 887
 888         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 889                 pf->floating_veb =
 890                         is_floating_veb_supported(pci_dev->device.devargs);
 891                 config_vf_floating_veb(pci_dev->device.devargs,
 892                                        pf->floating_veb,
 893                                        pf->floating_veb_list);
 894         } else {
 895                 pf->floating_veb = false;
 896         }
 897 }
 898
 899 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 900 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 901
 902 static int
 903 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 904 {
 905         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 906         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 907         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 908         int ret;
 909
 910         struct rte_hash_parameters ethertype_hash_params = {
 911                 .name = ethertype_hash_name,
 912                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 913                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 914                 .hash_func = rte_hash_crc,
 915                 .hash_func_init_val = 0,
 916                 .socket_id = rte_socket_id(),
 917         };
 918
 919         /* Initialize ethertype filter rule list and hash */
 920         TAILQ_INIT(&ethertype_rule->ethertype_list);
 921         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 922                  "ethertype_%s", dev->data->name);
 923         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 924         if (!ethertype_rule->hash_table) {
 925                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 926                 return -EINVAL;
 927         }
 928         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 929                                        sizeof(struct i40e_ethertype_filter *) *
 930                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 931                                        0);
 932         if (!ethertype_rule->hash_map) {
 933                 PMD_INIT_LOG(ERR,
 934                              "Failed to allocate memory for ethertype hash map!");
 935                 ret = -ENOMEM;
 936                 goto err_ethertype_hash_map_alloc;
 937         }
 938
 939         return 0;
 940
 941 err_ethertype_hash_map_alloc:
 942         rte_hash_free(ethertype_rule->hash_table);
 943
 944         return ret;
 945 }
 946
 947 static int
 948 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 949 {
 950         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 951         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 952         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 953         int ret;
 954
 955         struct rte_hash_parameters tunnel_hash_params = {
 956                 .name = tunnel_hash_name,
 957                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 958                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 959                 .hash_func = rte_hash_crc,
 960                 .hash_func_init_val = 0,
 961                 .socket_id = rte_socket_id(),
 962         };
 963
 964         /* Initialize tunnel filter rule list and hash */
 965         TAILQ_INIT(&tunnel_rule->tunnel_list);
 966         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 967                  "tunnel_%s", dev->data->name);
 968         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 969         if (!tunnel_rule->hash_table) {
 970                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 971                 return -EINVAL;
 972         }
 973         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 974                                     sizeof(struct i40e_tunnel_filter *) *
 975                                     I40E_MAX_TUNNEL_FILTER_NUM,
 976                                     0);
 977         if (!tunnel_rule->hash_map) {
 978                 PMD_INIT_LOG(ERR,
 979                              "Failed to allocate memory for tunnel hash map!");
 980                 ret = -ENOMEM;
 981                 goto err_tunnel_hash_map_alloc;
 982         }
 983
 984         return 0;
 985
 986 err_tunnel_hash_map_alloc:
 987         rte_hash_free(tunnel_rule->hash_table);
 988
 989         return ret;
 990 }
 991
 992 static int
 993 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 994 {
 995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 996         struct i40e_fdir_info *fdir_info = &pf->fdir;
 997         char fdir_hash_name[RTE_HASH_NAMESIZE];
 998         int ret;
 999
1000         struct rte_hash_parameters fdir_hash_params = {
1001                 .name = fdir_hash_name,
1002                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1003                 .key_len = sizeof(struct rte_eth_fdir_input),
1004                 .hash_func = rte_hash_crc,
1005                 .hash_func_init_val = 0,
1006                 .socket_id = rte_socket_id(),
1007         };
1008
1009         /* Initialize flow director filter rule list and hash */
1010         TAILQ_INIT(&fdir_info->fdir_list);
1011         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1012                  "fdir_%s", dev->data->name);
1013         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1014         if (!fdir_info->hash_table) {
1015                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1016                 return -EINVAL;
1017         }
1018         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1019                                           sizeof(struct i40e_fdir_filter *) *
1020                                           I40E_MAX_FDIR_FILTER_NUM,
1021                                           0);
1022         if (!fdir_info->hash_map) {
1023                 PMD_INIT_LOG(ERR,
1024                              "Failed to allocate memory for fdir hash map!");
1025                 ret = -ENOMEM;
1026                 goto err_fdir_hash_map_alloc;
1027         }
1028         return 0;
1029
1030 err_fdir_hash_map_alloc:
1031         rte_hash_free(fdir_info->hash_table);
1032
1033         return ret;
1034 }
1035
1036 static int
1037 eth_i40e_dev_init(struct rte_eth_dev *dev)
1038 {
1039         struct rte_pci_device *pci_dev;
1040         struct rte_intr_handle *intr_handle;
1041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043         struct i40e_vsi *vsi;
1044         int ret;
1045         uint32_t len;
1046         uint8_t aq_fail = 0;
1047
1048         PMD_INIT_FUNC_TRACE();
1049
1050         dev->dev_ops = &i40e_eth_dev_ops;
1051         dev->rx_pkt_burst = i40e_recv_pkts;
1052         dev->tx_pkt_burst = i40e_xmit_pkts;
1053         dev->tx_pkt_prepare = i40e_prep_pkts;
1054
1055         /* for secondary processes, we don't initialise any further as primary
1056          * has already done this work. Only check we don't need a different
1057          * RX function */
1058         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1059                 i40e_set_rx_function(dev);
1060                 i40e_set_tx_function(dev);
1061                 return 0;
1062         }
1063         i40e_set_default_ptype_table(dev);
1064         pci_dev = I40E_DEV_TO_PCI(dev);
1065         intr_handle = &pci_dev->intr_handle;
1066
1067         rte_eth_copy_pci_info(dev, pci_dev);
1068         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1069
1070         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071         pf->adapter->eth_dev = dev;
1072         pf->dev_data = dev->data;
1073
1074         hw->back = I40E_PF_TO_ADAPTER(pf);
1075         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1076         if (!hw->hw_addr) {
1077                 PMD_INIT_LOG(ERR,
1078                         "Hardware is not available, as address is NULL");
1079                 return -ENODEV;
1080         }
1081
1082         hw->vendor_id = pci_dev->id.vendor_id;
1083         hw->device_id = pci_dev->id.device_id;
1084         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086         hw->bus.device = pci_dev->addr.devid;
1087         hw->bus.func = pci_dev->addr.function;
1088         hw->adapter_stopped = 0;
1089
1090         /* Make sure all is clean before doing PF reset */
1091         i40e_clear_hw(hw);
1092
1093         /* Initialize the hardware */
1094         i40e_hw_init(dev);
1095
1096         /* Reset here to make sure all is clean for each PF */
1097         ret = i40e_pf_reset(hw);
1098         if (ret) {
1099                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1100                 return ret;
1101         }
1102
1103         /* Initialize the shared code (base driver) */
1104         ret = i40e_init_shared_code(hw);
1105         if (ret) {
1106                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1107                 return ret;
1108         }
1109
1110         /*
1111          * To work around the NVM issue, initialize registers
1112          * for flexible payload and packet type of QinQ by
1113          * software. It should be removed once issues are fixed
1114          * in NVM.
1115          */
1116         i40e_GLQF_reg_init(hw);
1117
1118         /* Initialize the input set for filters (hash and fd) to default value */
1119         i40e_filter_input_set_init(pf);
1120
1121         /* Initialize the parameters for adminq */
1122         i40e_init_adminq_parameter(hw);
1123         ret = i40e_init_adminq(hw);
1124         if (ret != I40E_SUCCESS) {
1125                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1126                 return -EIO;
1127         }
1128         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131                      ((hw->nvm.version >> 12) & 0xf),
1132                      ((hw->nvm.version >> 4) & 0xff),
1133                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1134
1135         /* initialise the L3_MAP register */
1136         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1137                                    0x00000028,  NULL);
1138         if (ret)
1139                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1140
1141         /* Need the special FW version to support floating VEB */
1142         config_floating_veb(dev);
1143         /* Clear PXE mode */
1144         i40e_clear_pxe_mode(hw);
1145         ret = i40e_dev_sync_phy_type(hw);
1146         if (ret) {
1147                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1148                 goto err_sync_phy_type;
1149         }
1150         /*
1151          * On X710, performance number is far from the expectation on recent
1152          * firmware versions. The fix for this issue may not be integrated in
1153          * the following firmware version. So the workaround in software driver
1154          * is needed. It needs to modify the initial values of 3 internal only
1155          * registers. Note that the workaround can be removed when it is fixed
1156          * in firmware in the future.
1157          */
1158         i40e_configure_registers(hw);
1159
1160         /* Get hw capabilities */
1161         ret = i40e_get_cap(hw);
1162         if (ret != I40E_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164                 goto err_get_capabilities;
1165         }
1166
1167         /* Initialize parameters for PF */
1168         ret = i40e_pf_parameter_init(dev);
1169         if (ret != 0) {
1170                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171                 goto err_parameter_init;
1172         }
1173
1174         /* Initialize the queue management */
1175         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1176         if (ret < 0) {
1177                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178                 goto err_qp_pool_init;
1179         }
1180         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181                                 hw->func_caps.num_msix_vectors - 1);
1182         if (ret < 0) {
1183                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184                 goto err_msix_pool_init;
1185         }
1186
1187         /* Initialize lan hmc */
1188         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189                                 hw->func_caps.num_rx_qp, 0, 0);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192                 goto err_init_lan_hmc;
1193         }
1194
1195         /* Configure lan hmc */
1196         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197         if (ret != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199                 goto err_configure_lan_hmc;
1200         }
1201
1202         /* Get and check the mac address */
1203         i40e_get_mac_addr(hw, hw->mac.addr);
1204         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205                 PMD_INIT_LOG(ERR, "mac address is not valid");
1206                 ret = -EIO;
1207                 goto err_get_mac_addr;
1208         }
1209         /* Copy the permanent MAC address */
1210         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211                         (struct ether_addr *) hw->mac.perm_addr);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* Set the global registers with default ether type value */
1218         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219         if (ret != I40E_SUCCESS) {
1220                 PMD_INIT_LOG(ERR,
1221                         "Failed to set the default outer VLAN ether type");
1222                 goto err_setup_pf_switch;
1223         }
1224
1225         /* PF setup, which includes VSI setup */
1226         ret = i40e_pf_setup(pf);
1227         if (ret) {
1228                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229                 goto err_setup_pf_switch;
1230         }
1231
1232         /* reset all stats of the device, including pf and main vsi */
1233         i40e_dev_stats_reset(dev);
1234
1235         vsi = pf->main_vsi;
1236
1237         /* Disable double vlan by default */
1238         i40e_vsi_config_double_vlan(vsi, FALSE);
1239
1240         /* Disable S-TAG identification when floating_veb is disabled */
1241         if (!pf->floating_veb) {
1242                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1246                 }
1247         }
1248
1249         if (!vsi->max_macaddrs)
1250                 len = ETHER_ADDR_LEN;
1251         else
1252                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1253
1254         /* Should be after VSI initialized */
1255         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256         if (!dev->data->mac_addrs) {
1257                 PMD_INIT_LOG(ERR,
1258                         "Failed to allocated memory for storing mac address");
1259                 goto err_mac_alloc;
1260         }
1261         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262                                         &dev->data->mac_addrs[0]);
1263
1264         /* Init dcb to sw mode by default */
1265         ret = i40e_dcb_init_configure(dev, TRUE);
1266         if (ret != I40E_SUCCESS) {
1267                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268                 pf->flags &= ~I40E_FLAG_DCB;
1269         }
1270         /* Update HW struct after DCB configuration */
1271         i40e_get_cap(hw);
1272
1273         /* initialize pf host driver to setup SRIOV resource if applicable */
1274         i40e_pf_host_init(dev);
1275
1276         /* register callback func to eal lib */
1277         rte_intr_callback_register(intr_handle,
1278                                    i40e_dev_interrupt_handler, dev);
1279
1280         /* configure and enable device interrupt */
1281         i40e_pf_config_irq0(hw, TRUE);
1282         i40e_pf_enable_irq0(hw);
1283
1284         /* enable uio intr after callback register */
1285         rte_intr_enable(intr_handle);
1286         /*
1287          * Add an ethertype filter to drop all flow control frames transmitted
1288          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1289          * frames to wire.
1290          */
1291         i40e_add_tx_flow_control_drop_filter(pf);
1292
1293         /* Set the max frame size to 0x2600 by default,
1294          * in case other drivers changed the default value.
1295          */
1296         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1297
1298         /* initialize mirror rule list */
1299         TAILQ_INIT(&pf->mirror_list);
1300
1301         ret = i40e_init_ethtype_filter_list(dev);
1302         if (ret < 0)
1303                 goto err_init_ethtype_filter_list;
1304         ret = i40e_init_tunnel_filter_list(dev);
1305         if (ret < 0)
1306                 goto err_init_tunnel_filter_list;
1307         ret = i40e_init_fdir_filter_list(dev);
1308         if (ret < 0)
1309                 goto err_init_fdir_filter_list;
1310
1311         return 0;
1312
1313 err_init_fdir_filter_list:
1314         rte_free(pf->tunnel.hash_table);
1315         rte_free(pf->tunnel.hash_map);
1316 err_init_tunnel_filter_list:
1317         rte_free(pf->ethertype.hash_table);
1318         rte_free(pf->ethertype.hash_map);
1319 err_init_ethtype_filter_list:
1320         rte_free(dev->data->mac_addrs);
1321 err_mac_alloc:
1322         i40e_vsi_release(pf->main_vsi);
1323 err_setup_pf_switch:
1324 err_get_mac_addr:
1325 err_configure_lan_hmc:
1326         (void)i40e_shutdown_lan_hmc(hw);
1327 err_init_lan_hmc:
1328         i40e_res_pool_destroy(&pf->msix_pool);
1329 err_msix_pool_init:
1330         i40e_res_pool_destroy(&pf->qp_pool);
1331 err_qp_pool_init:
1332 err_parameter_init:
1333 err_get_capabilities:
1334 err_sync_phy_type:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = I40E_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int
1468 i40e_dev_configure(struct rte_eth_dev *dev)
1469 {
1470         struct i40e_adapter *ad =
1471                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1473         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1474         int i, ret;
1475
1476         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1477          * bulk allocation or vector Rx preconditions we will reset it.
1478          */
1479         ad->rx_bulk_alloc_allowed = true;
1480         ad->rx_vec_allowed = true;
1481         ad->tx_simple_allowed = true;
1482         ad->tx_vec_allowed = true;
1483
1484         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1485                 ret = i40e_fdir_setup(pf);
1486                 if (ret != I40E_SUCCESS) {
1487                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1488                         return -ENOTSUP;
1489                 }
1490                 ret = i40e_fdir_configure(dev);
1491                 if (ret < 0) {
1492                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1493                         goto err;
1494                 }
1495         } else
1496                 i40e_fdir_teardown(pf);
1497
1498         ret = i40e_dev_init_vlan(dev);
1499         if (ret < 0)
1500                 goto err;
1501
1502         /* VMDQ setup.
1503          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1504          *  RSS setting have different requirements.
1505          *  General PMD driver call sequence are NIC init, configure,
1506          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1507          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1508          *  applicable. So, VMDQ setting has to be done before
1509          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1510          *  For RSS setting, it will try to calculate actual configured RX queue
1511          *  number, which will be available after rx_queue_setup(). dev_start()
1512          *  function is good to place RSS setup.
1513          */
1514         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1515                 ret = i40e_vmdq_setup(dev);
1516                 if (ret)
1517                         goto err;
1518         }
1519
1520         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1521                 ret = i40e_dcb_setup(dev);
1522                 if (ret) {
1523                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1524                         goto err_dcb;
1525                 }
1526         }
1527
1528         TAILQ_INIT(&pf->flow_list);
1529
1530         return 0;
1531
1532 err_dcb:
1533         /* need to release vmdq resource if exists */
1534         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1535                 i40e_vsi_release(pf->vmdq[i].vsi);
1536                 pf->vmdq[i].vsi = NULL;
1537         }
1538         rte_free(pf->vmdq);
1539         pf->vmdq = NULL;
1540 err:
1541         /* need to release fdir resource if exists */
1542         i40e_fdir_teardown(pf);
1543         return ret;
1544 }
1545
1546 void
1547 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1548 {
1549         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1550         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1551         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1553         uint16_t msix_vect = vsi->msix_intr;
1554         uint16_t i;
1555
1556         for (i = 0; i < vsi->nb_qps; i++) {
1557                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1558                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1559                 rte_wmb();
1560         }
1561
1562         if (vsi->type != I40E_VSI_SRIOV) {
1563                 if (!rte_intr_allow_others(intr_handle)) {
1564                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1565                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1566                         I40E_WRITE_REG(hw,
1567                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1568                                        0);
1569                 } else {
1570                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1571                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1572                         I40E_WRITE_REG(hw,
1573                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1574                                                        msix_vect - 1), 0);
1575                 }
1576         } else {
1577                 uint32_t reg;
1578                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1579                         vsi->user_param + (msix_vect - 1);
1580
1581                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1582                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1583         }
1584         I40E_WRITE_FLUSH(hw);
1585 }
1586
1587 static void
1588 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1589                        int base_queue, int nb_queue)
1590 {
1591         int i;
1592         uint32_t val;
1593         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1594
1595         /* Bind all RX queues to allocated MSIX interrupt */
1596         for (i = 0; i < nb_queue; i++) {
1597                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1598                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1599                         ((base_queue + i + 1) <<
1600                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1601                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1602                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1603
1604                 if (i == nb_queue - 1)
1605                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1606                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1607         }
1608
1609         /* Write first RX queue to Link list register as the head element */
1610         if (vsi->type != I40E_VSI_SRIOV) {
1611                 uint16_t interval =
1612                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1613
1614                 if (msix_vect == I40E_MISC_VEC_ID) {
1615                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1616                                        (base_queue <<
1617                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1618                                        (0x0 <<
1619                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1620                         I40E_WRITE_REG(hw,
1621                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1622                                        interval);
1623                 } else {
1624                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1625                                        (base_queue <<
1626                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1627                                        (0x0 <<
1628                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1629                         I40E_WRITE_REG(hw,
1630                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1631                                                        msix_vect - 1),
1632                                        interval);
1633                 }
1634         } else {
1635                 uint32_t reg;
1636
1637                 if (msix_vect == I40E_MISC_VEC_ID) {
1638                         I40E_WRITE_REG(hw,
1639                                        I40E_VPINT_LNKLST0(vsi->user_param),
1640                                        (base_queue <<
1641                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1642                                        (0x0 <<
1643                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1644                 } else {
1645                         /* num_msix_vectors_vf needs to minus irq0 */
1646                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1647                                 vsi->user_param + (msix_vect - 1);
1648
1649                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1650                                        (base_queue <<
1651                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1652                                        (0x0 <<
1653                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1654                 }
1655         }
1656
1657         I40E_WRITE_FLUSH(hw);
1658 }
1659
1660 void
1661 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1662 {
1663         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1664         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1665         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1667         uint16_t msix_vect = vsi->msix_intr;
1668         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1669         uint16_t queue_idx = 0;
1670         int record = 0;
1671         uint32_t val;
1672         int i;
1673
1674         for (i = 0; i < vsi->nb_qps; i++) {
1675                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1676                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1677         }
1678
1679         /* INTENA flag is not auto-cleared for interrupt */
1680         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1681         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1682                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1683                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1684         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1685
1686         /* VF bind interrupt */
1687         if (vsi->type == I40E_VSI_SRIOV) {
1688                 __vsi_queues_bind_intr(vsi, msix_vect,
1689                                        vsi->base_queue, vsi->nb_qps);
1690                 return;
1691         }
1692
1693         /* PF & VMDq bind interrupt */
1694         if (rte_intr_dp_is_en(intr_handle)) {
1695                 if (vsi->type == I40E_VSI_MAIN) {
1696                         queue_idx = 0;
1697                         record = 1;
1698                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1699                         struct i40e_vsi *main_vsi =
1700                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1701                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1702                         record = 1;
1703                 }
1704         }
1705
1706         for (i = 0; i < vsi->nb_used_qps; i++) {
1707                 if (nb_msix <= 1) {
1708                         if (!rte_intr_allow_others(intr_handle))
1709                                 /* allow to share MISC_VEC_ID */
1710                                 msix_vect = I40E_MISC_VEC_ID;
1711
1712                         /* no enough msix_vect, map all to one */
1713                         __vsi_queues_bind_intr(vsi, msix_vect,
1714                                                vsi->base_queue + i,
1715                                                vsi->nb_used_qps - i);
1716                         for (; !!record && i < vsi->nb_used_qps; i++)
1717                                 intr_handle->intr_vec[queue_idx + i] =
1718                                         msix_vect;
1719                         break;
1720                 }
1721                 /* 1:1 queue/msix_vect mapping */
1722                 __vsi_queues_bind_intr(vsi, msix_vect,
1723                                        vsi->base_queue + i, 1);
1724                 if (!!record)
1725                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1726
1727                 msix_vect++;
1728                 nb_msix--;
1729         }
1730 }
1731
1732 static void
1733 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1734 {
1735         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1736         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1737         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1738         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1739         uint16_t interval = i40e_calc_itr_interval(\
1740                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1741         uint16_t msix_intr, i;
1742
1743         if (rte_intr_allow_others(intr_handle))
1744                 for (i = 0; i < vsi->nb_msix; i++) {
1745                         msix_intr = vsi->msix_intr + i;
1746                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1747                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1748                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1749                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1750                                 (interval <<
1751                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1752                 }
1753         else
1754                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1755                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1756                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1757                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1758                                (interval <<
1759                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1760
1761         I40E_WRITE_FLUSH(hw);
1762 }
1763
1764 static void
1765 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1766 {
1767         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1769         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771         uint16_t msix_intr, i;
1772
1773         if (rte_intr_allow_others(intr_handle))
1774                 for (i = 0; i < vsi->nb_msix; i++) {
1775                         msix_intr = vsi->msix_intr + i;
1776                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1777                                        0);
1778                 }
1779         else
1780                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1781
1782         I40E_WRITE_FLUSH(hw);
1783 }
1784
1785 static inline uint8_t
1786 i40e_parse_link_speeds(uint16_t link_speeds)
1787 {
1788         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1789
1790         if (link_speeds & ETH_LINK_SPEED_40G)
1791                 link_speed |= I40E_LINK_SPEED_40GB;
1792         if (link_speeds & ETH_LINK_SPEED_25G)
1793                 link_speed |= I40E_LINK_SPEED_25GB;
1794         if (link_speeds & ETH_LINK_SPEED_20G)
1795                 link_speed |= I40E_LINK_SPEED_20GB;
1796         if (link_speeds & ETH_LINK_SPEED_10G)
1797                 link_speed |= I40E_LINK_SPEED_10GB;
1798         if (link_speeds & ETH_LINK_SPEED_1G)
1799                 link_speed |= I40E_LINK_SPEED_1GB;
1800         if (link_speeds & ETH_LINK_SPEED_100M)
1801                 link_speed |= I40E_LINK_SPEED_100MB;
1802
1803         return link_speed;
1804 }
1805
1806 static int
1807 i40e_phy_conf_link(struct i40e_hw *hw,
1808                    uint8_t abilities,
1809                    uint8_t force_speed)
1810 {
1811         enum i40e_status_code status;
1812         struct i40e_aq_get_phy_abilities_resp phy_ab;
1813         struct i40e_aq_set_phy_config phy_conf;
1814         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1815                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1816                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1817                         I40E_AQ_PHY_FLAG_LOW_POWER;
1818         const uint8_t advt = I40E_LINK_SPEED_40GB |
1819                         I40E_LINK_SPEED_25GB |
1820                         I40E_LINK_SPEED_10GB |
1821                         I40E_LINK_SPEED_1GB |
1822                         I40E_LINK_SPEED_100MB;
1823         int ret = -ENOTSUP;
1824
1825
1826         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1827                                               NULL);
1828         if (status)
1829                 return ret;
1830
1831         memset(&phy_conf, 0, sizeof(phy_conf));
1832
1833         /* bits 0-2 use the values from get_phy_abilities_resp */
1834         abilities &= ~mask;
1835         abilities |= phy_ab.abilities & mask;
1836
1837         /* update ablities and speed */
1838         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1839                 phy_conf.link_speed = advt;
1840         else
1841                 phy_conf.link_speed = force_speed;
1842
1843         phy_conf.abilities = abilities;
1844
1845         /* use get_phy_abilities_resp value for the rest */
1846         phy_conf.phy_type = phy_ab.phy_type;
1847         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1848         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1849         phy_conf.eee_capability = phy_ab.eee_capability;
1850         phy_conf.eeer = phy_ab.eeer_val;
1851         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1852
1853         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1854                     phy_ab.abilities, phy_ab.link_speed);
1855         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1856                     phy_conf.abilities, phy_conf.link_speed);
1857
1858         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1859         if (status)
1860                 return ret;
1861
1862         return I40E_SUCCESS;
1863 }
1864
1865 static int
1866 i40e_apply_link_speed(struct rte_eth_dev *dev)
1867 {
1868         uint8_t speed;
1869         uint8_t abilities = 0;
1870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         struct rte_eth_conf *conf = &dev->data->dev_conf;
1872
1873         speed = i40e_parse_link_speeds(conf->link_speeds);
1874         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1875         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1876                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1877         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1878
1879         /* Skip changing speed on 40G interfaces, FW does not support */
1880         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1881                 speed =  I40E_LINK_SPEED_UNKNOWN;
1882                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1883         }
1884
1885         return i40e_phy_conf_link(hw, abilities, speed);
1886 }
1887
1888 static int
1889 i40e_dev_start(struct rte_eth_dev *dev)
1890 {
1891         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893         struct i40e_vsi *main_vsi = pf->main_vsi;
1894         int ret, i;
1895         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1896         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897         uint32_t intr_vector = 0;
1898         struct i40e_vsi *vsi;
1899
1900         hw->adapter_stopped = 0;
1901
1902         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1903                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1904                              dev->data->port_id);
1905                 return -EINVAL;
1906         }
1907
1908         rte_intr_disable(intr_handle);
1909
1910         if ((rte_intr_cap_multiple(intr_handle) ||
1911              !RTE_ETH_DEV_SRIOV(dev).active) &&
1912             dev->data->dev_conf.intr_conf.rxq != 0) {
1913                 intr_vector = dev->data->nb_rx_queues;
1914                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1915                 if (ret)
1916                         return ret;
1917         }
1918
1919         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1920                 intr_handle->intr_vec =
1921                         rte_zmalloc("intr_vec",
1922                                     dev->data->nb_rx_queues * sizeof(int),
1923                                     0);
1924                 if (!intr_handle->intr_vec) {
1925                         PMD_INIT_LOG(ERR,
1926                                 "Failed to allocate %d rx_queues intr_vec",
1927                                 dev->data->nb_rx_queues);
1928                         return -ENOMEM;
1929                 }
1930         }
1931
1932         /* Initialize VSI */
1933         ret = i40e_dev_rxtx_init(pf);
1934         if (ret != I40E_SUCCESS) {
1935                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1936                 goto err_up;
1937         }
1938
1939         /* Map queues with MSIX interrupt */
1940         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1941                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1942         i40e_vsi_queues_bind_intr(main_vsi);
1943         i40e_vsi_enable_queues_intr(main_vsi);
1944
1945         /* Map VMDQ VSI queues with MSIX interrupt */
1946         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1947                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1948                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1949                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1950         }
1951
1952         /* enable FDIR MSIX interrupt */
1953         if (pf->fdir.fdir_vsi) {
1954                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1955                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1956         }
1957
1958         /* Enable all queues which have been configured */
1959         ret = i40e_dev_switch_queues(pf, TRUE);
1960         if (ret != I40E_SUCCESS) {
1961                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1962                 goto err_up;
1963         }
1964
1965         /* Enable receiving broadcast packets */
1966         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1967         if (ret != I40E_SUCCESS)
1968                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1969
1970         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1971                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1972                                                 true, NULL);
1973                 if (ret != I40E_SUCCESS)
1974                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1975         }
1976
1977         /* Enable the VLAN promiscuous mode. */
1978         if (pf->vfs) {
1979                 for (i = 0; i < pf->vf_num; i++) {
1980                         vsi = pf->vfs[i].vsi;
1981                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1982                                                      true, NULL);
1983                 }
1984         }
1985
1986         /* Apply link configure */
1987         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1988                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1989                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1990                                 ETH_LINK_SPEED_40G)) {
1991                 PMD_DRV_LOG(ERR, "Invalid link setting");
1992                 goto err_up;
1993         }
1994         ret = i40e_apply_link_speed(dev);
1995         if (I40E_SUCCESS != ret) {
1996                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1997                 goto err_up;
1998         }
1999
2000         if (!rte_intr_allow_others(intr_handle)) {
2001                 rte_intr_callback_unregister(intr_handle,
2002                                              i40e_dev_interrupt_handler,
2003                                              (void *)dev);
2004                 /* configure and enable device interrupt */
2005                 i40e_pf_config_irq0(hw, FALSE);
2006                 i40e_pf_enable_irq0(hw);
2007
2008                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2009                         PMD_INIT_LOG(INFO,
2010                                 "lsc won't enable because of no intr multiplex");
2011         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2012                 ret = i40e_aq_set_phy_int_mask(hw,
2013                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2014                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2015                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2016                 if (ret != I40E_SUCCESS)
2017                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2018
2019                 /* Call get_link_info aq commond to enable LSE */
2020                 i40e_dev_link_update(dev, 0);
2021         }
2022
2023         /* enable uio intr after callback register */
2024         rte_intr_enable(intr_handle);
2025
2026         i40e_filter_restore(pf);
2027
2028         return I40E_SUCCESS;
2029
2030 err_up:
2031         i40e_dev_switch_queues(pf, FALSE);
2032         i40e_dev_clear_queues(dev);
2033
2034         return ret;
2035 }
2036
2037 static void
2038 i40e_dev_stop(struct rte_eth_dev *dev)
2039 {
2040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2041         struct i40e_vsi *main_vsi = pf->main_vsi;
2042         struct i40e_mirror_rule *p_mirror;
2043         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2044         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2045         int i;
2046
2047         /* Disable all queues */
2048         i40e_dev_switch_queues(pf, FALSE);
2049
2050         /* un-map queues with interrupt registers */
2051         i40e_vsi_disable_queues_intr(main_vsi);
2052         i40e_vsi_queues_unbind_intr(main_vsi);
2053
2054         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2055                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2056                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2057         }
2058
2059         if (pf->fdir.fdir_vsi) {
2060                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2061                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2062         }
2063         /* Clear all queues and release memory */
2064         i40e_dev_clear_queues(dev);
2065
2066         /* Set link down */
2067         i40e_dev_set_link_down(dev);
2068
2069         /* Remove all mirror rules */
2070         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2071                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2072                 rte_free(p_mirror);
2073         }
2074         pf->nb_mirror_rule = 0;
2075
2076         if (!rte_intr_allow_others(intr_handle))
2077                 /* resume to the default handler */
2078                 rte_intr_callback_register(intr_handle,
2079                                            i40e_dev_interrupt_handler,
2080                                            (void *)dev);
2081
2082         /* Clean datapath event and queue/vec mapping */
2083         rte_intr_efd_disable(intr_handle);
2084         if (intr_handle->intr_vec) {
2085                 rte_free(intr_handle->intr_vec);
2086                 intr_handle->intr_vec = NULL;
2087         }
2088 }
2089
2090 static void
2091 i40e_dev_close(struct rte_eth_dev *dev)
2092 {
2093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2096         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2097         uint32_t reg;
2098         int i;
2099
2100         PMD_INIT_FUNC_TRACE();
2101
2102         i40e_dev_stop(dev);
2103         hw->adapter_stopped = 1;
2104         i40e_dev_free_queues(dev);
2105
2106         /* Disable interrupt */
2107         i40e_pf_disable_irq0(hw);
2108         rte_intr_disable(intr_handle);
2109
2110         /* shutdown and destroy the HMC */
2111         i40e_shutdown_lan_hmc(hw);
2112
2113         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114                 i40e_vsi_release(pf->vmdq[i].vsi);
2115                 pf->vmdq[i].vsi = NULL;
2116         }
2117         rte_free(pf->vmdq);
2118         pf->vmdq = NULL;
2119
2120         /* release all the existing VSIs and VEBs */
2121         i40e_fdir_teardown(pf);
2122         i40e_vsi_release(pf->main_vsi);
2123
2124         /* shutdown the adminq */
2125         i40e_aq_queue_shutdown(hw, true);
2126         i40e_shutdown_adminq(hw);
2127
2128         i40e_res_pool_destroy(&pf->qp_pool);
2129         i40e_res_pool_destroy(&pf->msix_pool);
2130
2131         /* force a PF reset to clean anything leftover */
2132         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2133         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2134                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2135         I40E_WRITE_FLUSH(hw);
2136 }
2137
2138 static void
2139 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2140 {
2141         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143         struct i40e_vsi *vsi = pf->main_vsi;
2144         int status;
2145
2146         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2147                                                      true, NULL, true);
2148         if (status != I40E_SUCCESS)
2149                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2150
2151         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2152                                                         TRUE, NULL);
2153         if (status != I40E_SUCCESS)
2154                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2155
2156 }
2157
2158 static void
2159 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2160 {
2161         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         struct i40e_vsi *vsi = pf->main_vsi;
2164         int status;
2165
2166         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2167                                                      false, NULL, true);
2168         if (status != I40E_SUCCESS)
2169                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2170
2171         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2172                                                         false, NULL);
2173         if (status != I40E_SUCCESS)
2174                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2175 }
2176
2177 static void
2178 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2179 {
2180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2181         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         struct i40e_vsi *vsi = pf->main_vsi;
2183         int ret;
2184
2185         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2186         if (ret != I40E_SUCCESS)
2187                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2188 }
2189
2190 static void
2191 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2192 {
2193         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2194         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195         struct i40e_vsi *vsi = pf->main_vsi;
2196         int ret;
2197
2198         if (dev->data->promiscuous == 1)
2199                 return; /* must remain in all_multicast mode */
2200
2201         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2202                                 vsi->seid, FALSE, NULL);
2203         if (ret != I40E_SUCCESS)
2204                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2205 }
2206
2207 /*
2208  * Set device link up.
2209  */
2210 static int
2211 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2212 {
2213         /* re-apply link speed setting */
2214         return i40e_apply_link_speed(dev);
2215 }
2216
2217 /*
2218  * Set device link down.
2219  */
2220 static int
2221 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2222 {
2223         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2224         uint8_t abilities = 0;
2225         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226
2227         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2228         return i40e_phy_conf_link(hw, abilities, speed);
2229 }
2230
2231 int
2232 i40e_dev_link_update(struct rte_eth_dev *dev,
2233                      int wait_to_complete)
2234 {
2235 #define CHECK_INTERVAL 100  /* 100ms */
2236 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         struct i40e_link_status link_status;
2239         struct rte_eth_link link, old;
2240         int status;
2241         unsigned rep_cnt = MAX_REPEAT_TIME;
2242         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2243
2244         memset(&link, 0, sizeof(link));
2245         memset(&old, 0, sizeof(old));
2246         memset(&link_status, 0, sizeof(link_status));
2247         rte_i40e_dev_atomic_read_link_status(dev, &old);
2248
2249         do {
2250                 /* Get link status information from hardware */
2251                 status = i40e_aq_get_link_info(hw, enable_lse,
2252                                                 &link_status, NULL);
2253                 if (status != I40E_SUCCESS) {
2254                         link.link_speed = ETH_SPEED_NUM_100M;
2255                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2256                         PMD_DRV_LOG(ERR, "Failed to get link info");
2257                         goto out;
2258                 }
2259
2260                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2261                 if (!wait_to_complete || link.link_status)
2262                         break;
2263
2264                 rte_delay_ms(CHECK_INTERVAL);
2265         } while (--rep_cnt);
2266
2267         if (!link.link_status)
2268                 goto out;
2269
2270         /* i40e uses full duplex only */
2271         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2272
2273         /* Parse the link status */
2274         switch (link_status.link_speed) {
2275         case I40E_LINK_SPEED_100MB:
2276                 link.link_speed = ETH_SPEED_NUM_100M;
2277                 break;
2278         case I40E_LINK_SPEED_1GB:
2279                 link.link_speed = ETH_SPEED_NUM_1G;
2280                 break;
2281         case I40E_LINK_SPEED_10GB:
2282                 link.link_speed = ETH_SPEED_NUM_10G;
2283                 break;
2284         case I40E_LINK_SPEED_20GB:
2285                 link.link_speed = ETH_SPEED_NUM_20G;
2286                 break;
2287         case I40E_LINK_SPEED_25GB:
2288                 link.link_speed = ETH_SPEED_NUM_25G;
2289                 break;
2290         case I40E_LINK_SPEED_40GB:
2291                 link.link_speed = ETH_SPEED_NUM_40G;
2292                 break;
2293         default:
2294                 link.link_speed = ETH_SPEED_NUM_100M;
2295                 break;
2296         }
2297
2298         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2299                         ETH_LINK_SPEED_FIXED);
2300
2301 out:
2302         rte_i40e_dev_atomic_write_link_status(dev, &link);
2303         if (link.link_status == old.link_status)
2304                 return -1;
2305
2306         i40e_notify_all_vfs_link_status(dev);
2307
2308         return 0;
2309 }
2310
2311 /* Get all the statistics of a VSI */
2312 void
2313 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2314 {
2315         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2316         struct i40e_eth_stats *nes = &vsi->eth_stats;
2317         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2318         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2319
2320         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2321                             vsi->offset_loaded, &oes->rx_bytes,
2322                             &nes->rx_bytes);
2323         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2324                             vsi->offset_loaded, &oes->rx_unicast,
2325                             &nes->rx_unicast);
2326         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2327                             vsi->offset_loaded, &oes->rx_multicast,
2328                             &nes->rx_multicast);
2329         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2330                             vsi->offset_loaded, &oes->rx_broadcast,
2331                             &nes->rx_broadcast);
2332         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2333                             &oes->rx_discards, &nes->rx_discards);
2334         /* GLV_REPC not supported */
2335         /* GLV_RMPC not supported */
2336         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2337                             &oes->rx_unknown_protocol,
2338                             &nes->rx_unknown_protocol);
2339         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2340                             vsi->offset_loaded, &oes->tx_bytes,
2341                             &nes->tx_bytes);
2342         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2343                             vsi->offset_loaded, &oes->tx_unicast,
2344                             &nes->tx_unicast);
2345         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2346                             vsi->offset_loaded, &oes->tx_multicast,
2347                             &nes->tx_multicast);
2348         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2349                             vsi->offset_loaded,  &oes->tx_broadcast,
2350                             &nes->tx_broadcast);
2351         /* GLV_TDPC not supported */
2352         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2353                             &oes->tx_errors, &nes->tx_errors);
2354         vsi->offset_loaded = true;
2355
2356         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2357                     vsi->vsi_id);
2358         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2359         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2360         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2361         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2362         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2363         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2364                     nes->rx_unknown_protocol);
2365         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2366         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2367         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2368         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2369         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2370         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2371         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2372                     vsi->vsi_id);
2373 }
2374
2375 static void
2376 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2377 {
2378         unsigned int i;
2379         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2380         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2381
2382         /* Get statistics of struct i40e_eth_stats */
2383         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2384                             I40E_GLPRT_GORCL(hw->port),
2385                             pf->offset_loaded, &os->eth.rx_bytes,
2386                             &ns->eth.rx_bytes);
2387         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2388                             I40E_GLPRT_UPRCL(hw->port),
2389                             pf->offset_loaded, &os->eth.rx_unicast,
2390                             &ns->eth.rx_unicast);
2391         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2392                             I40E_GLPRT_MPRCL(hw->port),
2393                             pf->offset_loaded, &os->eth.rx_multicast,
2394                             &ns->eth.rx_multicast);
2395         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2396                             I40E_GLPRT_BPRCL(hw->port),
2397                             pf->offset_loaded, &os->eth.rx_broadcast,
2398                             &ns->eth.rx_broadcast);
2399         /* Workaround: CRC size should not be included in byte statistics,
2400          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2401          */
2402         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2403                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2404
2405         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2406                             pf->offset_loaded, &os->eth.rx_discards,
2407                             &ns->eth.rx_discards);
2408         /* GLPRT_REPC not supported */
2409         /* GLPRT_RMPC not supported */
2410         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2411                             pf->offset_loaded,
2412                             &os->eth.rx_unknown_protocol,
2413                             &ns->eth.rx_unknown_protocol);
2414         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2415                             I40E_GLPRT_GOTCL(hw->port),
2416                             pf->offset_loaded, &os->eth.tx_bytes,
2417                             &ns->eth.tx_bytes);
2418         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2419                             I40E_GLPRT_UPTCL(hw->port),
2420                             pf->offset_loaded, &os->eth.tx_unicast,
2421                             &ns->eth.tx_unicast);
2422         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2423                             I40E_GLPRT_MPTCL(hw->port),
2424                             pf->offset_loaded, &os->eth.tx_multicast,
2425                             &ns->eth.tx_multicast);
2426         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2427                             I40E_GLPRT_BPTCL(hw->port),
2428                             pf->offset_loaded, &os->eth.tx_broadcast,
2429                             &ns->eth.tx_broadcast);
2430         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2431                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2432         /* GLPRT_TEPC not supported */
2433
2434         /* additional port specific stats */
2435         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2436                             pf->offset_loaded, &os->tx_dropped_link_down,
2437                             &ns->tx_dropped_link_down);
2438         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2439                             pf->offset_loaded, &os->crc_errors,
2440                             &ns->crc_errors);
2441         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2442                             pf->offset_loaded, &os->illegal_bytes,
2443                             &ns->illegal_bytes);
2444         /* GLPRT_ERRBC not supported */
2445         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2446                             pf->offset_loaded, &os->mac_local_faults,
2447                             &ns->mac_local_faults);
2448         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2449                             pf->offset_loaded, &os->mac_remote_faults,
2450                             &ns->mac_remote_faults);
2451         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2452                             pf->offset_loaded, &os->rx_length_errors,
2453                             &ns->rx_length_errors);
2454         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2455                             pf->offset_loaded, &os->link_xon_rx,
2456                             &ns->link_xon_rx);
2457         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2458                             pf->offset_loaded, &os->link_xoff_rx,
2459                             &ns->link_xoff_rx);
2460         for (i = 0; i < 8; i++) {
2461                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2462                                     pf->offset_loaded,
2463                                     &os->priority_xon_rx[i],
2464                                     &ns->priority_xon_rx[i]);
2465                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2466                                     pf->offset_loaded,
2467                                     &os->priority_xoff_rx[i],
2468                                     &ns->priority_xoff_rx[i]);
2469         }
2470         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2471                             pf->offset_loaded, &os->link_xon_tx,
2472                             &ns->link_xon_tx);
2473         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2474                             pf->offset_loaded, &os->link_xoff_tx,
2475                             &ns->link_xoff_tx);
2476         for (i = 0; i < 8; i++) {
2477                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2478                                     pf->offset_loaded,
2479                                     &os->priority_xon_tx[i],
2480                                     &ns->priority_xon_tx[i]);
2481                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2482                                     pf->offset_loaded,
2483                                     &os->priority_xoff_tx[i],
2484                                     &ns->priority_xoff_tx[i]);
2485                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2486                                     pf->offset_loaded,
2487                                     &os->priority_xon_2_xoff[i],
2488                                     &ns->priority_xon_2_xoff[i]);
2489         }
2490         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2491                             I40E_GLPRT_PRC64L(hw->port),
2492                             pf->offset_loaded, &os->rx_size_64,
2493                             &ns->rx_size_64);
2494         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2495                             I40E_GLPRT_PRC127L(hw->port),
2496                             pf->offset_loaded, &os->rx_size_127,
2497                             &ns->rx_size_127);
2498         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2499                             I40E_GLPRT_PRC255L(hw->port),
2500                             pf->offset_loaded, &os->rx_size_255,
2501                             &ns->rx_size_255);
2502         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2503                             I40E_GLPRT_PRC511L(hw->port),
2504                             pf->offset_loaded, &os->rx_size_511,
2505                             &ns->rx_size_511);
2506         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2507                             I40E_GLPRT_PRC1023L(hw->port),
2508                             pf->offset_loaded, &os->rx_size_1023,
2509                             &ns->rx_size_1023);
2510         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2511                             I40E_GLPRT_PRC1522L(hw->port),
2512                             pf->offset_loaded, &os->rx_size_1522,
2513                             &ns->rx_size_1522);
2514         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2515                             I40E_GLPRT_PRC9522L(hw->port),
2516                             pf->offset_loaded, &os->rx_size_big,
2517                             &ns->rx_size_big);
2518         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2519                             pf->offset_loaded, &os->rx_undersize,
2520                             &ns->rx_undersize);
2521         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2522                             pf->offset_loaded, &os->rx_fragments,
2523                             &ns->rx_fragments);
2524         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2525                             pf->offset_loaded, &os->rx_oversize,
2526                             &ns->rx_oversize);
2527         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2528                             pf->offset_loaded, &os->rx_jabber,
2529                             &ns->rx_jabber);
2530         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2531                             I40E_GLPRT_PTC64L(hw->port),
2532                             pf->offset_loaded, &os->tx_size_64,
2533                             &ns->tx_size_64);
2534         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2535                             I40E_GLPRT_PTC127L(hw->port),
2536                             pf->offset_loaded, &os->tx_size_127,
2537                             &ns->tx_size_127);
2538         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2539                             I40E_GLPRT_PTC255L(hw->port),
2540                             pf->offset_loaded, &os->tx_size_255,
2541                             &ns->tx_size_255);
2542         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2543                             I40E_GLPRT_PTC511L(hw->port),
2544                             pf->offset_loaded, &os->tx_size_511,
2545                             &ns->tx_size_511);
2546         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2547                             I40E_GLPRT_PTC1023L(hw->port),
2548                             pf->offset_loaded, &os->tx_size_1023,
2549                             &ns->tx_size_1023);
2550         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2551                             I40E_GLPRT_PTC1522L(hw->port),
2552                             pf->offset_loaded, &os->tx_size_1522,
2553                             &ns->tx_size_1522);
2554         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2555                             I40E_GLPRT_PTC9522L(hw->port),
2556                             pf->offset_loaded, &os->tx_size_big,
2557                             &ns->tx_size_big);
2558         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2559                            pf->offset_loaded,
2560                            &os->fd_sb_match, &ns->fd_sb_match);
2561         /* GLPRT_MSPDC not supported */
2562         /* GLPRT_XEC not supported */
2563
2564         pf->offset_loaded = true;
2565
2566         if (pf->main_vsi)
2567                 i40e_update_vsi_stats(pf->main_vsi);
2568 }
2569
2570 /* Get all statistics of a port */
2571 static void
2572 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2573 {
2574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2577         unsigned i;
2578
2579         /* call read registers - updates values, now write them to struct */
2580         i40e_read_stats_registers(pf, hw);
2581
2582         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2583                         pf->main_vsi->eth_stats.rx_multicast +
2584                         pf->main_vsi->eth_stats.rx_broadcast -
2585                         pf->main_vsi->eth_stats.rx_discards;
2586         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2587                         pf->main_vsi->eth_stats.tx_multicast +
2588                         pf->main_vsi->eth_stats.tx_broadcast;
2589         stats->ibytes   = ns->eth.rx_bytes;
2590         stats->obytes   = ns->eth.tx_bytes;
2591         stats->oerrors  = ns->eth.tx_errors +
2592                         pf->main_vsi->eth_stats.tx_errors;
2593
2594         /* Rx Errors */
2595         stats->imissed  = ns->eth.rx_discards +
2596                         pf->main_vsi->eth_stats.rx_discards;
2597         stats->ierrors  = ns->crc_errors +
2598                         ns->rx_length_errors + ns->rx_undersize +
2599                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2600
2601         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2602         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2603         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2604         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2605         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2606         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2607         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2608                     ns->eth.rx_unknown_protocol);
2609         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2610         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2611         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2612         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2613         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2614         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2615
2616         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2617                     ns->tx_dropped_link_down);
2618         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2619         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2620                     ns->illegal_bytes);
2621         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2622         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2623                     ns->mac_local_faults);
2624         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2625                     ns->mac_remote_faults);
2626         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2627                     ns->rx_length_errors);
2628         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2629         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2630         for (i = 0; i < 8; i++) {
2631                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2632                                 i, ns->priority_xon_rx[i]);
2633                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2634                                 i, ns->priority_xoff_rx[i]);
2635         }
2636         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2637         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2638         for (i = 0; i < 8; i++) {
2639                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2640                                 i, ns->priority_xon_tx[i]);
2641                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2642                                 i, ns->priority_xoff_tx[i]);
2643                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2644                                 i, ns->priority_xon_2_xoff[i]);
2645         }
2646         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2647         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2648         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2649         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2650         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2651         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2652         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2653         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2654         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2655         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2656         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2657         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2658         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2659         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2660         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2661         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2662         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2663         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2664         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2665                         ns->mac_short_packet_dropped);
2666         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2667                     ns->checksum_error);
2668         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2669         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2670 }
2671
2672 /* Reset the statistics */
2673 static void
2674 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2675 {
2676         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2677         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2678
2679         /* Mark PF and VSI stats to update the offset, aka "reset" */
2680         pf->offset_loaded = false;
2681         if (pf->main_vsi)
2682                 pf->main_vsi->offset_loaded = false;
2683
2684         /* read the stats, reading current register values into offset */
2685         i40e_read_stats_registers(pf, hw);
2686 }
2687
2688 static uint32_t
2689 i40e_xstats_calc_num(void)
2690 {
2691         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2692                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2693                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2694 }
2695
2696 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2697                                      struct rte_eth_xstat_name *xstats_names,
2698                                      __rte_unused unsigned limit)
2699 {
2700         unsigned count = 0;
2701         unsigned i, prio;
2702
2703         if (xstats_names == NULL)
2704                 return i40e_xstats_calc_num();
2705
2706         /* Note: limit checked in rte_eth_xstats_names() */
2707
2708         /* Get stats from i40e_eth_stats struct */
2709         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2710                 snprintf(xstats_names[count].name,
2711                          sizeof(xstats_names[count].name),
2712                          "%s", rte_i40e_stats_strings[i].name);
2713                 count++;
2714         }
2715
2716         /* Get individiual stats from i40e_hw_port struct */
2717         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2718                 snprintf(xstats_names[count].name,
2719                         sizeof(xstats_names[count].name),
2720                          "%s", rte_i40e_hw_port_strings[i].name);
2721                 count++;
2722         }
2723
2724         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2725                 for (prio = 0; prio < 8; prio++) {
2726                         snprintf(xstats_names[count].name,
2727                                  sizeof(xstats_names[count].name),
2728                                  "rx_priority%u_%s", prio,
2729                                  rte_i40e_rxq_prio_strings[i].name);
2730                         count++;
2731                 }
2732         }
2733
2734         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2735                 for (prio = 0; prio < 8; prio++) {
2736                         snprintf(xstats_names[count].name,
2737                                  sizeof(xstats_names[count].name),
2738                                  "tx_priority%u_%s", prio,
2739                                  rte_i40e_txq_prio_strings[i].name);
2740                         count++;
2741                 }
2742         }
2743         return count;
2744 }
2745
2746 static int
2747 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2748                     unsigned n)
2749 {
2750         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2752         unsigned i, count, prio;
2753         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2754
2755         count = i40e_xstats_calc_num();
2756         if (n < count)
2757                 return count;
2758
2759         i40e_read_stats_registers(pf, hw);
2760
2761         if (xstats == NULL)
2762                 return 0;
2763
2764         count = 0;
2765
2766         /* Get stats from i40e_eth_stats struct */
2767         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2768                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2769                         rte_i40e_stats_strings[i].offset);
2770                 xstats[count].id = count;
2771                 count++;
2772         }
2773
2774         /* Get individiual stats from i40e_hw_port struct */
2775         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2776                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2777                         rte_i40e_hw_port_strings[i].offset);
2778                 xstats[count].id = count;
2779                 count++;
2780         }
2781
2782         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2783                 for (prio = 0; prio < 8; prio++) {
2784                         xstats[count].value =
2785                                 *(uint64_t *)(((char *)hw_stats) +
2786                                 rte_i40e_rxq_prio_strings[i].offset +
2787                                 (sizeof(uint64_t) * prio));
2788                         xstats[count].id = count;
2789                         count++;
2790                 }
2791         }
2792
2793         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2794                 for (prio = 0; prio < 8; prio++) {
2795                         xstats[count].value =
2796                                 *(uint64_t *)(((char *)hw_stats) +
2797                                 rte_i40e_txq_prio_strings[i].offset +
2798                                 (sizeof(uint64_t) * prio));
2799                         xstats[count].id = count;
2800                         count++;
2801                 }
2802         }
2803
2804         return count;
2805 }
2806
2807 static int
2808 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2809                                  __rte_unused uint16_t queue_id,
2810                                  __rte_unused uint8_t stat_idx,
2811                                  __rte_unused uint8_t is_rx)
2812 {
2813         PMD_INIT_FUNC_TRACE();
2814
2815         return -ENOSYS;
2816 }
2817
2818 static int
2819 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2820 {
2821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822         u32 full_ver;
2823         u8 ver, patch;
2824         u16 build;
2825         int ret;
2826
2827         full_ver = hw->nvm.oem_ver;
2828         ver = (u8)(full_ver >> 24);
2829         build = (u16)((full_ver >> 8) & 0xffff);
2830         patch = (u8)(full_ver & 0xff);
2831
2832         ret = snprintf(fw_version, fw_size,
2833                  "%d.%d%d 0x%08x %d.%d.%d",
2834                  ((hw->nvm.version >> 12) & 0xf),
2835                  ((hw->nvm.version >> 4) & 0xff),
2836                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2837                  ver, build, patch);
2838
2839         ret += 1; /* add the size of '\0' */
2840         if (fw_size < (u32)ret)
2841                 return ret;
2842         else
2843                 return 0;
2844 }
2845
2846 static void
2847 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2848 {
2849         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2851         struct i40e_vsi *vsi = pf->main_vsi;
2852         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2853
2854         dev_info->pci_dev = pci_dev;
2855         dev_info->max_rx_queues = vsi->nb_qps;
2856         dev_info->max_tx_queues = vsi->nb_qps;
2857         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2858         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2859         dev_info->max_mac_addrs = vsi->max_macaddrs;
2860         dev_info->max_vfs = pci_dev->max_vfs;
2861         dev_info->rx_offload_capa =
2862                 DEV_RX_OFFLOAD_VLAN_STRIP |
2863                 DEV_RX_OFFLOAD_QINQ_STRIP |
2864                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2865                 DEV_RX_OFFLOAD_UDP_CKSUM |
2866                 DEV_RX_OFFLOAD_TCP_CKSUM;
2867         dev_info->tx_offload_capa =
2868                 DEV_TX_OFFLOAD_VLAN_INSERT |
2869                 DEV_TX_OFFLOAD_QINQ_INSERT |
2870                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2871                 DEV_TX_OFFLOAD_UDP_CKSUM |
2872                 DEV_TX_OFFLOAD_TCP_CKSUM |
2873                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2874                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2875                 DEV_TX_OFFLOAD_TCP_TSO |
2876                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2877                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2878                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2879                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2880         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2881                                                 sizeof(uint32_t);
2882         dev_info->reta_size = pf->hash_lut_size;
2883         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2884
2885         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2886                 .rx_thresh = {
2887                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2888                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2889                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2890                 },
2891                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2892                 .rx_drop_en = 0,
2893         };
2894
2895         dev_info->default_txconf = (struct rte_eth_txconf) {
2896                 .tx_thresh = {
2897                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2898                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2899                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2900                 },
2901                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2902                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2903                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2904                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2905         };
2906
2907         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2908                 .nb_max = I40E_MAX_RING_DESC,
2909                 .nb_min = I40E_MIN_RING_DESC,
2910                 .nb_align = I40E_ALIGN_RING_DESC,
2911         };
2912
2913         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2914                 .nb_max = I40E_MAX_RING_DESC,
2915                 .nb_min = I40E_MIN_RING_DESC,
2916                 .nb_align = I40E_ALIGN_RING_DESC,
2917                 .nb_seg_max = I40E_TX_MAX_SEG,
2918                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2919         };
2920
2921         if (pf->flags & I40E_FLAG_VMDQ) {
2922                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2923                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2924                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2925                                                 pf->max_nb_vmdq_vsi;
2926                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2927                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2928                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2929         }
2930
2931         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2932                 /* For XL710 */
2933                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2934         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2935                 /* For XXV710 */
2936                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2937         else
2938                 /* For X710 */
2939                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2940 }
2941
2942 static int
2943 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2944 {
2945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2946         struct i40e_vsi *vsi = pf->main_vsi;
2947         PMD_INIT_FUNC_TRACE();
2948
2949         if (on)
2950                 return i40e_vsi_add_vlan(vsi, vlan_id);
2951         else
2952                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2953 }
2954
2955 static int
2956 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2957                    enum rte_vlan_type vlan_type,
2958                    uint16_t tpid)
2959 {
2960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961         uint64_t reg_r = 0, reg_w = 0;
2962         uint16_t reg_id = 0;
2963         int ret = 0;
2964         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2965
2966         switch (vlan_type) {
2967         case ETH_VLAN_TYPE_OUTER:
2968                 if (qinq)
2969                         reg_id = 2;
2970                 else
2971                         reg_id = 3;
2972                 break;
2973         case ETH_VLAN_TYPE_INNER:
2974                 if (qinq)
2975                         reg_id = 3;
2976                 else {
2977                         ret = -EINVAL;
2978                         PMD_DRV_LOG(ERR,
2979                                 "Unsupported vlan type in single vlan.");
2980                         return ret;
2981                 }
2982                 break;
2983         default:
2984                 ret = -EINVAL;
2985                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2986                 return ret;
2987         }
2988         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2989                                           &reg_r, NULL);
2990         if (ret != I40E_SUCCESS) {
2991                 PMD_DRV_LOG(ERR,
2992                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2993                            reg_id);
2994                 ret = -EIO;
2995                 return ret;
2996         }
2997         PMD_DRV_LOG(DEBUG,
2998                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2999                 reg_id, reg_r);
3000
3001         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3002         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3003         if (reg_r == reg_w) {
3004                 ret = 0;
3005                 PMD_DRV_LOG(DEBUG, "No need to write");
3006                 return ret;
3007         }
3008
3009         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3010                                            reg_w, NULL);
3011         if (ret != I40E_SUCCESS) {
3012                 ret = -EIO;
3013                 PMD_DRV_LOG(ERR,
3014                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3015                         reg_id);
3016                 return ret;
3017         }
3018         PMD_DRV_LOG(DEBUG,
3019                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3020                 reg_w, reg_id);
3021
3022         return ret;
3023 }
3024
3025 static void
3026 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3027 {
3028         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3029         struct i40e_vsi *vsi = pf->main_vsi;
3030
3031         if (mask & ETH_VLAN_FILTER_MASK) {
3032                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3033                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3034                 else
3035                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3036         }
3037
3038         if (mask & ETH_VLAN_STRIP_MASK) {
3039                 /* Enable or disable VLAN stripping */
3040                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3041                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3042                 else
3043                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3044         }
3045
3046         if (mask & ETH_VLAN_EXTEND_MASK) {
3047                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3048                         i40e_vsi_config_double_vlan(vsi, TRUE);
3049                         /* Set global registers with default ether type value */
3050                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3051                                            ETHER_TYPE_VLAN);
3052                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3053                                            ETHER_TYPE_VLAN);
3054                 }
3055                 else
3056                         i40e_vsi_config_double_vlan(vsi, FALSE);
3057         }
3058 }
3059
3060 static void
3061 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3062                           __rte_unused uint16_t queue,
3063                           __rte_unused int on)
3064 {
3065         PMD_INIT_FUNC_TRACE();
3066 }
3067
3068 static int
3069 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3070 {
3071         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3072         struct i40e_vsi *vsi = pf->main_vsi;
3073         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3074         struct i40e_vsi_vlan_pvid_info info;
3075
3076         memset(&info, 0, sizeof(info));
3077         info.on = on;
3078         if (info.on)
3079                 info.config.pvid = pvid;
3080         else {
3081                 info.config.reject.tagged =
3082                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3083                 info.config.reject.untagged =
3084                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3085         }
3086
3087         return i40e_vsi_vlan_pvid_set(vsi, &info);
3088 }
3089
3090 static int
3091 i40e_dev_led_on(struct rte_eth_dev *dev)
3092 {
3093         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094         uint32_t mode = i40e_led_get(hw);
3095
3096         if (mode == 0)
3097                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3098
3099         return 0;
3100 }
3101
3102 static int
3103 i40e_dev_led_off(struct rte_eth_dev *dev)
3104 {
3105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3106         uint32_t mode = i40e_led_get(hw);
3107
3108         if (mode != 0)
3109                 i40e_led_set(hw, 0, false);
3110
3111         return 0;
3112 }
3113
3114 static int
3115 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3116 {
3117         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3118         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3119
3120         fc_conf->pause_time = pf->fc_conf.pause_time;
3121         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3122         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3123
3124          /* Return current mode according to actual setting*/
3125         switch (hw->fc.current_mode) {
3126         case I40E_FC_FULL:
3127                 fc_conf->mode = RTE_FC_FULL;
3128                 break;
3129         case I40E_FC_TX_PAUSE:
3130                 fc_conf->mode = RTE_FC_TX_PAUSE;
3131                 break;
3132         case I40E_FC_RX_PAUSE:
3133                 fc_conf->mode = RTE_FC_RX_PAUSE;
3134                 break;
3135         case I40E_FC_NONE:
3136         default:
3137                 fc_conf->mode = RTE_FC_NONE;
3138         };
3139
3140         return 0;
3141 }
3142
3143 static int
3144 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3145 {
3146         uint32_t mflcn_reg, fctrl_reg, reg;
3147         uint32_t max_high_water;
3148         uint8_t i, aq_failure;
3149         int err;
3150         struct i40e_hw *hw;
3151         struct i40e_pf *pf;
3152         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3153                 [RTE_FC_NONE] = I40E_FC_NONE,
3154                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3155                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3156                 [RTE_FC_FULL] = I40E_FC_FULL
3157         };
3158
3159         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3160
3161         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3162         if ((fc_conf->high_water > max_high_water) ||
3163                         (fc_conf->high_water < fc_conf->low_water)) {
3164                 PMD_INIT_LOG(ERR,
3165                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3166                         max_high_water);
3167                 return -EINVAL;
3168         }
3169
3170         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3172         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3173
3174         pf->fc_conf.pause_time = fc_conf->pause_time;
3175         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3176         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3177
3178         PMD_INIT_FUNC_TRACE();
3179
3180         /* All the link flow control related enable/disable register
3181          * configuration is handle by the F/W
3182          */
3183         err = i40e_set_fc(hw, &aq_failure, true);
3184         if (err < 0)
3185                 return -ENOSYS;
3186
3187         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3188                 /* Configure flow control refresh threshold,
3189                  * the value for stat_tx_pause_refresh_timer[8]
3190                  * is used for global pause operation.
3191                  */
3192
3193                 I40E_WRITE_REG(hw,
3194                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3195                                pf->fc_conf.pause_time);
3196
3197                 /* configure the timer value included in transmitted pause
3198                  * frame,
3199                  * the value for stat_tx_pause_quanta[8] is used for global
3200                  * pause operation
3201                  */
3202                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3203                                pf->fc_conf.pause_time);
3204
3205                 fctrl_reg = I40E_READ_REG(hw,
3206                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3207
3208                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3209                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3210                 else
3211                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3212
3213                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3214                                fctrl_reg);
3215         } else {
3216                 /* Configure pause time (2 TCs per register) */
3217                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3218                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3219                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3220
3221                 /* Configure flow control refresh threshold value */
3222                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3223                                pf->fc_conf.pause_time / 2);
3224
3225                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3226
3227                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3228                  *depending on configuration
3229                  */
3230                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3231                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3232                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3233                 } else {
3234                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3235                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3236                 }
3237
3238                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3239         }
3240
3241         /* config the water marker both based on the packets and bytes */
3242         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3243                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3244                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3245         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3246                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3247                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3248         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3249                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3250                        << I40E_KILOSHIFT);
3251         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3252                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3253                        << I40E_KILOSHIFT);
3254
3255         I40E_WRITE_FLUSH(hw);
3256
3257         return 0;
3258 }
3259
3260 static int
3261 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3262                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3263 {
3264         PMD_INIT_FUNC_TRACE();
3265
3266         return -ENOSYS;
3267 }
3268
3269 /* Add a MAC address, and update filters */
3270 static int
3271 i40e_macaddr_add(struct rte_eth_dev *dev,
3272                  struct ether_addr *mac_addr,
3273                  __rte_unused uint32_t index,
3274                  uint32_t pool)
3275 {
3276         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3277         struct i40e_mac_filter_info mac_filter;
3278         struct i40e_vsi *vsi;
3279         int ret;
3280
3281         /* If VMDQ not enabled or configured, return */
3282         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3283                           !pf->nb_cfg_vmdq_vsi)) {
3284                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3285                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3286                         pool);
3287                 return -ENOTSUP;
3288         }
3289
3290         if (pool > pf->nb_cfg_vmdq_vsi) {
3291                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3292                                 pool, pf->nb_cfg_vmdq_vsi);
3293                 return -EINVAL;
3294         }
3295
3296         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3297         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3298                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3299         else
3300                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3301
3302         if (pool == 0)
3303                 vsi = pf->main_vsi;
3304         else
3305                 vsi = pf->vmdq[pool - 1].vsi;
3306
3307         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3308         if (ret != I40E_SUCCESS) {
3309                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3310                 return -ENODEV;
3311         }
3312         return 0;
3313 }
3314
3315 /* Remove a MAC address, and update filters */
3316 static void
3317 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3318 {
3319         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320         struct i40e_vsi *vsi;
3321         struct rte_eth_dev_data *data = dev->data;
3322         struct ether_addr *macaddr;
3323         int ret;
3324         uint32_t i;
3325         uint64_t pool_sel;
3326
3327         macaddr = &(data->mac_addrs[index]);
3328
3329         pool_sel = dev->data->mac_pool_sel[index];
3330
3331         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3332                 if (pool_sel & (1ULL << i)) {
3333                         if (i == 0)
3334                                 vsi = pf->main_vsi;
3335                         else {
3336                                 /* No VMDQ pool enabled or configured */
3337                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3338                                         (i > pf->nb_cfg_vmdq_vsi)) {
3339                                         PMD_DRV_LOG(ERR,
3340                                                 "No VMDQ pool enabled/configured");
3341                                         return;
3342                                 }
3343                                 vsi = pf->vmdq[i - 1].vsi;
3344                         }
3345                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3346
3347                         if (ret) {
3348                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3349                                 return;
3350                         }
3351                 }
3352         }
3353 }
3354
3355 /* Set perfect match or hash match of MAC and VLAN for a VF */
3356 static int
3357 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3358                  struct rte_eth_mac_filter *filter,
3359                  bool add)
3360 {
3361         struct i40e_hw *hw;
3362         struct i40e_mac_filter_info mac_filter;
3363         struct ether_addr old_mac;
3364         struct ether_addr *new_mac;
3365         struct i40e_pf_vf *vf = NULL;
3366         uint16_t vf_id;
3367         int ret;
3368
3369         if (pf == NULL) {
3370                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3371                 return -EINVAL;
3372         }
3373         hw = I40E_PF_TO_HW(pf);
3374
3375         if (filter == NULL) {
3376                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3377                 return -EINVAL;
3378         }
3379
3380         new_mac = &filter->mac_addr;
3381
3382         if (is_zero_ether_addr(new_mac)) {
3383                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3384                 return -EINVAL;
3385         }
3386
3387         vf_id = filter->dst_id;
3388
3389         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3390                 PMD_DRV_LOG(ERR, "Invalid argument.");
3391                 return -EINVAL;
3392         }
3393         vf = &pf->vfs[vf_id];
3394
3395         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3396                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3397                 return -EINVAL;
3398         }
3399
3400         if (add) {
3401                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3402                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3403                                 ETHER_ADDR_LEN);
3404                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3405                                  ETHER_ADDR_LEN);
3406
3407                 mac_filter.filter_type = filter->filter_type;
3408                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3409                 if (ret != I40E_SUCCESS) {
3410                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3411                         return -1;
3412                 }
3413                 ether_addr_copy(new_mac, &pf->dev_addr);
3414         } else {
3415                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3416                                 ETHER_ADDR_LEN);
3417                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3418                 if (ret != I40E_SUCCESS) {
3419                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3420                         return -1;
3421                 }
3422
3423                 /* Clear device address as it has been removed */
3424                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3425                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3426         }
3427
3428         return 0;
3429 }
3430
3431 /* MAC filter handle */
3432 static int
3433 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3434                 void *arg)
3435 {
3436         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3437         struct rte_eth_mac_filter *filter;
3438         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3439         int ret = I40E_NOT_SUPPORTED;
3440
3441         filter = (struct rte_eth_mac_filter *)(arg);
3442
3443         switch (filter_op) {
3444         case RTE_ETH_FILTER_NOP:
3445                 ret = I40E_SUCCESS;
3446                 break;
3447         case RTE_ETH_FILTER_ADD:
3448                 i40e_pf_disable_irq0(hw);
3449                 if (filter->is_vf)
3450                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3451                 i40e_pf_enable_irq0(hw);
3452                 break;
3453         case RTE_ETH_FILTER_DELETE:
3454                 i40e_pf_disable_irq0(hw);
3455                 if (filter->is_vf)
3456                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3457                 i40e_pf_enable_irq0(hw);
3458                 break;
3459         default:
3460                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3461                 ret = I40E_ERR_PARAM;
3462                 break;
3463         }
3464
3465         return ret;
3466 }
3467
3468 static int
3469 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3470 {
3471         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3472         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3473         int ret;
3474
3475         if (!lut)
3476                 return -EINVAL;
3477
3478         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3479                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3480                                           lut, lut_size);
3481                 if (ret) {
3482                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3483                         return ret;
3484                 }
3485         } else {
3486                 uint32_t *lut_dw = (uint32_t *)lut;
3487                 uint16_t i, lut_size_dw = lut_size / 4;
3488
3489                 for (i = 0; i < lut_size_dw; i++)
3490                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3491         }
3492
3493         return 0;
3494 }
3495
3496 static int
3497 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3498 {
3499         struct i40e_pf *pf;
3500         struct i40e_hw *hw;
3501         int ret;
3502
3503         if (!vsi || !lut)
3504                 return -EINVAL;
3505
3506         pf = I40E_VSI_TO_PF(vsi);
3507         hw = I40E_VSI_TO_HW(vsi);
3508
3509         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3510                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3511                                           lut, lut_size);
3512                 if (ret) {
3513                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3514                         return ret;
3515                 }
3516         } else {
3517                 uint32_t *lut_dw = (uint32_t *)lut;
3518                 uint16_t i, lut_size_dw = lut_size / 4;
3519
3520                 for (i = 0; i < lut_size_dw; i++)
3521                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3522                 I40E_WRITE_FLUSH(hw);
3523         }
3524
3525         return 0;
3526 }
3527
3528 static int
3529 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3530                          struct rte_eth_rss_reta_entry64 *reta_conf,
3531                          uint16_t reta_size)
3532 {
3533         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534         uint16_t i, lut_size = pf->hash_lut_size;
3535         uint16_t idx, shift;
3536         uint8_t *lut;
3537         int ret;
3538
3539         if (reta_size != lut_size ||
3540                 reta_size > ETH_RSS_RETA_SIZE_512) {
3541                 PMD_DRV_LOG(ERR,
3542                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3543                         reta_size, lut_size);
3544                 return -EINVAL;
3545         }
3546
3547         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3548         if (!lut) {
3549                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3550                 return -ENOMEM;
3551         }
3552         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3553         if (ret)
3554                 goto out;
3555         for (i = 0; i < reta_size; i++) {
3556                 idx = i / RTE_RETA_GROUP_SIZE;
3557                 shift = i % RTE_RETA_GROUP_SIZE;
3558                 if (reta_conf[idx].mask & (1ULL << shift))
3559                         lut[i] = reta_conf[idx].reta[shift];
3560         }
3561         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3562
3563 out:
3564         rte_free(lut);
3565
3566         return ret;
3567 }
3568
3569 static int
3570 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3571                         struct rte_eth_rss_reta_entry64 *reta_conf,
3572                         uint16_t reta_size)
3573 {
3574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3575         uint16_t i, lut_size = pf->hash_lut_size;
3576         uint16_t idx, shift;
3577         uint8_t *lut;
3578         int ret;
3579
3580         if (reta_size != lut_size ||
3581                 reta_size > ETH_RSS_RETA_SIZE_512) {
3582                 PMD_DRV_LOG(ERR,
3583                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3584                         reta_size, lut_size);
3585                 return -EINVAL;
3586         }
3587
3588         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3589         if (!lut) {
3590                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3591                 return -ENOMEM;
3592         }
3593
3594         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3595         if (ret)
3596                 goto out;
3597         for (i = 0; i < reta_size; i++) {
3598                 idx = i / RTE_RETA_GROUP_SIZE;
3599                 shift = i % RTE_RETA_GROUP_SIZE;
3600                 if (reta_conf[idx].mask & (1ULL << shift))
3601                         reta_conf[idx].reta[shift] = lut[i];
3602         }
3603
3604 out:
3605         rte_free(lut);
3606
3607         return ret;
3608 }
3609
3610 /**
3611  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3612  * @hw:   pointer to the HW structure
3613  * @mem:  pointer to mem struct to fill out
3614  * @size: size of memory requested
3615  * @alignment: what to align the allocation to
3616  **/
3617 enum i40e_status_code
3618 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3619                         struct i40e_dma_mem *mem,
3620                         u64 size,
3621                         u32 alignment)
3622 {
3623         const struct rte_memzone *mz = NULL;
3624         char z_name[RTE_MEMZONE_NAMESIZE];
3625
3626         if (!mem)
3627                 return I40E_ERR_PARAM;
3628
3629         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3630         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3631                                          alignment, RTE_PGSIZE_2M);
3632         if (!mz)
3633                 return I40E_ERR_NO_MEMORY;
3634
3635         mem->size = size;
3636         mem->va = mz->addr;
3637         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3638         mem->zone = (const void *)mz;
3639         PMD_DRV_LOG(DEBUG,
3640                 "memzone %s allocated with physical address: %"PRIu64,
3641                 mz->name, mem->pa);
3642
3643         return I40E_SUCCESS;
3644 }
3645
3646 /**
3647  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3648  * @hw:   pointer to the HW structure
3649  * @mem:  ptr to mem struct to free
3650  **/
3651 enum i40e_status_code
3652 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3653                     struct i40e_dma_mem *mem)
3654 {
3655         if (!mem)
3656                 return I40E_ERR_PARAM;
3657
3658         PMD_DRV_LOG(DEBUG,
3659                 "memzone %s to be freed with physical address: %"PRIu64,
3660                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3661         rte_memzone_free((const struct rte_memzone *)mem->zone);
3662         mem->zone = NULL;
3663         mem->va = NULL;
3664         mem->pa = (u64)0;
3665
3666         return I40E_SUCCESS;
3667 }
3668
3669 /**
3670  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3671  * @hw:   pointer to the HW structure
3672  * @mem:  pointer to mem struct to fill out
3673  * @size: size of memory requested
3674  **/
3675 enum i40e_status_code
3676 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3677                          struct i40e_virt_mem *mem,
3678                          u32 size)
3679 {
3680         if (!mem)
3681                 return I40E_ERR_PARAM;
3682
3683         mem->size = size;
3684         mem->va = rte_zmalloc("i40e", size, 0);
3685
3686         if (mem->va)
3687                 return I40E_SUCCESS;
3688         else
3689                 return I40E_ERR_NO_MEMORY;
3690 }
3691
3692 /**
3693  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3694  * @hw:   pointer to the HW structure
3695  * @mem:  pointer to mem struct to free
3696  **/
3697 enum i40e_status_code
3698 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3699                      struct i40e_virt_mem *mem)
3700 {
3701         if (!mem)
3702                 return I40E_ERR_PARAM;
3703
3704         rte_free(mem->va);
3705         mem->va = NULL;
3706
3707         return I40E_SUCCESS;
3708 }
3709
3710 void
3711 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3712 {
3713         rte_spinlock_init(&sp->spinlock);
3714 }
3715
3716 void
3717 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3718 {
3719         rte_spinlock_lock(&sp->spinlock);
3720 }
3721
3722 void
3723 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3724 {
3725         rte_spinlock_unlock(&sp->spinlock);
3726 }
3727
3728 void
3729 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3730 {
3731         return;
3732 }
3733
3734 /**
3735  * Get the hardware capabilities, which will be parsed
3736  * and saved into struct i40e_hw.
3737  */
3738 static int
3739 i40e_get_cap(struct i40e_hw *hw)
3740 {
3741         struct i40e_aqc_list_capabilities_element_resp *buf;
3742         uint16_t len, size = 0;
3743         int ret;
3744
3745         /* Calculate a huge enough buff for saving response data temporarily */
3746         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3747                                                 I40E_MAX_CAP_ELE_NUM;
3748         buf = rte_zmalloc("i40e", len, 0);
3749         if (!buf) {
3750                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3751                 return I40E_ERR_NO_MEMORY;
3752         }
3753
3754         /* Get, parse the capabilities and save it to hw */
3755         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3756                         i40e_aqc_opc_list_func_capabilities, NULL);
3757         if (ret != I40E_SUCCESS)
3758                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3759
3760         /* Free the temporary buffer after being used */
3761         rte_free(buf);
3762
3763         return ret;
3764 }
3765
3766 static int
3767 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3768 {
3769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3770         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3771         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3772         uint16_t qp_count = 0, vsi_count = 0;
3773
3774         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3775                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3776                 return -EINVAL;
3777         }
3778         /* Add the parameter init for LFC */
3779         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3780         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3781         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3782
3783         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3784         pf->max_num_vsi = hw->func_caps.num_vsis;
3785         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3786         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3787         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3788
3789         /* FDir queue/VSI allocation */
3790         pf->fdir_qp_offset = 0;
3791         if (hw->func_caps.fd) {
3792                 pf->flags |= I40E_FLAG_FDIR;
3793                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3794         } else {
3795                 pf->fdir_nb_qps = 0;
3796         }
3797         qp_count += pf->fdir_nb_qps;
3798         vsi_count += 1;
3799
3800         /* LAN queue/VSI allocation */
3801         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3802         if (!hw->func_caps.rss) {
3803                 pf->lan_nb_qps = 1;
3804         } else {
3805                 pf->flags |= I40E_FLAG_RSS;
3806                 if (hw->mac.type == I40E_MAC_X722)
3807                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3808                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3809         }
3810         qp_count += pf->lan_nb_qps;
3811         vsi_count += 1;
3812
3813         /* VF queue/VSI allocation */
3814         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3815         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3816                 pf->flags |= I40E_FLAG_SRIOV;
3817                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3818                 pf->vf_num = pci_dev->max_vfs;
3819                 PMD_DRV_LOG(DEBUG,
3820                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3821                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3822         } else {
3823                 pf->vf_nb_qps = 0;
3824                 pf->vf_num = 0;
3825         }
3826         qp_count += pf->vf_nb_qps * pf->vf_num;
3827         vsi_count += pf->vf_num;
3828
3829         /* VMDq queue/VSI allocation */
3830         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3831         pf->vmdq_nb_qps = 0;
3832         pf->max_nb_vmdq_vsi = 0;
3833         if (hw->func_caps.vmdq) {
3834                 if (qp_count < hw->func_caps.num_tx_qp &&
3835                         vsi_count < hw->func_caps.num_vsis) {
3836                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3837                                 qp_count) / pf->vmdq_nb_qp_max;
3838
3839                         /* Limit the maximum number of VMDq vsi to the maximum
3840                          * ethdev can support
3841                          */
3842                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3843                                 hw->func_caps.num_vsis - vsi_count);
3844                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3845                                 ETH_64_POOLS);
3846                         if (pf->max_nb_vmdq_vsi) {
3847                                 pf->flags |= I40E_FLAG_VMDQ;
3848                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3849                                 PMD_DRV_LOG(DEBUG,
3850                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3851                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3852                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3853                         } else {
3854                                 PMD_DRV_LOG(INFO,
3855                                         "No enough queues left for VMDq");
3856                         }
3857                 } else {
3858                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3859                 }
3860         }
3861         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3862         vsi_count += pf->max_nb_vmdq_vsi;
3863
3864         if (hw->func_caps.dcb)
3865                 pf->flags |= I40E_FLAG_DCB;
3866
3867         if (qp_count > hw->func_caps.num_tx_qp) {
3868                 PMD_DRV_LOG(ERR,
3869                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3870                         qp_count, hw->func_caps.num_tx_qp);
3871                 return -EINVAL;
3872         }
3873         if (vsi_count > hw->func_caps.num_vsis) {
3874                 PMD_DRV_LOG(ERR,
3875                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3876                         vsi_count, hw->func_caps.num_vsis);
3877                 return -EINVAL;
3878         }
3879
3880         return 0;
3881 }
3882
3883 static int
3884 i40e_pf_get_switch_config(struct i40e_pf *pf)
3885 {
3886         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3887         struct i40e_aqc_get_switch_config_resp *switch_config;
3888         struct i40e_aqc_switch_config_element_resp *element;
3889         uint16_t start_seid = 0, num_reported;
3890         int ret;
3891
3892         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3893                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3894         if (!switch_config) {
3895                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3896                 return -ENOMEM;
3897         }
3898
3899         /* Get the switch configurations */
3900         ret = i40e_aq_get_switch_config(hw, switch_config,
3901                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3902         if (ret != I40E_SUCCESS) {
3903                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3904                 goto fail;
3905         }
3906         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3907         if (num_reported != 1) { /* The number should be 1 */
3908                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3909                 goto fail;
3910         }
3911
3912         /* Parse the switch configuration elements */
3913         element = &(switch_config->element[0]);
3914         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3915                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3916                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3917         } else
3918                 PMD_DRV_LOG(INFO, "Unknown element type");
3919
3920 fail:
3921         rte_free(switch_config);
3922
3923         return ret;
3924 }
3925
3926 static int
3927 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3928                         uint32_t num)
3929 {
3930         struct pool_entry *entry;
3931
3932         if (pool == NULL || num == 0)
3933                 return -EINVAL;
3934
3935         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3936         if (entry == NULL) {
3937                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3938                 return -ENOMEM;
3939         }
3940
3941         /* queue heap initialize */
3942         pool->num_free = num;
3943         pool->num_alloc = 0;
3944         pool->base = base;
3945         LIST_INIT(&pool->alloc_list);
3946         LIST_INIT(&pool->free_list);
3947
3948         /* Initialize element  */
3949         entry->base = 0;
3950         entry->len = num;
3951
3952         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3953         return 0;
3954 }
3955
3956 static void
3957 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3958 {
3959         struct pool_entry *entry, *next_entry;
3960
3961         if (pool == NULL)
3962                 return;
3963
3964         for (entry = LIST_FIRST(&pool->alloc_list);
3965                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3966                         entry = next_entry) {
3967                 LIST_REMOVE(entry, next);
3968                 rte_free(entry);
3969         }
3970
3971         for (entry = LIST_FIRST(&pool->free_list);
3972                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3973                         entry = next_entry) {
3974                 LIST_REMOVE(entry, next);
3975                 rte_free(entry);
3976         }
3977
3978         pool->num_free = 0;
3979         pool->num_alloc = 0;
3980         pool->base = 0;
3981         LIST_INIT(&pool->alloc_list);
3982         LIST_INIT(&pool->free_list);
3983 }
3984
3985 static int
3986 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3987                        uint32_t base)
3988 {
3989         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3990         uint32_t pool_offset;
3991         int insert;
3992
3993         if (pool == NULL) {
3994                 PMD_DRV_LOG(ERR, "Invalid parameter");
3995                 return -EINVAL;
3996         }
3997
3998         pool_offset = base - pool->base;
3999         /* Lookup in alloc list */
4000         LIST_FOREACH(entry, &pool->alloc_list, next) {
4001                 if (entry->base == pool_offset) {
4002                         valid_entry = entry;
4003                         LIST_REMOVE(entry, next);
4004                         break;
4005                 }
4006         }
4007
4008         /* Not find, return */
4009         if (valid_entry == NULL) {
4010                 PMD_DRV_LOG(ERR, "Failed to find entry");
4011                 return -EINVAL;
4012         }
4013
4014         /**
4015          * Found it, move it to free list  and try to merge.
4016          * In order to make merge easier, always sort it by qbase.
4017          * Find adjacent prev and last entries.
4018          */
4019         prev = next = NULL;
4020         LIST_FOREACH(entry, &pool->free_list, next) {
4021                 if (entry->base > valid_entry->base) {
4022                         next = entry;
4023                         break;
4024                 }
4025                 prev = entry;
4026         }
4027
4028         insert = 0;
4029         /* Try to merge with next one*/
4030         if (next != NULL) {
4031                 /* Merge with next one */
4032                 if (valid_entry->base + valid_entry->len == next->base) {
4033                         next->base = valid_entry->base;
4034                         next->len += valid_entry->len;
4035                         rte_free(valid_entry);
4036                         valid_entry = next;
4037                         insert = 1;
4038                 }
4039         }
4040
4041         if (prev != NULL) {
4042                 /* Merge with previous one */
4043                 if (prev->base + prev->len == valid_entry->base) {
4044                         prev->len += valid_entry->len;
4045                         /* If it merge with next one, remove next node */
4046                         if (insert == 1) {
4047                                 LIST_REMOVE(valid_entry, next);
4048                                 rte_free(valid_entry);
4049                         } else {
4050                                 rte_free(valid_entry);
4051                                 insert = 1;
4052                         }
4053                 }
4054         }
4055
4056         /* Not find any entry to merge, insert */
4057         if (insert == 0) {
4058                 if (prev != NULL)
4059                         LIST_INSERT_AFTER(prev, valid_entry, next);
4060                 else if (next != NULL)
4061                         LIST_INSERT_BEFORE(next, valid_entry, next);
4062                 else /* It's empty list, insert to head */
4063                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4064         }
4065
4066         pool->num_free += valid_entry->len;
4067         pool->num_alloc -= valid_entry->len;
4068
4069         return 0;
4070 }
4071
4072 static int
4073 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4074                        uint16_t num)
4075 {
4076         struct pool_entry *entry, *valid_entry;
4077
4078         if (pool == NULL || num == 0) {
4079                 PMD_DRV_LOG(ERR, "Invalid parameter");
4080                 return -EINVAL;
4081         }
4082
4083         if (pool->num_free < num) {
4084                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4085                             num, pool->num_free);
4086                 return -ENOMEM;
4087         }
4088
4089         valid_entry = NULL;
4090         /* Lookup  in free list and find most fit one */
4091         LIST_FOREACH(entry, &pool->free_list, next) {
4092                 if (entry->len >= num) {
4093                         /* Find best one */
4094                         if (entry->len == num) {
4095                                 valid_entry = entry;
4096                                 break;
4097                         }
4098                         if (valid_entry == NULL || valid_entry->len > entry->len)
4099                                 valid_entry = entry;
4100                 }
4101         }
4102
4103         /* Not find one to satisfy the request, return */
4104         if (valid_entry == NULL) {
4105                 PMD_DRV_LOG(ERR, "No valid entry found");
4106                 return -ENOMEM;
4107         }
4108         /**
4109          * The entry have equal queue number as requested,
4110          * remove it from alloc_list.
4111          */
4112         if (valid_entry->len == num) {
4113                 LIST_REMOVE(valid_entry, next);
4114         } else {
4115                 /**
4116                  * The entry have more numbers than requested,
4117                  * create a new entry for alloc_list and minus its
4118                  * queue base and number in free_list.
4119                  */
4120                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4121                 if (entry == NULL) {
4122                         PMD_DRV_LOG(ERR,
4123                                 "Failed to allocate memory for resource pool");
4124                         return -ENOMEM;
4125                 }
4126                 entry->base = valid_entry->base;
4127                 entry->len = num;
4128                 valid_entry->base += num;
4129                 valid_entry->len -= num;
4130                 valid_entry = entry;
4131         }
4132
4133         /* Insert it into alloc list, not sorted */
4134         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4135
4136         pool->num_free -= valid_entry->len;
4137         pool->num_alloc += valid_entry->len;
4138
4139         return valid_entry->base + pool->base;
4140 }
4141
4142 /**
4143  * bitmap_is_subset - Check whether src2 is subset of src1
4144  **/
4145 static inline int
4146 bitmap_is_subset(uint8_t src1, uint8_t src2)
4147 {
4148         return !((src1 ^ src2) & src2);
4149 }
4150
4151 static enum i40e_status_code
4152 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4153 {
4154         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4155
4156         /* If DCB is not supported, only default TC is supported */
4157         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4158                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4159                 return I40E_NOT_SUPPORTED;
4160         }
4161
4162         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4163                 PMD_DRV_LOG(ERR,
4164                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4165                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4166                 return I40E_NOT_SUPPORTED;
4167         }
4168         return I40E_SUCCESS;
4169 }
4170
4171 int
4172 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4173                                 struct i40e_vsi_vlan_pvid_info *info)
4174 {
4175         struct i40e_hw *hw;
4176         struct i40e_vsi_context ctxt;
4177         uint8_t vlan_flags = 0;
4178         int ret;
4179
4180         if (vsi == NULL || info == NULL) {
4181                 PMD_DRV_LOG(ERR, "invalid parameters");
4182                 return I40E_ERR_PARAM;
4183         }
4184
4185         if (info->on) {
4186                 vsi->info.pvid = info->config.pvid;
4187                 /**
4188                  * If insert pvid is enabled, only tagged pkts are
4189                  * allowed to be sent out.
4190                  */
4191                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4192                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4193         } else {
4194                 vsi->info.pvid = 0;
4195                 if (info->config.reject.tagged == 0)
4196                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4197
4198                 if (info->config.reject.untagged == 0)
4199                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4200         }
4201         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4202                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4203         vsi->info.port_vlan_flags |= vlan_flags;
4204         vsi->info.valid_sections =
4205                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4206         memset(&ctxt, 0, sizeof(ctxt));
4207         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4208         ctxt.seid = vsi->seid;
4209
4210         hw = I40E_VSI_TO_HW(vsi);
4211         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4212         if (ret != I40E_SUCCESS)
4213                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4214
4215         return ret;
4216 }
4217
4218 static int
4219 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4220 {
4221         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4222         int i, ret;
4223         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4224
4225         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4226         if (ret != I40E_SUCCESS)
4227                 return ret;
4228
4229         if (!vsi->seid) {
4230                 PMD_DRV_LOG(ERR, "seid not valid");
4231                 return -EINVAL;
4232         }
4233
4234         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4235         tc_bw_data.tc_valid_bits = enabled_tcmap;
4236         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4237                 tc_bw_data.tc_bw_credits[i] =
4238                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4239
4240         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4241         if (ret != I40E_SUCCESS) {
4242                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4243                 return ret;
4244         }
4245
4246         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4247                                         sizeof(vsi->info.qs_handle));
4248         return I40E_SUCCESS;
4249 }
4250
4251 static enum i40e_status_code
4252 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4253                                  struct i40e_aqc_vsi_properties_data *info,
4254                                  uint8_t enabled_tcmap)
4255 {
4256         enum i40e_status_code ret;
4257         int i, total_tc = 0;
4258         uint16_t qpnum_per_tc, bsf, qp_idx;
4259
4260         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4261         if (ret != I40E_SUCCESS)
4262                 return ret;
4263
4264         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4265                 if (enabled_tcmap & (1 << i))
4266                         total_tc++;
4267         vsi->enabled_tc = enabled_tcmap;
4268
4269         /* Number of queues per enabled TC */
4270         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4271         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4272         bsf = rte_bsf32(qpnum_per_tc);
4273
4274         /* Adjust the queue number to actual queues that can be applied */
4275         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4276                 vsi->nb_qps = qpnum_per_tc * total_tc;
4277
4278         /**
4279          * Configure TC and queue mapping parameters, for enabled TC,
4280          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4281          * default queue will serve it.
4282          */
4283         qp_idx = 0;
4284         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4285                 if (vsi->enabled_tc & (1 << i)) {
4286                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4287                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4288                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4289                         qp_idx += qpnum_per_tc;
4290                 } else
4291                         info->tc_mapping[i] = 0;
4292         }
4293
4294         /* Associate queue number with VSI */
4295         if (vsi->type == I40E_VSI_SRIOV) {
4296                 info->mapping_flags |=
4297                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4298                 for (i = 0; i < vsi->nb_qps; i++)
4299                         info->queue_mapping[i] =
4300                                 rte_cpu_to_le_16(vsi->base_queue + i);
4301         } else {
4302                 info->mapping_flags |=
4303                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4304                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4305         }
4306         info->valid_sections |=
4307                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4308
4309         return I40E_SUCCESS;
4310 }
4311
4312 static int
4313 i40e_veb_release(struct i40e_veb *veb)
4314 {
4315         struct i40e_vsi *vsi;
4316         struct i40e_hw *hw;
4317
4318         if (veb == NULL)
4319                 return -EINVAL;
4320
4321         if (!TAILQ_EMPTY(&veb->head)) {
4322                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4323                 return -EACCES;
4324         }
4325         /* associate_vsi field is NULL for floating VEB */
4326         if (veb->associate_vsi != NULL) {
4327                 vsi = veb->associate_vsi;
4328                 hw = I40E_VSI_TO_HW(vsi);
4329
4330                 vsi->uplink_seid = veb->uplink_seid;
4331                 vsi->veb = NULL;
4332         } else {
4333                 veb->associate_pf->main_vsi->floating_veb = NULL;
4334                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4335         }
4336
4337         i40e_aq_delete_element(hw, veb->seid, NULL);
4338         rte_free(veb);
4339         return I40E_SUCCESS;
4340 }
4341
4342 /* Setup a veb */
4343 static struct i40e_veb *
4344 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4345 {
4346         struct i40e_veb *veb;
4347         int ret;
4348         struct i40e_hw *hw;
4349
4350         if (pf == NULL) {
4351                 PMD_DRV_LOG(ERR,
4352                             "veb setup failed, associated PF shouldn't null");
4353                 return NULL;
4354         }
4355         hw = I40E_PF_TO_HW(pf);
4356
4357         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4358         if (!veb) {
4359                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4360                 goto fail;
4361         }
4362
4363         veb->associate_vsi = vsi;
4364         veb->associate_pf = pf;
4365         TAILQ_INIT(&veb->head);
4366         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4367
4368         /* create floating veb if vsi is NULL */
4369         if (vsi != NULL) {
4370                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4371                                       I40E_DEFAULT_TCMAP, false,
4372                                       &veb->seid, false, NULL);
4373         } else {
4374                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4375                                       true, &veb->seid, false, NULL);
4376         }
4377
4378         if (ret != I40E_SUCCESS) {
4379                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4380                             hw->aq.asq_last_status);
4381                 goto fail;
4382         }
4383         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4384
4385         /* get statistics index */
4386         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4387                                 &veb->stats_idx, NULL, NULL, NULL);
4388         if (ret != I40E_SUCCESS) {
4389                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4390                             hw->aq.asq_last_status);
4391                 goto fail;
4392         }
4393         /* Get VEB bandwidth, to be implemented */
4394         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4395         if (vsi)
4396                 vsi->uplink_seid = veb->seid;
4397
4398         return veb;
4399 fail:
4400         rte_free(veb);
4401         return NULL;
4402 }
4403
4404 int
4405 i40e_vsi_release(struct i40e_vsi *vsi)
4406 {
4407         struct i40e_pf *pf;
4408         struct i40e_hw *hw;
4409         struct i40e_vsi_list *vsi_list;
4410         void *temp;
4411         int ret;
4412         struct i40e_mac_filter *f;
4413         uint16_t user_param;
4414
4415         if (!vsi)
4416                 return I40E_SUCCESS;
4417
4418         if (!vsi->adapter)
4419                 return -EFAULT;
4420
4421         user_param = vsi->user_param;
4422
4423         pf = I40E_VSI_TO_PF(vsi);
4424         hw = I40E_VSI_TO_HW(vsi);
4425
4426         /* VSI has child to attach, release child first */
4427         if (vsi->veb) {
4428                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4429                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4430                                 return -1;
4431                 }
4432                 i40e_veb_release(vsi->veb);
4433         }
4434
4435         if (vsi->floating_veb) {
4436                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4437                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4438                                 return -1;
4439                 }
4440         }
4441
4442         /* Remove all macvlan filters of the VSI */
4443         i40e_vsi_remove_all_macvlan_filter(vsi);
4444         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4445                 rte_free(f);
4446
4447         if (vsi->type != I40E_VSI_MAIN &&
4448             ((vsi->type != I40E_VSI_SRIOV) ||
4449             !pf->floating_veb_list[user_param])) {
4450                 /* Remove vsi from parent's sibling list */
4451                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4452                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4453                         return I40E_ERR_PARAM;
4454                 }
4455                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4456                                 &vsi->sib_vsi_list, list);
4457
4458                 /* Remove all switch element of the VSI */
4459                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4460                 if (ret != I40E_SUCCESS)
4461                         PMD_DRV_LOG(ERR, "Failed to delete element");
4462         }
4463
4464         if ((vsi->type == I40E_VSI_SRIOV) &&
4465             pf->floating_veb_list[user_param]) {
4466                 /* Remove vsi from parent's sibling list */
4467                 if (vsi->parent_vsi == NULL ||
4468                     vsi->parent_vsi->floating_veb == NULL) {
4469                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4470                         return I40E_ERR_PARAM;
4471                 }
4472                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4473                              &vsi->sib_vsi_list, list);
4474
4475                 /* Remove all switch element of the VSI */
4476                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4477                 if (ret != I40E_SUCCESS)
4478                         PMD_DRV_LOG(ERR, "Failed to delete element");
4479         }
4480
4481         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4482
4483         if (vsi->type != I40E_VSI_SRIOV)
4484                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4485         rte_free(vsi);
4486
4487         return I40E_SUCCESS;
4488 }
4489
4490 static int
4491 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4492 {
4493         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4494         struct i40e_aqc_remove_macvlan_element_data def_filter;
4495         struct i40e_mac_filter_info filter;
4496         int ret;
4497
4498         if (vsi->type != I40E_VSI_MAIN)
4499                 return I40E_ERR_CONFIG;
4500         memset(&def_filter, 0, sizeof(def_filter));
4501         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4502                                         ETH_ADDR_LEN);
4503         def_filter.vlan_tag = 0;
4504         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4505                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4506         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4507         if (ret != I40E_SUCCESS) {
4508                 struct i40e_mac_filter *f;
4509                 struct ether_addr *mac;
4510
4511                 PMD_DRV_LOG(DEBUG,
4512                             "Cannot remove the default macvlan filter");
4513                 /* It needs to add the permanent mac into mac list */
4514                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4515                 if (f == NULL) {
4516                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4517                         return I40E_ERR_NO_MEMORY;
4518                 }
4519                 mac = &f->mac_info.mac_addr;
4520                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4521                                 ETH_ADDR_LEN);
4522                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4523                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4524                 vsi->mac_num++;
4525
4526                 return ret;
4527         }
4528         (void)rte_memcpy(&filter.mac_addr,
4529                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4530         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4531         return i40e_vsi_add_mac(vsi, &filter);
4532 }
4533
4534 /*
4535  * i40e_vsi_get_bw_config - Query VSI BW Information
4536  * @vsi: the VSI to be queried
4537  *
4538  * Returns 0 on success, negative value on failure
4539  */
4540 static enum i40e_status_code
4541 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4542 {
4543         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4544         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4545         struct i40e_hw *hw = &vsi->adapter->hw;
4546         i40e_status ret;
4547         int i;
4548         uint32_t bw_max;
4549
4550         memset(&bw_config, 0, sizeof(bw_config));
4551         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4552         if (ret != I40E_SUCCESS) {
4553                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4554                             hw->aq.asq_last_status);
4555                 return ret;
4556         }
4557
4558         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4559         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4560                                         &ets_sla_config, NULL);
4561         if (ret != I40E_SUCCESS) {
4562                 PMD_DRV_LOG(ERR,
4563                         "VSI failed to get TC bandwdith configuration %u",
4564                         hw->aq.asq_last_status);
4565                 return ret;
4566         }
4567
4568         /* store and print out BW info */
4569         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4570         vsi->bw_info.bw_max = bw_config.max_bw;
4571         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4572         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4573         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4574                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4575                      I40E_16_BIT_WIDTH);
4576         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4577                 vsi->bw_info.bw_ets_share_credits[i] =
4578                                 ets_sla_config.share_credits[i];
4579                 vsi->bw_info.bw_ets_credits[i] =
4580                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4581                 /* 4 bits per TC, 4th bit is reserved */
4582                 vsi->bw_info.bw_ets_max[i] =
4583                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4584                                   RTE_LEN2MASK(3, uint8_t));
4585                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4586                             vsi->bw_info.bw_ets_share_credits[i]);
4587                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4588                             vsi->bw_info.bw_ets_credits[i]);
4589                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4590                             vsi->bw_info.bw_ets_max[i]);
4591         }
4592
4593         return I40E_SUCCESS;
4594 }
4595
4596 /* i40e_enable_pf_lb
4597  * @pf: pointer to the pf structure
4598  *
4599  * allow loopback on pf
4600  */
4601 static inline void
4602 i40e_enable_pf_lb(struct i40e_pf *pf)
4603 {
4604         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4605         struct i40e_vsi_context ctxt;
4606         int ret;
4607
4608         /* Use the FW API if FW >= v5.0 */
4609         if (hw->aq.fw_maj_ver < 5) {
4610                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4611                 return;
4612         }
4613
4614         memset(&ctxt, 0, sizeof(ctxt));
4615         ctxt.seid = pf->main_vsi_seid;
4616         ctxt.pf_num = hw->pf_id;
4617         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4618         if (ret) {
4619                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4620                             ret, hw->aq.asq_last_status);
4621                 return;
4622         }
4623         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4624         ctxt.info.valid_sections =
4625                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4626         ctxt.info.switch_id |=
4627                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4628
4629         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4630         if (ret)
4631                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4632                             hw->aq.asq_last_status);
4633 }
4634
4635 /* Setup a VSI */
4636 struct i40e_vsi *
4637 i40e_vsi_setup(struct i40e_pf *pf,
4638                enum i40e_vsi_type type,
4639                struct i40e_vsi *uplink_vsi,
4640                uint16_t user_param)
4641 {
4642         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4643         struct i40e_vsi *vsi;
4644         struct i40e_mac_filter_info filter;
4645         int ret;
4646         struct i40e_vsi_context ctxt;
4647         struct ether_addr broadcast =
4648                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4649
4650         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4651             uplink_vsi == NULL) {
4652                 PMD_DRV_LOG(ERR,
4653                         "VSI setup failed, VSI link shouldn't be NULL");
4654                 return NULL;
4655         }
4656
4657         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4658                 PMD_DRV_LOG(ERR,
4659                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4660                 return NULL;
4661         }
4662
4663         /* two situations
4664          * 1.type is not MAIN and uplink vsi is not NULL
4665          * If uplink vsi didn't setup VEB, create one first under veb field
4666          * 2.type is SRIOV and the uplink is NULL
4667          * If floating VEB is NULL, create one veb under floating veb field
4668          */
4669
4670         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4671             uplink_vsi->veb == NULL) {
4672                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4673
4674                 if (uplink_vsi->veb == NULL) {
4675                         PMD_DRV_LOG(ERR, "VEB setup failed");
4676                         return NULL;
4677                 }
4678                 /* set ALLOWLOOPBACk on pf, when veb is created */
4679                 i40e_enable_pf_lb(pf);
4680         }
4681
4682         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4683             pf->main_vsi->floating_veb == NULL) {
4684                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4685
4686                 if (pf->main_vsi->floating_veb == NULL) {
4687                         PMD_DRV_LOG(ERR, "VEB setup failed");
4688                         return NULL;
4689                 }
4690         }
4691
4692         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4693         if (!vsi) {
4694                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4695                 return NULL;
4696         }
4697         TAILQ_INIT(&vsi->mac_list);
4698         vsi->type = type;
4699         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4700         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4701         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4702         vsi->user_param = user_param;
4703         vsi->vlan_anti_spoof_on = 0;
4704         vsi->vlan_filter_on = 0;
4705         /* Allocate queues */
4706         switch (vsi->type) {
4707         case I40E_VSI_MAIN  :
4708                 vsi->nb_qps = pf->lan_nb_qps;
4709                 break;
4710         case I40E_VSI_SRIOV :
4711                 vsi->nb_qps = pf->vf_nb_qps;
4712                 break;
4713         case I40E_VSI_VMDQ2:
4714                 vsi->nb_qps = pf->vmdq_nb_qps;
4715                 break;
4716         case I40E_VSI_FDIR:
4717                 vsi->nb_qps = pf->fdir_nb_qps;
4718                 break;
4719         default:
4720                 goto fail_mem;
4721         }
4722         /*
4723          * The filter status descriptor is reported in rx queue 0,
4724          * while the tx queue for fdir filter programming has no
4725          * such constraints, can be non-zero queues.
4726          * To simplify it, choose FDIR vsi use queue 0 pair.
4727          * To make sure it will use queue 0 pair, queue allocation
4728          * need be done before this function is called
4729          */
4730         if (type != I40E_VSI_FDIR) {
4731                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4732                         if (ret < 0) {
4733                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4734                                                 vsi->seid, ret);
4735                                 goto fail_mem;
4736                         }
4737                         vsi->base_queue = ret;
4738         } else
4739                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4740
4741         /* VF has MSIX interrupt in VF range, don't allocate here */
4742         if (type == I40E_VSI_MAIN) {
4743                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4744                                           RTE_MIN(vsi->nb_qps,
4745                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4746                 if (ret < 0) {
4747                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4748                                     vsi->seid, ret);
4749                         goto fail_queue_alloc;
4750                 }
4751                 vsi->msix_intr = ret;
4752                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4753         } else if (type != I40E_VSI_SRIOV) {
4754                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4755                 if (ret < 0) {
4756                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4757                         goto fail_queue_alloc;
4758                 }
4759                 vsi->msix_intr = ret;
4760                 vsi->nb_msix = 1;
4761         } else {
4762                 vsi->msix_intr = 0;
4763                 vsi->nb_msix = 0;
4764         }
4765
4766         /* Add VSI */
4767         if (type == I40E_VSI_MAIN) {
4768                 /* For main VSI, no need to add since it's default one */
4769                 vsi->uplink_seid = pf->mac_seid;
4770                 vsi->seid = pf->main_vsi_seid;
4771                 /* Bind queues with specific MSIX interrupt */
4772                 /**
4773                  * Needs 2 interrupt at least, one for misc cause which will
4774                  * enabled from OS side, Another for queues binding the
4775                  * interrupt from device side only.
4776                  */
4777
4778                 /* Get default VSI parameters from hardware */
4779                 memset(&ctxt, 0, sizeof(ctxt));
4780                 ctxt.seid = vsi->seid;
4781                 ctxt.pf_num = hw->pf_id;
4782                 ctxt.uplink_seid = vsi->uplink_seid;
4783                 ctxt.vf_num = 0;
4784                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4785                 if (ret != I40E_SUCCESS) {
4786                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4787                         goto fail_msix_alloc;
4788                 }
4789                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4790                         sizeof(struct i40e_aqc_vsi_properties_data));
4791                 vsi->vsi_id = ctxt.vsi_number;
4792                 vsi->info.valid_sections = 0;
4793
4794                 /* Configure tc, enabled TC0 only */
4795                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4796                         I40E_SUCCESS) {
4797                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4798                         goto fail_msix_alloc;
4799                 }
4800
4801                 /* TC, queue mapping */
4802                 memset(&ctxt, 0, sizeof(ctxt));
4803                 vsi->info.valid_sections |=
4804                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4805                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4806                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4807                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4808                         sizeof(struct i40e_aqc_vsi_properties_data));
4809                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4810                                                 I40E_DEFAULT_TCMAP);
4811                 if (ret != I40E_SUCCESS) {
4812                         PMD_DRV_LOG(ERR,
4813                                 "Failed to configure TC queue mapping");
4814                         goto fail_msix_alloc;
4815                 }
4816                 ctxt.seid = vsi->seid;
4817                 ctxt.pf_num = hw->pf_id;
4818                 ctxt.uplink_seid = vsi->uplink_seid;
4819                 ctxt.vf_num = 0;
4820
4821                 /* Update VSI parameters */
4822                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4823                 if (ret != I40E_SUCCESS) {
4824                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4825                         goto fail_msix_alloc;
4826                 }
4827
4828                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4829                                                 sizeof(vsi->info.tc_mapping));
4830                 (void)rte_memcpy(&vsi->info.queue_mapping,
4831                                 &ctxt.info.queue_mapping,
4832                         sizeof(vsi->info.queue_mapping));
4833                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4834                 vsi->info.valid_sections = 0;
4835
4836                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4837                                 ETH_ADDR_LEN);
4838
4839                 /**
4840                  * Updating default filter settings are necessary to prevent
4841                  * reception of tagged packets.
4842                  * Some old firmware configurations load a default macvlan
4843                  * filter which accepts both tagged and untagged packets.
4844                  * The updating is to use a normal filter instead if needed.
4845                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4846                  * The firmware with correct configurations load the default
4847                  * macvlan filter which is expected and cannot be removed.
4848                  */
4849                 i40e_update_default_filter_setting(vsi);
4850                 i40e_config_qinq(hw, vsi);
4851         } else if (type == I40E_VSI_SRIOV) {
4852                 memset(&ctxt, 0, sizeof(ctxt));
4853                 /**
4854                  * For other VSI, the uplink_seid equals to uplink VSI's
4855                  * uplink_seid since they share same VEB
4856                  */
4857                 if (uplink_vsi == NULL)
4858                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4859                 else
4860                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4861                 ctxt.pf_num = hw->pf_id;
4862                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4863                 ctxt.uplink_seid = vsi->uplink_seid;
4864                 ctxt.connection_type = 0x1;
4865                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4866
4867                 /* Use the VEB configuration if FW >= v5.0 */
4868                 if (hw->aq.fw_maj_ver >= 5) {
4869                         /* Configure switch ID */
4870                         ctxt.info.valid_sections |=
4871                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4872                         ctxt.info.switch_id =
4873                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4874                 }
4875
4876                 /* Configure port/vlan */
4877                 ctxt.info.valid_sections |=
4878                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4879                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4880                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4881                                                 hw->func_caps.enabled_tcmap);
4882                 if (ret != I40E_SUCCESS) {
4883                         PMD_DRV_LOG(ERR,
4884                                 "Failed to configure TC queue mapping");
4885                         goto fail_msix_alloc;
4886                 }
4887
4888                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4889                 ctxt.info.valid_sections |=
4890                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4891                 /**
4892                  * Since VSI is not created yet, only configure parameter,
4893                  * will add vsi below.
4894                  */
4895
4896                 i40e_config_qinq(hw, vsi);
4897         } else if (type == I40E_VSI_VMDQ2) {
4898                 memset(&ctxt, 0, sizeof(ctxt));
4899                 /*
4900                  * For other VSI, the uplink_seid equals to uplink VSI's
4901                  * uplink_seid since they share same VEB
4902                  */
4903                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4904                 ctxt.pf_num = hw->pf_id;
4905                 ctxt.vf_num = 0;
4906                 ctxt.uplink_seid = vsi->uplink_seid;
4907                 ctxt.connection_type = 0x1;
4908                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4909
4910                 ctxt.info.valid_sections |=
4911                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4912                 /* user_param carries flag to enable loop back */
4913                 if (user_param) {
4914                         ctxt.info.switch_id =
4915                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4916                         ctxt.info.switch_id |=
4917                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4918                 }
4919
4920                 /* Configure port/vlan */
4921                 ctxt.info.valid_sections |=
4922                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4923                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4924                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4925                                                 I40E_DEFAULT_TCMAP);
4926                 if (ret != I40E_SUCCESS) {
4927                         PMD_DRV_LOG(ERR,
4928                                 "Failed to configure TC queue mapping");
4929                         goto fail_msix_alloc;
4930                 }
4931                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4932                 ctxt.info.valid_sections |=
4933                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4934         } else if (type == I40E_VSI_FDIR) {
4935                 memset(&ctxt, 0, sizeof(ctxt));
4936                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4937                 ctxt.pf_num = hw->pf_id;
4938                 ctxt.vf_num = 0;
4939                 ctxt.uplink_seid = vsi->uplink_seid;
4940                 ctxt.connection_type = 0x1;     /* regular data port */
4941                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4942                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4943                                                 I40E_DEFAULT_TCMAP);
4944                 if (ret != I40E_SUCCESS) {
4945                         PMD_DRV_LOG(ERR,
4946                                 "Failed to configure TC queue mapping.");
4947                         goto fail_msix_alloc;
4948                 }
4949                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4950                 ctxt.info.valid_sections |=
4951                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4952         } else {
4953                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4954                 goto fail_msix_alloc;
4955         }
4956
4957         if (vsi->type != I40E_VSI_MAIN) {
4958                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4959                 if (ret != I40E_SUCCESS) {
4960                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4961                                     hw->aq.asq_last_status);
4962                         goto fail_msix_alloc;
4963                 }
4964                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4965                 vsi->info.valid_sections = 0;
4966                 vsi->seid = ctxt.seid;
4967                 vsi->vsi_id = ctxt.vsi_number;
4968                 vsi->sib_vsi_list.vsi = vsi;
4969                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4970                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4971                                           &vsi->sib_vsi_list, list);
4972                 } else {
4973                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4974                                           &vsi->sib_vsi_list, list);
4975                 }
4976         }
4977
4978         /* MAC/VLAN configuration */
4979         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4980         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4981
4982         ret = i40e_vsi_add_mac(vsi, &filter);
4983         if (ret != I40E_SUCCESS) {
4984                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4985                 goto fail_msix_alloc;
4986         }
4987
4988         /* Get VSI BW information */
4989         i40e_vsi_get_bw_config(vsi);
4990         return vsi;
4991 fail_msix_alloc:
4992         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4993 fail_queue_alloc:
4994         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4995 fail_mem:
4996         rte_free(vsi);
4997         return NULL;
4998 }
4999
5000 /* Configure vlan filter on or off */
5001 int
5002 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5003 {
5004         int i, num;
5005         struct i40e_mac_filter *f;
5006         void *temp;
5007         struct i40e_mac_filter_info *mac_filter;
5008         enum rte_mac_filter_type desired_filter;
5009         int ret = I40E_SUCCESS;
5010
5011         if (on) {
5012                 /* Filter to match MAC and VLAN */
5013                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5014         } else {
5015                 /* Filter to match only MAC */
5016                 desired_filter = RTE_MAC_PERFECT_MATCH;
5017         }
5018
5019         num = vsi->mac_num;
5020
5021         mac_filter = rte_zmalloc("mac_filter_info_data",
5022                                  num * sizeof(*mac_filter), 0);
5023         if (mac_filter == NULL) {
5024                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5025                 return I40E_ERR_NO_MEMORY;
5026         }
5027
5028         i = 0;
5029
5030         /* Remove all existing mac */
5031         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5032                 mac_filter[i] = f->mac_info;
5033                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5034                 if (ret) {
5035                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5036                                     on ? "enable" : "disable");
5037                         goto DONE;
5038                 }
5039                 i++;
5040         }
5041
5042         /* Override with new filter */
5043         for (i = 0; i < num; i++) {
5044                 mac_filter[i].filter_type = desired_filter;
5045                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5046                 if (ret) {
5047                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5048                                     on ? "enable" : "disable");
5049                         goto DONE;
5050                 }
5051         }
5052
5053 DONE:
5054         rte_free(mac_filter);
5055         return ret;
5056 }
5057
5058 /* Configure vlan stripping on or off */
5059 int
5060 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5061 {
5062         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5063         struct i40e_vsi_context ctxt;
5064         uint8_t vlan_flags;
5065         int ret = I40E_SUCCESS;
5066
5067         /* Check if it has been already on or off */
5068         if (vsi->info.valid_sections &
5069                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5070                 if (on) {
5071                         if ((vsi->info.port_vlan_flags &
5072                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5073                                 return 0; /* already on */
5074                 } else {
5075                         if ((vsi->info.port_vlan_flags &
5076                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5077                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5078                                 return 0; /* already off */
5079                 }
5080         }
5081
5082         if (on)
5083                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5084         else
5085                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5086         vsi->info.valid_sections =
5087                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5088         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5089         vsi->info.port_vlan_flags |= vlan_flags;
5090         ctxt.seid = vsi->seid;
5091         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5092         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5093         if (ret)
5094                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5095                             on ? "enable" : "disable");
5096
5097         return ret;
5098 }
5099
5100 static int
5101 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5102 {
5103         struct rte_eth_dev_data *data = dev->data;
5104         int ret;
5105         int mask = 0;
5106
5107         /* Apply vlan offload setting */
5108         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5109         i40e_vlan_offload_set(dev, mask);
5110
5111         /* Apply double-vlan setting, not implemented yet */
5112
5113         /* Apply pvid setting */
5114         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5115                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5116         if (ret)
5117                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5118
5119         return ret;
5120 }
5121
5122 static int
5123 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5124 {
5125         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5126
5127         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5128 }
5129
5130 static int
5131 i40e_update_flow_control(struct i40e_hw *hw)
5132 {
5133 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5134         struct i40e_link_status link_status;
5135         uint32_t rxfc = 0, txfc = 0, reg;
5136         uint8_t an_info;
5137         int ret;
5138
5139         memset(&link_status, 0, sizeof(link_status));
5140         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5141         if (ret != I40E_SUCCESS) {
5142                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5143                 goto write_reg; /* Disable flow control */
5144         }
5145
5146         an_info = hw->phy.link_info.an_info;
5147         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5148                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5149                 ret = I40E_ERR_NOT_READY;
5150                 goto write_reg; /* Disable flow control */
5151         }
5152         /**
5153          * If link auto negotiation is enabled, flow control needs to
5154          * be configured according to it
5155          */
5156         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5157         case I40E_LINK_PAUSE_RXTX:
5158                 rxfc = 1;
5159                 txfc = 1;
5160                 hw->fc.current_mode = I40E_FC_FULL;
5161                 break;
5162         case I40E_AQ_LINK_PAUSE_RX:
5163                 rxfc = 1;
5164                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5165                 break;
5166         case I40E_AQ_LINK_PAUSE_TX:
5167                 txfc = 1;
5168                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5169                 break;
5170         default:
5171                 hw->fc.current_mode = I40E_FC_NONE;
5172                 break;
5173         }
5174
5175 write_reg:
5176         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5177                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5178         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5179         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5180         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5181         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5182
5183         return ret;
5184 }
5185
5186 /* PF setup */
5187 static int
5188 i40e_pf_setup(struct i40e_pf *pf)
5189 {
5190         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5191         struct i40e_filter_control_settings settings;
5192         struct i40e_vsi *vsi;
5193         int ret;
5194
5195         /* Clear all stats counters */
5196         pf->offset_loaded = FALSE;
5197         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5198         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5199
5200         ret = i40e_pf_get_switch_config(pf);
5201         if (ret != I40E_SUCCESS) {
5202                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5203                 return ret;
5204         }
5205         if (pf->flags & I40E_FLAG_FDIR) {
5206                 /* make queue allocated first, let FDIR use queue pair 0*/
5207                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5208                 if (ret != I40E_FDIR_QUEUE_ID) {
5209                         PMD_DRV_LOG(ERR,
5210                                 "queue allocation fails for FDIR: ret =%d",
5211                                 ret);
5212                         pf->flags &= ~I40E_FLAG_FDIR;
5213                 }
5214         }
5215         /*  main VSI setup */
5216         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5217         if (!vsi) {
5218                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5219                 return I40E_ERR_NOT_READY;
5220         }
5221         pf->main_vsi = vsi;
5222
5223         /* Configure filter control */
5224         memset(&settings, 0, sizeof(settings));
5225         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5226                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5227         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5228                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5229         else {
5230                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5231                         hw->func_caps.rss_table_size);
5232                 return I40E_ERR_PARAM;
5233         }
5234         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5235                 hw->func_caps.rss_table_size);
5236         pf->hash_lut_size = hw->func_caps.rss_table_size;
5237
5238         /* Enable ethtype and macvlan filters */
5239         settings.enable_ethtype = TRUE;
5240         settings.enable_macvlan = TRUE;
5241         ret = i40e_set_filter_control(hw, &settings);
5242         if (ret)
5243                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5244                                                                 ret);
5245
5246         /* Update flow control according to the auto negotiation */
5247         i40e_update_flow_control(hw);
5248
5249         return I40E_SUCCESS;
5250 }
5251
5252 int
5253 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5254 {
5255         uint32_t reg;
5256         uint16_t j;
5257
5258         /**
5259          * Set or clear TX Queue Disable flags,
5260          * which is required by hardware.
5261          */
5262         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5263         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5264
5265         /* Wait until the request is finished */
5266         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5267                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5268                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5269                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5270                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5271                                                         & 0x1))) {
5272                         break;
5273                 }
5274         }
5275         if (on) {
5276                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5277                         return I40E_SUCCESS; /* already on, skip next steps */
5278
5279                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5280                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5281         } else {
5282                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5283                         return I40E_SUCCESS; /* already off, skip next steps */
5284                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5285         }
5286         /* Write the register */
5287         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5288         /* Check the result */
5289         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5290                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5291                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5292                 if (on) {
5293                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5294                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5295                                 break;
5296                 } else {
5297                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5298                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5299                                 break;
5300                 }
5301         }
5302         /* Check if it is timeout */
5303         if (j >= I40E_CHK_Q_ENA_COUNT) {
5304                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5305                             (on ? "enable" : "disable"), q_idx);
5306                 return I40E_ERR_TIMEOUT;
5307         }
5308
5309         return I40E_SUCCESS;
5310 }
5311
5312 /* Swith on or off the tx queues */
5313 static int
5314 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5315 {
5316         struct rte_eth_dev_data *dev_data = pf->dev_data;
5317         struct i40e_tx_queue *txq;
5318         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5319         uint16_t i;
5320         int ret;
5321
5322         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5323                 txq = dev_data->tx_queues[i];
5324                 /* Don't operate the queue if not configured or
5325                  * if starting only per queue */
5326                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5327                         continue;
5328                 if (on)
5329                         ret = i40e_dev_tx_queue_start(dev, i);
5330                 else
5331                         ret = i40e_dev_tx_queue_stop(dev, i);
5332                 if ( ret != I40E_SUCCESS)
5333                         return ret;
5334         }
5335
5336         return I40E_SUCCESS;
5337 }
5338
5339 int
5340 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5341 {
5342         uint32_t reg;
5343         uint16_t j;
5344
5345         /* Wait until the request is finished */
5346         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5347                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5348                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5349                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5350                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5351                         break;
5352         }
5353
5354         if (on) {
5355                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5356                         return I40E_SUCCESS; /* Already on, skip next steps */
5357                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5358         } else {
5359                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5360                         return I40E_SUCCESS; /* Already off, skip next steps */
5361                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5362         }
5363
5364         /* Write the register */
5365         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5366         /* Check the result */
5367         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5368                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5369                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5370                 if (on) {
5371                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5372                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5373                                 break;
5374                 } else {
5375                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5376                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5377                                 break;
5378                 }
5379         }
5380
5381         /* Check if it is timeout */
5382         if (j >= I40E_CHK_Q_ENA_COUNT) {
5383                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5384                             (on ? "enable" : "disable"), q_idx);
5385                 return I40E_ERR_TIMEOUT;
5386         }
5387
5388         return I40E_SUCCESS;
5389 }
5390 /* Switch on or off the rx queues */
5391 static int
5392 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5393 {
5394         struct rte_eth_dev_data *dev_data = pf->dev_data;
5395         struct i40e_rx_queue *rxq;
5396         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5397         uint16_t i;
5398         int ret;
5399
5400         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5401                 rxq = dev_data->rx_queues[i];
5402                 /* Don't operate the queue if not configured or
5403                  * if starting only per queue */
5404                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5405                         continue;
5406                 if (on)
5407                         ret = i40e_dev_rx_queue_start(dev, i);
5408                 else
5409                         ret = i40e_dev_rx_queue_stop(dev, i);
5410                 if (ret != I40E_SUCCESS)
5411                         return ret;
5412         }
5413
5414         return I40E_SUCCESS;
5415 }
5416
5417 /* Switch on or off all the rx/tx queues */
5418 int
5419 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5420 {
5421         int ret;
5422
5423         if (on) {
5424                 /* enable rx queues before enabling tx queues */
5425                 ret = i40e_dev_switch_rx_queues(pf, on);
5426                 if (ret) {
5427                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5428                         return ret;
5429                 }
5430                 ret = i40e_dev_switch_tx_queues(pf, on);
5431         } else {
5432                 /* Stop tx queues before stopping rx queues */
5433                 ret = i40e_dev_switch_tx_queues(pf, on);
5434                 if (ret) {
5435                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5436                         return ret;
5437                 }
5438                 ret = i40e_dev_switch_rx_queues(pf, on);
5439         }
5440
5441         return ret;
5442 }
5443
5444 /* Initialize VSI for TX */
5445 static int
5446 i40e_dev_tx_init(struct i40e_pf *pf)
5447 {
5448         struct rte_eth_dev_data *data = pf->dev_data;
5449         uint16_t i;
5450         uint32_t ret = I40E_SUCCESS;
5451         struct i40e_tx_queue *txq;
5452
5453         for (i = 0; i < data->nb_tx_queues; i++) {
5454                 txq = data->tx_queues[i];
5455                 if (!txq || !txq->q_set)
5456                         continue;
5457                 ret = i40e_tx_queue_init(txq);
5458                 if (ret != I40E_SUCCESS)
5459                         break;
5460         }
5461         if (ret == I40E_SUCCESS)
5462                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5463                                      ->eth_dev);
5464
5465         return ret;
5466 }
5467
5468 /* Initialize VSI for RX */
5469 static int
5470 i40e_dev_rx_init(struct i40e_pf *pf)
5471 {
5472         struct rte_eth_dev_data *data = pf->dev_data;
5473         int ret = I40E_SUCCESS;
5474         uint16_t i;
5475         struct i40e_rx_queue *rxq;
5476
5477         i40e_pf_config_mq_rx(pf);
5478         for (i = 0; i < data->nb_rx_queues; i++) {
5479                 rxq = data->rx_queues[i];
5480                 if (!rxq || !rxq->q_set)
5481                         continue;
5482
5483                 ret = i40e_rx_queue_init(rxq);
5484                 if (ret != I40E_SUCCESS) {
5485                         PMD_DRV_LOG(ERR,
5486                                 "Failed to do RX queue initialization");
5487                         break;
5488                 }
5489         }
5490         if (ret == I40E_SUCCESS)
5491                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5492                                      ->eth_dev);
5493
5494         return ret;
5495 }
5496
5497 static int
5498 i40e_dev_rxtx_init(struct i40e_pf *pf)
5499 {
5500         int err;
5501
5502         err = i40e_dev_tx_init(pf);
5503         if (err) {
5504                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5505                 return err;
5506         }
5507         err = i40e_dev_rx_init(pf);
5508         if (err) {
5509                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5510                 return err;
5511         }
5512
5513         return err;
5514 }
5515
5516 static int
5517 i40e_vmdq_setup(struct rte_eth_dev *dev)
5518 {
5519         struct rte_eth_conf *conf = &dev->data->dev_conf;
5520         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5521         int i, err, conf_vsis, j, loop;
5522         struct i40e_vsi *vsi;
5523         struct i40e_vmdq_info *vmdq_info;
5524         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5525         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5526
5527         /*
5528          * Disable interrupt to avoid message from VF. Furthermore, it will
5529          * avoid race condition in VSI creation/destroy.
5530          */
5531         i40e_pf_disable_irq0(hw);
5532
5533         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5534                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5535                 return -ENOTSUP;
5536         }
5537
5538         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5539         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5540                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5541                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5542                         pf->max_nb_vmdq_vsi);
5543                 return -ENOTSUP;
5544         }
5545
5546         if (pf->vmdq != NULL) {
5547                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5548                 return 0;
5549         }
5550
5551         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5552                                 sizeof(*vmdq_info) * conf_vsis, 0);
5553
5554         if (pf->vmdq == NULL) {
5555                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5556                 return -ENOMEM;
5557         }
5558
5559         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5560
5561         /* Create VMDQ VSI */
5562         for (i = 0; i < conf_vsis; i++) {
5563                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5564                                 vmdq_conf->enable_loop_back);
5565                 if (vsi == NULL) {
5566                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5567                         err = -1;
5568                         goto err_vsi_setup;
5569                 }
5570                 vmdq_info = &pf->vmdq[i];
5571                 vmdq_info->pf = pf;
5572                 vmdq_info->vsi = vsi;
5573         }
5574         pf->nb_cfg_vmdq_vsi = conf_vsis;
5575
5576         /* Configure Vlan */
5577         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5578         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5579                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5580                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5581                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5582                                         vmdq_conf->pool_map[i].vlan_id, j);
5583
5584                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5585                                                 vmdq_conf->pool_map[i].vlan_id);
5586                                 if (err) {
5587                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5588                                         err = -1;
5589                                         goto err_vsi_setup;
5590                                 }
5591                         }
5592                 }
5593         }
5594
5595         i40e_pf_enable_irq0(hw);
5596
5597         return 0;
5598
5599 err_vsi_setup:
5600         for (i = 0; i < conf_vsis; i++)
5601                 if (pf->vmdq[i].vsi == NULL)
5602                         break;
5603                 else
5604                         i40e_vsi_release(pf->vmdq[i].vsi);
5605
5606         rte_free(pf->vmdq);
5607         pf->vmdq = NULL;
5608         i40e_pf_enable_irq0(hw);
5609         return err;
5610 }
5611
5612 static void
5613 i40e_stat_update_32(struct i40e_hw *hw,
5614                    uint32_t reg,
5615                    bool offset_loaded,
5616                    uint64_t *offset,
5617                    uint64_t *stat)
5618 {
5619         uint64_t new_data;
5620
5621         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5622         if (!offset_loaded)
5623                 *offset = new_data;
5624
5625         if (new_data >= *offset)
5626                 *stat = (uint64_t)(new_data - *offset);
5627         else
5628                 *stat = (uint64_t)((new_data +
5629                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5630 }
5631
5632 static void
5633 i40e_stat_update_48(struct i40e_hw *hw,
5634                    uint32_t hireg,
5635                    uint32_t loreg,
5636                    bool offset_loaded,
5637                    uint64_t *offset,
5638                    uint64_t *stat)
5639 {
5640         uint64_t new_data;
5641
5642         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5643         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5644                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5645
5646         if (!offset_loaded)
5647                 *offset = new_data;
5648
5649         if (new_data >= *offset)
5650                 *stat = new_data - *offset;
5651         else
5652                 *stat = (uint64_t)((new_data +
5653                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5654
5655         *stat &= I40E_48_BIT_MASK;
5656 }
5657
5658 /* Disable IRQ0 */
5659 void
5660 i40e_pf_disable_irq0(struct i40e_hw *hw)
5661 {
5662         /* Disable all interrupt types */
5663         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5664         I40E_WRITE_FLUSH(hw);
5665 }
5666
5667 /* Enable IRQ0 */
5668 void
5669 i40e_pf_enable_irq0(struct i40e_hw *hw)
5670 {
5671         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5672                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5673                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5674                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5675         I40E_WRITE_FLUSH(hw);
5676 }
5677
5678 static void
5679 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5680 {
5681         /* read pending request and disable first */
5682         i40e_pf_disable_irq0(hw);
5683         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5684         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5685                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5686
5687         if (no_queue)
5688                 /* Link no queues with irq0 */
5689                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5690                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5691 }
5692
5693 static void
5694 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5695 {
5696         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5698         int i;
5699         uint16_t abs_vf_id;
5700         uint32_t index, offset, val;
5701
5702         if (!pf->vfs)
5703                 return;
5704         /**
5705          * Try to find which VF trigger a reset, use absolute VF id to access
5706          * since the reg is global register.
5707          */
5708         for (i = 0; i < pf->vf_num; i++) {
5709                 abs_vf_id = hw->func_caps.vf_base_id + i;
5710                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5711                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5712                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5713                 /* VFR event occured */
5714                 if (val & (0x1 << offset)) {
5715                         int ret;
5716
5717                         /* Clear the event first */
5718                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5719                                                         (0x1 << offset));
5720                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5721                         /**
5722                          * Only notify a VF reset event occured,
5723                          * don't trigger another SW reset
5724                          */
5725                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5726                         if (ret != I40E_SUCCESS)
5727                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5728                 }
5729         }
5730 }
5731
5732 static void
5733 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5734 {
5735         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5736         int i;
5737
5738         for (i = 0; i < pf->vf_num; i++)
5739                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5740 }
5741
5742 static void
5743 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5744 {
5745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         struct i40e_arq_event_info info;
5747         uint16_t pending, opcode;
5748         int ret;
5749
5750         info.buf_len = I40E_AQ_BUF_SZ;
5751         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5752         if (!info.msg_buf) {
5753                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5754                 return;
5755         }
5756
5757         pending = 1;
5758         while (pending) {
5759                 ret = i40e_clean_arq_element(hw, &info, &pending);
5760
5761                 if (ret != I40E_SUCCESS) {
5762                         PMD_DRV_LOG(INFO,
5763                                 "Failed to read msg from AdminQ, aq_err: %u",
5764                                 hw->aq.asq_last_status);
5765                         break;
5766                 }
5767                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5768
5769                 switch (opcode) {
5770                 case i40e_aqc_opc_send_msg_to_pf:
5771                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5772                         i40e_pf_host_handle_vf_msg(dev,
5773                                         rte_le_to_cpu_16(info.desc.retval),
5774                                         rte_le_to_cpu_32(info.desc.cookie_high),
5775                                         rte_le_to_cpu_32(info.desc.cookie_low),
5776                                         info.msg_buf,
5777                                         info.msg_len);
5778                         break;
5779                 case i40e_aqc_opc_get_link_status:
5780                         ret = i40e_dev_link_update(dev, 0);
5781                         if (!ret)
5782                                 _rte_eth_dev_callback_process(dev,
5783                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5784                         break;
5785                 default:
5786                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5787                                     opcode);
5788                         break;
5789                 }
5790         }
5791         rte_free(info.msg_buf);
5792 }
5793
5794 /**
5795  * Interrupt handler triggered by NIC  for handling
5796  * specific interrupt.
5797  *
5798  * @param handle
5799  *  Pointer to interrupt handle.
5800  * @param param
5801  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5802  *
5803  * @return
5804  *  void
5805  */
5806 static void
5807 i40e_dev_interrupt_handler(void *param)
5808 {
5809         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5811         uint32_t icr0;
5812
5813         /* Disable interrupt */
5814         i40e_pf_disable_irq0(hw);
5815
5816         /* read out interrupt causes */
5817         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5818
5819         /* No interrupt event indicated */
5820         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5821                 PMD_DRV_LOG(INFO, "No interrupt event");
5822                 goto done;
5823         }
5824         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5825                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5826         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5827                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5828         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5829                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5830         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5831                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5832         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5833                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5834         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5835                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5836         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5837                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5838
5839         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5840                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5841                 i40e_dev_handle_vfr_event(dev);
5842         }
5843         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5844                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5845                 i40e_dev_handle_aq_msg(dev);
5846         }
5847
5848 done:
5849         /* Enable interrupt */
5850         i40e_pf_enable_irq0(hw);
5851         rte_intr_enable(dev->intr_handle);
5852 }
5853
5854 int
5855 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5856                          struct i40e_macvlan_filter *filter,
5857                          int total)
5858 {
5859         int ele_num, ele_buff_size;
5860         int num, actual_num, i;
5861         uint16_t flags;
5862         int ret = I40E_SUCCESS;
5863         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5864         struct i40e_aqc_add_macvlan_element_data *req_list;
5865
5866         if (filter == NULL  || total == 0)
5867                 return I40E_ERR_PARAM;
5868         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5869         ele_buff_size = hw->aq.asq_buf_size;
5870
5871         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5872         if (req_list == NULL) {
5873                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5874                 return I40E_ERR_NO_MEMORY;
5875         }
5876
5877         num = 0;
5878         do {
5879                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5880                 memset(req_list, 0, ele_buff_size);
5881
5882                 for (i = 0; i < actual_num; i++) {
5883                         (void)rte_memcpy(req_list[i].mac_addr,
5884                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5885                         req_list[i].vlan_tag =
5886                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5887
5888                         switch (filter[num + i].filter_type) {
5889                         case RTE_MAC_PERFECT_MATCH:
5890                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5891                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5892                                 break;
5893                         case RTE_MACVLAN_PERFECT_MATCH:
5894                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5895                                 break;
5896                         case RTE_MAC_HASH_MATCH:
5897                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5898                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5899                                 break;
5900                         case RTE_MACVLAN_HASH_MATCH:
5901                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5902                                 break;
5903                         default:
5904                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5905                                 ret = I40E_ERR_PARAM;
5906                                 goto DONE;
5907                         }
5908
5909                         req_list[i].queue_number = 0;
5910
5911                         req_list[i].flags = rte_cpu_to_le_16(flags);
5912                 }
5913
5914                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5915                                                 actual_num, NULL);
5916                 if (ret != I40E_SUCCESS) {
5917                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5918                         goto DONE;
5919                 }
5920                 num += actual_num;
5921         } while (num < total);
5922
5923 DONE:
5924         rte_free(req_list);
5925         return ret;
5926 }
5927
5928 int
5929 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5930                             struct i40e_macvlan_filter *filter,
5931                             int total)
5932 {
5933         int ele_num, ele_buff_size;
5934         int num, actual_num, i;
5935         uint16_t flags;
5936         int ret = I40E_SUCCESS;
5937         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5938         struct i40e_aqc_remove_macvlan_element_data *req_list;
5939
5940         if (filter == NULL  || total == 0)
5941                 return I40E_ERR_PARAM;
5942
5943         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5944         ele_buff_size = hw->aq.asq_buf_size;
5945
5946         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5947         if (req_list == NULL) {
5948                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5949                 return I40E_ERR_NO_MEMORY;
5950         }
5951
5952         num = 0;
5953         do {
5954                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5955                 memset(req_list, 0, ele_buff_size);
5956
5957                 for (i = 0; i < actual_num; i++) {
5958                         (void)rte_memcpy(req_list[i].mac_addr,
5959                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5960                         req_list[i].vlan_tag =
5961                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5962
5963                         switch (filter[num + i].filter_type) {
5964                         case RTE_MAC_PERFECT_MATCH:
5965                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5966                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5967                                 break;
5968                         case RTE_MACVLAN_PERFECT_MATCH:
5969                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5970                                 break;
5971                         case RTE_MAC_HASH_MATCH:
5972                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5973                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5974                                 break;
5975                         case RTE_MACVLAN_HASH_MATCH:
5976                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5977                                 break;
5978                         default:
5979                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5980                                 ret = I40E_ERR_PARAM;
5981                                 goto DONE;
5982                         }
5983                         req_list[i].flags = rte_cpu_to_le_16(flags);
5984                 }
5985
5986                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5987                                                 actual_num, NULL);
5988                 if (ret != I40E_SUCCESS) {
5989                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5990                         goto DONE;
5991                 }
5992                 num += actual_num;
5993         } while (num < total);
5994
5995 DONE:
5996         rte_free(req_list);
5997         return ret;
5998 }
5999
6000 /* Find out specific MAC filter */
6001 static struct i40e_mac_filter *
6002 i40e_find_mac_filter(struct i40e_vsi *vsi,
6003                          struct ether_addr *macaddr)
6004 {
6005         struct i40e_mac_filter *f;
6006
6007         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6008                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6009                         return f;
6010         }
6011
6012         return NULL;
6013 }
6014
6015 static bool
6016 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6017                          uint16_t vlan_id)
6018 {
6019         uint32_t vid_idx, vid_bit;
6020
6021         if (vlan_id > ETH_VLAN_ID_MAX)
6022                 return 0;
6023
6024         vid_idx = I40E_VFTA_IDX(vlan_id);
6025         vid_bit = I40E_VFTA_BIT(vlan_id);
6026
6027         if (vsi->vfta[vid_idx] & vid_bit)
6028                 return 1;
6029         else
6030                 return 0;
6031 }
6032
6033 static void
6034 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6035                        uint16_t vlan_id, bool on)
6036 {
6037         uint32_t vid_idx, vid_bit;
6038
6039         vid_idx = I40E_VFTA_IDX(vlan_id);
6040         vid_bit = I40E_VFTA_BIT(vlan_id);
6041
6042         if (on)
6043                 vsi->vfta[vid_idx] |= vid_bit;
6044         else
6045                 vsi->vfta[vid_idx] &= ~vid_bit;
6046 }
6047
6048 void
6049 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6050                      uint16_t vlan_id, bool on)
6051 {
6052         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6053         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6054         int ret;
6055
6056         if (vlan_id > ETH_VLAN_ID_MAX)
6057                 return;
6058
6059         i40e_store_vlan_filter(vsi, vlan_id, on);
6060
6061         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6062                 return;
6063
6064         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6065
6066         if (on) {
6067                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6068                                        &vlan_data, 1, NULL);
6069                 if (ret != I40E_SUCCESS)
6070                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6071         } else {
6072                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6073                                           &vlan_data, 1, NULL);
6074                 if (ret != I40E_SUCCESS)
6075                         PMD_DRV_LOG(ERR,
6076                                     "Failed to remove vlan filter");
6077         }
6078 }
6079
6080 /**
6081  * Find all vlan options for specific mac addr,
6082  * return with actual vlan found.
6083  */
6084 int
6085 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6086                            struct i40e_macvlan_filter *mv_f,
6087                            int num, struct ether_addr *addr)
6088 {
6089         int i;
6090         uint32_t j, k;
6091
6092         /**
6093          * Not to use i40e_find_vlan_filter to decrease the loop time,
6094          * although the code looks complex.
6095           */
6096         if (num < vsi->vlan_num)
6097                 return I40E_ERR_PARAM;
6098
6099         i = 0;
6100         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6101                 if (vsi->vfta[j]) {
6102                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6103                                 if (vsi->vfta[j] & (1 << k)) {
6104                                         if (i > num - 1) {
6105                                                 PMD_DRV_LOG(ERR,
6106                                                         "vlan number doesn't match");
6107                                                 return I40E_ERR_PARAM;
6108                                         }
6109                                         (void)rte_memcpy(&mv_f[i].macaddr,
6110                                                         addr, ETH_ADDR_LEN);
6111                                         mv_f[i].vlan_id =
6112                                                 j * I40E_UINT32_BIT_SIZE + k;
6113                                         i++;
6114                                 }
6115                         }
6116                 }
6117         }
6118         return I40E_SUCCESS;
6119 }
6120
6121 static inline int
6122 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6123                            struct i40e_macvlan_filter *mv_f,
6124                            int num,
6125                            uint16_t vlan)
6126 {
6127         int i = 0;
6128         struct i40e_mac_filter *f;
6129
6130         if (num < vsi->mac_num)
6131                 return I40E_ERR_PARAM;
6132
6133         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6134                 if (i > num - 1) {
6135                         PMD_DRV_LOG(ERR, "buffer number not match");
6136                         return I40E_ERR_PARAM;
6137                 }
6138                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6139                                 ETH_ADDR_LEN);
6140                 mv_f[i].vlan_id = vlan;
6141                 mv_f[i].filter_type = f->mac_info.filter_type;
6142                 i++;
6143         }
6144
6145         return I40E_SUCCESS;
6146 }
6147
6148 static int
6149 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6150 {
6151         int i, j, num;
6152         struct i40e_mac_filter *f;
6153         struct i40e_macvlan_filter *mv_f;
6154         int ret = I40E_SUCCESS;
6155
6156         if (vsi == NULL || vsi->mac_num == 0)
6157                 return I40E_ERR_PARAM;
6158
6159         /* Case that no vlan is set */
6160         if (vsi->vlan_num == 0)
6161                 num = vsi->mac_num;
6162         else
6163                 num = vsi->mac_num * vsi->vlan_num;
6164
6165         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6166         if (mv_f == NULL) {
6167                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6168                 return I40E_ERR_NO_MEMORY;
6169         }
6170
6171         i = 0;
6172         if (vsi->vlan_num == 0) {
6173                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6174                         (void)rte_memcpy(&mv_f[i].macaddr,
6175                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6176                         mv_f[i].filter_type = f->mac_info.filter_type;
6177                         mv_f[i].vlan_id = 0;
6178                         i++;
6179                 }
6180         } else {
6181                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6182                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6183                                         vsi->vlan_num, &f->mac_info.mac_addr);
6184                         if (ret != I40E_SUCCESS)
6185                                 goto DONE;
6186                         for (j = i; j < i + vsi->vlan_num; j++)
6187                                 mv_f[j].filter_type = f->mac_info.filter_type;
6188                         i += vsi->vlan_num;
6189                 }
6190         }
6191
6192         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6193 DONE:
6194         rte_free(mv_f);
6195
6196         return ret;
6197 }
6198
6199 int
6200 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6201 {
6202         struct i40e_macvlan_filter *mv_f;
6203         int mac_num;
6204         int ret = I40E_SUCCESS;
6205
6206         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6207                 return I40E_ERR_PARAM;
6208
6209         /* If it's already set, just return */
6210         if (i40e_find_vlan_filter(vsi,vlan))
6211                 return I40E_SUCCESS;
6212
6213         mac_num = vsi->mac_num;
6214
6215         if (mac_num == 0) {
6216                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6217                 return I40E_ERR_PARAM;
6218         }
6219
6220         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6221
6222         if (mv_f == NULL) {
6223                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6224                 return I40E_ERR_NO_MEMORY;
6225         }
6226
6227         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6228
6229         if (ret != I40E_SUCCESS)
6230                 goto DONE;
6231
6232         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6233
6234         if (ret != I40E_SUCCESS)
6235                 goto DONE;
6236
6237         i40e_set_vlan_filter(vsi, vlan, 1);
6238
6239         vsi->vlan_num++;
6240         ret = I40E_SUCCESS;
6241 DONE:
6242         rte_free(mv_f);
6243         return ret;
6244 }
6245
6246 int
6247 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6248 {
6249         struct i40e_macvlan_filter *mv_f;
6250         int mac_num;
6251         int ret = I40E_SUCCESS;
6252
6253         /**
6254          * Vlan 0 is the generic filter for untagged packets
6255          * and can't be removed.
6256          */
6257         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6258                 return I40E_ERR_PARAM;
6259
6260         /* If can't find it, just return */
6261         if (!i40e_find_vlan_filter(vsi, vlan))
6262                 return I40E_ERR_PARAM;
6263
6264         mac_num = vsi->mac_num;
6265
6266         if (mac_num == 0) {
6267                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6268                 return I40E_ERR_PARAM;
6269         }
6270
6271         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6272
6273         if (mv_f == NULL) {
6274                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6275                 return I40E_ERR_NO_MEMORY;
6276         }
6277
6278         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6279
6280         if (ret != I40E_SUCCESS)
6281                 goto DONE;
6282
6283         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6284
6285         if (ret != I40E_SUCCESS)
6286                 goto DONE;
6287
6288         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6289         if (vsi->vlan_num == 1) {
6290                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6291                 if (ret != I40E_SUCCESS)
6292                         goto DONE;
6293
6294                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6295                 if (ret != I40E_SUCCESS)
6296                         goto DONE;
6297         }
6298
6299         i40e_set_vlan_filter(vsi, vlan, 0);
6300
6301         vsi->vlan_num--;
6302         ret = I40E_SUCCESS;
6303 DONE:
6304         rte_free(mv_f);
6305         return ret;
6306 }
6307
6308 int
6309 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6310 {
6311         struct i40e_mac_filter *f;
6312         struct i40e_macvlan_filter *mv_f;
6313         int i, vlan_num = 0;
6314         int ret = I40E_SUCCESS;
6315
6316         /* If it's add and we've config it, return */
6317         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6318         if (f != NULL)
6319                 return I40E_SUCCESS;
6320         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6321                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6322
6323                 /**
6324                  * If vlan_num is 0, that's the first time to add mac,
6325                  * set mask for vlan_id 0.
6326                  */
6327                 if (vsi->vlan_num == 0) {
6328                         i40e_set_vlan_filter(vsi, 0, 1);
6329                         vsi->vlan_num = 1;
6330                 }
6331                 vlan_num = vsi->vlan_num;
6332         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6333                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6334                 vlan_num = 1;
6335
6336         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6337         if (mv_f == NULL) {
6338                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6339                 return I40E_ERR_NO_MEMORY;
6340         }
6341
6342         for (i = 0; i < vlan_num; i++) {
6343                 mv_f[i].filter_type = mac_filter->filter_type;
6344                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6345                                 ETH_ADDR_LEN);
6346         }
6347
6348         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6349                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6350                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6351                                         &mac_filter->mac_addr);
6352                 if (ret != I40E_SUCCESS)
6353                         goto DONE;
6354         }
6355
6356         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6357         if (ret != I40E_SUCCESS)
6358                 goto DONE;
6359
6360         /* Add the mac addr into mac list */
6361         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6362         if (f == NULL) {
6363                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6364                 ret = I40E_ERR_NO_MEMORY;
6365                 goto DONE;
6366         }
6367         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6368                         ETH_ADDR_LEN);
6369         f->mac_info.filter_type = mac_filter->filter_type;
6370         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6371         vsi->mac_num++;
6372
6373         ret = I40E_SUCCESS;
6374 DONE:
6375         rte_free(mv_f);
6376
6377         return ret;
6378 }
6379
6380 int
6381 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6382 {
6383         struct i40e_mac_filter *f;
6384         struct i40e_macvlan_filter *mv_f;
6385         int i, vlan_num;
6386         enum rte_mac_filter_type filter_type;
6387         int ret = I40E_SUCCESS;
6388
6389         /* Can't find it, return an error */
6390         f = i40e_find_mac_filter(vsi, addr);
6391         if (f == NULL)
6392                 return I40E_ERR_PARAM;
6393
6394         vlan_num = vsi->vlan_num;
6395         filter_type = f->mac_info.filter_type;
6396         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6397                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6398                 if (vlan_num == 0) {
6399                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6400                         return I40E_ERR_PARAM;
6401                 }
6402         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6403                         filter_type == RTE_MAC_HASH_MATCH)
6404                 vlan_num = 1;
6405
6406         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6407         if (mv_f == NULL) {
6408                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6409                 return I40E_ERR_NO_MEMORY;
6410         }
6411
6412         for (i = 0; i < vlan_num; i++) {
6413                 mv_f[i].filter_type = filter_type;
6414                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6415                                 ETH_ADDR_LEN);
6416         }
6417         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6418                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6419                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6420                 if (ret != I40E_SUCCESS)
6421                         goto DONE;
6422         }
6423
6424         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6425         if (ret != I40E_SUCCESS)
6426                 goto DONE;
6427
6428         /* Remove the mac addr into mac list */
6429         TAILQ_REMOVE(&vsi->mac_list, f, next);
6430         rte_free(f);
6431         vsi->mac_num--;
6432
6433         ret = I40E_SUCCESS;
6434 DONE:
6435         rte_free(mv_f);
6436         return ret;
6437 }
6438
6439 /* Configure hash enable flags for RSS */
6440 uint64_t
6441 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6442 {
6443         uint64_t hena = 0;
6444
6445         if (!flags)
6446                 return hena;
6447
6448         if (flags & ETH_RSS_FRAG_IPV4)
6449                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6450         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6451                 if (type == I40E_MAC_X722) {
6452                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6453                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6454                 } else
6455                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6456         }
6457         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6458                 if (type == I40E_MAC_X722) {
6459                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6460                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6461                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6462                 } else
6463                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6464         }
6465         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6466                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6467         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6468                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6469         if (flags & ETH_RSS_FRAG_IPV6)
6470                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6471         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6472                 if (type == I40E_MAC_X722) {
6473                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6474                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6475                 } else
6476                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6477         }
6478         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6479                 if (type == I40E_MAC_X722) {
6480                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6481                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6482                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6483                 } else
6484                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6485         }
6486         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6487                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6488         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6489                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6490         if (flags & ETH_RSS_L2_PAYLOAD)
6491                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6492
6493         return hena;
6494 }
6495
6496 /* Parse the hash enable flags */
6497 uint64_t
6498 i40e_parse_hena(uint64_t flags)
6499 {
6500         uint64_t rss_hf = 0;
6501
6502         if (!flags)
6503                 return rss_hf;
6504         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6505                 rss_hf |= ETH_RSS_FRAG_IPV4;
6506         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6507                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6508         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6509                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6510         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6511                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6512         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6513                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6514         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6515                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6516         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6517                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6518         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6519                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6520         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6521                 rss_hf |= ETH_RSS_FRAG_IPV6;
6522         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6523                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6524         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6525                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6526         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6527                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6528         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6529                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6530         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6531                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6532         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6533                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6534         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6535                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6536         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6537                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6538
6539         return rss_hf;
6540 }
6541
6542 /* Disable RSS */
6543 static void
6544 i40e_pf_disable_rss(struct i40e_pf *pf)
6545 {
6546         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6547         uint64_t hena;
6548
6549         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6550         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6551         if (hw->mac.type == I40E_MAC_X722)
6552                 hena &= ~I40E_RSS_HENA_ALL_X722;
6553         else
6554                 hena &= ~I40E_RSS_HENA_ALL;
6555         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6556         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6557         I40E_WRITE_FLUSH(hw);
6558 }
6559
6560 static int
6561 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6562 {
6563         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6564         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6565         int ret = 0;
6566
6567         if (!key || key_len == 0) {
6568                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6569                 return 0;
6570         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6571                 sizeof(uint32_t)) {
6572                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6573                 return -EINVAL;
6574         }
6575
6576         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6577                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6578                         (struct i40e_aqc_get_set_rss_key_data *)key;
6579
6580                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6581                 if (ret)
6582                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6583         } else {
6584                 uint32_t *hash_key = (uint32_t *)key;
6585                 uint16_t i;
6586
6587                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6588                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6589                 I40E_WRITE_FLUSH(hw);
6590         }
6591
6592         return ret;
6593 }
6594
6595 static int
6596 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6597 {
6598         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6600         int ret;
6601
6602         if (!key || !key_len)
6603                 return -EINVAL;
6604
6605         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6606                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6607                         (struct i40e_aqc_get_set_rss_key_data *)key);
6608                 if (ret) {
6609                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6610                         return ret;
6611                 }
6612         } else {
6613                 uint32_t *key_dw = (uint32_t *)key;
6614                 uint16_t i;
6615
6616                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6617                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6618         }
6619         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6620
6621         return 0;
6622 }
6623
6624 static int
6625 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6626 {
6627         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6628         uint64_t rss_hf;
6629         uint64_t hena;
6630         int ret;
6631
6632         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6633                                rss_conf->rss_key_len);
6634         if (ret)
6635                 return ret;
6636
6637         rss_hf = rss_conf->rss_hf;
6638         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6639         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6640         if (hw->mac.type == I40E_MAC_X722)
6641                 hena &= ~I40E_RSS_HENA_ALL_X722;
6642         else
6643                 hena &= ~I40E_RSS_HENA_ALL;
6644         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6645         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6646         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6647         I40E_WRITE_FLUSH(hw);
6648
6649         return 0;
6650 }
6651
6652 static int
6653 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6654                          struct rte_eth_rss_conf *rss_conf)
6655 {
6656         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6657         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6658         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6659         uint64_t hena;
6660
6661         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6662         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6663         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6664                  ? I40E_RSS_HENA_ALL_X722
6665                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6666                 if (rss_hf != 0) /* Enable RSS */
6667                         return -EINVAL;
6668                 return 0; /* Nothing to do */
6669         }
6670         /* RSS enabled */
6671         if (rss_hf == 0) /* Disable RSS */
6672                 return -EINVAL;
6673
6674         return i40e_hw_rss_hash_set(pf, rss_conf);
6675 }
6676
6677 static int
6678 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6679                            struct rte_eth_rss_conf *rss_conf)
6680 {
6681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6682         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6683         uint64_t hena;
6684
6685         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6686                          &rss_conf->rss_key_len);
6687
6688         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6689         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6690         rss_conf->rss_hf = i40e_parse_hena(hena);
6691
6692         return 0;
6693 }
6694
6695 static int
6696 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6697 {
6698         switch (filter_type) {
6699         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6700                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6701                 break;
6702         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6703                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6704                 break;
6705         case RTE_TUNNEL_FILTER_IMAC_TENID:
6706                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6707                 break;
6708         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6709                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6710                 break;
6711         case ETH_TUNNEL_FILTER_IMAC:
6712                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6713                 break;
6714         case ETH_TUNNEL_FILTER_OIP:
6715                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6716                 break;
6717         case ETH_TUNNEL_FILTER_IIP:
6718                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6719                 break;
6720         default:
6721                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6722                 return -EINVAL;
6723         }
6724
6725         return 0;
6726 }
6727
6728 /* Convert tunnel filter structure */
6729 static int
6730 i40e_tunnel_filter_convert(
6731         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6732         struct i40e_tunnel_filter *tunnel_filter)
6733 {
6734         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6735                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6736         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6737                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6738         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6739         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6740              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6741             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6742                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6743         else
6744                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6745         tunnel_filter->input.flags = cld_filter->element.flags;
6746         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6747         tunnel_filter->queue = cld_filter->element.queue_number;
6748         rte_memcpy(tunnel_filter->input.general_fields,
6749                    cld_filter->general_fields,
6750                    sizeof(cld_filter->general_fields));
6751
6752         return 0;
6753 }
6754
6755 /* Check if there exists the tunnel filter */
6756 struct i40e_tunnel_filter *
6757 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6758                              const struct i40e_tunnel_filter_input *input)
6759 {
6760         int ret;
6761
6762         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6763         if (ret < 0)
6764                 return NULL;
6765
6766         return tunnel_rule->hash_map[ret];
6767 }
6768
6769 /* Add a tunnel filter into the SW list */
6770 static int
6771 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6772                              struct i40e_tunnel_filter *tunnel_filter)
6773 {
6774         struct i40e_tunnel_rule *rule = &pf->tunnel;
6775         int ret;
6776
6777         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6778         if (ret < 0) {
6779                 PMD_DRV_LOG(ERR,
6780                             "Failed to insert tunnel filter to hash table %d!",
6781                             ret);
6782                 return ret;
6783         }
6784         rule->hash_map[ret] = tunnel_filter;
6785
6786         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6787
6788         return 0;
6789 }
6790
6791 /* Delete a tunnel filter from the SW list */
6792 int
6793 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6794                           struct i40e_tunnel_filter_input *input)
6795 {
6796         struct i40e_tunnel_rule *rule = &pf->tunnel;
6797         struct i40e_tunnel_filter *tunnel_filter;
6798         int ret;
6799
6800         ret = rte_hash_del_key(rule->hash_table, input);
6801         if (ret < 0) {
6802                 PMD_DRV_LOG(ERR,
6803                             "Failed to delete tunnel filter to hash table %d!",
6804                             ret);
6805                 return ret;
6806         }
6807         tunnel_filter = rule->hash_map[ret];
6808         rule->hash_map[ret] = NULL;
6809
6810         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6811         rte_free(tunnel_filter);
6812
6813         return 0;
6814 }
6815
6816 int
6817 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6818                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6819                         uint8_t add)
6820 {
6821         uint16_t ip_type;
6822         uint32_t ipv4_addr;
6823         uint8_t i, tun_type = 0;
6824         /* internal varialbe to convert ipv6 byte order */
6825         uint32_t convert_ipv6[4];
6826         int val, ret = 0;
6827         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6828         struct i40e_vsi *vsi = pf->main_vsi;
6829         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6830         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6831         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6832         struct i40e_tunnel_filter *tunnel, *node;
6833         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6834
6835         cld_filter = rte_zmalloc("tunnel_filter",
6836                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6837         0);
6838
6839         if (NULL == cld_filter) {
6840                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6841                 return -ENOMEM;
6842         }
6843         pfilter = cld_filter;
6844
6845         ether_addr_copy(&tunnel_filter->outer_mac,
6846                         (struct ether_addr *)&pfilter->element.outer_mac);
6847         ether_addr_copy(&tunnel_filter->inner_mac,
6848                         (struct ether_addr *)&pfilter->element.inner_mac);
6849
6850         pfilter->element.inner_vlan =
6851                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6852         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6853                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6854                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6855                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6856                                 &rte_cpu_to_le_32(ipv4_addr),
6857                                 sizeof(pfilter->element.ipaddr.v4.data));
6858         } else {
6859                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6860                 for (i = 0; i < 4; i++) {
6861                         convert_ipv6[i] =
6862                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6863                 }
6864                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6865                            &convert_ipv6,
6866                            sizeof(pfilter->element.ipaddr.v6.data));
6867         }
6868
6869         /* check tunneled type */
6870         switch (tunnel_filter->tunnel_type) {
6871         case RTE_TUNNEL_TYPE_VXLAN:
6872                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6873                 break;
6874         case RTE_TUNNEL_TYPE_NVGRE:
6875                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6876                 break;
6877         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6878                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6879                 break;
6880         default:
6881                 /* Other tunnel types is not supported. */
6882                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6883                 rte_free(cld_filter);
6884                 return -EINVAL;
6885         }
6886
6887         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6888                                        &pfilter->element.flags);
6889         if (val < 0) {
6890                 rte_free(cld_filter);
6891                 return -EINVAL;
6892         }
6893
6894         pfilter->element.flags |= rte_cpu_to_le_16(
6895                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6896                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6897         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6898         pfilter->element.queue_number =
6899                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6900
6901         /* Check if there is the filter in SW list */
6902         memset(&check_filter, 0, sizeof(check_filter));
6903         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6904         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6905         if (add && node) {
6906                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6907                 return -EINVAL;
6908         }
6909
6910         if (!add && !node) {
6911                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6912                 return -EINVAL;
6913         }
6914
6915         if (add) {
6916                 ret = i40e_aq_add_cloud_filters(hw,
6917                                         vsi->seid, &cld_filter->element, 1);
6918                 if (ret < 0) {
6919                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6920                         return -ENOTSUP;
6921                 }
6922                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6923                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6924                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6925         } else {
6926                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6927                                                    &cld_filter->element, 1);
6928                 if (ret < 0) {
6929                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6930                         return -ENOTSUP;
6931                 }
6932                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6933         }
6934
6935         rte_free(cld_filter);
6936         return ret;
6937 }
6938
6939 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6940 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
6941 #define I40E_TR_GENEVE_KEY_MASK                 0x8
6942 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
6943 #define I40E_TR_GRE_KEY_MASK                    0x400
6944 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
6945 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
6946
6947 static enum
6948 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6949 {
6950         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6951         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6952         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6953         enum i40e_status_code status = I40E_SUCCESS;
6954
6955         memset(&filter_replace, 0,
6956                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6957         memset(&filter_replace_buf, 0,
6958                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6959
6960         /* create L1 filter */
6961         filter_replace.old_filter_type =
6962                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6963         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6964         filter_replace.tr_bit = 0;
6965
6966         /* Prepare the buffer, 3 entries */
6967         filter_replace_buf.data[0] =
6968                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6969         filter_replace_buf.data[0] |=
6970                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6971         filter_replace_buf.data[2] = 0xFF;
6972         filter_replace_buf.data[3] = 0xFF;
6973         filter_replace_buf.data[4] =
6974                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6975         filter_replace_buf.data[4] |=
6976                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6977         filter_replace_buf.data[7] = 0xF0;
6978         filter_replace_buf.data[8]
6979                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6980         filter_replace_buf.data[8] |=
6981                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6982         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6983                 I40E_TR_GENEVE_KEY_MASK |
6984                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6985         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6986                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6987                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
6988
6989         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
6990                                                &filter_replace_buf);
6991         return status;
6992 }
6993
6994 static enum
6995 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
6996 {
6997         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6998         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6999         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7000         enum i40e_status_code status = I40E_SUCCESS;
7001
7002         /* For MPLSoUDP */
7003         memset(&filter_replace, 0,
7004                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7005         memset(&filter_replace_buf, 0,
7006                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7007         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7008                 I40E_AQC_MIRROR_CLOUD_FILTER;
7009         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7010         filter_replace.new_filter_type =
7011                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7012         /* Prepare the buffer, 2 entries */
7013         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7014         filter_replace_buf.data[0] |=
7015                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7016         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7017         filter_replace_buf.data[4] |=
7018                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7019         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7020                                                &filter_replace_buf);
7021         if (status < 0)
7022                 return status;
7023
7024         /* For MPLSoGRE */
7025         memset(&filter_replace, 0,
7026                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7027         memset(&filter_replace_buf, 0,
7028                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7029
7030         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7031                 I40E_AQC_MIRROR_CLOUD_FILTER;
7032         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7033         filter_replace.new_filter_type =
7034                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7035         /* Prepare the buffer, 2 entries */
7036         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7037         filter_replace_buf.data[0] |=
7038                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7039         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7040         filter_replace_buf.data[4] |=
7041                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7042
7043         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7044                                                &filter_replace_buf);
7045         return status;
7046 }
7047
7048 int
7049 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7050                       struct i40e_tunnel_filter_conf *tunnel_filter,
7051                       uint8_t add)
7052 {
7053         uint16_t ip_type;
7054         uint32_t ipv4_addr;
7055         uint8_t i, tun_type = 0;
7056         /* internal variable to convert ipv6 byte order */
7057         uint32_t convert_ipv6[4];
7058         int val, ret = 0;
7059         struct i40e_pf_vf *vf = NULL;
7060         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7061         struct i40e_vsi *vsi;
7062         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7063         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7064         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7065         struct i40e_tunnel_filter *tunnel, *node;
7066         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7067         uint32_t teid_le;
7068         bool big_buffer = 0;
7069
7070         cld_filter = rte_zmalloc("tunnel_filter",
7071                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7072                          0);
7073
7074         if (cld_filter == NULL) {
7075                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7076                 return -ENOMEM;
7077         }
7078         pfilter = cld_filter;
7079
7080         ether_addr_copy(&tunnel_filter->outer_mac,
7081                         (struct ether_addr *)&pfilter->element.outer_mac);
7082         ether_addr_copy(&tunnel_filter->inner_mac,
7083                         (struct ether_addr *)&pfilter->element.inner_mac);
7084
7085         pfilter->element.inner_vlan =
7086                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7087         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7088                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7089                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7090                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7091                                 &rte_cpu_to_le_32(ipv4_addr),
7092                                 sizeof(pfilter->element.ipaddr.v4.data));
7093         } else {
7094                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7095                 for (i = 0; i < 4; i++) {
7096                         convert_ipv6[i] =
7097                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7098                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7099                 }
7100                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7101                            &convert_ipv6,
7102                            sizeof(pfilter->element.ipaddr.v6.data));
7103         }
7104
7105         /* check tunneled type */
7106         switch (tunnel_filter->tunnel_type) {
7107         case I40E_TUNNEL_TYPE_VXLAN:
7108                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7109                 break;
7110         case I40E_TUNNEL_TYPE_NVGRE:
7111                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7112                 break;
7113         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7114                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7115                 break;
7116         case I40E_TUNNEL_TYPE_MPLSoUDP:
7117                 if (!pf->mpls_replace_flag) {
7118                         i40e_replace_mpls_l1_filter(pf);
7119                         i40e_replace_mpls_cloud_filter(pf);
7120                         pf->mpls_replace_flag = 1;
7121                 }
7122                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7123                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7124                         teid_le >> 4;
7125                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7126                         (teid_le & 0xF) << 12;
7127                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7128                         0x40;
7129                 big_buffer = 1;
7130                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7131                 break;
7132         case I40E_TUNNEL_TYPE_MPLSoGRE:
7133                 if (!pf->mpls_replace_flag) {
7134                         i40e_replace_mpls_l1_filter(pf);
7135                         i40e_replace_mpls_cloud_filter(pf);
7136                         pf->mpls_replace_flag = 1;
7137                 }
7138                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7139                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7140                         teid_le >> 4;
7141                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7142                         (teid_le & 0xF) << 12;
7143                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7144                         0x0;
7145                 big_buffer = 1;
7146                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7147                 break;
7148         case I40E_TUNNEL_TYPE_QINQ:
7149                 if (!pf->qinq_replace_flag) {
7150                         ret = i40e_cloud_filter_qinq_create(pf);
7151                         if (ret < 0)
7152                                 PMD_DRV_LOG(DEBUG,
7153                                             "QinQ tunnel filter already created.");
7154                         pf->qinq_replace_flag = 1;
7155                 }
7156                 /*      Add in the General fields the values of
7157                  *      the Outer and Inner VLAN
7158                  *      Big Buffer should be set, see changes in
7159                  *      i40e_aq_add_cloud_filters
7160                  */
7161                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7162                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7163                 big_buffer = 1;
7164                 break;
7165         default:
7166                 /* Other tunnel types is not supported. */
7167                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7168                 rte_free(cld_filter);
7169                 return -EINVAL;
7170         }
7171
7172         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7173                 pfilter->element.flags =
7174                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7175         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7176                 pfilter->element.flags =
7177                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7178         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7179                 pfilter->element.flags |=
7180                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7181         else {
7182                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7183                                                 &pfilter->element.flags);
7184                 if (val < 0) {
7185                         rte_free(cld_filter);
7186                         return -EINVAL;
7187                 }
7188         }
7189
7190         pfilter->element.flags |= rte_cpu_to_le_16(
7191                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7192                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7193         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7194         pfilter->element.queue_number =
7195                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7196
7197         if (!tunnel_filter->is_to_vf)
7198                 vsi = pf->main_vsi;
7199         else {
7200                 if (tunnel_filter->vf_id >= pf->vf_num) {
7201                         PMD_DRV_LOG(ERR, "Invalid argument.");
7202                         return -EINVAL;
7203                 }
7204                 vf = &pf->vfs[tunnel_filter->vf_id];
7205                 vsi = vf->vsi;
7206         }
7207
7208         /* Check if there is the filter in SW list */
7209         memset(&check_filter, 0, sizeof(check_filter));
7210         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7211         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7212         check_filter.vf_id = tunnel_filter->vf_id;
7213         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7214         if (add && node) {
7215                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7216                 return -EINVAL;
7217         }
7218
7219         if (!add && !node) {
7220                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7221                 return -EINVAL;
7222         }
7223
7224         if (add) {
7225                 if (big_buffer)
7226                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7227                                                    vsi->seid, cld_filter, 1);
7228                 else
7229                         ret = i40e_aq_add_cloud_filters(hw,
7230                                         vsi->seid, &cld_filter->element, 1);
7231                 if (ret < 0) {
7232                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7233                         return -ENOTSUP;
7234                 }
7235                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7236                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7237                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7238         } else {
7239                 if (big_buffer)
7240                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7241                                 hw, vsi->seid, cld_filter, 1);
7242                 else
7243                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7244                                                    &cld_filter->element, 1);
7245                 if (ret < 0) {
7246                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7247                         return -ENOTSUP;
7248                 }
7249                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7250         }
7251
7252         rte_free(cld_filter);
7253         return ret;
7254 }
7255
7256 static int
7257 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7258 {
7259         uint8_t i;
7260
7261         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7262                 if (pf->vxlan_ports[i] == port)
7263                         return i;
7264         }
7265
7266         return -1;
7267 }
7268
7269 static int
7270 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7271 {
7272         int  idx, ret;
7273         uint8_t filter_idx;
7274         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7275
7276         idx = i40e_get_vxlan_port_idx(pf, port);
7277
7278         /* Check if port already exists */
7279         if (idx >= 0) {
7280                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7281                 return -EINVAL;
7282         }
7283
7284         /* Now check if there is space to add the new port */
7285         idx = i40e_get_vxlan_port_idx(pf, 0);
7286         if (idx < 0) {
7287                 PMD_DRV_LOG(ERR,
7288                         "Maximum number of UDP ports reached, not adding port %d",
7289                         port);
7290                 return -ENOSPC;
7291         }
7292
7293         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7294                                         &filter_idx, NULL);
7295         if (ret < 0) {
7296                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7297                 return -1;
7298         }
7299
7300         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7301                          port,  filter_idx);
7302
7303         /* New port: add it and mark its index in the bitmap */
7304         pf->vxlan_ports[idx] = port;
7305         pf->vxlan_bitmap |= (1 << idx);
7306
7307         if (!(pf->flags & I40E_FLAG_VXLAN))
7308                 pf->flags |= I40E_FLAG_VXLAN;
7309
7310         return 0;
7311 }
7312
7313 static int
7314 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7315 {
7316         int idx;
7317         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7318
7319         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7320                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7321                 return -EINVAL;
7322         }
7323
7324         idx = i40e_get_vxlan_port_idx(pf, port);
7325
7326         if (idx < 0) {
7327                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7328                 return -EINVAL;
7329         }
7330
7331         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7332                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7333                 return -1;
7334         }
7335
7336         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7337                         port, idx);
7338
7339         pf->vxlan_ports[idx] = 0;
7340         pf->vxlan_bitmap &= ~(1 << idx);
7341
7342         if (!pf->vxlan_bitmap)
7343                 pf->flags &= ~I40E_FLAG_VXLAN;
7344
7345         return 0;
7346 }
7347
7348 /* Add UDP tunneling port */
7349 static int
7350 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7351                              struct rte_eth_udp_tunnel *udp_tunnel)
7352 {
7353         int ret = 0;
7354         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7355
7356         if (udp_tunnel == NULL)
7357                 return -EINVAL;
7358
7359         switch (udp_tunnel->prot_type) {
7360         case RTE_TUNNEL_TYPE_VXLAN:
7361                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7362                 break;
7363
7364         case RTE_TUNNEL_TYPE_GENEVE:
7365         case RTE_TUNNEL_TYPE_TEREDO:
7366                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7367                 ret = -1;
7368                 break;
7369
7370         default:
7371                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7372                 ret = -1;
7373                 break;
7374         }
7375
7376         return ret;
7377 }
7378
7379 /* Remove UDP tunneling port */
7380 static int
7381 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7382                              struct rte_eth_udp_tunnel *udp_tunnel)
7383 {
7384         int ret = 0;
7385         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7386
7387         if (udp_tunnel == NULL)
7388                 return -EINVAL;
7389
7390         switch (udp_tunnel->prot_type) {
7391         case RTE_TUNNEL_TYPE_VXLAN:
7392                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7393                 break;
7394         case RTE_TUNNEL_TYPE_GENEVE:
7395         case RTE_TUNNEL_TYPE_TEREDO:
7396                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7397                 ret = -1;
7398                 break;
7399         default:
7400                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7401                 ret = -1;
7402                 break;
7403         }
7404
7405         return ret;
7406 }
7407
7408 /* Calculate the maximum number of contiguous PF queues that are configured */
7409 static int
7410 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7411 {
7412         struct rte_eth_dev_data *data = pf->dev_data;
7413         int i, num;
7414         struct i40e_rx_queue *rxq;
7415
7416         num = 0;
7417         for (i = 0; i < pf->lan_nb_qps; i++) {
7418                 rxq = data->rx_queues[i];
7419                 if (rxq && rxq->q_set)
7420                         num++;
7421                 else
7422                         break;
7423         }
7424
7425         return num;
7426 }
7427
7428 /* Configure RSS */
7429 static int
7430 i40e_pf_config_rss(struct i40e_pf *pf)
7431 {
7432         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7433         struct rte_eth_rss_conf rss_conf;
7434         uint32_t i, lut = 0;
7435         uint16_t j, num;
7436
7437         /*
7438          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7439          * It's necessary to calulate the actual PF queues that are configured.
7440          */
7441         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7442                 num = i40e_pf_calc_configured_queues_num(pf);
7443         else
7444                 num = pf->dev_data->nb_rx_queues;
7445
7446         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7447         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7448                         num);
7449
7450         if (num == 0) {
7451                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7452                 return -ENOTSUP;
7453         }
7454
7455         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7456                 if (j == num)
7457                         j = 0;
7458                 lut = (lut << 8) | (j & ((0x1 <<
7459                         hw->func_caps.rss_table_entry_width) - 1));
7460                 if ((i & 3) == 3)
7461                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7462         }
7463
7464         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7465         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7466                 i40e_pf_disable_rss(pf);
7467                 return 0;
7468         }
7469         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7470                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7471                 /* Random default keys */
7472                 static uint32_t rss_key_default[] = {0x6b793944,
7473                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7474                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7475                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7476
7477                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7478                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7479                                                         sizeof(uint32_t);
7480         }
7481
7482         return i40e_hw_rss_hash_set(pf, &rss_conf);
7483 }
7484
7485 static int
7486 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7487                                struct rte_eth_tunnel_filter_conf *filter)
7488 {
7489         if (pf == NULL || filter == NULL) {
7490                 PMD_DRV_LOG(ERR, "Invalid parameter");
7491                 return -EINVAL;
7492         }
7493
7494         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7495                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7496                 return -EINVAL;
7497         }
7498
7499         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7500                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7501                 return -EINVAL;
7502         }
7503
7504         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7505                 (is_zero_ether_addr(&filter->outer_mac))) {
7506                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7507                 return -EINVAL;
7508         }
7509
7510         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7511                 (is_zero_ether_addr(&filter->inner_mac))) {
7512                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7513                 return -EINVAL;
7514         }
7515
7516         return 0;
7517 }
7518
7519 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7520 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7521 static int
7522 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7523 {
7524         uint32_t val, reg;
7525         int ret = -EINVAL;
7526
7527         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7528         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7529
7530         if (len == 3) {
7531                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7532         } else if (len == 4) {
7533                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7534         } else {
7535                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7536                 return ret;
7537         }
7538
7539         if (reg != val) {
7540                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7541                                                    reg, NULL);
7542                 if (ret != 0)
7543                         return ret;
7544         } else {
7545                 ret = 0;
7546         }
7547         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7548                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7549
7550         return ret;
7551 }
7552
7553 static int
7554 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7555 {
7556         int ret = -EINVAL;
7557
7558         if (!hw || !cfg)
7559                 return -EINVAL;
7560
7561         switch (cfg->cfg_type) {
7562         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7563                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7564                 break;
7565         default:
7566                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7567                 break;
7568         }
7569
7570         return ret;
7571 }
7572
7573 static int
7574 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7575                                enum rte_filter_op filter_op,
7576                                void *arg)
7577 {
7578         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7579         int ret = I40E_ERR_PARAM;
7580
7581         switch (filter_op) {
7582         case RTE_ETH_FILTER_SET:
7583                 ret = i40e_dev_global_config_set(hw,
7584                         (struct rte_eth_global_cfg *)arg);
7585                 break;
7586         default:
7587                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7588                 break;
7589         }
7590
7591         return ret;
7592 }
7593
7594 static int
7595 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7596                           enum rte_filter_op filter_op,
7597                           void *arg)
7598 {
7599         struct rte_eth_tunnel_filter_conf *filter;
7600         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7601         int ret = I40E_SUCCESS;
7602
7603         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7604
7605         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7606                 return I40E_ERR_PARAM;
7607
7608         switch (filter_op) {
7609         case RTE_ETH_FILTER_NOP:
7610                 if (!(pf->flags & I40E_FLAG_VXLAN))
7611                         ret = I40E_NOT_SUPPORTED;
7612                 break;
7613         case RTE_ETH_FILTER_ADD:
7614                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7615                 break;
7616         case RTE_ETH_FILTER_DELETE:
7617                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7618                 break;
7619         default:
7620                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7621                 ret = I40E_ERR_PARAM;
7622                 break;
7623         }
7624
7625         return ret;
7626 }
7627
7628 static int
7629 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7630 {
7631         int ret = 0;
7632         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7633
7634         /* RSS setup */
7635         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7636                 ret = i40e_pf_config_rss(pf);
7637         else
7638                 i40e_pf_disable_rss(pf);
7639
7640         return ret;
7641 }
7642
7643 /* Get the symmetric hash enable configurations per port */
7644 static void
7645 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7646 {
7647         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7648
7649         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7650 }
7651
7652 /* Set the symmetric hash enable configurations per port */
7653 static void
7654 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7655 {
7656         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7657
7658         if (enable > 0) {
7659                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7660                         PMD_DRV_LOG(INFO,
7661                                 "Symmetric hash has already been enabled");
7662                         return;
7663                 }
7664                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7665         } else {
7666                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7667                         PMD_DRV_LOG(INFO,
7668                                 "Symmetric hash has already been disabled");
7669                         return;
7670                 }
7671                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7672         }
7673         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7674         I40E_WRITE_FLUSH(hw);
7675 }
7676
7677 /*
7678  * Get global configurations of hash function type and symmetric hash enable
7679  * per flow type (pctype). Note that global configuration means it affects all
7680  * the ports on the same NIC.
7681  */
7682 static int
7683 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7684                                    struct rte_eth_hash_global_conf *g_cfg)
7685 {
7686         uint32_t reg, mask = I40E_FLOW_TYPES;
7687         uint16_t i;
7688         enum i40e_filter_pctype pctype;
7689
7690         memset(g_cfg, 0, sizeof(*g_cfg));
7691         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7692         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7693                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7694         else
7695                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7696         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7697                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7698
7699         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7700                 if (!(mask & (1UL << i)))
7701                         continue;
7702                 mask &= ~(1UL << i);
7703                 /* Bit set indicats the coresponding flow type is supported */
7704                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7705                 /* if flowtype is invalid, continue */
7706                 if (!I40E_VALID_FLOW(i))
7707                         continue;
7708                 pctype = i40e_flowtype_to_pctype(i);
7709                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7710                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7711                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7712         }
7713
7714         return 0;
7715 }
7716
7717 static int
7718 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7719 {
7720         uint32_t i;
7721         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7722
7723         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7724                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7725                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7726                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7727                                                 g_cfg->hash_func);
7728                 return -EINVAL;
7729         }
7730
7731         /*
7732          * As i40e supports less than 32 flow types, only first 32 bits need to
7733          * be checked.
7734          */
7735         mask0 = g_cfg->valid_bit_mask[0];
7736         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7737                 if (i == 0) {
7738                         /* Check if any unsupported flow type configured */
7739                         if ((mask0 | i40e_mask) ^ i40e_mask)
7740                                 goto mask_err;
7741                 } else {
7742                         if (g_cfg->valid_bit_mask[i])
7743                                 goto mask_err;
7744                 }
7745         }
7746
7747         return 0;
7748
7749 mask_err:
7750         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7751
7752         return -EINVAL;
7753 }
7754
7755 /*
7756  * Set global configurations of hash function type and symmetric hash enable
7757  * per flow type (pctype). Note any modifying global configuration will affect
7758  * all the ports on the same NIC.
7759  */
7760 static int
7761 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7762                                    struct rte_eth_hash_global_conf *g_cfg)
7763 {
7764         int ret;
7765         uint16_t i;
7766         uint32_t reg;
7767         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7768         enum i40e_filter_pctype pctype;
7769
7770         /* Check the input parameters */
7771         ret = i40e_hash_global_config_check(g_cfg);
7772         if (ret < 0)
7773                 return ret;
7774
7775         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7776                 if (!(mask0 & (1UL << i)))
7777                         continue;
7778                 mask0 &= ~(1UL << i);
7779                 /* if flowtype is invalid, continue */
7780                 if (!I40E_VALID_FLOW(i))
7781                         continue;
7782                 pctype = i40e_flowtype_to_pctype(i);
7783                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7784                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7785                 if (hw->mac.type == I40E_MAC_X722) {
7786                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7787                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7788                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7789                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7790                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7791                                   reg);
7792                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7793                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7794                                   reg);
7795                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7796                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7797                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7798                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7799                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7800                                   reg);
7801                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7802                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7803                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7804                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7805                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7806                                   reg);
7807                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7808                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7809                                   reg);
7810                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7811                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7812                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7813                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7814                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7815                                   reg);
7816                         } else {
7817                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7818                                   reg);
7819                         }
7820                 } else {
7821                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7822                 }
7823         }
7824
7825         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7826         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7827                 /* Toeplitz */
7828                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7829                         PMD_DRV_LOG(DEBUG,
7830                                 "Hash function already set to Toeplitz");
7831                         goto out;
7832                 }
7833                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7834         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7835                 /* Simple XOR */
7836                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7837                         PMD_DRV_LOG(DEBUG,
7838                                 "Hash function already set to Simple XOR");
7839                         goto out;
7840                 }
7841                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7842         } else
7843                 /* Use the default, and keep it as it is */
7844                 goto out;
7845
7846         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7847
7848 out:
7849         I40E_WRITE_FLUSH(hw);
7850
7851         return 0;
7852 }
7853
7854 /**
7855  * Valid input sets for hash and flow director filters per PCTYPE
7856  */
7857 static uint64_t
7858 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7859                 enum rte_filter_type filter)
7860 {
7861         uint64_t valid;
7862
7863         static const uint64_t valid_hash_inset_table[] = {
7864                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7865                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7866                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7867                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7868                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7869                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7870                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7871                         I40E_INSET_FLEX_PAYLOAD,
7872                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7873                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7874                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7875                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7876                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7877                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7878                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7879                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7880                         I40E_INSET_FLEX_PAYLOAD,
7881                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7882                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7883                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7884                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7885                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7886                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7887                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7888                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7889                         I40E_INSET_FLEX_PAYLOAD,
7890                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7891                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7892                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7893                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7894                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7895                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7896                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7897                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7898                         I40E_INSET_FLEX_PAYLOAD,
7899                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7900                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7901                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7902                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7903                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7904                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7905                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7906                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7907                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7908                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7909                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7910                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7911                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7912                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7913                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7914                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7915                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7916                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7917                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7918                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7919                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7920                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7921                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7922                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7923                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7924                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7925                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7926                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7927                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7928                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7929                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7930                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7931                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7932                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7933                         I40E_INSET_FLEX_PAYLOAD,
7934                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7935                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7936                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7937                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7938                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7939                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7940                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7941                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7942                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7943                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7944                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7945                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7946                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7947                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7948                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7949                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7950                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7951                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7952                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7953                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7954                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7955                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7956                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7957                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7958                         I40E_INSET_FLEX_PAYLOAD,
7959                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7960                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7961                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7962                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7963                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7964                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7965                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7966                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7967                         I40E_INSET_FLEX_PAYLOAD,
7968                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7969                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7970                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7971                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7972                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7973                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7974                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7975                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7976                         I40E_INSET_FLEX_PAYLOAD,
7977                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7978                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7979                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7980                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7981                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7982                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7983                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7984                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7985                         I40E_INSET_FLEX_PAYLOAD,
7986                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7987                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7988                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7989                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7990                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7991                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7992                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7993                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7994                         I40E_INSET_FLEX_PAYLOAD,
7995                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7996                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7997                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7998                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7999                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8000                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8001                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8002                         I40E_INSET_FLEX_PAYLOAD,
8003                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8004                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8005                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8006                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8007                         I40E_INSET_FLEX_PAYLOAD,
8008         };
8009
8010         /**
8011          * Flow director supports only fields defined in
8012          * union rte_eth_fdir_flow.
8013          */
8014         static const uint64_t valid_fdir_inset_table[] = {
8015                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8016                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8017                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8018                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8019                 I40E_INSET_IPV4_TTL,
8020                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8021                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8022                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8023                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8024                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8025                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8026                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8027                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8028                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8029                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8030                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8031                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8032                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8033                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8034                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8035                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8036                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8037                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8038                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8039                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8040                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8041                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8042                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8043                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8044                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8045                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8046                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8047                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8048                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8049                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8050                 I40E_INSET_SCTP_VT,
8051                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8052                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8053                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8054                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8055                 I40E_INSET_IPV4_TTL,
8056                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8057                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8058                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8059                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8060                 I40E_INSET_IPV6_HOP_LIMIT,
8061                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8062                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8063                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8064                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8065                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8066                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8067                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8068                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8069                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8070                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8071                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8072                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8073                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8074                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8075                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8076                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8077                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8078                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8079                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8080                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8081                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8082                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8083                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8084                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8085                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8086                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8087                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8088                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8089                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8090                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8091                 I40E_INSET_SCTP_VT,
8092                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8093                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8094                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8095                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8096                 I40E_INSET_IPV6_HOP_LIMIT,
8097                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8098                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8099                 I40E_INSET_LAST_ETHER_TYPE,
8100         };
8101
8102         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8103                 return 0;
8104         if (filter == RTE_ETH_FILTER_HASH)
8105                 valid = valid_hash_inset_table[pctype];
8106         else
8107                 valid = valid_fdir_inset_table[pctype];
8108
8109         return valid;
8110 }
8111
8112 /**
8113  * Validate if the input set is allowed for a specific PCTYPE
8114  */
8115 static int
8116 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8117                 enum rte_filter_type filter, uint64_t inset)
8118 {
8119         uint64_t valid;
8120
8121         valid = i40e_get_valid_input_set(pctype, filter);
8122         if (inset & (~valid))
8123                 return -EINVAL;
8124
8125         return 0;
8126 }
8127
8128 /* default input set fields combination per pctype */
8129 uint64_t
8130 i40e_get_default_input_set(uint16_t pctype)
8131 {
8132         static const uint64_t default_inset_table[] = {
8133                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8134                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8135                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8136                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8137                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8138                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8139                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8140                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8141                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8142                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8143                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8144                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8145                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8146                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8147                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8148                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8149                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8150                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8151                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8152                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8153                         I40E_INSET_SCTP_VT,
8154                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8155                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8156                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8157                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8158                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8159                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8160                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8161                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8162                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8163                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8164                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8165                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8166                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8167                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8168                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8169                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8170                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8171                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8172                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8173                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8174                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8175                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8176                         I40E_INSET_SCTP_VT,
8177                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8178                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8179                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8180                         I40E_INSET_LAST_ETHER_TYPE,
8181         };
8182
8183         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8184                 return 0;
8185
8186         return default_inset_table[pctype];
8187 }
8188
8189 /**
8190  * Parse the input set from index to logical bit masks
8191  */
8192 static int
8193 i40e_parse_input_set(uint64_t *inset,
8194                      enum i40e_filter_pctype pctype,
8195                      enum rte_eth_input_set_field *field,
8196                      uint16_t size)
8197 {
8198         uint16_t i, j;
8199         int ret = -EINVAL;
8200
8201         static const struct {
8202                 enum rte_eth_input_set_field field;
8203                 uint64_t inset;
8204         } inset_convert_table[] = {
8205                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8206                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8207                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8208                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8209                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8210                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8211                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8212                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8213                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8214                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8215                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8216                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8217                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8218                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8219                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8220                         I40E_INSET_IPV6_NEXT_HDR},
8221                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8222                         I40E_INSET_IPV6_HOP_LIMIT},
8223                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8224                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8225                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8226                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8227                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8228                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8229                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8230                         I40E_INSET_SCTP_VT},
8231                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8232                         I40E_INSET_TUNNEL_DMAC},
8233                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8234                         I40E_INSET_VLAN_TUNNEL},
8235                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8236                         I40E_INSET_TUNNEL_ID},
8237                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8238                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8239                         I40E_INSET_FLEX_PAYLOAD_W1},
8240                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8241                         I40E_INSET_FLEX_PAYLOAD_W2},
8242                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8243                         I40E_INSET_FLEX_PAYLOAD_W3},
8244                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8245                         I40E_INSET_FLEX_PAYLOAD_W4},
8246                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8247                         I40E_INSET_FLEX_PAYLOAD_W5},
8248                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8249                         I40E_INSET_FLEX_PAYLOAD_W6},
8250                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8251                         I40E_INSET_FLEX_PAYLOAD_W7},
8252                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8253                         I40E_INSET_FLEX_PAYLOAD_W8},
8254         };
8255
8256         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8257                 return ret;
8258
8259         /* Only one item allowed for default or all */
8260         if (size == 1) {
8261                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8262                         *inset = i40e_get_default_input_set(pctype);
8263                         return 0;
8264                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8265                         *inset = I40E_INSET_NONE;
8266                         return 0;
8267                 }
8268         }
8269
8270         for (i = 0, *inset = 0; i < size; i++) {
8271                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8272                         if (field[i] == inset_convert_table[j].field) {
8273                                 *inset |= inset_convert_table[j].inset;
8274                                 break;
8275                         }
8276                 }
8277
8278                 /* It contains unsupported input set, return immediately */
8279                 if (j == RTE_DIM(inset_convert_table))
8280                         return ret;
8281         }
8282
8283         return 0;
8284 }
8285
8286 /**
8287  * Translate the input set from bit masks to register aware bit masks
8288  * and vice versa
8289  */
8290 static uint64_t
8291 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8292 {
8293         uint64_t val = 0;
8294         uint16_t i;
8295
8296         struct inset_map {
8297                 uint64_t inset;
8298                 uint64_t inset_reg;
8299         };
8300
8301         static const struct inset_map inset_map_common[] = {
8302                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8303                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8304                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8305                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8306                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8307                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8308                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8309                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8310                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8311                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8312                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8313                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8314                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8315                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8316                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8317                 {I40E_INSET_TUNNEL_DMAC,
8318                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8319                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8320                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8321                 {I40E_INSET_TUNNEL_SRC_PORT,
8322                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8323                 {I40E_INSET_TUNNEL_DST_PORT,
8324                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8325                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8326                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8327                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8328                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8329                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8330                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8331                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8332                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8333                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8334         };
8335
8336     /* some different registers map in x722*/
8337         static const struct inset_map inset_map_diff_x722[] = {
8338                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8339                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8340                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8341                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8342         };
8343
8344         static const struct inset_map inset_map_diff_not_x722[] = {
8345                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8346                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8347                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8348                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8349         };
8350
8351         if (input == 0)
8352                 return val;
8353
8354         /* Translate input set to register aware inset */
8355         if (type == I40E_MAC_X722) {
8356                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8357                         if (input & inset_map_diff_x722[i].inset)
8358                                 val |= inset_map_diff_x722[i].inset_reg;
8359                 }
8360         } else {
8361                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8362                         if (input & inset_map_diff_not_x722[i].inset)
8363                                 val |= inset_map_diff_not_x722[i].inset_reg;
8364                 }
8365         }
8366
8367         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8368                 if (input & inset_map_common[i].inset)
8369                         val |= inset_map_common[i].inset_reg;
8370         }
8371
8372         return val;
8373 }
8374
8375 static int
8376 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8377 {
8378         uint8_t i, idx = 0;
8379         uint64_t inset_need_mask = inset;
8380
8381         static const struct {
8382                 uint64_t inset;
8383                 uint32_t mask;
8384         } inset_mask_map[] = {
8385                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8386                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8387                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8388                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8389                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8390                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8391                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8392                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8393         };
8394
8395         if (!inset || !mask || !nb_elem)
8396                 return 0;
8397
8398         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8399                 /* Clear the inset bit, if no MASK is required,
8400                  * for example proto + ttl
8401                  */
8402                 if ((inset & inset_mask_map[i].inset) ==
8403                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8404                         inset_need_mask &= ~inset_mask_map[i].inset;
8405                 if (!inset_need_mask)
8406                         return 0;
8407         }
8408         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8409                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8410                     inset_mask_map[i].inset) {
8411                         if (idx >= nb_elem) {
8412                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8413                                 return -EINVAL;
8414                         }
8415                         mask[idx] = inset_mask_map[i].mask;
8416                         idx++;
8417                 }
8418         }
8419
8420         return idx;
8421 }
8422
8423 static void
8424 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8425 {
8426         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8427
8428         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8429         if (reg != val)
8430                 i40e_write_rx_ctl(hw, addr, val);
8431         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8432                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8433 }
8434
8435 static void
8436 i40e_filter_input_set_init(struct i40e_pf *pf)
8437 {
8438         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8439         enum i40e_filter_pctype pctype;
8440         uint64_t input_set, inset_reg;
8441         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8442         int num, i;
8443
8444         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8445              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8446                 if (hw->mac.type == I40E_MAC_X722) {
8447                         if (!I40E_VALID_PCTYPE_X722(pctype))
8448                                 continue;
8449                 } else {
8450                         if (!I40E_VALID_PCTYPE(pctype))
8451                                 continue;
8452                 }
8453
8454                 input_set = i40e_get_default_input_set(pctype);
8455
8456                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8457                                                    I40E_INSET_MASK_NUM_REG);
8458                 if (num < 0)
8459                         return;
8460                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8461                                         input_set);
8462
8463                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8464                                       (uint32_t)(inset_reg & UINT32_MAX));
8465                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8466                                      (uint32_t)((inset_reg >>
8467                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8468                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8469                                       (uint32_t)(inset_reg & UINT32_MAX));
8470                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8471                                      (uint32_t)((inset_reg >>
8472                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8473
8474                 for (i = 0; i < num; i++) {
8475                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8476                                              mask_reg[i]);
8477                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8478                                              mask_reg[i]);
8479                 }
8480                 /*clear unused mask registers of the pctype */
8481                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8482                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8483                                              0);
8484                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8485                                              0);
8486                 }
8487                 I40E_WRITE_FLUSH(hw);
8488
8489                 /* store the default input set */
8490                 pf->hash_input_set[pctype] = input_set;
8491                 pf->fdir.input_set[pctype] = input_set;
8492         }
8493 }
8494
8495 int
8496 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8497                          struct rte_eth_input_set_conf *conf)
8498 {
8499         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8500         enum i40e_filter_pctype pctype;
8501         uint64_t input_set, inset_reg = 0;
8502         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8503         int ret, i, num;
8504
8505         if (!conf) {
8506                 PMD_DRV_LOG(ERR, "Invalid pointer");
8507                 return -EFAULT;
8508         }
8509         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8510             conf->op != RTE_ETH_INPUT_SET_ADD) {
8511                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8512                 return -EINVAL;
8513         }
8514
8515         if (!I40E_VALID_FLOW(conf->flow_type)) {
8516                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8517                 return -EINVAL;
8518         }
8519
8520         if (hw->mac.type == I40E_MAC_X722) {
8521                 /* get translated pctype value in fd pctype register */
8522                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8523                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8524                         conf->flow_type)));
8525         } else
8526                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8527
8528         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8529                                    conf->inset_size);
8530         if (ret) {
8531                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8532                 return -EINVAL;
8533         }
8534         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8535                                     input_set) != 0) {
8536                 PMD_DRV_LOG(ERR, "Invalid input set");
8537                 return -EINVAL;
8538         }
8539         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8540                 /* get inset value in register */
8541                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8542                 inset_reg <<= I40E_32_BIT_WIDTH;
8543                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8544                 input_set |= pf->hash_input_set[pctype];
8545         }
8546         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8547                                            I40E_INSET_MASK_NUM_REG);
8548         if (num < 0)
8549                 return -EINVAL;
8550
8551         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8552
8553         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8554                               (uint32_t)(inset_reg & UINT32_MAX));
8555         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8556                              (uint32_t)((inset_reg >>
8557                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8558
8559         for (i = 0; i < num; i++)
8560                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8561                                      mask_reg[i]);
8562         /*clear unused mask registers of the pctype */
8563         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8564                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8565                                      0);
8566         I40E_WRITE_FLUSH(hw);
8567
8568         pf->hash_input_set[pctype] = input_set;
8569         return 0;
8570 }
8571
8572 int
8573 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8574                          struct rte_eth_input_set_conf *conf)
8575 {
8576         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8577         enum i40e_filter_pctype pctype;
8578         uint64_t input_set, inset_reg = 0;
8579         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8580         int ret, i, num;
8581
8582         if (!hw || !conf) {
8583                 PMD_DRV_LOG(ERR, "Invalid pointer");
8584                 return -EFAULT;
8585         }
8586         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8587             conf->op != RTE_ETH_INPUT_SET_ADD) {
8588                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8589                 return -EINVAL;
8590         }
8591
8592         if (!I40E_VALID_FLOW(conf->flow_type)) {
8593                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8594                 return -EINVAL;
8595         }
8596
8597         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8598
8599         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8600                                    conf->inset_size);
8601         if (ret) {
8602                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8603                 return -EINVAL;
8604         }
8605         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8606                                     input_set) != 0) {
8607                 PMD_DRV_LOG(ERR, "Invalid input set");
8608                 return -EINVAL;
8609         }
8610
8611         /* get inset value in register */
8612         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8613         inset_reg <<= I40E_32_BIT_WIDTH;
8614         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8615
8616         /* Can not change the inset reg for flex payload for fdir,
8617          * it is done by writing I40E_PRTQF_FD_FLXINSET
8618          * in i40e_set_flex_mask_on_pctype.
8619          */
8620         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8621                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8622         else
8623                 input_set |= pf->fdir.input_set[pctype];
8624         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8625                                            I40E_INSET_MASK_NUM_REG);
8626         if (num < 0)
8627                 return -EINVAL;
8628
8629         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8630
8631         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8632                               (uint32_t)(inset_reg & UINT32_MAX));
8633         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8634                              (uint32_t)((inset_reg >>
8635                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8636
8637         for (i = 0; i < num; i++)
8638                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8639                                      mask_reg[i]);
8640         /*clear unused mask registers of the pctype */
8641         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8642                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8643                                      0);
8644         I40E_WRITE_FLUSH(hw);
8645
8646         pf->fdir.input_set[pctype] = input_set;
8647         return 0;
8648 }
8649
8650 static int
8651 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8652 {
8653         int ret = 0;
8654
8655         if (!hw || !info) {
8656                 PMD_DRV_LOG(ERR, "Invalid pointer");
8657                 return -EFAULT;
8658         }
8659
8660         switch (info->info_type) {
8661         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8662                 i40e_get_symmetric_hash_enable_per_port(hw,
8663                                         &(info->info.enable));
8664                 break;
8665         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8666                 ret = i40e_get_hash_filter_global_config(hw,
8667                                 &(info->info.global_conf));
8668                 break;
8669         default:
8670                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8671                                                         info->info_type);
8672                 ret = -EINVAL;
8673                 break;
8674         }
8675
8676         return ret;
8677 }
8678
8679 static int
8680 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8681 {
8682         int ret = 0;
8683
8684         if (!hw || !info) {
8685                 PMD_DRV_LOG(ERR, "Invalid pointer");
8686                 return -EFAULT;
8687         }
8688
8689         switch (info->info_type) {
8690         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8691                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8692                 break;
8693         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8694                 ret = i40e_set_hash_filter_global_config(hw,
8695                                 &(info->info.global_conf));
8696                 break;
8697         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8698                 ret = i40e_hash_filter_inset_select(hw,
8699                                                &(info->info.input_set_conf));
8700                 break;
8701
8702         default:
8703                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8704                                                         info->info_type);
8705                 ret = -EINVAL;
8706                 break;
8707         }
8708
8709         return ret;
8710 }
8711
8712 /* Operations for hash function */
8713 static int
8714 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8715                       enum rte_filter_op filter_op,
8716                       void *arg)
8717 {
8718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8719         int ret = 0;
8720
8721         switch (filter_op) {
8722         case RTE_ETH_FILTER_NOP:
8723                 break;
8724         case RTE_ETH_FILTER_GET:
8725                 ret = i40e_hash_filter_get(hw,
8726                         (struct rte_eth_hash_filter_info *)arg);
8727                 break;
8728         case RTE_ETH_FILTER_SET:
8729                 ret = i40e_hash_filter_set(hw,
8730                         (struct rte_eth_hash_filter_info *)arg);
8731                 break;
8732         default:
8733                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8734                                                                 filter_op);
8735                 ret = -ENOTSUP;
8736                 break;
8737         }
8738
8739         return ret;
8740 }
8741
8742 /* Convert ethertype filter structure */
8743 static int
8744 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8745                               struct i40e_ethertype_filter *filter)
8746 {
8747         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8748         filter->input.ether_type = input->ether_type;
8749         filter->flags = input->flags;
8750         filter->queue = input->queue;
8751
8752         return 0;
8753 }
8754
8755 /* Check if there exists the ehtertype filter */
8756 struct i40e_ethertype_filter *
8757 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8758                                 const struct i40e_ethertype_filter_input *input)
8759 {
8760         int ret;
8761
8762         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8763         if (ret < 0)
8764                 return NULL;
8765
8766         return ethertype_rule->hash_map[ret];
8767 }
8768
8769 /* Add ethertype filter in SW list */
8770 static int
8771 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8772                                 struct i40e_ethertype_filter *filter)
8773 {
8774         struct i40e_ethertype_rule *rule = &pf->ethertype;
8775         int ret;
8776
8777         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8778         if (ret < 0) {
8779                 PMD_DRV_LOG(ERR,
8780                             "Failed to insert ethertype filter"
8781                             " to hash table %d!",
8782                             ret);
8783                 return ret;
8784         }
8785         rule->hash_map[ret] = filter;
8786
8787         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8788
8789         return 0;
8790 }
8791
8792 /* Delete ethertype filter in SW list */
8793 int
8794 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8795                              struct i40e_ethertype_filter_input *input)
8796 {
8797         struct i40e_ethertype_rule *rule = &pf->ethertype;
8798         struct i40e_ethertype_filter *filter;
8799         int ret;
8800
8801         ret = rte_hash_del_key(rule->hash_table, input);
8802         if (ret < 0) {
8803                 PMD_DRV_LOG(ERR,
8804                             "Failed to delete ethertype filter"
8805                             " to hash table %d!",
8806                             ret);
8807                 return ret;
8808         }
8809         filter = rule->hash_map[ret];
8810         rule->hash_map[ret] = NULL;
8811
8812         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8813         rte_free(filter);
8814
8815         return 0;
8816 }
8817
8818 /*
8819  * Configure ethertype filter, which can director packet by filtering
8820  * with mac address and ether_type or only ether_type
8821  */
8822 int
8823 i40e_ethertype_filter_set(struct i40e_pf *pf,
8824                         struct rte_eth_ethertype_filter *filter,
8825                         bool add)
8826 {
8827         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8828         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8829         struct i40e_ethertype_filter *ethertype_filter, *node;
8830         struct i40e_ethertype_filter check_filter;
8831         struct i40e_control_filter_stats stats;
8832         uint16_t flags = 0;
8833         int ret;
8834
8835         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8836                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8837                 return -EINVAL;
8838         }
8839         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8840                 filter->ether_type == ETHER_TYPE_IPv6) {
8841                 PMD_DRV_LOG(ERR,
8842                         "unsupported ether_type(0x%04x) in control packet filter.",
8843                         filter->ether_type);
8844                 return -EINVAL;
8845         }
8846         if (filter->ether_type == ETHER_TYPE_VLAN)
8847                 PMD_DRV_LOG(WARNING,
8848                         "filter vlan ether_type in first tag is not supported.");
8849
8850         /* Check if there is the filter in SW list */
8851         memset(&check_filter, 0, sizeof(check_filter));
8852         i40e_ethertype_filter_convert(filter, &check_filter);
8853         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8854                                                &check_filter.input);
8855         if (add && node) {
8856                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8857                 return -EINVAL;
8858         }
8859
8860         if (!add && !node) {
8861                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8862                 return -EINVAL;
8863         }
8864
8865         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8866                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8867         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8868                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8869         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8870
8871         memset(&stats, 0, sizeof(stats));
8872         ret = i40e_aq_add_rem_control_packet_filter(hw,
8873                         filter->mac_addr.addr_bytes,
8874                         filter->ether_type, flags,
8875                         pf->main_vsi->seid,
8876                         filter->queue, add, &stats, NULL);
8877
8878         PMD_DRV_LOG(INFO,
8879                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8880                 ret, stats.mac_etype_used, stats.etype_used,
8881                 stats.mac_etype_free, stats.etype_free);
8882         if (ret < 0)
8883                 return -ENOSYS;
8884
8885         /* Add or delete a filter in SW list */
8886         if (add) {
8887                 ethertype_filter = rte_zmalloc("ethertype_filter",
8888                                        sizeof(*ethertype_filter), 0);
8889                 rte_memcpy(ethertype_filter, &check_filter,
8890                            sizeof(check_filter));
8891                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8892         } else {
8893                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8894         }
8895
8896         return ret;
8897 }
8898
8899 /*
8900  * Handle operations for ethertype filter.
8901  */
8902 static int
8903 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8904                                 enum rte_filter_op filter_op,
8905                                 void *arg)
8906 {
8907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8908         int ret = 0;
8909
8910         if (filter_op == RTE_ETH_FILTER_NOP)
8911                 return ret;
8912
8913         if (arg == NULL) {
8914                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8915                             filter_op);
8916                 return -EINVAL;
8917         }
8918
8919         switch (filter_op) {
8920         case RTE_ETH_FILTER_ADD:
8921                 ret = i40e_ethertype_filter_set(pf,
8922                         (struct rte_eth_ethertype_filter *)arg,
8923                         TRUE);
8924                 break;
8925         case RTE_ETH_FILTER_DELETE:
8926                 ret = i40e_ethertype_filter_set(pf,
8927                         (struct rte_eth_ethertype_filter *)arg,
8928                         FALSE);
8929                 break;
8930         default:
8931                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8932                 ret = -ENOSYS;
8933                 break;
8934         }
8935         return ret;
8936 }
8937
8938 static int
8939 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8940                      enum rte_filter_type filter_type,
8941                      enum rte_filter_op filter_op,
8942                      void *arg)
8943 {
8944         int ret = 0;
8945
8946         if (dev == NULL)
8947                 return -EINVAL;
8948
8949         switch (filter_type) {
8950         case RTE_ETH_FILTER_NONE:
8951                 /* For global configuration */
8952                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8953                 break;
8954         case RTE_ETH_FILTER_HASH:
8955                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8956                 break;
8957         case RTE_ETH_FILTER_MACVLAN:
8958                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8959                 break;
8960         case RTE_ETH_FILTER_ETHERTYPE:
8961                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8962                 break;
8963         case RTE_ETH_FILTER_TUNNEL:
8964                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8965                 break;
8966         case RTE_ETH_FILTER_FDIR:
8967                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8968                 break;
8969         case RTE_ETH_FILTER_GENERIC:
8970                 if (filter_op != RTE_ETH_FILTER_GET)
8971                         return -EINVAL;
8972                 *(const void **)arg = &i40e_flow_ops;
8973                 break;
8974         default:
8975                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8976                                                         filter_type);
8977                 ret = -EINVAL;
8978                 break;
8979         }
8980
8981         return ret;
8982 }
8983
8984 /*
8985  * Check and enable Extended Tag.
8986  * Enabling Extended Tag is important for 40G performance.
8987  */
8988 static void
8989 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8990 {
8991         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8992         uint32_t buf = 0;
8993         int ret;
8994
8995         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
8996                                       PCI_DEV_CAP_REG);
8997         if (ret < 0) {
8998                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8999                             PCI_DEV_CAP_REG);
9000                 return;
9001         }
9002         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9003                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9004                 return;
9005         }
9006
9007         buf = 0;
9008         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9009                                       PCI_DEV_CTRL_REG);
9010         if (ret < 0) {
9011                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9012                             PCI_DEV_CTRL_REG);
9013                 return;
9014         }
9015         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9016                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9017                 return;
9018         }
9019         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9020         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9021                                        PCI_DEV_CTRL_REG);
9022         if (ret < 0) {
9023                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9024                             PCI_DEV_CTRL_REG);
9025                 return;
9026         }
9027 }
9028
9029 /*
9030  * As some registers wouldn't be reset unless a global hardware reset,
9031  * hardware initialization is needed to put those registers into an
9032  * expected initial state.
9033  */
9034 static void
9035 i40e_hw_init(struct rte_eth_dev *dev)
9036 {
9037         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9038
9039         i40e_enable_extended_tag(dev);
9040
9041         /* clear the PF Queue Filter control register */
9042         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9043
9044         /* Disable symmetric hash per port */
9045         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9046 }
9047
9048 enum i40e_filter_pctype
9049 i40e_flowtype_to_pctype(uint16_t flow_type)
9050 {
9051         static const enum i40e_filter_pctype pctype_table[] = {
9052                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9053                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9054                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9055                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9056                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9057                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9058                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9059                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9060                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9061                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9062                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9063                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9064                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9065                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9066                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9067                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9068                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9069                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9070                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9071         };
9072
9073         return pctype_table[flow_type];
9074 }
9075
9076 uint16_t
9077 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9078 {
9079         static const uint16_t flowtype_table[] = {
9080                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9081                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9082                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9083                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9084                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9085                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9086                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9087                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9088                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9089                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9090                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9091                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9092                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9093                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9094                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9095                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9096                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9097                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9098                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9099                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9100                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9101                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9102                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9103                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9104                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9105                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9106                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9107                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9108                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9109                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9110                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9111         };
9112
9113         return flowtype_table[pctype];
9114 }
9115
9116 /*
9117  * On X710, performance number is far from the expectation on recent firmware
9118  * versions; on XL710, performance number is also far from the expectation on
9119  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9120  * mode is enabled and port MAC address is equal to the packet destination MAC
9121  * address. The fix for this issue may not be integrated in the following
9122  * firmware version. So the workaround in software driver is needed. It needs
9123  * to modify the initial values of 3 internal only registers for both X710 and
9124  * XL710. Note that the values for X710 or XL710 could be different, and the
9125  * workaround can be removed when it is fixed in firmware in the future.
9126  */
9127
9128 /* For both X710 and XL710 */
9129 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9130 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9131
9132 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9133 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9134
9135 /* For X722 */
9136 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9137 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9138
9139 /* For X710 */
9140 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9141 /* For XL710 */
9142 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9143 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9144
9145 static int
9146 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9147 {
9148         enum i40e_status_code status;
9149         struct i40e_aq_get_phy_abilities_resp phy_ab;
9150         int ret = -ENOTSUP;
9151
9152         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9153                                               NULL);
9154
9155         if (status)
9156                 return ret;
9157
9158         return 0;
9159 }
9160
9161 static void
9162 i40e_configure_registers(struct i40e_hw *hw)
9163 {
9164         static struct {
9165                 uint32_t addr;
9166                 uint64_t val;
9167         } reg_table[] = {
9168                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9169                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9170                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9171         };
9172         uint64_t reg;
9173         uint32_t i;
9174         int ret;
9175
9176         for (i = 0; i < RTE_DIM(reg_table); i++) {
9177                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9178                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9179                                 reg_table[i].val =
9180                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9181                         else /* For X710/XL710/XXV710 */
9182                                 reg_table[i].val =
9183                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9184                 }
9185
9186                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9187                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9188                                 reg_table[i].val =
9189                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9190                         else /* For X710/XL710/XXV710 */
9191                                 reg_table[i].val =
9192                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9193                 }
9194
9195                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9196                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9197                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9198                                 reg_table[i].val =
9199                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9200                         else /* For X710 */
9201                                 reg_table[i].val =
9202                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9203                 }
9204
9205                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9206                                                         &reg, NULL);
9207                 if (ret < 0) {
9208                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9209                                                         reg_table[i].addr);
9210                         break;
9211                 }
9212                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9213                                                 reg_table[i].addr, reg);
9214                 if (reg == reg_table[i].val)
9215                         continue;
9216
9217                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9218                                                 reg_table[i].val, NULL);
9219                 if (ret < 0) {
9220                         PMD_DRV_LOG(ERR,
9221                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9222                                 reg_table[i].val, reg_table[i].addr);
9223                         break;
9224                 }
9225                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9226                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9227         }
9228 }
9229
9230 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9231 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9232 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9233 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9234 static int
9235 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9236 {
9237         uint32_t reg;
9238         int ret;
9239
9240         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9241                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9242                 return -EINVAL;
9243         }
9244
9245         /* Configure for double VLAN RX stripping */
9246         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9247         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9248                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9249                 ret = i40e_aq_debug_write_register(hw,
9250                                                    I40E_VSI_TSR(vsi->vsi_id),
9251                                                    reg, NULL);
9252                 if (ret < 0) {
9253                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9254                                     vsi->vsi_id);
9255                         return I40E_ERR_CONFIG;
9256                 }
9257         }
9258
9259         /* Configure for double VLAN TX insertion */
9260         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9261         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9262                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9263                 ret = i40e_aq_debug_write_register(hw,
9264                                                    I40E_VSI_L2TAGSTXVALID(
9265                                                    vsi->vsi_id), reg, NULL);
9266                 if (ret < 0) {
9267                         PMD_DRV_LOG(ERR,
9268                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9269                                 vsi->vsi_id);
9270                         return I40E_ERR_CONFIG;
9271                 }
9272         }
9273
9274         return 0;
9275 }
9276
9277 /**
9278  * i40e_aq_add_mirror_rule
9279  * @hw: pointer to the hardware structure
9280  * @seid: VEB seid to add mirror rule to
9281  * @dst_id: destination vsi seid
9282  * @entries: Buffer which contains the entities to be mirrored
9283  * @count: number of entities contained in the buffer
9284  * @rule_id:the rule_id of the rule to be added
9285  *
9286  * Add a mirror rule for a given veb.
9287  *
9288  **/
9289 static enum i40e_status_code
9290 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9291                         uint16_t seid, uint16_t dst_id,
9292                         uint16_t rule_type, uint16_t *entries,
9293                         uint16_t count, uint16_t *rule_id)
9294 {
9295         struct i40e_aq_desc desc;
9296         struct i40e_aqc_add_delete_mirror_rule cmd;
9297         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9298                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9299                 &desc.params.raw;
9300         uint16_t buff_len;
9301         enum i40e_status_code status;
9302
9303         i40e_fill_default_direct_cmd_desc(&desc,
9304                                           i40e_aqc_opc_add_mirror_rule);
9305         memset(&cmd, 0, sizeof(cmd));
9306
9307         buff_len = sizeof(uint16_t) * count;
9308         desc.datalen = rte_cpu_to_le_16(buff_len);
9309         if (buff_len > 0)
9310                 desc.flags |= rte_cpu_to_le_16(
9311                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9312         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9313                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9314         cmd.num_entries = rte_cpu_to_le_16(count);
9315         cmd.seid = rte_cpu_to_le_16(seid);
9316         cmd.destination = rte_cpu_to_le_16(dst_id);
9317
9318         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9319         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9320         PMD_DRV_LOG(INFO,
9321                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9322                 hw->aq.asq_last_status, resp->rule_id,
9323                 resp->mirror_rules_used, resp->mirror_rules_free);
9324         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9325
9326         return status;
9327 }
9328
9329 /**
9330  * i40e_aq_del_mirror_rule
9331  * @hw: pointer to the hardware structure
9332  * @seid: VEB seid to add mirror rule to
9333  * @entries: Buffer which contains the entities to be mirrored
9334  * @count: number of entities contained in the buffer
9335  * @rule_id:the rule_id of the rule to be delete
9336  *
9337  * Delete a mirror rule for a given veb.
9338  *
9339  **/
9340 static enum i40e_status_code
9341 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9342                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9343                 uint16_t count, uint16_t rule_id)
9344 {
9345         struct i40e_aq_desc desc;
9346         struct i40e_aqc_add_delete_mirror_rule cmd;
9347         uint16_t buff_len = 0;
9348         enum i40e_status_code status;
9349         void *buff = NULL;
9350
9351         i40e_fill_default_direct_cmd_desc(&desc,
9352                                           i40e_aqc_opc_delete_mirror_rule);
9353         memset(&cmd, 0, sizeof(cmd));
9354         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9355                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9356                                                           I40E_AQ_FLAG_RD));
9357                 cmd.num_entries = count;
9358                 buff_len = sizeof(uint16_t) * count;
9359                 desc.datalen = rte_cpu_to_le_16(buff_len);
9360                 buff = (void *)entries;
9361         } else
9362                 /* rule id is filled in destination field for deleting mirror rule */
9363                 cmd.destination = rte_cpu_to_le_16(rule_id);
9364
9365         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9366                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9367         cmd.seid = rte_cpu_to_le_16(seid);
9368
9369         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9370         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9371
9372         return status;
9373 }
9374
9375 /**
9376  * i40e_mirror_rule_set
9377  * @dev: pointer to the hardware structure
9378  * @mirror_conf: mirror rule info
9379  * @sw_id: mirror rule's sw_id
9380  * @on: enable/disable
9381  *
9382  * set a mirror rule.
9383  *
9384  **/
9385 static int
9386 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9387                         struct rte_eth_mirror_conf *mirror_conf,
9388                         uint8_t sw_id, uint8_t on)
9389 {
9390         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9392         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9393         struct i40e_mirror_rule *parent = NULL;
9394         uint16_t seid, dst_seid, rule_id;
9395         uint16_t i, j = 0;
9396         int ret;
9397
9398         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9399
9400         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9401                 PMD_DRV_LOG(ERR,
9402                         "mirror rule can not be configured without veb or vfs.");
9403                 return -ENOSYS;
9404         }
9405         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9406                 PMD_DRV_LOG(ERR, "mirror table is full.");
9407                 return -ENOSPC;
9408         }
9409         if (mirror_conf->dst_pool > pf->vf_num) {
9410                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9411                                  mirror_conf->dst_pool);
9412                 return -EINVAL;
9413         }
9414
9415         seid = pf->main_vsi->veb->seid;
9416
9417         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9418                 if (sw_id <= it->index) {
9419                         mirr_rule = it;
9420                         break;
9421                 }
9422                 parent = it;
9423         }
9424         if (mirr_rule && sw_id == mirr_rule->index) {
9425                 if (on) {
9426                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9427                         return -EEXIST;
9428                 } else {
9429                         ret = i40e_aq_del_mirror_rule(hw, seid,
9430                                         mirr_rule->rule_type,
9431                                         mirr_rule->entries,
9432                                         mirr_rule->num_entries, mirr_rule->id);
9433                         if (ret < 0) {
9434                                 PMD_DRV_LOG(ERR,
9435                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9436                                         ret, hw->aq.asq_last_status);
9437                                 return -ENOSYS;
9438                         }
9439                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9440                         rte_free(mirr_rule);
9441                         pf->nb_mirror_rule--;
9442                         return 0;
9443                 }
9444         } else if (!on) {
9445                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9446                 return -ENOENT;
9447         }
9448
9449         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9450                                 sizeof(struct i40e_mirror_rule) , 0);
9451         if (!mirr_rule) {
9452                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9453                 return I40E_ERR_NO_MEMORY;
9454         }
9455         switch (mirror_conf->rule_type) {
9456         case ETH_MIRROR_VLAN:
9457                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9458                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9459                                 mirr_rule->entries[j] =
9460                                         mirror_conf->vlan.vlan_id[i];
9461                                 j++;
9462                         }
9463                 }
9464                 if (j == 0) {
9465                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9466                         rte_free(mirr_rule);
9467                         return -EINVAL;
9468                 }
9469                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9470                 break;
9471         case ETH_MIRROR_VIRTUAL_POOL_UP:
9472         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9473                 /* check if the specified pool bit is out of range */
9474                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9475                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9476                         rte_free(mirr_rule);
9477                         return -EINVAL;
9478                 }
9479                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9480                         if (mirror_conf->pool_mask & (1ULL << i)) {
9481                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9482                                 j++;
9483                         }
9484                 }
9485                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9486                         /* add pf vsi to entries */
9487                         mirr_rule->entries[j] = pf->main_vsi_seid;
9488                         j++;
9489                 }
9490                 if (j == 0) {
9491                         PMD_DRV_LOG(ERR, "pool is not specified.");
9492                         rte_free(mirr_rule);
9493                         return -EINVAL;
9494                 }
9495                 /* egress and ingress in aq commands means from switch but not port */
9496                 mirr_rule->rule_type =
9497                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9498                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9499                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9500                 break;
9501         case ETH_MIRROR_UPLINK_PORT:
9502                 /* egress and ingress in aq commands means from switch but not port*/
9503                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9504                 break;
9505         case ETH_MIRROR_DOWNLINK_PORT:
9506                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9507                 break;
9508         default:
9509                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9510                         mirror_conf->rule_type);
9511                 rte_free(mirr_rule);
9512                 return -EINVAL;
9513         }
9514
9515         /* If the dst_pool is equal to vf_num, consider it as PF */
9516         if (mirror_conf->dst_pool == pf->vf_num)
9517                 dst_seid = pf->main_vsi_seid;
9518         else
9519                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9520
9521         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9522                                       mirr_rule->rule_type, mirr_rule->entries,
9523                                       j, &rule_id);
9524         if (ret < 0) {
9525                 PMD_DRV_LOG(ERR,
9526                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9527                         ret, hw->aq.asq_last_status);
9528                 rte_free(mirr_rule);
9529                 return -ENOSYS;
9530         }
9531
9532         mirr_rule->index = sw_id;
9533         mirr_rule->num_entries = j;
9534         mirr_rule->id = rule_id;
9535         mirr_rule->dst_vsi_seid = dst_seid;
9536
9537         if (parent)
9538                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9539         else
9540                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9541
9542         pf->nb_mirror_rule++;
9543         return 0;
9544 }
9545
9546 /**
9547  * i40e_mirror_rule_reset
9548  * @dev: pointer to the device
9549  * @sw_id: mirror rule's sw_id
9550  *
9551  * reset a mirror rule.
9552  *
9553  **/
9554 static int
9555 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9556 {
9557         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9558         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9559         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9560         uint16_t seid;
9561         int ret;
9562
9563         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9564
9565         seid = pf->main_vsi->veb->seid;
9566
9567         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9568                 if (sw_id == it->index) {
9569                         mirr_rule = it;
9570                         break;
9571                 }
9572         }
9573         if (mirr_rule) {
9574                 ret = i40e_aq_del_mirror_rule(hw, seid,
9575                                 mirr_rule->rule_type,
9576                                 mirr_rule->entries,
9577                                 mirr_rule->num_entries, mirr_rule->id);
9578                 if (ret < 0) {
9579                         PMD_DRV_LOG(ERR,
9580                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9581                                 ret, hw->aq.asq_last_status);
9582                         return -ENOSYS;
9583                 }
9584                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9585                 rte_free(mirr_rule);
9586                 pf->nb_mirror_rule--;
9587         } else {
9588                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9589                 return -ENOENT;
9590         }
9591         return 0;
9592 }
9593
9594 static uint64_t
9595 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9596 {
9597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9598         uint64_t systim_cycles;
9599
9600         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9601         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9602                         << 32;
9603
9604         return systim_cycles;
9605 }
9606
9607 static uint64_t
9608 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9609 {
9610         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9611         uint64_t rx_tstamp;
9612
9613         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9614         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9615                         << 32;
9616
9617         return rx_tstamp;
9618 }
9619
9620 static uint64_t
9621 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9622 {
9623         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9624         uint64_t tx_tstamp;
9625
9626         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9627         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9628                         << 32;
9629
9630         return tx_tstamp;
9631 }
9632
9633 static void
9634 i40e_start_timecounters(struct rte_eth_dev *dev)
9635 {
9636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9637         struct i40e_adapter *adapter =
9638                         (struct i40e_adapter *)dev->data->dev_private;
9639         struct rte_eth_link link;
9640         uint32_t tsync_inc_l;
9641         uint32_t tsync_inc_h;
9642
9643         /* Get current link speed. */
9644         memset(&link, 0, sizeof(link));
9645         i40e_dev_link_update(dev, 1);
9646         rte_i40e_dev_atomic_read_link_status(dev, &link);
9647
9648         switch (link.link_speed) {
9649         case ETH_SPEED_NUM_40G:
9650                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9651                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9652                 break;
9653         case ETH_SPEED_NUM_10G:
9654                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9655                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9656                 break;
9657         case ETH_SPEED_NUM_1G:
9658                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9659                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9660                 break;
9661         default:
9662                 tsync_inc_l = 0x0;
9663                 tsync_inc_h = 0x0;
9664         }
9665
9666         /* Set the timesync increment value. */
9667         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9668         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9669
9670         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9671         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9672         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9673
9674         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9675         adapter->systime_tc.cc_shift = 0;
9676         adapter->systime_tc.nsec_mask = 0;
9677
9678         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9679         adapter->rx_tstamp_tc.cc_shift = 0;
9680         adapter->rx_tstamp_tc.nsec_mask = 0;
9681
9682         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9683         adapter->tx_tstamp_tc.cc_shift = 0;
9684         adapter->tx_tstamp_tc.nsec_mask = 0;
9685 }
9686
9687 static int
9688 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9689 {
9690         struct i40e_adapter *adapter =
9691                         (struct i40e_adapter *)dev->data->dev_private;
9692
9693         adapter->systime_tc.nsec += delta;
9694         adapter->rx_tstamp_tc.nsec += delta;
9695         adapter->tx_tstamp_tc.nsec += delta;
9696
9697         return 0;
9698 }
9699
9700 static int
9701 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9702 {
9703         uint64_t ns;
9704         struct i40e_adapter *adapter =
9705                         (struct i40e_adapter *)dev->data->dev_private;
9706
9707         ns = rte_timespec_to_ns(ts);
9708
9709         /* Set the timecounters to a new value. */
9710         adapter->systime_tc.nsec = ns;
9711         adapter->rx_tstamp_tc.nsec = ns;
9712         adapter->tx_tstamp_tc.nsec = ns;
9713
9714         return 0;
9715 }
9716
9717 static int
9718 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9719 {
9720         uint64_t ns, systime_cycles;
9721         struct i40e_adapter *adapter =
9722                         (struct i40e_adapter *)dev->data->dev_private;
9723
9724         systime_cycles = i40e_read_systime_cyclecounter(dev);
9725         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9726         *ts = rte_ns_to_timespec(ns);
9727
9728         return 0;
9729 }
9730
9731 static int
9732 i40e_timesync_enable(struct rte_eth_dev *dev)
9733 {
9734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9735         uint32_t tsync_ctl_l;
9736         uint32_t tsync_ctl_h;
9737
9738         /* Stop the timesync system time. */
9739         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9740         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9741         /* Reset the timesync system time value. */
9742         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9743         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9744
9745         i40e_start_timecounters(dev);
9746
9747         /* Clear timesync registers. */
9748         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9749         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9750         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9751         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9752         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9753         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9754
9755         /* Enable timestamping of PTP packets. */
9756         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9757         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9758
9759         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9760         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9761         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9762
9763         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9764         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9765
9766         return 0;
9767 }
9768
9769 static int
9770 i40e_timesync_disable(struct rte_eth_dev *dev)
9771 {
9772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9773         uint32_t tsync_ctl_l;
9774         uint32_t tsync_ctl_h;
9775
9776         /* Disable timestamping of transmitted PTP packets. */
9777         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9778         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9779
9780         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9781         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9782
9783         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9784         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9785
9786         /* Reset the timesync increment value. */
9787         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9788         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9789
9790         return 0;
9791 }
9792
9793 static int
9794 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9795                                 struct timespec *timestamp, uint32_t flags)
9796 {
9797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9798         struct i40e_adapter *adapter =
9799                 (struct i40e_adapter *)dev->data->dev_private;
9800
9801         uint32_t sync_status;
9802         uint32_t index = flags & 0x03;
9803         uint64_t rx_tstamp_cycles;
9804         uint64_t ns;
9805
9806         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9807         if ((sync_status & (1 << index)) == 0)
9808                 return -EINVAL;
9809
9810         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9811         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9812         *timestamp = rte_ns_to_timespec(ns);
9813
9814         return 0;
9815 }
9816
9817 static int
9818 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9819                                 struct timespec *timestamp)
9820 {
9821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9822         struct i40e_adapter *adapter =
9823                 (struct i40e_adapter *)dev->data->dev_private;
9824
9825         uint32_t sync_status;
9826         uint64_t tx_tstamp_cycles;
9827         uint64_t ns;
9828
9829         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9830         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9831                 return -EINVAL;
9832
9833         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9834         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9835         *timestamp = rte_ns_to_timespec(ns);
9836
9837         return 0;
9838 }
9839
9840 /*
9841  * i40e_parse_dcb_configure - parse dcb configure from user
9842  * @dev: the device being configured
9843  * @dcb_cfg: pointer of the result of parse
9844  * @*tc_map: bit map of enabled traffic classes
9845  *
9846  * Returns 0 on success, negative value on failure
9847  */
9848 static int
9849 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9850                          struct i40e_dcbx_config *dcb_cfg,
9851                          uint8_t *tc_map)
9852 {
9853         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9854         uint8_t i, tc_bw, bw_lf;
9855
9856         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9857
9858         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9859         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9860                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9861                 return -EINVAL;
9862         }
9863
9864         /* assume each tc has the same bw */
9865         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9866         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9867                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9868         /* to ensure the sum of tcbw is equal to 100 */
9869         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9870         for (i = 0; i < bw_lf; i++)
9871                 dcb_cfg->etscfg.tcbwtable[i]++;
9872
9873         /* assume each tc has the same Transmission Selection Algorithm */
9874         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9875                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9876
9877         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9878                 dcb_cfg->etscfg.prioritytable[i] =
9879                                 dcb_rx_conf->dcb_tc[i];
9880
9881         /* FW needs one App to configure HW */
9882         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9883         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9884         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9885         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9886
9887         if (dcb_rx_conf->nb_tcs == 0)
9888                 *tc_map = 1; /* tc0 only */
9889         else
9890                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9891
9892         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9893                 dcb_cfg->pfc.willing = 0;
9894                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9895                 dcb_cfg->pfc.pfcenable = *tc_map;
9896         }
9897         return 0;
9898 }
9899
9900
9901 static enum i40e_status_code
9902 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9903                               struct i40e_aqc_vsi_properties_data *info,
9904                               uint8_t enabled_tcmap)
9905 {
9906         enum i40e_status_code ret;
9907         int i, total_tc = 0;
9908         uint16_t qpnum_per_tc, bsf, qp_idx;
9909         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9910         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9911         uint16_t used_queues;
9912
9913         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9914         if (ret != I40E_SUCCESS)
9915                 return ret;
9916
9917         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9918                 if (enabled_tcmap & (1 << i))
9919                         total_tc++;
9920         }
9921         if (total_tc == 0)
9922                 total_tc = 1;
9923         vsi->enabled_tc = enabled_tcmap;
9924
9925         /* different VSI has different queues assigned */
9926         if (vsi->type == I40E_VSI_MAIN)
9927                 used_queues = dev_data->nb_rx_queues -
9928                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9929         else if (vsi->type == I40E_VSI_VMDQ2)
9930                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9931         else {
9932                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9933                 return I40E_ERR_NO_AVAILABLE_VSI;
9934         }
9935
9936         qpnum_per_tc = used_queues / total_tc;
9937         /* Number of queues per enabled TC */
9938         if (qpnum_per_tc == 0) {
9939                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9940                 return I40E_ERR_INVALID_QP_ID;
9941         }
9942         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9943                                 I40E_MAX_Q_PER_TC);
9944         bsf = rte_bsf32(qpnum_per_tc);
9945
9946         /**
9947          * Configure TC and queue mapping parameters, for enabled TC,
9948          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9949          * default queue will serve it.
9950          */
9951         qp_idx = 0;
9952         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9953                 if (vsi->enabled_tc & (1 << i)) {
9954                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9955                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9956                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9957                         qp_idx += qpnum_per_tc;
9958                 } else
9959                         info->tc_mapping[i] = 0;
9960         }
9961
9962         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9963         if (vsi->type == I40E_VSI_SRIOV) {
9964                 info->mapping_flags |=
9965                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9966                 for (i = 0; i < vsi->nb_qps; i++)
9967                         info->queue_mapping[i] =
9968                                 rte_cpu_to_le_16(vsi->base_queue + i);
9969         } else {
9970                 info->mapping_flags |=
9971                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9972                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9973         }
9974         info->valid_sections |=
9975                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9976
9977         return I40E_SUCCESS;
9978 }
9979
9980 /*
9981  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9982  * @veb: VEB to be configured
9983  * @tc_map: enabled TC bitmap
9984  *
9985  * Returns 0 on success, negative value on failure
9986  */
9987 static enum i40e_status_code
9988 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9989 {
9990         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9991         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9992         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9993         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9994         enum i40e_status_code ret = I40E_SUCCESS;
9995         int i;
9996         uint32_t bw_max;
9997
9998         /* Check if enabled_tc is same as existing or new TCs */
9999         if (veb->enabled_tc == tc_map)
10000                 return ret;
10001
10002         /* configure tc bandwidth */
10003         memset(&veb_bw, 0, sizeof(veb_bw));
10004         veb_bw.tc_valid_bits = tc_map;
10005         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10006         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10007                 if (tc_map & BIT_ULL(i))
10008                         veb_bw.tc_bw_share_credits[i] = 1;
10009         }
10010         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10011                                                    &veb_bw, NULL);
10012         if (ret) {
10013                 PMD_INIT_LOG(ERR,
10014                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10015                         hw->aq.asq_last_status);
10016                 return ret;
10017         }
10018
10019         memset(&ets_query, 0, sizeof(ets_query));
10020         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10021                                                    &ets_query, NULL);
10022         if (ret != I40E_SUCCESS) {
10023                 PMD_DRV_LOG(ERR,
10024                         "Failed to get switch_comp ETS configuration %u",
10025                         hw->aq.asq_last_status);
10026                 return ret;
10027         }
10028         memset(&bw_query, 0, sizeof(bw_query));
10029         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10030                                                   &bw_query, NULL);
10031         if (ret != I40E_SUCCESS) {
10032                 PMD_DRV_LOG(ERR,
10033                         "Failed to get switch_comp bandwidth configuration %u",
10034                         hw->aq.asq_last_status);
10035                 return ret;
10036         }
10037
10038         /* store and print out BW info */
10039         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10040         veb->bw_info.bw_max = ets_query.tc_bw_max;
10041         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10042         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10043         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10044                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10045                      I40E_16_BIT_WIDTH);
10046         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10047                 veb->bw_info.bw_ets_share_credits[i] =
10048                                 bw_query.tc_bw_share_credits[i];
10049                 veb->bw_info.bw_ets_credits[i] =
10050                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10051                 /* 4 bits per TC, 4th bit is reserved */
10052                 veb->bw_info.bw_ets_max[i] =
10053                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10054                                   RTE_LEN2MASK(3, uint8_t));
10055                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10056                             veb->bw_info.bw_ets_share_credits[i]);
10057                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10058                             veb->bw_info.bw_ets_credits[i]);
10059                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10060                             veb->bw_info.bw_ets_max[i]);
10061         }
10062
10063         veb->enabled_tc = tc_map;
10064
10065         return ret;
10066 }
10067
10068
10069 /*
10070  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10071  * @vsi: VSI to be configured
10072  * @tc_map: enabled TC bitmap
10073  *
10074  * Returns 0 on success, negative value on failure
10075  */
10076 static enum i40e_status_code
10077 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10078 {
10079         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10080         struct i40e_vsi_context ctxt;
10081         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10082         enum i40e_status_code ret = I40E_SUCCESS;
10083         int i;
10084
10085         /* Check if enabled_tc is same as existing or new TCs */
10086         if (vsi->enabled_tc == tc_map)
10087                 return ret;
10088
10089         /* configure tc bandwidth */
10090         memset(&bw_data, 0, sizeof(bw_data));
10091         bw_data.tc_valid_bits = tc_map;
10092         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10093         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10094                 if (tc_map & BIT_ULL(i))
10095                         bw_data.tc_bw_credits[i] = 1;
10096         }
10097         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10098         if (ret) {
10099                 PMD_INIT_LOG(ERR,
10100                         "AQ command Config VSI BW allocation per TC failed = %d",
10101                         hw->aq.asq_last_status);
10102                 goto out;
10103         }
10104         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10105                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10106
10107         /* Update Queue Pairs Mapping for currently enabled UPs */
10108         ctxt.seid = vsi->seid;
10109         ctxt.pf_num = hw->pf_id;
10110         ctxt.vf_num = 0;
10111         ctxt.uplink_seid = vsi->uplink_seid;
10112         ctxt.info = vsi->info;
10113         i40e_get_cap(hw);
10114         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10115         if (ret)
10116                 goto out;
10117
10118         /* Update the VSI after updating the VSI queue-mapping information */
10119         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10120         if (ret) {
10121                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10122                         hw->aq.asq_last_status);
10123                 goto out;
10124         }
10125         /* update the local VSI info with updated queue map */
10126         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10127                                         sizeof(vsi->info.tc_mapping));
10128         (void)rte_memcpy(&vsi->info.queue_mapping,
10129                         &ctxt.info.queue_mapping,
10130                 sizeof(vsi->info.queue_mapping));
10131         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10132         vsi->info.valid_sections = 0;
10133
10134         /* query and update current VSI BW information */
10135         ret = i40e_vsi_get_bw_config(vsi);
10136         if (ret) {
10137                 PMD_INIT_LOG(ERR,
10138                          "Failed updating vsi bw info, err %s aq_err %s",
10139                          i40e_stat_str(hw, ret),
10140                          i40e_aq_str(hw, hw->aq.asq_last_status));
10141                 goto out;
10142         }
10143
10144         vsi->enabled_tc = tc_map;
10145
10146 out:
10147         return ret;
10148 }
10149
10150 /*
10151  * i40e_dcb_hw_configure - program the dcb setting to hw
10152  * @pf: pf the configuration is taken on
10153  * @new_cfg: new configuration
10154  * @tc_map: enabled TC bitmap
10155  *
10156  * Returns 0 on success, negative value on failure
10157  */
10158 static enum i40e_status_code
10159 i40e_dcb_hw_configure(struct i40e_pf *pf,
10160                       struct i40e_dcbx_config *new_cfg,
10161                       uint8_t tc_map)
10162 {
10163         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10164         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10165         struct i40e_vsi *main_vsi = pf->main_vsi;
10166         struct i40e_vsi_list *vsi_list;
10167         enum i40e_status_code ret;
10168         int i;
10169         uint32_t val;
10170
10171         /* Use the FW API if FW > v4.4*/
10172         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10173               (hw->aq.fw_maj_ver >= 5))) {
10174                 PMD_INIT_LOG(ERR,
10175                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10176                 return I40E_ERR_FIRMWARE_API_VERSION;
10177         }
10178
10179         /* Check if need reconfiguration */
10180         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10181                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10182                 return I40E_SUCCESS;
10183         }
10184
10185         /* Copy the new config to the current config */
10186         *old_cfg = *new_cfg;
10187         old_cfg->etsrec = old_cfg->etscfg;
10188         ret = i40e_set_dcb_config(hw);
10189         if (ret) {
10190                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10191                          i40e_stat_str(hw, ret),
10192                          i40e_aq_str(hw, hw->aq.asq_last_status));
10193                 return ret;
10194         }
10195         /* set receive Arbiter to RR mode and ETS scheme by default */
10196         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10197                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10198                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10199                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10200                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10201                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10202                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10203                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10204                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10205                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10206                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10207                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10208                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10209         }
10210         /* get local mib to check whether it is configured correctly */
10211         /* IEEE mode */
10212         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10213         /* Get Local DCB Config */
10214         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10215                                      &hw->local_dcbx_config);
10216
10217         /* if Veb is created, need to update TC of it at first */
10218         if (main_vsi->veb) {
10219                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10220                 if (ret)
10221                         PMD_INIT_LOG(WARNING,
10222                                  "Failed configuring TC for VEB seid=%d",
10223                                  main_vsi->veb->seid);
10224         }
10225         /* Update each VSI */
10226         i40e_vsi_config_tc(main_vsi, tc_map);
10227         if (main_vsi->veb) {
10228                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10229                         /* Beside main VSI and VMDQ VSIs, only enable default
10230                          * TC for other VSIs
10231                          */
10232                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10233                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10234                                                          tc_map);
10235                         else
10236                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10237                                                          I40E_DEFAULT_TCMAP);
10238                         if (ret)
10239                                 PMD_INIT_LOG(WARNING,
10240                                         "Failed configuring TC for VSI seid=%d",
10241                                         vsi_list->vsi->seid);
10242                         /* continue */
10243                 }
10244         }
10245         return I40E_SUCCESS;
10246 }
10247
10248 /*
10249  * i40e_dcb_init_configure - initial dcb config
10250  * @dev: device being configured
10251  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10252  *
10253  * Returns 0 on success, negative value on failure
10254  */
10255 static int
10256 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10257 {
10258         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10259         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10260         int i, ret = 0;
10261
10262         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10263                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10264                 return -ENOTSUP;
10265         }
10266
10267         /* DCB initialization:
10268          * Update DCB configuration from the Firmware and configure
10269          * LLDP MIB change event.
10270          */
10271         if (sw_dcb == TRUE) {
10272                 ret = i40e_init_dcb(hw);
10273                 /* If lldp agent is stopped, the return value from
10274                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10275                  * adminq status. Otherwise, it should return success.
10276                  */
10277                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10278                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10279                         memset(&hw->local_dcbx_config, 0,
10280                                 sizeof(struct i40e_dcbx_config));
10281                         /* set dcb default configuration */
10282                         hw->local_dcbx_config.etscfg.willing = 0;
10283                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10284                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10285                         hw->local_dcbx_config.etscfg.tsatable[0] =
10286                                                 I40E_IEEE_TSA_ETS;
10287                         /* all UPs mapping to TC0 */
10288                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10289                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10290                         hw->local_dcbx_config.etsrec =
10291                                 hw->local_dcbx_config.etscfg;
10292                         hw->local_dcbx_config.pfc.willing = 0;
10293                         hw->local_dcbx_config.pfc.pfccap =
10294                                                 I40E_MAX_TRAFFIC_CLASS;
10295                         /* FW needs one App to configure HW */
10296                         hw->local_dcbx_config.numapps = 1;
10297                         hw->local_dcbx_config.app[0].selector =
10298                                                 I40E_APP_SEL_ETHTYPE;
10299                         hw->local_dcbx_config.app[0].priority = 3;
10300                         hw->local_dcbx_config.app[0].protocolid =
10301                                                 I40E_APP_PROTOID_FCOE;
10302                         ret = i40e_set_dcb_config(hw);
10303                         if (ret) {
10304                                 PMD_INIT_LOG(ERR,
10305                                         "default dcb config fails. err = %d, aq_err = %d.",
10306                                         ret, hw->aq.asq_last_status);
10307                                 return -ENOSYS;
10308                         }
10309                 } else {
10310                         PMD_INIT_LOG(ERR,
10311                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10312                                 ret, hw->aq.asq_last_status);
10313                         return -ENOTSUP;
10314                 }
10315         } else {
10316                 ret = i40e_aq_start_lldp(hw, NULL);
10317                 if (ret != I40E_SUCCESS)
10318                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10319
10320                 ret = i40e_init_dcb(hw);
10321                 if (!ret) {
10322                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10323                                 PMD_INIT_LOG(ERR,
10324                                         "HW doesn't support DCBX offload.");
10325                                 return -ENOTSUP;
10326                         }
10327                 } else {
10328                         PMD_INIT_LOG(ERR,
10329                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10330                                 ret, hw->aq.asq_last_status);
10331                         return -ENOTSUP;
10332                 }
10333         }
10334         return 0;
10335 }
10336
10337 /*
10338  * i40e_dcb_setup - setup dcb related config
10339  * @dev: device being configured
10340  *
10341  * Returns 0 on success, negative value on failure
10342  */
10343 static int
10344 i40e_dcb_setup(struct rte_eth_dev *dev)
10345 {
10346         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10347         struct i40e_dcbx_config dcb_cfg;
10348         uint8_t tc_map = 0;
10349         int ret = 0;
10350
10351         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10352                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10353                 return -ENOTSUP;
10354         }
10355
10356         if (pf->vf_num != 0)
10357                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10358
10359         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10360         if (ret) {
10361                 PMD_INIT_LOG(ERR, "invalid dcb config");
10362                 return -EINVAL;
10363         }
10364         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10365         if (ret) {
10366                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10367                 return -ENOSYS;
10368         }
10369
10370         return 0;
10371 }
10372
10373 static int
10374 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10375                       struct rte_eth_dcb_info *dcb_info)
10376 {
10377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10379         struct i40e_vsi *vsi = pf->main_vsi;
10380         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10381         uint16_t bsf, tc_mapping;
10382         int i, j = 0;
10383
10384         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10385                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10386         else
10387                 dcb_info->nb_tcs = 1;
10388         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10389                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10390         for (i = 0; i < dcb_info->nb_tcs; i++)
10391                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10392
10393         /* get queue mapping if vmdq is disabled */
10394         if (!pf->nb_cfg_vmdq_vsi) {
10395                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10396                         if (!(vsi->enabled_tc & (1 << i)))
10397                                 continue;
10398                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10399                         dcb_info->tc_queue.tc_rxq[j][i].base =
10400                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10401                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10402                         dcb_info->tc_queue.tc_txq[j][i].base =
10403                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10404                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10405                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10406                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10407                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10408                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10409                 }
10410                 return 0;
10411         }
10412
10413         /* get queue mapping if vmdq is enabled */
10414         do {
10415                 vsi = pf->vmdq[j].vsi;
10416                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10417                         if (!(vsi->enabled_tc & (1 << i)))
10418                                 continue;
10419                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10420                         dcb_info->tc_queue.tc_rxq[j][i].base =
10421                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10422                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10423                         dcb_info->tc_queue.tc_txq[j][i].base =
10424                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10425                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10426                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10427                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10428                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10429                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10430                 }
10431                 j++;
10432         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10433         return 0;
10434 }
10435
10436 static int
10437 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10438 {
10439         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10440         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10441         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10442         uint16_t interval =
10443                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10444         uint16_t msix_intr;
10445
10446         msix_intr = intr_handle->intr_vec[queue_id];
10447         if (msix_intr == I40E_MISC_VEC_ID)
10448                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10449                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10450                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10451                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10452                                (interval <<
10453                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10454         else
10455                 I40E_WRITE_REG(hw,
10456                                I40E_PFINT_DYN_CTLN(msix_intr -
10457                                                    I40E_RX_VEC_START),
10458                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10459                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10460                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10461                                (interval <<
10462                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10463
10464         I40E_WRITE_FLUSH(hw);
10465         rte_intr_enable(&pci_dev->intr_handle);
10466
10467         return 0;
10468 }
10469
10470 static int
10471 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10472 {
10473         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10474         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10475         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10476         uint16_t msix_intr;
10477
10478         msix_intr = intr_handle->intr_vec[queue_id];
10479         if (msix_intr == I40E_MISC_VEC_ID)
10480                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10481         else
10482                 I40E_WRITE_REG(hw,
10483                                I40E_PFINT_DYN_CTLN(msix_intr -
10484                                                    I40E_RX_VEC_START),
10485                                0);
10486         I40E_WRITE_FLUSH(hw);
10487
10488         return 0;
10489 }
10490
10491 static int i40e_get_regs(struct rte_eth_dev *dev,
10492                          struct rte_dev_reg_info *regs)
10493 {
10494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10495         uint32_t *ptr_data = regs->data;
10496         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10497         const struct i40e_reg_info *reg_info;
10498
10499         if (ptr_data == NULL) {
10500                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10501                 regs->width = sizeof(uint32_t);
10502                 return 0;
10503         }
10504
10505         /* The first few registers have to be read using AQ operations */
10506         reg_idx = 0;
10507         while (i40e_regs_adminq[reg_idx].name) {
10508                 reg_info = &i40e_regs_adminq[reg_idx++];
10509                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10510                         for (arr_idx2 = 0;
10511                                         arr_idx2 <= reg_info->count2;
10512                                         arr_idx2++) {
10513                                 reg_offset = arr_idx * reg_info->stride1 +
10514                                         arr_idx2 * reg_info->stride2;
10515                                 reg_offset += reg_info->base_addr;
10516                                 ptr_data[reg_offset >> 2] =
10517                                         i40e_read_rx_ctl(hw, reg_offset);
10518                         }
10519         }
10520
10521         /* The remaining registers can be read using primitives */
10522         reg_idx = 0;
10523         while (i40e_regs_others[reg_idx].name) {
10524                 reg_info = &i40e_regs_others[reg_idx++];
10525                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10526                         for (arr_idx2 = 0;
10527                                         arr_idx2 <= reg_info->count2;
10528                                         arr_idx2++) {
10529                                 reg_offset = arr_idx * reg_info->stride1 +
10530                                         arr_idx2 * reg_info->stride2;
10531                                 reg_offset += reg_info->base_addr;
10532                                 ptr_data[reg_offset >> 2] =
10533                                         I40E_READ_REG(hw, reg_offset);
10534                         }
10535         }
10536
10537         return 0;
10538 }
10539
10540 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10541 {
10542         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10543
10544         /* Convert word count to byte count */
10545         return hw->nvm.sr_size << 1;
10546 }
10547
10548 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10549                            struct rte_dev_eeprom_info *eeprom)
10550 {
10551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10552         uint16_t *data = eeprom->data;
10553         uint16_t offset, length, cnt_words;
10554         int ret_code;
10555
10556         offset = eeprom->offset >> 1;
10557         length = eeprom->length >> 1;
10558         cnt_words = length;
10559
10560         if (offset > hw->nvm.sr_size ||
10561                 offset + length > hw->nvm.sr_size) {
10562                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10563                 return -EINVAL;
10564         }
10565
10566         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10567
10568         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10569         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10570                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10571                 return -EIO;
10572         }
10573
10574         return 0;
10575 }
10576
10577 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10578                                       struct ether_addr *mac_addr)
10579 {
10580         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10581
10582         if (!is_valid_assigned_ether_addr(mac_addr)) {
10583                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10584                 return;
10585         }
10586
10587         /* Flags: 0x3 updates port address */
10588         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10589 }
10590
10591 static int
10592 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10593 {
10594         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10595         struct rte_eth_dev_data *dev_data = pf->dev_data;
10596         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10597         int ret = 0;
10598
10599         /* check if mtu is within the allowed range */
10600         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10601                 return -EINVAL;
10602
10603         /* mtu setting is forbidden if port is start */
10604         if (dev_data->dev_started) {
10605                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10606                             dev_data->port_id);
10607                 return -EBUSY;
10608         }
10609
10610         if (frame_size > ETHER_MAX_LEN)
10611                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10612         else
10613                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10614
10615         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10616
10617         return ret;
10618 }
10619
10620 /* Restore ethertype filter */
10621 static void
10622 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10623 {
10624         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10625         struct i40e_ethertype_filter_list
10626                 *ethertype_list = &pf->ethertype.ethertype_list;
10627         struct i40e_ethertype_filter *f;
10628         struct i40e_control_filter_stats stats;
10629         uint16_t flags;
10630
10631         TAILQ_FOREACH(f, ethertype_list, rules) {
10632                 flags = 0;
10633                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10634                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10635                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10636                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10637                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10638
10639                 memset(&stats, 0, sizeof(stats));
10640                 i40e_aq_add_rem_control_packet_filter(hw,
10641                                             f->input.mac_addr.addr_bytes,
10642                                             f->input.ether_type,
10643                                             flags, pf->main_vsi->seid,
10644                                             f->queue, 1, &stats, NULL);
10645         }
10646         PMD_DRV_LOG(INFO, "Ethertype filter:"
10647                     " mac_etype_used = %u, etype_used = %u,"
10648                     " mac_etype_free = %u, etype_free = %u",
10649                     stats.mac_etype_used, stats.etype_used,
10650                     stats.mac_etype_free, stats.etype_free);
10651 }
10652
10653 /* Restore tunnel filter */
10654 static void
10655 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10656 {
10657         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10658         struct i40e_vsi *vsi;
10659         struct i40e_pf_vf *vf;
10660         struct i40e_tunnel_filter_list
10661                 *tunnel_list = &pf->tunnel.tunnel_list;
10662         struct i40e_tunnel_filter *f;
10663         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10664         bool big_buffer = 0;
10665
10666         TAILQ_FOREACH(f, tunnel_list, rules) {
10667                 if (!f->is_to_vf)
10668                         vsi = pf->main_vsi;
10669                 else {
10670                         vf = &pf->vfs[f->vf_id];
10671                         vsi = vf->vsi;
10672                 }
10673                 memset(&cld_filter, 0, sizeof(cld_filter));
10674                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10675                         (struct ether_addr *)&cld_filter.element.outer_mac);
10676                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10677                         (struct ether_addr *)&cld_filter.element.inner_mac);
10678                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10679                 cld_filter.element.flags = f->input.flags;
10680                 cld_filter.element.tenant_id = f->input.tenant_id;
10681                 cld_filter.element.queue_number = f->queue;
10682                 rte_memcpy(cld_filter.general_fields,
10683                            f->input.general_fields,
10684                            sizeof(f->input.general_fields));
10685
10686                 if (((f->input.flags &
10687                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10688                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10689                     ((f->input.flags &
10690                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10691                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10692                     ((f->input.flags &
10693                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10694                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10695                         big_buffer = 1;
10696
10697                 if (big_buffer)
10698                         i40e_aq_add_cloud_filters_big_buffer(hw,
10699                                              vsi->seid, &cld_filter, 1);
10700                 else
10701                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10702                                                   &cld_filter.element, 1);
10703         }
10704 }
10705
10706 static void
10707 i40e_filter_restore(struct i40e_pf *pf)
10708 {
10709         i40e_ethertype_filter_restore(pf);
10710         i40e_tunnel_filter_restore(pf);
10711         i40e_fdir_filter_restore(pf);
10712 }
10713
10714 static bool
10715 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10716 {
10717         if (strcmp(dev->data->drv_name,
10718                    drv->driver.name))
10719                 return false;
10720
10721         return true;
10722 }
10723
10724 bool
10725 is_i40e_supported(struct rte_eth_dev *dev)
10726 {
10727         return is_device_supported(dev, &rte_i40e_pmd);
10728 }
10729
10730 /* Create a QinQ cloud filter
10731  *
10732  * The Fortville NIC has limited resources for tunnel filters,
10733  * so we can only reuse existing filters.
10734  *
10735  * In step 1 we define which Field Vector fields can be used for
10736  * filter types.
10737  * As we do not have the inner tag defined as a field,
10738  * we have to define it first, by reusing one of L1 entries.
10739  *
10740  * In step 2 we are replacing one of existing filter types with
10741  * a new one for QinQ.
10742  * As we reusing L1 and replacing L2, some of the default filter
10743  * types will disappear,which depends on L1 and L2 entries we reuse.
10744  *
10745  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10746  *
10747  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10748  *              later when we define the cloud filter.
10749  *      a.      Valid_flags.replace_cloud = 0
10750  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10751  *      c.      New_filter = 0x10
10752  *      d.      TR bit = 0xff (optional, not used here)
10753  *      e.      Buffer – 2 entries:
10754  *              i.      Byte 0 = 8 (outer vlan FV index).
10755  *                      Byte 1 = 0 (rsv)
10756  *                      Byte 2-3 = 0x0fff
10757  *              ii.     Byte 0 = 37 (inner vlan FV index).
10758  *                      Byte 1 =0 (rsv)
10759  *                      Byte 2-3 = 0x0fff
10760  *
10761  * Step 2:
10762  * 2.   Create cloud filter using two L1 filters entries: stag and
10763  *              new filter(outer vlan+ inner vlan)
10764  *      a.      Valid_flags.replace_cloud = 1
10765  *      b.      Old_filter = 1 (instead of outer IP)
10766  *      c.      New_filter = 0x10
10767  *      d.      Buffer – 2 entries:
10768  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10769  *                      Byte 1-3 = 0 (rsv)
10770  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10771  *                      Byte 9-11 = 0 (rsv)
10772  */
10773 static int
10774 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10775 {
10776         int ret = -ENOTSUP;
10777         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10778         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10779         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10780
10781         /* Init */
10782         memset(&filter_replace, 0,
10783                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10784         memset(&filter_replace_buf, 0,
10785                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10786
10787         /* create L1 filter */
10788         filter_replace.old_filter_type =
10789                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10790         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10791         filter_replace.tr_bit = 0;
10792
10793         /* Prepare the buffer, 2 entries */
10794         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10795         filter_replace_buf.data[0] |=
10796                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10797         /* Field Vector 12b mask */
10798         filter_replace_buf.data[2] = 0xff;
10799         filter_replace_buf.data[3] = 0x0f;
10800         filter_replace_buf.data[4] =
10801                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10802         filter_replace_buf.data[4] |=
10803                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10804         /* Field Vector 12b mask */
10805         filter_replace_buf.data[6] = 0xff;
10806         filter_replace_buf.data[7] = 0x0f;
10807         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10808                         &filter_replace_buf);
10809         if (ret != I40E_SUCCESS)
10810                 return ret;
10811
10812         /* Apply the second L2 cloud filter */
10813         memset(&filter_replace, 0,
10814                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10815         memset(&filter_replace_buf, 0,
10816                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10817
10818         /* create L2 filter, input for L2 filter will be L1 filter  */
10819         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10820         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10821         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10822
10823         /* Prepare the buffer, 2 entries */
10824         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10825         filter_replace_buf.data[0] |=
10826                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10827         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10828         filter_replace_buf.data[4] |=
10829                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10830         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10831                         &filter_replace_buf);
10832         return ret;
10833 }
10834
10835 RTE_INIT(i40e_init_log);
10836 static void
10837 i40e_init_log(void)
10838 {
10839         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10840         if (i40e_logtype_init >= 0)
10841                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10842         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10843         if (i40e_logtype_driver >= 0)
10844                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10845 }