drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_bus_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_ethdev_pci.h>
  50 #include <rte_memzone.h>
  51 #include <rte_malloc.h>
  52 #include <rte_memcpy.h>
  53 #include <rte_alarm.h>
  54 #include <rte_dev.h>
  55 #include <rte_eth_ctrl.h>
  56 #include <rte_tailq.h>
  57 #include <rte_hash_crc.h>
  58
  59 #include "i40e_logs.h"
  60 #include "base/i40e_prototype.h"
  61 #include "base/i40e_adminq_cmd.h"
  62 #include "base/i40e_type.h"
  63 #include "base/i40e_register.h"
  64 #include "base/i40e_dcb.h"
  65 #include "i40e_ethdev.h"
  66 #include "i40e_rxtx.h"
  67 #include "i40e_pf.h"
  68 #include "i40e_regs.h"
  69 #include "rte_pmd_i40e.h"
  70
  71 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  72 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  73
  74 #define I40E_CLEAR_PXE_WAIT_MS     200
  75
  76 /* Maximun number of capability elements */
  77 #define I40E_MAX_CAP_ELE_NUM       128
  78
  79 /* Wait count and interval */
  80 #define I40E_CHK_Q_ENA_COUNT       1000
  81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  82
  83 /* Maximun number of VSI */
  84 #define I40E_MAX_NUM_VSIS          (384UL)
  85
  86 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  87
  88 /* Flow control default timer */
  89 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  90
  91 /* Flow control enable fwd bit */
  92 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  93
  94 /* Receive Packet Buffer size */
  95 #define I40E_RXPBSIZE (968 * 1024)
  96
  97 /* Kilobytes shift */
  98 #define I40E_KILOSHIFT 10
  99
 100 /* Flow control default high water */
 101 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 102
 103 /* Flow control default low water */
 104 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 105
 106 /* Receive Average Packet Size in Byte*/
 107 #define I40E_PACKET_AVERAGE_SIZE 128
 108
 109 /* Mask of PF interrupt causes */
 110 #define I40E_PFINT_ICR0_ENA_MASK ( \
 111                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 115                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 116                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 119                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 120
 121 #define I40E_FLOW_TYPES ( \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 131         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 132         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 133
 134 /* Additional timesync values. */
 135 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 136 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 137 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 138 #define I40E_PRTTSYN_TSYNENA     0x80000000
 139 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 140 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 141
 142 /**
 143  * Below are values for writing un-exposed registers suggested
 144  * by silicon experts
 145  */
 146 /* Destination MAC address */
 147 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 148 /* Source MAC address */
 149 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 150 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 151 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 152 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 154 /* Single VLAN tag in the inner L2 header */
 155 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 156 /* Source IPv4 address */
 157 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 158 /* Destination IPv4 address */
 159 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 160 /* Source IPv4 address for X722 */
 161 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 162 /* Destination IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 164 /* IPv4 Protocol for X722 */
 165 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 166 /* IPv4 Time to Live for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 168 /* IPv4 Type of Service (TOS) */
 169 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 170 /* IPv4 Protocol */
 171 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 172 /* IPv4 Time to Live */
 173 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 174 /* Source IPv6 address */
 175 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 176 /* Destination IPv6 address */
 177 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 178 /* IPv6 Traffic Class (TC) */
 179 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 180 /* IPv6 Next Header */
 181 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 182 /* IPv6 Hop Limit */
 183 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 184 /* Source L4 port */
 185 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 186 /* Destination L4 port */
 187 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 188 /* SCTP verification tag */
 189 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 190 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 191 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 192 /* Source port of tunneling UDP */
 193 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 194 /* Destination port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 196 /* UDP Tunneling ID, NVGRE/GRE key */
 197 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 198 /* Last ether type */
 199 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 200 /* Tunneling outer destination IPv4 address */
 201 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 202 /* Tunneling outer destination IPv6 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 204 /* 1st word of flex payload */
 205 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 206 /* 2nd word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 208 /* 3rd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 210 /* 4th word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 212 /* 5th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 214 /* 6th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 216 /* 7th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 218 /* 8th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 220 /* all 8 words flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 222 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 223
 224 #define I40E_TRANSLATE_INSET 0
 225 #define I40E_TRANSLATE_REG   1
 226
 227 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 228 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 229 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 230 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 231 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 232 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 233
 234 /* PCI offset for querying capability */
 235 #define PCI_DEV_CAP_REG            0xA4
 236 /* PCI offset for enabling/disabling Extended Tag */
 237 #define PCI_DEV_CTRL_REG           0xA8
 238 /* Bit mask of Extended Tag capability */
 239 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 240 /* Bit shift of Extended Tag enable/disable */
 241 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 242 /* Bit mask of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 244
 245 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int i40e_dev_configure(struct rte_eth_dev *dev);
 248 static int i40e_dev_start(struct rte_eth_dev *dev);
 249 static void i40e_dev_stop(struct rte_eth_dev *dev);
 250 static void i40e_dev_close(struct rte_eth_dev *dev);
 251 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 258 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_stats *stats);
 260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_xstat *xstats, unsigned n);
 262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 263                                      struct rte_eth_xstat_name *xstats_names,
 264                                      unsigned limit);
 265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id,
 268                                             uint8_t stat_idx,
 269                                             uint8_t is_rx);
 270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 271                                 char *fw_version, size_t fw_size);
 272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 273                               struct rte_eth_dev_info *dev_info);
 274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 275                                 uint16_t vlan_id,
 276                                 int on);
 277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 278                               enum rte_vlan_type vlan_type,
 279                               uint16_t tpid);
 280 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 282                                       uint16_t queue,
 283                                       int on);
 284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 288                               struct rte_eth_fc_conf *fc_conf);
 289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 292                                        struct rte_eth_pfc_conf *pfc_conf);
 293 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 294                             struct ether_addr *mac_addr,
 295                             uint32_t index,
 296                             uint32_t pool);
 297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 299                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 300                                     uint16_t reta_size);
 301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 302                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                    uint16_t reta_size);
 304
 305 static int i40e_get_cap(struct i40e_hw *hw);
 306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 307 static int i40e_pf_setup(struct i40e_pf *pf);
 308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 310 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 311 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 312                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 313 static void i40e_stat_update_48(struct i40e_hw *hw,
 314                                uint32_t hireg,
 315                                uint32_t loreg,
 316                                bool offset_loaded,
 317                                uint64_t *offset,
 318                                uint64_t *stat);
 319 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 320 static void i40e_dev_interrupt_handler(void *param);
 321 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 322                                 uint32_t base, uint32_t num);
 323 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 324 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 325                         uint32_t base);
 326 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 327                         uint16_t num);
 328 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 329 static int i40e_veb_release(struct i40e_veb *veb);
 330 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 331                                                 struct i40e_vsi *vsi);
 332 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 333 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 334 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 335                                              struct i40e_macvlan_filter *mv_f,
 336                                              int num,
 337                                              uint16_t vlan);
 338 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 339 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 340                                     struct rte_eth_rss_conf *rss_conf);
 341 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 342                                       struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 344                                         struct rte_eth_udp_tunnel *udp_tunnel);
 345 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 348 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 349                                 enum rte_filter_op filter_op,
 350                                 void *arg);
 351 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 352                                 enum rte_filter_type filter_type,
 353                                 enum rte_filter_op filter_op,
 354                                 void *arg);
 355 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 356                                   struct rte_eth_dcb_info *dcb_info);
 357 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 358 static void i40e_configure_registers(struct i40e_hw *hw);
 359 static void i40e_hw_init(struct rte_eth_dev *dev);
 360 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 361 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 362                                                      uint16_t seid,
 363                                                      uint16_t rule_type,
 364                                                      uint16_t *entries,
 365                                                      uint16_t count,
 366                                                      uint16_t rule_id);
 367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 368                         struct rte_eth_mirror_conf *mirror_conf,
 369                         uint8_t sw_id, uint8_t on);
 370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 371
 372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp,
 376                                            uint32_t flags);
 377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp);
 379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 380
 381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 382
 383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 384                                    struct timespec *timestamp);
 385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 386                                     const struct timespec *timestamp);
 387
 388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 389                                          uint16_t queue_id);
 390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 391                                           uint16_t queue_id);
 392
 393 static int i40e_get_regs(struct rte_eth_dev *dev,
 394                          struct rte_dev_reg_info *regs);
 395
 396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 397
 398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 399                            struct rte_dev_eeprom_info *eeprom);
 400
 401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 402                                       struct ether_addr *mac_addr);
 403
 404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 405
 406 static int i40e_ethertype_filter_convert(
 407         const struct rte_eth_ethertype_filter *input,
 408         struct i40e_ethertype_filter *filter);
 409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 410                                    struct i40e_ethertype_filter *filter);
 411
 412 static int i40e_tunnel_filter_convert(
 413         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 414         struct i40e_tunnel_filter *tunnel_filter);
 415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 416                                 struct i40e_tunnel_filter *tunnel_filter);
 417 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 418
 419 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 420 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 421 static void i40e_filter_restore(struct i40e_pf *pf);
 422 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 423
 424 int i40e_logtype_init;
 425 int i40e_logtype_driver;
 426
 427 static const struct rte_pci_id pci_id_i40e_map[] = {
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 448         { .vendor_id = 0, /* sentinel */ },
 449 };
 450
 451 static const struct eth_dev_ops i40e_eth_dev_ops = {
 452         .dev_configure                = i40e_dev_configure,
 453         .dev_start                    = i40e_dev_start,
 454         .dev_stop                     = i40e_dev_stop,
 455         .dev_close                    = i40e_dev_close,
 456         .dev_reset                    = i40e_dev_reset,
 457         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 458         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 459         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 460         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 461         .dev_set_link_up              = i40e_dev_set_link_up,
 462         .dev_set_link_down            = i40e_dev_set_link_down,
 463         .link_update                  = i40e_dev_link_update,
 464         .stats_get                    = i40e_dev_stats_get,
 465         .xstats_get                   = i40e_dev_xstats_get,
 466         .xstats_get_names             = i40e_dev_xstats_get_names,
 467         .stats_reset                  = i40e_dev_stats_reset,
 468         .xstats_reset                 = i40e_dev_stats_reset,
 469         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 470         .fw_version_get               = i40e_fw_version_get,
 471         .dev_infos_get                = i40e_dev_info_get,
 472         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 473         .vlan_filter_set              = i40e_vlan_filter_set,
 474         .vlan_tpid_set                = i40e_vlan_tpid_set,
 475         .vlan_offload_set             = i40e_vlan_offload_set,
 476         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 477         .vlan_pvid_set                = i40e_vlan_pvid_set,
 478         .rx_queue_start               = i40e_dev_rx_queue_start,
 479         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 480         .tx_queue_start               = i40e_dev_tx_queue_start,
 481         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 482         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 483         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 484         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 485         .rx_queue_release             = i40e_dev_rx_queue_release,
 486         .rx_queue_count               = i40e_dev_rx_queue_count,
 487         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 488         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 489         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 490         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 491         .tx_queue_release             = i40e_dev_tx_queue_release,
 492         .dev_led_on                   = i40e_dev_led_on,
 493         .dev_led_off                  = i40e_dev_led_off,
 494         .flow_ctrl_get                = i40e_flow_ctrl_get,
 495         .flow_ctrl_set                = i40e_flow_ctrl_set,
 496         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 497         .mac_addr_add                 = i40e_macaddr_add,
 498         .mac_addr_remove              = i40e_macaddr_remove,
 499         .reta_update                  = i40e_dev_rss_reta_update,
 500         .reta_query                   = i40e_dev_rss_reta_query,
 501         .rss_hash_update              = i40e_dev_rss_hash_update,
 502         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 503         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 504         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 505         .filter_ctrl                  = i40e_dev_filter_ctrl,
 506         .rxq_info_get                 = i40e_rxq_info_get,
 507         .txq_info_get                 = i40e_txq_info_get,
 508         .mirror_rule_set              = i40e_mirror_rule_set,
 509         .mirror_rule_reset            = i40e_mirror_rule_reset,
 510         .timesync_enable              = i40e_timesync_enable,
 511         .timesync_disable             = i40e_timesync_disable,
 512         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 513         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 514         .get_dcb_info                 = i40e_dev_get_dcb_info,
 515         .timesync_adjust_time         = i40e_timesync_adjust_time,
 516         .timesync_read_time           = i40e_timesync_read_time,
 517         .timesync_write_time          = i40e_timesync_write_time,
 518         .get_reg                      = i40e_get_regs,
 519         .get_eeprom_length            = i40e_get_eeprom_length,
 520         .get_eeprom                   = i40e_get_eeprom,
 521         .mac_addr_set                 = i40e_set_default_mac_addr,
 522         .mtu_set                      = i40e_dev_mtu_set,
 523         .tm_ops_get                   = i40e_tm_ops_get,
 524 };
 525
 526 /* store statistics names and its offset in stats structure */
 527 struct rte_i40e_xstats_name_off {
 528         char name[RTE_ETH_XSTATS_NAME_SIZE];
 529         unsigned offset;
 530 };
 531
 532 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 533         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 534         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 535         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 536         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 537         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 538                 rx_unknown_protocol)},
 539         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 540         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 541         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 542         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 543 };
 544
 545 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 546                 sizeof(rte_i40e_stats_strings[0]))
 547
 548 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 549         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 550                 tx_dropped_link_down)},
 551         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 552         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 553                 illegal_bytes)},
 554         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 555         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 556                 mac_local_faults)},
 557         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 558                 mac_remote_faults)},
 559         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 560                 rx_length_errors)},
 561         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 562         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 563         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 564         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 565         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 566         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_127)},
 568         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_255)},
 570         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_511)},
 572         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_1023)},
 574         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_1522)},
 576         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_big)},
 578         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_undersize)},
 580         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 581                 rx_oversize)},
 582         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 583                 mac_short_packet_dropped)},
 584         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_fragments)},
 586         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 587         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 588         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_127)},
 590         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_255)},
 592         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_511)},
 594         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_1023)},
 596         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_1522)},
 598         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_big)},
 600         {"rx_flow_director_atr_match_packets",
 601                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 602         {"rx_flow_director_sb_match_packets",
 603                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 604         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 605                 tx_lpi_status)},
 606         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 607                 rx_lpi_status)},
 608         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 609                 tx_lpi_count)},
 610         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 611                 rx_lpi_count)},
 612 };
 613
 614 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 615                 sizeof(rte_i40e_hw_port_strings[0]))
 616
 617 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 618         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xon_rx)},
 620         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xoff_rx)},
 622 };
 623
 624 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 625                 sizeof(rte_i40e_rxq_prio_strings[0]))
 626
 627 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 628         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 629                 priority_xon_tx)},
 630         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 631                 priority_xoff_tx)},
 632         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 633                 priority_xon_2_xoff)},
 634 };
 635
 636 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 637                 sizeof(rte_i40e_txq_prio_strings[0]))
 638
 639 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 640         struct rte_pci_device *pci_dev)
 641 {
 642         return rte_eth_dev_pci_generic_probe(pci_dev,
 643                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 644 }
 645
 646 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 647 {
 648         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 649 }
 650
 651 static struct rte_pci_driver rte_i40e_pmd = {
 652         .id_table = pci_id_i40e_map,
 653         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 654                      RTE_PCI_DRV_IOVA_AS_VA,
 655         .probe = eth_i40e_pci_probe,
 656         .remove = eth_i40e_pci_remove,
 657 };
 658
 659 static inline int
 660 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 661                                      struct rte_eth_link *link)
 662 {
 663         struct rte_eth_link *dst = link;
 664         struct rte_eth_link *src = &(dev->data->dev_link);
 665
 666         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 667                                         *(uint64_t *)src) == 0)
 668                 return -1;
 669
 670         return 0;
 671 }
 672
 673 static inline int
 674 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 675                                       struct rte_eth_link *link)
 676 {
 677         struct rte_eth_link *dst = &(dev->data->dev_link);
 678         struct rte_eth_link *src = link;
 679
 680         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 681                                         *(uint64_t *)src) == 0)
 682                 return -1;
 683
 684         return 0;
 685 }
 686
 687 static inline void
 688 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 689 {
 690         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 691         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 692                     "with value 0x%08x",
 693                     reg_addr, reg_val);
 694 }
 695
 696 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 697 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 698 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 699
 700 #ifndef I40E_GLQF_ORT
 701 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 702 #endif
 703 #ifndef I40E_GLQF_PIT
 704 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 705 #endif
 706 #ifndef I40E_GLQF_L3_MAP
 707 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 708 #endif
 709
 710 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 711 {
 712         /*
 713          * Force global configuration for flexible payload
 714          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 715          * This should be removed from code once proper
 716          * configuration API is added to avoid configuration conflicts
 717          * between ports of the same device.
 718          */
 719         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 720         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 721         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 722         i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
 723
 724         /*
 725          * Initialize registers for parsing packet type of QinQ
 726          * This should be removed from code once proper
 727          * configuration API is added to avoid configuration conflicts
 728          * between ports of the same device.
 729          */
 730         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 731         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 732         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 733 }
 734
 735 static inline void i40e_config_automask(struct i40e_pf *pf)
 736 {
 737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 738         uint32_t val;
 739
 740         /* INTENA flag is not auto-cleared for interrupt */
 741         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 742         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 743                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 744
 745         /* If support multi-driver, PF will use INT0. */
 746         if (!pf->support_multi_driver)
 747                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 748
 749         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 750 }
 751
 752 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 753
 754 /*
 755  * Add a ethertype filter to drop all flow control frames transmitted
 756  * from VSIs.
 757 */
 758 static void
 759 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 760 {
 761         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 762         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 763                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 764                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 765         int ret;
 766
 767         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 768                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 769                                 pf->main_vsi_seid, 0,
 770                                 TRUE, NULL, NULL);
 771         if (ret)
 772                 PMD_INIT_LOG(ERR,
 773                         "Failed to add filter to drop flow control frames from VSIs.");
 774 }
 775
 776 static int
 777 floating_veb_list_handler(__rte_unused const char *key,
 778                           const char *floating_veb_value,
 779                           void *opaque)
 780 {
 781         int idx = 0;
 782         unsigned int count = 0;
 783         char *end = NULL;
 784         int min, max;
 785         bool *vf_floating_veb = opaque;
 786
 787         while (isblank(*floating_veb_value))
 788                 floating_veb_value++;
 789
 790         /* Reset floating VEB configuration for VFs */
 791         for (idx = 0; idx < I40E_MAX_VF; idx++)
 792                 vf_floating_veb[idx] = false;
 793
 794         min = I40E_MAX_VF;
 795         do {
 796                 while (isblank(*floating_veb_value))
 797                         floating_veb_value++;
 798                 if (*floating_veb_value == '\0')
 799                         return -1;
 800                 errno = 0;
 801                 idx = strtoul(floating_veb_value, &end, 10);
 802                 if (errno || end == NULL)
 803                         return -1;
 804                 while (isblank(*end))
 805                         end++;
 806                 if (*end == '-') {
 807                         min = idx;
 808                 } else if ((*end == ';') || (*end == '\0')) {
 809                         max = idx;
 810                         if (min == I40E_MAX_VF)
 811                                 min = idx;
 812                         if (max >= I40E_MAX_VF)
 813                                 max = I40E_MAX_VF - 1;
 814                         for (idx = min; idx <= max; idx++) {
 815                                 vf_floating_veb[idx] = true;
 816                                 count++;
 817                         }
 818                         min = I40E_MAX_VF;
 819                 } else {
 820                         return -1;
 821                 }
 822                 floating_veb_value = end + 1;
 823         } while (*end != '\0');
 824
 825         if (count == 0)
 826                 return -1;
 827
 828         return 0;
 829 }
 830
 831 static void
 832 config_vf_floating_veb(struct rte_devargs *devargs,
 833                        uint16_t floating_veb,
 834                        bool *vf_floating_veb)
 835 {
 836         struct rte_kvargs *kvlist;
 837         int i;
 838         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 839
 840         if (!floating_veb)
 841                 return;
 842         /* All the VFs attach to the floating VEB by default
 843          * when the floating VEB is enabled.
 844          */
 845         for (i = 0; i < I40E_MAX_VF; i++)
 846                 vf_floating_veb[i] = true;
 847
 848         if (devargs == NULL)
 849                 return;
 850
 851         kvlist = rte_kvargs_parse(devargs->args, NULL);
 852         if (kvlist == NULL)
 853                 return;
 854
 855         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 856                 rte_kvargs_free(kvlist);
 857                 return;
 858         }
 859         /* When the floating_veb_list parameter exists, all the VFs
 860          * will attach to the legacy VEB firstly, then configure VFs
 861          * to the floating VEB according to the floating_veb_list.
 862          */
 863         if (rte_kvargs_process(kvlist, floating_veb_list,
 864                                floating_veb_list_handler,
 865                                vf_floating_veb) < 0) {
 866                 rte_kvargs_free(kvlist);
 867                 return;
 868         }
 869         rte_kvargs_free(kvlist);
 870 }
 871
 872 static int
 873 i40e_check_floating_handler(__rte_unused const char *key,
 874                             const char *value,
 875                             __rte_unused void *opaque)
 876 {
 877         if (strcmp(value, "1"))
 878                 return -1;
 879
 880         return 0;
 881 }
 882
 883 static int
 884 is_floating_veb_supported(struct rte_devargs *devargs)
 885 {
 886         struct rte_kvargs *kvlist;
 887         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 888
 889         if (devargs == NULL)
 890                 return 0;
 891
 892         kvlist = rte_kvargs_parse(devargs->args, NULL);
 893         if (kvlist == NULL)
 894                 return 0;
 895
 896         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 897                 rte_kvargs_free(kvlist);
 898                 return 0;
 899         }
 900         /* Floating VEB is enabled when there's key-value:
 901          * enable_floating_veb=1
 902          */
 903         if (rte_kvargs_process(kvlist, floating_veb_key,
 904                                i40e_check_floating_handler, NULL) < 0) {
 905                 rte_kvargs_free(kvlist);
 906                 return 0;
 907         }
 908         rte_kvargs_free(kvlist);
 909
 910         return 1;
 911 }
 912
 913 static void
 914 config_floating_veb(struct rte_eth_dev *dev)
 915 {
 916         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919
 920         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 921
 922         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 923                 pf->floating_veb =
 924                         is_floating_veb_supported(pci_dev->device.devargs);
 925                 config_vf_floating_veb(pci_dev->device.devargs,
 926                                        pf->floating_veb,
 927                                        pf->floating_veb_list);
 928         } else {
 929                 pf->floating_veb = false;
 930         }
 931 }
 932
 933 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 934 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 935
 936 static int
 937 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 938 {
 939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 940         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 941         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 942         int ret;
 943
 944         struct rte_hash_parameters ethertype_hash_params = {
 945                 .name = ethertype_hash_name,
 946                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 947                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 948                 .hash_func = rte_hash_crc,
 949                 .hash_func_init_val = 0,
 950                 .socket_id = rte_socket_id(),
 951         };
 952
 953         /* Initialize ethertype filter rule list and hash */
 954         TAILQ_INIT(&ethertype_rule->ethertype_list);
 955         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 956                  "ethertype_%s", dev->device->name);
 957         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 958         if (!ethertype_rule->hash_table) {
 959                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 960                 return -EINVAL;
 961         }
 962         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 963                                        sizeof(struct i40e_ethertype_filter *) *
 964                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 965                                        0);
 966         if (!ethertype_rule->hash_map) {
 967                 PMD_INIT_LOG(ERR,
 968                              "Failed to allocate memory for ethertype hash map!");
 969                 ret = -ENOMEM;
 970                 goto err_ethertype_hash_map_alloc;
 971         }
 972
 973         return 0;
 974
 975 err_ethertype_hash_map_alloc:
 976         rte_hash_free(ethertype_rule->hash_table);
 977
 978         return ret;
 979 }
 980
 981 static int
 982 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 983 {
 984         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 985         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 986         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 987         int ret;
 988
 989         struct rte_hash_parameters tunnel_hash_params = {
 990                 .name = tunnel_hash_name,
 991                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 992                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 993                 .hash_func = rte_hash_crc,
 994                 .hash_func_init_val = 0,
 995                 .socket_id = rte_socket_id(),
 996         };
 997
 998         /* Initialize tunnel filter rule list and hash */
 999         TAILQ_INIT(&tunnel_rule->tunnel_list);
1000         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1001                  "tunnel_%s", dev->device->name);
1002         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1003         if (!tunnel_rule->hash_table) {
1004                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1005                 return -EINVAL;
1006         }
1007         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1008                                     sizeof(struct i40e_tunnel_filter *) *
1009                                     I40E_MAX_TUNNEL_FILTER_NUM,
1010                                     0);
1011         if (!tunnel_rule->hash_map) {
1012                 PMD_INIT_LOG(ERR,
1013                              "Failed to allocate memory for tunnel hash map!");
1014                 ret = -ENOMEM;
1015                 goto err_tunnel_hash_map_alloc;
1016         }
1017
1018         return 0;
1019
1020 err_tunnel_hash_map_alloc:
1021         rte_hash_free(tunnel_rule->hash_table);
1022
1023         return ret;
1024 }
1025
1026 static int
1027 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1028 {
1029         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1030         struct i40e_fdir_info *fdir_info = &pf->fdir;
1031         char fdir_hash_name[RTE_HASH_NAMESIZE];
1032         int ret;
1033
1034         struct rte_hash_parameters fdir_hash_params = {
1035                 .name = fdir_hash_name,
1036                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1037                 .key_len = sizeof(struct i40e_fdir_input),
1038                 .hash_func = rte_hash_crc,
1039                 .hash_func_init_val = 0,
1040                 .socket_id = rte_socket_id(),
1041         };
1042
1043         /* Initialize flow director filter rule list and hash */
1044         TAILQ_INIT(&fdir_info->fdir_list);
1045         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1046                  "fdir_%s", dev->device->name);
1047         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1048         if (!fdir_info->hash_table) {
1049                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1050                 return -EINVAL;
1051         }
1052         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1053                                           sizeof(struct i40e_fdir_filter *) *
1054                                           I40E_MAX_FDIR_FILTER_NUM,
1055                                           0);
1056         if (!fdir_info->hash_map) {
1057                 PMD_INIT_LOG(ERR,
1058                              "Failed to allocate memory for fdir hash map!");
1059                 ret = -ENOMEM;
1060                 goto err_fdir_hash_map_alloc;
1061         }
1062         return 0;
1063
1064 err_fdir_hash_map_alloc:
1065         rte_hash_free(fdir_info->hash_table);
1066
1067         return ret;
1068 }
1069
1070 static void
1071 i40e_init_customized_info(struct i40e_pf *pf)
1072 {
1073         int i;
1074
1075         /* Initialize customized pctype */
1076         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1077                 pf->customized_pctype[i].index = i;
1078                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1079                 pf->customized_pctype[i].valid = false;
1080         }
1081
1082         pf->gtp_support = false;
1083 }
1084
1085 void
1086 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1087 {
1088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1090         struct i40e_queue_regions *info = &pf->queue_region;
1091         uint16_t i;
1092
1093         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1094                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1095
1096         memset(info, 0, sizeof(struct i40e_queue_regions));
1097 }
1098
1099 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1100
1101 static int
1102 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1103                                const char *value,
1104                                void *opaque)
1105 {
1106         struct i40e_pf *pf;
1107         unsigned long support_multi_driver;
1108         char *end;
1109
1110         pf = (struct i40e_pf *)opaque;
1111
1112         errno = 0;
1113         support_multi_driver = strtoul(value, &end, 10);
1114         if (errno != 0 || end == value || *end != 0) {
1115                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1116                 return -(EINVAL);
1117         }
1118
1119         if (support_multi_driver == 1 || support_multi_driver == 0)
1120                 pf->support_multi_driver = (bool)support_multi_driver;
1121         else
1122                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1123                             "enable global configuration by default."
1124                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1125         return 0;
1126 }
1127
1128 static int
1129 i40e_support_multi_driver(struct rte_eth_dev *dev)
1130 {
1131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1132         static const char *const valid_keys[] = {
1133                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1134         struct rte_kvargs *kvlist;
1135
1136         /* Enable global configuration by default */
1137         pf->support_multi_driver = false;
1138
1139         if (!dev->device->devargs)
1140                 return 0;
1141
1142         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1143         if (!kvlist)
1144                 return -EINVAL;
1145
1146         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1147                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1148                             "the first invalid or last valid one is used !",
1149                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1150
1151         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1152                                i40e_parse_multi_drv_handler, pf) < 0) {
1153                 rte_kvargs_free(kvlist);
1154                 return -EINVAL;
1155         }
1156
1157         rte_kvargs_free(kvlist);
1158         return 0;
1159 }
1160
1161 static int
1162 eth_i40e_dev_init(struct rte_eth_dev *dev)
1163 {
1164         struct rte_pci_device *pci_dev;
1165         struct rte_intr_handle *intr_handle;
1166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168         struct i40e_vsi *vsi;
1169         int ret;
1170         uint32_t len;
1171         uint8_t aq_fail = 0;
1172
1173         PMD_INIT_FUNC_TRACE();
1174
1175         dev->dev_ops = &i40e_eth_dev_ops;
1176         dev->rx_pkt_burst = i40e_recv_pkts;
1177         dev->tx_pkt_burst = i40e_xmit_pkts;
1178         dev->tx_pkt_prepare = i40e_prep_pkts;
1179
1180         /* for secondary processes, we don't initialise any further as primary
1181          * has already done this work. Only check we don't need a different
1182          * RX function */
1183         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1184                 i40e_set_rx_function(dev);
1185                 i40e_set_tx_function(dev);
1186                 return 0;
1187         }
1188         i40e_set_default_ptype_table(dev);
1189         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1190         intr_handle = &pci_dev->intr_handle;
1191
1192         rte_eth_copy_pci_info(dev, pci_dev);
1193
1194         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1195         pf->adapter->eth_dev = dev;
1196         pf->dev_data = dev->data;
1197
1198         hw->back = I40E_PF_TO_ADAPTER(pf);
1199         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1200         if (!hw->hw_addr) {
1201                 PMD_INIT_LOG(ERR,
1202                         "Hardware is not available, as address is NULL");
1203                 return -ENODEV;
1204         }
1205
1206         hw->vendor_id = pci_dev->id.vendor_id;
1207         hw->device_id = pci_dev->id.device_id;
1208         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1209         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1210         hw->bus.device = pci_dev->addr.devid;
1211         hw->bus.func = pci_dev->addr.function;
1212         hw->adapter_stopped = 0;
1213
1214         /*
1215          * Switch Tag value should not be identical to either the First Tag
1216          * or Second Tag values. So set something other than common Ethertype
1217          * for internal switching.
1218          */
1219         hw->switch_tag = 0xffff;
1220
1221         /* Check if need to support multi-driver */
1222         i40e_support_multi_driver(dev);
1223
1224         /* Make sure all is clean before doing PF reset */
1225         i40e_clear_hw(hw);
1226
1227         /* Reset here to make sure all is clean for each PF */
1228         ret = i40e_pf_reset(hw);
1229         if (ret) {
1230                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1231                 return ret;
1232         }
1233
1234         /* Initialize the shared code (base driver) */
1235         ret = i40e_init_shared_code(hw);
1236         if (ret) {
1237                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1238                 return ret;
1239         }
1240
1241         /* Initialize the parameters for adminq */
1242         i40e_init_adminq_parameter(hw);
1243         ret = i40e_init_adminq(hw);
1244         if (ret != I40E_SUCCESS) {
1245                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1246                 return -EIO;
1247         }
1248         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1249                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1250                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1251                      ((hw->nvm.version >> 12) & 0xf),
1252                      ((hw->nvm.version >> 4) & 0xff),
1253                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1254
1255         /* Initialize the hardware */
1256         i40e_hw_init(dev);
1257
1258         i40e_config_automask(pf);
1259
1260         i40e_set_default_pctype_table(dev);
1261
1262         /*
1263          * To work around the NVM issue, initialize registers
1264          * for flexible payload and packet type of QinQ by
1265          * software. It should be removed once issues are fixed
1266          * in NVM.
1267          */
1268         if (!pf->support_multi_driver)
1269                 i40e_GLQF_reg_init(hw);
1270
1271         /* Initialize the input set for filters (hash and fd) to default value */
1272         i40e_filter_input_set_init(pf);
1273
1274         /* initialise the L3_MAP register */
1275         if (!pf->support_multi_driver) {
1276                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1277                                                    0x00000028,  NULL);
1278                 if (ret)
1279                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1280                                      ret);
1281                 PMD_INIT_LOG(DEBUG,
1282                              "Global register 0x%08x is changed with 0x28",
1283                              I40E_GLQF_L3_MAP(40));
1284                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1285         }
1286
1287         /* Need the special FW version to support floating VEB */
1288         config_floating_veb(dev);
1289         /* Clear PXE mode */
1290         i40e_clear_pxe_mode(hw);
1291         i40e_dev_sync_phy_type(hw);
1292
1293         /*
1294          * On X710, performance number is far from the expectation on recent
1295          * firmware versions. The fix for this issue may not be integrated in
1296          * the following firmware version. So the workaround in software driver
1297          * is needed. It needs to modify the initial values of 3 internal only
1298          * registers. Note that the workaround can be removed when it is fixed
1299          * in firmware in the future.
1300          */
1301         i40e_configure_registers(hw);
1302
1303         /* Get hw capabilities */
1304         ret = i40e_get_cap(hw);
1305         if (ret != I40E_SUCCESS) {
1306                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1307                 goto err_get_capabilities;
1308         }
1309
1310         /* Initialize parameters for PF */
1311         ret = i40e_pf_parameter_init(dev);
1312         if (ret != 0) {
1313                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1314                 goto err_parameter_init;
1315         }
1316
1317         /* Initialize the queue management */
1318         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1319         if (ret < 0) {
1320                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1321                 goto err_qp_pool_init;
1322         }
1323         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1324                                 hw->func_caps.num_msix_vectors - 1);
1325         if (ret < 0) {
1326                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1327                 goto err_msix_pool_init;
1328         }
1329
1330         /* Initialize lan hmc */
1331         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1332                                 hw->func_caps.num_rx_qp, 0, 0);
1333         if (ret != I40E_SUCCESS) {
1334                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1335                 goto err_init_lan_hmc;
1336         }
1337
1338         /* Configure lan hmc */
1339         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1340         if (ret != I40E_SUCCESS) {
1341                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1342                 goto err_configure_lan_hmc;
1343         }
1344
1345         /* Get and check the mac address */
1346         i40e_get_mac_addr(hw, hw->mac.addr);
1347         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1348                 PMD_INIT_LOG(ERR, "mac address is not valid");
1349                 ret = -EIO;
1350                 goto err_get_mac_addr;
1351         }
1352         /* Copy the permanent MAC address */
1353         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1354                         (struct ether_addr *) hw->mac.perm_addr);
1355
1356         /* Disable flow control */
1357         hw->fc.requested_mode = I40E_FC_NONE;
1358         i40e_set_fc(hw, &aq_fail, TRUE);
1359
1360         /* Set the global registers with default ether type value */
1361         if (!pf->support_multi_driver) {
1362                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1363                                          ETHER_TYPE_VLAN);
1364                 if (ret != I40E_SUCCESS) {
1365                         PMD_INIT_LOG(ERR,
1366                                      "Failed to set the default outer "
1367                                      "VLAN ether type");
1368                         goto err_setup_pf_switch;
1369                 }
1370         }
1371
1372         /* PF setup, which includes VSI setup */
1373         ret = i40e_pf_setup(pf);
1374         if (ret) {
1375                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1376                 goto err_setup_pf_switch;
1377         }
1378
1379         /* reset all stats of the device, including pf and main vsi */
1380         i40e_dev_stats_reset(dev);
1381
1382         vsi = pf->main_vsi;
1383
1384         /* Disable double vlan by default */
1385         i40e_vsi_config_double_vlan(vsi, FALSE);
1386
1387         /* Disable S-TAG identification when floating_veb is disabled */
1388         if (!pf->floating_veb) {
1389                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1390                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1391                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1392                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1393                 }
1394         }
1395
1396         if (!vsi->max_macaddrs)
1397                 len = ETHER_ADDR_LEN;
1398         else
1399                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1400
1401         /* Should be after VSI initialized */
1402         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1403         if (!dev->data->mac_addrs) {
1404                 PMD_INIT_LOG(ERR,
1405                         "Failed to allocated memory for storing mac address");
1406                 goto err_mac_alloc;
1407         }
1408         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1409                                         &dev->data->mac_addrs[0]);
1410
1411         /* Init dcb to sw mode by default */
1412         ret = i40e_dcb_init_configure(dev, TRUE);
1413         if (ret != I40E_SUCCESS) {
1414                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1415                 pf->flags &= ~I40E_FLAG_DCB;
1416         }
1417         /* Update HW struct after DCB configuration */
1418         i40e_get_cap(hw);
1419
1420         /* initialize pf host driver to setup SRIOV resource if applicable */
1421         i40e_pf_host_init(dev);
1422
1423         /* register callback func to eal lib */
1424         rte_intr_callback_register(intr_handle,
1425                                    i40e_dev_interrupt_handler, dev);
1426
1427         /* configure and enable device interrupt */
1428         i40e_pf_config_irq0(hw, TRUE);
1429         i40e_pf_enable_irq0(hw);
1430
1431         /* enable uio intr after callback register */
1432         rte_intr_enable(intr_handle);
1433         /*
1434          * Add an ethertype filter to drop all flow control frames transmitted
1435          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1436          * frames to wire.
1437          */
1438         i40e_add_tx_flow_control_drop_filter(pf);
1439
1440         /* Set the max frame size to 0x2600 by default,
1441          * in case other drivers changed the default value.
1442          */
1443         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1444
1445         /* initialize mirror rule list */
1446         TAILQ_INIT(&pf->mirror_list);
1447
1448         /* initialize Traffic Manager configuration */
1449         i40e_tm_conf_init(dev);
1450
1451         /* Initialize customized information */
1452         i40e_init_customized_info(pf);
1453
1454         ret = i40e_init_ethtype_filter_list(dev);
1455         if (ret < 0)
1456                 goto err_init_ethtype_filter_list;
1457         ret = i40e_init_tunnel_filter_list(dev);
1458         if (ret < 0)
1459                 goto err_init_tunnel_filter_list;
1460         ret = i40e_init_fdir_filter_list(dev);
1461         if (ret < 0)
1462                 goto err_init_fdir_filter_list;
1463
1464         /* initialize queue region configuration */
1465         i40e_init_queue_region_conf(dev);
1466
1467         return 0;
1468
1469 err_init_fdir_filter_list:
1470         rte_free(pf->tunnel.hash_table);
1471         rte_free(pf->tunnel.hash_map);
1472 err_init_tunnel_filter_list:
1473         rte_free(pf->ethertype.hash_table);
1474         rte_free(pf->ethertype.hash_map);
1475 err_init_ethtype_filter_list:
1476         rte_free(dev->data->mac_addrs);
1477 err_mac_alloc:
1478         i40e_vsi_release(pf->main_vsi);
1479 err_setup_pf_switch:
1480 err_get_mac_addr:
1481 err_configure_lan_hmc:
1482         (void)i40e_shutdown_lan_hmc(hw);
1483 err_init_lan_hmc:
1484         i40e_res_pool_destroy(&pf->msix_pool);
1485 err_msix_pool_init:
1486         i40e_res_pool_destroy(&pf->qp_pool);
1487 err_qp_pool_init:
1488 err_parameter_init:
1489 err_get_capabilities:
1490         (void)i40e_shutdown_adminq(hw);
1491
1492         return ret;
1493 }
1494
1495 static void
1496 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1497 {
1498         struct i40e_ethertype_filter *p_ethertype;
1499         struct i40e_ethertype_rule *ethertype_rule;
1500
1501         ethertype_rule = &pf->ethertype;
1502         /* Remove all ethertype filter rules and hash */
1503         if (ethertype_rule->hash_map)
1504                 rte_free(ethertype_rule->hash_map);
1505         if (ethertype_rule->hash_table)
1506                 rte_hash_free(ethertype_rule->hash_table);
1507
1508         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1509                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1510                              p_ethertype, rules);
1511                 rte_free(p_ethertype);
1512         }
1513 }
1514
1515 static void
1516 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1517 {
1518         struct i40e_tunnel_filter *p_tunnel;
1519         struct i40e_tunnel_rule *tunnel_rule;
1520
1521         tunnel_rule = &pf->tunnel;
1522         /* Remove all tunnel director rules and hash */
1523         if (tunnel_rule->hash_map)
1524                 rte_free(tunnel_rule->hash_map);
1525         if (tunnel_rule->hash_table)
1526                 rte_hash_free(tunnel_rule->hash_table);
1527
1528         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1529                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1530                 rte_free(p_tunnel);
1531         }
1532 }
1533
1534 static void
1535 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1536 {
1537         struct i40e_fdir_filter *p_fdir;
1538         struct i40e_fdir_info *fdir_info;
1539
1540         fdir_info = &pf->fdir;
1541         /* Remove all flow director rules and hash */
1542         if (fdir_info->hash_map)
1543                 rte_free(fdir_info->hash_map);
1544         if (fdir_info->hash_table)
1545                 rte_hash_free(fdir_info->hash_table);
1546
1547         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1548                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1549                 rte_free(p_fdir);
1550         }
1551 }
1552
1553 static int
1554 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1555 {
1556         struct i40e_pf *pf;
1557         struct rte_pci_device *pci_dev;
1558         struct rte_intr_handle *intr_handle;
1559         struct i40e_hw *hw;
1560         struct i40e_filter_control_settings settings;
1561         struct rte_flow *p_flow;
1562         int ret;
1563         uint8_t aq_fail = 0;
1564         int retries = 0;
1565
1566         PMD_INIT_FUNC_TRACE();
1567
1568         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1569                 return 0;
1570
1571         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1572         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1574         intr_handle = &pci_dev->intr_handle;
1575
1576         if (hw->adapter_stopped == 0)
1577                 i40e_dev_close(dev);
1578
1579         dev->dev_ops = NULL;
1580         dev->rx_pkt_burst = NULL;
1581         dev->tx_pkt_burst = NULL;
1582
1583         /* Clear PXE mode */
1584         i40e_clear_pxe_mode(hw);
1585
1586         /* Unconfigure filter control */
1587         memset(&settings, 0, sizeof(settings));
1588         ret = i40e_set_filter_control(hw, &settings);
1589         if (ret)
1590                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1591                                         ret);
1592
1593         /* Disable flow control */
1594         hw->fc.requested_mode = I40E_FC_NONE;
1595         i40e_set_fc(hw, &aq_fail, TRUE);
1596
1597         /* uninitialize pf host driver */
1598         i40e_pf_host_uninit(dev);
1599
1600         rte_free(dev->data->mac_addrs);
1601         dev->data->mac_addrs = NULL;
1602
1603         /* disable uio intr before callback unregister */
1604         rte_intr_disable(intr_handle);
1605
1606         /* unregister callback func to eal lib */
1607         do {
1608                 ret = rte_intr_callback_unregister(intr_handle,
1609                                 i40e_dev_interrupt_handler, dev);
1610                 if (ret >= 0) {
1611                         break;
1612                 } else if (ret != -EAGAIN) {
1613                         PMD_INIT_LOG(ERR,
1614                                  "intr callback unregister failed: %d",
1615                                  ret);
1616                         return ret;
1617                 }
1618                 i40e_msec_delay(500);
1619         } while (retries++ < 5);
1620
1621         i40e_rm_ethtype_filter_list(pf);
1622         i40e_rm_tunnel_filter_list(pf);
1623         i40e_rm_fdir_filter_list(pf);
1624
1625         /* Remove all flows */
1626         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1627                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1628                 rte_free(p_flow);
1629         }
1630
1631         /* Remove all Traffic Manager configuration */
1632         i40e_tm_conf_uninit(dev);
1633
1634         return 0;
1635 }
1636
1637 static int
1638 i40e_dev_configure(struct rte_eth_dev *dev)
1639 {
1640         struct i40e_adapter *ad =
1641                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1642         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1643         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1645         int i, ret;
1646
1647         ret = i40e_dev_sync_phy_type(hw);
1648         if (ret)
1649                 return ret;
1650
1651         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1652          * bulk allocation or vector Rx preconditions we will reset it.
1653          */
1654         ad->rx_bulk_alloc_allowed = true;
1655         ad->rx_vec_allowed = true;
1656         ad->tx_simple_allowed = true;
1657         ad->tx_vec_allowed = true;
1658
1659         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1660                 ret = i40e_fdir_setup(pf);
1661                 if (ret != I40E_SUCCESS) {
1662                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1663                         return -ENOTSUP;
1664                 }
1665                 ret = i40e_fdir_configure(dev);
1666                 if (ret < 0) {
1667                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1668                         goto err;
1669                 }
1670         } else
1671                 i40e_fdir_teardown(pf);
1672
1673         ret = i40e_dev_init_vlan(dev);
1674         if (ret < 0)
1675                 goto err;
1676
1677         /* VMDQ setup.
1678          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1679          *  RSS setting have different requirements.
1680          *  General PMD driver call sequence are NIC init, configure,
1681          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1682          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1683          *  applicable. So, VMDQ setting has to be done before
1684          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1685          *  For RSS setting, it will try to calculate actual configured RX queue
1686          *  number, which will be available after rx_queue_setup(). dev_start()
1687          *  function is good to place RSS setup.
1688          */
1689         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1690                 ret = i40e_vmdq_setup(dev);
1691                 if (ret)
1692                         goto err;
1693         }
1694
1695         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1696                 ret = i40e_dcb_setup(dev);
1697                 if (ret) {
1698                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1699                         goto err_dcb;
1700                 }
1701         }
1702
1703         TAILQ_INIT(&pf->flow_list);
1704
1705         return 0;
1706
1707 err_dcb:
1708         /* need to release vmdq resource if exists */
1709         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1710                 i40e_vsi_release(pf->vmdq[i].vsi);
1711                 pf->vmdq[i].vsi = NULL;
1712         }
1713         rte_free(pf->vmdq);
1714         pf->vmdq = NULL;
1715 err:
1716         /* need to release fdir resource if exists */
1717         i40e_fdir_teardown(pf);
1718         return ret;
1719 }
1720
1721 void
1722 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1723 {
1724         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1725         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1726         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1727         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1728         uint16_t msix_vect = vsi->msix_intr;
1729         uint16_t i;
1730
1731         for (i = 0; i < vsi->nb_qps; i++) {
1732                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1733                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1734                 rte_wmb();
1735         }
1736
1737         if (vsi->type != I40E_VSI_SRIOV) {
1738                 if (!rte_intr_allow_others(intr_handle)) {
1739                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1740                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1741                         I40E_WRITE_REG(hw,
1742                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1743                                        0);
1744                 } else {
1745                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1746                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1747                         I40E_WRITE_REG(hw,
1748                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1749                                                        msix_vect - 1), 0);
1750                 }
1751         } else {
1752                 uint32_t reg;
1753                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1754                         vsi->user_param + (msix_vect - 1);
1755
1756                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1757                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1758         }
1759         I40E_WRITE_FLUSH(hw);
1760 }
1761
1762 static void
1763 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1764                        int base_queue, int nb_queue,
1765                        uint16_t itr_idx)
1766 {
1767         int i;
1768         uint32_t val;
1769         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1770         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1771
1772         /* Bind all RX queues to allocated MSIX interrupt */
1773         for (i = 0; i < nb_queue; i++) {
1774                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1775                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1776                         ((base_queue + i + 1) <<
1777                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1778                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1779                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1780
1781                 if (i == nb_queue - 1)
1782                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1783                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1784         }
1785
1786         /* Write first RX queue to Link list register as the head element */
1787         if (vsi->type != I40E_VSI_SRIOV) {
1788                 uint16_t interval =
1789                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL,
1790                                                pf->support_multi_driver);
1791
1792                 if (msix_vect == I40E_MISC_VEC_ID) {
1793                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1794                                        (base_queue <<
1795                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1796                                        (0x0 <<
1797                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1798                         I40E_WRITE_REG(hw,
1799                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1800                                        interval);
1801                 } else {
1802                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1803                                        (base_queue <<
1804                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1805                                        (0x0 <<
1806                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1807                         I40E_WRITE_REG(hw,
1808                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1809                                                        msix_vect - 1),
1810                                        interval);
1811                 }
1812         } else {
1813                 uint32_t reg;
1814
1815                 if (msix_vect == I40E_MISC_VEC_ID) {
1816                         I40E_WRITE_REG(hw,
1817                                        I40E_VPINT_LNKLST0(vsi->user_param),
1818                                        (base_queue <<
1819                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1820                                        (0x0 <<
1821                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1822                 } else {
1823                         /* num_msix_vectors_vf needs to minus irq0 */
1824                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1825                                 vsi->user_param + (msix_vect - 1);
1826
1827                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1828                                        (base_queue <<
1829                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1830                                        (0x0 <<
1831                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1832                 }
1833         }
1834
1835         I40E_WRITE_FLUSH(hw);
1836 }
1837
1838 void
1839 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1840 {
1841         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1842         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1843         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1844         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1845         uint16_t msix_vect = vsi->msix_intr;
1846         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1847         uint16_t queue_idx = 0;
1848         int record = 0;
1849         int i;
1850
1851         for (i = 0; i < vsi->nb_qps; i++) {
1852                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1853                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1854         }
1855
1856         /* VF bind interrupt */
1857         if (vsi->type == I40E_VSI_SRIOV) {
1858                 __vsi_queues_bind_intr(vsi, msix_vect,
1859                                        vsi->base_queue, vsi->nb_qps,
1860                                        itr_idx);
1861                 return;
1862         }
1863
1864         /* PF & VMDq bind interrupt */
1865         if (rte_intr_dp_is_en(intr_handle)) {
1866                 if (vsi->type == I40E_VSI_MAIN) {
1867                         queue_idx = 0;
1868                         record = 1;
1869                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1870                         struct i40e_vsi *main_vsi =
1871                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1872                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1873                         record = 1;
1874                 }
1875         }
1876
1877         for (i = 0; i < vsi->nb_used_qps; i++) {
1878                 if (nb_msix <= 1) {
1879                         if (!rte_intr_allow_others(intr_handle))
1880                                 /* allow to share MISC_VEC_ID */
1881                                 msix_vect = I40E_MISC_VEC_ID;
1882
1883                         /* no enough msix_vect, map all to one */
1884                         __vsi_queues_bind_intr(vsi, msix_vect,
1885                                                vsi->base_queue + i,
1886                                                vsi->nb_used_qps - i,
1887                                                itr_idx);
1888                         for (; !!record && i < vsi->nb_used_qps; i++)
1889                                 intr_handle->intr_vec[queue_idx + i] =
1890                                         msix_vect;
1891                         break;
1892                 }
1893                 /* 1:1 queue/msix_vect mapping */
1894                 __vsi_queues_bind_intr(vsi, msix_vect,
1895                                        vsi->base_queue + i, 1,
1896                                        itr_idx);
1897                 if (!!record)
1898                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1899
1900                 msix_vect++;
1901                 nb_msix--;
1902         }
1903 }
1904
1905 static void
1906 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1907 {
1908         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1909         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1910         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1911         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1912         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1913         uint16_t msix_intr, i;
1914
1915         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1916                 for (i = 0; i < vsi->nb_msix; i++) {
1917                         msix_intr = vsi->msix_intr + i;
1918                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1919                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1920                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1921                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1922                 }
1923         else
1924                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1925                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1926                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1927                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1928
1929         I40E_WRITE_FLUSH(hw);
1930 }
1931
1932 static void
1933 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1934 {
1935         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1937         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1938         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1939         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1940         uint16_t msix_intr, i;
1941
1942         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1943                 for (i = 0; i < vsi->nb_msix; i++) {
1944                         msix_intr = vsi->msix_intr + i;
1945                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1946                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1947                 }
1948         else
1949                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1950                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1951
1952         I40E_WRITE_FLUSH(hw);
1953 }
1954
1955 static inline uint8_t
1956 i40e_parse_link_speeds(uint16_t link_speeds)
1957 {
1958         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1959
1960         if (link_speeds & ETH_LINK_SPEED_40G)
1961                 link_speed |= I40E_LINK_SPEED_40GB;
1962         if (link_speeds & ETH_LINK_SPEED_25G)
1963                 link_speed |= I40E_LINK_SPEED_25GB;
1964         if (link_speeds & ETH_LINK_SPEED_20G)
1965                 link_speed |= I40E_LINK_SPEED_20GB;
1966         if (link_speeds & ETH_LINK_SPEED_10G)
1967                 link_speed |= I40E_LINK_SPEED_10GB;
1968         if (link_speeds & ETH_LINK_SPEED_1G)
1969                 link_speed |= I40E_LINK_SPEED_1GB;
1970         if (link_speeds & ETH_LINK_SPEED_100M)
1971                 link_speed |= I40E_LINK_SPEED_100MB;
1972
1973         return link_speed;
1974 }
1975
1976 static int
1977 i40e_phy_conf_link(struct i40e_hw *hw,
1978                    uint8_t abilities,
1979                    uint8_t force_speed,
1980                    bool is_up)
1981 {
1982         enum i40e_status_code status;
1983         struct i40e_aq_get_phy_abilities_resp phy_ab;
1984         struct i40e_aq_set_phy_config phy_conf;
1985         enum i40e_aq_phy_type cnt;
1986         uint8_t avail_speed;
1987         uint32_t phy_type_mask = 0;
1988
1989         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1990                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1991                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1992                         I40E_AQ_PHY_FLAG_LOW_POWER;
1993         int ret = -ENOTSUP;
1994
1995         /* To get phy capabilities of available speeds. */
1996         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
1997                                               NULL);
1998         if (status) {
1999                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2000                                 status);
2001                 return ret;
2002         }
2003         avail_speed = phy_ab.link_speed;
2004
2005         /* To get the current phy config. */
2006         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2007                                               NULL);
2008         if (status) {
2009                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2010                                 status);
2011                 return ret;
2012         }
2013
2014         /* If link needs to go up and it is in autoneg mode the speed is OK,
2015          * no need to set up again.
2016          */
2017         if (is_up && phy_ab.phy_type != 0 &&
2018                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2019                      phy_ab.link_speed != 0)
2020                 return I40E_SUCCESS;
2021
2022         memset(&phy_conf, 0, sizeof(phy_conf));
2023
2024         /* bits 0-2 use the values from get_phy_abilities_resp */
2025         abilities &= ~mask;
2026         abilities |= phy_ab.abilities & mask;
2027
2028         phy_conf.abilities = abilities;
2029
2030         /* If link needs to go up, but the force speed is not supported,
2031          * Warn users and config the default available speeds.
2032          */
2033         if (is_up && !(force_speed & avail_speed)) {
2034                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2035                 phy_conf.link_speed = avail_speed;
2036         } else {
2037                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2038         }
2039
2040         /* PHY type mask needs to include each type except PHY type extension */
2041         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2042                 phy_type_mask |= 1 << cnt;
2043
2044         /* use get_phy_abilities_resp value for the rest */
2045         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2046         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2047                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2048                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2049         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2050         phy_conf.eee_capability = phy_ab.eee_capability;
2051         phy_conf.eeer = phy_ab.eeer_val;
2052         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2053
2054         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2055                     phy_ab.abilities, phy_ab.link_speed);
2056         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2057                     phy_conf.abilities, phy_conf.link_speed);
2058
2059         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2060         if (status)
2061                 return ret;
2062
2063         return I40E_SUCCESS;
2064 }
2065
2066 static int
2067 i40e_apply_link_speed(struct rte_eth_dev *dev)
2068 {
2069         uint8_t speed;
2070         uint8_t abilities = 0;
2071         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072         struct rte_eth_conf *conf = &dev->data->dev_conf;
2073
2074         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2075                 conf->link_speeds = ETH_LINK_SPEED_40G |
2076                                     ETH_LINK_SPEED_25G |
2077                                     ETH_LINK_SPEED_20G |
2078                                     ETH_LINK_SPEED_10G |
2079                                     ETH_LINK_SPEED_1G |
2080                                     ETH_LINK_SPEED_100M;
2081         }
2082         speed = i40e_parse_link_speeds(conf->link_speeds);
2083         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2084                      I40E_AQ_PHY_AN_ENABLED |
2085                      I40E_AQ_PHY_LINK_ENABLED;
2086
2087         return i40e_phy_conf_link(hw, abilities, speed, true);
2088 }
2089
2090 static int
2091 i40e_dev_start(struct rte_eth_dev *dev)
2092 {
2093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct i40e_vsi *main_vsi = pf->main_vsi;
2096         int ret, i;
2097         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2098         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2099         uint32_t intr_vector = 0;
2100         struct i40e_vsi *vsi;
2101
2102         hw->adapter_stopped = 0;
2103
2104         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2105                 PMD_INIT_LOG(ERR,
2106                 "Invalid link_speeds for port %u, autonegotiation disabled",
2107                               dev->data->port_id);
2108                 return -EINVAL;
2109         }
2110
2111         rte_intr_disable(intr_handle);
2112
2113         if ((rte_intr_cap_multiple(intr_handle) ||
2114              !RTE_ETH_DEV_SRIOV(dev).active) &&
2115             dev->data->dev_conf.intr_conf.rxq != 0) {
2116                 intr_vector = dev->data->nb_rx_queues;
2117                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2118                 if (ret)
2119                         return ret;
2120         }
2121
2122         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2123                 intr_handle->intr_vec =
2124                         rte_zmalloc("intr_vec",
2125                                     dev->data->nb_rx_queues * sizeof(int),
2126                                     0);
2127                 if (!intr_handle->intr_vec) {
2128                         PMD_INIT_LOG(ERR,
2129                                 "Failed to allocate %d rx_queues intr_vec",
2130                                 dev->data->nb_rx_queues);
2131                         return -ENOMEM;
2132                 }
2133         }
2134
2135         /* Initialize VSI */
2136         ret = i40e_dev_rxtx_init(pf);
2137         if (ret != I40E_SUCCESS) {
2138                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2139                 goto err_up;
2140         }
2141
2142         /* Map queues with MSIX interrupt */
2143         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2144                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2145         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2146         i40e_vsi_enable_queues_intr(main_vsi);
2147
2148         /* Map VMDQ VSI queues with MSIX interrupt */
2149         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2150                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2151                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2152                                           I40E_ITR_INDEX_DEFAULT);
2153                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2154         }
2155
2156         /* enable FDIR MSIX interrupt */
2157         if (pf->fdir.fdir_vsi) {
2158                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2159                                           I40E_ITR_INDEX_NONE);
2160                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2161         }
2162
2163         /* Enable all queues which have been configured */
2164         ret = i40e_dev_switch_queues(pf, TRUE);
2165         if (ret != I40E_SUCCESS) {
2166                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2167                 goto err_up;
2168         }
2169
2170         /* Enable receiving broadcast packets */
2171         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2172         if (ret != I40E_SUCCESS)
2173                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2174
2175         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2176                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2177                                                 true, NULL);
2178                 if (ret != I40E_SUCCESS)
2179                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2180         }
2181
2182         /* Enable the VLAN promiscuous mode. */
2183         if (pf->vfs) {
2184                 for (i = 0; i < pf->vf_num; i++) {
2185                         vsi = pf->vfs[i].vsi;
2186                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2187                                                      true, NULL);
2188                 }
2189         }
2190
2191         /* Apply link configure */
2192         ret = i40e_apply_link_speed(dev);
2193         if (I40E_SUCCESS != ret) {
2194                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2195                 goto err_up;
2196         }
2197
2198         if (!rte_intr_allow_others(intr_handle)) {
2199                 rte_intr_callback_unregister(intr_handle,
2200                                              i40e_dev_interrupt_handler,
2201                                              (void *)dev);
2202                 /* configure and enable device interrupt */
2203                 i40e_pf_config_irq0(hw, FALSE);
2204                 i40e_pf_enable_irq0(hw);
2205
2206                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2207                         PMD_INIT_LOG(INFO,
2208                                 "lsc won't enable because of no intr multiplex");
2209         } else {
2210                 ret = i40e_aq_set_phy_int_mask(hw,
2211                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2212                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2213                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2214                 if (ret != I40E_SUCCESS)
2215                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2216
2217                 /* Call get_link_info aq commond to enable/disable LSE */
2218                 i40e_dev_link_update(dev, 0);
2219         }
2220
2221         /* enable uio intr after callback register */
2222         rte_intr_enable(intr_handle);
2223
2224         i40e_filter_restore(pf);
2225
2226         if (pf->tm_conf.root && !pf->tm_conf.committed)
2227                 PMD_DRV_LOG(WARNING,
2228                             "please call hierarchy_commit() "
2229                             "before starting the port");
2230
2231         return I40E_SUCCESS;
2232
2233 err_up:
2234         i40e_dev_switch_queues(pf, FALSE);
2235         i40e_dev_clear_queues(dev);
2236
2237         return ret;
2238 }
2239
2240 static void
2241 i40e_dev_stop(struct rte_eth_dev *dev)
2242 {
2243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245         struct i40e_vsi *main_vsi = pf->main_vsi;
2246         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2247         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2248         int i;
2249
2250         if (hw->adapter_stopped == 1)
2251                 return;
2252         /* Disable all queues */
2253         i40e_dev_switch_queues(pf, FALSE);
2254
2255         /* un-map queues with interrupt registers */
2256         i40e_vsi_disable_queues_intr(main_vsi);
2257         i40e_vsi_queues_unbind_intr(main_vsi);
2258
2259         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2260                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2261                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2262         }
2263
2264         if (pf->fdir.fdir_vsi) {
2265                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2266                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2267         }
2268         /* Clear all queues and release memory */
2269         i40e_dev_clear_queues(dev);
2270
2271         /* Set link down */
2272         i40e_dev_set_link_down(dev);
2273
2274         if (!rte_intr_allow_others(intr_handle))
2275                 /* resume to the default handler */
2276                 rte_intr_callback_register(intr_handle,
2277                                            i40e_dev_interrupt_handler,
2278                                            (void *)dev);
2279
2280         /* Clean datapath event and queue/vec mapping */
2281         rte_intr_efd_disable(intr_handle);
2282         if (intr_handle->intr_vec) {
2283                 rte_free(intr_handle->intr_vec);
2284                 intr_handle->intr_vec = NULL;
2285         }
2286
2287         /* reset hierarchy commit */
2288         pf->tm_conf.committed = false;
2289
2290         hw->adapter_stopped = 1;
2291 }
2292
2293 static void
2294 i40e_dev_close(struct rte_eth_dev *dev)
2295 {
2296         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2297         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2299         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2300         struct i40e_mirror_rule *p_mirror;
2301         uint32_t reg;
2302         int i;
2303         int ret;
2304
2305         PMD_INIT_FUNC_TRACE();
2306
2307         i40e_dev_stop(dev);
2308
2309         /* Remove all mirror rules */
2310         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2311                 ret = i40e_aq_del_mirror_rule(hw,
2312                                               pf->main_vsi->veb->seid,
2313                                               p_mirror->rule_type,
2314                                               p_mirror->entries,
2315                                               p_mirror->num_entries,
2316                                               p_mirror->id);
2317                 if (ret < 0)
2318                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2319                                     "status = %d, aq_err = %d.", ret,
2320                                     hw->aq.asq_last_status);
2321
2322                 /* remove mirror software resource anyway */
2323                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2324                 rte_free(p_mirror);
2325                 pf->nb_mirror_rule--;
2326         }
2327
2328         i40e_dev_free_queues(dev);
2329
2330         /* Disable interrupt */
2331         i40e_pf_disable_irq0(hw);
2332         rte_intr_disable(intr_handle);
2333
2334         i40e_fdir_teardown(pf);
2335
2336         /* shutdown and destroy the HMC */
2337         i40e_shutdown_lan_hmc(hw);
2338
2339         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2340                 i40e_vsi_release(pf->vmdq[i].vsi);
2341                 pf->vmdq[i].vsi = NULL;
2342         }
2343         rte_free(pf->vmdq);
2344         pf->vmdq = NULL;
2345
2346         /* release all the existing VSIs and VEBs */
2347         i40e_vsi_release(pf->main_vsi);
2348
2349         /* shutdown the adminq */
2350         i40e_aq_queue_shutdown(hw, true);
2351         i40e_shutdown_adminq(hw);
2352
2353         i40e_res_pool_destroy(&pf->qp_pool);
2354         i40e_res_pool_destroy(&pf->msix_pool);
2355
2356         /* force a PF reset to clean anything leftover */
2357         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2358         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2359                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2360         I40E_WRITE_FLUSH(hw);
2361 }
2362
2363 /*
2364  * Reset PF device only to re-initialize resources in PMD layer
2365  */
2366 static int
2367 i40e_dev_reset(struct rte_eth_dev *dev)
2368 {
2369         int ret;
2370
2371         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2372          * its VF to make them align with it. The detailed notification
2373          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2374          * To avoid unexpected behavior in VF, currently reset of PF with
2375          * SR-IOV activation is not supported. It might be supported later.
2376          */
2377         if (dev->data->sriov.active)
2378                 return -ENOTSUP;
2379
2380         ret = eth_i40e_dev_uninit(dev);
2381         if (ret)
2382                 return ret;
2383
2384         ret = eth_i40e_dev_init(dev);
2385
2386         return ret;
2387 }
2388
2389 static void
2390 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2391 {
2392         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2393         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394         struct i40e_vsi *vsi = pf->main_vsi;
2395         int status;
2396
2397         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2398                                                      true, NULL, true);
2399         if (status != I40E_SUCCESS)
2400                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2401
2402         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2403                                                         TRUE, NULL);
2404         if (status != I40E_SUCCESS)
2405                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2406
2407 }
2408
2409 static void
2410 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2411 {
2412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414         struct i40e_vsi *vsi = pf->main_vsi;
2415         int status;
2416
2417         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2418                                                      false, NULL, true);
2419         if (status != I40E_SUCCESS)
2420                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2421
2422         /* must remain in all_multicast mode */
2423         if (dev->data->all_multicast == 1)
2424                 return;
2425
2426         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2427                                                         false, NULL);
2428         if (status != I40E_SUCCESS)
2429                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2430 }
2431
2432 static void
2433 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2434 {
2435         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437         struct i40e_vsi *vsi = pf->main_vsi;
2438         int ret;
2439
2440         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2441         if (ret != I40E_SUCCESS)
2442                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2443 }
2444
2445 static void
2446 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2447 {
2448         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2449         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2450         struct i40e_vsi *vsi = pf->main_vsi;
2451         int ret;
2452
2453         if (dev->data->promiscuous == 1)
2454                 return; /* must remain in all_multicast mode */
2455
2456         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2457                                 vsi->seid, FALSE, NULL);
2458         if (ret != I40E_SUCCESS)
2459                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2460 }
2461
2462 /*
2463  * Set device link up.
2464  */
2465 static int
2466 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2467 {
2468         /* re-apply link speed setting */
2469         return i40e_apply_link_speed(dev);
2470 }
2471
2472 /*
2473  * Set device link down.
2474  */
2475 static int
2476 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2477 {
2478         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2479         uint8_t abilities = 0;
2480         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481
2482         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2483         return i40e_phy_conf_link(hw, abilities, speed, false);
2484 }
2485
2486 static __rte_always_inline void
2487 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2488 {
2489 /* Link status registers and values*/
2490 #define I40E_PRTMAC_LINKSTA             0x001E2420
2491 #define I40E_REG_LINK_UP                0x40000080
2492 #define I40E_PRTMAC_MACC                0x001E24E0
2493 #define I40E_REG_MACC_25GB              0x00020000
2494 #define I40E_REG_SPEED_MASK             0x38000000
2495 #define I40E_REG_SPEED_100MB            0x00000000
2496 #define I40E_REG_SPEED_1GB              0x08000000
2497 #define I40E_REG_SPEED_10GB             0x10000000
2498 #define I40E_REG_SPEED_20GB             0x20000000
2499 #define I40E_REG_SPEED_25_40GB          0x18000000
2500         uint32_t link_speed;
2501         uint32_t reg_val;
2502
2503         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2504         link_speed = reg_val & I40E_REG_SPEED_MASK;
2505         reg_val &= I40E_REG_LINK_UP;
2506         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2507
2508         if (unlikely(link->link_status == 0))
2509                 return;
2510
2511         /* Parse the link status */
2512         switch (link_speed) {
2513         case I40E_REG_SPEED_100MB:
2514                 link->link_speed = ETH_SPEED_NUM_100M;
2515                 break;
2516         case I40E_REG_SPEED_1GB:
2517                 link->link_speed = ETH_SPEED_NUM_1G;
2518                 break;
2519         case I40E_REG_SPEED_10GB:
2520                 link->link_speed = ETH_SPEED_NUM_10G;
2521                 break;
2522         case I40E_REG_SPEED_20GB:
2523                 link->link_speed = ETH_SPEED_NUM_20G;
2524                 break;
2525         case I40E_REG_SPEED_25_40GB:
2526                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2527
2528                 if (reg_val & I40E_REG_MACC_25GB)
2529                         link->link_speed = ETH_SPEED_NUM_25G;
2530                 else
2531                         link->link_speed = ETH_SPEED_NUM_40G;
2532
2533                 break;
2534         default:
2535                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2536                 break;
2537         }
2538 }
2539
2540 static __rte_always_inline void
2541 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2542         bool enable_lse, int wait_to_complete)
2543 {
2544 #define CHECK_INTERVAL             100  /* 100ms */
2545 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2546         uint32_t rep_cnt = MAX_REPEAT_TIME;
2547         struct i40e_link_status link_status;
2548         int status;
2549
2550         memset(&link_status, 0, sizeof(link_status));
2551
2552         do {
2553                 /* Get link status information from hardware */
2554                 status = i40e_aq_get_link_info(hw, enable_lse,
2555                                                 &link_status, NULL);
2556                 if (unlikely(status != I40E_SUCCESS)) {
2557                         link->link_speed = ETH_SPEED_NUM_100M;
2558                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2559                         PMD_DRV_LOG(ERR, "Failed to get link info");
2560                         return;
2561                 }
2562
2563                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2564                 if (!wait_to_complete || link->link_status)
2565                         break;
2566
2567                 rte_delay_ms(CHECK_INTERVAL);
2568         } while (--rep_cnt);
2569
2570         /* Parse the link status */
2571         switch (link_status.link_speed) {
2572         case I40E_LINK_SPEED_100MB:
2573                 link->link_speed = ETH_SPEED_NUM_100M;
2574                 break;
2575         case I40E_LINK_SPEED_1GB:
2576                 link->link_speed = ETH_SPEED_NUM_1G;
2577                 break;
2578         case I40E_LINK_SPEED_10GB:
2579                 link->link_speed = ETH_SPEED_NUM_10G;
2580                 break;
2581         case I40E_LINK_SPEED_20GB:
2582                 link->link_speed = ETH_SPEED_NUM_20G;
2583                 break;
2584         case I40E_LINK_SPEED_25GB:
2585                 link->link_speed = ETH_SPEED_NUM_25G;
2586                 break;
2587         case I40E_LINK_SPEED_40GB:
2588                 link->link_speed = ETH_SPEED_NUM_40G;
2589                 break;
2590         default:
2591                 link->link_speed = ETH_SPEED_NUM_100M;
2592                 break;
2593         }
2594 }
2595
2596 int
2597 i40e_dev_link_update(struct rte_eth_dev *dev,
2598                      int wait_to_complete)
2599 {
2600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2601         struct rte_eth_link link, old;
2602         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2603
2604         memset(&link, 0, sizeof(link));
2605         memset(&old, 0, sizeof(old));
2606
2607         rte_i40e_dev_atomic_read_link_status(dev, &old);
2608
2609         /* i40e uses full duplex only */
2610         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2611         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2612                         ETH_LINK_SPEED_FIXED);
2613
2614         if (!wait_to_complete && !enable_lse)
2615                 update_link_reg(hw, &link);
2616         else
2617                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2618
2619         rte_i40e_dev_atomic_write_link_status(dev, &link);
2620         if (link.link_status == old.link_status)
2621                 return -1;
2622
2623         i40e_notify_all_vfs_link_status(dev);
2624
2625         return 0;
2626 }
2627
2628 /* Get all the statistics of a VSI */
2629 void
2630 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2631 {
2632         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2633         struct i40e_eth_stats *nes = &vsi->eth_stats;
2634         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2635         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2636
2637         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2638                             vsi->offset_loaded, &oes->rx_bytes,
2639                             &nes->rx_bytes);
2640         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2641                             vsi->offset_loaded, &oes->rx_unicast,
2642                             &nes->rx_unicast);
2643         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2644                             vsi->offset_loaded, &oes->rx_multicast,
2645                             &nes->rx_multicast);
2646         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2647                             vsi->offset_loaded, &oes->rx_broadcast,
2648                             &nes->rx_broadcast);
2649         /* exclude CRC bytes */
2650         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2651                 nes->rx_broadcast) * ETHER_CRC_LEN;
2652
2653         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2654                             &oes->rx_discards, &nes->rx_discards);
2655         /* GLV_REPC not supported */
2656         /* GLV_RMPC not supported */
2657         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2658                             &oes->rx_unknown_protocol,
2659                             &nes->rx_unknown_protocol);
2660         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2661                             vsi->offset_loaded, &oes->tx_bytes,
2662                             &nes->tx_bytes);
2663         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2664                             vsi->offset_loaded, &oes->tx_unicast,
2665                             &nes->tx_unicast);
2666         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2667                             vsi->offset_loaded, &oes->tx_multicast,
2668                             &nes->tx_multicast);
2669         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2670                             vsi->offset_loaded,  &oes->tx_broadcast,
2671                             &nes->tx_broadcast);
2672         /* GLV_TDPC not supported */
2673         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2674                             &oes->tx_errors, &nes->tx_errors);
2675         vsi->offset_loaded = true;
2676
2677         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2678                     vsi->vsi_id);
2679         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2680         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2681         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2682         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2683         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2684         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2685                     nes->rx_unknown_protocol);
2686         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2687         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2688         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2689         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2690         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2691         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2692         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2693                     vsi->vsi_id);
2694 }
2695
2696 static void
2697 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2698 {
2699         unsigned int i;
2700         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2701         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2702
2703         /* Get rx/tx bytes of internal transfer packets */
2704         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2705                         I40E_GLV_GORCL(hw->port),
2706                         pf->offset_loaded,
2707                         &pf->internal_stats_offset.rx_bytes,
2708                         &pf->internal_stats.rx_bytes);
2709
2710         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2711                         I40E_GLV_GOTCL(hw->port),
2712                         pf->offset_loaded,
2713                         &pf->internal_stats_offset.tx_bytes,
2714                         &pf->internal_stats.tx_bytes);
2715         /* Get total internal rx packet count */
2716         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2717                             I40E_GLV_UPRCL(hw->port),
2718                             pf->offset_loaded,
2719                             &pf->internal_stats_offset.rx_unicast,
2720                             &pf->internal_stats.rx_unicast);
2721         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2722                             I40E_GLV_MPRCL(hw->port),
2723                             pf->offset_loaded,
2724                             &pf->internal_stats_offset.rx_multicast,
2725                             &pf->internal_stats.rx_multicast);
2726         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2727                             I40E_GLV_BPRCL(hw->port),
2728                             pf->offset_loaded,
2729                             &pf->internal_stats_offset.rx_broadcast,
2730                             &pf->internal_stats.rx_broadcast);
2731         /* Get total internal tx packet count */
2732         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2733                             I40E_GLV_UPTCL(hw->port),
2734                             pf->offset_loaded,
2735                             &pf->internal_stats_offset.tx_unicast,
2736                             &pf->internal_stats.tx_unicast);
2737         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2738                             I40E_GLV_MPTCL(hw->port),
2739                             pf->offset_loaded,
2740                             &pf->internal_stats_offset.tx_multicast,
2741                             &pf->internal_stats.tx_multicast);
2742         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2743                             I40E_GLV_BPTCL(hw->port),
2744                             pf->offset_loaded,
2745                             &pf->internal_stats_offset.tx_broadcast,
2746                             &pf->internal_stats.tx_broadcast);
2747
2748         /* exclude CRC size */
2749         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2750                 pf->internal_stats.rx_multicast +
2751                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2752
2753         /* Get statistics of struct i40e_eth_stats */
2754         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2755                             I40E_GLPRT_GORCL(hw->port),
2756                             pf->offset_loaded, &os->eth.rx_bytes,
2757                             &ns->eth.rx_bytes);
2758         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2759                             I40E_GLPRT_UPRCL(hw->port),
2760                             pf->offset_loaded, &os->eth.rx_unicast,
2761                             &ns->eth.rx_unicast);
2762         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2763                             I40E_GLPRT_MPRCL(hw->port),
2764                             pf->offset_loaded, &os->eth.rx_multicast,
2765                             &ns->eth.rx_multicast);
2766         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2767                             I40E_GLPRT_BPRCL(hw->port),
2768                             pf->offset_loaded, &os->eth.rx_broadcast,
2769                             &ns->eth.rx_broadcast);
2770         /* Workaround: CRC size should not be included in byte statistics,
2771          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2772          */
2773         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2774                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2775
2776         /* exclude internal rx bytes
2777          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2778          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2779          * value.
2780          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2781          */
2782         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2783                 ns->eth.rx_bytes = 0;
2784         else
2785                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2786
2787         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2788                 ns->eth.rx_unicast = 0;
2789         else
2790                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2791
2792         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2793                 ns->eth.rx_multicast = 0;
2794         else
2795                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2796
2797         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2798                 ns->eth.rx_broadcast = 0;
2799         else
2800                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2801
2802         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2803                             pf->offset_loaded, &os->eth.rx_discards,
2804                             &ns->eth.rx_discards);
2805         /* GLPRT_REPC not supported */
2806         /* GLPRT_RMPC not supported */
2807         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2808                             pf->offset_loaded,
2809                             &os->eth.rx_unknown_protocol,
2810                             &ns->eth.rx_unknown_protocol);
2811         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2812                             I40E_GLPRT_GOTCL(hw->port),
2813                             pf->offset_loaded, &os->eth.tx_bytes,
2814                             &ns->eth.tx_bytes);
2815         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2816                             I40E_GLPRT_UPTCL(hw->port),
2817                             pf->offset_loaded, &os->eth.tx_unicast,
2818                             &ns->eth.tx_unicast);
2819         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2820                             I40E_GLPRT_MPTCL(hw->port),
2821                             pf->offset_loaded, &os->eth.tx_multicast,
2822                             &ns->eth.tx_multicast);
2823         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2824                             I40E_GLPRT_BPTCL(hw->port),
2825                             pf->offset_loaded, &os->eth.tx_broadcast,
2826                             &ns->eth.tx_broadcast);
2827         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2828                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2829
2830         /* exclude internal tx bytes
2831          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2832          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2833          * value.
2834          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2835          */
2836         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2837                 ns->eth.tx_bytes = 0;
2838         else
2839                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2840
2841         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2842                 ns->eth.tx_unicast = 0;
2843         else
2844                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2845
2846         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2847                 ns->eth.tx_multicast = 0;
2848         else
2849                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2850
2851         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2852                 ns->eth.tx_broadcast = 0;
2853         else
2854                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2855
2856         /* GLPRT_TEPC not supported */
2857
2858         /* additional port specific stats */
2859         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2860                             pf->offset_loaded, &os->tx_dropped_link_down,
2861                             &ns->tx_dropped_link_down);
2862         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2863                             pf->offset_loaded, &os->crc_errors,
2864                             &ns->crc_errors);
2865         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2866                             pf->offset_loaded, &os->illegal_bytes,
2867                             &ns->illegal_bytes);
2868         /* GLPRT_ERRBC not supported */
2869         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2870                             pf->offset_loaded, &os->mac_local_faults,
2871                             &ns->mac_local_faults);
2872         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2873                             pf->offset_loaded, &os->mac_remote_faults,
2874                             &ns->mac_remote_faults);
2875         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2876                             pf->offset_loaded, &os->rx_length_errors,
2877                             &ns->rx_length_errors);
2878         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2879                             pf->offset_loaded, &os->link_xon_rx,
2880                             &ns->link_xon_rx);
2881         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2882                             pf->offset_loaded, &os->link_xoff_rx,
2883                             &ns->link_xoff_rx);
2884         for (i = 0; i < 8; i++) {
2885                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2886                                     pf->offset_loaded,
2887                                     &os->priority_xon_rx[i],
2888                                     &ns->priority_xon_rx[i]);
2889                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2890                                     pf->offset_loaded,
2891                                     &os->priority_xoff_rx[i],
2892                                     &ns->priority_xoff_rx[i]);
2893         }
2894         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2895                             pf->offset_loaded, &os->link_xon_tx,
2896                             &ns->link_xon_tx);
2897         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2898                             pf->offset_loaded, &os->link_xoff_tx,
2899                             &ns->link_xoff_tx);
2900         for (i = 0; i < 8; i++) {
2901                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2902                                     pf->offset_loaded,
2903                                     &os->priority_xon_tx[i],
2904                                     &ns->priority_xon_tx[i]);
2905                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2906                                     pf->offset_loaded,
2907                                     &os->priority_xoff_tx[i],
2908                                     &ns->priority_xoff_tx[i]);
2909                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2910                                     pf->offset_loaded,
2911                                     &os->priority_xon_2_xoff[i],
2912                                     &ns->priority_xon_2_xoff[i]);
2913         }
2914         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2915                             I40E_GLPRT_PRC64L(hw->port),
2916                             pf->offset_loaded, &os->rx_size_64,
2917                             &ns->rx_size_64);
2918         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2919                             I40E_GLPRT_PRC127L(hw->port),
2920                             pf->offset_loaded, &os->rx_size_127,
2921                             &ns->rx_size_127);
2922         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2923                             I40E_GLPRT_PRC255L(hw->port),
2924                             pf->offset_loaded, &os->rx_size_255,
2925                             &ns->rx_size_255);
2926         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2927                             I40E_GLPRT_PRC511L(hw->port),
2928                             pf->offset_loaded, &os->rx_size_511,
2929                             &ns->rx_size_511);
2930         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2931                             I40E_GLPRT_PRC1023L(hw->port),
2932                             pf->offset_loaded, &os->rx_size_1023,
2933                             &ns->rx_size_1023);
2934         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2935                             I40E_GLPRT_PRC1522L(hw->port),
2936                             pf->offset_loaded, &os->rx_size_1522,
2937                             &ns->rx_size_1522);
2938         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2939                             I40E_GLPRT_PRC9522L(hw->port),
2940                             pf->offset_loaded, &os->rx_size_big,
2941                             &ns->rx_size_big);
2942         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2943                             pf->offset_loaded, &os->rx_undersize,
2944                             &ns->rx_undersize);
2945         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2946                             pf->offset_loaded, &os->rx_fragments,
2947                             &ns->rx_fragments);
2948         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2949                             pf->offset_loaded, &os->rx_oversize,
2950                             &ns->rx_oversize);
2951         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2952                             pf->offset_loaded, &os->rx_jabber,
2953                             &ns->rx_jabber);
2954         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2955                             I40E_GLPRT_PTC64L(hw->port),
2956                             pf->offset_loaded, &os->tx_size_64,
2957                             &ns->tx_size_64);
2958         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2959                             I40E_GLPRT_PTC127L(hw->port),
2960                             pf->offset_loaded, &os->tx_size_127,
2961                             &ns->tx_size_127);
2962         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2963                             I40E_GLPRT_PTC255L(hw->port),
2964                             pf->offset_loaded, &os->tx_size_255,
2965                             &ns->tx_size_255);
2966         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2967                             I40E_GLPRT_PTC511L(hw->port),
2968                             pf->offset_loaded, &os->tx_size_511,
2969                             &ns->tx_size_511);
2970         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2971                             I40E_GLPRT_PTC1023L(hw->port),
2972                             pf->offset_loaded, &os->tx_size_1023,
2973                             &ns->tx_size_1023);
2974         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2975                             I40E_GLPRT_PTC1522L(hw->port),
2976                             pf->offset_loaded, &os->tx_size_1522,
2977                             &ns->tx_size_1522);
2978         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2979                             I40E_GLPRT_PTC9522L(hw->port),
2980                             pf->offset_loaded, &os->tx_size_big,
2981                             &ns->tx_size_big);
2982         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2983                            pf->offset_loaded,
2984                            &os->fd_sb_match, &ns->fd_sb_match);
2985         /* GLPRT_MSPDC not supported */
2986         /* GLPRT_XEC not supported */
2987
2988         pf->offset_loaded = true;
2989
2990         if (pf->main_vsi)
2991                 i40e_update_vsi_stats(pf->main_vsi);
2992 }
2993
2994 /* Get all statistics of a port */
2995 static int
2996 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2997 {
2998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2999         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3000         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3001         unsigned i;
3002
3003         /* call read registers - updates values, now write them to struct */
3004         i40e_read_stats_registers(pf, hw);
3005
3006         stats->ipackets = ns->eth.rx_unicast +
3007                         ns->eth.rx_multicast +
3008                         ns->eth.rx_broadcast -
3009                         ns->eth.rx_discards -
3010                         pf->main_vsi->eth_stats.rx_discards;
3011         stats->opackets = ns->eth.tx_unicast +
3012                         ns->eth.tx_multicast +
3013                         ns->eth.tx_broadcast;
3014         stats->ibytes   = ns->eth.rx_bytes;
3015         stats->obytes   = ns->eth.tx_bytes;
3016         stats->oerrors  = ns->eth.tx_errors +
3017                         pf->main_vsi->eth_stats.tx_errors;
3018
3019         /* Rx Errors */
3020         stats->imissed  = ns->eth.rx_discards +
3021                         pf->main_vsi->eth_stats.rx_discards;
3022         stats->ierrors  = ns->crc_errors +
3023                         ns->rx_length_errors + ns->rx_undersize +
3024                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3025
3026         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3027         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3028         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3029         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3030         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3031         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3032         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3033                     ns->eth.rx_unknown_protocol);
3034         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3035         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3036         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3037         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3038         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3039         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3040
3041         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3042                     ns->tx_dropped_link_down);
3043         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3044         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3045                     ns->illegal_bytes);
3046         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3047         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3048                     ns->mac_local_faults);
3049         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3050                     ns->mac_remote_faults);
3051         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3052                     ns->rx_length_errors);
3053         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3054         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3055         for (i = 0; i < 8; i++) {
3056                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3057                                 i, ns->priority_xon_rx[i]);
3058                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3059                                 i, ns->priority_xoff_rx[i]);
3060         }
3061         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3062         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3063         for (i = 0; i < 8; i++) {
3064                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3065                                 i, ns->priority_xon_tx[i]);
3066                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3067                                 i, ns->priority_xoff_tx[i]);
3068                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3069                                 i, ns->priority_xon_2_xoff[i]);
3070         }
3071         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3072         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3073         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3074         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3075         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3076         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3077         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3078         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3079         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3080         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3081         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3082         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3083         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3084         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3085         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3086         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3087         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3088         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3089         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3090                         ns->mac_short_packet_dropped);
3091         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3092                     ns->checksum_error);
3093         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3094         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3095         return 0;
3096 }
3097
3098 /* Reset the statistics */
3099 static void
3100 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3101 {
3102         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3103         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104
3105         /* Mark PF and VSI stats to update the offset, aka "reset" */
3106         pf->offset_loaded = false;
3107         if (pf->main_vsi)
3108                 pf->main_vsi->offset_loaded = false;
3109
3110         /* read the stats, reading current register values into offset */
3111         i40e_read_stats_registers(pf, hw);
3112 }
3113
3114 static uint32_t
3115 i40e_xstats_calc_num(void)
3116 {
3117         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3118                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3119                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3120 }
3121
3122 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3123                                      struct rte_eth_xstat_name *xstats_names,
3124                                      __rte_unused unsigned limit)
3125 {
3126         unsigned count = 0;
3127         unsigned i, prio;
3128
3129         if (xstats_names == NULL)
3130                 return i40e_xstats_calc_num();
3131
3132         /* Note: limit checked in rte_eth_xstats_names() */
3133
3134         /* Get stats from i40e_eth_stats struct */
3135         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3136                 snprintf(xstats_names[count].name,
3137                          sizeof(xstats_names[count].name),
3138                          "%s", rte_i40e_stats_strings[i].name);
3139                 count++;
3140         }
3141
3142         /* Get individiual stats from i40e_hw_port struct */
3143         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3144                 snprintf(xstats_names[count].name,
3145                         sizeof(xstats_names[count].name),
3146                          "%s", rte_i40e_hw_port_strings[i].name);
3147                 count++;
3148         }
3149
3150         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3151                 for (prio = 0; prio < 8; prio++) {
3152                         snprintf(xstats_names[count].name,
3153                                  sizeof(xstats_names[count].name),
3154                                  "rx_priority%u_%s", prio,
3155                                  rte_i40e_rxq_prio_strings[i].name);
3156                         count++;
3157                 }
3158         }
3159
3160         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3161                 for (prio = 0; prio < 8; prio++) {
3162                         snprintf(xstats_names[count].name,
3163                                  sizeof(xstats_names[count].name),
3164                                  "tx_priority%u_%s", prio,
3165                                  rte_i40e_txq_prio_strings[i].name);
3166                         count++;
3167                 }
3168         }
3169         return count;
3170 }
3171
3172 static int
3173 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3174                     unsigned n)
3175 {
3176         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3177         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3178         unsigned i, count, prio;
3179         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3180
3181         count = i40e_xstats_calc_num();
3182         if (n < count)
3183                 return count;
3184
3185         i40e_read_stats_registers(pf, hw);
3186
3187         if (xstats == NULL)
3188                 return 0;
3189
3190         count = 0;
3191
3192         /* Get stats from i40e_eth_stats struct */
3193         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3194                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3195                         rte_i40e_stats_strings[i].offset);
3196                 xstats[count].id = count;
3197                 count++;
3198         }
3199
3200         /* Get individiual stats from i40e_hw_port struct */
3201         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3202                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3203                         rte_i40e_hw_port_strings[i].offset);
3204                 xstats[count].id = count;
3205                 count++;
3206         }
3207
3208         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3209                 for (prio = 0; prio < 8; prio++) {
3210                         xstats[count].value =
3211                                 *(uint64_t *)(((char *)hw_stats) +
3212                                 rte_i40e_rxq_prio_strings[i].offset +
3213                                 (sizeof(uint64_t) * prio));
3214                         xstats[count].id = count;
3215                         count++;
3216                 }
3217         }
3218
3219         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3220                 for (prio = 0; prio < 8; prio++) {
3221                         xstats[count].value =
3222                                 *(uint64_t *)(((char *)hw_stats) +
3223                                 rte_i40e_txq_prio_strings[i].offset +
3224                                 (sizeof(uint64_t) * prio));
3225                         xstats[count].id = count;
3226                         count++;
3227                 }
3228         }
3229
3230         return count;
3231 }
3232
3233 static int
3234 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3235                                  __rte_unused uint16_t queue_id,
3236                                  __rte_unused uint8_t stat_idx,
3237                                  __rte_unused uint8_t is_rx)
3238 {
3239         PMD_INIT_FUNC_TRACE();
3240
3241         return -ENOSYS;
3242 }
3243
3244 static int
3245 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3246 {
3247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3248         u32 full_ver;
3249         u8 ver, patch;
3250         u16 build;
3251         int ret;
3252
3253         full_ver = hw->nvm.oem_ver;
3254         ver = (u8)(full_ver >> 24);
3255         build = (u16)((full_ver >> 8) & 0xffff);
3256         patch = (u8)(full_ver & 0xff);
3257
3258         ret = snprintf(fw_version, fw_size,
3259                  "%d.%d%d 0x%08x %d.%d.%d",
3260                  ((hw->nvm.version >> 12) & 0xf),
3261                  ((hw->nvm.version >> 4) & 0xff),
3262                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3263                  ver, build, patch);
3264
3265         ret += 1; /* add the size of '\0' */
3266         if (fw_size < (u32)ret)
3267                 return ret;
3268         else
3269                 return 0;
3270 }
3271
3272 static void
3273 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3274 {
3275         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3277         struct i40e_vsi *vsi = pf->main_vsi;
3278         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3279
3280         dev_info->pci_dev = pci_dev;
3281         dev_info->max_rx_queues = vsi->nb_qps;
3282         dev_info->max_tx_queues = vsi->nb_qps;
3283         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3284         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3285         dev_info->max_mac_addrs = vsi->max_macaddrs;
3286         dev_info->max_vfs = pci_dev->max_vfs;
3287         dev_info->rx_offload_capa =
3288                 DEV_RX_OFFLOAD_VLAN_STRIP |
3289                 DEV_RX_OFFLOAD_QINQ_STRIP |
3290                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3291                 DEV_RX_OFFLOAD_UDP_CKSUM |
3292                 DEV_RX_OFFLOAD_TCP_CKSUM;
3293         dev_info->tx_offload_capa =
3294                 DEV_TX_OFFLOAD_VLAN_INSERT |
3295                 DEV_TX_OFFLOAD_QINQ_INSERT |
3296                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3297                 DEV_TX_OFFLOAD_UDP_CKSUM |
3298                 DEV_TX_OFFLOAD_TCP_CKSUM |
3299                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3300                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3301                 DEV_TX_OFFLOAD_TCP_TSO |
3302                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3303                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3304                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3305                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3306         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3307                                                 sizeof(uint32_t);
3308         dev_info->reta_size = pf->hash_lut_size;
3309         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3310
3311         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3312                 .rx_thresh = {
3313                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3314                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3315                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3316                 },
3317                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3318                 .rx_drop_en = 0,
3319         };
3320
3321         dev_info->default_txconf = (struct rte_eth_txconf) {
3322                 .tx_thresh = {
3323                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3324                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3325                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3326                 },
3327                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3328                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3329                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3330                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3331         };
3332
3333         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3334                 .nb_max = I40E_MAX_RING_DESC,
3335                 .nb_min = I40E_MIN_RING_DESC,
3336                 .nb_align = I40E_ALIGN_RING_DESC,
3337         };
3338
3339         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3340                 .nb_max = I40E_MAX_RING_DESC,
3341                 .nb_min = I40E_MIN_RING_DESC,
3342                 .nb_align = I40E_ALIGN_RING_DESC,
3343                 .nb_seg_max = I40E_TX_MAX_SEG,
3344                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3345         };
3346
3347         if (pf->flags & I40E_FLAG_VMDQ) {
3348                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3349                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3350                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3351                                                 pf->max_nb_vmdq_vsi;
3352                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3353                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3354                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3355         }
3356
3357         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3358                 /* For XL710 */
3359                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3360         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3361                 /* For XXV710 */
3362                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3363         else
3364                 /* For X710 */
3365                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3366 }
3367
3368 static int
3369 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3370 {
3371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3372         struct i40e_vsi *vsi = pf->main_vsi;
3373         PMD_INIT_FUNC_TRACE();
3374
3375         if (on)
3376                 return i40e_vsi_add_vlan(vsi, vlan_id);
3377         else
3378                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3379 }
3380
3381 static int
3382 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3383                                 enum rte_vlan_type vlan_type,
3384                                 uint16_t tpid, int qinq)
3385 {
3386         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387         uint64_t reg_r = 0;
3388         uint64_t reg_w = 0;
3389         uint16_t reg_id = 3;
3390         int ret;
3391
3392         if (qinq) {
3393                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3394                         reg_id = 2;
3395         }
3396
3397         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3398                                           &reg_r, NULL);
3399         if (ret != I40E_SUCCESS) {
3400                 PMD_DRV_LOG(ERR,
3401                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3402                            reg_id);
3403                 return -EIO;
3404         }
3405         PMD_DRV_LOG(DEBUG,
3406                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3407                     reg_id, reg_r);
3408
3409         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3410         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3411         if (reg_r == reg_w) {
3412                 PMD_DRV_LOG(DEBUG, "No need to write");
3413                 return 0;
3414         }
3415
3416         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3417                                            reg_w, NULL);
3418         if (ret != I40E_SUCCESS) {
3419                 PMD_DRV_LOG(ERR,
3420                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3421                             reg_id);
3422                 return -EIO;
3423         }
3424         PMD_DRV_LOG(DEBUG,
3425                     "Global register 0x%08x is changed with value 0x%08x",
3426                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3427
3428         return 0;
3429 }
3430
3431 static int
3432 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3433                    enum rte_vlan_type vlan_type,
3434                    uint16_t tpid)
3435 {
3436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3438         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3439         int ret = 0;
3440
3441         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3442              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3443             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3444                 PMD_DRV_LOG(ERR,
3445                             "Unsupported vlan type.");
3446                 return -EINVAL;
3447         }
3448
3449         if (pf->support_multi_driver) {
3450                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3451                 return -ENOTSUP;
3452         }
3453
3454         /* 802.1ad frames ability is added in NVM API 1.7*/
3455         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3456                 if (qinq) {
3457                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3458                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3459                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3460                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3461                 } else {
3462                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3463                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3464                 }
3465                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3466                 if (ret != I40E_SUCCESS) {
3467                         PMD_DRV_LOG(ERR,
3468                                     "Set switch config failed aq_err: %d",
3469                                     hw->aq.asq_last_status);
3470                         ret = -EIO;
3471                 }
3472         } else
3473                 /* If NVM API < 1.7, keep the register setting */
3474                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3475                                                       tpid, qinq);
3476         i40e_global_cfg_warning(I40E_WARNING_TPID);
3477
3478         return ret;
3479 }
3480
3481 static int
3482 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3483 {
3484         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3485         struct i40e_vsi *vsi = pf->main_vsi;
3486
3487         if (mask & ETH_VLAN_FILTER_MASK) {
3488                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3489                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3490                 else
3491                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3492         }
3493
3494         if (mask & ETH_VLAN_STRIP_MASK) {
3495                 /* Enable or disable VLAN stripping */
3496                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3497                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3498                 else
3499                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3500         }
3501
3502         if (mask & ETH_VLAN_EXTEND_MASK) {
3503                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3504                         i40e_vsi_config_double_vlan(vsi, TRUE);
3505                         /* Set global registers with default ethertype. */
3506                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3507                                            ETHER_TYPE_VLAN);
3508                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3509                                            ETHER_TYPE_VLAN);
3510                 }
3511                 else
3512                         i40e_vsi_config_double_vlan(vsi, FALSE);
3513         }
3514
3515         return 0;
3516 }
3517
3518 static void
3519 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3520                           __rte_unused uint16_t queue,
3521                           __rte_unused int on)
3522 {
3523         PMD_INIT_FUNC_TRACE();
3524 }
3525
3526 static int
3527 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3528 {
3529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3530         struct i40e_vsi *vsi = pf->main_vsi;
3531         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3532         struct i40e_vsi_vlan_pvid_info info;
3533
3534         memset(&info, 0, sizeof(info));
3535         info.on = on;
3536         if (info.on)
3537                 info.config.pvid = pvid;
3538         else {
3539                 info.config.reject.tagged =
3540                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3541                 info.config.reject.untagged =
3542                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3543         }
3544
3545         return i40e_vsi_vlan_pvid_set(vsi, &info);
3546 }
3547
3548 static int
3549 i40e_dev_led_on(struct rte_eth_dev *dev)
3550 {
3551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3552         uint32_t mode = i40e_led_get(hw);
3553
3554         if (mode == 0)
3555                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3556
3557         return 0;
3558 }
3559
3560 static int
3561 i40e_dev_led_off(struct rte_eth_dev *dev)
3562 {
3563         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564         uint32_t mode = i40e_led_get(hw);
3565
3566         if (mode != 0)
3567                 i40e_led_set(hw, 0, false);
3568
3569         return 0;
3570 }
3571
3572 static int
3573 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3574 {
3575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3576         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3577
3578         fc_conf->pause_time = pf->fc_conf.pause_time;
3579
3580         /* read out from register, in case they are modified by other port */
3581         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3582                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3583         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3584                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3585
3586         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3587         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3588
3589          /* Return current mode according to actual setting*/
3590         switch (hw->fc.current_mode) {
3591         case I40E_FC_FULL:
3592                 fc_conf->mode = RTE_FC_FULL;
3593                 break;
3594         case I40E_FC_TX_PAUSE:
3595                 fc_conf->mode = RTE_FC_TX_PAUSE;
3596                 break;
3597         case I40E_FC_RX_PAUSE:
3598                 fc_conf->mode = RTE_FC_RX_PAUSE;
3599                 break;
3600         case I40E_FC_NONE:
3601         default:
3602                 fc_conf->mode = RTE_FC_NONE;
3603         };
3604
3605         return 0;
3606 }
3607
3608 static int
3609 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3610 {
3611         uint32_t mflcn_reg, fctrl_reg, reg;
3612         uint32_t max_high_water;
3613         uint8_t i, aq_failure;
3614         int err;
3615         struct i40e_hw *hw;
3616         struct i40e_pf *pf;
3617         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3618                 [RTE_FC_NONE] = I40E_FC_NONE,
3619                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3620                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3621                 [RTE_FC_FULL] = I40E_FC_FULL
3622         };
3623
3624         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3625
3626         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3627         if ((fc_conf->high_water > max_high_water) ||
3628                         (fc_conf->high_water < fc_conf->low_water)) {
3629                 PMD_INIT_LOG(ERR,
3630                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3631                         max_high_water);
3632                 return -EINVAL;
3633         }
3634
3635         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3636         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3637         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3638
3639         pf->fc_conf.pause_time = fc_conf->pause_time;
3640         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3641         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3642
3643         PMD_INIT_FUNC_TRACE();
3644
3645         /* All the link flow control related enable/disable register
3646          * configuration is handle by the F/W
3647          */
3648         err = i40e_set_fc(hw, &aq_failure, true);
3649         if (err < 0)
3650                 return -ENOSYS;
3651
3652         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3653                 /* Configure flow control refresh threshold,
3654                  * the value for stat_tx_pause_refresh_timer[8]
3655                  * is used for global pause operation.
3656                  */
3657
3658                 I40E_WRITE_REG(hw,
3659                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3660                                pf->fc_conf.pause_time);
3661
3662                 /* configure the timer value included in transmitted pause
3663                  * frame,
3664                  * the value for stat_tx_pause_quanta[8] is used for global
3665                  * pause operation
3666                  */
3667                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3668                                pf->fc_conf.pause_time);
3669
3670                 fctrl_reg = I40E_READ_REG(hw,
3671                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3672
3673                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3674                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3675                 else
3676                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3677
3678                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3679                                fctrl_reg);
3680         } else {
3681                 /* Configure pause time (2 TCs per register) */
3682                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3683                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3684                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3685
3686                 /* Configure flow control refresh threshold value */
3687                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3688                                pf->fc_conf.pause_time / 2);
3689
3690                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3691
3692                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3693                  *depending on configuration
3694                  */
3695                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3696                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3697                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3698                 } else {
3699                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3700                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3701                 }
3702
3703                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3704         }
3705
3706         if (!pf->support_multi_driver) {
3707                 /* config water marker both based on the packets and bytes */
3708                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3709                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3710                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3711                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3712                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3713                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3714                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3715                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3716                                   << I40E_KILOSHIFT);
3717                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3718                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3719                                    << I40E_KILOSHIFT);
3720                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3721         } else {
3722                 PMD_DRV_LOG(ERR,
3723                             "Water marker configuration is not supported.");
3724         }
3725
3726         I40E_WRITE_FLUSH(hw);
3727
3728         return 0;
3729 }
3730
3731 static int
3732 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3733                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3734 {
3735         PMD_INIT_FUNC_TRACE();
3736
3737         return -ENOSYS;
3738 }
3739
3740 /* Add a MAC address, and update filters */
3741 static int
3742 i40e_macaddr_add(struct rte_eth_dev *dev,
3743                  struct ether_addr *mac_addr,
3744                  __rte_unused uint32_t index,
3745                  uint32_t pool)
3746 {
3747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3748         struct i40e_mac_filter_info mac_filter;
3749         struct i40e_vsi *vsi;
3750         int ret;
3751
3752         /* If VMDQ not enabled or configured, return */
3753         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3754                           !pf->nb_cfg_vmdq_vsi)) {
3755                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3756                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3757                         pool);
3758                 return -ENOTSUP;
3759         }
3760
3761         if (pool > pf->nb_cfg_vmdq_vsi) {
3762                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3763                                 pool, pf->nb_cfg_vmdq_vsi);
3764                 return -EINVAL;
3765         }
3766
3767         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3768         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3769                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3770         else
3771                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3772
3773         if (pool == 0)
3774                 vsi = pf->main_vsi;
3775         else
3776                 vsi = pf->vmdq[pool - 1].vsi;
3777
3778         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3779         if (ret != I40E_SUCCESS) {
3780                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3781                 return -ENODEV;
3782         }
3783         return 0;
3784 }
3785
3786 /* Remove a MAC address, and update filters */
3787 static void
3788 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3789 {
3790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3791         struct i40e_vsi *vsi;
3792         struct rte_eth_dev_data *data = dev->data;
3793         struct ether_addr *macaddr;
3794         int ret;
3795         uint32_t i;
3796         uint64_t pool_sel;
3797
3798         macaddr = &(data->mac_addrs[index]);
3799
3800         pool_sel = dev->data->mac_pool_sel[index];
3801
3802         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3803                 if (pool_sel & (1ULL << i)) {
3804                         if (i == 0)
3805                                 vsi = pf->main_vsi;
3806                         else {
3807                                 /* No VMDQ pool enabled or configured */
3808                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3809                                         (i > pf->nb_cfg_vmdq_vsi)) {
3810                                         PMD_DRV_LOG(ERR,
3811                                                 "No VMDQ pool enabled/configured");
3812                                         return;
3813                                 }
3814                                 vsi = pf->vmdq[i - 1].vsi;
3815                         }
3816                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3817
3818                         if (ret) {
3819                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3820                                 return;
3821                         }
3822                 }
3823         }
3824 }
3825
3826 /* Set perfect match or hash match of MAC and VLAN for a VF */
3827 static int
3828 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3829                  struct rte_eth_mac_filter *filter,
3830                  bool add)
3831 {
3832         struct i40e_hw *hw;
3833         struct i40e_mac_filter_info mac_filter;
3834         struct ether_addr old_mac;
3835         struct ether_addr *new_mac;
3836         struct i40e_pf_vf *vf = NULL;
3837         uint16_t vf_id;
3838         int ret;
3839
3840         if (pf == NULL) {
3841                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3842                 return -EINVAL;
3843         }
3844         hw = I40E_PF_TO_HW(pf);
3845
3846         if (filter == NULL) {
3847                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3848                 return -EINVAL;
3849         }
3850
3851         new_mac = &filter->mac_addr;
3852
3853         if (is_zero_ether_addr(new_mac)) {
3854                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3855                 return -EINVAL;
3856         }
3857
3858         vf_id = filter->dst_id;
3859
3860         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3861                 PMD_DRV_LOG(ERR, "Invalid argument.");
3862                 return -EINVAL;
3863         }
3864         vf = &pf->vfs[vf_id];
3865
3866         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3867                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3868                 return -EINVAL;
3869         }
3870
3871         if (add) {
3872                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3873                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3874                                 ETHER_ADDR_LEN);
3875                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3876                                  ETHER_ADDR_LEN);
3877
3878                 mac_filter.filter_type = filter->filter_type;
3879                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3880                 if (ret != I40E_SUCCESS) {
3881                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3882                         return -1;
3883                 }
3884                 ether_addr_copy(new_mac, &pf->dev_addr);
3885         } else {
3886                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3887                                 ETHER_ADDR_LEN);
3888                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3889                 if (ret != I40E_SUCCESS) {
3890                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3891                         return -1;
3892                 }
3893
3894                 /* Clear device address as it has been removed */
3895                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3896                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3897         }
3898
3899         return 0;
3900 }
3901
3902 /* MAC filter handle */
3903 static int
3904 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3905                 void *arg)
3906 {
3907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3908         struct rte_eth_mac_filter *filter;
3909         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3910         int ret = I40E_NOT_SUPPORTED;
3911
3912         filter = (struct rte_eth_mac_filter *)(arg);
3913
3914         switch (filter_op) {
3915         case RTE_ETH_FILTER_NOP:
3916                 ret = I40E_SUCCESS;
3917                 break;
3918         case RTE_ETH_FILTER_ADD:
3919                 i40e_pf_disable_irq0(hw);
3920                 if (filter->is_vf)
3921                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3922                 i40e_pf_enable_irq0(hw);
3923                 break;
3924         case RTE_ETH_FILTER_DELETE:
3925                 i40e_pf_disable_irq0(hw);
3926                 if (filter->is_vf)
3927                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3928                 i40e_pf_enable_irq0(hw);
3929                 break;
3930         default:
3931                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3932                 ret = I40E_ERR_PARAM;
3933                 break;
3934         }
3935
3936         return ret;
3937 }
3938
3939 static int
3940 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3941 {
3942         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3943         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3944         int ret;
3945
3946         if (!lut)
3947                 return -EINVAL;
3948
3949         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3950                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3951                                           lut, lut_size);
3952                 if (ret) {
3953                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3954                         return ret;
3955                 }
3956         } else {
3957                 uint32_t *lut_dw = (uint32_t *)lut;
3958                 uint16_t i, lut_size_dw = lut_size / 4;
3959
3960                 for (i = 0; i < lut_size_dw; i++)
3961                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3962         }
3963
3964         return 0;
3965 }
3966
3967 static int
3968 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3969 {
3970         struct i40e_pf *pf;
3971         struct i40e_hw *hw;
3972         int ret;
3973
3974         if (!vsi || !lut)
3975                 return -EINVAL;
3976
3977         pf = I40E_VSI_TO_PF(vsi);
3978         hw = I40E_VSI_TO_HW(vsi);
3979
3980         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3981                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3982                                           lut, lut_size);
3983                 if (ret) {
3984                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3985                         return ret;
3986                 }
3987         } else {
3988                 uint32_t *lut_dw = (uint32_t *)lut;
3989                 uint16_t i, lut_size_dw = lut_size / 4;
3990
3991                 for (i = 0; i < lut_size_dw; i++)
3992                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3993                 I40E_WRITE_FLUSH(hw);
3994         }
3995
3996         return 0;
3997 }
3998
3999 static int
4000 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4001                          struct rte_eth_rss_reta_entry64 *reta_conf,
4002                          uint16_t reta_size)
4003 {
4004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4005         uint16_t i, lut_size = pf->hash_lut_size;
4006         uint16_t idx, shift;
4007         uint8_t *lut;
4008         int ret;
4009
4010         if (reta_size != lut_size ||
4011                 reta_size > ETH_RSS_RETA_SIZE_512) {
4012                 PMD_DRV_LOG(ERR,
4013                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4014                         reta_size, lut_size);
4015                 return -EINVAL;
4016         }
4017
4018         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4019         if (!lut) {
4020                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4021                 return -ENOMEM;
4022         }
4023         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4024         if (ret)
4025                 goto out;
4026         for (i = 0; i < reta_size; i++) {
4027                 idx = i / RTE_RETA_GROUP_SIZE;
4028                 shift = i % RTE_RETA_GROUP_SIZE;
4029                 if (reta_conf[idx].mask & (1ULL << shift))
4030                         lut[i] = reta_conf[idx].reta[shift];
4031         }
4032         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4033
4034 out:
4035         rte_free(lut);
4036
4037         return ret;
4038 }
4039
4040 static int
4041 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4042                         struct rte_eth_rss_reta_entry64 *reta_conf,
4043                         uint16_t reta_size)
4044 {
4045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4046         uint16_t i, lut_size = pf->hash_lut_size;
4047         uint16_t idx, shift;
4048         uint8_t *lut;
4049         int ret;
4050
4051         if (reta_size != lut_size ||
4052                 reta_size > ETH_RSS_RETA_SIZE_512) {
4053                 PMD_DRV_LOG(ERR,
4054                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4055                         reta_size, lut_size);
4056                 return -EINVAL;
4057         }
4058
4059         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4060         if (!lut) {
4061                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4062                 return -ENOMEM;
4063         }
4064
4065         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4066         if (ret)
4067                 goto out;
4068         for (i = 0; i < reta_size; i++) {
4069                 idx = i / RTE_RETA_GROUP_SIZE;
4070                 shift = i % RTE_RETA_GROUP_SIZE;
4071                 if (reta_conf[idx].mask & (1ULL << shift))
4072                         reta_conf[idx].reta[shift] = lut[i];
4073         }
4074
4075 out:
4076         rte_free(lut);
4077
4078         return ret;
4079 }
4080
4081 /**
4082  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4083  * @hw:   pointer to the HW structure
4084  * @mem:  pointer to mem struct to fill out
4085  * @size: size of memory requested
4086  * @alignment: what to align the allocation to
4087  **/
4088 enum i40e_status_code
4089 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4090                         struct i40e_dma_mem *mem,
4091                         u64 size,
4092                         u32 alignment)
4093 {
4094         const struct rte_memzone *mz = NULL;
4095         char z_name[RTE_MEMZONE_NAMESIZE];
4096
4097         if (!mem)
4098                 return I40E_ERR_PARAM;
4099
4100         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4101         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
4102                                          alignment, RTE_PGSIZE_2M);
4103         if (!mz)
4104                 return I40E_ERR_NO_MEMORY;
4105
4106         mem->size = size;
4107         mem->va = mz->addr;
4108         mem->pa = mz->iova;
4109         mem->zone = (const void *)mz;
4110         PMD_DRV_LOG(DEBUG,
4111                 "memzone %s allocated with physical address: %"PRIu64,
4112                 mz->name, mem->pa);
4113
4114         return I40E_SUCCESS;
4115 }
4116
4117 /**
4118  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4119  * @hw:   pointer to the HW structure
4120  * @mem:  ptr to mem struct to free
4121  **/
4122 enum i40e_status_code
4123 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4124                     struct i40e_dma_mem *mem)
4125 {
4126         if (!mem)
4127                 return I40E_ERR_PARAM;
4128
4129         PMD_DRV_LOG(DEBUG,
4130                 "memzone %s to be freed with physical address: %"PRIu64,
4131                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4132         rte_memzone_free((const struct rte_memzone *)mem->zone);
4133         mem->zone = NULL;
4134         mem->va = NULL;
4135         mem->pa = (u64)0;
4136
4137         return I40E_SUCCESS;
4138 }
4139
4140 /**
4141  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4142  * @hw:   pointer to the HW structure
4143  * @mem:  pointer to mem struct to fill out
4144  * @size: size of memory requested
4145  **/
4146 enum i40e_status_code
4147 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4148                          struct i40e_virt_mem *mem,
4149                          u32 size)
4150 {
4151         if (!mem)
4152                 return I40E_ERR_PARAM;
4153
4154         mem->size = size;
4155         mem->va = rte_zmalloc("i40e", size, 0);
4156
4157         if (mem->va)
4158                 return I40E_SUCCESS;
4159         else
4160                 return I40E_ERR_NO_MEMORY;
4161 }
4162
4163 /**
4164  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4165  * @hw:   pointer to the HW structure
4166  * @mem:  pointer to mem struct to free
4167  **/
4168 enum i40e_status_code
4169 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4170                      struct i40e_virt_mem *mem)
4171 {
4172         if (!mem)
4173                 return I40E_ERR_PARAM;
4174
4175         rte_free(mem->va);
4176         mem->va = NULL;
4177
4178         return I40E_SUCCESS;
4179 }
4180
4181 void
4182 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4183 {
4184         rte_spinlock_init(&sp->spinlock);
4185 }
4186
4187 void
4188 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4189 {
4190         rte_spinlock_lock(&sp->spinlock);
4191 }
4192
4193 void
4194 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4195 {
4196         rte_spinlock_unlock(&sp->spinlock);
4197 }
4198
4199 void
4200 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4201 {
4202         return;
4203 }
4204
4205 /**
4206  * Get the hardware capabilities, which will be parsed
4207  * and saved into struct i40e_hw.
4208  */
4209 static int
4210 i40e_get_cap(struct i40e_hw *hw)
4211 {
4212         struct i40e_aqc_list_capabilities_element_resp *buf;
4213         uint16_t len, size = 0;
4214         int ret;
4215
4216         /* Calculate a huge enough buff for saving response data temporarily */
4217         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4218                                                 I40E_MAX_CAP_ELE_NUM;
4219         buf = rte_zmalloc("i40e", len, 0);
4220         if (!buf) {
4221                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4222                 return I40E_ERR_NO_MEMORY;
4223         }
4224
4225         /* Get, parse the capabilities and save it to hw */
4226         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4227                         i40e_aqc_opc_list_func_capabilities, NULL);
4228         if (ret != I40E_SUCCESS)
4229                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4230
4231         /* Free the temporary buffer after being used */
4232         rte_free(buf);
4233
4234         return ret;
4235 }
4236
4237 static int
4238 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4239 {
4240         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4241         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4243         uint16_t qp_count = 0, vsi_count = 0;
4244
4245         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4246                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4247                 return -EINVAL;
4248         }
4249         /* Add the parameter init for LFC */
4250         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4251         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4252         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4253
4254         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4255         pf->max_num_vsi = hw->func_caps.num_vsis;
4256         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4257         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4258         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4259
4260         /* FDir queue/VSI allocation */
4261         pf->fdir_qp_offset = 0;
4262         if (hw->func_caps.fd) {
4263                 pf->flags |= I40E_FLAG_FDIR;
4264                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4265         } else {
4266                 pf->fdir_nb_qps = 0;
4267         }
4268         qp_count += pf->fdir_nb_qps;
4269         vsi_count += 1;
4270
4271         /* LAN queue/VSI allocation */
4272         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4273         if (!hw->func_caps.rss) {
4274                 pf->lan_nb_qps = 1;
4275         } else {
4276                 pf->flags |= I40E_FLAG_RSS;
4277                 if (hw->mac.type == I40E_MAC_X722)
4278                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4279                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4280         }
4281         qp_count += pf->lan_nb_qps;
4282         vsi_count += 1;
4283
4284         /* VF queue/VSI allocation */
4285         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4286         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4287                 pf->flags |= I40E_FLAG_SRIOV;
4288                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4289                 pf->vf_num = pci_dev->max_vfs;
4290                 PMD_DRV_LOG(DEBUG,
4291                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4292                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4293         } else {
4294                 pf->vf_nb_qps = 0;
4295                 pf->vf_num = 0;
4296         }
4297         qp_count += pf->vf_nb_qps * pf->vf_num;
4298         vsi_count += pf->vf_num;
4299
4300         /* VMDq queue/VSI allocation */
4301         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4302         pf->vmdq_nb_qps = 0;
4303         pf->max_nb_vmdq_vsi = 0;
4304         if (hw->func_caps.vmdq) {
4305                 if (qp_count < hw->func_caps.num_tx_qp &&
4306                         vsi_count < hw->func_caps.num_vsis) {
4307                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4308                                 qp_count) / pf->vmdq_nb_qp_max;
4309
4310                         /* Limit the maximum number of VMDq vsi to the maximum
4311                          * ethdev can support
4312                          */
4313                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4314                                 hw->func_caps.num_vsis - vsi_count);
4315                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4316                                 ETH_64_POOLS);
4317                         if (pf->max_nb_vmdq_vsi) {
4318                                 pf->flags |= I40E_FLAG_VMDQ;
4319                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4320                                 PMD_DRV_LOG(DEBUG,
4321                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4322                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4323                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4324                         } else {
4325                                 PMD_DRV_LOG(INFO,
4326                                         "No enough queues left for VMDq");
4327                         }
4328                 } else {
4329                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4330                 }
4331         }
4332         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4333         vsi_count += pf->max_nb_vmdq_vsi;
4334
4335         if (hw->func_caps.dcb)
4336                 pf->flags |= I40E_FLAG_DCB;
4337
4338         if (qp_count > hw->func_caps.num_tx_qp) {
4339                 PMD_DRV_LOG(ERR,
4340                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4341                         qp_count, hw->func_caps.num_tx_qp);
4342                 return -EINVAL;
4343         }
4344         if (vsi_count > hw->func_caps.num_vsis) {
4345                 PMD_DRV_LOG(ERR,
4346                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4347                         vsi_count, hw->func_caps.num_vsis);
4348                 return -EINVAL;
4349         }
4350
4351         return 0;
4352 }
4353
4354 static int
4355 i40e_pf_get_switch_config(struct i40e_pf *pf)
4356 {
4357         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4358         struct i40e_aqc_get_switch_config_resp *switch_config;
4359         struct i40e_aqc_switch_config_element_resp *element;
4360         uint16_t start_seid = 0, num_reported;
4361         int ret;
4362
4363         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4364                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4365         if (!switch_config) {
4366                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4367                 return -ENOMEM;
4368         }
4369
4370         /* Get the switch configurations */
4371         ret = i40e_aq_get_switch_config(hw, switch_config,
4372                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4373         if (ret != I40E_SUCCESS) {
4374                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4375                 goto fail;
4376         }
4377         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4378         if (num_reported != 1) { /* The number should be 1 */
4379                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4380                 goto fail;
4381         }
4382
4383         /* Parse the switch configuration elements */
4384         element = &(switch_config->element[0]);
4385         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4386                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4387                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4388         } else
4389                 PMD_DRV_LOG(INFO, "Unknown element type");
4390
4391 fail:
4392         rte_free(switch_config);
4393
4394         return ret;
4395 }
4396
4397 static int
4398 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4399                         uint32_t num)
4400 {
4401         struct pool_entry *entry;
4402
4403         if (pool == NULL || num == 0)
4404                 return -EINVAL;
4405
4406         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4407         if (entry == NULL) {
4408                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4409                 return -ENOMEM;
4410         }
4411
4412         /* queue heap initialize */
4413         pool->num_free = num;
4414         pool->num_alloc = 0;
4415         pool->base = base;
4416         LIST_INIT(&pool->alloc_list);
4417         LIST_INIT(&pool->free_list);
4418
4419         /* Initialize element  */
4420         entry->base = 0;
4421         entry->len = num;
4422
4423         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4424         return 0;
4425 }
4426
4427 static void
4428 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4429 {
4430         struct pool_entry *entry, *next_entry;
4431
4432         if (pool == NULL)
4433                 return;
4434
4435         for (entry = LIST_FIRST(&pool->alloc_list);
4436                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4437                         entry = next_entry) {
4438                 LIST_REMOVE(entry, next);
4439                 rte_free(entry);
4440         }
4441
4442         for (entry = LIST_FIRST(&pool->free_list);
4443                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4444                         entry = next_entry) {
4445                 LIST_REMOVE(entry, next);
4446                 rte_free(entry);
4447         }
4448
4449         pool->num_free = 0;
4450         pool->num_alloc = 0;
4451         pool->base = 0;
4452         LIST_INIT(&pool->alloc_list);
4453         LIST_INIT(&pool->free_list);
4454 }
4455
4456 static int
4457 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4458                        uint32_t base)
4459 {
4460         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4461         uint32_t pool_offset;
4462         int insert;
4463
4464         if (pool == NULL) {
4465                 PMD_DRV_LOG(ERR, "Invalid parameter");
4466                 return -EINVAL;
4467         }
4468
4469         pool_offset = base - pool->base;
4470         /* Lookup in alloc list */
4471         LIST_FOREACH(entry, &pool->alloc_list, next) {
4472                 if (entry->base == pool_offset) {
4473                         valid_entry = entry;
4474                         LIST_REMOVE(entry, next);
4475                         break;
4476                 }
4477         }
4478
4479         /* Not find, return */
4480         if (valid_entry == NULL) {
4481                 PMD_DRV_LOG(ERR, "Failed to find entry");
4482                 return -EINVAL;
4483         }
4484
4485         /**
4486          * Found it, move it to free list  and try to merge.
4487          * In order to make merge easier, always sort it by qbase.
4488          * Find adjacent prev and last entries.
4489          */
4490         prev = next = NULL;
4491         LIST_FOREACH(entry, &pool->free_list, next) {
4492                 if (entry->base > valid_entry->base) {
4493                         next = entry;
4494                         break;
4495                 }
4496                 prev = entry;
4497         }
4498
4499         insert = 0;
4500         /* Try to merge with next one*/
4501         if (next != NULL) {
4502                 /* Merge with next one */
4503                 if (valid_entry->base + valid_entry->len == next->base) {
4504                         next->base = valid_entry->base;
4505                         next->len += valid_entry->len;
4506                         rte_free(valid_entry);
4507                         valid_entry = next;
4508                         insert = 1;
4509                 }
4510         }
4511
4512         if (prev != NULL) {
4513                 /* Merge with previous one */
4514                 if (prev->base + prev->len == valid_entry->base) {
4515                         prev->len += valid_entry->len;
4516                         /* If it merge with next one, remove next node */
4517                         if (insert == 1) {
4518                                 LIST_REMOVE(valid_entry, next);
4519                                 rte_free(valid_entry);
4520                         } else {
4521                                 rte_free(valid_entry);
4522                                 insert = 1;
4523                         }
4524                 }
4525         }
4526
4527         /* Not find any entry to merge, insert */
4528         if (insert == 0) {
4529                 if (prev != NULL)
4530                         LIST_INSERT_AFTER(prev, valid_entry, next);
4531                 else if (next != NULL)
4532                         LIST_INSERT_BEFORE(next, valid_entry, next);
4533                 else /* It's empty list, insert to head */
4534                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4535         }
4536
4537         pool->num_free += valid_entry->len;
4538         pool->num_alloc -= valid_entry->len;
4539
4540         return 0;
4541 }
4542
4543 static int
4544 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4545                        uint16_t num)
4546 {
4547         struct pool_entry *entry, *valid_entry;
4548
4549         if (pool == NULL || num == 0) {
4550                 PMD_DRV_LOG(ERR, "Invalid parameter");
4551                 return -EINVAL;
4552         }
4553
4554         if (pool->num_free < num) {
4555                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4556                             num, pool->num_free);
4557                 return -ENOMEM;
4558         }
4559
4560         valid_entry = NULL;
4561         /* Lookup  in free list and find most fit one */
4562         LIST_FOREACH(entry, &pool->free_list, next) {
4563                 if (entry->len >= num) {
4564                         /* Find best one */
4565                         if (entry->len == num) {
4566                                 valid_entry = entry;
4567                                 break;
4568                         }
4569                         if (valid_entry == NULL || valid_entry->len > entry->len)
4570                                 valid_entry = entry;
4571                 }
4572         }
4573
4574         /* Not find one to satisfy the request, return */
4575         if (valid_entry == NULL) {
4576                 PMD_DRV_LOG(ERR, "No valid entry found");
4577                 return -ENOMEM;
4578         }
4579         /**
4580          * The entry have equal queue number as requested,
4581          * remove it from alloc_list.
4582          */
4583         if (valid_entry->len == num) {
4584                 LIST_REMOVE(valid_entry, next);
4585         } else {
4586                 /**
4587                  * The entry have more numbers than requested,
4588                  * create a new entry for alloc_list and minus its
4589                  * queue base and number in free_list.
4590                  */
4591                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4592                 if (entry == NULL) {
4593                         PMD_DRV_LOG(ERR,
4594                                 "Failed to allocate memory for resource pool");
4595                         return -ENOMEM;
4596                 }
4597                 entry->base = valid_entry->base;
4598                 entry->len = num;
4599                 valid_entry->base += num;
4600                 valid_entry->len -= num;
4601                 valid_entry = entry;
4602         }
4603
4604         /* Insert it into alloc list, not sorted */
4605         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4606
4607         pool->num_free -= valid_entry->len;
4608         pool->num_alloc += valid_entry->len;
4609
4610         return valid_entry->base + pool->base;
4611 }
4612
4613 /**
4614  * bitmap_is_subset - Check whether src2 is subset of src1
4615  **/
4616 static inline int
4617 bitmap_is_subset(uint8_t src1, uint8_t src2)
4618 {
4619         return !((src1 ^ src2) & src2);
4620 }
4621
4622 static enum i40e_status_code
4623 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4624 {
4625         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4626
4627         /* If DCB is not supported, only default TC is supported */
4628         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4629                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4630                 return I40E_NOT_SUPPORTED;
4631         }
4632
4633         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4634                 PMD_DRV_LOG(ERR,
4635                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4636                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4637                 return I40E_NOT_SUPPORTED;
4638         }
4639         return I40E_SUCCESS;
4640 }
4641
4642 int
4643 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4644                                 struct i40e_vsi_vlan_pvid_info *info)
4645 {
4646         struct i40e_hw *hw;
4647         struct i40e_vsi_context ctxt;
4648         uint8_t vlan_flags = 0;
4649         int ret;
4650
4651         if (vsi == NULL || info == NULL) {
4652                 PMD_DRV_LOG(ERR, "invalid parameters");
4653                 return I40E_ERR_PARAM;
4654         }
4655
4656         if (info->on) {
4657                 vsi->info.pvid = info->config.pvid;
4658                 /**
4659                  * If insert pvid is enabled, only tagged pkts are
4660                  * allowed to be sent out.
4661                  */
4662                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4663                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4664         } else {
4665                 vsi->info.pvid = 0;
4666                 if (info->config.reject.tagged == 0)
4667                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4668
4669                 if (info->config.reject.untagged == 0)
4670                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4671         }
4672         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4673                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4674         vsi->info.port_vlan_flags |= vlan_flags;
4675         vsi->info.valid_sections =
4676                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4677         memset(&ctxt, 0, sizeof(ctxt));
4678         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4679         ctxt.seid = vsi->seid;
4680
4681         hw = I40E_VSI_TO_HW(vsi);
4682         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4683         if (ret != I40E_SUCCESS)
4684                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4685
4686         return ret;
4687 }
4688
4689 static int
4690 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4691 {
4692         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4693         int i, ret;
4694         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4695
4696         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4697         if (ret != I40E_SUCCESS)
4698                 return ret;
4699
4700         if (!vsi->seid) {
4701                 PMD_DRV_LOG(ERR, "seid not valid");
4702                 return -EINVAL;
4703         }
4704
4705         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4706         tc_bw_data.tc_valid_bits = enabled_tcmap;
4707         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4708                 tc_bw_data.tc_bw_credits[i] =
4709                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4710
4711         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4712         if (ret != I40E_SUCCESS) {
4713                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4714                 return ret;
4715         }
4716
4717         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4718                                         sizeof(vsi->info.qs_handle));
4719         return I40E_SUCCESS;
4720 }
4721
4722 static enum i40e_status_code
4723 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4724                                  struct i40e_aqc_vsi_properties_data *info,
4725                                  uint8_t enabled_tcmap)
4726 {
4727         enum i40e_status_code ret;
4728         int i, total_tc = 0;
4729         uint16_t qpnum_per_tc, bsf, qp_idx;
4730
4731         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4732         if (ret != I40E_SUCCESS)
4733                 return ret;
4734
4735         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4736                 if (enabled_tcmap & (1 << i))
4737                         total_tc++;
4738         if (total_tc == 0)
4739                 total_tc = 1;
4740         vsi->enabled_tc = enabled_tcmap;
4741
4742         /* Number of queues per enabled TC */
4743         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4744         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4745         bsf = rte_bsf32(qpnum_per_tc);
4746
4747         /* Adjust the queue number to actual queues that can be applied */
4748         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4749                 vsi->nb_qps = qpnum_per_tc * total_tc;
4750
4751         /**
4752          * Configure TC and queue mapping parameters, for enabled TC,
4753          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4754          * default queue will serve it.
4755          */
4756         qp_idx = 0;
4757         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4758                 if (vsi->enabled_tc & (1 << i)) {
4759                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4760                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4761                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4762                         qp_idx += qpnum_per_tc;
4763                 } else
4764                         info->tc_mapping[i] = 0;
4765         }
4766
4767         /* Associate queue number with VSI */
4768         if (vsi->type == I40E_VSI_SRIOV) {
4769                 info->mapping_flags |=
4770                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4771                 for (i = 0; i < vsi->nb_qps; i++)
4772                         info->queue_mapping[i] =
4773                                 rte_cpu_to_le_16(vsi->base_queue + i);
4774         } else {
4775                 info->mapping_flags |=
4776                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4777                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4778         }
4779         info->valid_sections |=
4780                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4781
4782         return I40E_SUCCESS;
4783 }
4784
4785 static int
4786 i40e_veb_release(struct i40e_veb *veb)
4787 {
4788         struct i40e_vsi *vsi;
4789         struct i40e_hw *hw;
4790
4791         if (veb == NULL)
4792                 return -EINVAL;
4793
4794         if (!TAILQ_EMPTY(&veb->head)) {
4795                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4796                 return -EACCES;
4797         }
4798         /* associate_vsi field is NULL for floating VEB */
4799         if (veb->associate_vsi != NULL) {
4800                 vsi = veb->associate_vsi;
4801                 hw = I40E_VSI_TO_HW(vsi);
4802
4803                 vsi->uplink_seid = veb->uplink_seid;
4804                 vsi->veb = NULL;
4805         } else {
4806                 veb->associate_pf->main_vsi->floating_veb = NULL;
4807                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4808         }
4809
4810         i40e_aq_delete_element(hw, veb->seid, NULL);
4811         rte_free(veb);
4812         return I40E_SUCCESS;
4813 }
4814
4815 /* Setup a veb */
4816 static struct i40e_veb *
4817 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4818 {
4819         struct i40e_veb *veb;
4820         int ret;
4821         struct i40e_hw *hw;
4822
4823         if (pf == NULL) {
4824                 PMD_DRV_LOG(ERR,
4825                             "veb setup failed, associated PF shouldn't null");
4826                 return NULL;
4827         }
4828         hw = I40E_PF_TO_HW(pf);
4829
4830         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4831         if (!veb) {
4832                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4833                 goto fail;
4834         }
4835
4836         veb->associate_vsi = vsi;
4837         veb->associate_pf = pf;
4838         TAILQ_INIT(&veb->head);
4839         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4840
4841         /* create floating veb if vsi is NULL */
4842         if (vsi != NULL) {
4843                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4844                                       I40E_DEFAULT_TCMAP, false,
4845                                       &veb->seid, false, NULL);
4846         } else {
4847                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4848                                       true, &veb->seid, false, NULL);
4849         }
4850
4851         if (ret != I40E_SUCCESS) {
4852                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4853                             hw->aq.asq_last_status);
4854                 goto fail;
4855         }
4856         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4857
4858         /* get statistics index */
4859         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4860                                 &veb->stats_idx, NULL, NULL, NULL);
4861         if (ret != I40E_SUCCESS) {
4862                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4863                             hw->aq.asq_last_status);
4864                 goto fail;
4865         }
4866         /* Get VEB bandwidth, to be implemented */
4867         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4868         if (vsi)
4869                 vsi->uplink_seid = veb->seid;
4870
4871         return veb;
4872 fail:
4873         rte_free(veb);
4874         return NULL;
4875 }
4876
4877 int
4878 i40e_vsi_release(struct i40e_vsi *vsi)
4879 {
4880         struct i40e_pf *pf;
4881         struct i40e_hw *hw;
4882         struct i40e_vsi_list *vsi_list;
4883         void *temp;
4884         int ret;
4885         struct i40e_mac_filter *f;
4886         uint16_t user_param;
4887
4888         if (!vsi)
4889                 return I40E_SUCCESS;
4890
4891         if (!vsi->adapter)
4892                 return -EFAULT;
4893
4894         user_param = vsi->user_param;
4895
4896         pf = I40E_VSI_TO_PF(vsi);
4897         hw = I40E_VSI_TO_HW(vsi);
4898
4899         /* VSI has child to attach, release child first */
4900         if (vsi->veb) {
4901                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4902                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4903                                 return -1;
4904                 }
4905                 i40e_veb_release(vsi->veb);
4906         }
4907
4908         if (vsi->floating_veb) {
4909                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4910                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4911                                 return -1;
4912                 }
4913         }
4914
4915         /* Remove all macvlan filters of the VSI */
4916         i40e_vsi_remove_all_macvlan_filter(vsi);
4917         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4918                 rte_free(f);
4919
4920         if (vsi->type != I40E_VSI_MAIN &&
4921             ((vsi->type != I40E_VSI_SRIOV) ||
4922             !pf->floating_veb_list[user_param])) {
4923                 /* Remove vsi from parent's sibling list */
4924                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4925                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4926                         return I40E_ERR_PARAM;
4927                 }
4928                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4929                                 &vsi->sib_vsi_list, list);
4930
4931                 /* Remove all switch element of the VSI */
4932                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4933                 if (ret != I40E_SUCCESS)
4934                         PMD_DRV_LOG(ERR, "Failed to delete element");
4935         }
4936
4937         if ((vsi->type == I40E_VSI_SRIOV) &&
4938             pf->floating_veb_list[user_param]) {
4939                 /* Remove vsi from parent's sibling list */
4940                 if (vsi->parent_vsi == NULL ||
4941                     vsi->parent_vsi->floating_veb == NULL) {
4942                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4943                         return I40E_ERR_PARAM;
4944                 }
4945                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4946                              &vsi->sib_vsi_list, list);
4947
4948                 /* Remove all switch element of the VSI */
4949                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4950                 if (ret != I40E_SUCCESS)
4951                         PMD_DRV_LOG(ERR, "Failed to delete element");
4952         }
4953
4954         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4955
4956         if (vsi->type != I40E_VSI_SRIOV)
4957                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4958         rte_free(vsi);
4959
4960         return I40E_SUCCESS;
4961 }
4962
4963 static int
4964 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4965 {
4966         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4967         struct i40e_aqc_remove_macvlan_element_data def_filter;
4968         struct i40e_mac_filter_info filter;
4969         int ret;
4970
4971         if (vsi->type != I40E_VSI_MAIN)
4972                 return I40E_ERR_CONFIG;
4973         memset(&def_filter, 0, sizeof(def_filter));
4974         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4975                                         ETH_ADDR_LEN);
4976         def_filter.vlan_tag = 0;
4977         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4978                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4979         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4980         if (ret != I40E_SUCCESS) {
4981                 struct i40e_mac_filter *f;
4982                 struct ether_addr *mac;
4983
4984                 PMD_DRV_LOG(DEBUG,
4985                             "Cannot remove the default macvlan filter");
4986                 /* It needs to add the permanent mac into mac list */
4987                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4988                 if (f == NULL) {
4989                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4990                         return I40E_ERR_NO_MEMORY;
4991                 }
4992                 mac = &f->mac_info.mac_addr;
4993                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4994                                 ETH_ADDR_LEN);
4995                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4996                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4997                 vsi->mac_num++;
4998
4999                 return ret;
5000         }
5001         rte_memcpy(&filter.mac_addr,
5002                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5003         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5004         return i40e_vsi_add_mac(vsi, &filter);
5005 }
5006
5007 /*
5008  * i40e_vsi_get_bw_config - Query VSI BW Information
5009  * @vsi: the VSI to be queried
5010  *
5011  * Returns 0 on success, negative value on failure
5012  */
5013 static enum i40e_status_code
5014 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5015 {
5016         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5017         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5018         struct i40e_hw *hw = &vsi->adapter->hw;
5019         i40e_status ret;
5020         int i;
5021         uint32_t bw_max;
5022
5023         memset(&bw_config, 0, sizeof(bw_config));
5024         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5025         if (ret != I40E_SUCCESS) {
5026                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5027                             hw->aq.asq_last_status);
5028                 return ret;
5029         }
5030
5031         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5032         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5033                                         &ets_sla_config, NULL);
5034         if (ret != I40E_SUCCESS) {
5035                 PMD_DRV_LOG(ERR,
5036                         "VSI failed to get TC bandwdith configuration %u",
5037                         hw->aq.asq_last_status);
5038                 return ret;
5039         }
5040
5041         /* store and print out BW info */
5042         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5043         vsi->bw_info.bw_max = bw_config.max_bw;
5044         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5045         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5046         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5047                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5048                      I40E_16_BIT_WIDTH);
5049         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5050                 vsi->bw_info.bw_ets_share_credits[i] =
5051                                 ets_sla_config.share_credits[i];
5052                 vsi->bw_info.bw_ets_credits[i] =
5053                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5054                 /* 4 bits per TC, 4th bit is reserved */
5055                 vsi->bw_info.bw_ets_max[i] =
5056                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5057                                   RTE_LEN2MASK(3, uint8_t));
5058                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5059                             vsi->bw_info.bw_ets_share_credits[i]);
5060                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5061                             vsi->bw_info.bw_ets_credits[i]);
5062                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5063                             vsi->bw_info.bw_ets_max[i]);
5064         }
5065
5066         return I40E_SUCCESS;
5067 }
5068
5069 /* i40e_enable_pf_lb
5070  * @pf: pointer to the pf structure
5071  *
5072  * allow loopback on pf
5073  */
5074 static inline void
5075 i40e_enable_pf_lb(struct i40e_pf *pf)
5076 {
5077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5078         struct i40e_vsi_context ctxt;
5079         int ret;
5080
5081         /* Use the FW API if FW >= v5.0 */
5082         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5083                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5084                 return;
5085         }
5086
5087         memset(&ctxt, 0, sizeof(ctxt));
5088         ctxt.seid = pf->main_vsi_seid;
5089         ctxt.pf_num = hw->pf_id;
5090         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5091         if (ret) {
5092                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5093                             ret, hw->aq.asq_last_status);
5094                 return;
5095         }
5096         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5097         ctxt.info.valid_sections =
5098                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5099         ctxt.info.switch_id |=
5100                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5101
5102         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5103         if (ret)
5104                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5105                             hw->aq.asq_last_status);
5106 }
5107
5108 /* Setup a VSI */
5109 struct i40e_vsi *
5110 i40e_vsi_setup(struct i40e_pf *pf,
5111                enum i40e_vsi_type type,
5112                struct i40e_vsi *uplink_vsi,
5113                uint16_t user_param)
5114 {
5115         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5116         struct i40e_vsi *vsi;
5117         struct i40e_mac_filter_info filter;
5118         int ret;
5119         struct i40e_vsi_context ctxt;
5120         struct ether_addr broadcast =
5121                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5122
5123         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5124             uplink_vsi == NULL) {
5125                 PMD_DRV_LOG(ERR,
5126                         "VSI setup failed, VSI link shouldn't be NULL");
5127                 return NULL;
5128         }
5129
5130         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5131                 PMD_DRV_LOG(ERR,
5132                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5133                 return NULL;
5134         }
5135
5136         /* two situations
5137          * 1.type is not MAIN and uplink vsi is not NULL
5138          * If uplink vsi didn't setup VEB, create one first under veb field
5139          * 2.type is SRIOV and the uplink is NULL
5140          * If floating VEB is NULL, create one veb under floating veb field
5141          */
5142
5143         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5144             uplink_vsi->veb == NULL) {
5145                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5146
5147                 if (uplink_vsi->veb == NULL) {
5148                         PMD_DRV_LOG(ERR, "VEB setup failed");
5149                         return NULL;
5150                 }
5151                 /* set ALLOWLOOPBACk on pf, when veb is created */
5152                 i40e_enable_pf_lb(pf);
5153         }
5154
5155         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5156             pf->main_vsi->floating_veb == NULL) {
5157                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5158
5159                 if (pf->main_vsi->floating_veb == NULL) {
5160                         PMD_DRV_LOG(ERR, "VEB setup failed");
5161                         return NULL;
5162                 }
5163         }
5164
5165         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5166         if (!vsi) {
5167                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5168                 return NULL;
5169         }
5170         TAILQ_INIT(&vsi->mac_list);
5171         vsi->type = type;
5172         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5173         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5174         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5175         vsi->user_param = user_param;
5176         vsi->vlan_anti_spoof_on = 0;
5177         vsi->vlan_filter_on = 0;
5178         /* Allocate queues */
5179         switch (vsi->type) {
5180         case I40E_VSI_MAIN  :
5181                 vsi->nb_qps = pf->lan_nb_qps;
5182                 break;
5183         case I40E_VSI_SRIOV :
5184                 vsi->nb_qps = pf->vf_nb_qps;
5185                 break;
5186         case I40E_VSI_VMDQ2:
5187                 vsi->nb_qps = pf->vmdq_nb_qps;
5188                 break;
5189         case I40E_VSI_FDIR:
5190                 vsi->nb_qps = pf->fdir_nb_qps;
5191                 break;
5192         default:
5193                 goto fail_mem;
5194         }
5195         /*
5196          * The filter status descriptor is reported in rx queue 0,
5197          * while the tx queue for fdir filter programming has no
5198          * such constraints, can be non-zero queues.
5199          * To simplify it, choose FDIR vsi use queue 0 pair.
5200          * To make sure it will use queue 0 pair, queue allocation
5201          * need be done before this function is called
5202          */
5203         if (type != I40E_VSI_FDIR) {
5204                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5205                         if (ret < 0) {
5206                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5207                                                 vsi->seid, ret);
5208                                 goto fail_mem;
5209                         }
5210                         vsi->base_queue = ret;
5211         } else
5212                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5213
5214         /* VF has MSIX interrupt in VF range, don't allocate here */
5215         if (type == I40E_VSI_MAIN) {
5216                 if (pf->support_multi_driver) {
5217                         /* If support multi-driver, need to use INT0 instead of
5218                          * allocating from msix pool. The Msix pool is init from
5219                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5220                          * to 1 without calling i40e_res_pool_alloc.
5221                          */
5222                         vsi->msix_intr = 0;
5223                         vsi->nb_msix = 1;
5224                 } else {
5225                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5226                                                   RTE_MIN(vsi->nb_qps,
5227                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5228                         if (ret < 0) {
5229                                 PMD_DRV_LOG(ERR,
5230                                             "VSI MAIN %d get heap failed %d",
5231                                             vsi->seid, ret);
5232                                 goto fail_queue_alloc;
5233                         }
5234                         vsi->msix_intr = ret;
5235                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5236                                                RTE_MAX_RXTX_INTR_VEC_ID);
5237                 }
5238         } else if (type != I40E_VSI_SRIOV) {
5239                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5240                 if (ret < 0) {
5241                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5242                         goto fail_queue_alloc;
5243                 }
5244                 vsi->msix_intr = ret;
5245                 vsi->nb_msix = 1;
5246         } else {
5247                 vsi->msix_intr = 0;
5248                 vsi->nb_msix = 0;
5249         }
5250
5251         /* Add VSI */
5252         if (type == I40E_VSI_MAIN) {
5253                 /* For main VSI, no need to add since it's default one */
5254                 vsi->uplink_seid = pf->mac_seid;
5255                 vsi->seid = pf->main_vsi_seid;
5256                 /* Bind queues with specific MSIX interrupt */
5257                 /**
5258                  * Needs 2 interrupt at least, one for misc cause which will
5259                  * enabled from OS side, Another for queues binding the
5260                  * interrupt from device side only.
5261                  */
5262
5263                 /* Get default VSI parameters from hardware */
5264                 memset(&ctxt, 0, sizeof(ctxt));
5265                 ctxt.seid = vsi->seid;
5266                 ctxt.pf_num = hw->pf_id;
5267                 ctxt.uplink_seid = vsi->uplink_seid;
5268                 ctxt.vf_num = 0;
5269                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5270                 if (ret != I40E_SUCCESS) {
5271                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5272                         goto fail_msix_alloc;
5273                 }
5274                 rte_memcpy(&vsi->info, &ctxt.info,
5275                         sizeof(struct i40e_aqc_vsi_properties_data));
5276                 vsi->vsi_id = ctxt.vsi_number;
5277                 vsi->info.valid_sections = 0;
5278
5279                 /* Configure tc, enabled TC0 only */
5280                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5281                         I40E_SUCCESS) {
5282                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5283                         goto fail_msix_alloc;
5284                 }
5285
5286                 /* TC, queue mapping */
5287                 memset(&ctxt, 0, sizeof(ctxt));
5288                 vsi->info.valid_sections |=
5289                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5290                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5291                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5292                 rte_memcpy(&ctxt.info, &vsi->info,
5293                         sizeof(struct i40e_aqc_vsi_properties_data));
5294                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5295                                                 I40E_DEFAULT_TCMAP);
5296                 if (ret != I40E_SUCCESS) {
5297                         PMD_DRV_LOG(ERR,
5298                                 "Failed to configure TC queue mapping");
5299                         goto fail_msix_alloc;
5300                 }
5301                 ctxt.seid = vsi->seid;
5302                 ctxt.pf_num = hw->pf_id;
5303                 ctxt.uplink_seid = vsi->uplink_seid;
5304                 ctxt.vf_num = 0;
5305
5306                 /* Update VSI parameters */
5307                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5308                 if (ret != I40E_SUCCESS) {
5309                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5310                         goto fail_msix_alloc;
5311                 }
5312
5313                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5314                                                 sizeof(vsi->info.tc_mapping));
5315                 rte_memcpy(&vsi->info.queue_mapping,
5316                                 &ctxt.info.queue_mapping,
5317                         sizeof(vsi->info.queue_mapping));
5318                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5319                 vsi->info.valid_sections = 0;
5320
5321                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5322                                 ETH_ADDR_LEN);
5323
5324                 /**
5325                  * Updating default filter settings are necessary to prevent
5326                  * reception of tagged packets.
5327                  * Some old firmware configurations load a default macvlan
5328                  * filter which accepts both tagged and untagged packets.
5329                  * The updating is to use a normal filter instead if needed.
5330                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5331                  * The firmware with correct configurations load the default
5332                  * macvlan filter which is expected and cannot be removed.
5333                  */
5334                 i40e_update_default_filter_setting(vsi);
5335                 i40e_config_qinq(hw, vsi);
5336         } else if (type == I40E_VSI_SRIOV) {
5337                 memset(&ctxt, 0, sizeof(ctxt));
5338                 /**
5339                  * For other VSI, the uplink_seid equals to uplink VSI's
5340                  * uplink_seid since they share same VEB
5341                  */
5342                 if (uplink_vsi == NULL)
5343                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5344                 else
5345                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5346                 ctxt.pf_num = hw->pf_id;
5347                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5348                 ctxt.uplink_seid = vsi->uplink_seid;
5349                 ctxt.connection_type = 0x1;
5350                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5351
5352                 /* Use the VEB configuration if FW >= v5.0 */
5353                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5354                         /* Configure switch ID */
5355                         ctxt.info.valid_sections |=
5356                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5357                         ctxt.info.switch_id =
5358                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5359                 }
5360
5361                 /* Configure port/vlan */
5362                 ctxt.info.valid_sections |=
5363                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5364                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5365                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5366                                                 hw->func_caps.enabled_tcmap);
5367                 if (ret != I40E_SUCCESS) {
5368                         PMD_DRV_LOG(ERR,
5369                                 "Failed to configure TC queue mapping");
5370                         goto fail_msix_alloc;
5371                 }
5372
5373                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5374                 ctxt.info.valid_sections |=
5375                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5376                 /**
5377                  * Since VSI is not created yet, only configure parameter,
5378                  * will add vsi below.
5379                  */
5380
5381                 i40e_config_qinq(hw, vsi);
5382         } else if (type == I40E_VSI_VMDQ2) {
5383                 memset(&ctxt, 0, sizeof(ctxt));
5384                 /*
5385                  * For other VSI, the uplink_seid equals to uplink VSI's
5386                  * uplink_seid since they share same VEB
5387                  */
5388                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5389                 ctxt.pf_num = hw->pf_id;
5390                 ctxt.vf_num = 0;
5391                 ctxt.uplink_seid = vsi->uplink_seid;
5392                 ctxt.connection_type = 0x1;
5393                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5394
5395                 ctxt.info.valid_sections |=
5396                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5397                 /* user_param carries flag to enable loop back */
5398                 if (user_param) {
5399                         ctxt.info.switch_id =
5400                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5401                         ctxt.info.switch_id |=
5402                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5403                 }
5404
5405                 /* Configure port/vlan */
5406                 ctxt.info.valid_sections |=
5407                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5408                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5409                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5410                                                 I40E_DEFAULT_TCMAP);
5411                 if (ret != I40E_SUCCESS) {
5412                         PMD_DRV_LOG(ERR,
5413                                 "Failed to configure TC queue mapping");
5414                         goto fail_msix_alloc;
5415                 }
5416                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5417                 ctxt.info.valid_sections |=
5418                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5419         } else if (type == I40E_VSI_FDIR) {
5420                 memset(&ctxt, 0, sizeof(ctxt));
5421                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5422                 ctxt.pf_num = hw->pf_id;
5423                 ctxt.vf_num = 0;
5424                 ctxt.uplink_seid = vsi->uplink_seid;
5425                 ctxt.connection_type = 0x1;     /* regular data port */
5426                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5427                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5428                                                 I40E_DEFAULT_TCMAP);
5429                 if (ret != I40E_SUCCESS) {
5430                         PMD_DRV_LOG(ERR,
5431                                 "Failed to configure TC queue mapping.");
5432                         goto fail_msix_alloc;
5433                 }
5434                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5435                 ctxt.info.valid_sections |=
5436                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5437         } else {
5438                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5439                 goto fail_msix_alloc;
5440         }
5441
5442         if (vsi->type != I40E_VSI_MAIN) {
5443                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5444                 if (ret != I40E_SUCCESS) {
5445                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5446                                     hw->aq.asq_last_status);
5447                         goto fail_msix_alloc;
5448                 }
5449                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5450                 vsi->info.valid_sections = 0;
5451                 vsi->seid = ctxt.seid;
5452                 vsi->vsi_id = ctxt.vsi_number;
5453                 vsi->sib_vsi_list.vsi = vsi;
5454                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5455                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5456                                           &vsi->sib_vsi_list, list);
5457                 } else {
5458                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5459                                           &vsi->sib_vsi_list, list);
5460                 }
5461         }
5462
5463         /* MAC/VLAN configuration */
5464         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5465         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5466
5467         ret = i40e_vsi_add_mac(vsi, &filter);
5468         if (ret != I40E_SUCCESS) {
5469                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5470                 goto fail_msix_alloc;
5471         }
5472
5473         /* Get VSI BW information */
5474         i40e_vsi_get_bw_config(vsi);
5475         return vsi;
5476 fail_msix_alloc:
5477         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5478 fail_queue_alloc:
5479         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5480 fail_mem:
5481         rte_free(vsi);
5482         return NULL;
5483 }
5484
5485 /* Configure vlan filter on or off */
5486 int
5487 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5488 {
5489         int i, num;
5490         struct i40e_mac_filter *f;
5491         void *temp;
5492         struct i40e_mac_filter_info *mac_filter;
5493         enum rte_mac_filter_type desired_filter;
5494         int ret = I40E_SUCCESS;
5495
5496         if (on) {
5497                 /* Filter to match MAC and VLAN */
5498                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5499         } else {
5500                 /* Filter to match only MAC */
5501                 desired_filter = RTE_MAC_PERFECT_MATCH;
5502         }
5503
5504         num = vsi->mac_num;
5505
5506         mac_filter = rte_zmalloc("mac_filter_info_data",
5507                                  num * sizeof(*mac_filter), 0);
5508         if (mac_filter == NULL) {
5509                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5510                 return I40E_ERR_NO_MEMORY;
5511         }
5512
5513         i = 0;
5514
5515         /* Remove all existing mac */
5516         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5517                 mac_filter[i] = f->mac_info;
5518                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5519                 if (ret) {
5520                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5521                                     on ? "enable" : "disable");
5522                         goto DONE;
5523                 }
5524                 i++;
5525         }
5526
5527         /* Override with new filter */
5528         for (i = 0; i < num; i++) {
5529                 mac_filter[i].filter_type = desired_filter;
5530                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5531                 if (ret) {
5532                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5533                                     on ? "enable" : "disable");
5534                         goto DONE;
5535                 }
5536         }
5537
5538 DONE:
5539         rte_free(mac_filter);
5540         return ret;
5541 }
5542
5543 /* Configure vlan stripping on or off */
5544 int
5545 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5546 {
5547         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5548         struct i40e_vsi_context ctxt;
5549         uint8_t vlan_flags;
5550         int ret = I40E_SUCCESS;
5551
5552         /* Check if it has been already on or off */
5553         if (vsi->info.valid_sections &
5554                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5555                 if (on) {
5556                         if ((vsi->info.port_vlan_flags &
5557                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5558                                 return 0; /* already on */
5559                 } else {
5560                         if ((vsi->info.port_vlan_flags &
5561                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5562                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5563                                 return 0; /* already off */
5564                 }
5565         }
5566
5567         if (on)
5568                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5569         else
5570                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5571         vsi->info.valid_sections =
5572                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5573         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5574         vsi->info.port_vlan_flags |= vlan_flags;
5575         ctxt.seid = vsi->seid;
5576         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5577         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5578         if (ret)
5579                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5580                             on ? "enable" : "disable");
5581
5582         return ret;
5583 }
5584
5585 static int
5586 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5587 {
5588         struct rte_eth_dev_data *data = dev->data;
5589         int ret;
5590         int mask = 0;
5591
5592         /* Apply vlan offload setting */
5593         mask = ETH_VLAN_STRIP_MASK |
5594                ETH_VLAN_FILTER_MASK |
5595                ETH_VLAN_EXTEND_MASK;
5596         ret = i40e_vlan_offload_set(dev, mask);
5597         if (ret) {
5598                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5599                 return ret;
5600         }
5601
5602         /* Apply pvid setting */
5603         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5604                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5605         if (ret)
5606                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5607
5608         return ret;
5609 }
5610
5611 static int
5612 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5613 {
5614         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5615
5616         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5617 }
5618
5619 static int
5620 i40e_update_flow_control(struct i40e_hw *hw)
5621 {
5622 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5623         struct i40e_link_status link_status;
5624         uint32_t rxfc = 0, txfc = 0, reg;
5625         uint8_t an_info;
5626         int ret;
5627
5628         memset(&link_status, 0, sizeof(link_status));
5629         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5630         if (ret != I40E_SUCCESS) {
5631                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5632                 goto write_reg; /* Disable flow control */
5633         }
5634
5635         an_info = hw->phy.link_info.an_info;
5636         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5637                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5638                 ret = I40E_ERR_NOT_READY;
5639                 goto write_reg; /* Disable flow control */
5640         }
5641         /**
5642          * If link auto negotiation is enabled, flow control needs to
5643          * be configured according to it
5644          */
5645         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5646         case I40E_LINK_PAUSE_RXTX:
5647                 rxfc = 1;
5648                 txfc = 1;
5649                 hw->fc.current_mode = I40E_FC_FULL;
5650                 break;
5651         case I40E_AQ_LINK_PAUSE_RX:
5652                 rxfc = 1;
5653                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5654                 break;
5655         case I40E_AQ_LINK_PAUSE_TX:
5656                 txfc = 1;
5657                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5658                 break;
5659         default:
5660                 hw->fc.current_mode = I40E_FC_NONE;
5661                 break;
5662         }
5663
5664 write_reg:
5665         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5666                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5667         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5668         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5669         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5670         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5671
5672         return ret;
5673 }
5674
5675 /* PF setup */
5676 static int
5677 i40e_pf_setup(struct i40e_pf *pf)
5678 {
5679         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5680         struct i40e_filter_control_settings settings;
5681         struct i40e_vsi *vsi;
5682         int ret;
5683
5684         /* Clear all stats counters */
5685         pf->offset_loaded = FALSE;
5686         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5687         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5688         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5689         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5690
5691         ret = i40e_pf_get_switch_config(pf);
5692         if (ret != I40E_SUCCESS) {
5693                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5694                 return ret;
5695         }
5696         if (pf->flags & I40E_FLAG_FDIR) {
5697                 /* make queue allocated first, let FDIR use queue pair 0*/
5698                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5699                 if (ret != I40E_FDIR_QUEUE_ID) {
5700                         PMD_DRV_LOG(ERR,
5701                                 "queue allocation fails for FDIR: ret =%d",
5702                                 ret);
5703                         pf->flags &= ~I40E_FLAG_FDIR;
5704                 }
5705         }
5706         /*  main VSI setup */
5707         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5708         if (!vsi) {
5709                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5710                 return I40E_ERR_NOT_READY;
5711         }
5712         pf->main_vsi = vsi;
5713
5714         /* Configure filter control */
5715         memset(&settings, 0, sizeof(settings));
5716         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5717                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5718         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5719                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5720         else {
5721                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5722                         hw->func_caps.rss_table_size);
5723                 return I40E_ERR_PARAM;
5724         }
5725         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5726                 hw->func_caps.rss_table_size);
5727         pf->hash_lut_size = hw->func_caps.rss_table_size;
5728
5729         /* Enable ethtype and macvlan filters */
5730         settings.enable_ethtype = TRUE;
5731         settings.enable_macvlan = TRUE;
5732         ret = i40e_set_filter_control(hw, &settings);
5733         if (ret)
5734                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5735                                                                 ret);
5736
5737         /* Update flow control according to the auto negotiation */
5738         i40e_update_flow_control(hw);
5739
5740         return I40E_SUCCESS;
5741 }
5742
5743 int
5744 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5745 {
5746         uint32_t reg;
5747         uint16_t j;
5748
5749         /**
5750          * Set or clear TX Queue Disable flags,
5751          * which is required by hardware.
5752          */
5753         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5754         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5755
5756         /* Wait until the request is finished */
5757         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5758                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5759                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5760                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5761                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5762                                                         & 0x1))) {
5763                         break;
5764                 }
5765         }
5766         if (on) {
5767                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5768                         return I40E_SUCCESS; /* already on, skip next steps */
5769
5770                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5771                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5772         } else {
5773                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5774                         return I40E_SUCCESS; /* already off, skip next steps */
5775                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5776         }
5777         /* Write the register */
5778         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5779         /* Check the result */
5780         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5781                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5782                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5783                 if (on) {
5784                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5785                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5786                                 break;
5787                 } else {
5788                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5789                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5790                                 break;
5791                 }
5792         }
5793         /* Check if it is timeout */
5794         if (j >= I40E_CHK_Q_ENA_COUNT) {
5795                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5796                             (on ? "enable" : "disable"), q_idx);
5797                 return I40E_ERR_TIMEOUT;
5798         }
5799
5800         return I40E_SUCCESS;
5801 }
5802
5803 /* Swith on or off the tx queues */
5804 static int
5805 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5806 {
5807         struct rte_eth_dev_data *dev_data = pf->dev_data;
5808         struct i40e_tx_queue *txq;
5809         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5810         uint16_t i;
5811         int ret;
5812
5813         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5814                 txq = dev_data->tx_queues[i];
5815                 /* Don't operate the queue if not configured or
5816                  * if starting only per queue */
5817                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5818                         continue;
5819                 if (on)
5820                         ret = i40e_dev_tx_queue_start(dev, i);
5821                 else
5822                         ret = i40e_dev_tx_queue_stop(dev, i);
5823                 if ( ret != I40E_SUCCESS)
5824                         return ret;
5825         }
5826
5827         return I40E_SUCCESS;
5828 }
5829
5830 int
5831 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5832 {
5833         uint32_t reg;
5834         uint16_t j;
5835
5836         /* Wait until the request is finished */
5837         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5838                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5839                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5840                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5841                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5842                         break;
5843         }
5844
5845         if (on) {
5846                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5847                         return I40E_SUCCESS; /* Already on, skip next steps */
5848                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5849         } else {
5850                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5851                         return I40E_SUCCESS; /* Already off, skip next steps */
5852                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5853         }
5854
5855         /* Write the register */
5856         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5857         /* Check the result */
5858         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5859                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5860                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5861                 if (on) {
5862                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5863                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5864                                 break;
5865                 } else {
5866                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5867                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5868                                 break;
5869                 }
5870         }
5871
5872         /* Check if it is timeout */
5873         if (j >= I40E_CHK_Q_ENA_COUNT) {
5874                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5875                             (on ? "enable" : "disable"), q_idx);
5876                 return I40E_ERR_TIMEOUT;
5877         }
5878
5879         return I40E_SUCCESS;
5880 }
5881 /* Switch on or off the rx queues */
5882 static int
5883 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5884 {
5885         struct rte_eth_dev_data *dev_data = pf->dev_data;
5886         struct i40e_rx_queue *rxq;
5887         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5888         uint16_t i;
5889         int ret;
5890
5891         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5892                 rxq = dev_data->rx_queues[i];
5893                 /* Don't operate the queue if not configured or
5894                  * if starting only per queue */
5895                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5896                         continue;
5897                 if (on)
5898                         ret = i40e_dev_rx_queue_start(dev, i);
5899                 else
5900                         ret = i40e_dev_rx_queue_stop(dev, i);
5901                 if (ret != I40E_SUCCESS)
5902                         return ret;
5903         }
5904
5905         return I40E_SUCCESS;
5906 }
5907
5908 /* Switch on or off all the rx/tx queues */
5909 int
5910 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5911 {
5912         int ret;
5913
5914         if (on) {
5915                 /* enable rx queues before enabling tx queues */
5916                 ret = i40e_dev_switch_rx_queues(pf, on);
5917                 if (ret) {
5918                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5919                         return ret;
5920                 }
5921                 ret = i40e_dev_switch_tx_queues(pf, on);
5922         } else {
5923                 /* Stop tx queues before stopping rx queues */
5924                 ret = i40e_dev_switch_tx_queues(pf, on);
5925                 if (ret) {
5926                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5927                         return ret;
5928                 }
5929                 ret = i40e_dev_switch_rx_queues(pf, on);
5930         }
5931
5932         return ret;
5933 }
5934
5935 /* Initialize VSI for TX */
5936 static int
5937 i40e_dev_tx_init(struct i40e_pf *pf)
5938 {
5939         struct rte_eth_dev_data *data = pf->dev_data;
5940         uint16_t i;
5941         uint32_t ret = I40E_SUCCESS;
5942         struct i40e_tx_queue *txq;
5943
5944         for (i = 0; i < data->nb_tx_queues; i++) {
5945                 txq = data->tx_queues[i];
5946                 if (!txq || !txq->q_set)
5947                         continue;
5948                 ret = i40e_tx_queue_init(txq);
5949                 if (ret != I40E_SUCCESS)
5950                         break;
5951         }
5952         if (ret == I40E_SUCCESS)
5953                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5954                                      ->eth_dev);
5955
5956         return ret;
5957 }
5958
5959 /* Initialize VSI for RX */
5960 static int
5961 i40e_dev_rx_init(struct i40e_pf *pf)
5962 {
5963         struct rte_eth_dev_data *data = pf->dev_data;
5964         int ret = I40E_SUCCESS;
5965         uint16_t i;
5966         struct i40e_rx_queue *rxq;
5967
5968         i40e_pf_config_mq_rx(pf);
5969         for (i = 0; i < data->nb_rx_queues; i++) {
5970                 rxq = data->rx_queues[i];
5971                 if (!rxq || !rxq->q_set)
5972                         continue;
5973
5974                 ret = i40e_rx_queue_init(rxq);
5975                 if (ret != I40E_SUCCESS) {
5976                         PMD_DRV_LOG(ERR,
5977                                 "Failed to do RX queue initialization");
5978                         break;
5979                 }
5980         }
5981         if (ret == I40E_SUCCESS)
5982                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5983                                      ->eth_dev);
5984
5985         return ret;
5986 }
5987
5988 static int
5989 i40e_dev_rxtx_init(struct i40e_pf *pf)
5990 {
5991         int err;
5992
5993         err = i40e_dev_tx_init(pf);
5994         if (err) {
5995                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5996                 return err;
5997         }
5998         err = i40e_dev_rx_init(pf);
5999         if (err) {
6000                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6001                 return err;
6002         }
6003
6004         return err;
6005 }
6006
6007 static int
6008 i40e_vmdq_setup(struct rte_eth_dev *dev)
6009 {
6010         struct rte_eth_conf *conf = &dev->data->dev_conf;
6011         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6012         int i, err, conf_vsis, j, loop;
6013         struct i40e_vsi *vsi;
6014         struct i40e_vmdq_info *vmdq_info;
6015         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6016         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6017
6018         /*
6019          * Disable interrupt to avoid message from VF. Furthermore, it will
6020          * avoid race condition in VSI creation/destroy.
6021          */
6022         i40e_pf_disable_irq0(hw);
6023
6024         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6025                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6026                 return -ENOTSUP;
6027         }
6028
6029         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6030         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6031                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6032                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6033                         pf->max_nb_vmdq_vsi);
6034                 return -ENOTSUP;
6035         }
6036
6037         if (pf->vmdq != NULL) {
6038                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6039                 return 0;
6040         }
6041
6042         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6043                                 sizeof(*vmdq_info) * conf_vsis, 0);
6044
6045         if (pf->vmdq == NULL) {
6046                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6047                 return -ENOMEM;
6048         }
6049
6050         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6051
6052         /* Create VMDQ VSI */
6053         for (i = 0; i < conf_vsis; i++) {
6054                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6055                                 vmdq_conf->enable_loop_back);
6056                 if (vsi == NULL) {
6057                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6058                         err = -1;
6059                         goto err_vsi_setup;
6060                 }
6061                 vmdq_info = &pf->vmdq[i];
6062                 vmdq_info->pf = pf;
6063                 vmdq_info->vsi = vsi;
6064         }
6065         pf->nb_cfg_vmdq_vsi = conf_vsis;
6066
6067         /* Configure Vlan */
6068         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6069         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6070                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6071                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6072                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6073                                         vmdq_conf->pool_map[i].vlan_id, j);
6074
6075                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6076                                                 vmdq_conf->pool_map[i].vlan_id);
6077                                 if (err) {
6078                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6079                                         err = -1;
6080                                         goto err_vsi_setup;
6081                                 }
6082                         }
6083                 }
6084         }
6085
6086         i40e_pf_enable_irq0(hw);
6087
6088         return 0;
6089
6090 err_vsi_setup:
6091         for (i = 0; i < conf_vsis; i++)
6092                 if (pf->vmdq[i].vsi == NULL)
6093                         break;
6094                 else
6095                         i40e_vsi_release(pf->vmdq[i].vsi);
6096
6097         rte_free(pf->vmdq);
6098         pf->vmdq = NULL;
6099         i40e_pf_enable_irq0(hw);
6100         return err;
6101 }
6102
6103 static void
6104 i40e_stat_update_32(struct i40e_hw *hw,
6105                    uint32_t reg,
6106                    bool offset_loaded,
6107                    uint64_t *offset,
6108                    uint64_t *stat)
6109 {
6110         uint64_t new_data;
6111
6112         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6113         if (!offset_loaded)
6114                 *offset = new_data;
6115
6116         if (new_data >= *offset)
6117                 *stat = (uint64_t)(new_data - *offset);
6118         else
6119                 *stat = (uint64_t)((new_data +
6120                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6121 }
6122
6123 static void
6124 i40e_stat_update_48(struct i40e_hw *hw,
6125                    uint32_t hireg,
6126                    uint32_t loreg,
6127                    bool offset_loaded,
6128                    uint64_t *offset,
6129                    uint64_t *stat)
6130 {
6131         uint64_t new_data;
6132
6133         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6134         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6135                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6136
6137         if (!offset_loaded)
6138                 *offset = new_data;
6139
6140         if (new_data >= *offset)
6141                 *stat = new_data - *offset;
6142         else
6143                 *stat = (uint64_t)((new_data +
6144                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6145
6146         *stat &= I40E_48_BIT_MASK;
6147 }
6148
6149 /* Disable IRQ0 */
6150 void
6151 i40e_pf_disable_irq0(struct i40e_hw *hw)
6152 {
6153         /* Disable all interrupt types */
6154         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6155                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6156         I40E_WRITE_FLUSH(hw);
6157 }
6158
6159 /* Enable IRQ0 */
6160 void
6161 i40e_pf_enable_irq0(struct i40e_hw *hw)
6162 {
6163         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6164                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6165                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6166                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6167         I40E_WRITE_FLUSH(hw);
6168 }
6169
6170 static void
6171 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6172 {
6173         /* read pending request and disable first */
6174         i40e_pf_disable_irq0(hw);
6175         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6176         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6177                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6178
6179         if (no_queue)
6180                 /* Link no queues with irq0 */
6181                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6182                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6183 }
6184
6185 static void
6186 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6187 {
6188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6189         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6190         int i;
6191         uint16_t abs_vf_id;
6192         uint32_t index, offset, val;
6193
6194         if (!pf->vfs)
6195                 return;
6196         /**
6197          * Try to find which VF trigger a reset, use absolute VF id to access
6198          * since the reg is global register.
6199          */
6200         for (i = 0; i < pf->vf_num; i++) {
6201                 abs_vf_id = hw->func_caps.vf_base_id + i;
6202                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6203                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6204                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6205                 /* VFR event occurred */
6206                 if (val & (0x1 << offset)) {
6207                         int ret;
6208
6209                         /* Clear the event first */
6210                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6211                                                         (0x1 << offset));
6212                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6213                         /**
6214                          * Only notify a VF reset event occurred,
6215                          * don't trigger another SW reset
6216                          */
6217                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6218                         if (ret != I40E_SUCCESS)
6219                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6220                 }
6221         }
6222 }
6223
6224 static void
6225 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6226 {
6227         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6228         int i;
6229
6230         for (i = 0; i < pf->vf_num; i++)
6231                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6232 }
6233
6234 static void
6235 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6236 {
6237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6238         struct i40e_arq_event_info info;
6239         uint16_t pending, opcode;
6240         int ret;
6241
6242         info.buf_len = I40E_AQ_BUF_SZ;
6243         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6244         if (!info.msg_buf) {
6245                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6246                 return;
6247         }
6248
6249         pending = 1;
6250         while (pending) {
6251                 ret = i40e_clean_arq_element(hw, &info, &pending);
6252
6253                 if (ret != I40E_SUCCESS) {
6254                         PMD_DRV_LOG(INFO,
6255                                 "Failed to read msg from AdminQ, aq_err: %u",
6256                                 hw->aq.asq_last_status);
6257                         break;
6258                 }
6259                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6260
6261                 switch (opcode) {
6262                 case i40e_aqc_opc_send_msg_to_pf:
6263                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6264                         i40e_pf_host_handle_vf_msg(dev,
6265                                         rte_le_to_cpu_16(info.desc.retval),
6266                                         rte_le_to_cpu_32(info.desc.cookie_high),
6267                                         rte_le_to_cpu_32(info.desc.cookie_low),
6268                                         info.msg_buf,
6269                                         info.msg_len);
6270                         break;
6271                 case i40e_aqc_opc_get_link_status:
6272                         ret = i40e_dev_link_update(dev, 0);
6273                         if (!ret)
6274                                 _rte_eth_dev_callback_process(dev,
6275                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
6276                         break;
6277                 default:
6278                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6279                                     opcode);
6280                         break;
6281                 }
6282         }
6283         rte_free(info.msg_buf);
6284 }
6285
6286 /**
6287  * Interrupt handler triggered by NIC  for handling
6288  * specific interrupt.
6289  *
6290  * @param handle
6291  *  Pointer to interrupt handle.
6292  * @param param
6293  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6294  *
6295  * @return
6296  *  void
6297  */
6298 static void
6299 i40e_dev_interrupt_handler(void *param)
6300 {
6301         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6302         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6303         uint32_t icr0;
6304
6305         /* Disable interrupt */
6306         i40e_pf_disable_irq0(hw);
6307
6308         /* read out interrupt causes */
6309         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6310
6311         /* No interrupt event indicated */
6312         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6313                 PMD_DRV_LOG(INFO, "No interrupt event");
6314                 goto done;
6315         }
6316         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6317                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6318         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6319                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6320         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6321                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6322         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6323                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6324         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6325                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6326         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6327                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6328         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6329                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6330
6331         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6332                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6333                 i40e_dev_handle_vfr_event(dev);
6334         }
6335         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6336                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6337                 i40e_dev_handle_aq_msg(dev);
6338         }
6339
6340 done:
6341         /* Enable interrupt */
6342         i40e_pf_enable_irq0(hw);
6343         rte_intr_enable(dev->intr_handle);
6344 }
6345
6346 int
6347 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6348                          struct i40e_macvlan_filter *filter,
6349                          int total)
6350 {
6351         int ele_num, ele_buff_size;
6352         int num, actual_num, i;
6353         uint16_t flags;
6354         int ret = I40E_SUCCESS;
6355         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6356         struct i40e_aqc_add_macvlan_element_data *req_list;
6357
6358         if (filter == NULL  || total == 0)
6359                 return I40E_ERR_PARAM;
6360         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6361         ele_buff_size = hw->aq.asq_buf_size;
6362
6363         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6364         if (req_list == NULL) {
6365                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6366                 return I40E_ERR_NO_MEMORY;
6367         }
6368
6369         num = 0;
6370         do {
6371                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6372                 memset(req_list, 0, ele_buff_size);
6373
6374                 for (i = 0; i < actual_num; i++) {
6375                         rte_memcpy(req_list[i].mac_addr,
6376                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6377                         req_list[i].vlan_tag =
6378                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6379
6380                         switch (filter[num + i].filter_type) {
6381                         case RTE_MAC_PERFECT_MATCH:
6382                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6383                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6384                                 break;
6385                         case RTE_MACVLAN_PERFECT_MATCH:
6386                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6387                                 break;
6388                         case RTE_MAC_HASH_MATCH:
6389                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6390                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6391                                 break;
6392                         case RTE_MACVLAN_HASH_MATCH:
6393                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6394                                 break;
6395                         default:
6396                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6397                                 ret = I40E_ERR_PARAM;
6398                                 goto DONE;
6399                         }
6400
6401                         req_list[i].queue_number = 0;
6402
6403                         req_list[i].flags = rte_cpu_to_le_16(flags);
6404                 }
6405
6406                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6407                                                 actual_num, NULL);
6408                 if (ret != I40E_SUCCESS) {
6409                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6410                         goto DONE;
6411                 }
6412                 num += actual_num;
6413         } while (num < total);
6414
6415 DONE:
6416         rte_free(req_list);
6417         return ret;
6418 }
6419
6420 int
6421 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6422                             struct i40e_macvlan_filter *filter,
6423                             int total)
6424 {
6425         int ele_num, ele_buff_size;
6426         int num, actual_num, i;
6427         uint16_t flags;
6428         int ret = I40E_SUCCESS;
6429         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6430         struct i40e_aqc_remove_macvlan_element_data *req_list;
6431
6432         if (filter == NULL  || total == 0)
6433                 return I40E_ERR_PARAM;
6434
6435         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6436         ele_buff_size = hw->aq.asq_buf_size;
6437
6438         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6439         if (req_list == NULL) {
6440                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6441                 return I40E_ERR_NO_MEMORY;
6442         }
6443
6444         num = 0;
6445         do {
6446                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6447                 memset(req_list, 0, ele_buff_size);
6448
6449                 for (i = 0; i < actual_num; i++) {
6450                         rte_memcpy(req_list[i].mac_addr,
6451                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6452                         req_list[i].vlan_tag =
6453                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6454
6455                         switch (filter[num + i].filter_type) {
6456                         case RTE_MAC_PERFECT_MATCH:
6457                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6458                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6459                                 break;
6460                         case RTE_MACVLAN_PERFECT_MATCH:
6461                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6462                                 break;
6463                         case RTE_MAC_HASH_MATCH:
6464                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6465                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6466                                 break;
6467                         case RTE_MACVLAN_HASH_MATCH:
6468                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6469                                 break;
6470                         default:
6471                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6472                                 ret = I40E_ERR_PARAM;
6473                                 goto DONE;
6474                         }
6475                         req_list[i].flags = rte_cpu_to_le_16(flags);
6476                 }
6477
6478                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6479                                                 actual_num, NULL);
6480                 if (ret != I40E_SUCCESS) {
6481                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6482                         goto DONE;
6483                 }
6484                 num += actual_num;
6485         } while (num < total);
6486
6487 DONE:
6488         rte_free(req_list);
6489         return ret;
6490 }
6491
6492 /* Find out specific MAC filter */
6493 static struct i40e_mac_filter *
6494 i40e_find_mac_filter(struct i40e_vsi *vsi,
6495                          struct ether_addr *macaddr)
6496 {
6497         struct i40e_mac_filter *f;
6498
6499         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6500                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6501                         return f;
6502         }
6503
6504         return NULL;
6505 }
6506
6507 static bool
6508 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6509                          uint16_t vlan_id)
6510 {
6511         uint32_t vid_idx, vid_bit;
6512
6513         if (vlan_id > ETH_VLAN_ID_MAX)
6514                 return 0;
6515
6516         vid_idx = I40E_VFTA_IDX(vlan_id);
6517         vid_bit = I40E_VFTA_BIT(vlan_id);
6518
6519         if (vsi->vfta[vid_idx] & vid_bit)
6520                 return 1;
6521         else
6522                 return 0;
6523 }
6524
6525 static void
6526 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6527                        uint16_t vlan_id, bool on)
6528 {
6529         uint32_t vid_idx, vid_bit;
6530
6531         vid_idx = I40E_VFTA_IDX(vlan_id);
6532         vid_bit = I40E_VFTA_BIT(vlan_id);
6533
6534         if (on)
6535                 vsi->vfta[vid_idx] |= vid_bit;
6536         else
6537                 vsi->vfta[vid_idx] &= ~vid_bit;
6538 }
6539
6540 void
6541 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6542                      uint16_t vlan_id, bool on)
6543 {
6544         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6545         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6546         int ret;
6547
6548         if (vlan_id > ETH_VLAN_ID_MAX)
6549                 return;
6550
6551         i40e_store_vlan_filter(vsi, vlan_id, on);
6552
6553         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6554                 return;
6555
6556         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6557
6558         if (on) {
6559                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6560                                        &vlan_data, 1, NULL);
6561                 if (ret != I40E_SUCCESS)
6562                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6563         } else {
6564                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6565                                           &vlan_data, 1, NULL);
6566                 if (ret != I40E_SUCCESS)
6567                         PMD_DRV_LOG(ERR,
6568                                     "Failed to remove vlan filter");
6569         }
6570 }
6571
6572 /**
6573  * Find all vlan options for specific mac addr,
6574  * return with actual vlan found.
6575  */
6576 int
6577 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6578                            struct i40e_macvlan_filter *mv_f,
6579                            int num, struct ether_addr *addr)
6580 {
6581         int i;
6582         uint32_t j, k;
6583
6584         /**
6585          * Not to use i40e_find_vlan_filter to decrease the loop time,
6586          * although the code looks complex.
6587           */
6588         if (num < vsi->vlan_num)
6589                 return I40E_ERR_PARAM;
6590
6591         i = 0;
6592         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6593                 if (vsi->vfta[j]) {
6594                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6595                                 if (vsi->vfta[j] & (1 << k)) {
6596                                         if (i > num - 1) {
6597                                                 PMD_DRV_LOG(ERR,
6598                                                         "vlan number doesn't match");
6599                                                 return I40E_ERR_PARAM;
6600                                         }
6601                                         rte_memcpy(&mv_f[i].macaddr,
6602                                                         addr, ETH_ADDR_LEN);
6603                                         mv_f[i].vlan_id =
6604                                                 j * I40E_UINT32_BIT_SIZE + k;
6605                                         i++;
6606                                 }
6607                         }
6608                 }
6609         }
6610         return I40E_SUCCESS;
6611 }
6612
6613 static inline int
6614 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6615                            struct i40e_macvlan_filter *mv_f,
6616                            int num,
6617                            uint16_t vlan)
6618 {
6619         int i = 0;
6620         struct i40e_mac_filter *f;
6621
6622         if (num < vsi->mac_num)
6623                 return I40E_ERR_PARAM;
6624
6625         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6626                 if (i > num - 1) {
6627                         PMD_DRV_LOG(ERR, "buffer number not match");
6628                         return I40E_ERR_PARAM;
6629                 }
6630                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6631                                 ETH_ADDR_LEN);
6632                 mv_f[i].vlan_id = vlan;
6633                 mv_f[i].filter_type = f->mac_info.filter_type;
6634                 i++;
6635         }
6636
6637         return I40E_SUCCESS;
6638 }
6639
6640 static int
6641 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6642 {
6643         int i, j, num;
6644         struct i40e_mac_filter *f;
6645         struct i40e_macvlan_filter *mv_f;
6646         int ret = I40E_SUCCESS;
6647
6648         if (vsi == NULL || vsi->mac_num == 0)
6649                 return I40E_ERR_PARAM;
6650
6651         /* Case that no vlan is set */
6652         if (vsi->vlan_num == 0)
6653                 num = vsi->mac_num;
6654         else
6655                 num = vsi->mac_num * vsi->vlan_num;
6656
6657         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6658         if (mv_f == NULL) {
6659                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6660                 return I40E_ERR_NO_MEMORY;
6661         }
6662
6663         i = 0;
6664         if (vsi->vlan_num == 0) {
6665                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6666                         rte_memcpy(&mv_f[i].macaddr,
6667                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6668                         mv_f[i].filter_type = f->mac_info.filter_type;
6669                         mv_f[i].vlan_id = 0;
6670                         i++;
6671                 }
6672         } else {
6673                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6674                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6675                                         vsi->vlan_num, &f->mac_info.mac_addr);
6676                         if (ret != I40E_SUCCESS)
6677                                 goto DONE;
6678                         for (j = i; j < i + vsi->vlan_num; j++)
6679                                 mv_f[j].filter_type = f->mac_info.filter_type;
6680                         i += vsi->vlan_num;
6681                 }
6682         }
6683
6684         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6685 DONE:
6686         rte_free(mv_f);
6687
6688         return ret;
6689 }
6690
6691 int
6692 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6693 {
6694         struct i40e_macvlan_filter *mv_f;
6695         int mac_num;
6696         int ret = I40E_SUCCESS;
6697
6698         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6699                 return I40E_ERR_PARAM;
6700
6701         /* If it's already set, just return */
6702         if (i40e_find_vlan_filter(vsi,vlan))
6703                 return I40E_SUCCESS;
6704
6705         mac_num = vsi->mac_num;
6706
6707         if (mac_num == 0) {
6708                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6709                 return I40E_ERR_PARAM;
6710         }
6711
6712         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6713
6714         if (mv_f == NULL) {
6715                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6716                 return I40E_ERR_NO_MEMORY;
6717         }
6718
6719         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6720
6721         if (ret != I40E_SUCCESS)
6722                 goto DONE;
6723
6724         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6725
6726         if (ret != I40E_SUCCESS)
6727                 goto DONE;
6728
6729         i40e_set_vlan_filter(vsi, vlan, 1);
6730
6731         vsi->vlan_num++;
6732         ret = I40E_SUCCESS;
6733 DONE:
6734         rte_free(mv_f);
6735         return ret;
6736 }
6737
6738 int
6739 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6740 {
6741         struct i40e_macvlan_filter *mv_f;
6742         int mac_num;
6743         int ret = I40E_SUCCESS;
6744
6745         /**
6746          * Vlan 0 is the generic filter for untagged packets
6747          * and can't be removed.
6748          */
6749         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6750                 return I40E_ERR_PARAM;
6751
6752         /* If can't find it, just return */
6753         if (!i40e_find_vlan_filter(vsi, vlan))
6754                 return I40E_ERR_PARAM;
6755
6756         mac_num = vsi->mac_num;
6757
6758         if (mac_num == 0) {
6759                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6760                 return I40E_ERR_PARAM;
6761         }
6762
6763         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6764
6765         if (mv_f == NULL) {
6766                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6767                 return I40E_ERR_NO_MEMORY;
6768         }
6769
6770         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6771
6772         if (ret != I40E_SUCCESS)
6773                 goto DONE;
6774
6775         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6776
6777         if (ret != I40E_SUCCESS)
6778                 goto DONE;
6779
6780         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6781         if (vsi->vlan_num == 1) {
6782                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6783                 if (ret != I40E_SUCCESS)
6784                         goto DONE;
6785
6786                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6787                 if (ret != I40E_SUCCESS)
6788                         goto DONE;
6789         }
6790
6791         i40e_set_vlan_filter(vsi, vlan, 0);
6792
6793         vsi->vlan_num--;
6794         ret = I40E_SUCCESS;
6795 DONE:
6796         rte_free(mv_f);
6797         return ret;
6798 }
6799
6800 int
6801 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6802 {
6803         struct i40e_mac_filter *f;
6804         struct i40e_macvlan_filter *mv_f;
6805         int i, vlan_num = 0;
6806         int ret = I40E_SUCCESS;
6807
6808         /* If it's add and we've config it, return */
6809         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6810         if (f != NULL)
6811                 return I40E_SUCCESS;
6812         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6813                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6814
6815                 /**
6816                  * If vlan_num is 0, that's the first time to add mac,
6817                  * set mask for vlan_id 0.
6818                  */
6819                 if (vsi->vlan_num == 0) {
6820                         i40e_set_vlan_filter(vsi, 0, 1);
6821                         vsi->vlan_num = 1;
6822                 }
6823                 vlan_num = vsi->vlan_num;
6824         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6825                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6826                 vlan_num = 1;
6827
6828         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6829         if (mv_f == NULL) {
6830                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6831                 return I40E_ERR_NO_MEMORY;
6832         }
6833
6834         for (i = 0; i < vlan_num; i++) {
6835                 mv_f[i].filter_type = mac_filter->filter_type;
6836                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6837                                 ETH_ADDR_LEN);
6838         }
6839
6840         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6841                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6842                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6843                                         &mac_filter->mac_addr);
6844                 if (ret != I40E_SUCCESS)
6845                         goto DONE;
6846         }
6847
6848         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6849         if (ret != I40E_SUCCESS)
6850                 goto DONE;
6851
6852         /* Add the mac addr into mac list */
6853         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6854         if (f == NULL) {
6855                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6856                 ret = I40E_ERR_NO_MEMORY;
6857                 goto DONE;
6858         }
6859         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6860                         ETH_ADDR_LEN);
6861         f->mac_info.filter_type = mac_filter->filter_type;
6862         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6863         vsi->mac_num++;
6864
6865         ret = I40E_SUCCESS;
6866 DONE:
6867         rte_free(mv_f);
6868
6869         return ret;
6870 }
6871
6872 int
6873 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6874 {
6875         struct i40e_mac_filter *f;
6876         struct i40e_macvlan_filter *mv_f;
6877         int i, vlan_num;
6878         enum rte_mac_filter_type filter_type;
6879         int ret = I40E_SUCCESS;
6880
6881         /* Can't find it, return an error */
6882         f = i40e_find_mac_filter(vsi, addr);
6883         if (f == NULL)
6884                 return I40E_ERR_PARAM;
6885
6886         vlan_num = vsi->vlan_num;
6887         filter_type = f->mac_info.filter_type;
6888         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6889                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6890                 if (vlan_num == 0) {
6891                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6892                         return I40E_ERR_PARAM;
6893                 }
6894         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6895                         filter_type == RTE_MAC_HASH_MATCH)
6896                 vlan_num = 1;
6897
6898         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6899         if (mv_f == NULL) {
6900                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6901                 return I40E_ERR_NO_MEMORY;
6902         }
6903
6904         for (i = 0; i < vlan_num; i++) {
6905                 mv_f[i].filter_type = filter_type;
6906                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6907                                 ETH_ADDR_LEN);
6908         }
6909         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6910                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6911                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6912                 if (ret != I40E_SUCCESS)
6913                         goto DONE;
6914         }
6915
6916         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6917         if (ret != I40E_SUCCESS)
6918                 goto DONE;
6919
6920         /* Remove the mac addr into mac list */
6921         TAILQ_REMOVE(&vsi->mac_list, f, next);
6922         rte_free(f);
6923         vsi->mac_num--;
6924
6925         ret = I40E_SUCCESS;
6926 DONE:
6927         rte_free(mv_f);
6928         return ret;
6929 }
6930
6931 /* Configure hash enable flags for RSS */
6932 uint64_t
6933 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6934 {
6935         uint64_t hena = 0;
6936         int i;
6937
6938         if (!flags)
6939                 return hena;
6940
6941         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6942                 if (flags & (1ULL << i))
6943                         hena |= adapter->pctypes_tbl[i];
6944         }
6945
6946         return hena;
6947 }
6948
6949 /* Parse the hash enable flags */
6950 uint64_t
6951 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6952 {
6953         uint64_t rss_hf = 0;
6954
6955         if (!flags)
6956                 return rss_hf;
6957         int i;
6958
6959         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6960                 if (flags & adapter->pctypes_tbl[i])
6961                         rss_hf |= (1ULL << i);
6962         }
6963         return rss_hf;
6964 }
6965
6966 /* Disable RSS */
6967 static void
6968 i40e_pf_disable_rss(struct i40e_pf *pf)
6969 {
6970         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6971
6972         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6973         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6974         I40E_WRITE_FLUSH(hw);
6975 }
6976
6977 static int
6978 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6979 {
6980         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6981         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6982         int ret = 0;
6983
6984         if (!key || key_len == 0) {
6985                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6986                 return 0;
6987         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6988                 sizeof(uint32_t)) {
6989                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6990                 return -EINVAL;
6991         }
6992
6993         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6994                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6995                         (struct i40e_aqc_get_set_rss_key_data *)key;
6996
6997                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6998                 if (ret)
6999                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7000         } else {
7001                 uint32_t *hash_key = (uint32_t *)key;
7002                 uint16_t i;
7003
7004                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7005                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
7006                 I40E_WRITE_FLUSH(hw);
7007         }
7008
7009         return ret;
7010 }
7011
7012 static int
7013 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7014 {
7015         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7016         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7017         int ret;
7018
7019         if (!key || !key_len)
7020                 return -EINVAL;
7021
7022         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7023                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7024                         (struct i40e_aqc_get_set_rss_key_data *)key);
7025                 if (ret) {
7026                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7027                         return ret;
7028                 }
7029         } else {
7030                 uint32_t *key_dw = (uint32_t *)key;
7031                 uint16_t i;
7032
7033                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7034                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
7035         }
7036         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
7037
7038         return 0;
7039 }
7040
7041 static int
7042 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7043 {
7044         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7045         uint64_t hena;
7046         int ret;
7047
7048         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7049                                rss_conf->rss_key_len);
7050         if (ret)
7051                 return ret;
7052
7053         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7054         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7055         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7056         I40E_WRITE_FLUSH(hw);
7057
7058         return 0;
7059 }
7060
7061 static int
7062 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7063                          struct rte_eth_rss_conf *rss_conf)
7064 {
7065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7067         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7068         uint64_t hena;
7069
7070         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7071         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7072
7073         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7074                 if (rss_hf != 0) /* Enable RSS */
7075                         return -EINVAL;
7076                 return 0; /* Nothing to do */
7077         }
7078         /* RSS enabled */
7079         if (rss_hf == 0) /* Disable RSS */
7080                 return -EINVAL;
7081
7082         return i40e_hw_rss_hash_set(pf, rss_conf);
7083 }
7084
7085 static int
7086 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7087                            struct rte_eth_rss_conf *rss_conf)
7088 {
7089         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7090         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7091         uint64_t hena;
7092
7093         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7094                          &rss_conf->rss_key_len);
7095
7096         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7097         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7098         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7099
7100         return 0;
7101 }
7102
7103 static int
7104 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7105 {
7106         switch (filter_type) {
7107         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7108                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7109                 break;
7110         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7111                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7112                 break;
7113         case RTE_TUNNEL_FILTER_IMAC_TENID:
7114                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7115                 break;
7116         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7117                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7118                 break;
7119         case ETH_TUNNEL_FILTER_IMAC:
7120                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7121                 break;
7122         case ETH_TUNNEL_FILTER_OIP:
7123                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7124                 break;
7125         case ETH_TUNNEL_FILTER_IIP:
7126                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7127                 break;
7128         default:
7129                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7130                 return -EINVAL;
7131         }
7132
7133         return 0;
7134 }
7135
7136 /* Convert tunnel filter structure */
7137 static int
7138 i40e_tunnel_filter_convert(
7139         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7140         struct i40e_tunnel_filter *tunnel_filter)
7141 {
7142         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7143                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7144         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7145                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7146         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7147         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7148              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7149             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7150                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7151         else
7152                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7153         tunnel_filter->input.flags = cld_filter->element.flags;
7154         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7155         tunnel_filter->queue = cld_filter->element.queue_number;
7156         rte_memcpy(tunnel_filter->input.general_fields,
7157                    cld_filter->general_fields,
7158                    sizeof(cld_filter->general_fields));
7159
7160         return 0;
7161 }
7162
7163 /* Check if there exists the tunnel filter */
7164 struct i40e_tunnel_filter *
7165 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7166                              const struct i40e_tunnel_filter_input *input)
7167 {
7168         int ret;
7169
7170         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7171         if (ret < 0)
7172                 return NULL;
7173
7174         return tunnel_rule->hash_map[ret];
7175 }
7176
7177 /* Add a tunnel filter into the SW list */
7178 static int
7179 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7180                              struct i40e_tunnel_filter *tunnel_filter)
7181 {
7182         struct i40e_tunnel_rule *rule = &pf->tunnel;
7183         int ret;
7184
7185         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7186         if (ret < 0) {
7187                 PMD_DRV_LOG(ERR,
7188                             "Failed to insert tunnel filter to hash table %d!",
7189                             ret);
7190                 return ret;
7191         }
7192         rule->hash_map[ret] = tunnel_filter;
7193
7194         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7195
7196         return 0;
7197 }
7198
7199 /* Delete a tunnel filter from the SW list */
7200 int
7201 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7202                           struct i40e_tunnel_filter_input *input)
7203 {
7204         struct i40e_tunnel_rule *rule = &pf->tunnel;
7205         struct i40e_tunnel_filter *tunnel_filter;
7206         int ret;
7207
7208         ret = rte_hash_del_key(rule->hash_table, input);
7209         if (ret < 0) {
7210                 PMD_DRV_LOG(ERR,
7211                             "Failed to delete tunnel filter to hash table %d!",
7212                             ret);
7213                 return ret;
7214         }
7215         tunnel_filter = rule->hash_map[ret];
7216         rule->hash_map[ret] = NULL;
7217
7218         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7219         rte_free(tunnel_filter);
7220
7221         return 0;
7222 }
7223
7224 int
7225 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7226                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7227                         uint8_t add)
7228 {
7229         uint16_t ip_type;
7230         uint32_t ipv4_addr, ipv4_addr_le;
7231         uint8_t i, tun_type = 0;
7232         /* internal varialbe to convert ipv6 byte order */
7233         uint32_t convert_ipv6[4];
7234         int val, ret = 0;
7235         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7236         struct i40e_vsi *vsi = pf->main_vsi;
7237         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7238         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7239         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7240         struct i40e_tunnel_filter *tunnel, *node;
7241         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7242
7243         cld_filter = rte_zmalloc("tunnel_filter",
7244                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7245         0);
7246
7247         if (NULL == cld_filter) {
7248                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7249                 return -ENOMEM;
7250         }
7251         pfilter = cld_filter;
7252
7253         ether_addr_copy(&tunnel_filter->outer_mac,
7254                         (struct ether_addr *)&pfilter->element.outer_mac);
7255         ether_addr_copy(&tunnel_filter->inner_mac,
7256                         (struct ether_addr *)&pfilter->element.inner_mac);
7257
7258         pfilter->element.inner_vlan =
7259                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7260         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7261                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7262                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7263                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7264                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7265                                 &ipv4_addr_le,
7266                                 sizeof(pfilter->element.ipaddr.v4.data));
7267         } else {
7268                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7269                 for (i = 0; i < 4; i++) {
7270                         convert_ipv6[i] =
7271                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7272                 }
7273                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7274                            &convert_ipv6,
7275                            sizeof(pfilter->element.ipaddr.v6.data));
7276         }
7277
7278         /* check tunneled type */
7279         switch (tunnel_filter->tunnel_type) {
7280         case RTE_TUNNEL_TYPE_VXLAN:
7281                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7282                 break;
7283         case RTE_TUNNEL_TYPE_NVGRE:
7284                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7285                 break;
7286         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7287                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7288                 break;
7289         default:
7290                 /* Other tunnel types is not supported. */
7291                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7292                 rte_free(cld_filter);
7293                 return -EINVAL;
7294         }
7295
7296         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7297                                        &pfilter->element.flags);
7298         if (val < 0) {
7299                 rte_free(cld_filter);
7300                 return -EINVAL;
7301         }
7302
7303         pfilter->element.flags |= rte_cpu_to_le_16(
7304                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7305                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7306         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7307         pfilter->element.queue_number =
7308                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7309
7310         /* Check if there is the filter in SW list */
7311         memset(&check_filter, 0, sizeof(check_filter));
7312         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7313         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7314         if (add && node) {
7315                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7316                 rte_free(cld_filter);
7317                 return -EINVAL;
7318         }
7319
7320         if (!add && !node) {
7321                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7322                 rte_free(cld_filter);
7323                 return -EINVAL;
7324         }
7325
7326         if (add) {
7327                 ret = i40e_aq_add_cloud_filters(hw,
7328                                         vsi->seid, &cld_filter->element, 1);
7329                 if (ret < 0) {
7330                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7331                         rte_free(cld_filter);
7332                         return -ENOTSUP;
7333                 }
7334                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7335                 if (tunnel == NULL) {
7336                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7337                         rte_free(cld_filter);
7338                         return -ENOMEM;
7339                 }
7340
7341                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7342                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7343                 if (ret < 0)
7344                         rte_free(tunnel);
7345         } else {
7346                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7347                                                    &cld_filter->element, 1);
7348                 if (ret < 0) {
7349                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7350                         rte_free(cld_filter);
7351                         return -ENOTSUP;
7352                 }
7353                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7354         }
7355
7356         rte_free(cld_filter);
7357         return ret;
7358 }
7359
7360 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7361 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7362 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7363 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7364 #define I40E_TR_GRE_KEY_MASK                    0x400
7365 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7366 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7367
7368 static enum
7369 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7370 {
7371         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7372         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7373         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7374         enum i40e_status_code status = I40E_SUCCESS;
7375
7376         if (pf->support_multi_driver) {
7377                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7378                 return I40E_NOT_SUPPORTED;
7379         }
7380
7381         memset(&filter_replace, 0,
7382                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7383         memset(&filter_replace_buf, 0,
7384                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7385
7386         /* create L1 filter */
7387         filter_replace.old_filter_type =
7388                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7389         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7390         filter_replace.tr_bit = 0;
7391
7392         /* Prepare the buffer, 3 entries */
7393         filter_replace_buf.data[0] =
7394                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7395         filter_replace_buf.data[0] |=
7396                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7397         filter_replace_buf.data[2] = 0xFF;
7398         filter_replace_buf.data[3] = 0xFF;
7399         filter_replace_buf.data[4] =
7400                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7401         filter_replace_buf.data[4] |=
7402                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7403         filter_replace_buf.data[7] = 0xF0;
7404         filter_replace_buf.data[8]
7405                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7406         filter_replace_buf.data[8] |=
7407                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7408         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7409                 I40E_TR_GENEVE_KEY_MASK |
7410                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7411         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7412                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7413                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7414
7415         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7416                                                &filter_replace_buf);
7417         if (!status)
7418                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7419         return status;
7420 }
7421
7422 static enum
7423 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7424 {
7425         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7426         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7427         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7428         enum i40e_status_code status = I40E_SUCCESS;
7429
7430         if (pf->support_multi_driver) {
7431                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7432                 return I40E_NOT_SUPPORTED;
7433         }
7434
7435         /* For MPLSoUDP */
7436         memset(&filter_replace, 0,
7437                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7438         memset(&filter_replace_buf, 0,
7439                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7440         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7441                 I40E_AQC_MIRROR_CLOUD_FILTER;
7442         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7443         filter_replace.new_filter_type =
7444                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7445         /* Prepare the buffer, 2 entries */
7446         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7447         filter_replace_buf.data[0] |=
7448                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7449         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7450         filter_replace_buf.data[4] |=
7451                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7452         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7453                                                &filter_replace_buf);
7454         if (status < 0)
7455                 return status;
7456
7457         /* For MPLSoGRE */
7458         memset(&filter_replace, 0,
7459                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7460         memset(&filter_replace_buf, 0,
7461                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7462
7463         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7464                 I40E_AQC_MIRROR_CLOUD_FILTER;
7465         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7466         filter_replace.new_filter_type =
7467                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7468         /* Prepare the buffer, 2 entries */
7469         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7470         filter_replace_buf.data[0] |=
7471                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7472         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7473         filter_replace_buf.data[4] |=
7474                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7475
7476         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7477                                                &filter_replace_buf);
7478         if (!status)
7479                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7480         return status;
7481 }
7482
7483 static enum i40e_status_code
7484 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7485 {
7486         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7487         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7488         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7489         enum i40e_status_code status = I40E_SUCCESS;
7490
7491         if (pf->support_multi_driver) {
7492                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7493                 return I40E_NOT_SUPPORTED;
7494         }
7495
7496         /* For GTP-C */
7497         memset(&filter_replace, 0,
7498                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7499         memset(&filter_replace_buf, 0,
7500                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7501         /* create L1 filter */
7502         filter_replace.old_filter_type =
7503                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7504         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7505         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7506                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7507         /* Prepare the buffer, 2 entries */
7508         filter_replace_buf.data[0] =
7509                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7510         filter_replace_buf.data[0] |=
7511                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7512         filter_replace_buf.data[2] = 0xFF;
7513         filter_replace_buf.data[3] = 0xFF;
7514         filter_replace_buf.data[4] =
7515                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7516         filter_replace_buf.data[4] |=
7517                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7518         filter_replace_buf.data[6] = 0xFF;
7519         filter_replace_buf.data[7] = 0xFF;
7520         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7521                                                &filter_replace_buf);
7522         if (status < 0)
7523                 return status;
7524         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7525                     "cloud l1 type is changed from 0x%x to 0x%x",
7526                     filter_replace.old_filter_type,
7527                     filter_replace.new_filter_type);
7528
7529         /* for GTP-U */
7530         memset(&filter_replace, 0,
7531                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7532         memset(&filter_replace_buf, 0,
7533                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7534         /* create L1 filter */
7535         filter_replace.old_filter_type =
7536                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7537         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7538         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7539                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7540         /* Prepare the buffer, 2 entries */
7541         filter_replace_buf.data[0] =
7542                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7543         filter_replace_buf.data[0] |=
7544                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7545         filter_replace_buf.data[2] = 0xFF;
7546         filter_replace_buf.data[3] = 0xFF;
7547         filter_replace_buf.data[4] =
7548                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7549         filter_replace_buf.data[4] |=
7550                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7551         filter_replace_buf.data[6] = 0xFF;
7552         filter_replace_buf.data[7] = 0xFF;
7553
7554         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7555                                                &filter_replace_buf);
7556         if (!status) {
7557                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7558                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7559                             "cloud l1 type is changed from 0x%x to 0x%x",
7560                             filter_replace.old_filter_type,
7561                             filter_replace.new_filter_type);
7562         }
7563         return status;
7564 }
7565
7566 static enum
7567 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7568 {
7569         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7570         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7571         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7572         enum i40e_status_code status = I40E_SUCCESS;
7573
7574         if (pf->support_multi_driver) {
7575                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7576                 return I40E_NOT_SUPPORTED;
7577         }
7578
7579         /* for GTP-C */
7580         memset(&filter_replace, 0,
7581                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7582         memset(&filter_replace_buf, 0,
7583                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7584         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7585         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7586         filter_replace.new_filter_type =
7587                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7588         /* Prepare the buffer, 2 entries */
7589         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7590         filter_replace_buf.data[0] |=
7591                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7592         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7593         filter_replace_buf.data[4] |=
7594                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7595         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7596                                                &filter_replace_buf);
7597         if (status < 0)
7598                 return status;
7599         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7600                     "cloud filter type is changed from 0x%x to 0x%x",
7601                     filter_replace.old_filter_type,
7602                     filter_replace.new_filter_type);
7603
7604         /* for GTP-U */
7605         memset(&filter_replace, 0,
7606                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7607         memset(&filter_replace_buf, 0,
7608                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7609         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7610         filter_replace.old_filter_type =
7611                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7612         filter_replace.new_filter_type =
7613                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7614         /* Prepare the buffer, 2 entries */
7615         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7616         filter_replace_buf.data[0] |=
7617                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7618         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7619         filter_replace_buf.data[4] |=
7620                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7621
7622         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7623                                                &filter_replace_buf);
7624         if (!status) {
7625                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7626                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7627                             "cloud filter type is changed from 0x%x to 0x%x",
7628                             filter_replace.old_filter_type,
7629                             filter_replace.new_filter_type);
7630         }
7631         return status;
7632 }
7633
7634 int
7635 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7636                       struct i40e_tunnel_filter_conf *tunnel_filter,
7637                       uint8_t add)
7638 {
7639         uint16_t ip_type;
7640         uint32_t ipv4_addr, ipv4_addr_le;
7641         uint8_t i, tun_type = 0;
7642         /* internal variable to convert ipv6 byte order */
7643         uint32_t convert_ipv6[4];
7644         int val, ret = 0;
7645         struct i40e_pf_vf *vf = NULL;
7646         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7647         struct i40e_vsi *vsi;
7648         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7649         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7650         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7651         struct i40e_tunnel_filter *tunnel, *node;
7652         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7653         uint32_t teid_le;
7654         bool big_buffer = 0;
7655
7656         cld_filter = rte_zmalloc("tunnel_filter",
7657                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7658                          0);
7659
7660         if (cld_filter == NULL) {
7661                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7662                 return -ENOMEM;
7663         }
7664         pfilter = cld_filter;
7665
7666         ether_addr_copy(&tunnel_filter->outer_mac,
7667                         (struct ether_addr *)&pfilter->element.outer_mac);
7668         ether_addr_copy(&tunnel_filter->inner_mac,
7669                         (struct ether_addr *)&pfilter->element.inner_mac);
7670
7671         pfilter->element.inner_vlan =
7672                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7673         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7674                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7675                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7676                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7677                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7678                                 &ipv4_addr_le,
7679                                 sizeof(pfilter->element.ipaddr.v4.data));
7680         } else {
7681                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7682                 for (i = 0; i < 4; i++) {
7683                         convert_ipv6[i] =
7684                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7685                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7686                 }
7687                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7688                            &convert_ipv6,
7689                            sizeof(pfilter->element.ipaddr.v6.data));
7690         }
7691
7692         /* check tunneled type */
7693         switch (tunnel_filter->tunnel_type) {
7694         case I40E_TUNNEL_TYPE_VXLAN:
7695                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7696                 break;
7697         case I40E_TUNNEL_TYPE_NVGRE:
7698                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7699                 break;
7700         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7701                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7702                 break;
7703         case I40E_TUNNEL_TYPE_MPLSoUDP:
7704                 if (!pf->mpls_replace_flag) {
7705                         i40e_replace_mpls_l1_filter(pf);
7706                         i40e_replace_mpls_cloud_filter(pf);
7707                         pf->mpls_replace_flag = 1;
7708                 }
7709                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7710                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7711                         teid_le >> 4;
7712                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7713                         (teid_le & 0xF) << 12;
7714                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7715                         0x40;
7716                 big_buffer = 1;
7717                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7718                 break;
7719         case I40E_TUNNEL_TYPE_MPLSoGRE:
7720                 if (!pf->mpls_replace_flag) {
7721                         i40e_replace_mpls_l1_filter(pf);
7722                         i40e_replace_mpls_cloud_filter(pf);
7723                         pf->mpls_replace_flag = 1;
7724                 }
7725                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7726                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7727                         teid_le >> 4;
7728                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7729                         (teid_le & 0xF) << 12;
7730                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7731                         0x0;
7732                 big_buffer = 1;
7733                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7734                 break;
7735         case I40E_TUNNEL_TYPE_GTPC:
7736                 if (!pf->gtp_replace_flag) {
7737                         i40e_replace_gtp_l1_filter(pf);
7738                         i40e_replace_gtp_cloud_filter(pf);
7739                         pf->gtp_replace_flag = 1;
7740                 }
7741                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7742                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7743                         (teid_le >> 16) & 0xFFFF;
7744                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7745                         teid_le & 0xFFFF;
7746                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7747                         0x0;
7748                 big_buffer = 1;
7749                 break;
7750         case I40E_TUNNEL_TYPE_GTPU:
7751                 if (!pf->gtp_replace_flag) {
7752                         i40e_replace_gtp_l1_filter(pf);
7753                         i40e_replace_gtp_cloud_filter(pf);
7754                         pf->gtp_replace_flag = 1;
7755                 }
7756                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7757                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7758                         (teid_le >> 16) & 0xFFFF;
7759                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7760                         teid_le & 0xFFFF;
7761                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7762                         0x0;
7763                 big_buffer = 1;
7764                 break;
7765         case I40E_TUNNEL_TYPE_QINQ:
7766                 if (!pf->qinq_replace_flag) {
7767                         ret = i40e_cloud_filter_qinq_create(pf);
7768                         if (ret < 0)
7769                                 PMD_DRV_LOG(DEBUG,
7770                                             "QinQ tunnel filter already created.");
7771                         pf->qinq_replace_flag = 1;
7772                 }
7773                 /*      Add in the General fields the values of
7774                  *      the Outer and Inner VLAN
7775                  *      Big Buffer should be set, see changes in
7776                  *      i40e_aq_add_cloud_filters
7777                  */
7778                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7779                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7780                 big_buffer = 1;
7781                 break;
7782         default:
7783                 /* Other tunnel types is not supported. */
7784                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7785                 rte_free(cld_filter);
7786                 return -EINVAL;
7787         }
7788
7789         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7790                 pfilter->element.flags =
7791                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7792         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7793                 pfilter->element.flags =
7794                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7795         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7796                 pfilter->element.flags =
7797                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7798         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7799                 pfilter->element.flags =
7800                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7801         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7802                 pfilter->element.flags |=
7803                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7804         else {
7805                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7806                                                 &pfilter->element.flags);
7807                 if (val < 0) {
7808                         rte_free(cld_filter);
7809                         return -EINVAL;
7810                 }
7811         }
7812
7813         pfilter->element.flags |= rte_cpu_to_le_16(
7814                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7815                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7816         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7817         pfilter->element.queue_number =
7818                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7819
7820         if (!tunnel_filter->is_to_vf)
7821                 vsi = pf->main_vsi;
7822         else {
7823                 if (tunnel_filter->vf_id >= pf->vf_num) {
7824                         PMD_DRV_LOG(ERR, "Invalid argument.");
7825                         rte_free(cld_filter);
7826                         return -EINVAL;
7827                 }
7828                 vf = &pf->vfs[tunnel_filter->vf_id];
7829                 vsi = vf->vsi;
7830         }
7831
7832         /* Check if there is the filter in SW list */
7833         memset(&check_filter, 0, sizeof(check_filter));
7834         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7835         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7836         check_filter.vf_id = tunnel_filter->vf_id;
7837         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7838         if (add && node) {
7839                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7840                 rte_free(cld_filter);
7841                 return -EINVAL;
7842         }
7843
7844         if (!add && !node) {
7845                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7846                 rte_free(cld_filter);
7847                 return -EINVAL;
7848         }
7849
7850         if (add) {
7851                 if (big_buffer)
7852                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7853                                                    vsi->seid, cld_filter, 1);
7854                 else
7855                         ret = i40e_aq_add_cloud_filters(hw,
7856                                         vsi->seid, &cld_filter->element, 1);
7857                 if (ret < 0) {
7858                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7859                         rte_free(cld_filter);
7860                         return -ENOTSUP;
7861                 }
7862                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7863                 if (tunnel == NULL) {
7864                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7865                         rte_free(cld_filter);
7866                         return -ENOMEM;
7867                 }
7868
7869                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7870                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7871                 if (ret < 0)
7872                         rte_free(tunnel);
7873         } else {
7874                 if (big_buffer)
7875                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7876                                 hw, vsi->seid, cld_filter, 1);
7877                 else
7878                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7879                                                    &cld_filter->element, 1);
7880                 if (ret < 0) {
7881                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7882                         rte_free(cld_filter);
7883                         return -ENOTSUP;
7884                 }
7885                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7886         }
7887
7888         rte_free(cld_filter);
7889         return ret;
7890 }
7891
7892 static int
7893 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7894 {
7895         uint8_t i;
7896
7897         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7898                 if (pf->vxlan_ports[i] == port)
7899                         return i;
7900         }
7901
7902         return -1;
7903 }
7904
7905 static int
7906 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7907 {
7908         int  idx, ret;
7909         uint8_t filter_idx;
7910         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7911
7912         idx = i40e_get_vxlan_port_idx(pf, port);
7913
7914         /* Check if port already exists */
7915         if (idx >= 0) {
7916                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7917                 return -EINVAL;
7918         }
7919
7920         /* Now check if there is space to add the new port */
7921         idx = i40e_get_vxlan_port_idx(pf, 0);
7922         if (idx < 0) {
7923                 PMD_DRV_LOG(ERR,
7924                         "Maximum number of UDP ports reached, not adding port %d",
7925                         port);
7926                 return -ENOSPC;
7927         }
7928
7929         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7930                                         &filter_idx, NULL);
7931         if (ret < 0) {
7932                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7933                 return -1;
7934         }
7935
7936         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7937                          port,  filter_idx);
7938
7939         /* New port: add it and mark its index in the bitmap */
7940         pf->vxlan_ports[idx] = port;
7941         pf->vxlan_bitmap |= (1 << idx);
7942
7943         if (!(pf->flags & I40E_FLAG_VXLAN))
7944                 pf->flags |= I40E_FLAG_VXLAN;
7945
7946         return 0;
7947 }
7948
7949 static int
7950 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7951 {
7952         int idx;
7953         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7954
7955         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7956                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7957                 return -EINVAL;
7958         }
7959
7960         idx = i40e_get_vxlan_port_idx(pf, port);
7961
7962         if (idx < 0) {
7963                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7964                 return -EINVAL;
7965         }
7966
7967         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7968                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7969                 return -1;
7970         }
7971
7972         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7973                         port, idx);
7974
7975         pf->vxlan_ports[idx] = 0;
7976         pf->vxlan_bitmap &= ~(1 << idx);
7977
7978         if (!pf->vxlan_bitmap)
7979                 pf->flags &= ~I40E_FLAG_VXLAN;
7980
7981         return 0;
7982 }
7983
7984 /* Add UDP tunneling port */
7985 static int
7986 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7987                              struct rte_eth_udp_tunnel *udp_tunnel)
7988 {
7989         int ret = 0;
7990         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7991
7992         if (udp_tunnel == NULL)
7993                 return -EINVAL;
7994
7995         switch (udp_tunnel->prot_type) {
7996         case RTE_TUNNEL_TYPE_VXLAN:
7997                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7998                 break;
7999
8000         case RTE_TUNNEL_TYPE_GENEVE:
8001         case RTE_TUNNEL_TYPE_TEREDO:
8002                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8003                 ret = -1;
8004                 break;
8005
8006         default:
8007                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8008                 ret = -1;
8009                 break;
8010         }
8011
8012         return ret;
8013 }
8014
8015 /* Remove UDP tunneling port */
8016 static int
8017 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8018                              struct rte_eth_udp_tunnel *udp_tunnel)
8019 {
8020         int ret = 0;
8021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8022
8023         if (udp_tunnel == NULL)
8024                 return -EINVAL;
8025
8026         switch (udp_tunnel->prot_type) {
8027         case RTE_TUNNEL_TYPE_VXLAN:
8028                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8029                 break;
8030         case RTE_TUNNEL_TYPE_GENEVE:
8031         case RTE_TUNNEL_TYPE_TEREDO:
8032                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8033                 ret = -1;
8034                 break;
8035         default:
8036                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8037                 ret = -1;
8038                 break;
8039         }
8040
8041         return ret;
8042 }
8043
8044 /* Calculate the maximum number of contiguous PF queues that are configured */
8045 static int
8046 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8047 {
8048         struct rte_eth_dev_data *data = pf->dev_data;
8049         int i, num;
8050         struct i40e_rx_queue *rxq;
8051
8052         num = 0;
8053         for (i = 0; i < pf->lan_nb_qps; i++) {
8054                 rxq = data->rx_queues[i];
8055                 if (rxq && rxq->q_set)
8056                         num++;
8057                 else
8058                         break;
8059         }
8060
8061         return num;
8062 }
8063
8064 /* Configure RSS */
8065 static int
8066 i40e_pf_config_rss(struct i40e_pf *pf)
8067 {
8068         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8069         struct rte_eth_rss_conf rss_conf;
8070         uint32_t i, lut = 0;
8071         uint16_t j, num;
8072
8073         /*
8074          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8075          * It's necessary to calculate the actual PF queues that are configured.
8076          */
8077         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8078                 num = i40e_pf_calc_configured_queues_num(pf);
8079         else
8080                 num = pf->dev_data->nb_rx_queues;
8081
8082         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8083         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8084                         num);
8085
8086         if (num == 0) {
8087                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8088                 return -ENOTSUP;
8089         }
8090
8091         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8092                 if (j == num)
8093                         j = 0;
8094                 lut = (lut << 8) | (j & ((0x1 <<
8095                         hw->func_caps.rss_table_entry_width) - 1));
8096                 if ((i & 3) == 3)
8097                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8098         }
8099
8100         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8101         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8102                 i40e_pf_disable_rss(pf);
8103                 return 0;
8104         }
8105         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8106                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8107                 /* Random default keys */
8108                 static uint32_t rss_key_default[] = {0x6b793944,
8109                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8110                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8111                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8112
8113                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8114                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8115                                                         sizeof(uint32_t);
8116         }
8117
8118         return i40e_hw_rss_hash_set(pf, &rss_conf);
8119 }
8120
8121 static int
8122 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8123                                struct rte_eth_tunnel_filter_conf *filter)
8124 {
8125         if (pf == NULL || filter == NULL) {
8126                 PMD_DRV_LOG(ERR, "Invalid parameter");
8127                 return -EINVAL;
8128         }
8129
8130         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8131                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8132                 return -EINVAL;
8133         }
8134
8135         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8136                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8137                 return -EINVAL;
8138         }
8139
8140         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8141                 (is_zero_ether_addr(&filter->outer_mac))) {
8142                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8143                 return -EINVAL;
8144         }
8145
8146         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8147                 (is_zero_ether_addr(&filter->inner_mac))) {
8148                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8149                 return -EINVAL;
8150         }
8151
8152         return 0;
8153 }
8154
8155 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8156 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8157 static int
8158 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8159 {
8160         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8161         uint32_t val, reg;
8162         int ret = -EINVAL;
8163
8164         if (pf->support_multi_driver) {
8165                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8166                 return -ENOTSUP;
8167         }
8168
8169         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8170         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8171
8172         if (len == 3) {
8173                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8174         } else if (len == 4) {
8175                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8176         } else {
8177                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8178                 return ret;
8179         }
8180
8181         if (reg != val) {
8182                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8183                                                    reg, NULL);
8184                 if (ret != 0)
8185                         return ret;
8186                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8187                             "with value 0x%08x",
8188                             I40E_GL_PRS_FVBM(2), reg);
8189                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8190         } else {
8191                 ret = 0;
8192         }
8193         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8194                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8195
8196         return ret;
8197 }
8198
8199 static int
8200 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8201 {
8202         int ret = -EINVAL;
8203
8204         if (!hw || !cfg)
8205                 return -EINVAL;
8206
8207         switch (cfg->cfg_type) {
8208         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8209                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8210                 break;
8211         default:
8212                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8213                 break;
8214         }
8215
8216         return ret;
8217 }
8218
8219 static int
8220 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8221                                enum rte_filter_op filter_op,
8222                                void *arg)
8223 {
8224         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8225         int ret = I40E_ERR_PARAM;
8226
8227         switch (filter_op) {
8228         case RTE_ETH_FILTER_SET:
8229                 ret = i40e_dev_global_config_set(hw,
8230                         (struct rte_eth_global_cfg *)arg);
8231                 break;
8232         default:
8233                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8234                 break;
8235         }
8236
8237         return ret;
8238 }
8239
8240 static int
8241 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8242                           enum rte_filter_op filter_op,
8243                           void *arg)
8244 {
8245         struct rte_eth_tunnel_filter_conf *filter;
8246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8247         int ret = I40E_SUCCESS;
8248
8249         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8250
8251         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8252                 return I40E_ERR_PARAM;
8253
8254         switch (filter_op) {
8255         case RTE_ETH_FILTER_NOP:
8256                 if (!(pf->flags & I40E_FLAG_VXLAN))
8257                         ret = I40E_NOT_SUPPORTED;
8258                 break;
8259         case RTE_ETH_FILTER_ADD:
8260                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8261                 break;
8262         case RTE_ETH_FILTER_DELETE:
8263                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8264                 break;
8265         default:
8266                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8267                 ret = I40E_ERR_PARAM;
8268                 break;
8269         }
8270
8271         return ret;
8272 }
8273
8274 static int
8275 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8276 {
8277         int ret = 0;
8278         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8279
8280         /* RSS setup */
8281         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8282                 ret = i40e_pf_config_rss(pf);
8283         else
8284                 i40e_pf_disable_rss(pf);
8285
8286         return ret;
8287 }
8288
8289 /* Get the symmetric hash enable configurations per port */
8290 static void
8291 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8292 {
8293         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8294
8295         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8296 }
8297
8298 /* Set the symmetric hash enable configurations per port */
8299 static void
8300 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8301 {
8302         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8303
8304         if (enable > 0) {
8305                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8306                         PMD_DRV_LOG(INFO,
8307                                 "Symmetric hash has already been enabled");
8308                         return;
8309                 }
8310                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8311         } else {
8312                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8313                         PMD_DRV_LOG(INFO,
8314                                 "Symmetric hash has already been disabled");
8315                         return;
8316                 }
8317                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8318         }
8319         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8320         I40E_WRITE_FLUSH(hw);
8321 }
8322
8323 /*
8324  * Get global configurations of hash function type and symmetric hash enable
8325  * per flow type (pctype). Note that global configuration means it affects all
8326  * the ports on the same NIC.
8327  */
8328 static int
8329 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8330                                    struct rte_eth_hash_global_conf *g_cfg)
8331 {
8332         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8333         uint32_t reg;
8334         uint16_t i, j;
8335
8336         memset(g_cfg, 0, sizeof(*g_cfg));
8337         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8338         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8339                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8340         else
8341                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8342         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8343                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8344
8345         /*
8346          * We work only with lowest 32 bits which is not correct, but to work
8347          * properly the valid_bit_mask size should be increased up to 64 bits
8348          * and this will brake ABI. This modification will be done in next
8349          * release
8350          */
8351         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8352
8353         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8354                 if (!adapter->pctypes_tbl[i])
8355                         continue;
8356                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8357                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8358                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8359                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8360                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8361                                         g_cfg->sym_hash_enable_mask[0] |=
8362                                                                 (1UL << i);
8363                                 }
8364                         }
8365                 }
8366         }
8367
8368         return 0;
8369 }
8370
8371 static int
8372 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8373                               const struct rte_eth_hash_global_conf *g_cfg)
8374 {
8375         uint32_t i;
8376         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8377
8378         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8379                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8380                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8381                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8382                                                 g_cfg->hash_func);
8383                 return -EINVAL;
8384         }
8385
8386         /*
8387          * As i40e supports less than 32 flow types, only first 32 bits need to
8388          * be checked.
8389          */
8390         mask0 = g_cfg->valid_bit_mask[0];
8391         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8392                 if (i == 0) {
8393                         /* Check if any unsupported flow type configured */
8394                         if ((mask0 | i40e_mask) ^ i40e_mask)
8395                                 goto mask_err;
8396                 } else {
8397                         if (g_cfg->valid_bit_mask[i])
8398                                 goto mask_err;
8399                 }
8400         }
8401
8402         return 0;
8403
8404 mask_err:
8405         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8406
8407         return -EINVAL;
8408 }
8409
8410 /*
8411  * Set global configurations of hash function type and symmetric hash enable
8412  * per flow type (pctype). Note any modifying global configuration will affect
8413  * all the ports on the same NIC.
8414  */
8415 static int
8416 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8417                                    struct rte_eth_hash_global_conf *g_cfg)
8418 {
8419         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8420         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8421         int ret;
8422         uint16_t i, j;
8423         uint32_t reg;
8424         /*
8425          * We work only with lowest 32 bits which is not correct, but to work
8426          * properly the valid_bit_mask size should be increased up to 64 bits
8427          * and this will brake ABI. This modification will be done in next
8428          * release
8429          */
8430         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8431                                         (uint32_t)adapter->flow_types_mask;
8432
8433         if (pf->support_multi_driver) {
8434                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8435                 return -ENOTSUP;
8436         }
8437
8438         /* Check the input parameters */
8439         ret = i40e_hash_global_config_check(adapter, g_cfg);
8440         if (ret < 0)
8441                 return ret;
8442
8443         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8444                 if (mask0 & (1UL << i)) {
8445                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8446                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8447
8448                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8449                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8450                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8451                                         i40e_write_global_rx_ctl(hw,
8452                                                           I40E_GLQF_HSYM(j),
8453                                                           reg);
8454                         }
8455                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8456                 }
8457         }
8458
8459         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8460         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8461                 /* Toeplitz */
8462                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8463                         PMD_DRV_LOG(DEBUG,
8464                                 "Hash function already set to Toeplitz");
8465                         goto out;
8466                 }
8467                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8468         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8469                 /* Simple XOR */
8470                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8471                         PMD_DRV_LOG(DEBUG,
8472                                 "Hash function already set to Simple XOR");
8473                         goto out;
8474                 }
8475                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8476         } else
8477                 /* Use the default, and keep it as it is */
8478                 goto out;
8479
8480         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8481         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8482
8483 out:
8484         I40E_WRITE_FLUSH(hw);
8485
8486         return 0;
8487 }
8488
8489 /**
8490  * Valid input sets for hash and flow director filters per PCTYPE
8491  */
8492 static uint64_t
8493 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8494                 enum rte_filter_type filter)
8495 {
8496         uint64_t valid;
8497
8498         static const uint64_t valid_hash_inset_table[] = {
8499                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8500                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8501                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8502                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8503                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8504                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8505                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8506                         I40E_INSET_FLEX_PAYLOAD,
8507                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8508                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8509                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8510                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8511                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8512                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8513                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8514                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8515                         I40E_INSET_FLEX_PAYLOAD,
8516                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8517                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8518                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8519                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8520                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8521                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8522                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8523                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8524                         I40E_INSET_FLEX_PAYLOAD,
8525                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8526                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8527                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8528                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8529                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8530                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8531                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8532                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8533                         I40E_INSET_FLEX_PAYLOAD,
8534                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8535                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8536                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8537                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8538                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8539                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8540                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8541                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8542                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8543                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8544                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8545                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8546                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8547                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8548                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8549                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8550                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8551                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8552                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8553                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8554                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8555                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8556                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8557                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8558                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8559                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8560                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8561                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8562                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8563                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8564                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8565                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8566                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8567                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8568                         I40E_INSET_FLEX_PAYLOAD,
8569                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8570                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8571                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8572                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8573                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8574                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8575                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8576                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8577                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8578                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8579                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8580                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8581                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8582                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8583                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8584                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8585                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8586                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8587                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8588                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8589                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8590                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8591                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8592                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8593                         I40E_INSET_FLEX_PAYLOAD,
8594                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8595                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8596                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8597                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8598                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8599                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8600                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8601                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8602                         I40E_INSET_FLEX_PAYLOAD,
8603                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8604                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8605                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8606                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8607                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8608                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8609                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8610                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8611                         I40E_INSET_FLEX_PAYLOAD,
8612                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8613                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8614                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8615                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8616                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8617                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8618                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8619                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8620                         I40E_INSET_FLEX_PAYLOAD,
8621                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8622                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8623                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8624                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8625                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8626                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8627                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8628                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8629                         I40E_INSET_FLEX_PAYLOAD,
8630                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8631                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8632                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8633                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8634                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8635                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8636                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8637                         I40E_INSET_FLEX_PAYLOAD,
8638                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8639                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8640                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8641                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8642                         I40E_INSET_FLEX_PAYLOAD,
8643         };
8644
8645         /**
8646          * Flow director supports only fields defined in
8647          * union rte_eth_fdir_flow.
8648          */
8649         static const uint64_t valid_fdir_inset_table[] = {
8650                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8651                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8652                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8653                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8654                 I40E_INSET_IPV4_TTL,
8655                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8656                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8657                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8658                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8659                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8660                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8661                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8662                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8663                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8664                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8665                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8666                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8667                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8668                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8669                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8670                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8671                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8672                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8673                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8674                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8675                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8676                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8677                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8678                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8679                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8680                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8681                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8682                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8683                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8684                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8685                 I40E_INSET_SCTP_VT,
8686                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8687                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8688                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8689                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8690                 I40E_INSET_IPV4_TTL,
8691                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8692                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8693                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8694                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8695                 I40E_INSET_IPV6_HOP_LIMIT,
8696                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8697                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8698                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8699                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8700                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8701                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8702                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8703                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8704                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8705                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8706                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8707                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8708                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8709                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8710                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8711                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8712                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8713                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8714                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8715                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8716                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8717                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8718                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8719                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8720                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8721                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8722                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8723                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8724                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8725                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8726                 I40E_INSET_SCTP_VT,
8727                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8728                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8729                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8730                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8731                 I40E_INSET_IPV6_HOP_LIMIT,
8732                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8733                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8734                 I40E_INSET_LAST_ETHER_TYPE,
8735         };
8736
8737         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8738                 return 0;
8739         if (filter == RTE_ETH_FILTER_HASH)
8740                 valid = valid_hash_inset_table[pctype];
8741         else
8742                 valid = valid_fdir_inset_table[pctype];
8743
8744         return valid;
8745 }
8746
8747 /**
8748  * Validate if the input set is allowed for a specific PCTYPE
8749  */
8750 int
8751 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8752                 enum rte_filter_type filter, uint64_t inset)
8753 {
8754         uint64_t valid;
8755
8756         valid = i40e_get_valid_input_set(pctype, filter);
8757         if (inset & (~valid))
8758                 return -EINVAL;
8759
8760         return 0;
8761 }
8762
8763 /* default input set fields combination per pctype */
8764 uint64_t
8765 i40e_get_default_input_set(uint16_t pctype)
8766 {
8767         static const uint64_t default_inset_table[] = {
8768                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8769                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8770                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8771                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8772                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8773                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8774                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8775                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8776                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8777                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8779                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8780                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8782                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8783                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8784                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8785                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8786                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8787                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8788                         I40E_INSET_SCTP_VT,
8789                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8790                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8791                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8792                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8793                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8794                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8795                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8796                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8797                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8798                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8799                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8800                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8801                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8802                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8803                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8804                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8805                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8806                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8807                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8808                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8809                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8810                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8811                         I40E_INSET_SCTP_VT,
8812                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8813                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8814                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8815                         I40E_INSET_LAST_ETHER_TYPE,
8816         };
8817
8818         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8819                 return 0;
8820
8821         return default_inset_table[pctype];
8822 }
8823
8824 /**
8825  * Parse the input set from index to logical bit masks
8826  */
8827 static int
8828 i40e_parse_input_set(uint64_t *inset,
8829                      enum i40e_filter_pctype pctype,
8830                      enum rte_eth_input_set_field *field,
8831                      uint16_t size)
8832 {
8833         uint16_t i, j;
8834         int ret = -EINVAL;
8835
8836         static const struct {
8837                 enum rte_eth_input_set_field field;
8838                 uint64_t inset;
8839         } inset_convert_table[] = {
8840                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8841                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8842                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8843                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8844                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8845                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8846                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8847                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8848                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8849                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8850                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8851                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8852                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8853                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8854                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8855                         I40E_INSET_IPV6_NEXT_HDR},
8856                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8857                         I40E_INSET_IPV6_HOP_LIMIT},
8858                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8859                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8860                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8861                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8862                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8863                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8864                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8865                         I40E_INSET_SCTP_VT},
8866                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8867                         I40E_INSET_TUNNEL_DMAC},
8868                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8869                         I40E_INSET_VLAN_TUNNEL},
8870                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8871                         I40E_INSET_TUNNEL_ID},
8872                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8873                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8874                         I40E_INSET_FLEX_PAYLOAD_W1},
8875                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8876                         I40E_INSET_FLEX_PAYLOAD_W2},
8877                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8878                         I40E_INSET_FLEX_PAYLOAD_W3},
8879                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8880                         I40E_INSET_FLEX_PAYLOAD_W4},
8881                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8882                         I40E_INSET_FLEX_PAYLOAD_W5},
8883                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8884                         I40E_INSET_FLEX_PAYLOAD_W6},
8885                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8886                         I40E_INSET_FLEX_PAYLOAD_W7},
8887                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8888                         I40E_INSET_FLEX_PAYLOAD_W8},
8889         };
8890
8891         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8892                 return ret;
8893
8894         /* Only one item allowed for default or all */
8895         if (size == 1) {
8896                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8897                         *inset = i40e_get_default_input_set(pctype);
8898                         return 0;
8899                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8900                         *inset = I40E_INSET_NONE;
8901                         return 0;
8902                 }
8903         }
8904
8905         for (i = 0, *inset = 0; i < size; i++) {
8906                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8907                         if (field[i] == inset_convert_table[j].field) {
8908                                 *inset |= inset_convert_table[j].inset;
8909                                 break;
8910                         }
8911                 }
8912
8913                 /* It contains unsupported input set, return immediately */
8914                 if (j == RTE_DIM(inset_convert_table))
8915                         return ret;
8916         }
8917
8918         return 0;
8919 }
8920
8921 /**
8922  * Translate the input set from bit masks to register aware bit masks
8923  * and vice versa
8924  */
8925 uint64_t
8926 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8927 {
8928         uint64_t val = 0;
8929         uint16_t i;
8930
8931         struct inset_map {
8932                 uint64_t inset;
8933                 uint64_t inset_reg;
8934         };
8935
8936         static const struct inset_map inset_map_common[] = {
8937                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8938                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8939                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8940                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8941                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8942                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8943                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8944                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8945                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8946                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8947                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8948                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8949                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8950                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8951                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8952                 {I40E_INSET_TUNNEL_DMAC,
8953                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8954                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8955                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8956                 {I40E_INSET_TUNNEL_SRC_PORT,
8957                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8958                 {I40E_INSET_TUNNEL_DST_PORT,
8959                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8960                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8961                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8962                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8963                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8964                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8965                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8966                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8967                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8968                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8969         };
8970
8971     /* some different registers map in x722*/
8972         static const struct inset_map inset_map_diff_x722[] = {
8973                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8974                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8975                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8976                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8977         };
8978
8979         static const struct inset_map inset_map_diff_not_x722[] = {
8980                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8981                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8982                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8983                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8984         };
8985
8986         if (input == 0)
8987                 return val;
8988
8989         /* Translate input set to register aware inset */
8990         if (type == I40E_MAC_X722) {
8991                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8992                         if (input & inset_map_diff_x722[i].inset)
8993                                 val |= inset_map_diff_x722[i].inset_reg;
8994                 }
8995         } else {
8996                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8997                         if (input & inset_map_diff_not_x722[i].inset)
8998                                 val |= inset_map_diff_not_x722[i].inset_reg;
8999                 }
9000         }
9001
9002         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9003                 if (input & inset_map_common[i].inset)
9004                         val |= inset_map_common[i].inset_reg;
9005         }
9006
9007         return val;
9008 }
9009
9010 int
9011 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9012 {
9013         uint8_t i, idx = 0;
9014         uint64_t inset_need_mask = inset;
9015
9016         static const struct {
9017                 uint64_t inset;
9018                 uint32_t mask;
9019         } inset_mask_map[] = {
9020                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9021                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9022                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9023                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9024                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9025                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9026                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9027                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9028         };
9029
9030         if (!inset || !mask || !nb_elem)
9031                 return 0;
9032
9033         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9034                 /* Clear the inset bit, if no MASK is required,
9035                  * for example proto + ttl
9036                  */
9037                 if ((inset & inset_mask_map[i].inset) ==
9038                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9039                         inset_need_mask &= ~inset_mask_map[i].inset;
9040                 if (!inset_need_mask)
9041                         return 0;
9042         }
9043         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9044                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9045                     inset_mask_map[i].inset) {
9046                         if (idx >= nb_elem) {
9047                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9048                                 return -EINVAL;
9049                         }
9050                         mask[idx] = inset_mask_map[i].mask;
9051                         idx++;
9052                 }
9053         }
9054
9055         return idx;
9056 }
9057
9058 void
9059 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9060 {
9061         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9062
9063         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9064         if (reg != val)
9065                 i40e_write_rx_ctl(hw, addr, val);
9066         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9067                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9068 }
9069
9070 void
9071 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9072 {
9073         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9074
9075         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9076         if (reg != val)
9077                 i40e_write_global_rx_ctl(hw, addr, val);
9078         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9079                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9080 }
9081
9082 static void
9083 i40e_filter_input_set_init(struct i40e_pf *pf)
9084 {
9085         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9086         enum i40e_filter_pctype pctype;
9087         uint64_t input_set, inset_reg;
9088         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9089         int num, i;
9090         uint16_t flow_type;
9091
9092         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9093              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9094                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9095
9096                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9097                         continue;
9098
9099                 input_set = i40e_get_default_input_set(pctype);
9100
9101                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9102                                                    I40E_INSET_MASK_NUM_REG);
9103                 if (num < 0)
9104                         return;
9105                 if (pf->support_multi_driver && num > 0) {
9106                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9107                         return;
9108                 }
9109                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9110                                         input_set);
9111
9112                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9113                                       (uint32_t)(inset_reg & UINT32_MAX));
9114                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9115                                      (uint32_t)((inset_reg >>
9116                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9117                 if (!pf->support_multi_driver) {
9118                         i40e_check_write_global_reg(hw,
9119                                             I40E_GLQF_HASH_INSET(0, pctype),
9120                                             (uint32_t)(inset_reg & UINT32_MAX));
9121                         i40e_check_write_global_reg(hw,
9122                                              I40E_GLQF_HASH_INSET(1, pctype),
9123                                              (uint32_t)((inset_reg >>
9124                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9125
9126                         for (i = 0; i < num; i++) {
9127                                 i40e_check_write_global_reg(hw,
9128                                                     I40E_GLQF_FD_MSK(i, pctype),
9129                                                     mask_reg[i]);
9130                                 i40e_check_write_global_reg(hw,
9131                                                   I40E_GLQF_HASH_MSK(i, pctype),
9132                                                   mask_reg[i]);
9133                         }
9134                         /*clear unused mask registers of the pctype */
9135                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9136                                 i40e_check_write_global_reg(hw,
9137                                                     I40E_GLQF_FD_MSK(i, pctype),
9138                                                     0);
9139                                 i40e_check_write_global_reg(hw,
9140                                                   I40E_GLQF_HASH_MSK(i, pctype),
9141                                                   0);
9142                         }
9143                 } else {
9144                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9145                 }
9146                 I40E_WRITE_FLUSH(hw);
9147
9148                 /* store the default input set */
9149                 if (!pf->support_multi_driver)
9150                         pf->hash_input_set[pctype] = input_set;
9151                 pf->fdir.input_set[pctype] = input_set;
9152         }
9153
9154         if (!pf->support_multi_driver) {
9155                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9156                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9157                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9158         }
9159 }
9160
9161 int
9162 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9163                          struct rte_eth_input_set_conf *conf)
9164 {
9165         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9166         enum i40e_filter_pctype pctype;
9167         uint64_t input_set, inset_reg = 0;
9168         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9169         int ret, i, num;
9170
9171         if (!conf) {
9172                 PMD_DRV_LOG(ERR, "Invalid pointer");
9173                 return -EFAULT;
9174         }
9175         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9176             conf->op != RTE_ETH_INPUT_SET_ADD) {
9177                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9178                 return -EINVAL;
9179         }
9180
9181         if (pf->support_multi_driver) {
9182                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9183                 return -ENOTSUP;
9184         }
9185
9186         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9187         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9188                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9189                 return -EINVAL;
9190         }
9191
9192         if (hw->mac.type == I40E_MAC_X722) {
9193                 /* get translated pctype value in fd pctype register */
9194                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9195                         I40E_GLQF_FD_PCTYPES((int)pctype));
9196         }
9197
9198         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9199                                    conf->inset_size);
9200         if (ret) {
9201                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9202                 return -EINVAL;
9203         }
9204
9205         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9206                 /* get inset value in register */
9207                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9208                 inset_reg <<= I40E_32_BIT_WIDTH;
9209                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9210                 input_set |= pf->hash_input_set[pctype];
9211         }
9212         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9213                                            I40E_INSET_MASK_NUM_REG);
9214         if (num < 0)
9215                 return -EINVAL;
9216
9217         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9218
9219         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9220                                     (uint32_t)(inset_reg & UINT32_MAX));
9221         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9222                                     (uint32_t)((inset_reg >>
9223                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9224         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9225
9226         for (i = 0; i < num; i++)
9227                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9228                                             mask_reg[i]);
9229         /*clear unused mask registers of the pctype */
9230         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9231                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9232                                             0);
9233         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9234         I40E_WRITE_FLUSH(hw);
9235
9236         pf->hash_input_set[pctype] = input_set;
9237         return 0;
9238 }
9239
9240 int
9241 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9242                          struct rte_eth_input_set_conf *conf)
9243 {
9244         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9245         enum i40e_filter_pctype pctype;
9246         uint64_t input_set, inset_reg = 0;
9247         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9248         int ret, i, num;
9249
9250         if (!hw || !conf) {
9251                 PMD_DRV_LOG(ERR, "Invalid pointer");
9252                 return -EFAULT;
9253         }
9254         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9255             conf->op != RTE_ETH_INPUT_SET_ADD) {
9256                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9257                 return -EINVAL;
9258         }
9259
9260         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9261
9262         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9263                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9264                 return -EINVAL;
9265         }
9266
9267         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9268                                    conf->inset_size);
9269         if (ret) {
9270                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9271                 return -EINVAL;
9272         }
9273
9274         /* get inset value in register */
9275         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9276         inset_reg <<= I40E_32_BIT_WIDTH;
9277         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9278
9279         /* Can not change the inset reg for flex payload for fdir,
9280          * it is done by writing I40E_PRTQF_FD_FLXINSET
9281          * in i40e_set_flex_mask_on_pctype.
9282          */
9283         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9284                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9285         else
9286                 input_set |= pf->fdir.input_set[pctype];
9287         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9288                                            I40E_INSET_MASK_NUM_REG);
9289         if (num < 0)
9290                 return -EINVAL;
9291         if (pf->support_multi_driver && num > 0) {
9292                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9293                 return -ENOTSUP;
9294         }
9295
9296         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9297
9298         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9299                               (uint32_t)(inset_reg & UINT32_MAX));
9300         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9301                              (uint32_t)((inset_reg >>
9302                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9303
9304         if (!pf->support_multi_driver) {
9305                 for (i = 0; i < num; i++)
9306                         i40e_check_write_global_reg(hw,
9307                                                     I40E_GLQF_FD_MSK(i, pctype),
9308                                                     mask_reg[i]);
9309                 /*clear unused mask registers of the pctype */
9310                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9311                         i40e_check_write_global_reg(hw,
9312                                                     I40E_GLQF_FD_MSK(i, pctype),
9313                                                     0);
9314                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9315         } else {
9316                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9317         }
9318         I40E_WRITE_FLUSH(hw);
9319
9320         pf->fdir.input_set[pctype] = input_set;
9321         return 0;
9322 }
9323
9324 static int
9325 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9326 {
9327         int ret = 0;
9328
9329         if (!hw || !info) {
9330                 PMD_DRV_LOG(ERR, "Invalid pointer");
9331                 return -EFAULT;
9332         }
9333
9334         switch (info->info_type) {
9335         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9336                 i40e_get_symmetric_hash_enable_per_port(hw,
9337                                         &(info->info.enable));
9338                 break;
9339         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9340                 ret = i40e_get_hash_filter_global_config(hw,
9341                                 &(info->info.global_conf));
9342                 break;
9343         default:
9344                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9345                                                         info->info_type);
9346                 ret = -EINVAL;
9347                 break;
9348         }
9349
9350         return ret;
9351 }
9352
9353 static int
9354 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9355 {
9356         int ret = 0;
9357
9358         if (!hw || !info) {
9359                 PMD_DRV_LOG(ERR, "Invalid pointer");
9360                 return -EFAULT;
9361         }
9362
9363         switch (info->info_type) {
9364         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9365                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9366                 break;
9367         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9368                 ret = i40e_set_hash_filter_global_config(hw,
9369                                 &(info->info.global_conf));
9370                 break;
9371         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9372                 ret = i40e_hash_filter_inset_select(hw,
9373                                                &(info->info.input_set_conf));
9374                 break;
9375
9376         default:
9377                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9378                                                         info->info_type);
9379                 ret = -EINVAL;
9380                 break;
9381         }
9382
9383         return ret;
9384 }
9385
9386 /* Operations for hash function */
9387 static int
9388 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9389                       enum rte_filter_op filter_op,
9390                       void *arg)
9391 {
9392         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9393         int ret = 0;
9394
9395         switch (filter_op) {
9396         case RTE_ETH_FILTER_NOP:
9397                 break;
9398         case RTE_ETH_FILTER_GET:
9399                 ret = i40e_hash_filter_get(hw,
9400                         (struct rte_eth_hash_filter_info *)arg);
9401                 break;
9402         case RTE_ETH_FILTER_SET:
9403                 ret = i40e_hash_filter_set(hw,
9404                         (struct rte_eth_hash_filter_info *)arg);
9405                 break;
9406         default:
9407                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9408                                                                 filter_op);
9409                 ret = -ENOTSUP;
9410                 break;
9411         }
9412
9413         return ret;
9414 }
9415
9416 /* Convert ethertype filter structure */
9417 static int
9418 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9419                               struct i40e_ethertype_filter *filter)
9420 {
9421         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9422         filter->input.ether_type = input->ether_type;
9423         filter->flags = input->flags;
9424         filter->queue = input->queue;
9425
9426         return 0;
9427 }
9428
9429 /* Check if there exists the ehtertype filter */
9430 struct i40e_ethertype_filter *
9431 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9432                                 const struct i40e_ethertype_filter_input *input)
9433 {
9434         int ret;
9435
9436         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9437         if (ret < 0)
9438                 return NULL;
9439
9440         return ethertype_rule->hash_map[ret];
9441 }
9442
9443 /* Add ethertype filter in SW list */
9444 static int
9445 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9446                                 struct i40e_ethertype_filter *filter)
9447 {
9448         struct i40e_ethertype_rule *rule = &pf->ethertype;
9449         int ret;
9450
9451         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9452         if (ret < 0) {
9453                 PMD_DRV_LOG(ERR,
9454                             "Failed to insert ethertype filter"
9455                             " to hash table %d!",
9456                             ret);
9457                 return ret;
9458         }
9459         rule->hash_map[ret] = filter;
9460
9461         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9462
9463         return 0;
9464 }
9465
9466 /* Delete ethertype filter in SW list */
9467 int
9468 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9469                              struct i40e_ethertype_filter_input *input)
9470 {
9471         struct i40e_ethertype_rule *rule = &pf->ethertype;
9472         struct i40e_ethertype_filter *filter;
9473         int ret;
9474
9475         ret = rte_hash_del_key(rule->hash_table, input);
9476         if (ret < 0) {
9477                 PMD_DRV_LOG(ERR,
9478                             "Failed to delete ethertype filter"
9479                             " to hash table %d!",
9480                             ret);
9481                 return ret;
9482         }
9483         filter = rule->hash_map[ret];
9484         rule->hash_map[ret] = NULL;
9485
9486         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9487         rte_free(filter);
9488
9489         return 0;
9490 }
9491
9492 /*
9493  * Configure ethertype filter, which can director packet by filtering
9494  * with mac address and ether_type or only ether_type
9495  */
9496 int
9497 i40e_ethertype_filter_set(struct i40e_pf *pf,
9498                         struct rte_eth_ethertype_filter *filter,
9499                         bool add)
9500 {
9501         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9502         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9503         struct i40e_ethertype_filter *ethertype_filter, *node;
9504         struct i40e_ethertype_filter check_filter;
9505         struct i40e_control_filter_stats stats;
9506         uint16_t flags = 0;
9507         int ret;
9508
9509         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9510                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9511                 return -EINVAL;
9512         }
9513         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9514                 filter->ether_type == ETHER_TYPE_IPv6) {
9515                 PMD_DRV_LOG(ERR,
9516                         "unsupported ether_type(0x%04x) in control packet filter.",
9517                         filter->ether_type);
9518                 return -EINVAL;
9519         }
9520         if (filter->ether_type == ETHER_TYPE_VLAN)
9521                 PMD_DRV_LOG(WARNING,
9522                         "filter vlan ether_type in first tag is not supported.");
9523
9524         /* Check if there is the filter in SW list */
9525         memset(&check_filter, 0, sizeof(check_filter));
9526         i40e_ethertype_filter_convert(filter, &check_filter);
9527         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9528                                                &check_filter.input);
9529         if (add && node) {
9530                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9531                 return -EINVAL;
9532         }
9533
9534         if (!add && !node) {
9535                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9536                 return -EINVAL;
9537         }
9538
9539         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9540                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9541         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9542                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9543         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9544
9545         memset(&stats, 0, sizeof(stats));
9546         ret = i40e_aq_add_rem_control_packet_filter(hw,
9547                         filter->mac_addr.addr_bytes,
9548                         filter->ether_type, flags,
9549                         pf->main_vsi->seid,
9550                         filter->queue, add, &stats, NULL);
9551
9552         PMD_DRV_LOG(INFO,
9553                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9554                 ret, stats.mac_etype_used, stats.etype_used,
9555                 stats.mac_etype_free, stats.etype_free);
9556         if (ret < 0)
9557                 return -ENOSYS;
9558
9559         /* Add or delete a filter in SW list */
9560         if (add) {
9561                 ethertype_filter = rte_zmalloc("ethertype_filter",
9562                                        sizeof(*ethertype_filter), 0);
9563                 if (ethertype_filter == NULL) {
9564                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9565                         return -ENOMEM;
9566                 }
9567
9568                 rte_memcpy(ethertype_filter, &check_filter,
9569                            sizeof(check_filter));
9570                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9571                 if (ret < 0)
9572                         rte_free(ethertype_filter);
9573         } else {
9574                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9575         }
9576
9577         return ret;
9578 }
9579
9580 /*
9581  * Handle operations for ethertype filter.
9582  */
9583 static int
9584 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9585                                 enum rte_filter_op filter_op,
9586                                 void *arg)
9587 {
9588         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9589         int ret = 0;
9590
9591         if (filter_op == RTE_ETH_FILTER_NOP)
9592                 return ret;
9593
9594         if (arg == NULL) {
9595                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9596                             filter_op);
9597                 return -EINVAL;
9598         }
9599
9600         switch (filter_op) {
9601         case RTE_ETH_FILTER_ADD:
9602                 ret = i40e_ethertype_filter_set(pf,
9603                         (struct rte_eth_ethertype_filter *)arg,
9604                         TRUE);
9605                 break;
9606         case RTE_ETH_FILTER_DELETE:
9607                 ret = i40e_ethertype_filter_set(pf,
9608                         (struct rte_eth_ethertype_filter *)arg,
9609                         FALSE);
9610                 break;
9611         default:
9612                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9613                 ret = -ENOSYS;
9614                 break;
9615         }
9616         return ret;
9617 }
9618
9619 static int
9620 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9621                      enum rte_filter_type filter_type,
9622                      enum rte_filter_op filter_op,
9623                      void *arg)
9624 {
9625         int ret = 0;
9626
9627         if (dev == NULL)
9628                 return -EINVAL;
9629
9630         switch (filter_type) {
9631         case RTE_ETH_FILTER_NONE:
9632                 /* For global configuration */
9633                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9634                 break;
9635         case RTE_ETH_FILTER_HASH:
9636                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9637                 break;
9638         case RTE_ETH_FILTER_MACVLAN:
9639                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9640                 break;
9641         case RTE_ETH_FILTER_ETHERTYPE:
9642                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9643                 break;
9644         case RTE_ETH_FILTER_TUNNEL:
9645                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9646                 break;
9647         case RTE_ETH_FILTER_FDIR:
9648                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9649                 break;
9650         case RTE_ETH_FILTER_GENERIC:
9651                 if (filter_op != RTE_ETH_FILTER_GET)
9652                         return -EINVAL;
9653                 *(const void **)arg = &i40e_flow_ops;
9654                 break;
9655         default:
9656                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9657                                                         filter_type);
9658                 ret = -EINVAL;
9659                 break;
9660         }
9661
9662         return ret;
9663 }
9664
9665 /*
9666  * Check and enable Extended Tag.
9667  * Enabling Extended Tag is important for 40G performance.
9668  */
9669 static void
9670 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9671 {
9672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9673         uint32_t buf = 0;
9674         int ret;
9675
9676         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9677                                       PCI_DEV_CAP_REG);
9678         if (ret < 0) {
9679                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9680                             PCI_DEV_CAP_REG);
9681                 return;
9682         }
9683         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9684                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9685                 return;
9686         }
9687
9688         buf = 0;
9689         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9690                                       PCI_DEV_CTRL_REG);
9691         if (ret < 0) {
9692                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9693                             PCI_DEV_CTRL_REG);
9694                 return;
9695         }
9696         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9697                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9698                 return;
9699         }
9700         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9701         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9702                                        PCI_DEV_CTRL_REG);
9703         if (ret < 0) {
9704                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9705                             PCI_DEV_CTRL_REG);
9706                 return;
9707         }
9708 }
9709
9710 /*
9711  * As some registers wouldn't be reset unless a global hardware reset,
9712  * hardware initialization is needed to put those registers into an
9713  * expected initial state.
9714  */
9715 static void
9716 i40e_hw_init(struct rte_eth_dev *dev)
9717 {
9718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9719
9720         i40e_enable_extended_tag(dev);
9721
9722         /* clear the PF Queue Filter control register */
9723         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9724
9725         /* Disable symmetric hash per port */
9726         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9727 }
9728
9729 /*
9730  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9731  * however this function will return only one highest pctype index,
9732  * which is not quite correct. This is known problem of i40e driver
9733  * and needs to be fixed later.
9734  */
9735 enum i40e_filter_pctype
9736 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9737 {
9738         int i;
9739         uint64_t pctype_mask;
9740
9741         if (flow_type < I40E_FLOW_TYPE_MAX) {
9742                 pctype_mask = adapter->pctypes_tbl[flow_type];
9743                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9744                         if (pctype_mask & (1ULL << i))
9745                                 return (enum i40e_filter_pctype)i;
9746                 }
9747         }
9748         return I40E_FILTER_PCTYPE_INVALID;
9749 }
9750
9751 uint16_t
9752 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9753                         enum i40e_filter_pctype pctype)
9754 {
9755         uint16_t flowtype;
9756         uint64_t pctype_mask = 1ULL << pctype;
9757
9758         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9759              flowtype++) {
9760                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9761                         return flowtype;
9762         }
9763
9764         return RTE_ETH_FLOW_UNKNOWN;
9765 }
9766
9767 /*
9768  * On X710, performance number is far from the expectation on recent firmware
9769  * versions; on XL710, performance number is also far from the expectation on
9770  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9771  * mode is enabled and port MAC address is equal to the packet destination MAC
9772  * address. The fix for this issue may not be integrated in the following
9773  * firmware version. So the workaround in software driver is needed. It needs
9774  * to modify the initial values of 3 internal only registers for both X710 and
9775  * XL710. Note that the values for X710 or XL710 could be different, and the
9776  * workaround can be removed when it is fixed in firmware in the future.
9777  */
9778
9779 /* For both X710 and XL710 */
9780 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9781 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9782 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9783
9784 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9785 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9786
9787 /* For X722 */
9788 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9789 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9790
9791 /* For X710 */
9792 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9793 /* For XL710 */
9794 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9795 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9796
9797 /*
9798  * GL_SWR_PM_UP_THR:
9799  * The value is not impacted from the link speed, its value is set according
9800  * to the total number of ports for a better pipe-monitor configuration.
9801  */
9802 static bool
9803 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
9804 {
9805 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
9806                 .device_id = (dev),   \
9807                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
9808
9809 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
9810                 .device_id = (dev),   \
9811                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
9812
9813         static const struct {
9814                 uint16_t device_id;
9815                 uint32_t val;
9816         } swr_pm_table[] = {
9817                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
9818                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
9819                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
9820                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
9821
9822                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
9823                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
9824                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
9825                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
9826                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
9827                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
9828                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
9829         };
9830         uint32_t i;
9831
9832         if (value == NULL) {
9833                 PMD_DRV_LOG(ERR, "value is NULL");
9834                 return false;
9835         }
9836
9837         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
9838                 if (hw->device_id == swr_pm_table[i].device_id) {
9839                         *value = swr_pm_table[i].val;
9840
9841                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
9842                                     "value - 0x%08x",
9843                                     hw->device_id, *value);
9844                         return true;
9845                 }
9846         }
9847
9848         return false;
9849 }
9850
9851 static int
9852 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9853 {
9854         enum i40e_status_code status;
9855         struct i40e_aq_get_phy_abilities_resp phy_ab;
9856         int ret = -ENOTSUP;
9857         int retries = 0;
9858
9859         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9860                                               NULL);
9861
9862         while (status) {
9863                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9864                         status);
9865                 retries++;
9866                 rte_delay_us(100000);
9867                 if  (retries < 5)
9868                         status = i40e_aq_get_phy_capabilities(hw, false,
9869                                         true, &phy_ab, NULL);
9870                 else
9871                         return ret;
9872         }
9873         return 0;
9874 }
9875
9876 static void
9877 i40e_configure_registers(struct i40e_hw *hw)
9878 {
9879         static struct {
9880                 uint32_t addr;
9881                 uint64_t val;
9882         } reg_table[] = {
9883                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9884                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9885                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9886         };
9887         uint64_t reg;
9888         uint32_t i;
9889         int ret;
9890
9891         for (i = 0; i < RTE_DIM(reg_table); i++) {
9892                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9893                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9894                                 reg_table[i].val =
9895                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9896                         else /* For X710/XL710/XXV710 */
9897                                 if (hw->aq.fw_maj_ver < 6)
9898                                         reg_table[i].val =
9899                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9900                                 else
9901                                         reg_table[i].val =
9902                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9903                 }
9904
9905                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9906                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9907                                 reg_table[i].val =
9908                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9909                         else /* For X710/XL710/XXV710 */
9910                                 reg_table[i].val =
9911                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9912                 }
9913
9914                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9915                         uint32_t cfg_val;
9916
9917                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
9918                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
9919                                             "GL_SWR_PM_UP_THR value fixup",
9920                                             hw->device_id);
9921                                 continue;
9922                         }
9923
9924                         reg_table[i].val = cfg_val;
9925                 }
9926
9927                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9928                                                         &reg, NULL);
9929                 if (ret < 0) {
9930                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9931                                                         reg_table[i].addr);
9932                         break;
9933                 }
9934                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9935                                                 reg_table[i].addr, reg);
9936                 if (reg == reg_table[i].val)
9937                         continue;
9938
9939                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9940                                                 reg_table[i].val, NULL);
9941                 if (ret < 0) {
9942                         PMD_DRV_LOG(ERR,
9943                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9944                                 reg_table[i].val, reg_table[i].addr);
9945                         break;
9946                 }
9947                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9948                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9949         }
9950 }
9951
9952 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9953 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9954 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9955 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9956 static int
9957 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9958 {
9959         uint32_t reg;
9960         int ret;
9961
9962         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9963                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9964                 return -EINVAL;
9965         }
9966
9967         /* Configure for double VLAN RX stripping */
9968         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9969         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9970                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9971                 ret = i40e_aq_debug_write_register(hw,
9972                                                    I40E_VSI_TSR(vsi->vsi_id),
9973                                                    reg, NULL);
9974                 if (ret < 0) {
9975                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9976                                     vsi->vsi_id);
9977                         return I40E_ERR_CONFIG;
9978                 }
9979         }
9980
9981         /* Configure for double VLAN TX insertion */
9982         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9983         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9984                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9985                 ret = i40e_aq_debug_write_register(hw,
9986                                                    I40E_VSI_L2TAGSTXVALID(
9987                                                    vsi->vsi_id), reg, NULL);
9988                 if (ret < 0) {
9989                         PMD_DRV_LOG(ERR,
9990                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9991                                 vsi->vsi_id);
9992                         return I40E_ERR_CONFIG;
9993                 }
9994         }
9995
9996         return 0;
9997 }
9998
9999 /**
10000  * i40e_aq_add_mirror_rule
10001  * @hw: pointer to the hardware structure
10002  * @seid: VEB seid to add mirror rule to
10003  * @dst_id: destination vsi seid
10004  * @entries: Buffer which contains the entities to be mirrored
10005  * @count: number of entities contained in the buffer
10006  * @rule_id:the rule_id of the rule to be added
10007  *
10008  * Add a mirror rule for a given veb.
10009  *
10010  **/
10011 static enum i40e_status_code
10012 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10013                         uint16_t seid, uint16_t dst_id,
10014                         uint16_t rule_type, uint16_t *entries,
10015                         uint16_t count, uint16_t *rule_id)
10016 {
10017         struct i40e_aq_desc desc;
10018         struct i40e_aqc_add_delete_mirror_rule cmd;
10019         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10020                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10021                 &desc.params.raw;
10022         uint16_t buff_len;
10023         enum i40e_status_code status;
10024
10025         i40e_fill_default_direct_cmd_desc(&desc,
10026                                           i40e_aqc_opc_add_mirror_rule);
10027         memset(&cmd, 0, sizeof(cmd));
10028
10029         buff_len = sizeof(uint16_t) * count;
10030         desc.datalen = rte_cpu_to_le_16(buff_len);
10031         if (buff_len > 0)
10032                 desc.flags |= rte_cpu_to_le_16(
10033                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10034         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10035                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10036         cmd.num_entries = rte_cpu_to_le_16(count);
10037         cmd.seid = rte_cpu_to_le_16(seid);
10038         cmd.destination = rte_cpu_to_le_16(dst_id);
10039
10040         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10041         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10042         PMD_DRV_LOG(INFO,
10043                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10044                 hw->aq.asq_last_status, resp->rule_id,
10045                 resp->mirror_rules_used, resp->mirror_rules_free);
10046         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10047
10048         return status;
10049 }
10050
10051 /**
10052  * i40e_aq_del_mirror_rule
10053  * @hw: pointer to the hardware structure
10054  * @seid: VEB seid to add mirror rule to
10055  * @entries: Buffer which contains the entities to be mirrored
10056  * @count: number of entities contained in the buffer
10057  * @rule_id:the rule_id of the rule to be delete
10058  *
10059  * Delete a mirror rule for a given veb.
10060  *
10061  **/
10062 static enum i40e_status_code
10063 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10064                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10065                 uint16_t count, uint16_t rule_id)
10066 {
10067         struct i40e_aq_desc desc;
10068         struct i40e_aqc_add_delete_mirror_rule cmd;
10069         uint16_t buff_len = 0;
10070         enum i40e_status_code status;
10071         void *buff = NULL;
10072
10073         i40e_fill_default_direct_cmd_desc(&desc,
10074                                           i40e_aqc_opc_delete_mirror_rule);
10075         memset(&cmd, 0, sizeof(cmd));
10076         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10077                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10078                                                           I40E_AQ_FLAG_RD));
10079                 cmd.num_entries = count;
10080                 buff_len = sizeof(uint16_t) * count;
10081                 desc.datalen = rte_cpu_to_le_16(buff_len);
10082                 buff = (void *)entries;
10083         } else
10084                 /* rule id is filled in destination field for deleting mirror rule */
10085                 cmd.destination = rte_cpu_to_le_16(rule_id);
10086
10087         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10088                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10089         cmd.seid = rte_cpu_to_le_16(seid);
10090
10091         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10092         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10093
10094         return status;
10095 }
10096
10097 /**
10098  * i40e_mirror_rule_set
10099  * @dev: pointer to the hardware structure
10100  * @mirror_conf: mirror rule info
10101  * @sw_id: mirror rule's sw_id
10102  * @on: enable/disable
10103  *
10104  * set a mirror rule.
10105  *
10106  **/
10107 static int
10108 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10109                         struct rte_eth_mirror_conf *mirror_conf,
10110                         uint8_t sw_id, uint8_t on)
10111 {
10112         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10113         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10114         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10115         struct i40e_mirror_rule *parent = NULL;
10116         uint16_t seid, dst_seid, rule_id;
10117         uint16_t i, j = 0;
10118         int ret;
10119
10120         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10121
10122         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10123                 PMD_DRV_LOG(ERR,
10124                         "mirror rule can not be configured without veb or vfs.");
10125                 return -ENOSYS;
10126         }
10127         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10128                 PMD_DRV_LOG(ERR, "mirror table is full.");
10129                 return -ENOSPC;
10130         }
10131         if (mirror_conf->dst_pool > pf->vf_num) {
10132                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10133                                  mirror_conf->dst_pool);
10134                 return -EINVAL;
10135         }
10136
10137         seid = pf->main_vsi->veb->seid;
10138
10139         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10140                 if (sw_id <= it->index) {
10141                         mirr_rule = it;
10142                         break;
10143                 }
10144                 parent = it;
10145         }
10146         if (mirr_rule && sw_id == mirr_rule->index) {
10147                 if (on) {
10148                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10149                         return -EEXIST;
10150                 } else {
10151                         ret = i40e_aq_del_mirror_rule(hw, seid,
10152                                         mirr_rule->rule_type,
10153                                         mirr_rule->entries,
10154                                         mirr_rule->num_entries, mirr_rule->id);
10155                         if (ret < 0) {
10156                                 PMD_DRV_LOG(ERR,
10157                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10158                                         ret, hw->aq.asq_last_status);
10159                                 return -ENOSYS;
10160                         }
10161                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10162                         rte_free(mirr_rule);
10163                         pf->nb_mirror_rule--;
10164                         return 0;
10165                 }
10166         } else if (!on) {
10167                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10168                 return -ENOENT;
10169         }
10170
10171         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10172                                 sizeof(struct i40e_mirror_rule) , 0);
10173         if (!mirr_rule) {
10174                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10175                 return I40E_ERR_NO_MEMORY;
10176         }
10177         switch (mirror_conf->rule_type) {
10178         case ETH_MIRROR_VLAN:
10179                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10180                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10181                                 mirr_rule->entries[j] =
10182                                         mirror_conf->vlan.vlan_id[i];
10183                                 j++;
10184                         }
10185                 }
10186                 if (j == 0) {
10187                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10188                         rte_free(mirr_rule);
10189                         return -EINVAL;
10190                 }
10191                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10192                 break;
10193         case ETH_MIRROR_VIRTUAL_POOL_UP:
10194         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10195                 /* check if the specified pool bit is out of range */
10196                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10197                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10198                         rte_free(mirr_rule);
10199                         return -EINVAL;
10200                 }
10201                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10202                         if (mirror_conf->pool_mask & (1ULL << i)) {
10203                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10204                                 j++;
10205                         }
10206                 }
10207                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10208                         /* add pf vsi to entries */
10209                         mirr_rule->entries[j] = pf->main_vsi_seid;
10210                         j++;
10211                 }
10212                 if (j == 0) {
10213                         PMD_DRV_LOG(ERR, "pool is not specified.");
10214                         rte_free(mirr_rule);
10215                         return -EINVAL;
10216                 }
10217                 /* egress and ingress in aq commands means from switch but not port */
10218                 mirr_rule->rule_type =
10219                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10220                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10221                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10222                 break;
10223         case ETH_MIRROR_UPLINK_PORT:
10224                 /* egress and ingress in aq commands means from switch but not port*/
10225                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10226                 break;
10227         case ETH_MIRROR_DOWNLINK_PORT:
10228                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10229                 break;
10230         default:
10231                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10232                         mirror_conf->rule_type);
10233                 rte_free(mirr_rule);
10234                 return -EINVAL;
10235         }
10236
10237         /* If the dst_pool is equal to vf_num, consider it as PF */
10238         if (mirror_conf->dst_pool == pf->vf_num)
10239                 dst_seid = pf->main_vsi_seid;
10240         else
10241                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10242
10243         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10244                                       mirr_rule->rule_type, mirr_rule->entries,
10245                                       j, &rule_id);
10246         if (ret < 0) {
10247                 PMD_DRV_LOG(ERR,
10248                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10249                         ret, hw->aq.asq_last_status);
10250                 rte_free(mirr_rule);
10251                 return -ENOSYS;
10252         }
10253
10254         mirr_rule->index = sw_id;
10255         mirr_rule->num_entries = j;
10256         mirr_rule->id = rule_id;
10257         mirr_rule->dst_vsi_seid = dst_seid;
10258
10259         if (parent)
10260                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10261         else
10262                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10263
10264         pf->nb_mirror_rule++;
10265         return 0;
10266 }
10267
10268 /**
10269  * i40e_mirror_rule_reset
10270  * @dev: pointer to the device
10271  * @sw_id: mirror rule's sw_id
10272  *
10273  * reset a mirror rule.
10274  *
10275  **/
10276 static int
10277 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10278 {
10279         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10280         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10281         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10282         uint16_t seid;
10283         int ret;
10284
10285         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10286
10287         seid = pf->main_vsi->veb->seid;
10288
10289         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10290                 if (sw_id == it->index) {
10291                         mirr_rule = it;
10292                         break;
10293                 }
10294         }
10295         if (mirr_rule) {
10296                 ret = i40e_aq_del_mirror_rule(hw, seid,
10297                                 mirr_rule->rule_type,
10298                                 mirr_rule->entries,
10299                                 mirr_rule->num_entries, mirr_rule->id);
10300                 if (ret < 0) {
10301                         PMD_DRV_LOG(ERR,
10302                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10303                                 ret, hw->aq.asq_last_status);
10304                         return -ENOSYS;
10305                 }
10306                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10307                 rte_free(mirr_rule);
10308                 pf->nb_mirror_rule--;
10309         } else {
10310                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10311                 return -ENOENT;
10312         }
10313         return 0;
10314 }
10315
10316 static uint64_t
10317 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10318 {
10319         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10320         uint64_t systim_cycles;
10321
10322         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10323         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10324                         << 32;
10325
10326         return systim_cycles;
10327 }
10328
10329 static uint64_t
10330 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10331 {
10332         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10333         uint64_t rx_tstamp;
10334
10335         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10336         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10337                         << 32;
10338
10339         return rx_tstamp;
10340 }
10341
10342 static uint64_t
10343 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10344 {
10345         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10346         uint64_t tx_tstamp;
10347
10348         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10349         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10350                         << 32;
10351
10352         return tx_tstamp;
10353 }
10354
10355 static void
10356 i40e_start_timecounters(struct rte_eth_dev *dev)
10357 {
10358         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10359         struct i40e_adapter *adapter =
10360                         (struct i40e_adapter *)dev->data->dev_private;
10361         struct rte_eth_link link;
10362         uint32_t tsync_inc_l;
10363         uint32_t tsync_inc_h;
10364
10365         /* Get current link speed. */
10366         memset(&link, 0, sizeof(link));
10367         i40e_dev_link_update(dev, 1);
10368         rte_i40e_dev_atomic_read_link_status(dev, &link);
10369
10370         switch (link.link_speed) {
10371         case ETH_SPEED_NUM_40G:
10372                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10373                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10374                 break;
10375         case ETH_SPEED_NUM_10G:
10376                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10377                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10378                 break;
10379         case ETH_SPEED_NUM_1G:
10380                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10381                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10382                 break;
10383         default:
10384                 tsync_inc_l = 0x0;
10385                 tsync_inc_h = 0x0;
10386         }
10387
10388         /* Set the timesync increment value. */
10389         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10390         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10391
10392         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10393         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10394         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10395
10396         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10397         adapter->systime_tc.cc_shift = 0;
10398         adapter->systime_tc.nsec_mask = 0;
10399
10400         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10401         adapter->rx_tstamp_tc.cc_shift = 0;
10402         adapter->rx_tstamp_tc.nsec_mask = 0;
10403
10404         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10405         adapter->tx_tstamp_tc.cc_shift = 0;
10406         adapter->tx_tstamp_tc.nsec_mask = 0;
10407 }
10408
10409 static int
10410 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10411 {
10412         struct i40e_adapter *adapter =
10413                         (struct i40e_adapter *)dev->data->dev_private;
10414
10415         adapter->systime_tc.nsec += delta;
10416         adapter->rx_tstamp_tc.nsec += delta;
10417         adapter->tx_tstamp_tc.nsec += delta;
10418
10419         return 0;
10420 }
10421
10422 static int
10423 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10424 {
10425         uint64_t ns;
10426         struct i40e_adapter *adapter =
10427                         (struct i40e_adapter *)dev->data->dev_private;
10428
10429         ns = rte_timespec_to_ns(ts);
10430
10431         /* Set the timecounters to a new value. */
10432         adapter->systime_tc.nsec = ns;
10433         adapter->rx_tstamp_tc.nsec = ns;
10434         adapter->tx_tstamp_tc.nsec = ns;
10435
10436         return 0;
10437 }
10438
10439 static int
10440 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10441 {
10442         uint64_t ns, systime_cycles;
10443         struct i40e_adapter *adapter =
10444                         (struct i40e_adapter *)dev->data->dev_private;
10445
10446         systime_cycles = i40e_read_systime_cyclecounter(dev);
10447         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10448         *ts = rte_ns_to_timespec(ns);
10449
10450         return 0;
10451 }
10452
10453 static int
10454 i40e_timesync_enable(struct rte_eth_dev *dev)
10455 {
10456         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10457         uint32_t tsync_ctl_l;
10458         uint32_t tsync_ctl_h;
10459
10460         /* Stop the timesync system time. */
10461         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10462         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10463         /* Reset the timesync system time value. */
10464         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10465         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10466
10467         i40e_start_timecounters(dev);
10468
10469         /* Clear timesync registers. */
10470         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10471         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10472         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10473         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10474         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10475         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10476
10477         /* Enable timestamping of PTP packets. */
10478         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10479         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10480
10481         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10482         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10483         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10484
10485         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10486         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10487
10488         return 0;
10489 }
10490
10491 static int
10492 i40e_timesync_disable(struct rte_eth_dev *dev)
10493 {
10494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10495         uint32_t tsync_ctl_l;
10496         uint32_t tsync_ctl_h;
10497
10498         /* Disable timestamping of transmitted PTP packets. */
10499         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10500         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10501
10502         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10503         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10504
10505         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10506         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10507
10508         /* Reset the timesync increment value. */
10509         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10510         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10511
10512         return 0;
10513 }
10514
10515 static int
10516 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10517                                 struct timespec *timestamp, uint32_t flags)
10518 {
10519         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10520         struct i40e_adapter *adapter =
10521                 (struct i40e_adapter *)dev->data->dev_private;
10522
10523         uint32_t sync_status;
10524         uint32_t index = flags & 0x03;
10525         uint64_t rx_tstamp_cycles;
10526         uint64_t ns;
10527
10528         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10529         if ((sync_status & (1 << index)) == 0)
10530                 return -EINVAL;
10531
10532         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10533         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10534         *timestamp = rte_ns_to_timespec(ns);
10535
10536         return 0;
10537 }
10538
10539 static int
10540 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10541                                 struct timespec *timestamp)
10542 {
10543         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10544         struct i40e_adapter *adapter =
10545                 (struct i40e_adapter *)dev->data->dev_private;
10546
10547         uint32_t sync_status;
10548         uint64_t tx_tstamp_cycles;
10549         uint64_t ns;
10550
10551         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10552         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10553                 return -EINVAL;
10554
10555         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10556         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10557         *timestamp = rte_ns_to_timespec(ns);
10558
10559         return 0;
10560 }
10561
10562 /*
10563  * i40e_parse_dcb_configure - parse dcb configure from user
10564  * @dev: the device being configured
10565  * @dcb_cfg: pointer of the result of parse
10566  * @*tc_map: bit map of enabled traffic classes
10567  *
10568  * Returns 0 on success, negative value on failure
10569  */
10570 static int
10571 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10572                          struct i40e_dcbx_config *dcb_cfg,
10573                          uint8_t *tc_map)
10574 {
10575         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10576         uint8_t i, tc_bw, bw_lf;
10577
10578         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10579
10580         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10581         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10582                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10583                 return -EINVAL;
10584         }
10585
10586         /* assume each tc has the same bw */
10587         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10588         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10589                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10590         /* to ensure the sum of tcbw is equal to 100 */
10591         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10592         for (i = 0; i < bw_lf; i++)
10593                 dcb_cfg->etscfg.tcbwtable[i]++;
10594
10595         /* assume each tc has the same Transmission Selection Algorithm */
10596         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10597                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10598
10599         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10600                 dcb_cfg->etscfg.prioritytable[i] =
10601                                 dcb_rx_conf->dcb_tc[i];
10602
10603         /* FW needs one App to configure HW */
10604         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10605         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10606         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10607         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10608
10609         if (dcb_rx_conf->nb_tcs == 0)
10610                 *tc_map = 1; /* tc0 only */
10611         else
10612                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10613
10614         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10615                 dcb_cfg->pfc.willing = 0;
10616                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10617                 dcb_cfg->pfc.pfcenable = *tc_map;
10618         }
10619         return 0;
10620 }
10621
10622
10623 static enum i40e_status_code
10624 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10625                               struct i40e_aqc_vsi_properties_data *info,
10626                               uint8_t enabled_tcmap)
10627 {
10628         enum i40e_status_code ret;
10629         int i, total_tc = 0;
10630         uint16_t qpnum_per_tc, bsf, qp_idx;
10631         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10632         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10633         uint16_t used_queues;
10634
10635         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10636         if (ret != I40E_SUCCESS)
10637                 return ret;
10638
10639         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10640                 if (enabled_tcmap & (1 << i))
10641                         total_tc++;
10642         }
10643         if (total_tc == 0)
10644                 total_tc = 1;
10645         vsi->enabled_tc = enabled_tcmap;
10646
10647         /* different VSI has different queues assigned */
10648         if (vsi->type == I40E_VSI_MAIN)
10649                 used_queues = dev_data->nb_rx_queues -
10650                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10651         else if (vsi->type == I40E_VSI_VMDQ2)
10652                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10653         else {
10654                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10655                 return I40E_ERR_NO_AVAILABLE_VSI;
10656         }
10657
10658         qpnum_per_tc = used_queues / total_tc;
10659         /* Number of queues per enabled TC */
10660         if (qpnum_per_tc == 0) {
10661                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10662                 return I40E_ERR_INVALID_QP_ID;
10663         }
10664         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10665                                 I40E_MAX_Q_PER_TC);
10666         bsf = rte_bsf32(qpnum_per_tc);
10667
10668         /**
10669          * Configure TC and queue mapping parameters, for enabled TC,
10670          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10671          * default queue will serve it.
10672          */
10673         qp_idx = 0;
10674         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10675                 if (vsi->enabled_tc & (1 << i)) {
10676                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10677                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10678                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10679                         qp_idx += qpnum_per_tc;
10680                 } else
10681                         info->tc_mapping[i] = 0;
10682         }
10683
10684         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10685         if (vsi->type == I40E_VSI_SRIOV) {
10686                 info->mapping_flags |=
10687                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10688                 for (i = 0; i < vsi->nb_qps; i++)
10689                         info->queue_mapping[i] =
10690                                 rte_cpu_to_le_16(vsi->base_queue + i);
10691         } else {
10692                 info->mapping_flags |=
10693                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10694                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10695         }
10696         info->valid_sections |=
10697                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10698
10699         return I40E_SUCCESS;
10700 }
10701
10702 /*
10703  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10704  * @veb: VEB to be configured
10705  * @tc_map: enabled TC bitmap
10706  *
10707  * Returns 0 on success, negative value on failure
10708  */
10709 static enum i40e_status_code
10710 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10711 {
10712         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10713         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10714         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10715         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10716         enum i40e_status_code ret = I40E_SUCCESS;
10717         int i;
10718         uint32_t bw_max;
10719
10720         /* Check if enabled_tc is same as existing or new TCs */
10721         if (veb->enabled_tc == tc_map)
10722                 return ret;
10723
10724         /* configure tc bandwidth */
10725         memset(&veb_bw, 0, sizeof(veb_bw));
10726         veb_bw.tc_valid_bits = tc_map;
10727         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10728         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10729                 if (tc_map & BIT_ULL(i))
10730                         veb_bw.tc_bw_share_credits[i] = 1;
10731         }
10732         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10733                                                    &veb_bw, NULL);
10734         if (ret) {
10735                 PMD_INIT_LOG(ERR,
10736                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10737                         hw->aq.asq_last_status);
10738                 return ret;
10739         }
10740
10741         memset(&ets_query, 0, sizeof(ets_query));
10742         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10743                                                    &ets_query, NULL);
10744         if (ret != I40E_SUCCESS) {
10745                 PMD_DRV_LOG(ERR,
10746                         "Failed to get switch_comp ETS configuration %u",
10747                         hw->aq.asq_last_status);
10748                 return ret;
10749         }
10750         memset(&bw_query, 0, sizeof(bw_query));
10751         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10752                                                   &bw_query, NULL);
10753         if (ret != I40E_SUCCESS) {
10754                 PMD_DRV_LOG(ERR,
10755                         "Failed to get switch_comp bandwidth configuration %u",
10756                         hw->aq.asq_last_status);
10757                 return ret;
10758         }
10759
10760         /* store and print out BW info */
10761         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10762         veb->bw_info.bw_max = ets_query.tc_bw_max;
10763         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10764         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10765         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10766                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10767                      I40E_16_BIT_WIDTH);
10768         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10769                 veb->bw_info.bw_ets_share_credits[i] =
10770                                 bw_query.tc_bw_share_credits[i];
10771                 veb->bw_info.bw_ets_credits[i] =
10772                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10773                 /* 4 bits per TC, 4th bit is reserved */
10774                 veb->bw_info.bw_ets_max[i] =
10775                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10776                                   RTE_LEN2MASK(3, uint8_t));
10777                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10778                             veb->bw_info.bw_ets_share_credits[i]);
10779                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10780                             veb->bw_info.bw_ets_credits[i]);
10781                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10782                             veb->bw_info.bw_ets_max[i]);
10783         }
10784
10785         veb->enabled_tc = tc_map;
10786
10787         return ret;
10788 }
10789
10790
10791 /*
10792  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10793  * @vsi: VSI to be configured
10794  * @tc_map: enabled TC bitmap
10795  *
10796  * Returns 0 on success, negative value on failure
10797  */
10798 static enum i40e_status_code
10799 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10800 {
10801         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10802         struct i40e_vsi_context ctxt;
10803         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10804         enum i40e_status_code ret = I40E_SUCCESS;
10805         int i;
10806
10807         /* Check if enabled_tc is same as existing or new TCs */
10808         if (vsi->enabled_tc == tc_map)
10809                 return ret;
10810
10811         /* configure tc bandwidth */
10812         memset(&bw_data, 0, sizeof(bw_data));
10813         bw_data.tc_valid_bits = tc_map;
10814         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10815         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10816                 if (tc_map & BIT_ULL(i))
10817                         bw_data.tc_bw_credits[i] = 1;
10818         }
10819         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10820         if (ret) {
10821                 PMD_INIT_LOG(ERR,
10822                         "AQ command Config VSI BW allocation per TC failed = %d",
10823                         hw->aq.asq_last_status);
10824                 goto out;
10825         }
10826         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10827                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10828
10829         /* Update Queue Pairs Mapping for currently enabled UPs */
10830         ctxt.seid = vsi->seid;
10831         ctxt.pf_num = hw->pf_id;
10832         ctxt.vf_num = 0;
10833         ctxt.uplink_seid = vsi->uplink_seid;
10834         ctxt.info = vsi->info;
10835         i40e_get_cap(hw);
10836         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10837         if (ret)
10838                 goto out;
10839
10840         /* Update the VSI after updating the VSI queue-mapping information */
10841         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10842         if (ret) {
10843                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10844                         hw->aq.asq_last_status);
10845                 goto out;
10846         }
10847         /* update the local VSI info with updated queue map */
10848         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10849                                         sizeof(vsi->info.tc_mapping));
10850         rte_memcpy(&vsi->info.queue_mapping,
10851                         &ctxt.info.queue_mapping,
10852                 sizeof(vsi->info.queue_mapping));
10853         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10854         vsi->info.valid_sections = 0;
10855
10856         /* query and update current VSI BW information */
10857         ret = i40e_vsi_get_bw_config(vsi);
10858         if (ret) {
10859                 PMD_INIT_LOG(ERR,
10860                          "Failed updating vsi bw info, err %s aq_err %s",
10861                          i40e_stat_str(hw, ret),
10862                          i40e_aq_str(hw, hw->aq.asq_last_status));
10863                 goto out;
10864         }
10865
10866         vsi->enabled_tc = tc_map;
10867
10868 out:
10869         return ret;
10870 }
10871
10872 /*
10873  * i40e_dcb_hw_configure - program the dcb setting to hw
10874  * @pf: pf the configuration is taken on
10875  * @new_cfg: new configuration
10876  * @tc_map: enabled TC bitmap
10877  *
10878  * Returns 0 on success, negative value on failure
10879  */
10880 static enum i40e_status_code
10881 i40e_dcb_hw_configure(struct i40e_pf *pf,
10882                       struct i40e_dcbx_config *new_cfg,
10883                       uint8_t tc_map)
10884 {
10885         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10886         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10887         struct i40e_vsi *main_vsi = pf->main_vsi;
10888         struct i40e_vsi_list *vsi_list;
10889         enum i40e_status_code ret;
10890         int i;
10891         uint32_t val;
10892
10893         /* Use the FW API if FW > v4.4*/
10894         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10895               (hw->aq.fw_maj_ver >= 5))) {
10896                 PMD_INIT_LOG(ERR,
10897                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10898                 return I40E_ERR_FIRMWARE_API_VERSION;
10899         }
10900
10901         /* Check if need reconfiguration */
10902         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10903                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10904                 return I40E_SUCCESS;
10905         }
10906
10907         /* Copy the new config to the current config */
10908         *old_cfg = *new_cfg;
10909         old_cfg->etsrec = old_cfg->etscfg;
10910         ret = i40e_set_dcb_config(hw);
10911         if (ret) {
10912                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10913                          i40e_stat_str(hw, ret),
10914                          i40e_aq_str(hw, hw->aq.asq_last_status));
10915                 return ret;
10916         }
10917         /* set receive Arbiter to RR mode and ETS scheme by default */
10918         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10919                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10920                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10921                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10922                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10923                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10924                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10925                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10926                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10927                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10928                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10929                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10930                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10931         }
10932         /* get local mib to check whether it is configured correctly */
10933         /* IEEE mode */
10934         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10935         /* Get Local DCB Config */
10936         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10937                                      &hw->local_dcbx_config);
10938
10939         /* if Veb is created, need to update TC of it at first */
10940         if (main_vsi->veb) {
10941                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10942                 if (ret)
10943                         PMD_INIT_LOG(WARNING,
10944                                  "Failed configuring TC for VEB seid=%d",
10945                                  main_vsi->veb->seid);
10946         }
10947         /* Update each VSI */
10948         i40e_vsi_config_tc(main_vsi, tc_map);
10949         if (main_vsi->veb) {
10950                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10951                         /* Beside main VSI and VMDQ VSIs, only enable default
10952                          * TC for other VSIs
10953                          */
10954                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10955                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10956                                                          tc_map);
10957                         else
10958                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10959                                                          I40E_DEFAULT_TCMAP);
10960                         if (ret)
10961                                 PMD_INIT_LOG(WARNING,
10962                                         "Failed configuring TC for VSI seid=%d",
10963                                         vsi_list->vsi->seid);
10964                         /* continue */
10965                 }
10966         }
10967         return I40E_SUCCESS;
10968 }
10969
10970 /*
10971  * i40e_dcb_init_configure - initial dcb config
10972  * @dev: device being configured
10973  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10974  *
10975  * Returns 0 on success, negative value on failure
10976  */
10977 int
10978 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10979 {
10980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10982         int i, ret = 0;
10983
10984         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10985                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10986                 return -ENOTSUP;
10987         }
10988
10989         /* DCB initialization:
10990          * Update DCB configuration from the Firmware and configure
10991          * LLDP MIB change event.
10992          */
10993         if (sw_dcb == TRUE) {
10994                 ret = i40e_init_dcb(hw);
10995                 /* If lldp agent is stopped, the return value from
10996                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10997                  * adminq status. Otherwise, it should return success.
10998                  */
10999                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11000                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11001                         memset(&hw->local_dcbx_config, 0,
11002                                 sizeof(struct i40e_dcbx_config));
11003                         /* set dcb default configuration */
11004                         hw->local_dcbx_config.etscfg.willing = 0;
11005                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11006                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11007                         hw->local_dcbx_config.etscfg.tsatable[0] =
11008                                                 I40E_IEEE_TSA_ETS;
11009                         /* all UPs mapping to TC0 */
11010                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11011                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11012                         hw->local_dcbx_config.etsrec =
11013                                 hw->local_dcbx_config.etscfg;
11014                         hw->local_dcbx_config.pfc.willing = 0;
11015                         hw->local_dcbx_config.pfc.pfccap =
11016                                                 I40E_MAX_TRAFFIC_CLASS;
11017                         /* FW needs one App to configure HW */
11018                         hw->local_dcbx_config.numapps = 1;
11019                         hw->local_dcbx_config.app[0].selector =
11020                                                 I40E_APP_SEL_ETHTYPE;
11021                         hw->local_dcbx_config.app[0].priority = 3;
11022                         hw->local_dcbx_config.app[0].protocolid =
11023                                                 I40E_APP_PROTOID_FCOE;
11024                         ret = i40e_set_dcb_config(hw);
11025                         if (ret) {
11026                                 PMD_INIT_LOG(ERR,
11027                                         "default dcb config fails. err = %d, aq_err = %d.",
11028                                         ret, hw->aq.asq_last_status);
11029                                 return -ENOSYS;
11030                         }
11031                 } else {
11032                         PMD_INIT_LOG(ERR,
11033                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11034                                 ret, hw->aq.asq_last_status);
11035                         return -ENOTSUP;
11036                 }
11037         } else {
11038                 ret = i40e_aq_start_lldp(hw, NULL);
11039                 if (ret != I40E_SUCCESS)
11040                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11041
11042                 ret = i40e_init_dcb(hw);
11043                 if (!ret) {
11044                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11045                                 PMD_INIT_LOG(ERR,
11046                                         "HW doesn't support DCBX offload.");
11047                                 return -ENOTSUP;
11048                         }
11049                 } else {
11050                         PMD_INIT_LOG(ERR,
11051                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11052                                 ret, hw->aq.asq_last_status);
11053                         return -ENOTSUP;
11054                 }
11055         }
11056         return 0;
11057 }
11058
11059 /*
11060  * i40e_dcb_setup - setup dcb related config
11061  * @dev: device being configured
11062  *
11063  * Returns 0 on success, negative value on failure
11064  */
11065 static int
11066 i40e_dcb_setup(struct rte_eth_dev *dev)
11067 {
11068         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11069         struct i40e_dcbx_config dcb_cfg;
11070         uint8_t tc_map = 0;
11071         int ret = 0;
11072
11073         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11074                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11075                 return -ENOTSUP;
11076         }
11077
11078         if (pf->vf_num != 0)
11079                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11080
11081         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11082         if (ret) {
11083                 PMD_INIT_LOG(ERR, "invalid dcb config");
11084                 return -EINVAL;
11085         }
11086         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11087         if (ret) {
11088                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11089                 return -ENOSYS;
11090         }
11091
11092         return 0;
11093 }
11094
11095 static int
11096 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11097                       struct rte_eth_dcb_info *dcb_info)
11098 {
11099         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11101         struct i40e_vsi *vsi = pf->main_vsi;
11102         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11103         uint16_t bsf, tc_mapping;
11104         int i, j = 0;
11105
11106         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11107                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11108         else
11109                 dcb_info->nb_tcs = 1;
11110         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11111                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11112         for (i = 0; i < dcb_info->nb_tcs; i++)
11113                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11114
11115         /* get queue mapping if vmdq is disabled */
11116         if (!pf->nb_cfg_vmdq_vsi) {
11117                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11118                         if (!(vsi->enabled_tc & (1 << i)))
11119                                 continue;
11120                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11121                         dcb_info->tc_queue.tc_rxq[j][i].base =
11122                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11123                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11124                         dcb_info->tc_queue.tc_txq[j][i].base =
11125                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11126                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11127                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11128                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11129                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11130                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11131                 }
11132                 return 0;
11133         }
11134
11135         /* get queue mapping if vmdq is enabled */
11136         do {
11137                 vsi = pf->vmdq[j].vsi;
11138                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11139                         if (!(vsi->enabled_tc & (1 << i)))
11140                                 continue;
11141                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11142                         dcb_info->tc_queue.tc_rxq[j][i].base =
11143                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11144                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11145                         dcb_info->tc_queue.tc_txq[j][i].base =
11146                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11147                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11148                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11149                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11150                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11151                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11152                 }
11153                 j++;
11154         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11155         return 0;
11156 }
11157
11158 static int
11159 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11160 {
11161         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11162         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11164         uint16_t msix_intr;
11165
11166         msix_intr = intr_handle->intr_vec[queue_id];
11167         if (msix_intr == I40E_MISC_VEC_ID)
11168                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11169                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11170                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11171                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11172         else
11173                 I40E_WRITE_REG(hw,
11174                                I40E_PFINT_DYN_CTLN(msix_intr -
11175                                                    I40E_RX_VEC_START),
11176                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11177                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11178                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11179
11180         I40E_WRITE_FLUSH(hw);
11181         rte_intr_enable(&pci_dev->intr_handle);
11182
11183         return 0;
11184 }
11185
11186 static int
11187 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11188 {
11189         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11190         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11191         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11192         uint16_t msix_intr;
11193
11194         msix_intr = intr_handle->intr_vec[queue_id];
11195         if (msix_intr == I40E_MISC_VEC_ID)
11196                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11197                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11198         else
11199                 I40E_WRITE_REG(hw,
11200                                I40E_PFINT_DYN_CTLN(msix_intr -
11201                                                    I40E_RX_VEC_START),
11202                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11203         I40E_WRITE_FLUSH(hw);
11204
11205         return 0;
11206 }
11207
11208 /**
11209  * This function is used to check if the register is valid.
11210  * Below is the valid registers list for X722 only:
11211  * 0x2b800--0x2bb00
11212  * 0x38700--0x38a00
11213  * 0x3d800--0x3db00
11214  * 0x208e00--0x209000
11215  * 0x20be00--0x20c000
11216  * 0x263c00--0x264000
11217  * 0x265c00--0x266000
11218  */
11219 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11220 {
11221         if ((type != I40E_MAC_X722) &&
11222             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11223              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11224              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11225              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11226              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11227              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11228              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11229                 return 0;
11230         else
11231                 return 1;
11232 }
11233
11234 static int i40e_get_regs(struct rte_eth_dev *dev,
11235                          struct rte_dev_reg_info *regs)
11236 {
11237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11238         uint32_t *ptr_data = regs->data;
11239         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11240         const struct i40e_reg_info *reg_info;
11241
11242         if (ptr_data == NULL) {
11243                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11244                 regs->width = sizeof(uint32_t);
11245                 return 0;
11246         }
11247
11248         /* The first few registers have to be read using AQ operations */
11249         reg_idx = 0;
11250         while (i40e_regs_adminq[reg_idx].name) {
11251                 reg_info = &i40e_regs_adminq[reg_idx++];
11252                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11253                         for (arr_idx2 = 0;
11254                                         arr_idx2 <= reg_info->count2;
11255                                         arr_idx2++) {
11256                                 reg_offset = arr_idx * reg_info->stride1 +
11257                                         arr_idx2 * reg_info->stride2;
11258                                 reg_offset += reg_info->base_addr;
11259                                 ptr_data[reg_offset >> 2] =
11260                                         i40e_read_rx_ctl(hw, reg_offset);
11261                         }
11262         }
11263
11264         /* The remaining registers can be read using primitives */
11265         reg_idx = 0;
11266         while (i40e_regs_others[reg_idx].name) {
11267                 reg_info = &i40e_regs_others[reg_idx++];
11268                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11269                         for (arr_idx2 = 0;
11270                                         arr_idx2 <= reg_info->count2;
11271                                         arr_idx2++) {
11272                                 reg_offset = arr_idx * reg_info->stride1 +
11273                                         arr_idx2 * reg_info->stride2;
11274                                 reg_offset += reg_info->base_addr;
11275                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11276                                         ptr_data[reg_offset >> 2] = 0;
11277                                 else
11278                                         ptr_data[reg_offset >> 2] =
11279                                                 I40E_READ_REG(hw, reg_offset);
11280                         }
11281         }
11282
11283         return 0;
11284 }
11285
11286 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11287 {
11288         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11289
11290         /* Convert word count to byte count */
11291         return hw->nvm.sr_size << 1;
11292 }
11293
11294 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11295                            struct rte_dev_eeprom_info *eeprom)
11296 {
11297         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11298         uint16_t *data = eeprom->data;
11299         uint16_t offset, length, cnt_words;
11300         int ret_code;
11301
11302         offset = eeprom->offset >> 1;
11303         length = eeprom->length >> 1;
11304         cnt_words = length;
11305
11306         if (offset > hw->nvm.sr_size ||
11307                 offset + length > hw->nvm.sr_size) {
11308                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11309                 return -EINVAL;
11310         }
11311
11312         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11313
11314         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11315         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11316                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11317                 return -EIO;
11318         }
11319
11320         return 0;
11321 }
11322
11323 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11324                                       struct ether_addr *mac_addr)
11325 {
11326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11328         struct i40e_vsi *vsi = pf->main_vsi;
11329         struct i40e_mac_filter_info mac_filter;
11330         struct i40e_mac_filter *f;
11331         int ret;
11332
11333         if (!is_valid_assigned_ether_addr(mac_addr)) {
11334                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11335                 return;
11336         }
11337
11338         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11339                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11340                         break;
11341         }
11342
11343         if (f == NULL) {
11344                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11345                 return;
11346         }
11347
11348         mac_filter = f->mac_info;
11349         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11350         if (ret != I40E_SUCCESS) {
11351                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11352                 return;
11353         }
11354         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11355         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11356         if (ret != I40E_SUCCESS) {
11357                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11358                 return;
11359         }
11360         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11361
11362         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11363                                   mac_addr->addr_bytes, NULL);
11364 }
11365
11366 static int
11367 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11368 {
11369         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11370         struct rte_eth_dev_data *dev_data = pf->dev_data;
11371         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11372         int ret = 0;
11373
11374         /* check if mtu is within the allowed range */
11375         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11376                 return -EINVAL;
11377
11378         /* mtu setting is forbidden if port is start */
11379         if (dev_data->dev_started) {
11380                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11381                             dev_data->port_id);
11382                 return -EBUSY;
11383         }
11384
11385         if (frame_size > ETHER_MAX_LEN)
11386                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11387         else
11388                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11389
11390         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11391
11392         return ret;
11393 }
11394
11395 /* Restore ethertype filter */
11396 static void
11397 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11398 {
11399         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11400         struct i40e_ethertype_filter_list
11401                 *ethertype_list = &pf->ethertype.ethertype_list;
11402         struct i40e_ethertype_filter *f;
11403         struct i40e_control_filter_stats stats;
11404         uint16_t flags;
11405
11406         TAILQ_FOREACH(f, ethertype_list, rules) {
11407                 flags = 0;
11408                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11409                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11410                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11411                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11412                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11413
11414                 memset(&stats, 0, sizeof(stats));
11415                 i40e_aq_add_rem_control_packet_filter(hw,
11416                                             f->input.mac_addr.addr_bytes,
11417                                             f->input.ether_type,
11418                                             flags, pf->main_vsi->seid,
11419                                             f->queue, 1, &stats, NULL);
11420         }
11421         PMD_DRV_LOG(INFO, "Ethertype filter:"
11422                     " mac_etype_used = %u, etype_used = %u,"
11423                     " mac_etype_free = %u, etype_free = %u",
11424                     stats.mac_etype_used, stats.etype_used,
11425                     stats.mac_etype_free, stats.etype_free);
11426 }
11427
11428 /* Restore tunnel filter */
11429 static void
11430 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11431 {
11432         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11433         struct i40e_vsi *vsi;
11434         struct i40e_pf_vf *vf;
11435         struct i40e_tunnel_filter_list
11436                 *tunnel_list = &pf->tunnel.tunnel_list;
11437         struct i40e_tunnel_filter *f;
11438         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11439         bool big_buffer = 0;
11440
11441         TAILQ_FOREACH(f, tunnel_list, rules) {
11442                 if (!f->is_to_vf)
11443                         vsi = pf->main_vsi;
11444                 else {
11445                         vf = &pf->vfs[f->vf_id];
11446                         vsi = vf->vsi;
11447                 }
11448                 memset(&cld_filter, 0, sizeof(cld_filter));
11449                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11450                         (struct ether_addr *)&cld_filter.element.outer_mac);
11451                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11452                         (struct ether_addr *)&cld_filter.element.inner_mac);
11453                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11454                 cld_filter.element.flags = f->input.flags;
11455                 cld_filter.element.tenant_id = f->input.tenant_id;
11456                 cld_filter.element.queue_number = f->queue;
11457                 rte_memcpy(cld_filter.general_fields,
11458                            f->input.general_fields,
11459                            sizeof(f->input.general_fields));
11460
11461                 if (((f->input.flags &
11462                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11463                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11464                     ((f->input.flags &
11465                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11466                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11467                     ((f->input.flags &
11468                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11469                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11470                         big_buffer = 1;
11471
11472                 if (big_buffer)
11473                         i40e_aq_add_cloud_filters_big_buffer(hw,
11474                                              vsi->seid, &cld_filter, 1);
11475                 else
11476                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11477                                                   &cld_filter.element, 1);
11478         }
11479 }
11480
11481 static void
11482 i40e_filter_restore(struct i40e_pf *pf)
11483 {
11484         i40e_ethertype_filter_restore(pf);
11485         i40e_tunnel_filter_restore(pf);
11486         i40e_fdir_filter_restore(pf);
11487 }
11488
11489 static bool
11490 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11491 {
11492         if (strcmp(dev->device->driver->name, drv->driver.name))
11493                 return false;
11494
11495         return true;
11496 }
11497
11498 bool
11499 is_i40e_supported(struct rte_eth_dev *dev)
11500 {
11501         return is_device_supported(dev, &rte_i40e_pmd);
11502 }
11503
11504 struct i40e_customized_pctype*
11505 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11506 {
11507         int i;
11508
11509         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11510                 if (pf->customized_pctype[i].index == index)
11511                         return &pf->customized_pctype[i];
11512         }
11513         return NULL;
11514 }
11515
11516 static int
11517 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11518                               uint32_t pkg_size, uint32_t proto_num,
11519                               struct rte_pmd_i40e_proto_info *proto,
11520                               enum rte_pmd_i40e_package_op op)
11521 {
11522         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11523         uint32_t pctype_num;
11524         struct rte_pmd_i40e_ptype_info *pctype;
11525         uint32_t buff_size;
11526         struct i40e_customized_pctype *new_pctype = NULL;
11527         uint8_t proto_id;
11528         uint8_t pctype_value;
11529         char name[64];
11530         uint32_t i, j, n;
11531         int ret;
11532
11533         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11534             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11535                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11536                 return -1;
11537         }
11538
11539         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11540                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11541                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11542         if (ret) {
11543                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11544                 return -1;
11545         }
11546         if (!pctype_num) {
11547                 PMD_DRV_LOG(INFO, "No new pctype added");
11548                 return -1;
11549         }
11550
11551         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11552         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11553         if (!pctype) {
11554                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11555                 return -1;
11556         }
11557         /* get information about new pctype list */
11558         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11559                                         (uint8_t *)pctype, buff_size,
11560                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11561         if (ret) {
11562                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11563                 rte_free(pctype);
11564                 return -1;
11565         }
11566
11567         /* Update customized pctype. */
11568         for (i = 0; i < pctype_num; i++) {
11569                 pctype_value = pctype[i].ptype_id;
11570                 memset(name, 0, sizeof(name));
11571                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11572                         proto_id = pctype[i].protocols[j];
11573                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11574                                 continue;
11575                         for (n = 0; n < proto_num; n++) {
11576                                 if (proto[n].proto_id != proto_id)
11577                                         continue;
11578                                 strcat(name, proto[n].name);
11579                                 strcat(name, "_");
11580                                 break;
11581                         }
11582                 }
11583                 name[strlen(name) - 1] = '\0';
11584                 if (!strcmp(name, "GTPC"))
11585                         new_pctype =
11586                                 i40e_find_customized_pctype(pf,
11587                                                       I40E_CUSTOMIZED_GTPC);
11588                 else if (!strcmp(name, "GTPU_IPV4"))
11589                         new_pctype =
11590                                 i40e_find_customized_pctype(pf,
11591                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11592                 else if (!strcmp(name, "GTPU_IPV6"))
11593                         new_pctype =
11594                                 i40e_find_customized_pctype(pf,
11595                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11596                 else if (!strcmp(name, "GTPU"))
11597                         new_pctype =
11598                                 i40e_find_customized_pctype(pf,
11599                                                       I40E_CUSTOMIZED_GTPU);
11600                 if (new_pctype) {
11601                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11602                                 new_pctype->pctype = pctype_value;
11603                                 new_pctype->valid = true;
11604                         } else {
11605                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11606                                 new_pctype->valid = false;
11607                         }
11608                 }
11609         }
11610
11611         rte_free(pctype);
11612         return 0;
11613 }
11614
11615 static int
11616 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11617                              uint32_t pkg_size, uint32_t proto_num,
11618                              struct rte_pmd_i40e_proto_info *proto,
11619                              enum rte_pmd_i40e_package_op op)
11620 {
11621         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11622         uint16_t port_id = dev->data->port_id;
11623         uint32_t ptype_num;
11624         struct rte_pmd_i40e_ptype_info *ptype;
11625         uint32_t buff_size;
11626         uint8_t proto_id;
11627         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11628         uint32_t i, j, n;
11629         bool inner_ip;
11630         int ret;
11631
11632         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11633             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11634                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11635                 return -1;
11636         }
11637
11638         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11639                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11640                 return 0;
11641         }
11642
11643         /* get information about new ptype num */
11644         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11645                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11646                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11647         if (ret) {
11648                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11649                 return ret;
11650         }
11651         if (!ptype_num) {
11652                 PMD_DRV_LOG(INFO, "No new ptype added");
11653                 return -1;
11654         }
11655
11656         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11657         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11658         if (!ptype) {
11659                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11660                 return -1;
11661         }
11662
11663         /* get information about new ptype list */
11664         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11665                                         (uint8_t *)ptype, buff_size,
11666                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11667         if (ret) {
11668                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11669                 rte_free(ptype);
11670                 return ret;
11671         }
11672
11673         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11674         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11675         if (!ptype_mapping) {
11676                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11677                 rte_free(ptype);
11678                 return -1;
11679         }
11680
11681         /* Update ptype mapping table. */
11682         for (i = 0; i < ptype_num; i++) {
11683                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11684                 ptype_mapping[i].sw_ptype = 0;
11685                 inner_ip = false;
11686                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11687                         proto_id = ptype[i].protocols[j];
11688                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11689                                 continue;
11690                         for (n = 0; n < proto_num; n++) {
11691                                 if (proto[n].proto_id != proto_id)
11692                                         continue;
11693                                 memset(name, 0, sizeof(name));
11694                                 strcpy(name, proto[n].name);
11695                                 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11696                                         ptype_mapping[i].sw_ptype |=
11697                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11698                                         inner_ip = true;
11699                                 } else if (!strncmp(name, "IPV4FRAG", 8) &&
11700                                            inner_ip) {
11701                                         ptype_mapping[i].sw_ptype |=
11702                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11703                                         ptype_mapping[i].sw_ptype |=
11704                                                 RTE_PTYPE_INNER_L4_FRAG;
11705                                 } else if (!strncmp(name, "IPV4", 4) &&
11706                                            inner_ip)
11707                                         ptype_mapping[i].sw_ptype |=
11708                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11709                                 else if (!strncmp(name, "IPV6", 4) &&
11710                                          !inner_ip) {
11711                                         ptype_mapping[i].sw_ptype |=
11712                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11713                                         inner_ip = true;
11714                                 } else if (!strncmp(name, "IPV6FRAG", 8) &&
11715                                            inner_ip) {
11716                                         ptype_mapping[i].sw_ptype |=
11717                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11718                                         ptype_mapping[i].sw_ptype |=
11719                                                 RTE_PTYPE_INNER_L4_FRAG;
11720                                 } else if (!strncmp(name, "IPV6", 4) &&
11721                                            inner_ip)
11722                                         ptype_mapping[i].sw_ptype |=
11723                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11724                                 else if (!strncmp(name, "GTPC", 4))
11725                                         ptype_mapping[i].sw_ptype |=
11726                                                 RTE_PTYPE_TUNNEL_GTPC;
11727                                 else if (!strncmp(name, "GTPU", 4))
11728                                         ptype_mapping[i].sw_ptype |=
11729                                                 RTE_PTYPE_TUNNEL_GTPU;
11730                                 else if (!strncmp(name, "UDP", 3))
11731                                         ptype_mapping[i].sw_ptype |=
11732                                                 RTE_PTYPE_INNER_L4_UDP;
11733                                 else if (!strncmp(name, "TCP", 3))
11734                                         ptype_mapping[i].sw_ptype |=
11735                                                 RTE_PTYPE_INNER_L4_TCP;
11736                                 else if (!strncmp(name, "SCTP", 4))
11737                                         ptype_mapping[i].sw_ptype |=
11738                                                 RTE_PTYPE_INNER_L4_SCTP;
11739                                 else if (!strncmp(name, "ICMP", 4) ||
11740                                          !strncmp(name, "ICMPV6", 6))
11741                                         ptype_mapping[i].sw_ptype |=
11742                                                 RTE_PTYPE_INNER_L4_ICMP;
11743
11744                                 break;
11745                         }
11746                 }
11747         }
11748
11749         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11750                                                 ptype_num, 0);
11751         if (ret)
11752                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11753
11754         rte_free(ptype_mapping);
11755         rte_free(ptype);
11756         return ret;
11757 }
11758
11759 void
11760 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11761                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11762 {
11763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11764         uint32_t proto_num;
11765         struct rte_pmd_i40e_proto_info *proto;
11766         uint32_t buff_size;
11767         uint32_t i;
11768         int ret;
11769
11770         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11771             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11772                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11773                 return;
11774         }
11775
11776         /* get information about protocol number */
11777         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11778                                        (uint8_t *)&proto_num, sizeof(proto_num),
11779                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11780         if (ret) {
11781                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11782                 return;
11783         }
11784         if (!proto_num) {
11785                 PMD_DRV_LOG(INFO, "No new protocol added");
11786                 return;
11787         }
11788
11789         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11790         proto = rte_zmalloc("new_proto", buff_size, 0);
11791         if (!proto) {
11792                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11793                 return;
11794         }
11795
11796         /* get information about protocol list */
11797         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11798                                         (uint8_t *)proto, buff_size,
11799                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11800         if (ret) {
11801                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11802                 rte_free(proto);
11803                 return;
11804         }
11805
11806         /* Check if GTP is supported. */
11807         for (i = 0; i < proto_num; i++) {
11808                 if (!strncmp(proto[i].name, "GTP", 3)) {
11809                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11810                                 pf->gtp_support = true;
11811                         else
11812                                 pf->gtp_support = false;
11813                         break;
11814                 }
11815         }
11816
11817         /* Update customized pctype info */
11818         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11819                                             proto_num, proto, op);
11820         if (ret)
11821                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11822
11823         /* Update customized ptype info */
11824         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11825                                            proto_num, proto, op);
11826         if (ret)
11827                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11828
11829         rte_free(proto);
11830 }
11831
11832 /* Create a QinQ cloud filter
11833  *
11834  * The Fortville NIC has limited resources for tunnel filters,
11835  * so we can only reuse existing filters.
11836  *
11837  * In step 1 we define which Field Vector fields can be used for
11838  * filter types.
11839  * As we do not have the inner tag defined as a field,
11840  * we have to define it first, by reusing one of L1 entries.
11841  *
11842  * In step 2 we are replacing one of existing filter types with
11843  * a new one for QinQ.
11844  * As we reusing L1 and replacing L2, some of the default filter
11845  * types will disappear,which depends on L1 and L2 entries we reuse.
11846  *
11847  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11848  *
11849  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11850  *              later when we define the cloud filter.
11851  *      a.      Valid_flags.replace_cloud = 0
11852  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11853  *      c.      New_filter = 0x10
11854  *      d.      TR bit = 0xff (optional, not used here)
11855  *      e.      Buffer – 2 entries:
11856  *              i.      Byte 0 = 8 (outer vlan FV index).
11857  *                      Byte 1 = 0 (rsv)
11858  *                      Byte 2-3 = 0x0fff
11859  *              ii.     Byte 0 = 37 (inner vlan FV index).
11860  *                      Byte 1 =0 (rsv)
11861  *                      Byte 2-3 = 0x0fff
11862  *
11863  * Step 2:
11864  * 2.   Create cloud filter using two L1 filters entries: stag and
11865  *              new filter(outer vlan+ inner vlan)
11866  *      a.      Valid_flags.replace_cloud = 1
11867  *      b.      Old_filter = 1 (instead of outer IP)
11868  *      c.      New_filter = 0x10
11869  *      d.      Buffer – 2 entries:
11870  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11871  *                      Byte 1-3 = 0 (rsv)
11872  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11873  *                      Byte 9-11 = 0 (rsv)
11874  */
11875 static int
11876 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11877 {
11878         int ret = -ENOTSUP;
11879         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11880         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11881         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11882
11883         if (pf->support_multi_driver) {
11884                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11885                 return ret;
11886         }
11887
11888         /* Init */
11889         memset(&filter_replace, 0,
11890                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11891         memset(&filter_replace_buf, 0,
11892                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11893
11894         /* create L1 filter */
11895         filter_replace.old_filter_type =
11896                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11897         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11898         filter_replace.tr_bit = 0;
11899
11900         /* Prepare the buffer, 2 entries */
11901         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11902         filter_replace_buf.data[0] |=
11903                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11904         /* Field Vector 12b mask */
11905         filter_replace_buf.data[2] = 0xff;
11906         filter_replace_buf.data[3] = 0x0f;
11907         filter_replace_buf.data[4] =
11908                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11909         filter_replace_buf.data[4] |=
11910                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11911         /* Field Vector 12b mask */
11912         filter_replace_buf.data[6] = 0xff;
11913         filter_replace_buf.data[7] = 0x0f;
11914         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11915                         &filter_replace_buf);
11916         if (ret != I40E_SUCCESS)
11917                 return ret;
11918         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11919                     "cloud l1 type is changed from 0x%x to 0x%x",
11920                     filter_replace.old_filter_type,
11921                     filter_replace.new_filter_type);
11922
11923         /* Apply the second L2 cloud filter */
11924         memset(&filter_replace, 0,
11925                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11926         memset(&filter_replace_buf, 0,
11927                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11928
11929         /* create L2 filter, input for L2 filter will be L1 filter  */
11930         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11931         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11932         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11933
11934         /* Prepare the buffer, 2 entries */
11935         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11936         filter_replace_buf.data[0] |=
11937                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11938         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11939         filter_replace_buf.data[4] |=
11940                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11941         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11942                         &filter_replace_buf);
11943         if (!ret) {
11944                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11945                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11946                             "cloud filter type is changed from 0x%x to 0x%x",
11947                             filter_replace.old_filter_type,
11948                             filter_replace.new_filter_type);
11949         }
11950         return ret;
11951 }
11952
11953 RTE_INIT(i40e_init_log);
11954 static void
11955 i40e_init_log(void)
11956 {
11957         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11958         if (i40e_logtype_init >= 0)
11959                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11960         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11961         if (i40e_logtype_driver >= 0)
11962                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11963 }
11964
11965 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
11966                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");