drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518         .tm_ops_get                   = i40e_tm_ops_get,
 519 };
 520
 521 /* store statistics names and its offset in stats structure */
 522 struct rte_i40e_xstats_name_off {
 523         char name[RTE_ETH_XSTATS_NAME_SIZE];
 524         unsigned offset;
 525 };
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 528         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 529         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 530         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 531         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 532         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 533                 rx_unknown_protocol)},
 534         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 535         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 536         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 537         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 538 };
 539
 540 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 541                 sizeof(rte_i40e_stats_strings[0]))
 542
 543 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 544         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 545                 tx_dropped_link_down)},
 546         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 547         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 548                 illegal_bytes)},
 549         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 550         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_local_faults)},
 552         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_remote_faults)},
 554         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 555                 rx_length_errors)},
 556         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 557         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 558         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 559         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 560         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 561         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_127)},
 563         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_255)},
 565         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_511)},
 567         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1023)},
 569         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1522)},
 571         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_big)},
 573         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_undersize)},
 575         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_oversize)},
 577         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 578                 mac_short_packet_dropped)},
 579         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_fragments)},
 581         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 582         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 583         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_127)},
 585         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_255)},
 587         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_511)},
 589         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1023)},
 591         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1522)},
 593         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_big)},
 595         {"rx_flow_director_atr_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 597         {"rx_flow_director_sb_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 599         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_status)},
 601         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_status)},
 603         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_count)},
 605         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_count)},
 607 };
 608
 609 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 610                 sizeof(rte_i40e_hw_port_strings[0]))
 611
 612 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 613         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xon_rx)},
 615         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xoff_rx)},
 617 };
 618
 619 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 620                 sizeof(rte_i40e_rxq_prio_strings[0]))
 621
 622 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 623         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_tx)},
 625         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xoff_tx)},
 627         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_2_xoff)},
 629 };
 630
 631 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 632                 sizeof(rte_i40e_txq_prio_strings[0]))
 633
 634 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         return rte_eth_dev_pci_generic_probe(pci_dev,
 638                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 639 }
 640
 641 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 642 {
 643         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 644 }
 645
 646 static struct rte_pci_driver rte_i40e_pmd = {
 647         .id_table = pci_id_i40e_map,
 648         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 649         .probe = eth_i40e_pci_probe,
 650         .remove = eth_i40e_pci_remove,
 651 };
 652
 653 static inline int
 654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 655                                      struct rte_eth_link *link)
 656 {
 657         struct rte_eth_link *dst = link;
 658         struct rte_eth_link *src = &(dev->data->dev_link);
 659
 660         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 661                                         *(uint64_t *)src) == 0)
 662                 return -1;
 663
 664         return 0;
 665 }
 666
 667 static inline int
 668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 669                                       struct rte_eth_link *link)
 670 {
 671         struct rte_eth_link *dst = &(dev->data->dev_link);
 672         struct rte_eth_link *src = link;
 673
 674         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 675                                         *(uint64_t *)src) == 0)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 684
 685 #ifndef I40E_GLQF_ORT
 686 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 687 #endif
 688 #ifndef I40E_GLQF_PIT
 689 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 690 #endif
 691 #ifndef I40E_GLQF_L3_MAP
 692 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 693 #endif
 694
 695 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 696 {
 697         /*
 698          * Initialize registers for flexible payload, which should be set by NVM.
 699          * This should be removed from code once it is fixed in NVM.
 700          */
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 712         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 713
 714         /* Initialize registers for parsing packet type of QinQ */
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 716         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 717 }
 718
 719 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 720
 721 /*
 722  * Add a ethertype filter to drop all flow control frames transmitted
 723  * from VSIs.
 724 */
 725 static void
 726 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 727 {
 728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 729         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 731                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 732         int ret;
 733
 734         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 735                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 736                                 pf->main_vsi_seid, 0,
 737                                 TRUE, NULL, NULL);
 738         if (ret)
 739                 PMD_INIT_LOG(ERR,
 740                         "Failed to add filter to drop flow control frames from VSIs.");
 741 }
 742
 743 static int
 744 floating_veb_list_handler(__rte_unused const char *key,
 745                           const char *floating_veb_value,
 746                           void *opaque)
 747 {
 748         int idx = 0;
 749         unsigned int count = 0;
 750         char *end = NULL;
 751         int min, max;
 752         bool *vf_floating_veb = opaque;
 753
 754         while (isblank(*floating_veb_value))
 755                 floating_veb_value++;
 756
 757         /* Reset floating VEB configuration for VFs */
 758         for (idx = 0; idx < I40E_MAX_VF; idx++)
 759                 vf_floating_veb[idx] = false;
 760
 761         min = I40E_MAX_VF;
 762         do {
 763                 while (isblank(*floating_veb_value))
 764                         floating_veb_value++;
 765                 if (*floating_veb_value == '\0')
 766                         return -1;
 767                 errno = 0;
 768                 idx = strtoul(floating_veb_value, &end, 10);
 769                 if (errno || end == NULL)
 770                         return -1;
 771                 while (isblank(*end))
 772                         end++;
 773                 if (*end == '-') {
 774                         min = idx;
 775                 } else if ((*end == ';') || (*end == '\0')) {
 776                         max = idx;
 777                         if (min == I40E_MAX_VF)
 778                                 min = idx;
 779                         if (max >= I40E_MAX_VF)
 780                                 max = I40E_MAX_VF - 1;
 781                         for (idx = min; idx <= max; idx++) {
 782                                 vf_floating_veb[idx] = true;
 783                                 count++;
 784                         }
 785                         min = I40E_MAX_VF;
 786                 } else {
 787                         return -1;
 788                 }
 789                 floating_veb_value = end + 1;
 790         } while (*end != '\0');
 791
 792         if (count == 0)
 793                 return -1;
 794
 795         return 0;
 796 }
 797
 798 static void
 799 config_vf_floating_veb(struct rte_devargs *devargs,
 800                        uint16_t floating_veb,
 801                        bool *vf_floating_veb)
 802 {
 803         struct rte_kvargs *kvlist;
 804         int i;
 805         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 806
 807         if (!floating_veb)
 808                 return;
 809         /* All the VFs attach to the floating VEB by default
 810          * when the floating VEB is enabled.
 811          */
 812         for (i = 0; i < I40E_MAX_VF; i++)
 813                 vf_floating_veb[i] = true;
 814
 815         if (devargs == NULL)
 816                 return;
 817
 818         kvlist = rte_kvargs_parse(devargs->args, NULL);
 819         if (kvlist == NULL)
 820                 return;
 821
 822         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 823                 rte_kvargs_free(kvlist);
 824                 return;
 825         }
 826         /* When the floating_veb_list parameter exists, all the VFs
 827          * will attach to the legacy VEB firstly, then configure VFs
 828          * to the floating VEB according to the floating_veb_list.
 829          */
 830         if (rte_kvargs_process(kvlist, floating_veb_list,
 831                                floating_veb_list_handler,
 832                                vf_floating_veb) < 0) {
 833                 rte_kvargs_free(kvlist);
 834                 return;
 835         }
 836         rte_kvargs_free(kvlist);
 837 }
 838
 839 static int
 840 i40e_check_floating_handler(__rte_unused const char *key,
 841                             const char *value,
 842                             __rte_unused void *opaque)
 843 {
 844         if (strcmp(value, "1"))
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static int
 851 is_floating_veb_supported(struct rte_devargs *devargs)
 852 {
 853         struct rte_kvargs *kvlist;
 854         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 855
 856         if (devargs == NULL)
 857                 return 0;
 858
 859         kvlist = rte_kvargs_parse(devargs->args, NULL);
 860         if (kvlist == NULL)
 861                 return 0;
 862
 863         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 864                 rte_kvargs_free(kvlist);
 865                 return 0;
 866         }
 867         /* Floating VEB is enabled when there's key-value:
 868          * enable_floating_veb=1
 869          */
 870         if (rte_kvargs_process(kvlist, floating_veb_key,
 871                                i40e_check_floating_handler, NULL) < 0) {
 872                 rte_kvargs_free(kvlist);
 873                 return 0;
 874         }
 875         rte_kvargs_free(kvlist);
 876
 877         return 1;
 878 }
 879
 880 static void
 881 config_floating_veb(struct rte_eth_dev *dev)
 882 {
 883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886
 887         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 888
 889         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 890                 pf->floating_veb =
 891                         is_floating_veb_supported(pci_dev->device.devargs);
 892                 config_vf_floating_veb(pci_dev->device.devargs,
 893                                        pf->floating_veb,
 894                                        pf->floating_veb_list);
 895         } else {
 896                 pf->floating_veb = false;
 897         }
 898 }
 899
 900 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 901 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 902
 903 static int
 904 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 905 {
 906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 907         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 908         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 909         int ret;
 910
 911         struct rte_hash_parameters ethertype_hash_params = {
 912                 .name = ethertype_hash_name,
 913                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 914                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 915                 .hash_func = rte_hash_crc,
 916                 .hash_func_init_val = 0,
 917                 .socket_id = rte_socket_id(),
 918         };
 919
 920         /* Initialize ethertype filter rule list and hash */
 921         TAILQ_INIT(&ethertype_rule->ethertype_list);
 922         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 923                  "ethertype_%s", dev->device->name);
 924         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 925         if (!ethertype_rule->hash_table) {
 926                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 927                 return -EINVAL;
 928         }
 929         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 930                                        sizeof(struct i40e_ethertype_filter *) *
 931                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 932                                        0);
 933         if (!ethertype_rule->hash_map) {
 934                 PMD_INIT_LOG(ERR,
 935                              "Failed to allocate memory for ethertype hash map!");
 936                 ret = -ENOMEM;
 937                 goto err_ethertype_hash_map_alloc;
 938         }
 939
 940         return 0;
 941
 942 err_ethertype_hash_map_alloc:
 943         rte_hash_free(ethertype_rule->hash_table);
 944
 945         return ret;
 946 }
 947
 948 static int
 949 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 950 {
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 953         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 954         int ret;
 955
 956         struct rte_hash_parameters tunnel_hash_params = {
 957                 .name = tunnel_hash_name,
 958                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 959                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 960                 .hash_func = rte_hash_crc,
 961                 .hash_func_init_val = 0,
 962                 .socket_id = rte_socket_id(),
 963         };
 964
 965         /* Initialize tunnel filter rule list and hash */
 966         TAILQ_INIT(&tunnel_rule->tunnel_list);
 967         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 968                  "tunnel_%s", dev->device->name);
 969         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 970         if (!tunnel_rule->hash_table) {
 971                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 972                 return -EINVAL;
 973         }
 974         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 975                                     sizeof(struct i40e_tunnel_filter *) *
 976                                     I40E_MAX_TUNNEL_FILTER_NUM,
 977                                     0);
 978         if (!tunnel_rule->hash_map) {
 979                 PMD_INIT_LOG(ERR,
 980                              "Failed to allocate memory for tunnel hash map!");
 981                 ret = -ENOMEM;
 982                 goto err_tunnel_hash_map_alloc;
 983         }
 984
 985         return 0;
 986
 987 err_tunnel_hash_map_alloc:
 988         rte_hash_free(tunnel_rule->hash_table);
 989
 990         return ret;
 991 }
 992
 993 static int
 994 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_fdir_info *fdir_info = &pf->fdir;
 998         char fdir_hash_name[RTE_HASH_NAMESIZE];
 999         int ret;
1000
1001         struct rte_hash_parameters fdir_hash_params = {
1002                 .name = fdir_hash_name,
1003                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1004                 .key_len = sizeof(struct rte_eth_fdir_input),
1005                 .hash_func = rte_hash_crc,
1006                 .hash_func_init_val = 0,
1007                 .socket_id = rte_socket_id(),
1008         };
1009
1010         /* Initialize flow director filter rule list and hash */
1011         TAILQ_INIT(&fdir_info->fdir_list);
1012         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1013                  "fdir_%s", dev->device->name);
1014         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1015         if (!fdir_info->hash_table) {
1016                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1017                 return -EINVAL;
1018         }
1019         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1020                                           sizeof(struct i40e_fdir_filter *) *
1021                                           I40E_MAX_FDIR_FILTER_NUM,
1022                                           0);
1023         if (!fdir_info->hash_map) {
1024                 PMD_INIT_LOG(ERR,
1025                              "Failed to allocate memory for fdir hash map!");
1026                 ret = -ENOMEM;
1027                 goto err_fdir_hash_map_alloc;
1028         }
1029         return 0;
1030
1031 err_fdir_hash_map_alloc:
1032         rte_hash_free(fdir_info->hash_table);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 {
1040         struct rte_pci_device *pci_dev;
1041         struct rte_intr_handle *intr_handle;
1042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044         struct i40e_vsi *vsi;
1045         int ret;
1046         uint32_t len;
1047         uint8_t aq_fail = 0;
1048
1049         PMD_INIT_FUNC_TRACE();
1050
1051         dev->dev_ops = &i40e_eth_dev_ops;
1052         dev->rx_pkt_burst = i40e_recv_pkts;
1053         dev->tx_pkt_burst = i40e_xmit_pkts;
1054         dev->tx_pkt_prepare = i40e_prep_pkts;
1055
1056         /* for secondary processes, we don't initialise any further as primary
1057          * has already done this work. Only check we don't need a different
1058          * RX function */
1059         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1060                 i40e_set_rx_function(dev);
1061                 i40e_set_tx_function(dev);
1062                 return 0;
1063         }
1064         i40e_set_default_ptype_table(dev);
1065         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1066         intr_handle = &pci_dev->intr_handle;
1067
1068         rte_eth_copy_pci_info(dev, pci_dev);
1069         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070
1071         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072         pf->adapter->eth_dev = dev;
1073         pf->dev_data = dev->data;
1074
1075         hw->back = I40E_PF_TO_ADAPTER(pf);
1076         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1077         if (!hw->hw_addr) {
1078                 PMD_INIT_LOG(ERR,
1079                         "Hardware is not available, as address is NULL");
1080                 return -ENODEV;
1081         }
1082
1083         hw->vendor_id = pci_dev->id.vendor_id;
1084         hw->device_id = pci_dev->id.device_id;
1085         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1086         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1087         hw->bus.device = pci_dev->addr.devid;
1088         hw->bus.func = pci_dev->addr.function;
1089         hw->adapter_stopped = 0;
1090
1091         /* Make sure all is clean before doing PF reset */
1092         i40e_clear_hw(hw);
1093
1094         /* Initialize the hardware */
1095         i40e_hw_init(dev);
1096
1097         /* Reset here to make sure all is clean for each PF */
1098         ret = i40e_pf_reset(hw);
1099         if (ret) {
1100                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1101                 return ret;
1102         }
1103
1104         /* Initialize the shared code (base driver) */
1105         ret = i40e_init_shared_code(hw);
1106         if (ret) {
1107                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1108                 return ret;
1109         }
1110
1111         /*
1112          * To work around the NVM issue, initialize registers
1113          * for flexible payload and packet type of QinQ by
1114          * software. It should be removed once issues are fixed
1115          * in NVM.
1116          */
1117         i40e_GLQF_reg_init(hw);
1118
1119         /* Initialize the input set for filters (hash and fd) to default value */
1120         i40e_filter_input_set_init(pf);
1121
1122         /* Initialize the parameters for adminq */
1123         i40e_init_adminq_parameter(hw);
1124         ret = i40e_init_adminq(hw);
1125         if (ret != I40E_SUCCESS) {
1126                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1127                 return -EIO;
1128         }
1129         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1130                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1131                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1132                      ((hw->nvm.version >> 12) & 0xf),
1133                      ((hw->nvm.version >> 4) & 0xff),
1134                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135
1136         /* initialise the L3_MAP register */
1137         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1138                                    0x00000028,  NULL);
1139         if (ret)
1140                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141
1142         /* Need the special FW version to support floating VEB */
1143         config_floating_veb(dev);
1144         /* Clear PXE mode */
1145         i40e_clear_pxe_mode(hw);
1146         i40e_dev_sync_phy_type(hw);
1147
1148         /*
1149          * On X710, performance number is far from the expectation on recent
1150          * firmware versions. The fix for this issue may not be integrated in
1151          * the following firmware version. So the workaround in software driver
1152          * is needed. It needs to modify the initial values of 3 internal only
1153          * registers. Note that the workaround can be removed when it is fixed
1154          * in firmware in the future.
1155          */
1156         i40e_configure_registers(hw);
1157
1158         /* Get hw capabilities */
1159         ret = i40e_get_cap(hw);
1160         if (ret != I40E_SUCCESS) {
1161                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1162                 goto err_get_capabilities;
1163         }
1164
1165         /* Initialize parameters for PF */
1166         ret = i40e_pf_parameter_init(dev);
1167         if (ret != 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1169                 goto err_parameter_init;
1170         }
1171
1172         /* Initialize the queue management */
1173         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174         if (ret < 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1176                 goto err_qp_pool_init;
1177         }
1178         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1179                                 hw->func_caps.num_msix_vectors - 1);
1180         if (ret < 0) {
1181                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1182                 goto err_msix_pool_init;
1183         }
1184
1185         /* Initialize lan hmc */
1186         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1187                                 hw->func_caps.num_rx_qp, 0, 0);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1190                 goto err_init_lan_hmc;
1191         }
1192
1193         /* Configure lan hmc */
1194         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1197                 goto err_configure_lan_hmc;
1198         }
1199
1200         /* Get and check the mac address */
1201         i40e_get_mac_addr(hw, hw->mac.addr);
1202         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "mac address is not valid");
1204                 ret = -EIO;
1205                 goto err_get_mac_addr;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1209                         (struct ether_addr *) hw->mac.perm_addr);
1210
1211         /* Disable flow control */
1212         hw->fc.requested_mode = I40E_FC_NONE;
1213         i40e_set_fc(hw, &aq_fail, TRUE);
1214
1215         /* Set the global registers with default ether type value */
1216         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1217         if (ret != I40E_SUCCESS) {
1218                 PMD_INIT_LOG(ERR,
1219                         "Failed to set the default outer VLAN ether type");
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* PF setup, which includes VSI setup */
1224         ret = i40e_pf_setup(pf);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1227                 goto err_setup_pf_switch;
1228         }
1229
1230         /* reset all stats of the device, including pf and main vsi */
1231         i40e_dev_stats_reset(dev);
1232
1233         vsi = pf->main_vsi;
1234
1235         /* Disable double vlan by default */
1236         i40e_vsi_config_double_vlan(vsi, FALSE);
1237
1238         /* Disable S-TAG identification when floating_veb is disabled */
1239         if (!pf->floating_veb) {
1240                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1241                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1242                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1243                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1244                 }
1245         }
1246
1247         if (!vsi->max_macaddrs)
1248                 len = ETHER_ADDR_LEN;
1249         else
1250                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251
1252         /* Should be after VSI initialized */
1253         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1254         if (!dev->data->mac_addrs) {
1255                 PMD_INIT_LOG(ERR,
1256                         "Failed to allocated memory for storing mac address");
1257                 goto err_mac_alloc;
1258         }
1259         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1260                                         &dev->data->mac_addrs[0]);
1261
1262         /* Init dcb to sw mode by default */
1263         ret = i40e_dcb_init_configure(dev, TRUE);
1264         if (ret != I40E_SUCCESS) {
1265                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1266                 pf->flags &= ~I40E_FLAG_DCB;
1267         }
1268         /* Update HW struct after DCB configuration */
1269         i40e_get_cap(hw);
1270
1271         /* initialize pf host driver to setup SRIOV resource if applicable */
1272         i40e_pf_host_init(dev);
1273
1274         /* register callback func to eal lib */
1275         rte_intr_callback_register(intr_handle,
1276                                    i40e_dev_interrupt_handler, dev);
1277
1278         /* configure and enable device interrupt */
1279         i40e_pf_config_irq0(hw, TRUE);
1280         i40e_pf_enable_irq0(hw);
1281
1282         /* enable uio intr after callback register */
1283         rte_intr_enable(intr_handle);
1284         /*
1285          * Add an ethertype filter to drop all flow control frames transmitted
1286          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1287          * frames to wire.
1288          */
1289         i40e_add_tx_flow_control_drop_filter(pf);
1290
1291         /* Set the max frame size to 0x2600 by default,
1292          * in case other drivers changed the default value.
1293          */
1294         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295
1296         /* initialize mirror rule list */
1297         TAILQ_INIT(&pf->mirror_list);
1298
1299         /* initialize Traffic Manager configuration */
1300         i40e_tm_conf_init(dev);
1301
1302         ret = i40e_init_ethtype_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_ethtype_filter_list;
1305         ret = i40e_init_tunnel_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_tunnel_filter_list;
1308         ret = i40e_init_fdir_filter_list(dev);
1309         if (ret < 0)
1310                 goto err_init_fdir_filter_list;
1311
1312         return 0;
1313
1314 err_init_fdir_filter_list:
1315         rte_free(pf->tunnel.hash_table);
1316         rte_free(pf->tunnel.hash_map);
1317 err_init_tunnel_filter_list:
1318         rte_free(pf->ethertype.hash_table);
1319         rte_free(pf->ethertype.hash_map);
1320 err_init_ethtype_filter_list:
1321         rte_free(dev->data->mac_addrs);
1322 err_mac_alloc:
1323         i40e_vsi_release(pf->main_vsi);
1324 err_setup_pf_switch:
1325 err_get_mac_addr:
1326 err_configure_lan_hmc:
1327         (void)i40e_shutdown_lan_hmc(hw);
1328 err_init_lan_hmc:
1329         i40e_res_pool_destroy(&pf->msix_pool);
1330 err_msix_pool_init:
1331         i40e_res_pool_destroy(&pf->qp_pool);
1332 err_qp_pool_init:
1333 err_parameter_init:
1334 err_get_capabilities:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         /* Remove all Traffic Manager configuration */
1465         i40e_tm_conf_uninit(dev);
1466
1467         return 0;
1468 }
1469
1470 static int
1471 i40e_dev_configure(struct rte_eth_dev *dev)
1472 {
1473         struct i40e_adapter *ad =
1474                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1478         int i, ret;
1479
1480         ret = i40e_dev_sync_phy_type(hw);
1481         if (ret)
1482                 return ret;
1483
1484         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1485          * bulk allocation or vector Rx preconditions we will reset it.
1486          */
1487         ad->rx_bulk_alloc_allowed = true;
1488         ad->rx_vec_allowed = true;
1489         ad->tx_simple_allowed = true;
1490         ad->tx_vec_allowed = true;
1491
1492         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1493                 ret = i40e_fdir_setup(pf);
1494                 if (ret != I40E_SUCCESS) {
1495                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1496                         return -ENOTSUP;
1497                 }
1498                 ret = i40e_fdir_configure(dev);
1499                 if (ret < 0) {
1500                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1501                         goto err;
1502                 }
1503         } else
1504                 i40e_fdir_teardown(pf);
1505
1506         ret = i40e_dev_init_vlan(dev);
1507         if (ret < 0)
1508                 goto err;
1509
1510         /* VMDQ setup.
1511          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1512          *  RSS setting have different requirements.
1513          *  General PMD driver call sequence are NIC init, configure,
1514          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1515          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1516          *  applicable. So, VMDQ setting has to be done before
1517          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1518          *  For RSS setting, it will try to calculate actual configured RX queue
1519          *  number, which will be available after rx_queue_setup(). dev_start()
1520          *  function is good to place RSS setup.
1521          */
1522         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1523                 ret = i40e_vmdq_setup(dev);
1524                 if (ret)
1525                         goto err;
1526         }
1527
1528         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1529                 ret = i40e_dcb_setup(dev);
1530                 if (ret) {
1531                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1532                         goto err_dcb;
1533                 }
1534         }
1535
1536         TAILQ_INIT(&pf->flow_list);
1537
1538         return 0;
1539
1540 err_dcb:
1541         /* need to release vmdq resource if exists */
1542         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1543                 i40e_vsi_release(pf->vmdq[i].vsi);
1544                 pf->vmdq[i].vsi = NULL;
1545         }
1546         rte_free(pf->vmdq);
1547         pf->vmdq = NULL;
1548 err:
1549         /* need to release fdir resource if exists */
1550         i40e_fdir_teardown(pf);
1551         return ret;
1552 }
1553
1554 void
1555 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1556 {
1557         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1558         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1559         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1561         uint16_t msix_vect = vsi->msix_intr;
1562         uint16_t i;
1563
1564         for (i = 0; i < vsi->nb_qps; i++) {
1565                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1566                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1567                 rte_wmb();
1568         }
1569
1570         if (vsi->type != I40E_VSI_SRIOV) {
1571                 if (!rte_intr_allow_others(intr_handle)) {
1572                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1573                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1574                         I40E_WRITE_REG(hw,
1575                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1576                                        0);
1577                 } else {
1578                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1579                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1580                         I40E_WRITE_REG(hw,
1581                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1582                                                        msix_vect - 1), 0);
1583                 }
1584         } else {
1585                 uint32_t reg;
1586                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1587                         vsi->user_param + (msix_vect - 1);
1588
1589                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1590                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1591         }
1592         I40E_WRITE_FLUSH(hw);
1593 }
1594
1595 static void
1596 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1597                        int base_queue, int nb_queue)
1598 {
1599         int i;
1600         uint32_t val;
1601         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1602
1603         /* Bind all RX queues to allocated MSIX interrupt */
1604         for (i = 0; i < nb_queue; i++) {
1605                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1606                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1607                         ((base_queue + i + 1) <<
1608                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1609                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1610                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1611
1612                 if (i == nb_queue - 1)
1613                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1614                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1615         }
1616
1617         /* Write first RX queue to Link list register as the head element */
1618         if (vsi->type != I40E_VSI_SRIOV) {
1619                 uint16_t interval =
1620                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1621
1622                 if (msix_vect == I40E_MISC_VEC_ID) {
1623                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1624                                        (base_queue <<
1625                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1628                         I40E_WRITE_REG(hw,
1629                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1630                                        interval);
1631                 } else {
1632                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1633                                        (base_queue <<
1634                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1635                                        (0x0 <<
1636                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1637                         I40E_WRITE_REG(hw,
1638                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1639                                                        msix_vect - 1),
1640                                        interval);
1641                 }
1642         } else {
1643                 uint32_t reg;
1644
1645                 if (msix_vect == I40E_MISC_VEC_ID) {
1646                         I40E_WRITE_REG(hw,
1647                                        I40E_VPINT_LNKLST0(vsi->user_param),
1648                                        (base_queue <<
1649                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1652                 } else {
1653                         /* num_msix_vectors_vf needs to minus irq0 */
1654                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1655                                 vsi->user_param + (msix_vect - 1);
1656
1657                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1658                                        (base_queue <<
1659                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1660                                        (0x0 <<
1661                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1662                 }
1663         }
1664
1665         I40E_WRITE_FLUSH(hw);
1666 }
1667
1668 void
1669 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1670 {
1671         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1673         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1674         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1675         uint16_t msix_vect = vsi->msix_intr;
1676         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1677         uint16_t queue_idx = 0;
1678         int record = 0;
1679         uint32_t val;
1680         int i;
1681
1682         for (i = 0; i < vsi->nb_qps; i++) {
1683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1684                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1685         }
1686
1687         /* INTENA flag is not auto-cleared for interrupt */
1688         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1689         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1690                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1691                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1692         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1693
1694         /* VF bind interrupt */
1695         if (vsi->type == I40E_VSI_SRIOV) {
1696                 __vsi_queues_bind_intr(vsi, msix_vect,
1697                                        vsi->base_queue, vsi->nb_qps);
1698                 return;
1699         }
1700
1701         /* PF & VMDq bind interrupt */
1702         if (rte_intr_dp_is_en(intr_handle)) {
1703                 if (vsi->type == I40E_VSI_MAIN) {
1704                         queue_idx = 0;
1705                         record = 1;
1706                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1707                         struct i40e_vsi *main_vsi =
1708                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1709                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1710                         record = 1;
1711                 }
1712         }
1713
1714         for (i = 0; i < vsi->nb_used_qps; i++) {
1715                 if (nb_msix <= 1) {
1716                         if (!rte_intr_allow_others(intr_handle))
1717                                 /* allow to share MISC_VEC_ID */
1718                                 msix_vect = I40E_MISC_VEC_ID;
1719
1720                         /* no enough msix_vect, map all to one */
1721                         __vsi_queues_bind_intr(vsi, msix_vect,
1722                                                vsi->base_queue + i,
1723                                                vsi->nb_used_qps - i);
1724                         for (; !!record && i < vsi->nb_used_qps; i++)
1725                                 intr_handle->intr_vec[queue_idx + i] =
1726                                         msix_vect;
1727                         break;
1728                 }
1729                 /* 1:1 queue/msix_vect mapping */
1730                 __vsi_queues_bind_intr(vsi, msix_vect,
1731                                        vsi->base_queue + i, 1);
1732                 if (!!record)
1733                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734
1735                 msix_vect++;
1736                 nb_msix--;
1737         }
1738 }
1739
1740 static void
1741 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1742 {
1743         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1745         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1747         uint16_t interval = i40e_calc_itr_interval(\
1748                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1749         uint16_t msix_intr, i;
1750
1751         if (rte_intr_allow_others(intr_handle))
1752                 for (i = 0; i < vsi->nb_msix; i++) {
1753                         msix_intr = vsi->msix_intr + i;
1754                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1755                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1756                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1757                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1758                                 (interval <<
1759                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1760                 }
1761         else
1762                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1763                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1764                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1765                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1766                                (interval <<
1767                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1768
1769         I40E_WRITE_FLUSH(hw);
1770 }
1771
1772 static void
1773 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t msix_intr, i;
1780
1781         if (rte_intr_allow_others(intr_handle))
1782                 for (i = 0; i < vsi->nb_msix; i++) {
1783                         msix_intr = vsi->msix_intr + i;
1784                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1785                                        0);
1786                 }
1787         else
1788                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1789
1790         I40E_WRITE_FLUSH(hw);
1791 }
1792
1793 static inline uint8_t
1794 i40e_parse_link_speeds(uint16_t link_speeds)
1795 {
1796         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1797
1798         if (link_speeds & ETH_LINK_SPEED_40G)
1799                 link_speed |= I40E_LINK_SPEED_40GB;
1800         if (link_speeds & ETH_LINK_SPEED_25G)
1801                 link_speed |= I40E_LINK_SPEED_25GB;
1802         if (link_speeds & ETH_LINK_SPEED_20G)
1803                 link_speed |= I40E_LINK_SPEED_20GB;
1804         if (link_speeds & ETH_LINK_SPEED_10G)
1805                 link_speed |= I40E_LINK_SPEED_10GB;
1806         if (link_speeds & ETH_LINK_SPEED_1G)
1807                 link_speed |= I40E_LINK_SPEED_1GB;
1808         if (link_speeds & ETH_LINK_SPEED_100M)
1809                 link_speed |= I40E_LINK_SPEED_100MB;
1810
1811         return link_speed;
1812 }
1813
1814 static int
1815 i40e_phy_conf_link(struct i40e_hw *hw,
1816                    uint8_t abilities,
1817                    uint8_t force_speed,
1818                    bool is_up)
1819 {
1820         enum i40e_status_code status;
1821         struct i40e_aq_get_phy_abilities_resp phy_ab;
1822         struct i40e_aq_set_phy_config phy_conf;
1823         enum i40e_aq_phy_type cnt;
1824         uint32_t phy_type_mask = 0;
1825
1826         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1827                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1828                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1829                         I40E_AQ_PHY_FLAG_LOW_POWER;
1830         const uint8_t advt = I40E_LINK_SPEED_40GB |
1831                         I40E_LINK_SPEED_25GB |
1832                         I40E_LINK_SPEED_10GB |
1833                         I40E_LINK_SPEED_1GB |
1834                         I40E_LINK_SPEED_100MB;
1835         int ret = -ENOTSUP;
1836
1837
1838         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1839                                               NULL);
1840         if (status)
1841                 return ret;
1842
1843         /* If link already up, no need to set up again */
1844         if (is_up && phy_ab.phy_type != 0)
1845                 return I40E_SUCCESS;
1846
1847         memset(&phy_conf, 0, sizeof(phy_conf));
1848
1849         /* bits 0-2 use the values from get_phy_abilities_resp */
1850         abilities &= ~mask;
1851         abilities |= phy_ab.abilities & mask;
1852
1853         /* update ablities and speed */
1854         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1855                 phy_conf.link_speed = advt;
1856         else
1857                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1858
1859         phy_conf.abilities = abilities;
1860
1861
1862
1863         /* To enable link, phy_type mask needs to include each type */
1864         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1865                 phy_type_mask |= 1 << cnt;
1866
1867         /* use get_phy_abilities_resp value for the rest */
1868         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1869         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1870                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1871                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1872         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1873         phy_conf.eee_capability = phy_ab.eee_capability;
1874         phy_conf.eeer = phy_ab.eeer_val;
1875         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1876
1877         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1878                     phy_ab.abilities, phy_ab.link_speed);
1879         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1880                     phy_conf.abilities, phy_conf.link_speed);
1881
1882         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1883         if (status)
1884                 return ret;
1885
1886         return I40E_SUCCESS;
1887 }
1888
1889 static int
1890 i40e_apply_link_speed(struct rte_eth_dev *dev)
1891 {
1892         uint8_t speed;
1893         uint8_t abilities = 0;
1894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895         struct rte_eth_conf *conf = &dev->data->dev_conf;
1896
1897         speed = i40e_parse_link_speeds(conf->link_speeds);
1898         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1899         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1900                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1901         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1902
1903         return i40e_phy_conf_link(hw, abilities, speed, true);
1904 }
1905
1906 static int
1907 i40e_dev_start(struct rte_eth_dev *dev)
1908 {
1909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         struct i40e_vsi *main_vsi = pf->main_vsi;
1912         int ret, i;
1913         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1914         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1915         uint32_t intr_vector = 0;
1916         struct i40e_vsi *vsi;
1917
1918         hw->adapter_stopped = 0;
1919
1920         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1921                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1922                              dev->data->port_id);
1923                 return -EINVAL;
1924         }
1925
1926         rte_intr_disable(intr_handle);
1927
1928         if ((rte_intr_cap_multiple(intr_handle) ||
1929              !RTE_ETH_DEV_SRIOV(dev).active) &&
1930             dev->data->dev_conf.intr_conf.rxq != 0) {
1931                 intr_vector = dev->data->nb_rx_queues;
1932                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1933                 if (ret)
1934                         return ret;
1935         }
1936
1937         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1938                 intr_handle->intr_vec =
1939                         rte_zmalloc("intr_vec",
1940                                     dev->data->nb_rx_queues * sizeof(int),
1941                                     0);
1942                 if (!intr_handle->intr_vec) {
1943                         PMD_INIT_LOG(ERR,
1944                                 "Failed to allocate %d rx_queues intr_vec",
1945                                 dev->data->nb_rx_queues);
1946                         return -ENOMEM;
1947                 }
1948         }
1949
1950         /* Initialize VSI */
1951         ret = i40e_dev_rxtx_init(pf);
1952         if (ret != I40E_SUCCESS) {
1953                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1954                 goto err_up;
1955         }
1956
1957         /* Map queues with MSIX interrupt */
1958         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1959                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1960         i40e_vsi_queues_bind_intr(main_vsi);
1961         i40e_vsi_enable_queues_intr(main_vsi);
1962
1963         /* Map VMDQ VSI queues with MSIX interrupt */
1964         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1965                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1966                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1967                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1968         }
1969
1970         /* enable FDIR MSIX interrupt */
1971         if (pf->fdir.fdir_vsi) {
1972                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1973                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1974         }
1975
1976         /* Enable all queues which have been configured */
1977         ret = i40e_dev_switch_queues(pf, TRUE);
1978         if (ret != I40E_SUCCESS) {
1979                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1980                 goto err_up;
1981         }
1982
1983         /* Enable receiving broadcast packets */
1984         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1985         if (ret != I40E_SUCCESS)
1986                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1987
1988         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1990                                                 true, NULL);
1991                 if (ret != I40E_SUCCESS)
1992                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1993         }
1994
1995         /* Enable the VLAN promiscuous mode. */
1996         if (pf->vfs) {
1997                 for (i = 0; i < pf->vf_num; i++) {
1998                         vsi = pf->vfs[i].vsi;
1999                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2000                                                      true, NULL);
2001                 }
2002         }
2003
2004         /* Apply link configure */
2005         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2006                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2007                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2008                                 ETH_LINK_SPEED_40G)) {
2009                 PMD_DRV_LOG(ERR, "Invalid link setting");
2010                 goto err_up;
2011         }
2012         ret = i40e_apply_link_speed(dev);
2013         if (I40E_SUCCESS != ret) {
2014                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2015                 goto err_up;
2016         }
2017
2018         if (!rte_intr_allow_others(intr_handle)) {
2019                 rte_intr_callback_unregister(intr_handle,
2020                                              i40e_dev_interrupt_handler,
2021                                              (void *)dev);
2022                 /* configure and enable device interrupt */
2023                 i40e_pf_config_irq0(hw, FALSE);
2024                 i40e_pf_enable_irq0(hw);
2025
2026                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2027                         PMD_INIT_LOG(INFO,
2028                                 "lsc won't enable because of no intr multiplex");
2029         } else {
2030                 ret = i40e_aq_set_phy_int_mask(hw,
2031                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2032                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2033                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2034                 if (ret != I40E_SUCCESS)
2035                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2036
2037                 /* Call get_link_info aq commond to enable/disable LSE */
2038                 i40e_dev_link_update(dev, 0);
2039         }
2040
2041         /* enable uio intr after callback register */
2042         rte_intr_enable(intr_handle);
2043
2044         i40e_filter_restore(pf);
2045
2046         if (pf->tm_conf.root && !pf->tm_conf.committed)
2047                 PMD_DRV_LOG(WARNING,
2048                             "please call hierarchy_commit() "
2049                             "before starting the port");
2050
2051         return I40E_SUCCESS;
2052
2053 err_up:
2054         i40e_dev_switch_queues(pf, FALSE);
2055         i40e_dev_clear_queues(dev);
2056
2057         return ret;
2058 }
2059
2060 static void
2061 i40e_dev_stop(struct rte_eth_dev *dev)
2062 {
2063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2064         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct i40e_vsi *main_vsi = pf->main_vsi;
2066         struct i40e_mirror_rule *p_mirror;
2067         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2068         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2069         int i;
2070
2071         if (hw->adapter_stopped == 1)
2072                 return;
2073         /* Disable all queues */
2074         i40e_dev_switch_queues(pf, FALSE);
2075
2076         /* un-map queues with interrupt registers */
2077         i40e_vsi_disable_queues_intr(main_vsi);
2078         i40e_vsi_queues_unbind_intr(main_vsi);
2079
2080         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2081                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2082                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2083         }
2084
2085         if (pf->fdir.fdir_vsi) {
2086                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2087                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2088         }
2089         /* Clear all queues and release memory */
2090         i40e_dev_clear_queues(dev);
2091
2092         /* Set link down */
2093         i40e_dev_set_link_down(dev);
2094
2095         /* Remove all mirror rules */
2096         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2097                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2098                 rte_free(p_mirror);
2099         }
2100         pf->nb_mirror_rule = 0;
2101
2102         if (!rte_intr_allow_others(intr_handle))
2103                 /* resume to the default handler */
2104                 rte_intr_callback_register(intr_handle,
2105                                            i40e_dev_interrupt_handler,
2106                                            (void *)dev);
2107
2108         /* Clean datapath event and queue/vec mapping */
2109         rte_intr_efd_disable(intr_handle);
2110         if (intr_handle->intr_vec) {
2111                 rte_free(intr_handle->intr_vec);
2112                 intr_handle->intr_vec = NULL;
2113         }
2114
2115         /* reset hierarchy commit */
2116         pf->tm_conf.committed = false;
2117
2118         hw->adapter_stopped = 1;
2119 }
2120
2121 static void
2122 i40e_dev_close(struct rte_eth_dev *dev)
2123 {
2124         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2128         uint32_t reg;
2129         int i;
2130
2131         PMD_INIT_FUNC_TRACE();
2132
2133         i40e_dev_stop(dev);
2134         i40e_dev_free_queues(dev);
2135
2136         /* Disable interrupt */
2137         i40e_pf_disable_irq0(hw);
2138         rte_intr_disable(intr_handle);
2139
2140         /* shutdown and destroy the HMC */
2141         i40e_shutdown_lan_hmc(hw);
2142
2143         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2144                 i40e_vsi_release(pf->vmdq[i].vsi);
2145                 pf->vmdq[i].vsi = NULL;
2146         }
2147         rte_free(pf->vmdq);
2148         pf->vmdq = NULL;
2149
2150         /* release all the existing VSIs and VEBs */
2151         i40e_fdir_teardown(pf);
2152         i40e_vsi_release(pf->main_vsi);
2153
2154         /* shutdown the adminq */
2155         i40e_aq_queue_shutdown(hw, true);
2156         i40e_shutdown_adminq(hw);
2157
2158         i40e_res_pool_destroy(&pf->qp_pool);
2159         i40e_res_pool_destroy(&pf->msix_pool);
2160
2161         /* force a PF reset to clean anything leftover */
2162         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2163         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2164                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2165         I40E_WRITE_FLUSH(hw);
2166 }
2167
2168 static void
2169 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2170 {
2171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         struct i40e_vsi *vsi = pf->main_vsi;
2174         int status;
2175
2176         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2177                                                      true, NULL, true);
2178         if (status != I40E_SUCCESS)
2179                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2180
2181         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2182                                                         TRUE, NULL);
2183         if (status != I40E_SUCCESS)
2184                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2185
2186 }
2187
2188 static void
2189 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2190 {
2191         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2192         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         struct i40e_vsi *vsi = pf->main_vsi;
2194         int status;
2195
2196         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2197                                                      false, NULL, true);
2198         if (status != I40E_SUCCESS)
2199                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2200
2201         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2202                                                         false, NULL);
2203         if (status != I40E_SUCCESS)
2204                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2205 }
2206
2207 static void
2208 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2209 {
2210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         struct i40e_vsi *vsi = pf->main_vsi;
2213         int ret;
2214
2215         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2216         if (ret != I40E_SUCCESS)
2217                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2218 }
2219
2220 static void
2221 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2222 {
2223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2224         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225         struct i40e_vsi *vsi = pf->main_vsi;
2226         int ret;
2227
2228         if (dev->data->promiscuous == 1)
2229                 return; /* must remain in all_multicast mode */
2230
2231         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2232                                 vsi->seid, FALSE, NULL);
2233         if (ret != I40E_SUCCESS)
2234                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2235 }
2236
2237 /*
2238  * Set device link up.
2239  */
2240 static int
2241 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2242 {
2243         /* re-apply link speed setting */
2244         return i40e_apply_link_speed(dev);
2245 }
2246
2247 /*
2248  * Set device link down.
2249  */
2250 static int
2251 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2252 {
2253         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2254         uint8_t abilities = 0;
2255         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2256
2257         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2258         return i40e_phy_conf_link(hw, abilities, speed, false);
2259 }
2260
2261 int
2262 i40e_dev_link_update(struct rte_eth_dev *dev,
2263                      int wait_to_complete)
2264 {
2265 #define CHECK_INTERVAL 100  /* 100ms */
2266 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2268         struct i40e_link_status link_status;
2269         struct rte_eth_link link, old;
2270         int status;
2271         unsigned rep_cnt = MAX_REPEAT_TIME;
2272         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2273
2274         memset(&link, 0, sizeof(link));
2275         memset(&old, 0, sizeof(old));
2276         memset(&link_status, 0, sizeof(link_status));
2277         rte_i40e_dev_atomic_read_link_status(dev, &old);
2278
2279         do {
2280                 /* Get link status information from hardware */
2281                 status = i40e_aq_get_link_info(hw, enable_lse,
2282                                                 &link_status, NULL);
2283                 if (status != I40E_SUCCESS) {
2284                         link.link_speed = ETH_SPEED_NUM_100M;
2285                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2286                         PMD_DRV_LOG(ERR, "Failed to get link info");
2287                         goto out;
2288                 }
2289
2290                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2291                 if (!wait_to_complete || link.link_status)
2292                         break;
2293
2294                 rte_delay_ms(CHECK_INTERVAL);
2295         } while (--rep_cnt);
2296
2297         if (!link.link_status)
2298                 goto out;
2299
2300         /* i40e uses full duplex only */
2301         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2302
2303         /* Parse the link status */
2304         switch (link_status.link_speed) {
2305         case I40E_LINK_SPEED_100MB:
2306                 link.link_speed = ETH_SPEED_NUM_100M;
2307                 break;
2308         case I40E_LINK_SPEED_1GB:
2309                 link.link_speed = ETH_SPEED_NUM_1G;
2310                 break;
2311         case I40E_LINK_SPEED_10GB:
2312                 link.link_speed = ETH_SPEED_NUM_10G;
2313                 break;
2314         case I40E_LINK_SPEED_20GB:
2315                 link.link_speed = ETH_SPEED_NUM_20G;
2316                 break;
2317         case I40E_LINK_SPEED_25GB:
2318                 link.link_speed = ETH_SPEED_NUM_25G;
2319                 break;
2320         case I40E_LINK_SPEED_40GB:
2321                 link.link_speed = ETH_SPEED_NUM_40G;
2322                 break;
2323         default:
2324                 link.link_speed = ETH_SPEED_NUM_100M;
2325                 break;
2326         }
2327
2328         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2329                         ETH_LINK_SPEED_FIXED);
2330
2331 out:
2332         rte_i40e_dev_atomic_write_link_status(dev, &link);
2333         if (link.link_status == old.link_status)
2334                 return -1;
2335
2336         i40e_notify_all_vfs_link_status(dev);
2337
2338         return 0;
2339 }
2340
2341 /* Get all the statistics of a VSI */
2342 void
2343 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2344 {
2345         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2346         struct i40e_eth_stats *nes = &vsi->eth_stats;
2347         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2348         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2349
2350         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2351                             vsi->offset_loaded, &oes->rx_bytes,
2352                             &nes->rx_bytes);
2353         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2354                             vsi->offset_loaded, &oes->rx_unicast,
2355                             &nes->rx_unicast);
2356         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2357                             vsi->offset_loaded, &oes->rx_multicast,
2358                             &nes->rx_multicast);
2359         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2360                             vsi->offset_loaded, &oes->rx_broadcast,
2361                             &nes->rx_broadcast);
2362         /* exclude CRC bytes */
2363         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2364                 nes->rx_broadcast) * ETHER_CRC_LEN;
2365
2366         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2367                             &oes->rx_discards, &nes->rx_discards);
2368         /* GLV_REPC not supported */
2369         /* GLV_RMPC not supported */
2370         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2371                             &oes->rx_unknown_protocol,
2372                             &nes->rx_unknown_protocol);
2373         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2374                             vsi->offset_loaded, &oes->tx_bytes,
2375                             &nes->tx_bytes);
2376         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2377                             vsi->offset_loaded, &oes->tx_unicast,
2378                             &nes->tx_unicast);
2379         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2380                             vsi->offset_loaded, &oes->tx_multicast,
2381                             &nes->tx_multicast);
2382         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2383                             vsi->offset_loaded,  &oes->tx_broadcast,
2384                             &nes->tx_broadcast);
2385         /* GLV_TDPC not supported */
2386         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2387                             &oes->tx_errors, &nes->tx_errors);
2388         vsi->offset_loaded = true;
2389
2390         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2391                     vsi->vsi_id);
2392         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2393         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2394         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2395         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2396         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2397         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2398                     nes->rx_unknown_protocol);
2399         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2400         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2401         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2402         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2403         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2404         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2405         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2406                     vsi->vsi_id);
2407 }
2408
2409 static void
2410 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2411 {
2412         unsigned int i;
2413         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2414         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2415
2416         /* Get rx/tx bytes of internal transfer packets */
2417         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2418                         I40E_GLV_GORCL(hw->port),
2419                         pf->offset_loaded,
2420                         &pf->internal_stats_offset.rx_bytes,
2421                         &pf->internal_stats.rx_bytes);
2422
2423         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2424                         I40E_GLV_GOTCL(hw->port),
2425                         pf->offset_loaded,
2426                         &pf->internal_stats_offset.tx_bytes,
2427                         &pf->internal_stats.tx_bytes);
2428         /* Get total internal rx packet count */
2429         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2430                             I40E_GLV_UPRCL(hw->port),
2431                             pf->offset_loaded,
2432                             &pf->internal_stats_offset.rx_unicast,
2433                             &pf->internal_stats.rx_unicast);
2434         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2435                             I40E_GLV_MPRCL(hw->port),
2436                             pf->offset_loaded,
2437                             &pf->internal_stats_offset.rx_multicast,
2438                             &pf->internal_stats.rx_multicast);
2439         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2440                             I40E_GLV_BPRCL(hw->port),
2441                             pf->offset_loaded,
2442                             &pf->internal_stats_offset.rx_broadcast,
2443                             &pf->internal_stats.rx_broadcast);
2444
2445         /* exclude CRC size */
2446         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2447                 pf->internal_stats.rx_multicast +
2448                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2449
2450         /* Get statistics of struct i40e_eth_stats */
2451         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2452                             I40E_GLPRT_GORCL(hw->port),
2453                             pf->offset_loaded, &os->eth.rx_bytes,
2454                             &ns->eth.rx_bytes);
2455         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2456                             I40E_GLPRT_UPRCL(hw->port),
2457                             pf->offset_loaded, &os->eth.rx_unicast,
2458                             &ns->eth.rx_unicast);
2459         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2460                             I40E_GLPRT_MPRCL(hw->port),
2461                             pf->offset_loaded, &os->eth.rx_multicast,
2462                             &ns->eth.rx_multicast);
2463         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2464                             I40E_GLPRT_BPRCL(hw->port),
2465                             pf->offset_loaded, &os->eth.rx_broadcast,
2466                             &ns->eth.rx_broadcast);
2467         /* Workaround: CRC size should not be included in byte statistics,
2468          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2469          */
2470         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2471                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2472
2473         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2474          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2475          * value.
2476          */
2477         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2478                 ns->eth.rx_bytes = 0;
2479         /* exlude internal rx bytes */
2480         else
2481                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2482
2483         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2484                             pf->offset_loaded, &os->eth.rx_discards,
2485                             &ns->eth.rx_discards);
2486         /* GLPRT_REPC not supported */
2487         /* GLPRT_RMPC not supported */
2488         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2489                             pf->offset_loaded,
2490                             &os->eth.rx_unknown_protocol,
2491                             &ns->eth.rx_unknown_protocol);
2492         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2493                             I40E_GLPRT_GOTCL(hw->port),
2494                             pf->offset_loaded, &os->eth.tx_bytes,
2495                             &ns->eth.tx_bytes);
2496         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2497                             I40E_GLPRT_UPTCL(hw->port),
2498                             pf->offset_loaded, &os->eth.tx_unicast,
2499                             &ns->eth.tx_unicast);
2500         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2501                             I40E_GLPRT_MPTCL(hw->port),
2502                             pf->offset_loaded, &os->eth.tx_multicast,
2503                             &ns->eth.tx_multicast);
2504         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2505                             I40E_GLPRT_BPTCL(hw->port),
2506                             pf->offset_loaded, &os->eth.tx_broadcast,
2507                             &ns->eth.tx_broadcast);
2508         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2509                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2510
2511         /* exclude internal tx bytes */
2512         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2513                 ns->eth.tx_bytes = 0;
2514         else
2515                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2516
2517         /* GLPRT_TEPC not supported */
2518
2519         /* additional port specific stats */
2520         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2521                             pf->offset_loaded, &os->tx_dropped_link_down,
2522                             &ns->tx_dropped_link_down);
2523         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2524                             pf->offset_loaded, &os->crc_errors,
2525                             &ns->crc_errors);
2526         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2527                             pf->offset_loaded, &os->illegal_bytes,
2528                             &ns->illegal_bytes);
2529         /* GLPRT_ERRBC not supported */
2530         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2531                             pf->offset_loaded, &os->mac_local_faults,
2532                             &ns->mac_local_faults);
2533         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2534                             pf->offset_loaded, &os->mac_remote_faults,
2535                             &ns->mac_remote_faults);
2536         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2537                             pf->offset_loaded, &os->rx_length_errors,
2538                             &ns->rx_length_errors);
2539         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2540                             pf->offset_loaded, &os->link_xon_rx,
2541                             &ns->link_xon_rx);
2542         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2543                             pf->offset_loaded, &os->link_xoff_rx,
2544                             &ns->link_xoff_rx);
2545         for (i = 0; i < 8; i++) {
2546                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2547                                     pf->offset_loaded,
2548                                     &os->priority_xon_rx[i],
2549                                     &ns->priority_xon_rx[i]);
2550                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2551                                     pf->offset_loaded,
2552                                     &os->priority_xoff_rx[i],
2553                                     &ns->priority_xoff_rx[i]);
2554         }
2555         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2556                             pf->offset_loaded, &os->link_xon_tx,
2557                             &ns->link_xon_tx);
2558         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2559                             pf->offset_loaded, &os->link_xoff_tx,
2560                             &ns->link_xoff_tx);
2561         for (i = 0; i < 8; i++) {
2562                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2563                                     pf->offset_loaded,
2564                                     &os->priority_xon_tx[i],
2565                                     &ns->priority_xon_tx[i]);
2566                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2567                                     pf->offset_loaded,
2568                                     &os->priority_xoff_tx[i],
2569                                     &ns->priority_xoff_tx[i]);
2570                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2571                                     pf->offset_loaded,
2572                                     &os->priority_xon_2_xoff[i],
2573                                     &ns->priority_xon_2_xoff[i]);
2574         }
2575         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2576                             I40E_GLPRT_PRC64L(hw->port),
2577                             pf->offset_loaded, &os->rx_size_64,
2578                             &ns->rx_size_64);
2579         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2580                             I40E_GLPRT_PRC127L(hw->port),
2581                             pf->offset_loaded, &os->rx_size_127,
2582                             &ns->rx_size_127);
2583         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2584                             I40E_GLPRT_PRC255L(hw->port),
2585                             pf->offset_loaded, &os->rx_size_255,
2586                             &ns->rx_size_255);
2587         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2588                             I40E_GLPRT_PRC511L(hw->port),
2589                             pf->offset_loaded, &os->rx_size_511,
2590                             &ns->rx_size_511);
2591         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2592                             I40E_GLPRT_PRC1023L(hw->port),
2593                             pf->offset_loaded, &os->rx_size_1023,
2594                             &ns->rx_size_1023);
2595         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2596                             I40E_GLPRT_PRC1522L(hw->port),
2597                             pf->offset_loaded, &os->rx_size_1522,
2598                             &ns->rx_size_1522);
2599         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2600                             I40E_GLPRT_PRC9522L(hw->port),
2601                             pf->offset_loaded, &os->rx_size_big,
2602                             &ns->rx_size_big);
2603         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2604                             pf->offset_loaded, &os->rx_undersize,
2605                             &ns->rx_undersize);
2606         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2607                             pf->offset_loaded, &os->rx_fragments,
2608                             &ns->rx_fragments);
2609         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2610                             pf->offset_loaded, &os->rx_oversize,
2611                             &ns->rx_oversize);
2612         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2613                             pf->offset_loaded, &os->rx_jabber,
2614                             &ns->rx_jabber);
2615         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2616                             I40E_GLPRT_PTC64L(hw->port),
2617                             pf->offset_loaded, &os->tx_size_64,
2618                             &ns->tx_size_64);
2619         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2620                             I40E_GLPRT_PTC127L(hw->port),
2621                             pf->offset_loaded, &os->tx_size_127,
2622                             &ns->tx_size_127);
2623         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2624                             I40E_GLPRT_PTC255L(hw->port),
2625                             pf->offset_loaded, &os->tx_size_255,
2626                             &ns->tx_size_255);
2627         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2628                             I40E_GLPRT_PTC511L(hw->port),
2629                             pf->offset_loaded, &os->tx_size_511,
2630                             &ns->tx_size_511);
2631         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2632                             I40E_GLPRT_PTC1023L(hw->port),
2633                             pf->offset_loaded, &os->tx_size_1023,
2634                             &ns->tx_size_1023);
2635         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2636                             I40E_GLPRT_PTC1522L(hw->port),
2637                             pf->offset_loaded, &os->tx_size_1522,
2638                             &ns->tx_size_1522);
2639         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2640                             I40E_GLPRT_PTC9522L(hw->port),
2641                             pf->offset_loaded, &os->tx_size_big,
2642                             &ns->tx_size_big);
2643         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2644                            pf->offset_loaded,
2645                            &os->fd_sb_match, &ns->fd_sb_match);
2646         /* GLPRT_MSPDC not supported */
2647         /* GLPRT_XEC not supported */
2648
2649         pf->offset_loaded = true;
2650
2651         if (pf->main_vsi)
2652                 i40e_update_vsi_stats(pf->main_vsi);
2653 }
2654
2655 /* Get all statistics of a port */
2656 static void
2657 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2658 {
2659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2661         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2662         unsigned i;
2663
2664         /* call read registers - updates values, now write them to struct */
2665         i40e_read_stats_registers(pf, hw);
2666
2667         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2668                         pf->main_vsi->eth_stats.rx_multicast +
2669                         pf->main_vsi->eth_stats.rx_broadcast -
2670                         pf->main_vsi->eth_stats.rx_discards;
2671         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2672                         pf->main_vsi->eth_stats.tx_multicast +
2673                         pf->main_vsi->eth_stats.tx_broadcast;
2674         stats->ibytes   = ns->eth.rx_bytes;
2675         stats->obytes   = ns->eth.tx_bytes;
2676         stats->oerrors  = ns->eth.tx_errors +
2677                         pf->main_vsi->eth_stats.tx_errors;
2678
2679         /* Rx Errors */
2680         stats->imissed  = ns->eth.rx_discards +
2681                         pf->main_vsi->eth_stats.rx_discards;
2682         stats->ierrors  = ns->crc_errors +
2683                         ns->rx_length_errors + ns->rx_undersize +
2684                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2685
2686         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2687         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2688         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2689         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2690         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2691         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2692         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2693                     ns->eth.rx_unknown_protocol);
2694         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2695         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2696         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2697         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2698         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2699         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2700
2701         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2702                     ns->tx_dropped_link_down);
2703         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2704         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2705                     ns->illegal_bytes);
2706         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2707         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2708                     ns->mac_local_faults);
2709         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2710                     ns->mac_remote_faults);
2711         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2712                     ns->rx_length_errors);
2713         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2714         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2715         for (i = 0; i < 8; i++) {
2716                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2717                                 i, ns->priority_xon_rx[i]);
2718                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2719                                 i, ns->priority_xoff_rx[i]);
2720         }
2721         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2722         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2723         for (i = 0; i < 8; i++) {
2724                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2725                                 i, ns->priority_xon_tx[i]);
2726                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2727                                 i, ns->priority_xoff_tx[i]);
2728                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2729                                 i, ns->priority_xon_2_xoff[i]);
2730         }
2731         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2732         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2733         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2734         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2735         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2736         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2737         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2738         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2739         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2740         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2741         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2742         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2743         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2744         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2745         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2746         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2747         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2748         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2749         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2750                         ns->mac_short_packet_dropped);
2751         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2752                     ns->checksum_error);
2753         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2754         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2755 }
2756
2757 /* Reset the statistics */
2758 static void
2759 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2760 {
2761         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763
2764         /* Mark PF and VSI stats to update the offset, aka "reset" */
2765         pf->offset_loaded = false;
2766         if (pf->main_vsi)
2767                 pf->main_vsi->offset_loaded = false;
2768
2769         /* read the stats, reading current register values into offset */
2770         i40e_read_stats_registers(pf, hw);
2771 }
2772
2773 static uint32_t
2774 i40e_xstats_calc_num(void)
2775 {
2776         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2777                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2778                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2779 }
2780
2781 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2782                                      struct rte_eth_xstat_name *xstats_names,
2783                                      __rte_unused unsigned limit)
2784 {
2785         unsigned count = 0;
2786         unsigned i, prio;
2787
2788         if (xstats_names == NULL)
2789                 return i40e_xstats_calc_num();
2790
2791         /* Note: limit checked in rte_eth_xstats_names() */
2792
2793         /* Get stats from i40e_eth_stats struct */
2794         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2795                 snprintf(xstats_names[count].name,
2796                          sizeof(xstats_names[count].name),
2797                          "%s", rte_i40e_stats_strings[i].name);
2798                 count++;
2799         }
2800
2801         /* Get individiual stats from i40e_hw_port struct */
2802         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2803                 snprintf(xstats_names[count].name,
2804                         sizeof(xstats_names[count].name),
2805                          "%s", rte_i40e_hw_port_strings[i].name);
2806                 count++;
2807         }
2808
2809         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2810                 for (prio = 0; prio < 8; prio++) {
2811                         snprintf(xstats_names[count].name,
2812                                  sizeof(xstats_names[count].name),
2813                                  "rx_priority%u_%s", prio,
2814                                  rte_i40e_rxq_prio_strings[i].name);
2815                         count++;
2816                 }
2817         }
2818
2819         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2820                 for (prio = 0; prio < 8; prio++) {
2821                         snprintf(xstats_names[count].name,
2822                                  sizeof(xstats_names[count].name),
2823                                  "tx_priority%u_%s", prio,
2824                                  rte_i40e_txq_prio_strings[i].name);
2825                         count++;
2826                 }
2827         }
2828         return count;
2829 }
2830
2831 static int
2832 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2833                     unsigned n)
2834 {
2835         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837         unsigned i, count, prio;
2838         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2839
2840         count = i40e_xstats_calc_num();
2841         if (n < count)
2842                 return count;
2843
2844         i40e_read_stats_registers(pf, hw);
2845
2846         if (xstats == NULL)
2847                 return 0;
2848
2849         count = 0;
2850
2851         /* Get stats from i40e_eth_stats struct */
2852         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2853                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2854                         rte_i40e_stats_strings[i].offset);
2855                 xstats[count].id = count;
2856                 count++;
2857         }
2858
2859         /* Get individiual stats from i40e_hw_port struct */
2860         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2861                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2862                         rte_i40e_hw_port_strings[i].offset);
2863                 xstats[count].id = count;
2864                 count++;
2865         }
2866
2867         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2868                 for (prio = 0; prio < 8; prio++) {
2869                         xstats[count].value =
2870                                 *(uint64_t *)(((char *)hw_stats) +
2871                                 rte_i40e_rxq_prio_strings[i].offset +
2872                                 (sizeof(uint64_t) * prio));
2873                         xstats[count].id = count;
2874                         count++;
2875                 }
2876         }
2877
2878         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2879                 for (prio = 0; prio < 8; prio++) {
2880                         xstats[count].value =
2881                                 *(uint64_t *)(((char *)hw_stats) +
2882                                 rte_i40e_txq_prio_strings[i].offset +
2883                                 (sizeof(uint64_t) * prio));
2884                         xstats[count].id = count;
2885                         count++;
2886                 }
2887         }
2888
2889         return count;
2890 }
2891
2892 static int
2893 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2894                                  __rte_unused uint16_t queue_id,
2895                                  __rte_unused uint8_t stat_idx,
2896                                  __rte_unused uint8_t is_rx)
2897 {
2898         PMD_INIT_FUNC_TRACE();
2899
2900         return -ENOSYS;
2901 }
2902
2903 static int
2904 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2905 {
2906         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2907         u32 full_ver;
2908         u8 ver, patch;
2909         u16 build;
2910         int ret;
2911
2912         full_ver = hw->nvm.oem_ver;
2913         ver = (u8)(full_ver >> 24);
2914         build = (u16)((full_ver >> 8) & 0xffff);
2915         patch = (u8)(full_ver & 0xff);
2916
2917         ret = snprintf(fw_version, fw_size,
2918                  "%d.%d%d 0x%08x %d.%d.%d",
2919                  ((hw->nvm.version >> 12) & 0xf),
2920                  ((hw->nvm.version >> 4) & 0xff),
2921                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2922                  ver, build, patch);
2923
2924         ret += 1; /* add the size of '\0' */
2925         if (fw_size < (u32)ret)
2926                 return ret;
2927         else
2928                 return 0;
2929 }
2930
2931 static void
2932 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2933 {
2934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936         struct i40e_vsi *vsi = pf->main_vsi;
2937         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2938
2939         dev_info->pci_dev = pci_dev;
2940         dev_info->max_rx_queues = vsi->nb_qps;
2941         dev_info->max_tx_queues = vsi->nb_qps;
2942         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2943         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2944         dev_info->max_mac_addrs = vsi->max_macaddrs;
2945         dev_info->max_vfs = pci_dev->max_vfs;
2946         dev_info->rx_offload_capa =
2947                 DEV_RX_OFFLOAD_VLAN_STRIP |
2948                 DEV_RX_OFFLOAD_QINQ_STRIP |
2949                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2950                 DEV_RX_OFFLOAD_UDP_CKSUM |
2951                 DEV_RX_OFFLOAD_TCP_CKSUM;
2952         dev_info->tx_offload_capa =
2953                 DEV_TX_OFFLOAD_VLAN_INSERT |
2954                 DEV_TX_OFFLOAD_QINQ_INSERT |
2955                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2956                 DEV_TX_OFFLOAD_UDP_CKSUM |
2957                 DEV_TX_OFFLOAD_TCP_CKSUM |
2958                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2959                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2960                 DEV_TX_OFFLOAD_TCP_TSO |
2961                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2962                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2963                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2964                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2965         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2966                                                 sizeof(uint32_t);
2967         dev_info->reta_size = pf->hash_lut_size;
2968         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2969
2970         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2971                 .rx_thresh = {
2972                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2973                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2974                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2975                 },
2976                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2977                 .rx_drop_en = 0,
2978         };
2979
2980         dev_info->default_txconf = (struct rte_eth_txconf) {
2981                 .tx_thresh = {
2982                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2983                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2984                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2985                 },
2986                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2987                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2988                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2989                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2990         };
2991
2992         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2993                 .nb_max = I40E_MAX_RING_DESC,
2994                 .nb_min = I40E_MIN_RING_DESC,
2995                 .nb_align = I40E_ALIGN_RING_DESC,
2996         };
2997
2998         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2999                 .nb_max = I40E_MAX_RING_DESC,
3000                 .nb_min = I40E_MIN_RING_DESC,
3001                 .nb_align = I40E_ALIGN_RING_DESC,
3002                 .nb_seg_max = I40E_TX_MAX_SEG,
3003                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3004         };
3005
3006         if (pf->flags & I40E_FLAG_VMDQ) {
3007                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3008                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3009                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3010                                                 pf->max_nb_vmdq_vsi;
3011                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3012                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3013                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3014         }
3015
3016         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3017                 /* For XL710 */
3018                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3019         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3020                 /* For XXV710 */
3021                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3022         else
3023                 /* For X710 */
3024                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3025 }
3026
3027 static int
3028 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3029 {
3030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3031         struct i40e_vsi *vsi = pf->main_vsi;
3032         PMD_INIT_FUNC_TRACE();
3033
3034         if (on)
3035                 return i40e_vsi_add_vlan(vsi, vlan_id);
3036         else
3037                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3038 }
3039
3040 static int
3041 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3042                                 enum rte_vlan_type vlan_type,
3043                                 uint16_t tpid, int qinq)
3044 {
3045         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3046         uint64_t reg_r = 0;
3047         uint64_t reg_w = 0;
3048         uint16_t reg_id = 3;
3049         int ret;
3050
3051         if (qinq) {
3052                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3053                         reg_id = 2;
3054         }
3055
3056         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3057                                           &reg_r, NULL);
3058         if (ret != I40E_SUCCESS) {
3059                 PMD_DRV_LOG(ERR,
3060                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3061                            reg_id);
3062                 return -EIO;
3063         }
3064         PMD_DRV_LOG(DEBUG,
3065                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3066                     reg_id, reg_r);
3067
3068         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3069         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3070         if (reg_r == reg_w) {
3071                 PMD_DRV_LOG(DEBUG, "No need to write");
3072                 return 0;
3073         }
3074
3075         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3076                                            reg_w, NULL);
3077         if (ret != I40E_SUCCESS) {
3078                 PMD_DRV_LOG(ERR,
3079                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3080                             reg_id);
3081                 return -EIO;
3082         }
3083         PMD_DRV_LOG(DEBUG,
3084                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3085                     reg_w, reg_id);
3086
3087         return 0;
3088 }
3089
3090 static int
3091 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3092                    enum rte_vlan_type vlan_type,
3093                    uint16_t tpid)
3094 {
3095         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3096         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3097         int ret = 0;
3098
3099         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3100              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3101             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3102                 PMD_DRV_LOG(ERR,
3103                             "Unsupported vlan type.");
3104                 return -EINVAL;
3105         }
3106         /* 802.1ad frames ability is added in NVM API 1.7*/
3107         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3108                 if (qinq) {
3109                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3110                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3111                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3112                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3113                 } else {
3114                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3115                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3116                 }
3117                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3118                 if (ret != I40E_SUCCESS) {
3119                         PMD_DRV_LOG(ERR,
3120                                     "Set switch config failed aq_err: %d",
3121                                     hw->aq.asq_last_status);
3122                         ret = -EIO;
3123                 }
3124         } else
3125                 /* If NVM API < 1.7, keep the register setting */
3126                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3127                                                       tpid, qinq);
3128
3129         return ret;
3130 }
3131
3132 static void
3133 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3134 {
3135         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3136         struct i40e_vsi *vsi = pf->main_vsi;
3137
3138         if (mask & ETH_VLAN_FILTER_MASK) {
3139                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3140                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3141                 else
3142                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3143         }
3144
3145         if (mask & ETH_VLAN_STRIP_MASK) {
3146                 /* Enable or disable VLAN stripping */
3147                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3148                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3149                 else
3150                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3151         }
3152
3153         if (mask & ETH_VLAN_EXTEND_MASK) {
3154                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3155                         i40e_vsi_config_double_vlan(vsi, TRUE);
3156                         /* Set global registers with default ethertype. */
3157                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3158                                            ETHER_TYPE_VLAN);
3159                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3160                                            ETHER_TYPE_VLAN);
3161                 }
3162                 else
3163                         i40e_vsi_config_double_vlan(vsi, FALSE);
3164         }
3165 }
3166
3167 static void
3168 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3169                           __rte_unused uint16_t queue,
3170                           __rte_unused int on)
3171 {
3172         PMD_INIT_FUNC_TRACE();
3173 }
3174
3175 static int
3176 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3177 {
3178         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3179         struct i40e_vsi *vsi = pf->main_vsi;
3180         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3181         struct i40e_vsi_vlan_pvid_info info;
3182
3183         memset(&info, 0, sizeof(info));
3184         info.on = on;
3185         if (info.on)
3186                 info.config.pvid = pvid;
3187         else {
3188                 info.config.reject.tagged =
3189                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3190                 info.config.reject.untagged =
3191                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3192         }
3193
3194         return i40e_vsi_vlan_pvid_set(vsi, &info);
3195 }
3196
3197 static int
3198 i40e_dev_led_on(struct rte_eth_dev *dev)
3199 {
3200         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3201         uint32_t mode = i40e_led_get(hw);
3202
3203         if (mode == 0)
3204                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3205
3206         return 0;
3207 }
3208
3209 static int
3210 i40e_dev_led_off(struct rte_eth_dev *dev)
3211 {
3212         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3213         uint32_t mode = i40e_led_get(hw);
3214
3215         if (mode != 0)
3216                 i40e_led_set(hw, 0, false);
3217
3218         return 0;
3219 }
3220
3221 static int
3222 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3223 {
3224         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3226
3227         fc_conf->pause_time = pf->fc_conf.pause_time;
3228         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3229         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3230
3231          /* Return current mode according to actual setting*/
3232         switch (hw->fc.current_mode) {
3233         case I40E_FC_FULL:
3234                 fc_conf->mode = RTE_FC_FULL;
3235                 break;
3236         case I40E_FC_TX_PAUSE:
3237                 fc_conf->mode = RTE_FC_TX_PAUSE;
3238                 break;
3239         case I40E_FC_RX_PAUSE:
3240                 fc_conf->mode = RTE_FC_RX_PAUSE;
3241                 break;
3242         case I40E_FC_NONE:
3243         default:
3244                 fc_conf->mode = RTE_FC_NONE;
3245         };
3246
3247         return 0;
3248 }
3249
3250 static int
3251 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3252 {
3253         uint32_t mflcn_reg, fctrl_reg, reg;
3254         uint32_t max_high_water;
3255         uint8_t i, aq_failure;
3256         int err;
3257         struct i40e_hw *hw;
3258         struct i40e_pf *pf;
3259         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3260                 [RTE_FC_NONE] = I40E_FC_NONE,
3261                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3262                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3263                 [RTE_FC_FULL] = I40E_FC_FULL
3264         };
3265
3266         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3267
3268         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3269         if ((fc_conf->high_water > max_high_water) ||
3270                         (fc_conf->high_water < fc_conf->low_water)) {
3271                 PMD_INIT_LOG(ERR,
3272                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3273                         max_high_water);
3274                 return -EINVAL;
3275         }
3276
3277         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3280
3281         pf->fc_conf.pause_time = fc_conf->pause_time;
3282         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3283         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3284
3285         PMD_INIT_FUNC_TRACE();
3286
3287         /* All the link flow control related enable/disable register
3288          * configuration is handle by the F/W
3289          */
3290         err = i40e_set_fc(hw, &aq_failure, true);
3291         if (err < 0)
3292                 return -ENOSYS;
3293
3294         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3295                 /* Configure flow control refresh threshold,
3296                  * the value for stat_tx_pause_refresh_timer[8]
3297                  * is used for global pause operation.
3298                  */
3299
3300                 I40E_WRITE_REG(hw,
3301                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3302                                pf->fc_conf.pause_time);
3303
3304                 /* configure the timer value included in transmitted pause
3305                  * frame,
3306                  * the value for stat_tx_pause_quanta[8] is used for global
3307                  * pause operation
3308                  */
3309                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3310                                pf->fc_conf.pause_time);
3311
3312                 fctrl_reg = I40E_READ_REG(hw,
3313                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3314
3315                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3316                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3317                 else
3318                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3319
3320                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3321                                fctrl_reg);
3322         } else {
3323                 /* Configure pause time (2 TCs per register) */
3324                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3325                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3326                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3327
3328                 /* Configure flow control refresh threshold value */
3329                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3330                                pf->fc_conf.pause_time / 2);
3331
3332                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3333
3334                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3335                  *depending on configuration
3336                  */
3337                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3338                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3339                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3340                 } else {
3341                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3342                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3343                 }
3344
3345                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3346         }
3347
3348         /* config the water marker both based on the packets and bytes */
3349         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3350                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3351                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3352         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3353                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3354                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3355         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3356                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3357                        << I40E_KILOSHIFT);
3358         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3359                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3360                        << I40E_KILOSHIFT);
3361
3362         I40E_WRITE_FLUSH(hw);
3363
3364         return 0;
3365 }
3366
3367 static int
3368 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3369                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3370 {
3371         PMD_INIT_FUNC_TRACE();
3372
3373         return -ENOSYS;
3374 }
3375
3376 /* Add a MAC address, and update filters */
3377 static int
3378 i40e_macaddr_add(struct rte_eth_dev *dev,
3379                  struct ether_addr *mac_addr,
3380                  __rte_unused uint32_t index,
3381                  uint32_t pool)
3382 {
3383         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3384         struct i40e_mac_filter_info mac_filter;
3385         struct i40e_vsi *vsi;
3386         int ret;
3387
3388         /* If VMDQ not enabled or configured, return */
3389         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3390                           !pf->nb_cfg_vmdq_vsi)) {
3391                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3392                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3393                         pool);
3394                 return -ENOTSUP;
3395         }
3396
3397         if (pool > pf->nb_cfg_vmdq_vsi) {
3398                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3399                                 pool, pf->nb_cfg_vmdq_vsi);
3400                 return -EINVAL;
3401         }
3402
3403         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3404         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3405                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3406         else
3407                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3408
3409         if (pool == 0)
3410                 vsi = pf->main_vsi;
3411         else
3412                 vsi = pf->vmdq[pool - 1].vsi;
3413
3414         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3415         if (ret != I40E_SUCCESS) {
3416                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3417                 return -ENODEV;
3418         }
3419         return 0;
3420 }
3421
3422 /* Remove a MAC address, and update filters */
3423 static void
3424 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3425 {
3426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3427         struct i40e_vsi *vsi;
3428         struct rte_eth_dev_data *data = dev->data;
3429         struct ether_addr *macaddr;
3430         int ret;
3431         uint32_t i;
3432         uint64_t pool_sel;
3433
3434         macaddr = &(data->mac_addrs[index]);
3435
3436         pool_sel = dev->data->mac_pool_sel[index];
3437
3438         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3439                 if (pool_sel & (1ULL << i)) {
3440                         if (i == 0)
3441                                 vsi = pf->main_vsi;
3442                         else {
3443                                 /* No VMDQ pool enabled or configured */
3444                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3445                                         (i > pf->nb_cfg_vmdq_vsi)) {
3446                                         PMD_DRV_LOG(ERR,
3447                                                 "No VMDQ pool enabled/configured");
3448                                         return;
3449                                 }
3450                                 vsi = pf->vmdq[i - 1].vsi;
3451                         }
3452                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3453
3454                         if (ret) {
3455                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3456                                 return;
3457                         }
3458                 }
3459         }
3460 }
3461
3462 /* Set perfect match or hash match of MAC and VLAN for a VF */
3463 static int
3464 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3465                  struct rte_eth_mac_filter *filter,
3466                  bool add)
3467 {
3468         struct i40e_hw *hw;
3469         struct i40e_mac_filter_info mac_filter;
3470         struct ether_addr old_mac;
3471         struct ether_addr *new_mac;
3472         struct i40e_pf_vf *vf = NULL;
3473         uint16_t vf_id;
3474         int ret;
3475
3476         if (pf == NULL) {
3477                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3478                 return -EINVAL;
3479         }
3480         hw = I40E_PF_TO_HW(pf);
3481
3482         if (filter == NULL) {
3483                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3484                 return -EINVAL;
3485         }
3486
3487         new_mac = &filter->mac_addr;
3488
3489         if (is_zero_ether_addr(new_mac)) {
3490                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3491                 return -EINVAL;
3492         }
3493
3494         vf_id = filter->dst_id;
3495
3496         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3497                 PMD_DRV_LOG(ERR, "Invalid argument.");
3498                 return -EINVAL;
3499         }
3500         vf = &pf->vfs[vf_id];
3501
3502         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3503                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3504                 return -EINVAL;
3505         }
3506
3507         if (add) {
3508                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3509                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3510                                 ETHER_ADDR_LEN);
3511                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3512                                  ETHER_ADDR_LEN);
3513
3514                 mac_filter.filter_type = filter->filter_type;
3515                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3516                 if (ret != I40E_SUCCESS) {
3517                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3518                         return -1;
3519                 }
3520                 ether_addr_copy(new_mac, &pf->dev_addr);
3521         } else {
3522                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3523                                 ETHER_ADDR_LEN);
3524                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3525                 if (ret != I40E_SUCCESS) {
3526                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3527                         return -1;
3528                 }
3529
3530                 /* Clear device address as it has been removed */
3531                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3532                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3533         }
3534
3535         return 0;
3536 }
3537
3538 /* MAC filter handle */
3539 static int
3540 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3541                 void *arg)
3542 {
3543         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3544         struct rte_eth_mac_filter *filter;
3545         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3546         int ret = I40E_NOT_SUPPORTED;
3547
3548         filter = (struct rte_eth_mac_filter *)(arg);
3549
3550         switch (filter_op) {
3551         case RTE_ETH_FILTER_NOP:
3552                 ret = I40E_SUCCESS;
3553                 break;
3554         case RTE_ETH_FILTER_ADD:
3555                 i40e_pf_disable_irq0(hw);
3556                 if (filter->is_vf)
3557                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3558                 i40e_pf_enable_irq0(hw);
3559                 break;
3560         case RTE_ETH_FILTER_DELETE:
3561                 i40e_pf_disable_irq0(hw);
3562                 if (filter->is_vf)
3563                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3564                 i40e_pf_enable_irq0(hw);
3565                 break;
3566         default:
3567                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3568                 ret = I40E_ERR_PARAM;
3569                 break;
3570         }
3571
3572         return ret;
3573 }
3574
3575 static int
3576 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3577 {
3578         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3579         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3580         int ret;
3581
3582         if (!lut)
3583                 return -EINVAL;
3584
3585         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3586                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3587                                           lut, lut_size);
3588                 if (ret) {
3589                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3590                         return ret;
3591                 }
3592         } else {
3593                 uint32_t *lut_dw = (uint32_t *)lut;
3594                 uint16_t i, lut_size_dw = lut_size / 4;
3595
3596                 for (i = 0; i < lut_size_dw; i++)
3597                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3598         }
3599
3600         return 0;
3601 }
3602
3603 static int
3604 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3605 {
3606         struct i40e_pf *pf;
3607         struct i40e_hw *hw;
3608         int ret;
3609
3610         if (!vsi || !lut)
3611                 return -EINVAL;
3612
3613         pf = I40E_VSI_TO_PF(vsi);
3614         hw = I40E_VSI_TO_HW(vsi);
3615
3616         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3617                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3618                                           lut, lut_size);
3619                 if (ret) {
3620                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3621                         return ret;
3622                 }
3623         } else {
3624                 uint32_t *lut_dw = (uint32_t *)lut;
3625                 uint16_t i, lut_size_dw = lut_size / 4;
3626
3627                 for (i = 0; i < lut_size_dw; i++)
3628                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3629                 I40E_WRITE_FLUSH(hw);
3630         }
3631
3632         return 0;
3633 }
3634
3635 static int
3636 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3637                          struct rte_eth_rss_reta_entry64 *reta_conf,
3638                          uint16_t reta_size)
3639 {
3640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3641         uint16_t i, lut_size = pf->hash_lut_size;
3642         uint16_t idx, shift;
3643         uint8_t *lut;
3644         int ret;
3645
3646         if (reta_size != lut_size ||
3647                 reta_size > ETH_RSS_RETA_SIZE_512) {
3648                 PMD_DRV_LOG(ERR,
3649                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3650                         reta_size, lut_size);
3651                 return -EINVAL;
3652         }
3653
3654         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3655         if (!lut) {
3656                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3657                 return -ENOMEM;
3658         }
3659         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3660         if (ret)
3661                 goto out;
3662         for (i = 0; i < reta_size; i++) {
3663                 idx = i / RTE_RETA_GROUP_SIZE;
3664                 shift = i % RTE_RETA_GROUP_SIZE;
3665                 if (reta_conf[idx].mask & (1ULL << shift))
3666                         lut[i] = reta_conf[idx].reta[shift];
3667         }
3668         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3669
3670 out:
3671         rte_free(lut);
3672
3673         return ret;
3674 }
3675
3676 static int
3677 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3678                         struct rte_eth_rss_reta_entry64 *reta_conf,
3679                         uint16_t reta_size)
3680 {
3681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3682         uint16_t i, lut_size = pf->hash_lut_size;
3683         uint16_t idx, shift;
3684         uint8_t *lut;
3685         int ret;
3686
3687         if (reta_size != lut_size ||
3688                 reta_size > ETH_RSS_RETA_SIZE_512) {
3689                 PMD_DRV_LOG(ERR,
3690                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3691                         reta_size, lut_size);
3692                 return -EINVAL;
3693         }
3694
3695         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3696         if (!lut) {
3697                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3698                 return -ENOMEM;
3699         }
3700
3701         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3702         if (ret)
3703                 goto out;
3704         for (i = 0; i < reta_size; i++) {
3705                 idx = i / RTE_RETA_GROUP_SIZE;
3706                 shift = i % RTE_RETA_GROUP_SIZE;
3707                 if (reta_conf[idx].mask & (1ULL << shift))
3708                         reta_conf[idx].reta[shift] = lut[i];
3709         }
3710
3711 out:
3712         rte_free(lut);
3713
3714         return ret;
3715 }
3716
3717 /**
3718  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3719  * @hw:   pointer to the HW structure
3720  * @mem:  pointer to mem struct to fill out
3721  * @size: size of memory requested
3722  * @alignment: what to align the allocation to
3723  **/
3724 enum i40e_status_code
3725 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3726                         struct i40e_dma_mem *mem,
3727                         u64 size,
3728                         u32 alignment)
3729 {
3730         const struct rte_memzone *mz = NULL;
3731         char z_name[RTE_MEMZONE_NAMESIZE];
3732
3733         if (!mem)
3734                 return I40E_ERR_PARAM;
3735
3736         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3737         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3738                                          alignment, RTE_PGSIZE_2M);
3739         if (!mz)
3740                 return I40E_ERR_NO_MEMORY;
3741
3742         mem->size = size;
3743         mem->va = mz->addr;
3744         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3745         mem->zone = (const void *)mz;
3746         PMD_DRV_LOG(DEBUG,
3747                 "memzone %s allocated with physical address: %"PRIu64,
3748                 mz->name, mem->pa);
3749
3750         return I40E_SUCCESS;
3751 }
3752
3753 /**
3754  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3755  * @hw:   pointer to the HW structure
3756  * @mem:  ptr to mem struct to free
3757  **/
3758 enum i40e_status_code
3759 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3760                     struct i40e_dma_mem *mem)
3761 {
3762         if (!mem)
3763                 return I40E_ERR_PARAM;
3764
3765         PMD_DRV_LOG(DEBUG,
3766                 "memzone %s to be freed with physical address: %"PRIu64,
3767                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3768         rte_memzone_free((const struct rte_memzone *)mem->zone);
3769         mem->zone = NULL;
3770         mem->va = NULL;
3771         mem->pa = (u64)0;
3772
3773         return I40E_SUCCESS;
3774 }
3775
3776 /**
3777  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3778  * @hw:   pointer to the HW structure
3779  * @mem:  pointer to mem struct to fill out
3780  * @size: size of memory requested
3781  **/
3782 enum i40e_status_code
3783 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3784                          struct i40e_virt_mem *mem,
3785                          u32 size)
3786 {
3787         if (!mem)
3788                 return I40E_ERR_PARAM;
3789
3790         mem->size = size;
3791         mem->va = rte_zmalloc("i40e", size, 0);
3792
3793         if (mem->va)
3794                 return I40E_SUCCESS;
3795         else
3796                 return I40E_ERR_NO_MEMORY;
3797 }
3798
3799 /**
3800  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3801  * @hw:   pointer to the HW structure
3802  * @mem:  pointer to mem struct to free
3803  **/
3804 enum i40e_status_code
3805 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3806                      struct i40e_virt_mem *mem)
3807 {
3808         if (!mem)
3809                 return I40E_ERR_PARAM;
3810
3811         rte_free(mem->va);
3812         mem->va = NULL;
3813
3814         return I40E_SUCCESS;
3815 }
3816
3817 void
3818 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3819 {
3820         rte_spinlock_init(&sp->spinlock);
3821 }
3822
3823 void
3824 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3825 {
3826         rte_spinlock_lock(&sp->spinlock);
3827 }
3828
3829 void
3830 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3831 {
3832         rte_spinlock_unlock(&sp->spinlock);
3833 }
3834
3835 void
3836 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3837 {
3838         return;
3839 }
3840
3841 /**
3842  * Get the hardware capabilities, which will be parsed
3843  * and saved into struct i40e_hw.
3844  */
3845 static int
3846 i40e_get_cap(struct i40e_hw *hw)
3847 {
3848         struct i40e_aqc_list_capabilities_element_resp *buf;
3849         uint16_t len, size = 0;
3850         int ret;
3851
3852         /* Calculate a huge enough buff for saving response data temporarily */
3853         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3854                                                 I40E_MAX_CAP_ELE_NUM;
3855         buf = rte_zmalloc("i40e", len, 0);
3856         if (!buf) {
3857                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3858                 return I40E_ERR_NO_MEMORY;
3859         }
3860
3861         /* Get, parse the capabilities and save it to hw */
3862         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3863                         i40e_aqc_opc_list_func_capabilities, NULL);
3864         if (ret != I40E_SUCCESS)
3865                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3866
3867         /* Free the temporary buffer after being used */
3868         rte_free(buf);
3869
3870         return ret;
3871 }
3872
3873 static int
3874 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3875 {
3876         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3877         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3878         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3879         uint16_t qp_count = 0, vsi_count = 0;
3880
3881         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3882                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3883                 return -EINVAL;
3884         }
3885         /* Add the parameter init for LFC */
3886         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3887         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3888         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3889
3890         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3891         pf->max_num_vsi = hw->func_caps.num_vsis;
3892         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3893         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3894         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3895
3896         /* FDir queue/VSI allocation */
3897         pf->fdir_qp_offset = 0;
3898         if (hw->func_caps.fd) {
3899                 pf->flags |= I40E_FLAG_FDIR;
3900                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3901         } else {
3902                 pf->fdir_nb_qps = 0;
3903         }
3904         qp_count += pf->fdir_nb_qps;
3905         vsi_count += 1;
3906
3907         /* LAN queue/VSI allocation */
3908         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3909         if (!hw->func_caps.rss) {
3910                 pf->lan_nb_qps = 1;
3911         } else {
3912                 pf->flags |= I40E_FLAG_RSS;
3913                 if (hw->mac.type == I40E_MAC_X722)
3914                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3915                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3916         }
3917         qp_count += pf->lan_nb_qps;
3918         vsi_count += 1;
3919
3920         /* VF queue/VSI allocation */
3921         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3922         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3923                 pf->flags |= I40E_FLAG_SRIOV;
3924                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3925                 pf->vf_num = pci_dev->max_vfs;
3926                 PMD_DRV_LOG(DEBUG,
3927                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3928                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3929         } else {
3930                 pf->vf_nb_qps = 0;
3931                 pf->vf_num = 0;
3932         }
3933         qp_count += pf->vf_nb_qps * pf->vf_num;
3934         vsi_count += pf->vf_num;
3935
3936         /* VMDq queue/VSI allocation */
3937         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3938         pf->vmdq_nb_qps = 0;
3939         pf->max_nb_vmdq_vsi = 0;
3940         if (hw->func_caps.vmdq) {
3941                 if (qp_count < hw->func_caps.num_tx_qp &&
3942                         vsi_count < hw->func_caps.num_vsis) {
3943                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3944                                 qp_count) / pf->vmdq_nb_qp_max;
3945
3946                         /* Limit the maximum number of VMDq vsi to the maximum
3947                          * ethdev can support
3948                          */
3949                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3950                                 hw->func_caps.num_vsis - vsi_count);
3951                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3952                                 ETH_64_POOLS);
3953                         if (pf->max_nb_vmdq_vsi) {
3954                                 pf->flags |= I40E_FLAG_VMDQ;
3955                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3956                                 PMD_DRV_LOG(DEBUG,
3957                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3958                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3959                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3960                         } else {
3961                                 PMD_DRV_LOG(INFO,
3962                                         "No enough queues left for VMDq");
3963                         }
3964                 } else {
3965                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3966                 }
3967         }
3968         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3969         vsi_count += pf->max_nb_vmdq_vsi;
3970
3971         if (hw->func_caps.dcb)
3972                 pf->flags |= I40E_FLAG_DCB;
3973
3974         if (qp_count > hw->func_caps.num_tx_qp) {
3975                 PMD_DRV_LOG(ERR,
3976                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3977                         qp_count, hw->func_caps.num_tx_qp);
3978                 return -EINVAL;
3979         }
3980         if (vsi_count > hw->func_caps.num_vsis) {
3981                 PMD_DRV_LOG(ERR,
3982                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3983                         vsi_count, hw->func_caps.num_vsis);
3984                 return -EINVAL;
3985         }
3986
3987         return 0;
3988 }
3989
3990 static int
3991 i40e_pf_get_switch_config(struct i40e_pf *pf)
3992 {
3993         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3994         struct i40e_aqc_get_switch_config_resp *switch_config;
3995         struct i40e_aqc_switch_config_element_resp *element;
3996         uint16_t start_seid = 0, num_reported;
3997         int ret;
3998
3999         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4000                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4001         if (!switch_config) {
4002                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4003                 return -ENOMEM;
4004         }
4005
4006         /* Get the switch configurations */
4007         ret = i40e_aq_get_switch_config(hw, switch_config,
4008                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4009         if (ret != I40E_SUCCESS) {
4010                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4011                 goto fail;
4012         }
4013         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4014         if (num_reported != 1) { /* The number should be 1 */
4015                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4016                 goto fail;
4017         }
4018
4019         /* Parse the switch configuration elements */
4020         element = &(switch_config->element[0]);
4021         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4022                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4023                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4024         } else
4025                 PMD_DRV_LOG(INFO, "Unknown element type");
4026
4027 fail:
4028         rte_free(switch_config);
4029
4030         return ret;
4031 }
4032
4033 static int
4034 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4035                         uint32_t num)
4036 {
4037         struct pool_entry *entry;
4038
4039         if (pool == NULL || num == 0)
4040                 return -EINVAL;
4041
4042         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4043         if (entry == NULL) {
4044                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4045                 return -ENOMEM;
4046         }
4047
4048         /* queue heap initialize */
4049         pool->num_free = num;
4050         pool->num_alloc = 0;
4051         pool->base = base;
4052         LIST_INIT(&pool->alloc_list);
4053         LIST_INIT(&pool->free_list);
4054
4055         /* Initialize element  */
4056         entry->base = 0;
4057         entry->len = num;
4058
4059         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4060         return 0;
4061 }
4062
4063 static void
4064 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4065 {
4066         struct pool_entry *entry, *next_entry;
4067
4068         if (pool == NULL)
4069                 return;
4070
4071         for (entry = LIST_FIRST(&pool->alloc_list);
4072                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4073                         entry = next_entry) {
4074                 LIST_REMOVE(entry, next);
4075                 rte_free(entry);
4076         }
4077
4078         for (entry = LIST_FIRST(&pool->free_list);
4079                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4080                         entry = next_entry) {
4081                 LIST_REMOVE(entry, next);
4082                 rte_free(entry);
4083         }
4084
4085         pool->num_free = 0;
4086         pool->num_alloc = 0;
4087         pool->base = 0;
4088         LIST_INIT(&pool->alloc_list);
4089         LIST_INIT(&pool->free_list);
4090 }
4091
4092 static int
4093 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4094                        uint32_t base)
4095 {
4096         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4097         uint32_t pool_offset;
4098         int insert;
4099
4100         if (pool == NULL) {
4101                 PMD_DRV_LOG(ERR, "Invalid parameter");
4102                 return -EINVAL;
4103         }
4104
4105         pool_offset = base - pool->base;
4106         /* Lookup in alloc list */
4107         LIST_FOREACH(entry, &pool->alloc_list, next) {
4108                 if (entry->base == pool_offset) {
4109                         valid_entry = entry;
4110                         LIST_REMOVE(entry, next);
4111                         break;
4112                 }
4113         }
4114
4115         /* Not find, return */
4116         if (valid_entry == NULL) {
4117                 PMD_DRV_LOG(ERR, "Failed to find entry");
4118                 return -EINVAL;
4119         }
4120
4121         /**
4122          * Found it, move it to free list  and try to merge.
4123          * In order to make merge easier, always sort it by qbase.
4124          * Find adjacent prev and last entries.
4125          */
4126         prev = next = NULL;
4127         LIST_FOREACH(entry, &pool->free_list, next) {
4128                 if (entry->base > valid_entry->base) {
4129                         next = entry;
4130                         break;
4131                 }
4132                 prev = entry;
4133         }
4134
4135         insert = 0;
4136         /* Try to merge with next one*/
4137         if (next != NULL) {
4138                 /* Merge with next one */
4139                 if (valid_entry->base + valid_entry->len == next->base) {
4140                         next->base = valid_entry->base;
4141                         next->len += valid_entry->len;
4142                         rte_free(valid_entry);
4143                         valid_entry = next;
4144                         insert = 1;
4145                 }
4146         }
4147
4148         if (prev != NULL) {
4149                 /* Merge with previous one */
4150                 if (prev->base + prev->len == valid_entry->base) {
4151                         prev->len += valid_entry->len;
4152                         /* If it merge with next one, remove next node */
4153                         if (insert == 1) {
4154                                 LIST_REMOVE(valid_entry, next);
4155                                 rte_free(valid_entry);
4156                         } else {
4157                                 rte_free(valid_entry);
4158                                 insert = 1;
4159                         }
4160                 }
4161         }
4162
4163         /* Not find any entry to merge, insert */
4164         if (insert == 0) {
4165                 if (prev != NULL)
4166                         LIST_INSERT_AFTER(prev, valid_entry, next);
4167                 else if (next != NULL)
4168                         LIST_INSERT_BEFORE(next, valid_entry, next);
4169                 else /* It's empty list, insert to head */
4170                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4171         }
4172
4173         pool->num_free += valid_entry->len;
4174         pool->num_alloc -= valid_entry->len;
4175
4176         return 0;
4177 }
4178
4179 static int
4180 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4181                        uint16_t num)
4182 {
4183         struct pool_entry *entry, *valid_entry;
4184
4185         if (pool == NULL || num == 0) {
4186                 PMD_DRV_LOG(ERR, "Invalid parameter");
4187                 return -EINVAL;
4188         }
4189
4190         if (pool->num_free < num) {
4191                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4192                             num, pool->num_free);
4193                 return -ENOMEM;
4194         }
4195
4196         valid_entry = NULL;
4197         /* Lookup  in free list and find most fit one */
4198         LIST_FOREACH(entry, &pool->free_list, next) {
4199                 if (entry->len >= num) {
4200                         /* Find best one */
4201                         if (entry->len == num) {
4202                                 valid_entry = entry;
4203                                 break;
4204                         }
4205                         if (valid_entry == NULL || valid_entry->len > entry->len)
4206                                 valid_entry = entry;
4207                 }
4208         }
4209
4210         /* Not find one to satisfy the request, return */
4211         if (valid_entry == NULL) {
4212                 PMD_DRV_LOG(ERR, "No valid entry found");
4213                 return -ENOMEM;
4214         }
4215         /**
4216          * The entry have equal queue number as requested,
4217          * remove it from alloc_list.
4218          */
4219         if (valid_entry->len == num) {
4220                 LIST_REMOVE(valid_entry, next);
4221         } else {
4222                 /**
4223                  * The entry have more numbers than requested,
4224                  * create a new entry for alloc_list and minus its
4225                  * queue base and number in free_list.
4226                  */
4227                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4228                 if (entry == NULL) {
4229                         PMD_DRV_LOG(ERR,
4230                                 "Failed to allocate memory for resource pool");
4231                         return -ENOMEM;
4232                 }
4233                 entry->base = valid_entry->base;
4234                 entry->len = num;
4235                 valid_entry->base += num;
4236                 valid_entry->len -= num;
4237                 valid_entry = entry;
4238         }
4239
4240         /* Insert it into alloc list, not sorted */
4241         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4242
4243         pool->num_free -= valid_entry->len;
4244         pool->num_alloc += valid_entry->len;
4245
4246         return valid_entry->base + pool->base;
4247 }
4248
4249 /**
4250  * bitmap_is_subset - Check whether src2 is subset of src1
4251  **/
4252 static inline int
4253 bitmap_is_subset(uint8_t src1, uint8_t src2)
4254 {
4255         return !((src1 ^ src2) & src2);
4256 }
4257
4258 static enum i40e_status_code
4259 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4260 {
4261         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4262
4263         /* If DCB is not supported, only default TC is supported */
4264         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4265                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4266                 return I40E_NOT_SUPPORTED;
4267         }
4268
4269         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4270                 PMD_DRV_LOG(ERR,
4271                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4272                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4273                 return I40E_NOT_SUPPORTED;
4274         }
4275         return I40E_SUCCESS;
4276 }
4277
4278 int
4279 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4280                                 struct i40e_vsi_vlan_pvid_info *info)
4281 {
4282         struct i40e_hw *hw;
4283         struct i40e_vsi_context ctxt;
4284         uint8_t vlan_flags = 0;
4285         int ret;
4286
4287         if (vsi == NULL || info == NULL) {
4288                 PMD_DRV_LOG(ERR, "invalid parameters");
4289                 return I40E_ERR_PARAM;
4290         }
4291
4292         if (info->on) {
4293                 vsi->info.pvid = info->config.pvid;
4294                 /**
4295                  * If insert pvid is enabled, only tagged pkts are
4296                  * allowed to be sent out.
4297                  */
4298                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4299                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4300         } else {
4301                 vsi->info.pvid = 0;
4302                 if (info->config.reject.tagged == 0)
4303                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4304
4305                 if (info->config.reject.untagged == 0)
4306                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4307         }
4308         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4309                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4310         vsi->info.port_vlan_flags |= vlan_flags;
4311         vsi->info.valid_sections =
4312                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4313         memset(&ctxt, 0, sizeof(ctxt));
4314         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4315         ctxt.seid = vsi->seid;
4316
4317         hw = I40E_VSI_TO_HW(vsi);
4318         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4319         if (ret != I40E_SUCCESS)
4320                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4321
4322         return ret;
4323 }
4324
4325 static int
4326 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4327 {
4328         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4329         int i, ret;
4330         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4331
4332         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4333         if (ret != I40E_SUCCESS)
4334                 return ret;
4335
4336         if (!vsi->seid) {
4337                 PMD_DRV_LOG(ERR, "seid not valid");
4338                 return -EINVAL;
4339         }
4340
4341         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4342         tc_bw_data.tc_valid_bits = enabled_tcmap;
4343         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4344                 tc_bw_data.tc_bw_credits[i] =
4345                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4346
4347         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4348         if (ret != I40E_SUCCESS) {
4349                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4350                 return ret;
4351         }
4352
4353         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4354                                         sizeof(vsi->info.qs_handle));
4355         return I40E_SUCCESS;
4356 }
4357
4358 static enum i40e_status_code
4359 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4360                                  struct i40e_aqc_vsi_properties_data *info,
4361                                  uint8_t enabled_tcmap)
4362 {
4363         enum i40e_status_code ret;
4364         int i, total_tc = 0;
4365         uint16_t qpnum_per_tc, bsf, qp_idx;
4366
4367         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4368         if (ret != I40E_SUCCESS)
4369                 return ret;
4370
4371         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4372                 if (enabled_tcmap & (1 << i))
4373                         total_tc++;
4374         if (total_tc == 0)
4375                 total_tc = 1;
4376         vsi->enabled_tc = enabled_tcmap;
4377
4378         /* Number of queues per enabled TC */
4379         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4380         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4381         bsf = rte_bsf32(qpnum_per_tc);
4382
4383         /* Adjust the queue number to actual queues that can be applied */
4384         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4385                 vsi->nb_qps = qpnum_per_tc * total_tc;
4386
4387         /**
4388          * Configure TC and queue mapping parameters, for enabled TC,
4389          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4390          * default queue will serve it.
4391          */
4392         qp_idx = 0;
4393         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4394                 if (vsi->enabled_tc & (1 << i)) {
4395                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4396                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4397                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4398                         qp_idx += qpnum_per_tc;
4399                 } else
4400                         info->tc_mapping[i] = 0;
4401         }
4402
4403         /* Associate queue number with VSI */
4404         if (vsi->type == I40E_VSI_SRIOV) {
4405                 info->mapping_flags |=
4406                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4407                 for (i = 0; i < vsi->nb_qps; i++)
4408                         info->queue_mapping[i] =
4409                                 rte_cpu_to_le_16(vsi->base_queue + i);
4410         } else {
4411                 info->mapping_flags |=
4412                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4413                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4414         }
4415         info->valid_sections |=
4416                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4417
4418         return I40E_SUCCESS;
4419 }
4420
4421 static int
4422 i40e_veb_release(struct i40e_veb *veb)
4423 {
4424         struct i40e_vsi *vsi;
4425         struct i40e_hw *hw;
4426
4427         if (veb == NULL)
4428                 return -EINVAL;
4429
4430         if (!TAILQ_EMPTY(&veb->head)) {
4431                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4432                 return -EACCES;
4433         }
4434         /* associate_vsi field is NULL for floating VEB */
4435         if (veb->associate_vsi != NULL) {
4436                 vsi = veb->associate_vsi;
4437                 hw = I40E_VSI_TO_HW(vsi);
4438
4439                 vsi->uplink_seid = veb->uplink_seid;
4440                 vsi->veb = NULL;
4441         } else {
4442                 veb->associate_pf->main_vsi->floating_veb = NULL;
4443                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4444         }
4445
4446         i40e_aq_delete_element(hw, veb->seid, NULL);
4447         rte_free(veb);
4448         return I40E_SUCCESS;
4449 }
4450
4451 /* Setup a veb */
4452 static struct i40e_veb *
4453 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4454 {
4455         struct i40e_veb *veb;
4456         int ret;
4457         struct i40e_hw *hw;
4458
4459         if (pf == NULL) {
4460                 PMD_DRV_LOG(ERR,
4461                             "veb setup failed, associated PF shouldn't null");
4462                 return NULL;
4463         }
4464         hw = I40E_PF_TO_HW(pf);
4465
4466         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4467         if (!veb) {
4468                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4469                 goto fail;
4470         }
4471
4472         veb->associate_vsi = vsi;
4473         veb->associate_pf = pf;
4474         TAILQ_INIT(&veb->head);
4475         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4476
4477         /* create floating veb if vsi is NULL */
4478         if (vsi != NULL) {
4479                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4480                                       I40E_DEFAULT_TCMAP, false,
4481                                       &veb->seid, false, NULL);
4482         } else {
4483                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4484                                       true, &veb->seid, false, NULL);
4485         }
4486
4487         if (ret != I40E_SUCCESS) {
4488                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4489                             hw->aq.asq_last_status);
4490                 goto fail;
4491         }
4492         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4493
4494         /* get statistics index */
4495         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4496                                 &veb->stats_idx, NULL, NULL, NULL);
4497         if (ret != I40E_SUCCESS) {
4498                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4499                             hw->aq.asq_last_status);
4500                 goto fail;
4501         }
4502         /* Get VEB bandwidth, to be implemented */
4503         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4504         if (vsi)
4505                 vsi->uplink_seid = veb->seid;
4506
4507         return veb;
4508 fail:
4509         rte_free(veb);
4510         return NULL;
4511 }
4512
4513 int
4514 i40e_vsi_release(struct i40e_vsi *vsi)
4515 {
4516         struct i40e_pf *pf;
4517         struct i40e_hw *hw;
4518         struct i40e_vsi_list *vsi_list;
4519         void *temp;
4520         int ret;
4521         struct i40e_mac_filter *f;
4522         uint16_t user_param;
4523
4524         if (!vsi)
4525                 return I40E_SUCCESS;
4526
4527         if (!vsi->adapter)
4528                 return -EFAULT;
4529
4530         user_param = vsi->user_param;
4531
4532         pf = I40E_VSI_TO_PF(vsi);
4533         hw = I40E_VSI_TO_HW(vsi);
4534
4535         /* VSI has child to attach, release child first */
4536         if (vsi->veb) {
4537                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4538                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4539                                 return -1;
4540                 }
4541                 i40e_veb_release(vsi->veb);
4542         }
4543
4544         if (vsi->floating_veb) {
4545                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4546                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4547                                 return -1;
4548                 }
4549         }
4550
4551         /* Remove all macvlan filters of the VSI */
4552         i40e_vsi_remove_all_macvlan_filter(vsi);
4553         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4554                 rte_free(f);
4555
4556         if (vsi->type != I40E_VSI_MAIN &&
4557             ((vsi->type != I40E_VSI_SRIOV) ||
4558             !pf->floating_veb_list[user_param])) {
4559                 /* Remove vsi from parent's sibling list */
4560                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4561                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4562                         return I40E_ERR_PARAM;
4563                 }
4564                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4565                                 &vsi->sib_vsi_list, list);
4566
4567                 /* Remove all switch element of the VSI */
4568                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4569                 if (ret != I40E_SUCCESS)
4570                         PMD_DRV_LOG(ERR, "Failed to delete element");
4571         }
4572
4573         if ((vsi->type == I40E_VSI_SRIOV) &&
4574             pf->floating_veb_list[user_param]) {
4575                 /* Remove vsi from parent's sibling list */
4576                 if (vsi->parent_vsi == NULL ||
4577                     vsi->parent_vsi->floating_veb == NULL) {
4578                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4579                         return I40E_ERR_PARAM;
4580                 }
4581                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4582                              &vsi->sib_vsi_list, list);
4583
4584                 /* Remove all switch element of the VSI */
4585                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4586                 if (ret != I40E_SUCCESS)
4587                         PMD_DRV_LOG(ERR, "Failed to delete element");
4588         }
4589
4590         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4591
4592         if (vsi->type != I40E_VSI_SRIOV)
4593                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4594         rte_free(vsi);
4595
4596         return I40E_SUCCESS;
4597 }
4598
4599 static int
4600 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4601 {
4602         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4603         struct i40e_aqc_remove_macvlan_element_data def_filter;
4604         struct i40e_mac_filter_info filter;
4605         int ret;
4606
4607         if (vsi->type != I40E_VSI_MAIN)
4608                 return I40E_ERR_CONFIG;
4609         memset(&def_filter, 0, sizeof(def_filter));
4610         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4611                                         ETH_ADDR_LEN);
4612         def_filter.vlan_tag = 0;
4613         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4614                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4615         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4616         if (ret != I40E_SUCCESS) {
4617                 struct i40e_mac_filter *f;
4618                 struct ether_addr *mac;
4619
4620                 PMD_DRV_LOG(DEBUG,
4621                             "Cannot remove the default macvlan filter");
4622                 /* It needs to add the permanent mac into mac list */
4623                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4624                 if (f == NULL) {
4625                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4626                         return I40E_ERR_NO_MEMORY;
4627                 }
4628                 mac = &f->mac_info.mac_addr;
4629                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4630                                 ETH_ADDR_LEN);
4631                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4632                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4633                 vsi->mac_num++;
4634
4635                 return ret;
4636         }
4637         (void)rte_memcpy(&filter.mac_addr,
4638                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4639         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4640         return i40e_vsi_add_mac(vsi, &filter);
4641 }
4642
4643 /*
4644  * i40e_vsi_get_bw_config - Query VSI BW Information
4645  * @vsi: the VSI to be queried
4646  *
4647  * Returns 0 on success, negative value on failure
4648  */
4649 static enum i40e_status_code
4650 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4651 {
4652         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4653         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4654         struct i40e_hw *hw = &vsi->adapter->hw;
4655         i40e_status ret;
4656         int i;
4657         uint32_t bw_max;
4658
4659         memset(&bw_config, 0, sizeof(bw_config));
4660         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4661         if (ret != I40E_SUCCESS) {
4662                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4663                             hw->aq.asq_last_status);
4664                 return ret;
4665         }
4666
4667         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4668         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4669                                         &ets_sla_config, NULL);
4670         if (ret != I40E_SUCCESS) {
4671                 PMD_DRV_LOG(ERR,
4672                         "VSI failed to get TC bandwdith configuration %u",
4673                         hw->aq.asq_last_status);
4674                 return ret;
4675         }
4676
4677         /* store and print out BW info */
4678         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4679         vsi->bw_info.bw_max = bw_config.max_bw;
4680         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4681         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4682         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4683                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4684                      I40E_16_BIT_WIDTH);
4685         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4686                 vsi->bw_info.bw_ets_share_credits[i] =
4687                                 ets_sla_config.share_credits[i];
4688                 vsi->bw_info.bw_ets_credits[i] =
4689                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4690                 /* 4 bits per TC, 4th bit is reserved */
4691                 vsi->bw_info.bw_ets_max[i] =
4692                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4693                                   RTE_LEN2MASK(3, uint8_t));
4694                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4695                             vsi->bw_info.bw_ets_share_credits[i]);
4696                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4697                             vsi->bw_info.bw_ets_credits[i]);
4698                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4699                             vsi->bw_info.bw_ets_max[i]);
4700         }
4701
4702         return I40E_SUCCESS;
4703 }
4704
4705 /* i40e_enable_pf_lb
4706  * @pf: pointer to the pf structure
4707  *
4708  * allow loopback on pf
4709  */
4710 static inline void
4711 i40e_enable_pf_lb(struct i40e_pf *pf)
4712 {
4713         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4714         struct i40e_vsi_context ctxt;
4715         int ret;
4716
4717         /* Use the FW API if FW >= v5.0 */
4718         if (hw->aq.fw_maj_ver < 5) {
4719                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4720                 return;
4721         }
4722
4723         memset(&ctxt, 0, sizeof(ctxt));
4724         ctxt.seid = pf->main_vsi_seid;
4725         ctxt.pf_num = hw->pf_id;
4726         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4727         if (ret) {
4728                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4729                             ret, hw->aq.asq_last_status);
4730                 return;
4731         }
4732         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4733         ctxt.info.valid_sections =
4734                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4735         ctxt.info.switch_id |=
4736                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4737
4738         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4739         if (ret)
4740                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4741                             hw->aq.asq_last_status);
4742 }
4743
4744 /* Setup a VSI */
4745 struct i40e_vsi *
4746 i40e_vsi_setup(struct i40e_pf *pf,
4747                enum i40e_vsi_type type,
4748                struct i40e_vsi *uplink_vsi,
4749                uint16_t user_param)
4750 {
4751         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4752         struct i40e_vsi *vsi;
4753         struct i40e_mac_filter_info filter;
4754         int ret;
4755         struct i40e_vsi_context ctxt;
4756         struct ether_addr broadcast =
4757                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4758
4759         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4760             uplink_vsi == NULL) {
4761                 PMD_DRV_LOG(ERR,
4762                         "VSI setup failed, VSI link shouldn't be NULL");
4763                 return NULL;
4764         }
4765
4766         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4767                 PMD_DRV_LOG(ERR,
4768                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4769                 return NULL;
4770         }
4771
4772         /* two situations
4773          * 1.type is not MAIN and uplink vsi is not NULL
4774          * If uplink vsi didn't setup VEB, create one first under veb field
4775          * 2.type is SRIOV and the uplink is NULL
4776          * If floating VEB is NULL, create one veb under floating veb field
4777          */
4778
4779         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4780             uplink_vsi->veb == NULL) {
4781                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4782
4783                 if (uplink_vsi->veb == NULL) {
4784                         PMD_DRV_LOG(ERR, "VEB setup failed");
4785                         return NULL;
4786                 }
4787                 /* set ALLOWLOOPBACk on pf, when veb is created */
4788                 i40e_enable_pf_lb(pf);
4789         }
4790
4791         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4792             pf->main_vsi->floating_veb == NULL) {
4793                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4794
4795                 if (pf->main_vsi->floating_veb == NULL) {
4796                         PMD_DRV_LOG(ERR, "VEB setup failed");
4797                         return NULL;
4798                 }
4799         }
4800
4801         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4802         if (!vsi) {
4803                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4804                 return NULL;
4805         }
4806         TAILQ_INIT(&vsi->mac_list);
4807         vsi->type = type;
4808         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4809         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4810         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4811         vsi->user_param = user_param;
4812         vsi->vlan_anti_spoof_on = 0;
4813         vsi->vlan_filter_on = 0;
4814         /* Allocate queues */
4815         switch (vsi->type) {
4816         case I40E_VSI_MAIN  :
4817                 vsi->nb_qps = pf->lan_nb_qps;
4818                 break;
4819         case I40E_VSI_SRIOV :
4820                 vsi->nb_qps = pf->vf_nb_qps;
4821                 break;
4822         case I40E_VSI_VMDQ2:
4823                 vsi->nb_qps = pf->vmdq_nb_qps;
4824                 break;
4825         case I40E_VSI_FDIR:
4826                 vsi->nb_qps = pf->fdir_nb_qps;
4827                 break;
4828         default:
4829                 goto fail_mem;
4830         }
4831         /*
4832          * The filter status descriptor is reported in rx queue 0,
4833          * while the tx queue for fdir filter programming has no
4834          * such constraints, can be non-zero queues.
4835          * To simplify it, choose FDIR vsi use queue 0 pair.
4836          * To make sure it will use queue 0 pair, queue allocation
4837          * need be done before this function is called
4838          */
4839         if (type != I40E_VSI_FDIR) {
4840                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4841                         if (ret < 0) {
4842                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4843                                                 vsi->seid, ret);
4844                                 goto fail_mem;
4845                         }
4846                         vsi->base_queue = ret;
4847         } else
4848                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4849
4850         /* VF has MSIX interrupt in VF range, don't allocate here */
4851         if (type == I40E_VSI_MAIN) {
4852                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4853                                           RTE_MIN(vsi->nb_qps,
4854                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4855                 if (ret < 0) {
4856                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4857                                     vsi->seid, ret);
4858                         goto fail_queue_alloc;
4859                 }
4860                 vsi->msix_intr = ret;
4861                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4862         } else if (type != I40E_VSI_SRIOV) {
4863                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4864                 if (ret < 0) {
4865                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4866                         goto fail_queue_alloc;
4867                 }
4868                 vsi->msix_intr = ret;
4869                 vsi->nb_msix = 1;
4870         } else {
4871                 vsi->msix_intr = 0;
4872                 vsi->nb_msix = 0;
4873         }
4874
4875         /* Add VSI */
4876         if (type == I40E_VSI_MAIN) {
4877                 /* For main VSI, no need to add since it's default one */
4878                 vsi->uplink_seid = pf->mac_seid;
4879                 vsi->seid = pf->main_vsi_seid;
4880                 /* Bind queues with specific MSIX interrupt */
4881                 /**
4882                  * Needs 2 interrupt at least, one for misc cause which will
4883                  * enabled from OS side, Another for queues binding the
4884                  * interrupt from device side only.
4885                  */
4886
4887                 /* Get default VSI parameters from hardware */
4888                 memset(&ctxt, 0, sizeof(ctxt));
4889                 ctxt.seid = vsi->seid;
4890                 ctxt.pf_num = hw->pf_id;
4891                 ctxt.uplink_seid = vsi->uplink_seid;
4892                 ctxt.vf_num = 0;
4893                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4894                 if (ret != I40E_SUCCESS) {
4895                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4896                         goto fail_msix_alloc;
4897                 }
4898                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4899                         sizeof(struct i40e_aqc_vsi_properties_data));
4900                 vsi->vsi_id = ctxt.vsi_number;
4901                 vsi->info.valid_sections = 0;
4902
4903                 /* Configure tc, enabled TC0 only */
4904                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4905                         I40E_SUCCESS) {
4906                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4907                         goto fail_msix_alloc;
4908                 }
4909
4910                 /* TC, queue mapping */
4911                 memset(&ctxt, 0, sizeof(ctxt));
4912                 vsi->info.valid_sections |=
4913                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4914                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4915                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4916                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4917                         sizeof(struct i40e_aqc_vsi_properties_data));
4918                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4919                                                 I40E_DEFAULT_TCMAP);
4920                 if (ret != I40E_SUCCESS) {
4921                         PMD_DRV_LOG(ERR,
4922                                 "Failed to configure TC queue mapping");
4923                         goto fail_msix_alloc;
4924                 }
4925                 ctxt.seid = vsi->seid;
4926                 ctxt.pf_num = hw->pf_id;
4927                 ctxt.uplink_seid = vsi->uplink_seid;
4928                 ctxt.vf_num = 0;
4929
4930                 /* Update VSI parameters */
4931                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4932                 if (ret != I40E_SUCCESS) {
4933                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4934                         goto fail_msix_alloc;
4935                 }
4936
4937                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4938                                                 sizeof(vsi->info.tc_mapping));
4939                 (void)rte_memcpy(&vsi->info.queue_mapping,
4940                                 &ctxt.info.queue_mapping,
4941                         sizeof(vsi->info.queue_mapping));
4942                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4943                 vsi->info.valid_sections = 0;
4944
4945                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4946                                 ETH_ADDR_LEN);
4947
4948                 /**
4949                  * Updating default filter settings are necessary to prevent
4950                  * reception of tagged packets.
4951                  * Some old firmware configurations load a default macvlan
4952                  * filter which accepts both tagged and untagged packets.
4953                  * The updating is to use a normal filter instead if needed.
4954                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4955                  * The firmware with correct configurations load the default
4956                  * macvlan filter which is expected and cannot be removed.
4957                  */
4958                 i40e_update_default_filter_setting(vsi);
4959                 i40e_config_qinq(hw, vsi);
4960         } else if (type == I40E_VSI_SRIOV) {
4961                 memset(&ctxt, 0, sizeof(ctxt));
4962                 /**
4963                  * For other VSI, the uplink_seid equals to uplink VSI's
4964                  * uplink_seid since they share same VEB
4965                  */
4966                 if (uplink_vsi == NULL)
4967                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4968                 else
4969                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4970                 ctxt.pf_num = hw->pf_id;
4971                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4972                 ctxt.uplink_seid = vsi->uplink_seid;
4973                 ctxt.connection_type = 0x1;
4974                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4975
4976                 /* Use the VEB configuration if FW >= v5.0 */
4977                 if (hw->aq.fw_maj_ver >= 5) {
4978                         /* Configure switch ID */
4979                         ctxt.info.valid_sections |=
4980                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4981                         ctxt.info.switch_id =
4982                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4983                 }
4984
4985                 /* Configure port/vlan */
4986                 ctxt.info.valid_sections |=
4987                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4988                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4989                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4990                                                 hw->func_caps.enabled_tcmap);
4991                 if (ret != I40E_SUCCESS) {
4992                         PMD_DRV_LOG(ERR,
4993                                 "Failed to configure TC queue mapping");
4994                         goto fail_msix_alloc;
4995                 }
4996
4997                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4998                 ctxt.info.valid_sections |=
4999                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5000                 /**
5001                  * Since VSI is not created yet, only configure parameter,
5002                  * will add vsi below.
5003                  */
5004
5005                 i40e_config_qinq(hw, vsi);
5006         } else if (type == I40E_VSI_VMDQ2) {
5007                 memset(&ctxt, 0, sizeof(ctxt));
5008                 /*
5009                  * For other VSI, the uplink_seid equals to uplink VSI's
5010                  * uplink_seid since they share same VEB
5011                  */
5012                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5013                 ctxt.pf_num = hw->pf_id;
5014                 ctxt.vf_num = 0;
5015                 ctxt.uplink_seid = vsi->uplink_seid;
5016                 ctxt.connection_type = 0x1;
5017                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5018
5019                 ctxt.info.valid_sections |=
5020                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5021                 /* user_param carries flag to enable loop back */
5022                 if (user_param) {
5023                         ctxt.info.switch_id =
5024                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5025                         ctxt.info.switch_id |=
5026                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5027                 }
5028
5029                 /* Configure port/vlan */
5030                 ctxt.info.valid_sections |=
5031                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5032                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5033                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5034                                                 I40E_DEFAULT_TCMAP);
5035                 if (ret != I40E_SUCCESS) {
5036                         PMD_DRV_LOG(ERR,
5037                                 "Failed to configure TC queue mapping");
5038                         goto fail_msix_alloc;
5039                 }
5040                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5041                 ctxt.info.valid_sections |=
5042                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5043         } else if (type == I40E_VSI_FDIR) {
5044                 memset(&ctxt, 0, sizeof(ctxt));
5045                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5046                 ctxt.pf_num = hw->pf_id;
5047                 ctxt.vf_num = 0;
5048                 ctxt.uplink_seid = vsi->uplink_seid;
5049                 ctxt.connection_type = 0x1;     /* regular data port */
5050                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5051                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5052                                                 I40E_DEFAULT_TCMAP);
5053                 if (ret != I40E_SUCCESS) {
5054                         PMD_DRV_LOG(ERR,
5055                                 "Failed to configure TC queue mapping.");
5056                         goto fail_msix_alloc;
5057                 }
5058                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5059                 ctxt.info.valid_sections |=
5060                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5061         } else {
5062                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5063                 goto fail_msix_alloc;
5064         }
5065
5066         if (vsi->type != I40E_VSI_MAIN) {
5067                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5068                 if (ret != I40E_SUCCESS) {
5069                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5070                                     hw->aq.asq_last_status);
5071                         goto fail_msix_alloc;
5072                 }
5073                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5074                 vsi->info.valid_sections = 0;
5075                 vsi->seid = ctxt.seid;
5076                 vsi->vsi_id = ctxt.vsi_number;
5077                 vsi->sib_vsi_list.vsi = vsi;
5078                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5079                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5080                                           &vsi->sib_vsi_list, list);
5081                 } else {
5082                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5083                                           &vsi->sib_vsi_list, list);
5084                 }
5085         }
5086
5087         /* MAC/VLAN configuration */
5088         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5089         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5090
5091         ret = i40e_vsi_add_mac(vsi, &filter);
5092         if (ret != I40E_SUCCESS) {
5093                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5094                 goto fail_msix_alloc;
5095         }
5096
5097         /* Get VSI BW information */
5098         i40e_vsi_get_bw_config(vsi);
5099         return vsi;
5100 fail_msix_alloc:
5101         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5102 fail_queue_alloc:
5103         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5104 fail_mem:
5105         rte_free(vsi);
5106         return NULL;
5107 }
5108
5109 /* Configure vlan filter on or off */
5110 int
5111 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5112 {
5113         int i, num;
5114         struct i40e_mac_filter *f;
5115         void *temp;
5116         struct i40e_mac_filter_info *mac_filter;
5117         enum rte_mac_filter_type desired_filter;
5118         int ret = I40E_SUCCESS;
5119
5120         if (on) {
5121                 /* Filter to match MAC and VLAN */
5122                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5123         } else {
5124                 /* Filter to match only MAC */
5125                 desired_filter = RTE_MAC_PERFECT_MATCH;
5126         }
5127
5128         num = vsi->mac_num;
5129
5130         mac_filter = rte_zmalloc("mac_filter_info_data",
5131                                  num * sizeof(*mac_filter), 0);
5132         if (mac_filter == NULL) {
5133                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5134                 return I40E_ERR_NO_MEMORY;
5135         }
5136
5137         i = 0;
5138
5139         /* Remove all existing mac */
5140         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5141                 mac_filter[i] = f->mac_info;
5142                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5143                 if (ret) {
5144                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5145                                     on ? "enable" : "disable");
5146                         goto DONE;
5147                 }
5148                 i++;
5149         }
5150
5151         /* Override with new filter */
5152         for (i = 0; i < num; i++) {
5153                 mac_filter[i].filter_type = desired_filter;
5154                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5155                 if (ret) {
5156                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5157                                     on ? "enable" : "disable");
5158                         goto DONE;
5159                 }
5160         }
5161
5162 DONE:
5163         rte_free(mac_filter);
5164         return ret;
5165 }
5166
5167 /* Configure vlan stripping on or off */
5168 int
5169 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5170 {
5171         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5172         struct i40e_vsi_context ctxt;
5173         uint8_t vlan_flags;
5174         int ret = I40E_SUCCESS;
5175
5176         /* Check if it has been already on or off */
5177         if (vsi->info.valid_sections &
5178                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5179                 if (on) {
5180                         if ((vsi->info.port_vlan_flags &
5181                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5182                                 return 0; /* already on */
5183                 } else {
5184                         if ((vsi->info.port_vlan_flags &
5185                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5186                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5187                                 return 0; /* already off */
5188                 }
5189         }
5190
5191         if (on)
5192                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5193         else
5194                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5195         vsi->info.valid_sections =
5196                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5197         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5198         vsi->info.port_vlan_flags |= vlan_flags;
5199         ctxt.seid = vsi->seid;
5200         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5201         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5202         if (ret)
5203                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5204                             on ? "enable" : "disable");
5205
5206         return ret;
5207 }
5208
5209 static int
5210 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5211 {
5212         struct rte_eth_dev_data *data = dev->data;
5213         int ret;
5214         int mask = 0;
5215
5216         /* Apply vlan offload setting */
5217         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5218         i40e_vlan_offload_set(dev, mask);
5219
5220         /* Apply double-vlan setting, not implemented yet */
5221
5222         /* Apply pvid setting */
5223         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5224                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5225         if (ret)
5226                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5227
5228         return ret;
5229 }
5230
5231 static int
5232 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5233 {
5234         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5235
5236         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5237 }
5238
5239 static int
5240 i40e_update_flow_control(struct i40e_hw *hw)
5241 {
5242 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5243         struct i40e_link_status link_status;
5244         uint32_t rxfc = 0, txfc = 0, reg;
5245         uint8_t an_info;
5246         int ret;
5247
5248         memset(&link_status, 0, sizeof(link_status));
5249         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5250         if (ret != I40E_SUCCESS) {
5251                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5252                 goto write_reg; /* Disable flow control */
5253         }
5254
5255         an_info = hw->phy.link_info.an_info;
5256         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5257                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5258                 ret = I40E_ERR_NOT_READY;
5259                 goto write_reg; /* Disable flow control */
5260         }
5261         /**
5262          * If link auto negotiation is enabled, flow control needs to
5263          * be configured according to it
5264          */
5265         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5266         case I40E_LINK_PAUSE_RXTX:
5267                 rxfc = 1;
5268                 txfc = 1;
5269                 hw->fc.current_mode = I40E_FC_FULL;
5270                 break;
5271         case I40E_AQ_LINK_PAUSE_RX:
5272                 rxfc = 1;
5273                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5274                 break;
5275         case I40E_AQ_LINK_PAUSE_TX:
5276                 txfc = 1;
5277                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5278                 break;
5279         default:
5280                 hw->fc.current_mode = I40E_FC_NONE;
5281                 break;
5282         }
5283
5284 write_reg:
5285         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5286                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5287         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5288         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5289         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5290         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5291
5292         return ret;
5293 }
5294
5295 /* PF setup */
5296 static int
5297 i40e_pf_setup(struct i40e_pf *pf)
5298 {
5299         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5300         struct i40e_filter_control_settings settings;
5301         struct i40e_vsi *vsi;
5302         int ret;
5303
5304         /* Clear all stats counters */
5305         pf->offset_loaded = FALSE;
5306         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5307         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5308         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5309         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5310
5311         ret = i40e_pf_get_switch_config(pf);
5312         if (ret != I40E_SUCCESS) {
5313                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5314                 return ret;
5315         }
5316         if (pf->flags & I40E_FLAG_FDIR) {
5317                 /* make queue allocated first, let FDIR use queue pair 0*/
5318                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5319                 if (ret != I40E_FDIR_QUEUE_ID) {
5320                         PMD_DRV_LOG(ERR,
5321                                 "queue allocation fails for FDIR: ret =%d",
5322                                 ret);
5323                         pf->flags &= ~I40E_FLAG_FDIR;
5324                 }
5325         }
5326         /*  main VSI setup */
5327         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5328         if (!vsi) {
5329                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5330                 return I40E_ERR_NOT_READY;
5331         }
5332         pf->main_vsi = vsi;
5333
5334         /* Configure filter control */
5335         memset(&settings, 0, sizeof(settings));
5336         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5337                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5338         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5339                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5340         else {
5341                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5342                         hw->func_caps.rss_table_size);
5343                 return I40E_ERR_PARAM;
5344         }
5345         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5346                 hw->func_caps.rss_table_size);
5347         pf->hash_lut_size = hw->func_caps.rss_table_size;
5348
5349         /* Enable ethtype and macvlan filters */
5350         settings.enable_ethtype = TRUE;
5351         settings.enable_macvlan = TRUE;
5352         ret = i40e_set_filter_control(hw, &settings);
5353         if (ret)
5354                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5355                                                                 ret);
5356
5357         /* Update flow control according to the auto negotiation */
5358         i40e_update_flow_control(hw);
5359
5360         return I40E_SUCCESS;
5361 }
5362
5363 int
5364 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5365 {
5366         uint32_t reg;
5367         uint16_t j;
5368
5369         /**
5370          * Set or clear TX Queue Disable flags,
5371          * which is required by hardware.
5372          */
5373         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5374         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5375
5376         /* Wait until the request is finished */
5377         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5378                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5379                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5380                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5381                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5382                                                         & 0x1))) {
5383                         break;
5384                 }
5385         }
5386         if (on) {
5387                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5388                         return I40E_SUCCESS; /* already on, skip next steps */
5389
5390                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5391                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5392         } else {
5393                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5394                         return I40E_SUCCESS; /* already off, skip next steps */
5395                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5396         }
5397         /* Write the register */
5398         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5399         /* Check the result */
5400         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5401                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5402                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5403                 if (on) {
5404                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5405                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5406                                 break;
5407                 } else {
5408                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5409                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5410                                 break;
5411                 }
5412         }
5413         /* Check if it is timeout */
5414         if (j >= I40E_CHK_Q_ENA_COUNT) {
5415                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5416                             (on ? "enable" : "disable"), q_idx);
5417                 return I40E_ERR_TIMEOUT;
5418         }
5419
5420         return I40E_SUCCESS;
5421 }
5422
5423 /* Swith on or off the tx queues */
5424 static int
5425 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5426 {
5427         struct rte_eth_dev_data *dev_data = pf->dev_data;
5428         struct i40e_tx_queue *txq;
5429         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5430         uint16_t i;
5431         int ret;
5432
5433         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5434                 txq = dev_data->tx_queues[i];
5435                 /* Don't operate the queue if not configured or
5436                  * if starting only per queue */
5437                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5438                         continue;
5439                 if (on)
5440                         ret = i40e_dev_tx_queue_start(dev, i);
5441                 else
5442                         ret = i40e_dev_tx_queue_stop(dev, i);
5443                 if ( ret != I40E_SUCCESS)
5444                         return ret;
5445         }
5446
5447         return I40E_SUCCESS;
5448 }
5449
5450 int
5451 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5452 {
5453         uint32_t reg;
5454         uint16_t j;
5455
5456         /* Wait until the request is finished */
5457         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5458                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5459                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5460                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5461                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5462                         break;
5463         }
5464
5465         if (on) {
5466                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5467                         return I40E_SUCCESS; /* Already on, skip next steps */
5468                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5469         } else {
5470                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5471                         return I40E_SUCCESS; /* Already off, skip next steps */
5472                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5473         }
5474
5475         /* Write the register */
5476         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5477         /* Check the result */
5478         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5479                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5480                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5481                 if (on) {
5482                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5483                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5484                                 break;
5485                 } else {
5486                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5487                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5488                                 break;
5489                 }
5490         }
5491
5492         /* Check if it is timeout */
5493         if (j >= I40E_CHK_Q_ENA_COUNT) {
5494                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5495                             (on ? "enable" : "disable"), q_idx);
5496                 return I40E_ERR_TIMEOUT;
5497         }
5498
5499         return I40E_SUCCESS;
5500 }
5501 /* Switch on or off the rx queues */
5502 static int
5503 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5504 {
5505         struct rte_eth_dev_data *dev_data = pf->dev_data;
5506         struct i40e_rx_queue *rxq;
5507         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5508         uint16_t i;
5509         int ret;
5510
5511         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5512                 rxq = dev_data->rx_queues[i];
5513                 /* Don't operate the queue if not configured or
5514                  * if starting only per queue */
5515                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5516                         continue;
5517                 if (on)
5518                         ret = i40e_dev_rx_queue_start(dev, i);
5519                 else
5520                         ret = i40e_dev_rx_queue_stop(dev, i);
5521                 if (ret != I40E_SUCCESS)
5522                         return ret;
5523         }
5524
5525         return I40E_SUCCESS;
5526 }
5527
5528 /* Switch on or off all the rx/tx queues */
5529 int
5530 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5531 {
5532         int ret;
5533
5534         if (on) {
5535                 /* enable rx queues before enabling tx queues */
5536                 ret = i40e_dev_switch_rx_queues(pf, on);
5537                 if (ret) {
5538                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5539                         return ret;
5540                 }
5541                 ret = i40e_dev_switch_tx_queues(pf, on);
5542         } else {
5543                 /* Stop tx queues before stopping rx queues */
5544                 ret = i40e_dev_switch_tx_queues(pf, on);
5545                 if (ret) {
5546                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5547                         return ret;
5548                 }
5549                 ret = i40e_dev_switch_rx_queues(pf, on);
5550         }
5551
5552         return ret;
5553 }
5554
5555 /* Initialize VSI for TX */
5556 static int
5557 i40e_dev_tx_init(struct i40e_pf *pf)
5558 {
5559         struct rte_eth_dev_data *data = pf->dev_data;
5560         uint16_t i;
5561         uint32_t ret = I40E_SUCCESS;
5562         struct i40e_tx_queue *txq;
5563
5564         for (i = 0; i < data->nb_tx_queues; i++) {
5565                 txq = data->tx_queues[i];
5566                 if (!txq || !txq->q_set)
5567                         continue;
5568                 ret = i40e_tx_queue_init(txq);
5569                 if (ret != I40E_SUCCESS)
5570                         break;
5571         }
5572         if (ret == I40E_SUCCESS)
5573                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5574                                      ->eth_dev);
5575
5576         return ret;
5577 }
5578
5579 /* Initialize VSI for RX */
5580 static int
5581 i40e_dev_rx_init(struct i40e_pf *pf)
5582 {
5583         struct rte_eth_dev_data *data = pf->dev_data;
5584         int ret = I40E_SUCCESS;
5585         uint16_t i;
5586         struct i40e_rx_queue *rxq;
5587
5588         i40e_pf_config_mq_rx(pf);
5589         for (i = 0; i < data->nb_rx_queues; i++) {
5590                 rxq = data->rx_queues[i];
5591                 if (!rxq || !rxq->q_set)
5592                         continue;
5593
5594                 ret = i40e_rx_queue_init(rxq);
5595                 if (ret != I40E_SUCCESS) {
5596                         PMD_DRV_LOG(ERR,
5597                                 "Failed to do RX queue initialization");
5598                         break;
5599                 }
5600         }
5601         if (ret == I40E_SUCCESS)
5602                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5603                                      ->eth_dev);
5604
5605         return ret;
5606 }
5607
5608 static int
5609 i40e_dev_rxtx_init(struct i40e_pf *pf)
5610 {
5611         int err;
5612
5613         err = i40e_dev_tx_init(pf);
5614         if (err) {
5615                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5616                 return err;
5617         }
5618         err = i40e_dev_rx_init(pf);
5619         if (err) {
5620                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5621                 return err;
5622         }
5623
5624         return err;
5625 }
5626
5627 static int
5628 i40e_vmdq_setup(struct rte_eth_dev *dev)
5629 {
5630         struct rte_eth_conf *conf = &dev->data->dev_conf;
5631         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5632         int i, err, conf_vsis, j, loop;
5633         struct i40e_vsi *vsi;
5634         struct i40e_vmdq_info *vmdq_info;
5635         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5636         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5637
5638         /*
5639          * Disable interrupt to avoid message from VF. Furthermore, it will
5640          * avoid race condition in VSI creation/destroy.
5641          */
5642         i40e_pf_disable_irq0(hw);
5643
5644         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5645                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5646                 return -ENOTSUP;
5647         }
5648
5649         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5650         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5651                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5652                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5653                         pf->max_nb_vmdq_vsi);
5654                 return -ENOTSUP;
5655         }
5656
5657         if (pf->vmdq != NULL) {
5658                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5659                 return 0;
5660         }
5661
5662         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5663                                 sizeof(*vmdq_info) * conf_vsis, 0);
5664
5665         if (pf->vmdq == NULL) {
5666                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5667                 return -ENOMEM;
5668         }
5669
5670         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5671
5672         /* Create VMDQ VSI */
5673         for (i = 0; i < conf_vsis; i++) {
5674                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5675                                 vmdq_conf->enable_loop_back);
5676                 if (vsi == NULL) {
5677                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5678                         err = -1;
5679                         goto err_vsi_setup;
5680                 }
5681                 vmdq_info = &pf->vmdq[i];
5682                 vmdq_info->pf = pf;
5683                 vmdq_info->vsi = vsi;
5684         }
5685         pf->nb_cfg_vmdq_vsi = conf_vsis;
5686
5687         /* Configure Vlan */
5688         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5689         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5690                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5691                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5692                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5693                                         vmdq_conf->pool_map[i].vlan_id, j);
5694
5695                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5696                                                 vmdq_conf->pool_map[i].vlan_id);
5697                                 if (err) {
5698                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5699                                         err = -1;
5700                                         goto err_vsi_setup;
5701                                 }
5702                         }
5703                 }
5704         }
5705
5706         i40e_pf_enable_irq0(hw);
5707
5708         return 0;
5709
5710 err_vsi_setup:
5711         for (i = 0; i < conf_vsis; i++)
5712                 if (pf->vmdq[i].vsi == NULL)
5713                         break;
5714                 else
5715                         i40e_vsi_release(pf->vmdq[i].vsi);
5716
5717         rte_free(pf->vmdq);
5718         pf->vmdq = NULL;
5719         i40e_pf_enable_irq0(hw);
5720         return err;
5721 }
5722
5723 static void
5724 i40e_stat_update_32(struct i40e_hw *hw,
5725                    uint32_t reg,
5726                    bool offset_loaded,
5727                    uint64_t *offset,
5728                    uint64_t *stat)
5729 {
5730         uint64_t new_data;
5731
5732         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5733         if (!offset_loaded)
5734                 *offset = new_data;
5735
5736         if (new_data >= *offset)
5737                 *stat = (uint64_t)(new_data - *offset);
5738         else
5739                 *stat = (uint64_t)((new_data +
5740                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5741 }
5742
5743 static void
5744 i40e_stat_update_48(struct i40e_hw *hw,
5745                    uint32_t hireg,
5746                    uint32_t loreg,
5747                    bool offset_loaded,
5748                    uint64_t *offset,
5749                    uint64_t *stat)
5750 {
5751         uint64_t new_data;
5752
5753         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5754         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5755                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5756
5757         if (!offset_loaded)
5758                 *offset = new_data;
5759
5760         if (new_data >= *offset)
5761                 *stat = new_data - *offset;
5762         else
5763                 *stat = (uint64_t)((new_data +
5764                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5765
5766         *stat &= I40E_48_BIT_MASK;
5767 }
5768
5769 /* Disable IRQ0 */
5770 void
5771 i40e_pf_disable_irq0(struct i40e_hw *hw)
5772 {
5773         /* Disable all interrupt types */
5774         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5775         I40E_WRITE_FLUSH(hw);
5776 }
5777
5778 /* Enable IRQ0 */
5779 void
5780 i40e_pf_enable_irq0(struct i40e_hw *hw)
5781 {
5782         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5783                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5784                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5785                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5786         I40E_WRITE_FLUSH(hw);
5787 }
5788
5789 static void
5790 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5791 {
5792         /* read pending request and disable first */
5793         i40e_pf_disable_irq0(hw);
5794         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5795         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5796                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5797
5798         if (no_queue)
5799                 /* Link no queues with irq0 */
5800                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5801                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5802 }
5803
5804 static void
5805 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5806 {
5807         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5808         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5809         int i;
5810         uint16_t abs_vf_id;
5811         uint32_t index, offset, val;
5812
5813         if (!pf->vfs)
5814                 return;
5815         /**
5816          * Try to find which VF trigger a reset, use absolute VF id to access
5817          * since the reg is global register.
5818          */
5819         for (i = 0; i < pf->vf_num; i++) {
5820                 abs_vf_id = hw->func_caps.vf_base_id + i;
5821                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5822                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5823                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5824                 /* VFR event occurred */
5825                 if (val & (0x1 << offset)) {
5826                         int ret;
5827
5828                         /* Clear the event first */
5829                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5830                                                         (0x1 << offset));
5831                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5832                         /**
5833                          * Only notify a VF reset event occurred,
5834                          * don't trigger another SW reset
5835                          */
5836                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5837                         if (ret != I40E_SUCCESS)
5838                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5839                 }
5840         }
5841 }
5842
5843 static void
5844 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5845 {
5846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5847         int i;
5848
5849         for (i = 0; i < pf->vf_num; i++)
5850                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5851 }
5852
5853 static void
5854 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5855 {
5856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5857         struct i40e_arq_event_info info;
5858         uint16_t pending, opcode;
5859         int ret;
5860
5861         info.buf_len = I40E_AQ_BUF_SZ;
5862         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5863         if (!info.msg_buf) {
5864                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5865                 return;
5866         }
5867
5868         pending = 1;
5869         while (pending) {
5870                 ret = i40e_clean_arq_element(hw, &info, &pending);
5871
5872                 if (ret != I40E_SUCCESS) {
5873                         PMD_DRV_LOG(INFO,
5874                                 "Failed to read msg from AdminQ, aq_err: %u",
5875                                 hw->aq.asq_last_status);
5876                         break;
5877                 }
5878                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5879
5880                 switch (opcode) {
5881                 case i40e_aqc_opc_send_msg_to_pf:
5882                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5883                         i40e_pf_host_handle_vf_msg(dev,
5884                                         rte_le_to_cpu_16(info.desc.retval),
5885                                         rte_le_to_cpu_32(info.desc.cookie_high),
5886                                         rte_le_to_cpu_32(info.desc.cookie_low),
5887                                         info.msg_buf,
5888                                         info.msg_len);
5889                         break;
5890                 case i40e_aqc_opc_get_link_status:
5891                         ret = i40e_dev_link_update(dev, 0);
5892                         if (!ret)
5893                                 _rte_eth_dev_callback_process(dev,
5894                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5895                         break;
5896                 default:
5897                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5898                                     opcode);
5899                         break;
5900                 }
5901         }
5902         rte_free(info.msg_buf);
5903 }
5904
5905 /**
5906  * Interrupt handler triggered by NIC  for handling
5907  * specific interrupt.
5908  *
5909  * @param handle
5910  *  Pointer to interrupt handle.
5911  * @param param
5912  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5913  *
5914  * @return
5915  *  void
5916  */
5917 static void
5918 i40e_dev_interrupt_handler(void *param)
5919 {
5920         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5922         uint32_t icr0;
5923
5924         /* Disable interrupt */
5925         i40e_pf_disable_irq0(hw);
5926
5927         /* read out interrupt causes */
5928         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5929
5930         /* No interrupt event indicated */
5931         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5932                 PMD_DRV_LOG(INFO, "No interrupt event");
5933                 goto done;
5934         }
5935         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5936                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5937         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5938                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5939         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5940                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5941         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5942                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5943         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5944                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5945         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5946                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5947         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5948                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5949
5950         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5951                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5952                 i40e_dev_handle_vfr_event(dev);
5953         }
5954         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5955                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5956                 i40e_dev_handle_aq_msg(dev);
5957         }
5958
5959 done:
5960         /* Enable interrupt */
5961         i40e_pf_enable_irq0(hw);
5962         rte_intr_enable(dev->intr_handle);
5963 }
5964
5965 int
5966 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5967                          struct i40e_macvlan_filter *filter,
5968                          int total)
5969 {
5970         int ele_num, ele_buff_size;
5971         int num, actual_num, i;
5972         uint16_t flags;
5973         int ret = I40E_SUCCESS;
5974         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5975         struct i40e_aqc_add_macvlan_element_data *req_list;
5976
5977         if (filter == NULL  || total == 0)
5978                 return I40E_ERR_PARAM;
5979         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5980         ele_buff_size = hw->aq.asq_buf_size;
5981
5982         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5983         if (req_list == NULL) {
5984                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5985                 return I40E_ERR_NO_MEMORY;
5986         }
5987
5988         num = 0;
5989         do {
5990                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5991                 memset(req_list, 0, ele_buff_size);
5992
5993                 for (i = 0; i < actual_num; i++) {
5994                         (void)rte_memcpy(req_list[i].mac_addr,
5995                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5996                         req_list[i].vlan_tag =
5997                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5998
5999                         switch (filter[num + i].filter_type) {
6000                         case RTE_MAC_PERFECT_MATCH:
6001                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6002                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6003                                 break;
6004                         case RTE_MACVLAN_PERFECT_MATCH:
6005                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6006                                 break;
6007                         case RTE_MAC_HASH_MATCH:
6008                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6009                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6010                                 break;
6011                         case RTE_MACVLAN_HASH_MATCH:
6012                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6013                                 break;
6014                         default:
6015                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6016                                 ret = I40E_ERR_PARAM;
6017                                 goto DONE;
6018                         }
6019
6020                         req_list[i].queue_number = 0;
6021
6022                         req_list[i].flags = rte_cpu_to_le_16(flags);
6023                 }
6024
6025                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6026                                                 actual_num, NULL);
6027                 if (ret != I40E_SUCCESS) {
6028                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6029                         goto DONE;
6030                 }
6031                 num += actual_num;
6032         } while (num < total);
6033
6034 DONE:
6035         rte_free(req_list);
6036         return ret;
6037 }
6038
6039 int
6040 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6041                             struct i40e_macvlan_filter *filter,
6042                             int total)
6043 {
6044         int ele_num, ele_buff_size;
6045         int num, actual_num, i;
6046         uint16_t flags;
6047         int ret = I40E_SUCCESS;
6048         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6049         struct i40e_aqc_remove_macvlan_element_data *req_list;
6050
6051         if (filter == NULL  || total == 0)
6052                 return I40E_ERR_PARAM;
6053
6054         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6055         ele_buff_size = hw->aq.asq_buf_size;
6056
6057         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6058         if (req_list == NULL) {
6059                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6060                 return I40E_ERR_NO_MEMORY;
6061         }
6062
6063         num = 0;
6064         do {
6065                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6066                 memset(req_list, 0, ele_buff_size);
6067
6068                 for (i = 0; i < actual_num; i++) {
6069                         (void)rte_memcpy(req_list[i].mac_addr,
6070                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6071                         req_list[i].vlan_tag =
6072                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6073
6074                         switch (filter[num + i].filter_type) {
6075                         case RTE_MAC_PERFECT_MATCH:
6076                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6077                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6078                                 break;
6079                         case RTE_MACVLAN_PERFECT_MATCH:
6080                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6081                                 break;
6082                         case RTE_MAC_HASH_MATCH:
6083                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6084                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6085                                 break;
6086                         case RTE_MACVLAN_HASH_MATCH:
6087                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6088                                 break;
6089                         default:
6090                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6091                                 ret = I40E_ERR_PARAM;
6092                                 goto DONE;
6093                         }
6094                         req_list[i].flags = rte_cpu_to_le_16(flags);
6095                 }
6096
6097                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6098                                                 actual_num, NULL);
6099                 if (ret != I40E_SUCCESS) {
6100                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6101                         goto DONE;
6102                 }
6103                 num += actual_num;
6104         } while (num < total);
6105
6106 DONE:
6107         rte_free(req_list);
6108         return ret;
6109 }
6110
6111 /* Find out specific MAC filter */
6112 static struct i40e_mac_filter *
6113 i40e_find_mac_filter(struct i40e_vsi *vsi,
6114                          struct ether_addr *macaddr)
6115 {
6116         struct i40e_mac_filter *f;
6117
6118         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6119                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6120                         return f;
6121         }
6122
6123         return NULL;
6124 }
6125
6126 static bool
6127 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6128                          uint16_t vlan_id)
6129 {
6130         uint32_t vid_idx, vid_bit;
6131
6132         if (vlan_id > ETH_VLAN_ID_MAX)
6133                 return 0;
6134
6135         vid_idx = I40E_VFTA_IDX(vlan_id);
6136         vid_bit = I40E_VFTA_BIT(vlan_id);
6137
6138         if (vsi->vfta[vid_idx] & vid_bit)
6139                 return 1;
6140         else
6141                 return 0;
6142 }
6143
6144 static void
6145 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6146                        uint16_t vlan_id, bool on)
6147 {
6148         uint32_t vid_idx, vid_bit;
6149
6150         vid_idx = I40E_VFTA_IDX(vlan_id);
6151         vid_bit = I40E_VFTA_BIT(vlan_id);
6152
6153         if (on)
6154                 vsi->vfta[vid_idx] |= vid_bit;
6155         else
6156                 vsi->vfta[vid_idx] &= ~vid_bit;
6157 }
6158
6159 void
6160 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6161                      uint16_t vlan_id, bool on)
6162 {
6163         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6164         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6165         int ret;
6166
6167         if (vlan_id > ETH_VLAN_ID_MAX)
6168                 return;
6169
6170         i40e_store_vlan_filter(vsi, vlan_id, on);
6171
6172         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6173                 return;
6174
6175         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6176
6177         if (on) {
6178                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6179                                        &vlan_data, 1, NULL);
6180                 if (ret != I40E_SUCCESS)
6181                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6182         } else {
6183                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6184                                           &vlan_data, 1, NULL);
6185                 if (ret != I40E_SUCCESS)
6186                         PMD_DRV_LOG(ERR,
6187                                     "Failed to remove vlan filter");
6188         }
6189 }
6190
6191 /**
6192  * Find all vlan options for specific mac addr,
6193  * return with actual vlan found.
6194  */
6195 int
6196 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6197                            struct i40e_macvlan_filter *mv_f,
6198                            int num, struct ether_addr *addr)
6199 {
6200         int i;
6201         uint32_t j, k;
6202
6203         /**
6204          * Not to use i40e_find_vlan_filter to decrease the loop time,
6205          * although the code looks complex.
6206           */
6207         if (num < vsi->vlan_num)
6208                 return I40E_ERR_PARAM;
6209
6210         i = 0;
6211         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6212                 if (vsi->vfta[j]) {
6213                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6214                                 if (vsi->vfta[j] & (1 << k)) {
6215                                         if (i > num - 1) {
6216                                                 PMD_DRV_LOG(ERR,
6217                                                         "vlan number doesn't match");
6218                                                 return I40E_ERR_PARAM;
6219                                         }
6220                                         (void)rte_memcpy(&mv_f[i].macaddr,
6221                                                         addr, ETH_ADDR_LEN);
6222                                         mv_f[i].vlan_id =
6223                                                 j * I40E_UINT32_BIT_SIZE + k;
6224                                         i++;
6225                                 }
6226                         }
6227                 }
6228         }
6229         return I40E_SUCCESS;
6230 }
6231
6232 static inline int
6233 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6234                            struct i40e_macvlan_filter *mv_f,
6235                            int num,
6236                            uint16_t vlan)
6237 {
6238         int i = 0;
6239         struct i40e_mac_filter *f;
6240
6241         if (num < vsi->mac_num)
6242                 return I40E_ERR_PARAM;
6243
6244         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6245                 if (i > num - 1) {
6246                         PMD_DRV_LOG(ERR, "buffer number not match");
6247                         return I40E_ERR_PARAM;
6248                 }
6249                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6250                                 ETH_ADDR_LEN);
6251                 mv_f[i].vlan_id = vlan;
6252                 mv_f[i].filter_type = f->mac_info.filter_type;
6253                 i++;
6254         }
6255
6256         return I40E_SUCCESS;
6257 }
6258
6259 static int
6260 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6261 {
6262         int i, j, num;
6263         struct i40e_mac_filter *f;
6264         struct i40e_macvlan_filter *mv_f;
6265         int ret = I40E_SUCCESS;
6266
6267         if (vsi == NULL || vsi->mac_num == 0)
6268                 return I40E_ERR_PARAM;
6269
6270         /* Case that no vlan is set */
6271         if (vsi->vlan_num == 0)
6272                 num = vsi->mac_num;
6273         else
6274                 num = vsi->mac_num * vsi->vlan_num;
6275
6276         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6277         if (mv_f == NULL) {
6278                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6279                 return I40E_ERR_NO_MEMORY;
6280         }
6281
6282         i = 0;
6283         if (vsi->vlan_num == 0) {
6284                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6285                         (void)rte_memcpy(&mv_f[i].macaddr,
6286                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6287                         mv_f[i].filter_type = f->mac_info.filter_type;
6288                         mv_f[i].vlan_id = 0;
6289                         i++;
6290                 }
6291         } else {
6292                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6293                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6294                                         vsi->vlan_num, &f->mac_info.mac_addr);
6295                         if (ret != I40E_SUCCESS)
6296                                 goto DONE;
6297                         for (j = i; j < i + vsi->vlan_num; j++)
6298                                 mv_f[j].filter_type = f->mac_info.filter_type;
6299                         i += vsi->vlan_num;
6300                 }
6301         }
6302
6303         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6304 DONE:
6305         rte_free(mv_f);
6306
6307         return ret;
6308 }
6309
6310 int
6311 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6312 {
6313         struct i40e_macvlan_filter *mv_f;
6314         int mac_num;
6315         int ret = I40E_SUCCESS;
6316
6317         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6318                 return I40E_ERR_PARAM;
6319
6320         /* If it's already set, just return */
6321         if (i40e_find_vlan_filter(vsi,vlan))
6322                 return I40E_SUCCESS;
6323
6324         mac_num = vsi->mac_num;
6325
6326         if (mac_num == 0) {
6327                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6328                 return I40E_ERR_PARAM;
6329         }
6330
6331         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6332
6333         if (mv_f == NULL) {
6334                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6335                 return I40E_ERR_NO_MEMORY;
6336         }
6337
6338         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6339
6340         if (ret != I40E_SUCCESS)
6341                 goto DONE;
6342
6343         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6344
6345         if (ret != I40E_SUCCESS)
6346                 goto DONE;
6347
6348         i40e_set_vlan_filter(vsi, vlan, 1);
6349
6350         vsi->vlan_num++;
6351         ret = I40E_SUCCESS;
6352 DONE:
6353         rte_free(mv_f);
6354         return ret;
6355 }
6356
6357 int
6358 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6359 {
6360         struct i40e_macvlan_filter *mv_f;
6361         int mac_num;
6362         int ret = I40E_SUCCESS;
6363
6364         /**
6365          * Vlan 0 is the generic filter for untagged packets
6366          * and can't be removed.
6367          */
6368         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6369                 return I40E_ERR_PARAM;
6370
6371         /* If can't find it, just return */
6372         if (!i40e_find_vlan_filter(vsi, vlan))
6373                 return I40E_ERR_PARAM;
6374
6375         mac_num = vsi->mac_num;
6376
6377         if (mac_num == 0) {
6378                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6379                 return I40E_ERR_PARAM;
6380         }
6381
6382         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6383
6384         if (mv_f == NULL) {
6385                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6386                 return I40E_ERR_NO_MEMORY;
6387         }
6388
6389         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6390
6391         if (ret != I40E_SUCCESS)
6392                 goto DONE;
6393
6394         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6395
6396         if (ret != I40E_SUCCESS)
6397                 goto DONE;
6398
6399         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6400         if (vsi->vlan_num == 1) {
6401                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6402                 if (ret != I40E_SUCCESS)
6403                         goto DONE;
6404
6405                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6406                 if (ret != I40E_SUCCESS)
6407                         goto DONE;
6408         }
6409
6410         i40e_set_vlan_filter(vsi, vlan, 0);
6411
6412         vsi->vlan_num--;
6413         ret = I40E_SUCCESS;
6414 DONE:
6415         rte_free(mv_f);
6416         return ret;
6417 }
6418
6419 int
6420 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6421 {
6422         struct i40e_mac_filter *f;
6423         struct i40e_macvlan_filter *mv_f;
6424         int i, vlan_num = 0;
6425         int ret = I40E_SUCCESS;
6426
6427         /* If it's add and we've config it, return */
6428         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6429         if (f != NULL)
6430                 return I40E_SUCCESS;
6431         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6432                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6433
6434                 /**
6435                  * If vlan_num is 0, that's the first time to add mac,
6436                  * set mask for vlan_id 0.
6437                  */
6438                 if (vsi->vlan_num == 0) {
6439                         i40e_set_vlan_filter(vsi, 0, 1);
6440                         vsi->vlan_num = 1;
6441                 }
6442                 vlan_num = vsi->vlan_num;
6443         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6444                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6445                 vlan_num = 1;
6446
6447         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6448         if (mv_f == NULL) {
6449                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6450                 return I40E_ERR_NO_MEMORY;
6451         }
6452
6453         for (i = 0; i < vlan_num; i++) {
6454                 mv_f[i].filter_type = mac_filter->filter_type;
6455                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6456                                 ETH_ADDR_LEN);
6457         }
6458
6459         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6460                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6461                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6462                                         &mac_filter->mac_addr);
6463                 if (ret != I40E_SUCCESS)
6464                         goto DONE;
6465         }
6466
6467         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6468         if (ret != I40E_SUCCESS)
6469                 goto DONE;
6470
6471         /* Add the mac addr into mac list */
6472         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6473         if (f == NULL) {
6474                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6475                 ret = I40E_ERR_NO_MEMORY;
6476                 goto DONE;
6477         }
6478         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6479                         ETH_ADDR_LEN);
6480         f->mac_info.filter_type = mac_filter->filter_type;
6481         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6482         vsi->mac_num++;
6483
6484         ret = I40E_SUCCESS;
6485 DONE:
6486         rte_free(mv_f);
6487
6488         return ret;
6489 }
6490
6491 int
6492 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6493 {
6494         struct i40e_mac_filter *f;
6495         struct i40e_macvlan_filter *mv_f;
6496         int i, vlan_num;
6497         enum rte_mac_filter_type filter_type;
6498         int ret = I40E_SUCCESS;
6499
6500         /* Can't find it, return an error */
6501         f = i40e_find_mac_filter(vsi, addr);
6502         if (f == NULL)
6503                 return I40E_ERR_PARAM;
6504
6505         vlan_num = vsi->vlan_num;
6506         filter_type = f->mac_info.filter_type;
6507         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6508                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6509                 if (vlan_num == 0) {
6510                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6511                         return I40E_ERR_PARAM;
6512                 }
6513         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6514                         filter_type == RTE_MAC_HASH_MATCH)
6515                 vlan_num = 1;
6516
6517         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6518         if (mv_f == NULL) {
6519                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6520                 return I40E_ERR_NO_MEMORY;
6521         }
6522
6523         for (i = 0; i < vlan_num; i++) {
6524                 mv_f[i].filter_type = filter_type;
6525                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6526                                 ETH_ADDR_LEN);
6527         }
6528         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6529                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6530                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6531                 if (ret != I40E_SUCCESS)
6532                         goto DONE;
6533         }
6534
6535         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6536         if (ret != I40E_SUCCESS)
6537                 goto DONE;
6538
6539         /* Remove the mac addr into mac list */
6540         TAILQ_REMOVE(&vsi->mac_list, f, next);
6541         rte_free(f);
6542         vsi->mac_num--;
6543
6544         ret = I40E_SUCCESS;
6545 DONE:
6546         rte_free(mv_f);
6547         return ret;
6548 }
6549
6550 /* Configure hash enable flags for RSS */
6551 uint64_t
6552 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6553 {
6554         uint64_t hena = 0;
6555
6556         if (!flags)
6557                 return hena;
6558
6559         if (flags & ETH_RSS_FRAG_IPV4)
6560                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6561         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6562                 if (type == I40E_MAC_X722) {
6563                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6564                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6565                 } else
6566                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6567         }
6568         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6569                 if (type == I40E_MAC_X722) {
6570                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6571                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6572                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6573                 } else
6574                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6575         }
6576         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6577                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6578         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6579                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6580         if (flags & ETH_RSS_FRAG_IPV6)
6581                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6582         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6583                 if (type == I40E_MAC_X722) {
6584                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6585                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6586                 } else
6587                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6588         }
6589         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6590                 if (type == I40E_MAC_X722) {
6591                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6592                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6593                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6594                 } else
6595                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6596         }
6597         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6598                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6599         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6600                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6601         if (flags & ETH_RSS_L2_PAYLOAD)
6602                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6603
6604         return hena;
6605 }
6606
6607 /* Parse the hash enable flags */
6608 uint64_t
6609 i40e_parse_hena(uint64_t flags)
6610 {
6611         uint64_t rss_hf = 0;
6612
6613         if (!flags)
6614                 return rss_hf;
6615         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6616                 rss_hf |= ETH_RSS_FRAG_IPV4;
6617         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6618                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6619         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6620                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6621         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6622                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6623         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6624                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6625         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6626                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6627         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6628                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6629         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6630                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6631         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6632                 rss_hf |= ETH_RSS_FRAG_IPV6;
6633         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6634                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6635         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6636                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6637         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6638                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6639         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6640                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6641         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6642                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6643         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6644                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6645         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6646                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6647         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6648                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6649
6650         return rss_hf;
6651 }
6652
6653 /* Disable RSS */
6654 static void
6655 i40e_pf_disable_rss(struct i40e_pf *pf)
6656 {
6657         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6658         uint64_t hena;
6659
6660         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6661         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6662         if (hw->mac.type == I40E_MAC_X722)
6663                 hena &= ~I40E_RSS_HENA_ALL_X722;
6664         else
6665                 hena &= ~I40E_RSS_HENA_ALL;
6666         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6667         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6668         I40E_WRITE_FLUSH(hw);
6669 }
6670
6671 static int
6672 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6673 {
6674         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6675         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6676         int ret = 0;
6677
6678         if (!key || key_len == 0) {
6679                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6680                 return 0;
6681         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6682                 sizeof(uint32_t)) {
6683                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6684                 return -EINVAL;
6685         }
6686
6687         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6688                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6689                         (struct i40e_aqc_get_set_rss_key_data *)key;
6690
6691                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6692                 if (ret)
6693                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6694         } else {
6695                 uint32_t *hash_key = (uint32_t *)key;
6696                 uint16_t i;
6697
6698                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6699                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6700                 I40E_WRITE_FLUSH(hw);
6701         }
6702
6703         return ret;
6704 }
6705
6706 static int
6707 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6708 {
6709         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6710         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6711         int ret;
6712
6713         if (!key || !key_len)
6714                 return -EINVAL;
6715
6716         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6717                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6718                         (struct i40e_aqc_get_set_rss_key_data *)key);
6719                 if (ret) {
6720                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6721                         return ret;
6722                 }
6723         } else {
6724                 uint32_t *key_dw = (uint32_t *)key;
6725                 uint16_t i;
6726
6727                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6728                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6729         }
6730         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6731
6732         return 0;
6733 }
6734
6735 static int
6736 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6737 {
6738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6739         uint64_t rss_hf;
6740         uint64_t hena;
6741         int ret;
6742
6743         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6744                                rss_conf->rss_key_len);
6745         if (ret)
6746                 return ret;
6747
6748         rss_hf = rss_conf->rss_hf;
6749         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6750         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6751         if (hw->mac.type == I40E_MAC_X722)
6752                 hena &= ~I40E_RSS_HENA_ALL_X722;
6753         else
6754                 hena &= ~I40E_RSS_HENA_ALL;
6755         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6756         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6757         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6758         I40E_WRITE_FLUSH(hw);
6759
6760         return 0;
6761 }
6762
6763 static int
6764 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6765                          struct rte_eth_rss_conf *rss_conf)
6766 {
6767         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6770         uint64_t hena;
6771
6772         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6773         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6774         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6775                  ? I40E_RSS_HENA_ALL_X722
6776                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6777                 if (rss_hf != 0) /* Enable RSS */
6778                         return -EINVAL;
6779                 return 0; /* Nothing to do */
6780         }
6781         /* RSS enabled */
6782         if (rss_hf == 0) /* Disable RSS */
6783                 return -EINVAL;
6784
6785         return i40e_hw_rss_hash_set(pf, rss_conf);
6786 }
6787
6788 static int
6789 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6790                            struct rte_eth_rss_conf *rss_conf)
6791 {
6792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6794         uint64_t hena;
6795
6796         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6797                          &rss_conf->rss_key_len);
6798
6799         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6800         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6801         rss_conf->rss_hf = i40e_parse_hena(hena);
6802
6803         return 0;
6804 }
6805
6806 static int
6807 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6808 {
6809         switch (filter_type) {
6810         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6811                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6812                 break;
6813         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6814                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6815                 break;
6816         case RTE_TUNNEL_FILTER_IMAC_TENID:
6817                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6818                 break;
6819         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6820                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6821                 break;
6822         case ETH_TUNNEL_FILTER_IMAC:
6823                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6824                 break;
6825         case ETH_TUNNEL_FILTER_OIP:
6826                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6827                 break;
6828         case ETH_TUNNEL_FILTER_IIP:
6829                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6830                 break;
6831         default:
6832                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6833                 return -EINVAL;
6834         }
6835
6836         return 0;
6837 }
6838
6839 /* Convert tunnel filter structure */
6840 static int
6841 i40e_tunnel_filter_convert(
6842         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6843         struct i40e_tunnel_filter *tunnel_filter)
6844 {
6845         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6846                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6847         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6848                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6849         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6850         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6851              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6852             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6853                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6854         else
6855                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6856         tunnel_filter->input.flags = cld_filter->element.flags;
6857         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6858         tunnel_filter->queue = cld_filter->element.queue_number;
6859         rte_memcpy(tunnel_filter->input.general_fields,
6860                    cld_filter->general_fields,
6861                    sizeof(cld_filter->general_fields));
6862
6863         return 0;
6864 }
6865
6866 /* Check if there exists the tunnel filter */
6867 struct i40e_tunnel_filter *
6868 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6869                              const struct i40e_tunnel_filter_input *input)
6870 {
6871         int ret;
6872
6873         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6874         if (ret < 0)
6875                 return NULL;
6876
6877         return tunnel_rule->hash_map[ret];
6878 }
6879
6880 /* Add a tunnel filter into the SW list */
6881 static int
6882 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6883                              struct i40e_tunnel_filter *tunnel_filter)
6884 {
6885         struct i40e_tunnel_rule *rule = &pf->tunnel;
6886         int ret;
6887
6888         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6889         if (ret < 0) {
6890                 PMD_DRV_LOG(ERR,
6891                             "Failed to insert tunnel filter to hash table %d!",
6892                             ret);
6893                 return ret;
6894         }
6895         rule->hash_map[ret] = tunnel_filter;
6896
6897         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6898
6899         return 0;
6900 }
6901
6902 /* Delete a tunnel filter from the SW list */
6903 int
6904 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6905                           struct i40e_tunnel_filter_input *input)
6906 {
6907         struct i40e_tunnel_rule *rule = &pf->tunnel;
6908         struct i40e_tunnel_filter *tunnel_filter;
6909         int ret;
6910
6911         ret = rte_hash_del_key(rule->hash_table, input);
6912         if (ret < 0) {
6913                 PMD_DRV_LOG(ERR,
6914                             "Failed to delete tunnel filter to hash table %d!",
6915                             ret);
6916                 return ret;
6917         }
6918         tunnel_filter = rule->hash_map[ret];
6919         rule->hash_map[ret] = NULL;
6920
6921         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6922         rte_free(tunnel_filter);
6923
6924         return 0;
6925 }
6926
6927 int
6928 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6929                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6930                         uint8_t add)
6931 {
6932         uint16_t ip_type;
6933         uint32_t ipv4_addr;
6934         uint8_t i, tun_type = 0;
6935         /* internal varialbe to convert ipv6 byte order */
6936         uint32_t convert_ipv6[4];
6937         int val, ret = 0;
6938         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6939         struct i40e_vsi *vsi = pf->main_vsi;
6940         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6941         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6942         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6943         struct i40e_tunnel_filter *tunnel, *node;
6944         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6945
6946         cld_filter = rte_zmalloc("tunnel_filter",
6947                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6948         0);
6949
6950         if (NULL == cld_filter) {
6951                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6952                 return -ENOMEM;
6953         }
6954         pfilter = cld_filter;
6955
6956         ether_addr_copy(&tunnel_filter->outer_mac,
6957                         (struct ether_addr *)&pfilter->element.outer_mac);
6958         ether_addr_copy(&tunnel_filter->inner_mac,
6959                         (struct ether_addr *)&pfilter->element.inner_mac);
6960
6961         pfilter->element.inner_vlan =
6962                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6963         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6964                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6965                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6966                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6967                                 &rte_cpu_to_le_32(ipv4_addr),
6968                                 sizeof(pfilter->element.ipaddr.v4.data));
6969         } else {
6970                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6971                 for (i = 0; i < 4; i++) {
6972                         convert_ipv6[i] =
6973                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6974                 }
6975                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6976                            &convert_ipv6,
6977                            sizeof(pfilter->element.ipaddr.v6.data));
6978         }
6979
6980         /* check tunneled type */
6981         switch (tunnel_filter->tunnel_type) {
6982         case RTE_TUNNEL_TYPE_VXLAN:
6983                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6984                 break;
6985         case RTE_TUNNEL_TYPE_NVGRE:
6986                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6987                 break;
6988         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6989                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6990                 break;
6991         default:
6992                 /* Other tunnel types is not supported. */
6993                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6994                 rte_free(cld_filter);
6995                 return -EINVAL;
6996         }
6997
6998         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6999                                        &pfilter->element.flags);
7000         if (val < 0) {
7001                 rte_free(cld_filter);
7002                 return -EINVAL;
7003         }
7004
7005         pfilter->element.flags |= rte_cpu_to_le_16(
7006                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7007                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7008         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7009         pfilter->element.queue_number =
7010                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7011
7012         /* Check if there is the filter in SW list */
7013         memset(&check_filter, 0, sizeof(check_filter));
7014         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7015         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7016         if (add && node) {
7017                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7018                 return -EINVAL;
7019         }
7020
7021         if (!add && !node) {
7022                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7023                 return -EINVAL;
7024         }
7025
7026         if (add) {
7027                 ret = i40e_aq_add_cloud_filters(hw,
7028                                         vsi->seid, &cld_filter->element, 1);
7029                 if (ret < 0) {
7030                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7031                         return -ENOTSUP;
7032                 }
7033                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7034                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7035                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7036         } else {
7037                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7038                                                    &cld_filter->element, 1);
7039                 if (ret < 0) {
7040                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7041                         return -ENOTSUP;
7042                 }
7043                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7044         }
7045
7046         rte_free(cld_filter);
7047         return ret;
7048 }
7049
7050 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7051 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7052 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7053 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7054 #define I40E_TR_GRE_KEY_MASK                    0x400
7055 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7056 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7057
7058 static enum
7059 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7060 {
7061         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7062         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7063         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7064         enum i40e_status_code status = I40E_SUCCESS;
7065
7066         memset(&filter_replace, 0,
7067                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7068         memset(&filter_replace_buf, 0,
7069                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7070
7071         /* create L1 filter */
7072         filter_replace.old_filter_type =
7073                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7074         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7075         filter_replace.tr_bit = 0;
7076
7077         /* Prepare the buffer, 3 entries */
7078         filter_replace_buf.data[0] =
7079                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7080         filter_replace_buf.data[0] |=
7081                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7082         filter_replace_buf.data[2] = 0xFF;
7083         filter_replace_buf.data[3] = 0xFF;
7084         filter_replace_buf.data[4] =
7085                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7086         filter_replace_buf.data[4] |=
7087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7088         filter_replace_buf.data[7] = 0xF0;
7089         filter_replace_buf.data[8]
7090                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7091         filter_replace_buf.data[8] |=
7092                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7093         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7094                 I40E_TR_GENEVE_KEY_MASK |
7095                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7096         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7097                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7098                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7099
7100         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7101                                                &filter_replace_buf);
7102         return status;
7103 }
7104
7105 static enum
7106 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7107 {
7108         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7109         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7110         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7111         enum i40e_status_code status = I40E_SUCCESS;
7112
7113         /* For MPLSoUDP */
7114         memset(&filter_replace, 0,
7115                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7116         memset(&filter_replace_buf, 0,
7117                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7118         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7119                 I40E_AQC_MIRROR_CLOUD_FILTER;
7120         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7121         filter_replace.new_filter_type =
7122                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7123         /* Prepare the buffer, 2 entries */
7124         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7125         filter_replace_buf.data[0] |=
7126                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7127         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7128         filter_replace_buf.data[4] |=
7129                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7130         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7131                                                &filter_replace_buf);
7132         if (status < 0)
7133                 return status;
7134
7135         /* For MPLSoGRE */
7136         memset(&filter_replace, 0,
7137                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7138         memset(&filter_replace_buf, 0,
7139                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7140
7141         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7142                 I40E_AQC_MIRROR_CLOUD_FILTER;
7143         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7144         filter_replace.new_filter_type =
7145                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7146         /* Prepare the buffer, 2 entries */
7147         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7148         filter_replace_buf.data[0] |=
7149                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7150         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7151         filter_replace_buf.data[4] |=
7152                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7153
7154         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7155                                                &filter_replace_buf);
7156         return status;
7157 }
7158
7159 int
7160 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7161                       struct i40e_tunnel_filter_conf *tunnel_filter,
7162                       uint8_t add)
7163 {
7164         uint16_t ip_type;
7165         uint32_t ipv4_addr;
7166         uint8_t i, tun_type = 0;
7167         /* internal variable to convert ipv6 byte order */
7168         uint32_t convert_ipv6[4];
7169         int val, ret = 0;
7170         struct i40e_pf_vf *vf = NULL;
7171         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7172         struct i40e_vsi *vsi;
7173         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7174         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7175         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7176         struct i40e_tunnel_filter *tunnel, *node;
7177         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7178         uint32_t teid_le;
7179         bool big_buffer = 0;
7180
7181         cld_filter = rte_zmalloc("tunnel_filter",
7182                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7183                          0);
7184
7185         if (cld_filter == NULL) {
7186                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7187                 return -ENOMEM;
7188         }
7189         pfilter = cld_filter;
7190
7191         ether_addr_copy(&tunnel_filter->outer_mac,
7192                         (struct ether_addr *)&pfilter->element.outer_mac);
7193         ether_addr_copy(&tunnel_filter->inner_mac,
7194                         (struct ether_addr *)&pfilter->element.inner_mac);
7195
7196         pfilter->element.inner_vlan =
7197                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7198         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7199                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7200                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7201                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7202                                 &rte_cpu_to_le_32(ipv4_addr),
7203                                 sizeof(pfilter->element.ipaddr.v4.data));
7204         } else {
7205                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7206                 for (i = 0; i < 4; i++) {
7207                         convert_ipv6[i] =
7208                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7209                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7210                 }
7211                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7212                            &convert_ipv6,
7213                            sizeof(pfilter->element.ipaddr.v6.data));
7214         }
7215
7216         /* check tunneled type */
7217         switch (tunnel_filter->tunnel_type) {
7218         case I40E_TUNNEL_TYPE_VXLAN:
7219                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7220                 break;
7221         case I40E_TUNNEL_TYPE_NVGRE:
7222                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7223                 break;
7224         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7225                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7226                 break;
7227         case I40E_TUNNEL_TYPE_MPLSoUDP:
7228                 if (!pf->mpls_replace_flag) {
7229                         i40e_replace_mpls_l1_filter(pf);
7230                         i40e_replace_mpls_cloud_filter(pf);
7231                         pf->mpls_replace_flag = 1;
7232                 }
7233                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7234                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7235                         teid_le >> 4;
7236                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7237                         (teid_le & 0xF) << 12;
7238                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7239                         0x40;
7240                 big_buffer = 1;
7241                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7242                 break;
7243         case I40E_TUNNEL_TYPE_MPLSoGRE:
7244                 if (!pf->mpls_replace_flag) {
7245                         i40e_replace_mpls_l1_filter(pf);
7246                         i40e_replace_mpls_cloud_filter(pf);
7247                         pf->mpls_replace_flag = 1;
7248                 }
7249                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7250                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7251                         teid_le >> 4;
7252                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7253                         (teid_le & 0xF) << 12;
7254                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7255                         0x0;
7256                 big_buffer = 1;
7257                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7258                 break;
7259         case I40E_TUNNEL_TYPE_QINQ:
7260                 if (!pf->qinq_replace_flag) {
7261                         ret = i40e_cloud_filter_qinq_create(pf);
7262                         if (ret < 0)
7263                                 PMD_DRV_LOG(DEBUG,
7264                                             "QinQ tunnel filter already created.");
7265                         pf->qinq_replace_flag = 1;
7266                 }
7267                 /*      Add in the General fields the values of
7268                  *      the Outer and Inner VLAN
7269                  *      Big Buffer should be set, see changes in
7270                  *      i40e_aq_add_cloud_filters
7271                  */
7272                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7273                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7274                 big_buffer = 1;
7275                 break;
7276         default:
7277                 /* Other tunnel types is not supported. */
7278                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7279                 rte_free(cld_filter);
7280                 return -EINVAL;
7281         }
7282
7283         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7284                 pfilter->element.flags =
7285                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7286         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7287                 pfilter->element.flags =
7288                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7289         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7290                 pfilter->element.flags |=
7291                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7292         else {
7293                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7294                                                 &pfilter->element.flags);
7295                 if (val < 0) {
7296                         rte_free(cld_filter);
7297                         return -EINVAL;
7298                 }
7299         }
7300
7301         pfilter->element.flags |= rte_cpu_to_le_16(
7302                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7303                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7304         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7305         pfilter->element.queue_number =
7306                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7307
7308         if (!tunnel_filter->is_to_vf)
7309                 vsi = pf->main_vsi;
7310         else {
7311                 if (tunnel_filter->vf_id >= pf->vf_num) {
7312                         PMD_DRV_LOG(ERR, "Invalid argument.");
7313                         return -EINVAL;
7314                 }
7315                 vf = &pf->vfs[tunnel_filter->vf_id];
7316                 vsi = vf->vsi;
7317         }
7318
7319         /* Check if there is the filter in SW list */
7320         memset(&check_filter, 0, sizeof(check_filter));
7321         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7322         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7323         check_filter.vf_id = tunnel_filter->vf_id;
7324         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7325         if (add && node) {
7326                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7327                 return -EINVAL;
7328         }
7329
7330         if (!add && !node) {
7331                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7332                 return -EINVAL;
7333         }
7334
7335         if (add) {
7336                 if (big_buffer)
7337                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7338                                                    vsi->seid, cld_filter, 1);
7339                 else
7340                         ret = i40e_aq_add_cloud_filters(hw,
7341                                         vsi->seid, &cld_filter->element, 1);
7342                 if (ret < 0) {
7343                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7344                         return -ENOTSUP;
7345                 }
7346                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7347                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7348                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7349         } else {
7350                 if (big_buffer)
7351                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7352                                 hw, vsi->seid, cld_filter, 1);
7353                 else
7354                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7355                                                    &cld_filter->element, 1);
7356                 if (ret < 0) {
7357                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7358                         return -ENOTSUP;
7359                 }
7360                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7361         }
7362
7363         rte_free(cld_filter);
7364         return ret;
7365 }
7366
7367 static int
7368 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7369 {
7370         uint8_t i;
7371
7372         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7373                 if (pf->vxlan_ports[i] == port)
7374                         return i;
7375         }
7376
7377         return -1;
7378 }
7379
7380 static int
7381 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7382 {
7383         int  idx, ret;
7384         uint8_t filter_idx;
7385         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7386
7387         idx = i40e_get_vxlan_port_idx(pf, port);
7388
7389         /* Check if port already exists */
7390         if (idx >= 0) {
7391                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7392                 return -EINVAL;
7393         }
7394
7395         /* Now check if there is space to add the new port */
7396         idx = i40e_get_vxlan_port_idx(pf, 0);
7397         if (idx < 0) {
7398                 PMD_DRV_LOG(ERR,
7399                         "Maximum number of UDP ports reached, not adding port %d",
7400                         port);
7401                 return -ENOSPC;
7402         }
7403
7404         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7405                                         &filter_idx, NULL);
7406         if (ret < 0) {
7407                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7408                 return -1;
7409         }
7410
7411         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7412                          port,  filter_idx);
7413
7414         /* New port: add it and mark its index in the bitmap */
7415         pf->vxlan_ports[idx] = port;
7416         pf->vxlan_bitmap |= (1 << idx);
7417
7418         if (!(pf->flags & I40E_FLAG_VXLAN))
7419                 pf->flags |= I40E_FLAG_VXLAN;
7420
7421         return 0;
7422 }
7423
7424 static int
7425 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7426 {
7427         int idx;
7428         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7429
7430         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7431                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7432                 return -EINVAL;
7433         }
7434
7435         idx = i40e_get_vxlan_port_idx(pf, port);
7436
7437         if (idx < 0) {
7438                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7439                 return -EINVAL;
7440         }
7441
7442         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7443                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7444                 return -1;
7445         }
7446
7447         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7448                         port, idx);
7449
7450         pf->vxlan_ports[idx] = 0;
7451         pf->vxlan_bitmap &= ~(1 << idx);
7452
7453         if (!pf->vxlan_bitmap)
7454                 pf->flags &= ~I40E_FLAG_VXLAN;
7455
7456         return 0;
7457 }
7458
7459 /* Add UDP tunneling port */
7460 static int
7461 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7462                              struct rte_eth_udp_tunnel *udp_tunnel)
7463 {
7464         int ret = 0;
7465         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7466
7467         if (udp_tunnel == NULL)
7468                 return -EINVAL;
7469
7470         switch (udp_tunnel->prot_type) {
7471         case RTE_TUNNEL_TYPE_VXLAN:
7472                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7473                 break;
7474
7475         case RTE_TUNNEL_TYPE_GENEVE:
7476         case RTE_TUNNEL_TYPE_TEREDO:
7477                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7478                 ret = -1;
7479                 break;
7480
7481         default:
7482                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7483                 ret = -1;
7484                 break;
7485         }
7486
7487         return ret;
7488 }
7489
7490 /* Remove UDP tunneling port */
7491 static int
7492 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7493                              struct rte_eth_udp_tunnel *udp_tunnel)
7494 {
7495         int ret = 0;
7496         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7497
7498         if (udp_tunnel == NULL)
7499                 return -EINVAL;
7500
7501         switch (udp_tunnel->prot_type) {
7502         case RTE_TUNNEL_TYPE_VXLAN:
7503                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7504                 break;
7505         case RTE_TUNNEL_TYPE_GENEVE:
7506         case RTE_TUNNEL_TYPE_TEREDO:
7507                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7508                 ret = -1;
7509                 break;
7510         default:
7511                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7512                 ret = -1;
7513                 break;
7514         }
7515
7516         return ret;
7517 }
7518
7519 /* Calculate the maximum number of contiguous PF queues that are configured */
7520 static int
7521 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7522 {
7523         struct rte_eth_dev_data *data = pf->dev_data;
7524         int i, num;
7525         struct i40e_rx_queue *rxq;
7526
7527         num = 0;
7528         for (i = 0; i < pf->lan_nb_qps; i++) {
7529                 rxq = data->rx_queues[i];
7530                 if (rxq && rxq->q_set)
7531                         num++;
7532                 else
7533                         break;
7534         }
7535
7536         return num;
7537 }
7538
7539 /* Configure RSS */
7540 static int
7541 i40e_pf_config_rss(struct i40e_pf *pf)
7542 {
7543         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7544         struct rte_eth_rss_conf rss_conf;
7545         uint32_t i, lut = 0;
7546         uint16_t j, num;
7547
7548         /*
7549          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7550          * It's necessary to calculate the actual PF queues that are configured.
7551          */
7552         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7553                 num = i40e_pf_calc_configured_queues_num(pf);
7554         else
7555                 num = pf->dev_data->nb_rx_queues;
7556
7557         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7558         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7559                         num);
7560
7561         if (num == 0) {
7562                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7563                 return -ENOTSUP;
7564         }
7565
7566         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7567                 if (j == num)
7568                         j = 0;
7569                 lut = (lut << 8) | (j & ((0x1 <<
7570                         hw->func_caps.rss_table_entry_width) - 1));
7571                 if ((i & 3) == 3)
7572                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7573         }
7574
7575         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7576         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7577                 i40e_pf_disable_rss(pf);
7578                 return 0;
7579         }
7580         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7581                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7582                 /* Random default keys */
7583                 static uint32_t rss_key_default[] = {0x6b793944,
7584                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7585                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7586                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7587
7588                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7589                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7590                                                         sizeof(uint32_t);
7591         }
7592
7593         return i40e_hw_rss_hash_set(pf, &rss_conf);
7594 }
7595
7596 static int
7597 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7598                                struct rte_eth_tunnel_filter_conf *filter)
7599 {
7600         if (pf == NULL || filter == NULL) {
7601                 PMD_DRV_LOG(ERR, "Invalid parameter");
7602                 return -EINVAL;
7603         }
7604
7605         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7606                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7607                 return -EINVAL;
7608         }
7609
7610         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7611                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7612                 return -EINVAL;
7613         }
7614
7615         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7616                 (is_zero_ether_addr(&filter->outer_mac))) {
7617                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7618                 return -EINVAL;
7619         }
7620
7621         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7622                 (is_zero_ether_addr(&filter->inner_mac))) {
7623                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7624                 return -EINVAL;
7625         }
7626
7627         return 0;
7628 }
7629
7630 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7631 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7632 static int
7633 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7634 {
7635         uint32_t val, reg;
7636         int ret = -EINVAL;
7637
7638         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7639         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7640
7641         if (len == 3) {
7642                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7643         } else if (len == 4) {
7644                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7645         } else {
7646                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7647                 return ret;
7648         }
7649
7650         if (reg != val) {
7651                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7652                                                    reg, NULL);
7653                 if (ret != 0)
7654                         return ret;
7655         } else {
7656                 ret = 0;
7657         }
7658         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7659                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7660
7661         return ret;
7662 }
7663
7664 static int
7665 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7666 {
7667         int ret = -EINVAL;
7668
7669         if (!hw || !cfg)
7670                 return -EINVAL;
7671
7672         switch (cfg->cfg_type) {
7673         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7674                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7675                 break;
7676         default:
7677                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7678                 break;
7679         }
7680
7681         return ret;
7682 }
7683
7684 static int
7685 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7686                                enum rte_filter_op filter_op,
7687                                void *arg)
7688 {
7689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7690         int ret = I40E_ERR_PARAM;
7691
7692         switch (filter_op) {
7693         case RTE_ETH_FILTER_SET:
7694                 ret = i40e_dev_global_config_set(hw,
7695                         (struct rte_eth_global_cfg *)arg);
7696                 break;
7697         default:
7698                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7699                 break;
7700         }
7701
7702         return ret;
7703 }
7704
7705 static int
7706 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7707                           enum rte_filter_op filter_op,
7708                           void *arg)
7709 {
7710         struct rte_eth_tunnel_filter_conf *filter;
7711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7712         int ret = I40E_SUCCESS;
7713
7714         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7715
7716         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7717                 return I40E_ERR_PARAM;
7718
7719         switch (filter_op) {
7720         case RTE_ETH_FILTER_NOP:
7721                 if (!(pf->flags & I40E_FLAG_VXLAN))
7722                         ret = I40E_NOT_SUPPORTED;
7723                 break;
7724         case RTE_ETH_FILTER_ADD:
7725                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7726                 break;
7727         case RTE_ETH_FILTER_DELETE:
7728                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7729                 break;
7730         default:
7731                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7732                 ret = I40E_ERR_PARAM;
7733                 break;
7734         }
7735
7736         return ret;
7737 }
7738
7739 static int
7740 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7741 {
7742         int ret = 0;
7743         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7744
7745         /* RSS setup */
7746         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7747                 ret = i40e_pf_config_rss(pf);
7748         else
7749                 i40e_pf_disable_rss(pf);
7750
7751         return ret;
7752 }
7753
7754 /* Get the symmetric hash enable configurations per port */
7755 static void
7756 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7757 {
7758         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7759
7760         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7761 }
7762
7763 /* Set the symmetric hash enable configurations per port */
7764 static void
7765 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7766 {
7767         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7768
7769         if (enable > 0) {
7770                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7771                         PMD_DRV_LOG(INFO,
7772                                 "Symmetric hash has already been enabled");
7773                         return;
7774                 }
7775                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7776         } else {
7777                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7778                         PMD_DRV_LOG(INFO,
7779                                 "Symmetric hash has already been disabled");
7780                         return;
7781                 }
7782                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7783         }
7784         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7785         I40E_WRITE_FLUSH(hw);
7786 }
7787
7788 /*
7789  * Get global configurations of hash function type and symmetric hash enable
7790  * per flow type (pctype). Note that global configuration means it affects all
7791  * the ports on the same NIC.
7792  */
7793 static int
7794 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7795                                    struct rte_eth_hash_global_conf *g_cfg)
7796 {
7797         uint32_t reg, mask = I40E_FLOW_TYPES;
7798         uint16_t i;
7799         enum i40e_filter_pctype pctype;
7800
7801         memset(g_cfg, 0, sizeof(*g_cfg));
7802         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7803         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7804                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7805         else
7806                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7807         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7808                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7809
7810         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7811                 if (!(mask & (1UL << i)))
7812                         continue;
7813                 mask &= ~(1UL << i);
7814                 /* Bit set indicats the coresponding flow type is supported */
7815                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7816                 /* if flowtype is invalid, continue */
7817                 if (!I40E_VALID_FLOW(i))
7818                         continue;
7819                 pctype = i40e_flowtype_to_pctype(i);
7820                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7821                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7822                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7823         }
7824
7825         return 0;
7826 }
7827
7828 static int
7829 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7830 {
7831         uint32_t i;
7832         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7833
7834         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7835                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7836                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7837                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7838                                                 g_cfg->hash_func);
7839                 return -EINVAL;
7840         }
7841
7842         /*
7843          * As i40e supports less than 32 flow types, only first 32 bits need to
7844          * be checked.
7845          */
7846         mask0 = g_cfg->valid_bit_mask[0];
7847         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7848                 if (i == 0) {
7849                         /* Check if any unsupported flow type configured */
7850                         if ((mask0 | i40e_mask) ^ i40e_mask)
7851                                 goto mask_err;
7852                 } else {
7853                         if (g_cfg->valid_bit_mask[i])
7854                                 goto mask_err;
7855                 }
7856         }
7857
7858         return 0;
7859
7860 mask_err:
7861         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7862
7863         return -EINVAL;
7864 }
7865
7866 /*
7867  * Set global configurations of hash function type and symmetric hash enable
7868  * per flow type (pctype). Note any modifying global configuration will affect
7869  * all the ports on the same NIC.
7870  */
7871 static int
7872 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7873                                    struct rte_eth_hash_global_conf *g_cfg)
7874 {
7875         int ret;
7876         uint16_t i;
7877         uint32_t reg;
7878         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7879         enum i40e_filter_pctype pctype;
7880
7881         /* Check the input parameters */
7882         ret = i40e_hash_global_config_check(g_cfg);
7883         if (ret < 0)
7884                 return ret;
7885
7886         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7887                 if (!(mask0 & (1UL << i)))
7888                         continue;
7889                 mask0 &= ~(1UL << i);
7890                 /* if flowtype is invalid, continue */
7891                 if (!I40E_VALID_FLOW(i))
7892                         continue;
7893                 pctype = i40e_flowtype_to_pctype(i);
7894                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7895                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7896                 if (hw->mac.type == I40E_MAC_X722) {
7897                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7898                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7899                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7900                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7901                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7902                                   reg);
7903                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7904                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7905                                   reg);
7906                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7907                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7908                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7909                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7910                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7911                                   reg);
7912                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7913                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7914                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7915                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7916                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7917                                   reg);
7918                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7919                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7920                                   reg);
7921                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7922                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7923                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7924                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7925                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7926                                   reg);
7927                         } else {
7928                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7929                                   reg);
7930                         }
7931                 } else {
7932                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7933                 }
7934         }
7935
7936         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7937         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7938                 /* Toeplitz */
7939                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7940                         PMD_DRV_LOG(DEBUG,
7941                                 "Hash function already set to Toeplitz");
7942                         goto out;
7943                 }
7944                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7945         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7946                 /* Simple XOR */
7947                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7948                         PMD_DRV_LOG(DEBUG,
7949                                 "Hash function already set to Simple XOR");
7950                         goto out;
7951                 }
7952                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7953         } else
7954                 /* Use the default, and keep it as it is */
7955                 goto out;
7956
7957         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7958
7959 out:
7960         I40E_WRITE_FLUSH(hw);
7961
7962         return 0;
7963 }
7964
7965 /**
7966  * Valid input sets for hash and flow director filters per PCTYPE
7967  */
7968 static uint64_t
7969 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7970                 enum rte_filter_type filter)
7971 {
7972         uint64_t valid;
7973
7974         static const uint64_t valid_hash_inset_table[] = {
7975                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7976                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7977                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7978                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7979                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7980                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7981                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7982                         I40E_INSET_FLEX_PAYLOAD,
7983                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7984                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7985                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7986                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7987                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7988                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7989                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7990                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7991                         I40E_INSET_FLEX_PAYLOAD,
7992                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7993                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7994                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7995                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7996                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7997                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7998                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7999                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8000                         I40E_INSET_FLEX_PAYLOAD,
8001                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8002                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8003                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8004                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8005                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8006                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8007                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8008                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8009                         I40E_INSET_FLEX_PAYLOAD,
8010                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8011                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8012                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8013                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8014                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8015                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8016                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8017                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8018                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8019                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8020                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8021                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8022                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8023                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8024                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8025                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8026                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8027                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8028                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8029                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8030                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8031                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8032                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8033                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8034                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8035                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8036                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8037                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8038                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8039                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8040                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8041                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8042                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8043                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8044                         I40E_INSET_FLEX_PAYLOAD,
8045                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8046                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8047                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8048                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8049                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8050                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8051                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8052                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8053                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8054                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8055                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8056                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8057                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8058                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8059                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8060                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8061                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8062                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8063                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8064                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8065                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8066                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8067                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8068                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8069                         I40E_INSET_FLEX_PAYLOAD,
8070                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8071                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8072                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8073                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8074                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8075                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8076                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8077                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8078                         I40E_INSET_FLEX_PAYLOAD,
8079                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8080                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8081                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8082                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8083                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8084                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8085                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8086                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8087                         I40E_INSET_FLEX_PAYLOAD,
8088                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8089                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8090                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8091                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8092                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8093                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8094                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8095                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8096                         I40E_INSET_FLEX_PAYLOAD,
8097                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8098                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8099                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8100                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8101                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8102                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8103                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8104                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8105                         I40E_INSET_FLEX_PAYLOAD,
8106                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8107                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8108                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8109                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8110                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8111                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8112                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8113                         I40E_INSET_FLEX_PAYLOAD,
8114                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8118                         I40E_INSET_FLEX_PAYLOAD,
8119         };
8120
8121         /**
8122          * Flow director supports only fields defined in
8123          * union rte_eth_fdir_flow.
8124          */
8125         static const uint64_t valid_fdir_inset_table[] = {
8126                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8127                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8128                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8129                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8130                 I40E_INSET_IPV4_TTL,
8131                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8132                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8133                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8134                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8135                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8136                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8137                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8138                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8139                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8140                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8141                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8142                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8143                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8144                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8145                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8146                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8147                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8148                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8149                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8150                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8151                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8152                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8153                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8154                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8155                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8156                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8157                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8158                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8159                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8160                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8161                 I40E_INSET_SCTP_VT,
8162                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8163                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8164                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8165                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8166                 I40E_INSET_IPV4_TTL,
8167                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8168                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8169                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8170                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8171                 I40E_INSET_IPV6_HOP_LIMIT,
8172                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8173                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8174                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8175                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8176                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8177                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8178                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8179                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8180                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8181                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8182                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8183                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8184                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8185                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8186                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8187                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8188                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8189                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8190                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8191                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8192                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8193                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8194                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8195                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8196                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8197                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8198                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8200                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8201                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8202                 I40E_INSET_SCTP_VT,
8203                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8204                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8205                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8206                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8207                 I40E_INSET_IPV6_HOP_LIMIT,
8208                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8209                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8210                 I40E_INSET_LAST_ETHER_TYPE,
8211         };
8212
8213         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8214                 return 0;
8215         if (filter == RTE_ETH_FILTER_HASH)
8216                 valid = valid_hash_inset_table[pctype];
8217         else
8218                 valid = valid_fdir_inset_table[pctype];
8219
8220         return valid;
8221 }
8222
8223 /**
8224  * Validate if the input set is allowed for a specific PCTYPE
8225  */
8226 int
8227 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8228                 enum rte_filter_type filter, uint64_t inset)
8229 {
8230         uint64_t valid;
8231
8232         valid = i40e_get_valid_input_set(pctype, filter);
8233         if (inset & (~valid))
8234                 return -EINVAL;
8235
8236         return 0;
8237 }
8238
8239 /* default input set fields combination per pctype */
8240 uint64_t
8241 i40e_get_default_input_set(uint16_t pctype)
8242 {
8243         static const uint64_t default_inset_table[] = {
8244                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8245                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8246                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8247                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8248                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8249                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8250                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8251                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8252                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8253                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8254                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8255                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8256                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8257                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8258                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8259                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8260                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8261                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8262                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8263                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8264                         I40E_INSET_SCTP_VT,
8265                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8266                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8267                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8268                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8269                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8270                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8271                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8272                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8273                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8274                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8275                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8276                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8277                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8278                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8279                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8280                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8281                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8282                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8283                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8284                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8285                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8286                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8287                         I40E_INSET_SCTP_VT,
8288                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8289                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8290                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8291                         I40E_INSET_LAST_ETHER_TYPE,
8292         };
8293
8294         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8295                 return 0;
8296
8297         return default_inset_table[pctype];
8298 }
8299
8300 /**
8301  * Parse the input set from index to logical bit masks
8302  */
8303 static int
8304 i40e_parse_input_set(uint64_t *inset,
8305                      enum i40e_filter_pctype pctype,
8306                      enum rte_eth_input_set_field *field,
8307                      uint16_t size)
8308 {
8309         uint16_t i, j;
8310         int ret = -EINVAL;
8311
8312         static const struct {
8313                 enum rte_eth_input_set_field field;
8314                 uint64_t inset;
8315         } inset_convert_table[] = {
8316                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8317                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8318                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8319                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8320                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8321                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8322                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8323                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8324                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8325                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8326                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8327                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8328                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8329                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8330                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8331                         I40E_INSET_IPV6_NEXT_HDR},
8332                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8333                         I40E_INSET_IPV6_HOP_LIMIT},
8334                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8335                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8336                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8337                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8338                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8339                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8340                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8341                         I40E_INSET_SCTP_VT},
8342                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8343                         I40E_INSET_TUNNEL_DMAC},
8344                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8345                         I40E_INSET_VLAN_TUNNEL},
8346                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8347                         I40E_INSET_TUNNEL_ID},
8348                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8349                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8350                         I40E_INSET_FLEX_PAYLOAD_W1},
8351                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8352                         I40E_INSET_FLEX_PAYLOAD_W2},
8353                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8354                         I40E_INSET_FLEX_PAYLOAD_W3},
8355                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8356                         I40E_INSET_FLEX_PAYLOAD_W4},
8357                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8358                         I40E_INSET_FLEX_PAYLOAD_W5},
8359                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8360                         I40E_INSET_FLEX_PAYLOAD_W6},
8361                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8362                         I40E_INSET_FLEX_PAYLOAD_W7},
8363                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8364                         I40E_INSET_FLEX_PAYLOAD_W8},
8365         };
8366
8367         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8368                 return ret;
8369
8370         /* Only one item allowed for default or all */
8371         if (size == 1) {
8372                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8373                         *inset = i40e_get_default_input_set(pctype);
8374                         return 0;
8375                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8376                         *inset = I40E_INSET_NONE;
8377                         return 0;
8378                 }
8379         }
8380
8381         for (i = 0, *inset = 0; i < size; i++) {
8382                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8383                         if (field[i] == inset_convert_table[j].field) {
8384                                 *inset |= inset_convert_table[j].inset;
8385                                 break;
8386                         }
8387                 }
8388
8389                 /* It contains unsupported input set, return immediately */
8390                 if (j == RTE_DIM(inset_convert_table))
8391                         return ret;
8392         }
8393
8394         return 0;
8395 }
8396
8397 /**
8398  * Translate the input set from bit masks to register aware bit masks
8399  * and vice versa
8400  */
8401 uint64_t
8402 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8403 {
8404         uint64_t val = 0;
8405         uint16_t i;
8406
8407         struct inset_map {
8408                 uint64_t inset;
8409                 uint64_t inset_reg;
8410         };
8411
8412         static const struct inset_map inset_map_common[] = {
8413                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8414                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8415                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8416                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8417                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8418                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8419                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8420                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8421                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8422                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8423                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8424                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8425                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8426                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8427                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8428                 {I40E_INSET_TUNNEL_DMAC,
8429                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8430                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8431                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8432                 {I40E_INSET_TUNNEL_SRC_PORT,
8433                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8434                 {I40E_INSET_TUNNEL_DST_PORT,
8435                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8436                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8437                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8438                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8439                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8440                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8441                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8442                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8443                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8444                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8445         };
8446
8447     /* some different registers map in x722*/
8448         static const struct inset_map inset_map_diff_x722[] = {
8449                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8450                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8451                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8452                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8453         };
8454
8455         static const struct inset_map inset_map_diff_not_x722[] = {
8456                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8457                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8458                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8459                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8460         };
8461
8462         if (input == 0)
8463                 return val;
8464
8465         /* Translate input set to register aware inset */
8466         if (type == I40E_MAC_X722) {
8467                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8468                         if (input & inset_map_diff_x722[i].inset)
8469                                 val |= inset_map_diff_x722[i].inset_reg;
8470                 }
8471         } else {
8472                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8473                         if (input & inset_map_diff_not_x722[i].inset)
8474                                 val |= inset_map_diff_not_x722[i].inset_reg;
8475                 }
8476         }
8477
8478         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8479                 if (input & inset_map_common[i].inset)
8480                         val |= inset_map_common[i].inset_reg;
8481         }
8482
8483         return val;
8484 }
8485
8486 int
8487 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8488 {
8489         uint8_t i, idx = 0;
8490         uint64_t inset_need_mask = inset;
8491
8492         static const struct {
8493                 uint64_t inset;
8494                 uint32_t mask;
8495         } inset_mask_map[] = {
8496                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8497                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8498                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8499                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8500                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8501                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8502                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8503                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8504         };
8505
8506         if (!inset || !mask || !nb_elem)
8507                 return 0;
8508
8509         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8510                 /* Clear the inset bit, if no MASK is required,
8511                  * for example proto + ttl
8512                  */
8513                 if ((inset & inset_mask_map[i].inset) ==
8514                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8515                         inset_need_mask &= ~inset_mask_map[i].inset;
8516                 if (!inset_need_mask)
8517                         return 0;
8518         }
8519         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8520                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8521                     inset_mask_map[i].inset) {
8522                         if (idx >= nb_elem) {
8523                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8524                                 return -EINVAL;
8525                         }
8526                         mask[idx] = inset_mask_map[i].mask;
8527                         idx++;
8528                 }
8529         }
8530
8531         return idx;
8532 }
8533
8534 void
8535 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8536 {
8537         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8538
8539         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8540         if (reg != val)
8541                 i40e_write_rx_ctl(hw, addr, val);
8542         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8543                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8544 }
8545
8546 static void
8547 i40e_filter_input_set_init(struct i40e_pf *pf)
8548 {
8549         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8550         enum i40e_filter_pctype pctype;
8551         uint64_t input_set, inset_reg;
8552         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8553         int num, i;
8554
8555         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8556              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8557                 if (hw->mac.type == I40E_MAC_X722) {
8558                         if (!I40E_VALID_PCTYPE_X722(pctype))
8559                                 continue;
8560                 } else {
8561                         if (!I40E_VALID_PCTYPE(pctype))
8562                                 continue;
8563                 }
8564
8565                 input_set = i40e_get_default_input_set(pctype);
8566
8567                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8568                                                    I40E_INSET_MASK_NUM_REG);
8569                 if (num < 0)
8570                         return;
8571                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8572                                         input_set);
8573
8574                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8575                                       (uint32_t)(inset_reg & UINT32_MAX));
8576                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8577                                      (uint32_t)((inset_reg >>
8578                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8579                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8580                                       (uint32_t)(inset_reg & UINT32_MAX));
8581                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8582                                      (uint32_t)((inset_reg >>
8583                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8584
8585                 for (i = 0; i < num; i++) {
8586                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8587                                              mask_reg[i]);
8588                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8589                                              mask_reg[i]);
8590                 }
8591                 /*clear unused mask registers of the pctype */
8592                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8593                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8594                                              0);
8595                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8596                                              0);
8597                 }
8598                 I40E_WRITE_FLUSH(hw);
8599
8600                 /* store the default input set */
8601                 pf->hash_input_set[pctype] = input_set;
8602                 pf->fdir.input_set[pctype] = input_set;
8603         }
8604 }
8605
8606 int
8607 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8608                          struct rte_eth_input_set_conf *conf)
8609 {
8610         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8611         enum i40e_filter_pctype pctype;
8612         uint64_t input_set, inset_reg = 0;
8613         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8614         int ret, i, num;
8615
8616         if (!conf) {
8617                 PMD_DRV_LOG(ERR, "Invalid pointer");
8618                 return -EFAULT;
8619         }
8620         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8621             conf->op != RTE_ETH_INPUT_SET_ADD) {
8622                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8623                 return -EINVAL;
8624         }
8625
8626         if (!I40E_VALID_FLOW(conf->flow_type)) {
8627                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8628                 return -EINVAL;
8629         }
8630
8631         if (hw->mac.type == I40E_MAC_X722) {
8632                 /* get translated pctype value in fd pctype register */
8633                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8634                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8635                         conf->flow_type)));
8636         } else
8637                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8638
8639         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8640                                    conf->inset_size);
8641         if (ret) {
8642                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8643                 return -EINVAL;
8644         }
8645         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8646                                     input_set) != 0) {
8647                 PMD_DRV_LOG(ERR, "Invalid input set");
8648                 return -EINVAL;
8649         }
8650         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8651                 /* get inset value in register */
8652                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8653                 inset_reg <<= I40E_32_BIT_WIDTH;
8654                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8655                 input_set |= pf->hash_input_set[pctype];
8656         }
8657         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8658                                            I40E_INSET_MASK_NUM_REG);
8659         if (num < 0)
8660                 return -EINVAL;
8661
8662         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8663
8664         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8665                               (uint32_t)(inset_reg & UINT32_MAX));
8666         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8667                              (uint32_t)((inset_reg >>
8668                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8669
8670         for (i = 0; i < num; i++)
8671                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8672                                      mask_reg[i]);
8673         /*clear unused mask registers of the pctype */
8674         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8675                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8676                                      0);
8677         I40E_WRITE_FLUSH(hw);
8678
8679         pf->hash_input_set[pctype] = input_set;
8680         return 0;
8681 }
8682
8683 int
8684 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8685                          struct rte_eth_input_set_conf *conf)
8686 {
8687         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8688         enum i40e_filter_pctype pctype;
8689         uint64_t input_set, inset_reg = 0;
8690         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8691         int ret, i, num;
8692
8693         if (!hw || !conf) {
8694                 PMD_DRV_LOG(ERR, "Invalid pointer");
8695                 return -EFAULT;
8696         }
8697         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8698             conf->op != RTE_ETH_INPUT_SET_ADD) {
8699                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8700                 return -EINVAL;
8701         }
8702
8703         if (!I40E_VALID_FLOW(conf->flow_type)) {
8704                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8705                 return -EINVAL;
8706         }
8707
8708         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8709
8710         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8711                                    conf->inset_size);
8712         if (ret) {
8713                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8714                 return -EINVAL;
8715         }
8716         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8717                                     input_set) != 0) {
8718                 PMD_DRV_LOG(ERR, "Invalid input set");
8719                 return -EINVAL;
8720         }
8721
8722         /* get inset value in register */
8723         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8724         inset_reg <<= I40E_32_BIT_WIDTH;
8725         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8726
8727         /* Can not change the inset reg for flex payload for fdir,
8728          * it is done by writing I40E_PRTQF_FD_FLXINSET
8729          * in i40e_set_flex_mask_on_pctype.
8730          */
8731         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8732                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8733         else
8734                 input_set |= pf->fdir.input_set[pctype];
8735         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8736                                            I40E_INSET_MASK_NUM_REG);
8737         if (num < 0)
8738                 return -EINVAL;
8739
8740         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8741
8742         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8743                               (uint32_t)(inset_reg & UINT32_MAX));
8744         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8745                              (uint32_t)((inset_reg >>
8746                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8747
8748         for (i = 0; i < num; i++)
8749                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8750                                      mask_reg[i]);
8751         /*clear unused mask registers of the pctype */
8752         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8753                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8754                                      0);
8755         I40E_WRITE_FLUSH(hw);
8756
8757         pf->fdir.input_set[pctype] = input_set;
8758         return 0;
8759 }
8760
8761 static int
8762 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8763 {
8764         int ret = 0;
8765
8766         if (!hw || !info) {
8767                 PMD_DRV_LOG(ERR, "Invalid pointer");
8768                 return -EFAULT;
8769         }
8770
8771         switch (info->info_type) {
8772         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8773                 i40e_get_symmetric_hash_enable_per_port(hw,
8774                                         &(info->info.enable));
8775                 break;
8776         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8777                 ret = i40e_get_hash_filter_global_config(hw,
8778                                 &(info->info.global_conf));
8779                 break;
8780         default:
8781                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8782                                                         info->info_type);
8783                 ret = -EINVAL;
8784                 break;
8785         }
8786
8787         return ret;
8788 }
8789
8790 static int
8791 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8792 {
8793         int ret = 0;
8794
8795         if (!hw || !info) {
8796                 PMD_DRV_LOG(ERR, "Invalid pointer");
8797                 return -EFAULT;
8798         }
8799
8800         switch (info->info_type) {
8801         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8802                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8803                 break;
8804         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8805                 ret = i40e_set_hash_filter_global_config(hw,
8806                                 &(info->info.global_conf));
8807                 break;
8808         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8809                 ret = i40e_hash_filter_inset_select(hw,
8810                                                &(info->info.input_set_conf));
8811                 break;
8812
8813         default:
8814                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8815                                                         info->info_type);
8816                 ret = -EINVAL;
8817                 break;
8818         }
8819
8820         return ret;
8821 }
8822
8823 /* Operations for hash function */
8824 static int
8825 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8826                       enum rte_filter_op filter_op,
8827                       void *arg)
8828 {
8829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8830         int ret = 0;
8831
8832         switch (filter_op) {
8833         case RTE_ETH_FILTER_NOP:
8834                 break;
8835         case RTE_ETH_FILTER_GET:
8836                 ret = i40e_hash_filter_get(hw,
8837                         (struct rte_eth_hash_filter_info *)arg);
8838                 break;
8839         case RTE_ETH_FILTER_SET:
8840                 ret = i40e_hash_filter_set(hw,
8841                         (struct rte_eth_hash_filter_info *)arg);
8842                 break;
8843         default:
8844                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8845                                                                 filter_op);
8846                 ret = -ENOTSUP;
8847                 break;
8848         }
8849
8850         return ret;
8851 }
8852
8853 /* Convert ethertype filter structure */
8854 static int
8855 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8856                               struct i40e_ethertype_filter *filter)
8857 {
8858         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8859         filter->input.ether_type = input->ether_type;
8860         filter->flags = input->flags;
8861         filter->queue = input->queue;
8862
8863         return 0;
8864 }
8865
8866 /* Check if there exists the ehtertype filter */
8867 struct i40e_ethertype_filter *
8868 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8869                                 const struct i40e_ethertype_filter_input *input)
8870 {
8871         int ret;
8872
8873         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8874         if (ret < 0)
8875                 return NULL;
8876
8877         return ethertype_rule->hash_map[ret];
8878 }
8879
8880 /* Add ethertype filter in SW list */
8881 static int
8882 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8883                                 struct i40e_ethertype_filter *filter)
8884 {
8885         struct i40e_ethertype_rule *rule = &pf->ethertype;
8886         int ret;
8887
8888         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8889         if (ret < 0) {
8890                 PMD_DRV_LOG(ERR,
8891                             "Failed to insert ethertype filter"
8892                             " to hash table %d!",
8893                             ret);
8894                 return ret;
8895         }
8896         rule->hash_map[ret] = filter;
8897
8898         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8899
8900         return 0;
8901 }
8902
8903 /* Delete ethertype filter in SW list */
8904 int
8905 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8906                              struct i40e_ethertype_filter_input *input)
8907 {
8908         struct i40e_ethertype_rule *rule = &pf->ethertype;
8909         struct i40e_ethertype_filter *filter;
8910         int ret;
8911
8912         ret = rte_hash_del_key(rule->hash_table, input);
8913         if (ret < 0) {
8914                 PMD_DRV_LOG(ERR,
8915                             "Failed to delete ethertype filter"
8916                             " to hash table %d!",
8917                             ret);
8918                 return ret;
8919         }
8920         filter = rule->hash_map[ret];
8921         rule->hash_map[ret] = NULL;
8922
8923         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8924         rte_free(filter);
8925
8926         return 0;
8927 }
8928
8929 /*
8930  * Configure ethertype filter, which can director packet by filtering
8931  * with mac address and ether_type or only ether_type
8932  */
8933 int
8934 i40e_ethertype_filter_set(struct i40e_pf *pf,
8935                         struct rte_eth_ethertype_filter *filter,
8936                         bool add)
8937 {
8938         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8939         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8940         struct i40e_ethertype_filter *ethertype_filter, *node;
8941         struct i40e_ethertype_filter check_filter;
8942         struct i40e_control_filter_stats stats;
8943         uint16_t flags = 0;
8944         int ret;
8945
8946         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8947                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8948                 return -EINVAL;
8949         }
8950         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8951                 filter->ether_type == ETHER_TYPE_IPv6) {
8952                 PMD_DRV_LOG(ERR,
8953                         "unsupported ether_type(0x%04x) in control packet filter.",
8954                         filter->ether_type);
8955                 return -EINVAL;
8956         }
8957         if (filter->ether_type == ETHER_TYPE_VLAN)
8958                 PMD_DRV_LOG(WARNING,
8959                         "filter vlan ether_type in first tag is not supported.");
8960
8961         /* Check if there is the filter in SW list */
8962         memset(&check_filter, 0, sizeof(check_filter));
8963         i40e_ethertype_filter_convert(filter, &check_filter);
8964         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8965                                                &check_filter.input);
8966         if (add && node) {
8967                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8968                 return -EINVAL;
8969         }
8970
8971         if (!add && !node) {
8972                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8973                 return -EINVAL;
8974         }
8975
8976         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8977                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8978         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8979                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8980         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8981
8982         memset(&stats, 0, sizeof(stats));
8983         ret = i40e_aq_add_rem_control_packet_filter(hw,
8984                         filter->mac_addr.addr_bytes,
8985                         filter->ether_type, flags,
8986                         pf->main_vsi->seid,
8987                         filter->queue, add, &stats, NULL);
8988
8989         PMD_DRV_LOG(INFO,
8990                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8991                 ret, stats.mac_etype_used, stats.etype_used,
8992                 stats.mac_etype_free, stats.etype_free);
8993         if (ret < 0)
8994                 return -ENOSYS;
8995
8996         /* Add or delete a filter in SW list */
8997         if (add) {
8998                 ethertype_filter = rte_zmalloc("ethertype_filter",
8999                                        sizeof(*ethertype_filter), 0);
9000                 rte_memcpy(ethertype_filter, &check_filter,
9001                            sizeof(check_filter));
9002                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9003         } else {
9004                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9005         }
9006
9007         return ret;
9008 }
9009
9010 /*
9011  * Handle operations for ethertype filter.
9012  */
9013 static int
9014 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9015                                 enum rte_filter_op filter_op,
9016                                 void *arg)
9017 {
9018         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9019         int ret = 0;
9020
9021         if (filter_op == RTE_ETH_FILTER_NOP)
9022                 return ret;
9023
9024         if (arg == NULL) {
9025                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9026                             filter_op);
9027                 return -EINVAL;
9028         }
9029
9030         switch (filter_op) {
9031         case RTE_ETH_FILTER_ADD:
9032                 ret = i40e_ethertype_filter_set(pf,
9033                         (struct rte_eth_ethertype_filter *)arg,
9034                         TRUE);
9035                 break;
9036         case RTE_ETH_FILTER_DELETE:
9037                 ret = i40e_ethertype_filter_set(pf,
9038                         (struct rte_eth_ethertype_filter *)arg,
9039                         FALSE);
9040                 break;
9041         default:
9042                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9043                 ret = -ENOSYS;
9044                 break;
9045         }
9046         return ret;
9047 }
9048
9049 static int
9050 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9051                      enum rte_filter_type filter_type,
9052                      enum rte_filter_op filter_op,
9053                      void *arg)
9054 {
9055         int ret = 0;
9056
9057         if (dev == NULL)
9058                 return -EINVAL;
9059
9060         switch (filter_type) {
9061         case RTE_ETH_FILTER_NONE:
9062                 /* For global configuration */
9063                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9064                 break;
9065         case RTE_ETH_FILTER_HASH:
9066                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9067                 break;
9068         case RTE_ETH_FILTER_MACVLAN:
9069                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9070                 break;
9071         case RTE_ETH_FILTER_ETHERTYPE:
9072                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9073                 break;
9074         case RTE_ETH_FILTER_TUNNEL:
9075                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9076                 break;
9077         case RTE_ETH_FILTER_FDIR:
9078                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9079                 break;
9080         case RTE_ETH_FILTER_GENERIC:
9081                 if (filter_op != RTE_ETH_FILTER_GET)
9082                         return -EINVAL;
9083                 *(const void **)arg = &i40e_flow_ops;
9084                 break;
9085         default:
9086                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9087                                                         filter_type);
9088                 ret = -EINVAL;
9089                 break;
9090         }
9091
9092         return ret;
9093 }
9094
9095 /*
9096  * Check and enable Extended Tag.
9097  * Enabling Extended Tag is important for 40G performance.
9098  */
9099 static void
9100 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9101 {
9102         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9103         uint32_t buf = 0;
9104         int ret;
9105
9106         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9107                                       PCI_DEV_CAP_REG);
9108         if (ret < 0) {
9109                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9110                             PCI_DEV_CAP_REG);
9111                 return;
9112         }
9113         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9114                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9115                 return;
9116         }
9117
9118         buf = 0;
9119         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9120                                       PCI_DEV_CTRL_REG);
9121         if (ret < 0) {
9122                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9123                             PCI_DEV_CTRL_REG);
9124                 return;
9125         }
9126         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9127                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9128                 return;
9129         }
9130         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9131         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9132                                        PCI_DEV_CTRL_REG);
9133         if (ret < 0) {
9134                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9135                             PCI_DEV_CTRL_REG);
9136                 return;
9137         }
9138 }
9139
9140 /*
9141  * As some registers wouldn't be reset unless a global hardware reset,
9142  * hardware initialization is needed to put those registers into an
9143  * expected initial state.
9144  */
9145 static void
9146 i40e_hw_init(struct rte_eth_dev *dev)
9147 {
9148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9149
9150         i40e_enable_extended_tag(dev);
9151
9152         /* clear the PF Queue Filter control register */
9153         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9154
9155         /* Disable symmetric hash per port */
9156         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9157 }
9158
9159 enum i40e_filter_pctype
9160 i40e_flowtype_to_pctype(uint16_t flow_type)
9161 {
9162         static const enum i40e_filter_pctype pctype_table[] = {
9163                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9164                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9165                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9166                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9167                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9168                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9169                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9170                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9171                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9172                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9173                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9174                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9175                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9176                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9177                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9178                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9179                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9180                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9181                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9182         };
9183
9184         return pctype_table[flow_type];
9185 }
9186
9187 uint16_t
9188 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9189 {
9190         static const uint16_t flowtype_table[] = {
9191                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9192                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9193                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9194                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9195                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9196                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9197                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9198                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9199                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9200                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9201                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9202                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9203                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9204                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9205                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9206                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9207                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9208                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9209                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9210                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9211                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9212                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9213                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9214                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9215                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9216                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9217                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9218                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9219                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9220                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9221                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9222         };
9223
9224         return flowtype_table[pctype];
9225 }
9226
9227 /*
9228  * On X710, performance number is far from the expectation on recent firmware
9229  * versions; on XL710, performance number is also far from the expectation on
9230  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9231  * mode is enabled and port MAC address is equal to the packet destination MAC
9232  * address. The fix for this issue may not be integrated in the following
9233  * firmware version. So the workaround in software driver is needed. It needs
9234  * to modify the initial values of 3 internal only registers for both X710 and
9235  * XL710. Note that the values for X710 or XL710 could be different, and the
9236  * workaround can be removed when it is fixed in firmware in the future.
9237  */
9238
9239 /* For both X710 and XL710 */
9240 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9241 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9242 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9243
9244 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9245 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9246
9247 /* For X722 */
9248 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9249 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9250
9251 /* For X710 */
9252 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9253 /* For XL710 */
9254 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9255 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9256
9257 static int
9258 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9259 {
9260         enum i40e_status_code status;
9261         struct i40e_aq_get_phy_abilities_resp phy_ab;
9262         int ret = -ENOTSUP;
9263         int retries = 0;
9264
9265         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9266                                               NULL);
9267
9268         while (status) {
9269                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9270                         status);
9271                 retries++;
9272                 rte_delay_us(100000);
9273                 if  (retries < 5)
9274                         status = i40e_aq_get_phy_capabilities(hw, false,
9275                                         true, &phy_ab, NULL);
9276                 else
9277                         return ret;
9278         }
9279         return 0;
9280 }
9281
9282 static void
9283 i40e_configure_registers(struct i40e_hw *hw)
9284 {
9285         static struct {
9286                 uint32_t addr;
9287                 uint64_t val;
9288         } reg_table[] = {
9289                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9290                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9291                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9292         };
9293         uint64_t reg;
9294         uint32_t i;
9295         int ret;
9296
9297         for (i = 0; i < RTE_DIM(reg_table); i++) {
9298                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9299                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9300                                 reg_table[i].val =
9301                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9302                         else /* For X710/XL710/XXV710 */
9303                                 if (hw->aq.fw_maj_ver < 6)
9304                                         reg_table[i].val =
9305                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9306                                 else
9307                                         reg_table[i].val =
9308                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9309                 }
9310
9311                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9312                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9313                                 reg_table[i].val =
9314                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9315                         else /* For X710/XL710/XXV710 */
9316                                 reg_table[i].val =
9317                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9318                 }
9319
9320                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9321                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9322                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9323                                 reg_table[i].val =
9324                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9325                         else /* For X710 */
9326                                 reg_table[i].val =
9327                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9328                 }
9329
9330                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9331                                                         &reg, NULL);
9332                 if (ret < 0) {
9333                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9334                                                         reg_table[i].addr);
9335                         break;
9336                 }
9337                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9338                                                 reg_table[i].addr, reg);
9339                 if (reg == reg_table[i].val)
9340                         continue;
9341
9342                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9343                                                 reg_table[i].val, NULL);
9344                 if (ret < 0) {
9345                         PMD_DRV_LOG(ERR,
9346                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9347                                 reg_table[i].val, reg_table[i].addr);
9348                         break;
9349                 }
9350                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9351                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9352         }
9353 }
9354
9355 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9356 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9357 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9358 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9359 static int
9360 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9361 {
9362         uint32_t reg;
9363         int ret;
9364
9365         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9366                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9367                 return -EINVAL;
9368         }
9369
9370         /* Configure for double VLAN RX stripping */
9371         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9372         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9373                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9374                 ret = i40e_aq_debug_write_register(hw,
9375                                                    I40E_VSI_TSR(vsi->vsi_id),
9376                                                    reg, NULL);
9377                 if (ret < 0) {
9378                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9379                                     vsi->vsi_id);
9380                         return I40E_ERR_CONFIG;
9381                 }
9382         }
9383
9384         /* Configure for double VLAN TX insertion */
9385         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9386         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9387                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9388                 ret = i40e_aq_debug_write_register(hw,
9389                                                    I40E_VSI_L2TAGSTXVALID(
9390                                                    vsi->vsi_id), reg, NULL);
9391                 if (ret < 0) {
9392                         PMD_DRV_LOG(ERR,
9393                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9394                                 vsi->vsi_id);
9395                         return I40E_ERR_CONFIG;
9396                 }
9397         }
9398
9399         return 0;
9400 }
9401
9402 /**
9403  * i40e_aq_add_mirror_rule
9404  * @hw: pointer to the hardware structure
9405  * @seid: VEB seid to add mirror rule to
9406  * @dst_id: destination vsi seid
9407  * @entries: Buffer which contains the entities to be mirrored
9408  * @count: number of entities contained in the buffer
9409  * @rule_id:the rule_id of the rule to be added
9410  *
9411  * Add a mirror rule for a given veb.
9412  *
9413  **/
9414 static enum i40e_status_code
9415 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9416                         uint16_t seid, uint16_t dst_id,
9417                         uint16_t rule_type, uint16_t *entries,
9418                         uint16_t count, uint16_t *rule_id)
9419 {
9420         struct i40e_aq_desc desc;
9421         struct i40e_aqc_add_delete_mirror_rule cmd;
9422         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9423                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9424                 &desc.params.raw;
9425         uint16_t buff_len;
9426         enum i40e_status_code status;
9427
9428         i40e_fill_default_direct_cmd_desc(&desc,
9429                                           i40e_aqc_opc_add_mirror_rule);
9430         memset(&cmd, 0, sizeof(cmd));
9431
9432         buff_len = sizeof(uint16_t) * count;
9433         desc.datalen = rte_cpu_to_le_16(buff_len);
9434         if (buff_len > 0)
9435                 desc.flags |= rte_cpu_to_le_16(
9436                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9437         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9438                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9439         cmd.num_entries = rte_cpu_to_le_16(count);
9440         cmd.seid = rte_cpu_to_le_16(seid);
9441         cmd.destination = rte_cpu_to_le_16(dst_id);
9442
9443         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9444         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9445         PMD_DRV_LOG(INFO,
9446                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9447                 hw->aq.asq_last_status, resp->rule_id,
9448                 resp->mirror_rules_used, resp->mirror_rules_free);
9449         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9450
9451         return status;
9452 }
9453
9454 /**
9455  * i40e_aq_del_mirror_rule
9456  * @hw: pointer to the hardware structure
9457  * @seid: VEB seid to add mirror rule to
9458  * @entries: Buffer which contains the entities to be mirrored
9459  * @count: number of entities contained in the buffer
9460  * @rule_id:the rule_id of the rule to be delete
9461  *
9462  * Delete a mirror rule for a given veb.
9463  *
9464  **/
9465 static enum i40e_status_code
9466 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9467                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9468                 uint16_t count, uint16_t rule_id)
9469 {
9470         struct i40e_aq_desc desc;
9471         struct i40e_aqc_add_delete_mirror_rule cmd;
9472         uint16_t buff_len = 0;
9473         enum i40e_status_code status;
9474         void *buff = NULL;
9475
9476         i40e_fill_default_direct_cmd_desc(&desc,
9477                                           i40e_aqc_opc_delete_mirror_rule);
9478         memset(&cmd, 0, sizeof(cmd));
9479         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9480                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9481                                                           I40E_AQ_FLAG_RD));
9482                 cmd.num_entries = count;
9483                 buff_len = sizeof(uint16_t) * count;
9484                 desc.datalen = rte_cpu_to_le_16(buff_len);
9485                 buff = (void *)entries;
9486         } else
9487                 /* rule id is filled in destination field for deleting mirror rule */
9488                 cmd.destination = rte_cpu_to_le_16(rule_id);
9489
9490         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9491                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9492         cmd.seid = rte_cpu_to_le_16(seid);
9493
9494         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9495         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9496
9497         return status;
9498 }
9499
9500 /**
9501  * i40e_mirror_rule_set
9502  * @dev: pointer to the hardware structure
9503  * @mirror_conf: mirror rule info
9504  * @sw_id: mirror rule's sw_id
9505  * @on: enable/disable
9506  *
9507  * set a mirror rule.
9508  *
9509  **/
9510 static int
9511 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9512                         struct rte_eth_mirror_conf *mirror_conf,
9513                         uint8_t sw_id, uint8_t on)
9514 {
9515         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9516         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9517         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9518         struct i40e_mirror_rule *parent = NULL;
9519         uint16_t seid, dst_seid, rule_id;
9520         uint16_t i, j = 0;
9521         int ret;
9522
9523         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9524
9525         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9526                 PMD_DRV_LOG(ERR,
9527                         "mirror rule can not be configured without veb or vfs.");
9528                 return -ENOSYS;
9529         }
9530         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9531                 PMD_DRV_LOG(ERR, "mirror table is full.");
9532                 return -ENOSPC;
9533         }
9534         if (mirror_conf->dst_pool > pf->vf_num) {
9535                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9536                                  mirror_conf->dst_pool);
9537                 return -EINVAL;
9538         }
9539
9540         seid = pf->main_vsi->veb->seid;
9541
9542         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9543                 if (sw_id <= it->index) {
9544                         mirr_rule = it;
9545                         break;
9546                 }
9547                 parent = it;
9548         }
9549         if (mirr_rule && sw_id == mirr_rule->index) {
9550                 if (on) {
9551                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9552                         return -EEXIST;
9553                 } else {
9554                         ret = i40e_aq_del_mirror_rule(hw, seid,
9555                                         mirr_rule->rule_type,
9556                                         mirr_rule->entries,
9557                                         mirr_rule->num_entries, mirr_rule->id);
9558                         if (ret < 0) {
9559                                 PMD_DRV_LOG(ERR,
9560                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9561                                         ret, hw->aq.asq_last_status);
9562                                 return -ENOSYS;
9563                         }
9564                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9565                         rte_free(mirr_rule);
9566                         pf->nb_mirror_rule--;
9567                         return 0;
9568                 }
9569         } else if (!on) {
9570                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9571                 return -ENOENT;
9572         }
9573
9574         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9575                                 sizeof(struct i40e_mirror_rule) , 0);
9576         if (!mirr_rule) {
9577                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9578                 return I40E_ERR_NO_MEMORY;
9579         }
9580         switch (mirror_conf->rule_type) {
9581         case ETH_MIRROR_VLAN:
9582                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9583                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9584                                 mirr_rule->entries[j] =
9585                                         mirror_conf->vlan.vlan_id[i];
9586                                 j++;
9587                         }
9588                 }
9589                 if (j == 0) {
9590                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9591                         rte_free(mirr_rule);
9592                         return -EINVAL;
9593                 }
9594                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9595                 break;
9596         case ETH_MIRROR_VIRTUAL_POOL_UP:
9597         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9598                 /* check if the specified pool bit is out of range */
9599                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9600                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9601                         rte_free(mirr_rule);
9602                         return -EINVAL;
9603                 }
9604                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9605                         if (mirror_conf->pool_mask & (1ULL << i)) {
9606                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9607                                 j++;
9608                         }
9609                 }
9610                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9611                         /* add pf vsi to entries */
9612                         mirr_rule->entries[j] = pf->main_vsi_seid;
9613                         j++;
9614                 }
9615                 if (j == 0) {
9616                         PMD_DRV_LOG(ERR, "pool is not specified.");
9617                         rte_free(mirr_rule);
9618                         return -EINVAL;
9619                 }
9620                 /* egress and ingress in aq commands means from switch but not port */
9621                 mirr_rule->rule_type =
9622                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9623                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9624                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9625                 break;
9626         case ETH_MIRROR_UPLINK_PORT:
9627                 /* egress and ingress in aq commands means from switch but not port*/
9628                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9629                 break;
9630         case ETH_MIRROR_DOWNLINK_PORT:
9631                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9632                 break;
9633         default:
9634                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9635                         mirror_conf->rule_type);
9636                 rte_free(mirr_rule);
9637                 return -EINVAL;
9638         }
9639
9640         /* If the dst_pool is equal to vf_num, consider it as PF */
9641         if (mirror_conf->dst_pool == pf->vf_num)
9642                 dst_seid = pf->main_vsi_seid;
9643         else
9644                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9645
9646         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9647                                       mirr_rule->rule_type, mirr_rule->entries,
9648                                       j, &rule_id);
9649         if (ret < 0) {
9650                 PMD_DRV_LOG(ERR,
9651                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9652                         ret, hw->aq.asq_last_status);
9653                 rte_free(mirr_rule);
9654                 return -ENOSYS;
9655         }
9656
9657         mirr_rule->index = sw_id;
9658         mirr_rule->num_entries = j;
9659         mirr_rule->id = rule_id;
9660         mirr_rule->dst_vsi_seid = dst_seid;
9661
9662         if (parent)
9663                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9664         else
9665                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9666
9667         pf->nb_mirror_rule++;
9668         return 0;
9669 }
9670
9671 /**
9672  * i40e_mirror_rule_reset
9673  * @dev: pointer to the device
9674  * @sw_id: mirror rule's sw_id
9675  *
9676  * reset a mirror rule.
9677  *
9678  **/
9679 static int
9680 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9681 {
9682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9684         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9685         uint16_t seid;
9686         int ret;
9687
9688         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9689
9690         seid = pf->main_vsi->veb->seid;
9691
9692         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9693                 if (sw_id == it->index) {
9694                         mirr_rule = it;
9695                         break;
9696                 }
9697         }
9698         if (mirr_rule) {
9699                 ret = i40e_aq_del_mirror_rule(hw, seid,
9700                                 mirr_rule->rule_type,
9701                                 mirr_rule->entries,
9702                                 mirr_rule->num_entries, mirr_rule->id);
9703                 if (ret < 0) {
9704                         PMD_DRV_LOG(ERR,
9705                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9706                                 ret, hw->aq.asq_last_status);
9707                         return -ENOSYS;
9708                 }
9709                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9710                 rte_free(mirr_rule);
9711                 pf->nb_mirror_rule--;
9712         } else {
9713                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9714                 return -ENOENT;
9715         }
9716         return 0;
9717 }
9718
9719 static uint64_t
9720 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9721 {
9722         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9723         uint64_t systim_cycles;
9724
9725         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9726         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9727                         << 32;
9728
9729         return systim_cycles;
9730 }
9731
9732 static uint64_t
9733 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9734 {
9735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9736         uint64_t rx_tstamp;
9737
9738         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9739         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9740                         << 32;
9741
9742         return rx_tstamp;
9743 }
9744
9745 static uint64_t
9746 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9747 {
9748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9749         uint64_t tx_tstamp;
9750
9751         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9752         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9753                         << 32;
9754
9755         return tx_tstamp;
9756 }
9757
9758 static void
9759 i40e_start_timecounters(struct rte_eth_dev *dev)
9760 {
9761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9762         struct i40e_adapter *adapter =
9763                         (struct i40e_adapter *)dev->data->dev_private;
9764         struct rte_eth_link link;
9765         uint32_t tsync_inc_l;
9766         uint32_t tsync_inc_h;
9767
9768         /* Get current link speed. */
9769         memset(&link, 0, sizeof(link));
9770         i40e_dev_link_update(dev, 1);
9771         rte_i40e_dev_atomic_read_link_status(dev, &link);
9772
9773         switch (link.link_speed) {
9774         case ETH_SPEED_NUM_40G:
9775                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9776                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9777                 break;
9778         case ETH_SPEED_NUM_10G:
9779                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9780                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9781                 break;
9782         case ETH_SPEED_NUM_1G:
9783                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9784                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9785                 break;
9786         default:
9787                 tsync_inc_l = 0x0;
9788                 tsync_inc_h = 0x0;
9789         }
9790
9791         /* Set the timesync increment value. */
9792         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9793         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9794
9795         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9796         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9797         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9798
9799         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9800         adapter->systime_tc.cc_shift = 0;
9801         adapter->systime_tc.nsec_mask = 0;
9802
9803         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9804         adapter->rx_tstamp_tc.cc_shift = 0;
9805         adapter->rx_tstamp_tc.nsec_mask = 0;
9806
9807         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9808         adapter->tx_tstamp_tc.cc_shift = 0;
9809         adapter->tx_tstamp_tc.nsec_mask = 0;
9810 }
9811
9812 static int
9813 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9814 {
9815         struct i40e_adapter *adapter =
9816                         (struct i40e_adapter *)dev->data->dev_private;
9817
9818         adapter->systime_tc.nsec += delta;
9819         adapter->rx_tstamp_tc.nsec += delta;
9820         adapter->tx_tstamp_tc.nsec += delta;
9821
9822         return 0;
9823 }
9824
9825 static int
9826 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9827 {
9828         uint64_t ns;
9829         struct i40e_adapter *adapter =
9830                         (struct i40e_adapter *)dev->data->dev_private;
9831
9832         ns = rte_timespec_to_ns(ts);
9833
9834         /* Set the timecounters to a new value. */
9835         adapter->systime_tc.nsec = ns;
9836         adapter->rx_tstamp_tc.nsec = ns;
9837         adapter->tx_tstamp_tc.nsec = ns;
9838
9839         return 0;
9840 }
9841
9842 static int
9843 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9844 {
9845         uint64_t ns, systime_cycles;
9846         struct i40e_adapter *adapter =
9847                         (struct i40e_adapter *)dev->data->dev_private;
9848
9849         systime_cycles = i40e_read_systime_cyclecounter(dev);
9850         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9851         *ts = rte_ns_to_timespec(ns);
9852
9853         return 0;
9854 }
9855
9856 static int
9857 i40e_timesync_enable(struct rte_eth_dev *dev)
9858 {
9859         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9860         uint32_t tsync_ctl_l;
9861         uint32_t tsync_ctl_h;
9862
9863         /* Stop the timesync system time. */
9864         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9865         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9866         /* Reset the timesync system time value. */
9867         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9868         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9869
9870         i40e_start_timecounters(dev);
9871
9872         /* Clear timesync registers. */
9873         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9874         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9875         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9876         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9877         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9878         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9879
9880         /* Enable timestamping of PTP packets. */
9881         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9882         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9883
9884         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9885         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9886         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9887
9888         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9889         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9890
9891         return 0;
9892 }
9893
9894 static int
9895 i40e_timesync_disable(struct rte_eth_dev *dev)
9896 {
9897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9898         uint32_t tsync_ctl_l;
9899         uint32_t tsync_ctl_h;
9900
9901         /* Disable timestamping of transmitted PTP packets. */
9902         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9903         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9904
9905         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9906         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9907
9908         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9909         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9910
9911         /* Reset the timesync increment value. */
9912         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9913         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9914
9915         return 0;
9916 }
9917
9918 static int
9919 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9920                                 struct timespec *timestamp, uint32_t flags)
9921 {
9922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9923         struct i40e_adapter *adapter =
9924                 (struct i40e_adapter *)dev->data->dev_private;
9925
9926         uint32_t sync_status;
9927         uint32_t index = flags & 0x03;
9928         uint64_t rx_tstamp_cycles;
9929         uint64_t ns;
9930
9931         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9932         if ((sync_status & (1 << index)) == 0)
9933                 return -EINVAL;
9934
9935         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9936         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9937         *timestamp = rte_ns_to_timespec(ns);
9938
9939         return 0;
9940 }
9941
9942 static int
9943 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9944                                 struct timespec *timestamp)
9945 {
9946         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9947         struct i40e_adapter *adapter =
9948                 (struct i40e_adapter *)dev->data->dev_private;
9949
9950         uint32_t sync_status;
9951         uint64_t tx_tstamp_cycles;
9952         uint64_t ns;
9953
9954         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9955         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9956                 return -EINVAL;
9957
9958         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9959         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9960         *timestamp = rte_ns_to_timespec(ns);
9961
9962         return 0;
9963 }
9964
9965 /*
9966  * i40e_parse_dcb_configure - parse dcb configure from user
9967  * @dev: the device being configured
9968  * @dcb_cfg: pointer of the result of parse
9969  * @*tc_map: bit map of enabled traffic classes
9970  *
9971  * Returns 0 on success, negative value on failure
9972  */
9973 static int
9974 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9975                          struct i40e_dcbx_config *dcb_cfg,
9976                          uint8_t *tc_map)
9977 {
9978         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9979         uint8_t i, tc_bw, bw_lf;
9980
9981         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9982
9983         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9984         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9985                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9986                 return -EINVAL;
9987         }
9988
9989         /* assume each tc has the same bw */
9990         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9991         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9992                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9993         /* to ensure the sum of tcbw is equal to 100 */
9994         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9995         for (i = 0; i < bw_lf; i++)
9996                 dcb_cfg->etscfg.tcbwtable[i]++;
9997
9998         /* assume each tc has the same Transmission Selection Algorithm */
9999         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10000                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10001
10002         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10003                 dcb_cfg->etscfg.prioritytable[i] =
10004                                 dcb_rx_conf->dcb_tc[i];
10005
10006         /* FW needs one App to configure HW */
10007         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10008         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10009         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10010         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10011
10012         if (dcb_rx_conf->nb_tcs == 0)
10013                 *tc_map = 1; /* tc0 only */
10014         else
10015                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10016
10017         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10018                 dcb_cfg->pfc.willing = 0;
10019                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10020                 dcb_cfg->pfc.pfcenable = *tc_map;
10021         }
10022         return 0;
10023 }
10024
10025
10026 static enum i40e_status_code
10027 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10028                               struct i40e_aqc_vsi_properties_data *info,
10029                               uint8_t enabled_tcmap)
10030 {
10031         enum i40e_status_code ret;
10032         int i, total_tc = 0;
10033         uint16_t qpnum_per_tc, bsf, qp_idx;
10034         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10035         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10036         uint16_t used_queues;
10037
10038         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10039         if (ret != I40E_SUCCESS)
10040                 return ret;
10041
10042         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10043                 if (enabled_tcmap & (1 << i))
10044                         total_tc++;
10045         }
10046         if (total_tc == 0)
10047                 total_tc = 1;
10048         vsi->enabled_tc = enabled_tcmap;
10049
10050         /* different VSI has different queues assigned */
10051         if (vsi->type == I40E_VSI_MAIN)
10052                 used_queues = dev_data->nb_rx_queues -
10053                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10054         else if (vsi->type == I40E_VSI_VMDQ2)
10055                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10056         else {
10057                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10058                 return I40E_ERR_NO_AVAILABLE_VSI;
10059         }
10060
10061         qpnum_per_tc = used_queues / total_tc;
10062         /* Number of queues per enabled TC */
10063         if (qpnum_per_tc == 0) {
10064                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10065                 return I40E_ERR_INVALID_QP_ID;
10066         }
10067         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10068                                 I40E_MAX_Q_PER_TC);
10069         bsf = rte_bsf32(qpnum_per_tc);
10070
10071         /**
10072          * Configure TC and queue mapping parameters, for enabled TC,
10073          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10074          * default queue will serve it.
10075          */
10076         qp_idx = 0;
10077         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10078                 if (vsi->enabled_tc & (1 << i)) {
10079                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10080                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10081                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10082                         qp_idx += qpnum_per_tc;
10083                 } else
10084                         info->tc_mapping[i] = 0;
10085         }
10086
10087         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10088         if (vsi->type == I40E_VSI_SRIOV) {
10089                 info->mapping_flags |=
10090                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10091                 for (i = 0; i < vsi->nb_qps; i++)
10092                         info->queue_mapping[i] =
10093                                 rte_cpu_to_le_16(vsi->base_queue + i);
10094         } else {
10095                 info->mapping_flags |=
10096                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10097                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10098         }
10099         info->valid_sections |=
10100                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10101
10102         return I40E_SUCCESS;
10103 }
10104
10105 /*
10106  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10107  * @veb: VEB to be configured
10108  * @tc_map: enabled TC bitmap
10109  *
10110  * Returns 0 on success, negative value on failure
10111  */
10112 static enum i40e_status_code
10113 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10114 {
10115         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10116         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10117         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10118         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10119         enum i40e_status_code ret = I40E_SUCCESS;
10120         int i;
10121         uint32_t bw_max;
10122
10123         /* Check if enabled_tc is same as existing or new TCs */
10124         if (veb->enabled_tc == tc_map)
10125                 return ret;
10126
10127         /* configure tc bandwidth */
10128         memset(&veb_bw, 0, sizeof(veb_bw));
10129         veb_bw.tc_valid_bits = tc_map;
10130         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10131         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10132                 if (tc_map & BIT_ULL(i))
10133                         veb_bw.tc_bw_share_credits[i] = 1;
10134         }
10135         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10136                                                    &veb_bw, NULL);
10137         if (ret) {
10138                 PMD_INIT_LOG(ERR,
10139                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10140                         hw->aq.asq_last_status);
10141                 return ret;
10142         }
10143
10144         memset(&ets_query, 0, sizeof(ets_query));
10145         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10146                                                    &ets_query, NULL);
10147         if (ret != I40E_SUCCESS) {
10148                 PMD_DRV_LOG(ERR,
10149                         "Failed to get switch_comp ETS configuration %u",
10150                         hw->aq.asq_last_status);
10151                 return ret;
10152         }
10153         memset(&bw_query, 0, sizeof(bw_query));
10154         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10155                                                   &bw_query, NULL);
10156         if (ret != I40E_SUCCESS) {
10157                 PMD_DRV_LOG(ERR,
10158                         "Failed to get switch_comp bandwidth configuration %u",
10159                         hw->aq.asq_last_status);
10160                 return ret;
10161         }
10162
10163         /* store and print out BW info */
10164         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10165         veb->bw_info.bw_max = ets_query.tc_bw_max;
10166         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10167         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10168         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10169                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10170                      I40E_16_BIT_WIDTH);
10171         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10172                 veb->bw_info.bw_ets_share_credits[i] =
10173                                 bw_query.tc_bw_share_credits[i];
10174                 veb->bw_info.bw_ets_credits[i] =
10175                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10176                 /* 4 bits per TC, 4th bit is reserved */
10177                 veb->bw_info.bw_ets_max[i] =
10178                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10179                                   RTE_LEN2MASK(3, uint8_t));
10180                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10181                             veb->bw_info.bw_ets_share_credits[i]);
10182                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10183                             veb->bw_info.bw_ets_credits[i]);
10184                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10185                             veb->bw_info.bw_ets_max[i]);
10186         }
10187
10188         veb->enabled_tc = tc_map;
10189
10190         return ret;
10191 }
10192
10193
10194 /*
10195  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10196  * @vsi: VSI to be configured
10197  * @tc_map: enabled TC bitmap
10198  *
10199  * Returns 0 on success, negative value on failure
10200  */
10201 static enum i40e_status_code
10202 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10203 {
10204         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10205         struct i40e_vsi_context ctxt;
10206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10207         enum i40e_status_code ret = I40E_SUCCESS;
10208         int i;
10209
10210         /* Check if enabled_tc is same as existing or new TCs */
10211         if (vsi->enabled_tc == tc_map)
10212                 return ret;
10213
10214         /* configure tc bandwidth */
10215         memset(&bw_data, 0, sizeof(bw_data));
10216         bw_data.tc_valid_bits = tc_map;
10217         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10218         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10219                 if (tc_map & BIT_ULL(i))
10220                         bw_data.tc_bw_credits[i] = 1;
10221         }
10222         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10223         if (ret) {
10224                 PMD_INIT_LOG(ERR,
10225                         "AQ command Config VSI BW allocation per TC failed = %d",
10226                         hw->aq.asq_last_status);
10227                 goto out;
10228         }
10229         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10230                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10231
10232         /* Update Queue Pairs Mapping for currently enabled UPs */
10233         ctxt.seid = vsi->seid;
10234         ctxt.pf_num = hw->pf_id;
10235         ctxt.vf_num = 0;
10236         ctxt.uplink_seid = vsi->uplink_seid;
10237         ctxt.info = vsi->info;
10238         i40e_get_cap(hw);
10239         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10240         if (ret)
10241                 goto out;
10242
10243         /* Update the VSI after updating the VSI queue-mapping information */
10244         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10245         if (ret) {
10246                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10247                         hw->aq.asq_last_status);
10248                 goto out;
10249         }
10250         /* update the local VSI info with updated queue map */
10251         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10252                                         sizeof(vsi->info.tc_mapping));
10253         (void)rte_memcpy(&vsi->info.queue_mapping,
10254                         &ctxt.info.queue_mapping,
10255                 sizeof(vsi->info.queue_mapping));
10256         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10257         vsi->info.valid_sections = 0;
10258
10259         /* query and update current VSI BW information */
10260         ret = i40e_vsi_get_bw_config(vsi);
10261         if (ret) {
10262                 PMD_INIT_LOG(ERR,
10263                          "Failed updating vsi bw info, err %s aq_err %s",
10264                          i40e_stat_str(hw, ret),
10265                          i40e_aq_str(hw, hw->aq.asq_last_status));
10266                 goto out;
10267         }
10268
10269         vsi->enabled_tc = tc_map;
10270
10271 out:
10272         return ret;
10273 }
10274
10275 /*
10276  * i40e_dcb_hw_configure - program the dcb setting to hw
10277  * @pf: pf the configuration is taken on
10278  * @new_cfg: new configuration
10279  * @tc_map: enabled TC bitmap
10280  *
10281  * Returns 0 on success, negative value on failure
10282  */
10283 static enum i40e_status_code
10284 i40e_dcb_hw_configure(struct i40e_pf *pf,
10285                       struct i40e_dcbx_config *new_cfg,
10286                       uint8_t tc_map)
10287 {
10288         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10289         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10290         struct i40e_vsi *main_vsi = pf->main_vsi;
10291         struct i40e_vsi_list *vsi_list;
10292         enum i40e_status_code ret;
10293         int i;
10294         uint32_t val;
10295
10296         /* Use the FW API if FW > v4.4*/
10297         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10298               (hw->aq.fw_maj_ver >= 5))) {
10299                 PMD_INIT_LOG(ERR,
10300                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10301                 return I40E_ERR_FIRMWARE_API_VERSION;
10302         }
10303
10304         /* Check if need reconfiguration */
10305         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10306                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10307                 return I40E_SUCCESS;
10308         }
10309
10310         /* Copy the new config to the current config */
10311         *old_cfg = *new_cfg;
10312         old_cfg->etsrec = old_cfg->etscfg;
10313         ret = i40e_set_dcb_config(hw);
10314         if (ret) {
10315                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10316                          i40e_stat_str(hw, ret),
10317                          i40e_aq_str(hw, hw->aq.asq_last_status));
10318                 return ret;
10319         }
10320         /* set receive Arbiter to RR mode and ETS scheme by default */
10321         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10322                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10323                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10324                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10325                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10326                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10327                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10328                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10329                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10330                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10331                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10332                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10333                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10334         }
10335         /* get local mib to check whether it is configured correctly */
10336         /* IEEE mode */
10337         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10338         /* Get Local DCB Config */
10339         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10340                                      &hw->local_dcbx_config);
10341
10342         /* if Veb is created, need to update TC of it at first */
10343         if (main_vsi->veb) {
10344                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10345                 if (ret)
10346                         PMD_INIT_LOG(WARNING,
10347                                  "Failed configuring TC for VEB seid=%d",
10348                                  main_vsi->veb->seid);
10349         }
10350         /* Update each VSI */
10351         i40e_vsi_config_tc(main_vsi, tc_map);
10352         if (main_vsi->veb) {
10353                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10354                         /* Beside main VSI and VMDQ VSIs, only enable default
10355                          * TC for other VSIs
10356                          */
10357                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10358                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10359                                                          tc_map);
10360                         else
10361                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10362                                                          I40E_DEFAULT_TCMAP);
10363                         if (ret)
10364                                 PMD_INIT_LOG(WARNING,
10365                                         "Failed configuring TC for VSI seid=%d",
10366                                         vsi_list->vsi->seid);
10367                         /* continue */
10368                 }
10369         }
10370         return I40E_SUCCESS;
10371 }
10372
10373 /*
10374  * i40e_dcb_init_configure - initial dcb config
10375  * @dev: device being configured
10376  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10377  *
10378  * Returns 0 on success, negative value on failure
10379  */
10380 static int
10381 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10382 {
10383         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10384         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10385         int i, ret = 0;
10386
10387         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10388                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10389                 return -ENOTSUP;
10390         }
10391
10392         /* DCB initialization:
10393          * Update DCB configuration from the Firmware and configure
10394          * LLDP MIB change event.
10395          */
10396         if (sw_dcb == TRUE) {
10397                 ret = i40e_init_dcb(hw);
10398                 /* If lldp agent is stopped, the return value from
10399                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10400                  * adminq status. Otherwise, it should return success.
10401                  */
10402                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10403                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10404                         memset(&hw->local_dcbx_config, 0,
10405                                 sizeof(struct i40e_dcbx_config));
10406                         /* set dcb default configuration */
10407                         hw->local_dcbx_config.etscfg.willing = 0;
10408                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10409                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10410                         hw->local_dcbx_config.etscfg.tsatable[0] =
10411                                                 I40E_IEEE_TSA_ETS;
10412                         /* all UPs mapping to TC0 */
10413                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10414                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10415                         hw->local_dcbx_config.etsrec =
10416                                 hw->local_dcbx_config.etscfg;
10417                         hw->local_dcbx_config.pfc.willing = 0;
10418                         hw->local_dcbx_config.pfc.pfccap =
10419                                                 I40E_MAX_TRAFFIC_CLASS;
10420                         /* FW needs one App to configure HW */
10421                         hw->local_dcbx_config.numapps = 1;
10422                         hw->local_dcbx_config.app[0].selector =
10423                                                 I40E_APP_SEL_ETHTYPE;
10424                         hw->local_dcbx_config.app[0].priority = 3;
10425                         hw->local_dcbx_config.app[0].protocolid =
10426                                                 I40E_APP_PROTOID_FCOE;
10427                         ret = i40e_set_dcb_config(hw);
10428                         if (ret) {
10429                                 PMD_INIT_LOG(ERR,
10430                                         "default dcb config fails. err = %d, aq_err = %d.",
10431                                         ret, hw->aq.asq_last_status);
10432                                 return -ENOSYS;
10433                         }
10434                 } else {
10435                         PMD_INIT_LOG(ERR,
10436                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10437                                 ret, hw->aq.asq_last_status);
10438                         return -ENOTSUP;
10439                 }
10440         } else {
10441                 ret = i40e_aq_start_lldp(hw, NULL);
10442                 if (ret != I40E_SUCCESS)
10443                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10444
10445                 ret = i40e_init_dcb(hw);
10446                 if (!ret) {
10447                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10448                                 PMD_INIT_LOG(ERR,
10449                                         "HW doesn't support DCBX offload.");
10450                                 return -ENOTSUP;
10451                         }
10452                 } else {
10453                         PMD_INIT_LOG(ERR,
10454                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10455                                 ret, hw->aq.asq_last_status);
10456                         return -ENOTSUP;
10457                 }
10458         }
10459         return 0;
10460 }
10461
10462 /*
10463  * i40e_dcb_setup - setup dcb related config
10464  * @dev: device being configured
10465  *
10466  * Returns 0 on success, negative value on failure
10467  */
10468 static int
10469 i40e_dcb_setup(struct rte_eth_dev *dev)
10470 {
10471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10472         struct i40e_dcbx_config dcb_cfg;
10473         uint8_t tc_map = 0;
10474         int ret = 0;
10475
10476         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10477                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10478                 return -ENOTSUP;
10479         }
10480
10481         if (pf->vf_num != 0)
10482                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10483
10484         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10485         if (ret) {
10486                 PMD_INIT_LOG(ERR, "invalid dcb config");
10487                 return -EINVAL;
10488         }
10489         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10490         if (ret) {
10491                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10492                 return -ENOSYS;
10493         }
10494
10495         return 0;
10496 }
10497
10498 static int
10499 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10500                       struct rte_eth_dcb_info *dcb_info)
10501 {
10502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10504         struct i40e_vsi *vsi = pf->main_vsi;
10505         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10506         uint16_t bsf, tc_mapping;
10507         int i, j = 0;
10508
10509         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10510                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10511         else
10512                 dcb_info->nb_tcs = 1;
10513         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10514                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10515         for (i = 0; i < dcb_info->nb_tcs; i++)
10516                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10517
10518         /* get queue mapping if vmdq is disabled */
10519         if (!pf->nb_cfg_vmdq_vsi) {
10520                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10521                         if (!(vsi->enabled_tc & (1 << i)))
10522                                 continue;
10523                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10524                         dcb_info->tc_queue.tc_rxq[j][i].base =
10525                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10526                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10527                         dcb_info->tc_queue.tc_txq[j][i].base =
10528                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10529                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10530                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10531                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10532                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10533                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10534                 }
10535                 return 0;
10536         }
10537
10538         /* get queue mapping if vmdq is enabled */
10539         do {
10540                 vsi = pf->vmdq[j].vsi;
10541                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10542                         if (!(vsi->enabled_tc & (1 << i)))
10543                                 continue;
10544                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10545                         dcb_info->tc_queue.tc_rxq[j][i].base =
10546                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10547                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10548                         dcb_info->tc_queue.tc_txq[j][i].base =
10549                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10550                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10551                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10552                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10553                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10554                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10555                 }
10556                 j++;
10557         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10558         return 0;
10559 }
10560
10561 static int
10562 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10563 {
10564         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10565         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10566         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10567         uint16_t interval =
10568                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10569         uint16_t msix_intr;
10570
10571         msix_intr = intr_handle->intr_vec[queue_id];
10572         if (msix_intr == I40E_MISC_VEC_ID)
10573                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10574                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10575                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10576                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10577                                (interval <<
10578                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10579         else
10580                 I40E_WRITE_REG(hw,
10581                                I40E_PFINT_DYN_CTLN(msix_intr -
10582                                                    I40E_RX_VEC_START),
10583                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10584                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10585                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10586                                (interval <<
10587                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10588
10589         I40E_WRITE_FLUSH(hw);
10590         rte_intr_enable(&pci_dev->intr_handle);
10591
10592         return 0;
10593 }
10594
10595 static int
10596 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10597 {
10598         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10599         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10601         uint16_t msix_intr;
10602
10603         msix_intr = intr_handle->intr_vec[queue_id];
10604         if (msix_intr == I40E_MISC_VEC_ID)
10605                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10606         else
10607                 I40E_WRITE_REG(hw,
10608                                I40E_PFINT_DYN_CTLN(msix_intr -
10609                                                    I40E_RX_VEC_START),
10610                                0);
10611         I40E_WRITE_FLUSH(hw);
10612
10613         return 0;
10614 }
10615
10616 static int i40e_get_regs(struct rte_eth_dev *dev,
10617                          struct rte_dev_reg_info *regs)
10618 {
10619         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10620         uint32_t *ptr_data = regs->data;
10621         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10622         const struct i40e_reg_info *reg_info;
10623
10624         if (ptr_data == NULL) {
10625                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10626                 regs->width = sizeof(uint32_t);
10627                 return 0;
10628         }
10629
10630         /* The first few registers have to be read using AQ operations */
10631         reg_idx = 0;
10632         while (i40e_regs_adminq[reg_idx].name) {
10633                 reg_info = &i40e_regs_adminq[reg_idx++];
10634                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10635                         for (arr_idx2 = 0;
10636                                         arr_idx2 <= reg_info->count2;
10637                                         arr_idx2++) {
10638                                 reg_offset = arr_idx * reg_info->stride1 +
10639                                         arr_idx2 * reg_info->stride2;
10640                                 reg_offset += reg_info->base_addr;
10641                                 ptr_data[reg_offset >> 2] =
10642                                         i40e_read_rx_ctl(hw, reg_offset);
10643                         }
10644         }
10645
10646         /* The remaining registers can be read using primitives */
10647         reg_idx = 0;
10648         while (i40e_regs_others[reg_idx].name) {
10649                 reg_info = &i40e_regs_others[reg_idx++];
10650                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10651                         for (arr_idx2 = 0;
10652                                         arr_idx2 <= reg_info->count2;
10653                                         arr_idx2++) {
10654                                 reg_offset = arr_idx * reg_info->stride1 +
10655                                         arr_idx2 * reg_info->stride2;
10656                                 reg_offset += reg_info->base_addr;
10657                                 ptr_data[reg_offset >> 2] =
10658                                         I40E_READ_REG(hw, reg_offset);
10659                         }
10660         }
10661
10662         return 0;
10663 }
10664
10665 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10666 {
10667         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10668
10669         /* Convert word count to byte count */
10670         return hw->nvm.sr_size << 1;
10671 }
10672
10673 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10674                            struct rte_dev_eeprom_info *eeprom)
10675 {
10676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10677         uint16_t *data = eeprom->data;
10678         uint16_t offset, length, cnt_words;
10679         int ret_code;
10680
10681         offset = eeprom->offset >> 1;
10682         length = eeprom->length >> 1;
10683         cnt_words = length;
10684
10685         if (offset > hw->nvm.sr_size ||
10686                 offset + length > hw->nvm.sr_size) {
10687                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10688                 return -EINVAL;
10689         }
10690
10691         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10692
10693         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10694         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10695                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10696                 return -EIO;
10697         }
10698
10699         return 0;
10700 }
10701
10702 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10703                                       struct ether_addr *mac_addr)
10704 {
10705         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10706
10707         if (!is_valid_assigned_ether_addr(mac_addr)) {
10708                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10709                 return;
10710         }
10711
10712         /* Flags: 0x3 updates port address */
10713         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10714 }
10715
10716 static int
10717 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10718 {
10719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10720         struct rte_eth_dev_data *dev_data = pf->dev_data;
10721         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10722         int ret = 0;
10723
10724         /* check if mtu is within the allowed range */
10725         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10726                 return -EINVAL;
10727
10728         /* mtu setting is forbidden if port is start */
10729         if (dev_data->dev_started) {
10730                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10731                             dev_data->port_id);
10732                 return -EBUSY;
10733         }
10734
10735         if (frame_size > ETHER_MAX_LEN)
10736                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10737         else
10738                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10739
10740         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10741
10742         return ret;
10743 }
10744
10745 /* Restore ethertype filter */
10746 static void
10747 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10748 {
10749         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10750         struct i40e_ethertype_filter_list
10751                 *ethertype_list = &pf->ethertype.ethertype_list;
10752         struct i40e_ethertype_filter *f;
10753         struct i40e_control_filter_stats stats;
10754         uint16_t flags;
10755
10756         TAILQ_FOREACH(f, ethertype_list, rules) {
10757                 flags = 0;
10758                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10759                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10760                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10761                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10762                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10763
10764                 memset(&stats, 0, sizeof(stats));
10765                 i40e_aq_add_rem_control_packet_filter(hw,
10766                                             f->input.mac_addr.addr_bytes,
10767                                             f->input.ether_type,
10768                                             flags, pf->main_vsi->seid,
10769                                             f->queue, 1, &stats, NULL);
10770         }
10771         PMD_DRV_LOG(INFO, "Ethertype filter:"
10772                     " mac_etype_used = %u, etype_used = %u,"
10773                     " mac_etype_free = %u, etype_free = %u",
10774                     stats.mac_etype_used, stats.etype_used,
10775                     stats.mac_etype_free, stats.etype_free);
10776 }
10777
10778 /* Restore tunnel filter */
10779 static void
10780 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10781 {
10782         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10783         struct i40e_vsi *vsi;
10784         struct i40e_pf_vf *vf;
10785         struct i40e_tunnel_filter_list
10786                 *tunnel_list = &pf->tunnel.tunnel_list;
10787         struct i40e_tunnel_filter *f;
10788         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10789         bool big_buffer = 0;
10790
10791         TAILQ_FOREACH(f, tunnel_list, rules) {
10792                 if (!f->is_to_vf)
10793                         vsi = pf->main_vsi;
10794                 else {
10795                         vf = &pf->vfs[f->vf_id];
10796                         vsi = vf->vsi;
10797                 }
10798                 memset(&cld_filter, 0, sizeof(cld_filter));
10799                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10800                         (struct ether_addr *)&cld_filter.element.outer_mac);
10801                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10802                         (struct ether_addr *)&cld_filter.element.inner_mac);
10803                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10804                 cld_filter.element.flags = f->input.flags;
10805                 cld_filter.element.tenant_id = f->input.tenant_id;
10806                 cld_filter.element.queue_number = f->queue;
10807                 rte_memcpy(cld_filter.general_fields,
10808                            f->input.general_fields,
10809                            sizeof(f->input.general_fields));
10810
10811                 if (((f->input.flags &
10812                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10813                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10814                     ((f->input.flags &
10815                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10816                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10817                     ((f->input.flags &
10818                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10819                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10820                         big_buffer = 1;
10821
10822                 if (big_buffer)
10823                         i40e_aq_add_cloud_filters_big_buffer(hw,
10824                                              vsi->seid, &cld_filter, 1);
10825                 else
10826                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10827                                                   &cld_filter.element, 1);
10828         }
10829 }
10830
10831 static void
10832 i40e_filter_restore(struct i40e_pf *pf)
10833 {
10834         i40e_ethertype_filter_restore(pf);
10835         i40e_tunnel_filter_restore(pf);
10836         i40e_fdir_filter_restore(pf);
10837 }
10838
10839 static bool
10840 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10841 {
10842         if (strcmp(dev->device->driver->name, drv->driver.name))
10843                 return false;
10844
10845         return true;
10846 }
10847
10848 bool
10849 is_i40e_supported(struct rte_eth_dev *dev)
10850 {
10851         return is_device_supported(dev, &rte_i40e_pmd);
10852 }
10853
10854 /* Create a QinQ cloud filter
10855  *
10856  * The Fortville NIC has limited resources for tunnel filters,
10857  * so we can only reuse existing filters.
10858  *
10859  * In step 1 we define which Field Vector fields can be used for
10860  * filter types.
10861  * As we do not have the inner tag defined as a field,
10862  * we have to define it first, by reusing one of L1 entries.
10863  *
10864  * In step 2 we are replacing one of existing filter types with
10865  * a new one for QinQ.
10866  * As we reusing L1 and replacing L2, some of the default filter
10867  * types will disappear,which depends on L1 and L2 entries we reuse.
10868  *
10869  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10870  *
10871  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10872  *              later when we define the cloud filter.
10873  *      a.      Valid_flags.replace_cloud = 0
10874  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10875  *      c.      New_filter = 0x10
10876  *      d.      TR bit = 0xff (optional, not used here)
10877  *      e.      Buffer – 2 entries:
10878  *              i.      Byte 0 = 8 (outer vlan FV index).
10879  *                      Byte 1 = 0 (rsv)
10880  *                      Byte 2-3 = 0x0fff
10881  *              ii.     Byte 0 = 37 (inner vlan FV index).
10882  *                      Byte 1 =0 (rsv)
10883  *                      Byte 2-3 = 0x0fff
10884  *
10885  * Step 2:
10886  * 2.   Create cloud filter using two L1 filters entries: stag and
10887  *              new filter(outer vlan+ inner vlan)
10888  *      a.      Valid_flags.replace_cloud = 1
10889  *      b.      Old_filter = 1 (instead of outer IP)
10890  *      c.      New_filter = 0x10
10891  *      d.      Buffer – 2 entries:
10892  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10893  *                      Byte 1-3 = 0 (rsv)
10894  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10895  *                      Byte 9-11 = 0 (rsv)
10896  */
10897 static int
10898 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10899 {
10900         int ret = -ENOTSUP;
10901         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10902         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10903         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10904
10905         /* Init */
10906         memset(&filter_replace, 0,
10907                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10908         memset(&filter_replace_buf, 0,
10909                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10910
10911         /* create L1 filter */
10912         filter_replace.old_filter_type =
10913                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10914         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10915         filter_replace.tr_bit = 0;
10916
10917         /* Prepare the buffer, 2 entries */
10918         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10919         filter_replace_buf.data[0] |=
10920                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10921         /* Field Vector 12b mask */
10922         filter_replace_buf.data[2] = 0xff;
10923         filter_replace_buf.data[3] = 0x0f;
10924         filter_replace_buf.data[4] =
10925                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10926         filter_replace_buf.data[4] |=
10927                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10928         /* Field Vector 12b mask */
10929         filter_replace_buf.data[6] = 0xff;
10930         filter_replace_buf.data[7] = 0x0f;
10931         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10932                         &filter_replace_buf);
10933         if (ret != I40E_SUCCESS)
10934                 return ret;
10935
10936         /* Apply the second L2 cloud filter */
10937         memset(&filter_replace, 0,
10938                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10939         memset(&filter_replace_buf, 0,
10940                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10941
10942         /* create L2 filter, input for L2 filter will be L1 filter  */
10943         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10944         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10945         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10946
10947         /* Prepare the buffer, 2 entries */
10948         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10949         filter_replace_buf.data[0] |=
10950                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10951         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10952         filter_replace_buf.data[4] |=
10953                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10954         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10955                         &filter_replace_buf);
10956         return ret;
10957 }
10958
10959 RTE_INIT(i40e_init_log);
10960 static void
10961 i40e_init_log(void)
10962 {
10963         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10964         if (i40e_logtype_init >= 0)
10965                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10966         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10967         if (i40e_logtype_driver >= 0)
10968                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10969 }