drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(
 377                 __rte_unused struct rte_intr_handle *handle, void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 426                         struct rte_eth_mirror_conf *mirror_conf,
 427                         uint8_t sw_id, uint8_t on);
 428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 429
 430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 433                                            struct timespec *timestamp,
 434                                            uint32_t flags);
 435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp);
 437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 438
 439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 440
 441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 442                                    struct timespec *timestamp);
 443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 444                                     const struct timespec *timestamp);
 445
 446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 447                                          uint16_t queue_id);
 448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 449                                           uint16_t queue_id);
 450
 451 static int i40e_get_regs(struct rte_eth_dev *dev,
 452                          struct rte_dev_reg_info *regs);
 453
 454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 455
 456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 457                            struct rte_dev_eeprom_info *eeprom);
 458
 459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 460                                       struct ether_addr *mac_addr);
 461
 462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 463
 464 static const struct rte_pci_id pci_id_i40e_map[] = {
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct eth_dev_ops i40e_eth_dev_ops = {
 489         .dev_configure                = i40e_dev_configure,
 490         .dev_start                    = i40e_dev_start,
 491         .dev_stop                     = i40e_dev_stop,
 492         .dev_close                    = i40e_dev_close,
 493         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 494         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 495         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 496         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 497         .dev_set_link_up              = i40e_dev_set_link_up,
 498         .dev_set_link_down            = i40e_dev_set_link_down,
 499         .link_update                  = i40e_dev_link_update,
 500         .stats_get                    = i40e_dev_stats_get,
 501         .xstats_get                   = i40e_dev_xstats_get,
 502         .xstats_get_names             = i40e_dev_xstats_get_names,
 503         .stats_reset                  = i40e_dev_stats_reset,
 504         .xstats_reset                 = i40e_dev_stats_reset,
 505         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 506         .dev_infos_get                = i40e_dev_info_get,
 507         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 508         .vlan_filter_set              = i40e_vlan_filter_set,
 509         .vlan_tpid_set                = i40e_vlan_tpid_set,
 510         .vlan_offload_set             = i40e_vlan_offload_set,
 511         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 512         .vlan_pvid_set                = i40e_vlan_pvid_set,
 513         .rx_queue_start               = i40e_dev_rx_queue_start,
 514         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 515         .tx_queue_start               = i40e_dev_tx_queue_start,
 516         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 517         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 518         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 519         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 520         .rx_queue_release             = i40e_dev_rx_queue_release,
 521         .rx_queue_count               = i40e_dev_rx_queue_count,
 522         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 523         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 524         .tx_queue_release             = i40e_dev_tx_queue_release,
 525         .dev_led_on                   = i40e_dev_led_on,
 526         .dev_led_off                  = i40e_dev_led_off,
 527         .flow_ctrl_get                = i40e_flow_ctrl_get,
 528         .flow_ctrl_set                = i40e_flow_ctrl_set,
 529         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 530         .mac_addr_add                 = i40e_macaddr_add,
 531         .mac_addr_remove              = i40e_macaddr_remove,
 532         .reta_update                  = i40e_dev_rss_reta_update,
 533         .reta_query                   = i40e_dev_rss_reta_query,
 534         .rss_hash_update              = i40e_dev_rss_hash_update,
 535         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 536         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 537         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 538         .filter_ctrl                  = i40e_dev_filter_ctrl,
 539         .rxq_info_get                 = i40e_rxq_info_get,
 540         .txq_info_get                 = i40e_txq_info_get,
 541         .mirror_rule_set              = i40e_mirror_rule_set,
 542         .mirror_rule_reset            = i40e_mirror_rule_reset,
 543         .timesync_enable              = i40e_timesync_enable,
 544         .timesync_disable             = i40e_timesync_disable,
 545         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 547         .get_dcb_info                 = i40e_dev_get_dcb_info,
 548         .timesync_adjust_time         = i40e_timesync_adjust_time,
 549         .timesync_read_time           = i40e_timesync_read_time,
 550         .timesync_write_time          = i40e_timesync_write_time,
 551         .get_reg                      = i40e_get_regs,
 552         .get_eeprom_length            = i40e_get_eeprom_length,
 553         .get_eeprom                   = i40e_get_eeprom,
 554         .mac_addr_set                 = i40e_set_default_mac_addr,
 555         .mtu_set                      = i40e_dev_mtu_set,
 556 };
 557
 558 /* store statistics names and its offset in stats structure */
 559 struct rte_i40e_xstats_name_off {
 560         char name[RTE_ETH_XSTATS_NAME_SIZE];
 561         unsigned offset;
 562 };
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 565         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 566         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 567         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 568         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 569         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 570                 rx_unknown_protocol)},
 571         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 572         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 573         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 574         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 575 };
 576
 577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 578                 sizeof(rte_i40e_stats_strings[0]))
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 581         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 582                 tx_dropped_link_down)},
 583         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 584         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 585                 illegal_bytes)},
 586         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 587         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 588                 mac_local_faults)},
 589         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 590                 mac_remote_faults)},
 591         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_length_errors)},
 593         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 594         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 595         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 596         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 597         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 598         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 599                 rx_size_127)},
 600         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 601                 rx_size_255)},
 602         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 603                 rx_size_511)},
 604         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 605                 rx_size_1023)},
 606         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 607                 rx_size_1522)},
 608         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 609                 rx_size_big)},
 610         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_undersize)},
 612         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 613                 rx_oversize)},
 614         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 615                 mac_short_packet_dropped)},
 616         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 617                 rx_fragments)},
 618         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 619         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 620         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 621                 tx_size_127)},
 622         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 623                 tx_size_255)},
 624         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 625                 tx_size_511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 627                 tx_size_1023)},
 628         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 629                 tx_size_1522)},
 630         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 631                 tx_size_big)},
 632         {"rx_flow_director_atr_match_packets",
 633                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 634         {"rx_flow_director_sb_match_packets",
 635                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 636         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 637                 tx_lpi_status)},
 638         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 639                 rx_lpi_status)},
 640         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 641                 tx_lpi_count)},
 642         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 643                 rx_lpi_count)},
 644 };
 645
 646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 647                 sizeof(rte_i40e_hw_port_strings[0]))
 648
 649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 650         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 651                 priority_xon_rx)},
 652         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 653                 priority_xoff_rx)},
 654 };
 655
 656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 657                 sizeof(rte_i40e_rxq_prio_strings[0]))
 658
 659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 660         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 661                 priority_xon_tx)},
 662         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 663                 priority_xoff_tx)},
 664         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 665                 priority_xon_2_xoff)},
 666 };
 667
 668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 669                 sizeof(rte_i40e_txq_prio_strings[0]))
 670
 671 static struct eth_driver rte_i40e_pmd = {
 672         .pci_drv = {
 673                 .id_table = pci_id_i40e_map,
 674                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 675                         RTE_PCI_DRV_DETACHABLE,
 676                 .probe = rte_eth_dev_pci_probe,
 677                 .remove = rte_eth_dev_pci_remove,
 678         },
 679         .eth_dev_init = eth_i40e_dev_init,
 680         .eth_dev_uninit = eth_i40e_dev_uninit,
 681         .dev_private_size = sizeof(struct i40e_adapter),
 682 };
 683
 684 static inline int
 685 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 686                                      struct rte_eth_link *link)
 687 {
 688         struct rte_eth_link *dst = link;
 689         struct rte_eth_link *src = &(dev->data->dev_link);
 690
 691         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 692                                         *(uint64_t *)src) == 0)
 693                 return -1;
 694
 695         return 0;
 696 }
 697
 698 static inline int
 699 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 700                                       struct rte_eth_link *link)
 701 {
 702         struct rte_eth_link *dst = &(dev->data->dev_link);
 703         struct rte_eth_link *src = link;
 704
 705         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 706                                         *(uint64_t *)src) == 0)
 707                 return -1;
 708
 709         return 0;
 710 }
 711
 712 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 713 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 714
 715 #ifndef I40E_GLQF_ORT
 716 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 717 #endif
 718 #ifndef I40E_GLQF_PIT
 719 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 720 #endif
 721
 722 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 723 {
 724         /*
 725          * Initialize registers for flexible payload, which should be set by NVM.
 726          * This should be removed from code once it is fixed in NVM.
 727          */
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 738         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 739         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 740
 741         /* Initialize registers for parsing packet type of QinQ */
 742         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 743         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 744 }
 745
 746 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 747
 748 /*
 749  * Add a ethertype filter to drop all flow control frames transmitted
 750  * from VSIs.
 751 */
 752 static void
 753 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 754 {
 755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 756         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 757                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 758                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 759         int ret;
 760
 761         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 762                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 763                                 pf->main_vsi_seid, 0,
 764                                 TRUE, NULL, NULL);
 765         if (ret)
 766                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 767                                   " frames from VSIs.");
 768 }
 769
 770 static int
 771 floating_veb_list_handler(__rte_unused const char *key,
 772                           const char *floating_veb_value,
 773                           void *opaque)
 774 {
 775         int idx = 0;
 776         unsigned int count = 0;
 777         char *end = NULL;
 778         int min, max;
 779         bool *vf_floating_veb = opaque;
 780
 781         while (isblank(*floating_veb_value))
 782                 floating_veb_value++;
 783
 784         /* Reset floating VEB configuration for VFs */
 785         for (idx = 0; idx < I40E_MAX_VF; idx++)
 786                 vf_floating_veb[idx] = false;
 787
 788         min = I40E_MAX_VF;
 789         do {
 790                 while (isblank(*floating_veb_value))
 791                         floating_veb_value++;
 792                 if (*floating_veb_value == '\0')
 793                         return -1;
 794                 errno = 0;
 795                 idx = strtoul(floating_veb_value, &end, 10);
 796                 if (errno || end == NULL)
 797                         return -1;
 798                 while (isblank(*end))
 799                         end++;
 800                 if (*end == '-') {
 801                         min = idx;
 802                 } else if ((*end == ';') || (*end == '\0')) {
 803                         max = idx;
 804                         if (min == I40E_MAX_VF)
 805                                 min = idx;
 806                         if (max >= I40E_MAX_VF)
 807                                 max = I40E_MAX_VF - 1;
 808                         for (idx = min; idx <= max; idx++) {
 809                                 vf_floating_veb[idx] = true;
 810                                 count++;
 811                         }
 812                         min = I40E_MAX_VF;
 813                 } else {
 814                         return -1;
 815                 }
 816                 floating_veb_value = end + 1;
 817         } while (*end != '\0');
 818
 819         if (count == 0)
 820                 return -1;
 821
 822         return 0;
 823 }
 824
 825 static void
 826 config_vf_floating_veb(struct rte_devargs *devargs,
 827                        uint16_t floating_veb,
 828                        bool *vf_floating_veb)
 829 {
 830         struct rte_kvargs *kvlist;
 831         int i;
 832         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 833
 834         if (!floating_veb)
 835                 return;
 836         /* All the VFs attach to the floating VEB by default
 837          * when the floating VEB is enabled.
 838          */
 839         for (i = 0; i < I40E_MAX_VF; i++)
 840                 vf_floating_veb[i] = true;
 841
 842         if (devargs == NULL)
 843                 return;
 844
 845         kvlist = rte_kvargs_parse(devargs->args, NULL);
 846         if (kvlist == NULL)
 847                 return;
 848
 849         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 850                 rte_kvargs_free(kvlist);
 851                 return;
 852         }
 853         /* When the floating_veb_list parameter exists, all the VFs
 854          * will attach to the legacy VEB firstly, then configure VFs
 855          * to the floating VEB according to the floating_veb_list.
 856          */
 857         if (rte_kvargs_process(kvlist, floating_veb_list,
 858                                floating_veb_list_handler,
 859                                vf_floating_veb) < 0) {
 860                 rte_kvargs_free(kvlist);
 861                 return;
 862         }
 863         rte_kvargs_free(kvlist);
 864 }
 865
 866 static int
 867 i40e_check_floating_handler(__rte_unused const char *key,
 868                             const char *value,
 869                             __rte_unused void *opaque)
 870 {
 871         if (strcmp(value, "1"))
 872                 return -1;
 873
 874         return 0;
 875 }
 876
 877 static int
 878 is_floating_veb_supported(struct rte_devargs *devargs)
 879 {
 880         struct rte_kvargs *kvlist;
 881         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 882
 883         if (devargs == NULL)
 884                 return 0;
 885
 886         kvlist = rte_kvargs_parse(devargs->args, NULL);
 887         if (kvlist == NULL)
 888                 return 0;
 889
 890         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 891                 rte_kvargs_free(kvlist);
 892                 return 0;
 893         }
 894         /* Floating VEB is enabled when there's key-value:
 895          * enable_floating_veb=1
 896          */
 897         if (rte_kvargs_process(kvlist, floating_veb_key,
 898                                i40e_check_floating_handler, NULL) < 0) {
 899                 rte_kvargs_free(kvlist);
 900                 return 0;
 901         }
 902         rte_kvargs_free(kvlist);
 903
 904         return 1;
 905 }
 906
 907 static void
 908 config_floating_veb(struct rte_eth_dev *dev)
 909 {
 910         struct rte_pci_device *pci_dev = dev->pci_dev;
 911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 913
 914         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 915
 916         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 917                 pf->floating_veb =
 918                         is_floating_veb_supported(pci_dev->device.devargs);
 919                 config_vf_floating_veb(pci_dev->device.devargs,
 920                                        pf->floating_veb,
 921                                        pf->floating_veb_list);
 922         } else {
 923                 pf->floating_veb = false;
 924         }
 925 }
 926
 927 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 928 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 929
 930 static int
 931 eth_i40e_dev_init(struct rte_eth_dev *dev)
 932 {
 933         struct rte_pci_device *pci_dev;
 934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         struct i40e_vsi *vsi;
 937         int ret;
 938         uint32_t len;
 939         uint8_t aq_fail = 0;
 940
 941         PMD_INIT_FUNC_TRACE();
 942
 943         dev->dev_ops = &i40e_eth_dev_ops;
 944         dev->rx_pkt_burst = i40e_recv_pkts;
 945         dev->tx_pkt_burst = i40e_xmit_pkts;
 946
 947         /* for secondary processes, we don't initialise any further as primary
 948          * has already done this work. Only check we don't need a different
 949          * RX function */
 950         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 951                 i40e_set_rx_function(dev);
 952                 i40e_set_tx_function(dev);
 953                 return 0;
 954         }
 955         pci_dev = dev->pci_dev;
 956
 957         rte_eth_copy_pci_info(dev, pci_dev);
 958
 959         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 960         pf->adapter->eth_dev = dev;
 961         pf->dev_data = dev->data;
 962
 963         hw->back = I40E_PF_TO_ADAPTER(pf);
 964         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 965         if (!hw->hw_addr) {
 966                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 967                              "as address is NULL");
 968                 return -ENODEV;
 969         }
 970
 971         hw->vendor_id = pci_dev->id.vendor_id;
 972         hw->device_id = pci_dev->id.device_id;
 973         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 974         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 975         hw->bus.device = pci_dev->addr.devid;
 976         hw->bus.func = pci_dev->addr.function;
 977         hw->adapter_stopped = 0;
 978
 979         /* Make sure all is clean before doing PF reset */
 980         i40e_clear_hw(hw);
 981
 982         /* Initialize the hardware */
 983         i40e_hw_init(dev);
 984
 985         /* Reset here to make sure all is clean for each PF */
 986         ret = i40e_pf_reset(hw);
 987         if (ret) {
 988                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 989                 return ret;
 990         }
 991
 992         /* Initialize the shared code (base driver) */
 993         ret = i40e_init_shared_code(hw);
 994         if (ret) {
 995                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 996                 return ret;
 997         }
 998
 999         /*
1000          * To work around the NVM issue, initialize registers
1001          * for flexible payload and packet type of QinQ by
1002          * software. It should be removed once issues are fixed
1003          * in NVM.
1004          */
1005         i40e_GLQF_reg_init(hw);
1006
1007         /* Initialize the input set for filters (hash and fd) to default value */
1008         i40e_filter_input_set_init(pf);
1009
1010         /* Initialize the parameters for adminq */
1011         i40e_init_adminq_parameter(hw);
1012         ret = i40e_init_adminq(hw);
1013         if (ret != I40E_SUCCESS) {
1014                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1015                 return -EIO;
1016         }
1017         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1018                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1019                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1020                      ((hw->nvm.version >> 12) & 0xf),
1021                      ((hw->nvm.version >> 4) & 0xff),
1022                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1023
1024         /* Need the special FW version to support floating VEB */
1025         config_floating_veb(dev);
1026         /* Clear PXE mode */
1027         i40e_clear_pxe_mode(hw);
1028         ret = i40e_dev_sync_phy_type(hw);
1029         if (ret) {
1030                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1031                 goto err_sync_phy_type;
1032         }
1033         /*
1034          * On X710, performance number is far from the expectation on recent
1035          * firmware versions. The fix for this issue may not be integrated in
1036          * the following firmware version. So the workaround in software driver
1037          * is needed. It needs to modify the initial values of 3 internal only
1038          * registers. Note that the workaround can be removed when it is fixed
1039          * in firmware in the future.
1040          */
1041         i40e_configure_registers(hw);
1042
1043         /* Get hw capabilities */
1044         ret = i40e_get_cap(hw);
1045         if (ret != I40E_SUCCESS) {
1046                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1047                 goto err_get_capabilities;
1048         }
1049
1050         /* Initialize parameters for PF */
1051         ret = i40e_pf_parameter_init(dev);
1052         if (ret != 0) {
1053                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1054                 goto err_parameter_init;
1055         }
1056
1057         /* Initialize the queue management */
1058         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1059         if (ret < 0) {
1060                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1061                 goto err_qp_pool_init;
1062         }
1063         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1064                                 hw->func_caps.num_msix_vectors - 1);
1065         if (ret < 0) {
1066                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1067                 goto err_msix_pool_init;
1068         }
1069
1070         /* Initialize lan hmc */
1071         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1072                                 hw->func_caps.num_rx_qp, 0, 0);
1073         if (ret != I40E_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1075                 goto err_init_lan_hmc;
1076         }
1077
1078         /* Configure lan hmc */
1079         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1080         if (ret != I40E_SUCCESS) {
1081                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1082                 goto err_configure_lan_hmc;
1083         }
1084
1085         /* Get and check the mac address */
1086         i40e_get_mac_addr(hw, hw->mac.addr);
1087         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "mac address is not valid");
1089                 ret = -EIO;
1090                 goto err_get_mac_addr;
1091         }
1092         /* Copy the permanent MAC address */
1093         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1094                         (struct ether_addr *) hw->mac.perm_addr);
1095
1096         /* Disable flow control */
1097         hw->fc.requested_mode = I40E_FC_NONE;
1098         i40e_set_fc(hw, &aq_fail, TRUE);
1099
1100         /* Set the global registers with default ether type value */
1101         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1102         if (ret != I40E_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1104                              "VLAN ether type");
1105                 goto err_setup_pf_switch;
1106         }
1107
1108         /* PF setup, which includes VSI setup */
1109         ret = i40e_pf_setup(pf);
1110         if (ret) {
1111                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1112                 goto err_setup_pf_switch;
1113         }
1114
1115         /* reset all stats of the device, including pf and main vsi */
1116         i40e_dev_stats_reset(dev);
1117
1118         vsi = pf->main_vsi;
1119
1120         /* Disable double vlan by default */
1121         i40e_vsi_config_double_vlan(vsi, FALSE);
1122
1123         /* Disable S-TAG identification when floating_veb is disabled */
1124         if (!pf->floating_veb) {
1125                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1126                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1127                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1128                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1129                 }
1130         }
1131
1132         if (!vsi->max_macaddrs)
1133                 len = ETHER_ADDR_LEN;
1134         else
1135                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1136
1137         /* Should be after VSI initialized */
1138         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1139         if (!dev->data->mac_addrs) {
1140                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1141                                         "for storing mac address");
1142                 goto err_mac_alloc;
1143         }
1144         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1145                                         &dev->data->mac_addrs[0]);
1146
1147         /* initialize pf host driver to setup SRIOV resource if applicable */
1148         i40e_pf_host_init(dev);
1149
1150         /* register callback func to eal lib */
1151         rte_intr_callback_register(&(pci_dev->intr_handle),
1152                 i40e_dev_interrupt_handler, (void *)dev);
1153
1154         /* configure and enable device interrupt */
1155         i40e_pf_config_irq0(hw, TRUE);
1156         i40e_pf_enable_irq0(hw);
1157
1158         /* enable uio intr after callback register */
1159         rte_intr_enable(&(pci_dev->intr_handle));
1160         /*
1161          * Add an ethertype filter to drop all flow control frames transmitted
1162          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1163          * frames to wire.
1164          */
1165         i40e_add_tx_flow_control_drop_filter(pf);
1166
1167         /* Set the max frame size to 0x2600 by default,
1168          * in case other drivers changed the default value.
1169          */
1170         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1171
1172         /* initialize mirror rule list */
1173         TAILQ_INIT(&pf->mirror_list);
1174
1175         /* Init dcb to sw mode by default */
1176         ret = i40e_dcb_init_configure(dev, TRUE);
1177         if (ret != I40E_SUCCESS) {
1178                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1179                 pf->flags &= ~I40E_FLAG_DCB;
1180         }
1181
1182         return 0;
1183
1184 err_mac_alloc:
1185         i40e_vsi_release(pf->main_vsi);
1186 err_setup_pf_switch:
1187 err_get_mac_addr:
1188 err_configure_lan_hmc:
1189         (void)i40e_shutdown_lan_hmc(hw);
1190 err_init_lan_hmc:
1191         i40e_res_pool_destroy(&pf->msix_pool);
1192 err_msix_pool_init:
1193         i40e_res_pool_destroy(&pf->qp_pool);
1194 err_qp_pool_init:
1195 err_parameter_init:
1196 err_get_capabilities:
1197 err_sync_phy_type:
1198         (void)i40e_shutdown_adminq(hw);
1199
1200         return ret;
1201 }
1202
1203 static int
1204 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1205 {
1206         struct rte_pci_device *pci_dev;
1207         struct i40e_hw *hw;
1208         struct i40e_filter_control_settings settings;
1209         int ret;
1210         uint8_t aq_fail = 0;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1215                 return 0;
1216
1217         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218         pci_dev = dev->pci_dev;
1219
1220         if (hw->adapter_stopped == 0)
1221                 i40e_dev_close(dev);
1222
1223         dev->dev_ops = NULL;
1224         dev->rx_pkt_burst = NULL;
1225         dev->tx_pkt_burst = NULL;
1226
1227         /* Clear PXE mode */
1228         i40e_clear_pxe_mode(hw);
1229
1230         /* Unconfigure filter control */
1231         memset(&settings, 0, sizeof(settings));
1232         ret = i40e_set_filter_control(hw, &settings);
1233         if (ret)
1234                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1235                                         ret);
1236
1237         /* Disable flow control */
1238         hw->fc.requested_mode = I40E_FC_NONE;
1239         i40e_set_fc(hw, &aq_fail, TRUE);
1240
1241         /* uninitialize pf host driver */
1242         i40e_pf_host_uninit(dev);
1243
1244         rte_free(dev->data->mac_addrs);
1245         dev->data->mac_addrs = NULL;
1246
1247         /* disable uio intr before callback unregister */
1248         rte_intr_disable(&(pci_dev->intr_handle));
1249
1250         /* register callback func to eal lib */
1251         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1252                 i40e_dev_interrupt_handler, (void *)dev);
1253
1254         return 0;
1255 }
1256
1257 static int
1258 i40e_dev_configure(struct rte_eth_dev *dev)
1259 {
1260         struct i40e_adapter *ad =
1261                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1262         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1263         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1264         int i, ret;
1265
1266         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1267          * bulk allocation or vector Rx preconditions we will reset it.
1268          */
1269         ad->rx_bulk_alloc_allowed = true;
1270         ad->rx_vec_allowed = true;
1271         ad->tx_simple_allowed = true;
1272         ad->tx_vec_allowed = true;
1273
1274         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1275                 ret = i40e_fdir_setup(pf);
1276                 if (ret != I40E_SUCCESS) {
1277                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1278                         return -ENOTSUP;
1279                 }
1280                 ret = i40e_fdir_configure(dev);
1281                 if (ret < 0) {
1282                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1283                         goto err;
1284                 }
1285         } else
1286                 i40e_fdir_teardown(pf);
1287
1288         ret = i40e_dev_init_vlan(dev);
1289         if (ret < 0)
1290                 goto err;
1291
1292         /* VMDQ setup.
1293          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1294          *  RSS setting have different requirements.
1295          *  General PMD driver call sequence are NIC init, configure,
1296          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1297          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1298          *  applicable. So, VMDQ setting has to be done before
1299          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1300          *  For RSS setting, it will try to calculate actual configured RX queue
1301          *  number, which will be available after rx_queue_setup(). dev_start()
1302          *  function is good to place RSS setup.
1303          */
1304         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1305                 ret = i40e_vmdq_setup(dev);
1306                 if (ret)
1307                         goto err;
1308         }
1309
1310         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1311                 ret = i40e_dcb_setup(dev);
1312                 if (ret) {
1313                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1314                         goto err_dcb;
1315                 }
1316         }
1317
1318         return 0;
1319
1320 err_dcb:
1321         /* need to release vmdq resource if exists */
1322         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1323                 i40e_vsi_release(pf->vmdq[i].vsi);
1324                 pf->vmdq[i].vsi = NULL;
1325         }
1326         rte_free(pf->vmdq);
1327         pf->vmdq = NULL;
1328 err:
1329         /* need to release fdir resource if exists */
1330         i40e_fdir_teardown(pf);
1331         return ret;
1332 }
1333
1334 void
1335 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1336 {
1337         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1338         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1339         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1340         uint16_t msix_vect = vsi->msix_intr;
1341         uint16_t i;
1342
1343         for (i = 0; i < vsi->nb_qps; i++) {
1344                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1345                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1346                 rte_wmb();
1347         }
1348
1349         if (vsi->type != I40E_VSI_SRIOV) {
1350                 if (!rte_intr_allow_others(intr_handle)) {
1351                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1352                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1353                         I40E_WRITE_REG(hw,
1354                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1355                                        0);
1356                 } else {
1357                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1358                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1359                         I40E_WRITE_REG(hw,
1360                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1361                                                        msix_vect - 1), 0);
1362                 }
1363         } else {
1364                 uint32_t reg;
1365                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1366                         vsi->user_param + (msix_vect - 1);
1367
1368                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1369                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1370         }
1371         I40E_WRITE_FLUSH(hw);
1372 }
1373
1374 static void
1375 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1376                        int base_queue, int nb_queue)
1377 {
1378         int i;
1379         uint32_t val;
1380         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1381
1382         /* Bind all RX queues to allocated MSIX interrupt */
1383         for (i = 0; i < nb_queue; i++) {
1384                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1385                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1386                         ((base_queue + i + 1) <<
1387                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1388                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1389                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1390
1391                 if (i == nb_queue - 1)
1392                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1393                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1394         }
1395
1396         /* Write first RX queue to Link list register as the head element */
1397         if (vsi->type != I40E_VSI_SRIOV) {
1398                 uint16_t interval =
1399                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1400
1401                 if (msix_vect == I40E_MISC_VEC_ID) {
1402                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1403                                        (base_queue <<
1404                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1405                                        (0x0 <<
1406                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1407                         I40E_WRITE_REG(hw,
1408                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1409                                        interval);
1410                 } else {
1411                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1412                                        (base_queue <<
1413                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1414                                        (0x0 <<
1415                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1416                         I40E_WRITE_REG(hw,
1417                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1418                                                        msix_vect - 1),
1419                                        interval);
1420                 }
1421         } else {
1422                 uint32_t reg;
1423
1424                 if (msix_vect == I40E_MISC_VEC_ID) {
1425                         I40E_WRITE_REG(hw,
1426                                        I40E_VPINT_LNKLST0(vsi->user_param),
1427                                        (base_queue <<
1428                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1429                                        (0x0 <<
1430                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1431                 } else {
1432                         /* num_msix_vectors_vf needs to minus irq0 */
1433                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1434                                 vsi->user_param + (msix_vect - 1);
1435
1436                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1437                                        (base_queue <<
1438                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1439                                        (0x0 <<
1440                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1441                 }
1442         }
1443
1444         I40E_WRITE_FLUSH(hw);
1445 }
1446
1447 void
1448 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1449 {
1450         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1451         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1452         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1453         uint16_t msix_vect = vsi->msix_intr;
1454         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1455         uint16_t queue_idx = 0;
1456         int record = 0;
1457         uint32_t val;
1458         int i;
1459
1460         for (i = 0; i < vsi->nb_qps; i++) {
1461                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1462                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1463         }
1464
1465         /* INTENA flag is not auto-cleared for interrupt */
1466         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1467         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1468                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1469                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1470         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1471
1472         /* VF bind interrupt */
1473         if (vsi->type == I40E_VSI_SRIOV) {
1474                 __vsi_queues_bind_intr(vsi, msix_vect,
1475                                        vsi->base_queue, vsi->nb_qps);
1476                 return;
1477         }
1478
1479         /* PF & VMDq bind interrupt */
1480         if (rte_intr_dp_is_en(intr_handle)) {
1481                 if (vsi->type == I40E_VSI_MAIN) {
1482                         queue_idx = 0;
1483                         record = 1;
1484                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1485                         struct i40e_vsi *main_vsi =
1486                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1487                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1488                         record = 1;
1489                 }
1490         }
1491
1492         for (i = 0; i < vsi->nb_used_qps; i++) {
1493                 if (nb_msix <= 1) {
1494                         if (!rte_intr_allow_others(intr_handle))
1495                                 /* allow to share MISC_VEC_ID */
1496                                 msix_vect = I40E_MISC_VEC_ID;
1497
1498                         /* no enough msix_vect, map all to one */
1499                         __vsi_queues_bind_intr(vsi, msix_vect,
1500                                                vsi->base_queue + i,
1501                                                vsi->nb_used_qps - i);
1502                         for (; !!record && i < vsi->nb_used_qps; i++)
1503                                 intr_handle->intr_vec[queue_idx + i] =
1504                                         msix_vect;
1505                         break;
1506                 }
1507                 /* 1:1 queue/msix_vect mapping */
1508                 __vsi_queues_bind_intr(vsi, msix_vect,
1509                                        vsi->base_queue + i, 1);
1510                 if (!!record)
1511                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1512
1513                 msix_vect++;
1514                 nb_msix--;
1515         }
1516 }
1517
1518 static void
1519 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1520 {
1521         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1522         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1524         uint16_t interval = i40e_calc_itr_interval(\
1525                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1526         uint16_t msix_intr, i;
1527
1528         if (rte_intr_allow_others(intr_handle))
1529                 for (i = 0; i < vsi->nb_msix; i++) {
1530                         msix_intr = vsi->msix_intr + i;
1531                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1532                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1533                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1534                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1535                                 (interval <<
1536                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1537                 }
1538         else
1539                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1540                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1541                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1542                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1543                                (interval <<
1544                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1545
1546         I40E_WRITE_FLUSH(hw);
1547 }
1548
1549 static void
1550 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1551 {
1552         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1553         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1554         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1555         uint16_t msix_intr, i;
1556
1557         if (rte_intr_allow_others(intr_handle))
1558                 for (i = 0; i < vsi->nb_msix; i++) {
1559                         msix_intr = vsi->msix_intr + i;
1560                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1561                                        0);
1562                 }
1563         else
1564                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1565
1566         I40E_WRITE_FLUSH(hw);
1567 }
1568
1569 static inline uint8_t
1570 i40e_parse_link_speeds(uint16_t link_speeds)
1571 {
1572         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1573
1574         if (link_speeds & ETH_LINK_SPEED_40G)
1575                 link_speed |= I40E_LINK_SPEED_40GB;
1576         if (link_speeds & ETH_LINK_SPEED_25G)
1577                 link_speed |= I40E_LINK_SPEED_25GB;
1578         if (link_speeds & ETH_LINK_SPEED_20G)
1579                 link_speed |= I40E_LINK_SPEED_20GB;
1580         if (link_speeds & ETH_LINK_SPEED_10G)
1581                 link_speed |= I40E_LINK_SPEED_10GB;
1582         if (link_speeds & ETH_LINK_SPEED_1G)
1583                 link_speed |= I40E_LINK_SPEED_1GB;
1584         if (link_speeds & ETH_LINK_SPEED_100M)
1585                 link_speed |= I40E_LINK_SPEED_100MB;
1586
1587         return link_speed;
1588 }
1589
1590 static int
1591 i40e_phy_conf_link(struct i40e_hw *hw,
1592                    uint8_t abilities,
1593                    uint8_t force_speed)
1594 {
1595         enum i40e_status_code status;
1596         struct i40e_aq_get_phy_abilities_resp phy_ab;
1597         struct i40e_aq_set_phy_config phy_conf;
1598         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1599                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1600                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1601                         I40E_AQ_PHY_FLAG_LOW_POWER;
1602         const uint8_t advt = I40E_LINK_SPEED_40GB |
1603                         I40E_LINK_SPEED_25GB |
1604                         I40E_LINK_SPEED_10GB |
1605                         I40E_LINK_SPEED_1GB |
1606                         I40E_LINK_SPEED_100MB;
1607         int ret = -ENOTSUP;
1608
1609
1610         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1611                                               NULL);
1612         if (status)
1613                 return ret;
1614
1615         memset(&phy_conf, 0, sizeof(phy_conf));
1616
1617         /* bits 0-2 use the values from get_phy_abilities_resp */
1618         abilities &= ~mask;
1619         abilities |= phy_ab.abilities & mask;
1620
1621         /* update ablities and speed */
1622         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1623                 phy_conf.link_speed = advt;
1624         else
1625                 phy_conf.link_speed = force_speed;
1626
1627         phy_conf.abilities = abilities;
1628
1629         /* use get_phy_abilities_resp value for the rest */
1630         phy_conf.phy_type = phy_ab.phy_type;
1631         phy_conf.eee_capability = phy_ab.eee_capability;
1632         phy_conf.eeer = phy_ab.eeer_val;
1633         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1634
1635         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1636                     phy_ab.abilities, phy_ab.link_speed);
1637         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1638                     phy_conf.abilities, phy_conf.link_speed);
1639
1640         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1641         if (status)
1642                 return ret;
1643
1644         return I40E_SUCCESS;
1645 }
1646
1647 static int
1648 i40e_apply_link_speed(struct rte_eth_dev *dev)
1649 {
1650         uint8_t speed;
1651         uint8_t abilities = 0;
1652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         struct rte_eth_conf *conf = &dev->data->dev_conf;
1654
1655         speed = i40e_parse_link_speeds(conf->link_speeds);
1656         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1657                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1658         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1659                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1660         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1661
1662         /* Skip changing speed on 40G interfaces, FW does not support */
1663         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1664                 speed =  I40E_LINK_SPEED_UNKNOWN;
1665                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1666         }
1667
1668         return i40e_phy_conf_link(hw, abilities, speed);
1669 }
1670
1671 static int
1672 i40e_dev_start(struct rte_eth_dev *dev)
1673 {
1674         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1676         struct i40e_vsi *main_vsi = pf->main_vsi;
1677         int ret, i;
1678         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1679         uint32_t intr_vector = 0;
1680
1681         hw->adapter_stopped = 0;
1682
1683         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1684                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1685                              dev->data->port_id);
1686                 return -EINVAL;
1687         }
1688
1689         rte_intr_disable(intr_handle);
1690
1691         if ((rte_intr_cap_multiple(intr_handle) ||
1692              !RTE_ETH_DEV_SRIOV(dev).active) &&
1693             dev->data->dev_conf.intr_conf.rxq != 0) {
1694                 intr_vector = dev->data->nb_rx_queues;
1695                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1696                         return -1;
1697         }
1698
1699         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1700                 intr_handle->intr_vec =
1701                         rte_zmalloc("intr_vec",
1702                                     dev->data->nb_rx_queues * sizeof(int),
1703                                     0);
1704                 if (!intr_handle->intr_vec) {
1705                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1706                                      " intr_vec\n", dev->data->nb_rx_queues);
1707                         return -ENOMEM;
1708                 }
1709         }
1710
1711         /* Initialize VSI */
1712         ret = i40e_dev_rxtx_init(pf);
1713         if (ret != I40E_SUCCESS) {
1714                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1715                 goto err_up;
1716         }
1717
1718         /* Map queues with MSIX interrupt */
1719         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1720                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1721         i40e_vsi_queues_bind_intr(main_vsi);
1722         i40e_vsi_enable_queues_intr(main_vsi);
1723
1724         /* Map VMDQ VSI queues with MSIX interrupt */
1725         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1726                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1727                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1728                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1729         }
1730
1731         /* enable FDIR MSIX interrupt */
1732         if (pf->fdir.fdir_vsi) {
1733                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1734                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1735         }
1736
1737         /* Enable all queues which have been configured */
1738         ret = i40e_dev_switch_queues(pf, TRUE);
1739         if (ret != I40E_SUCCESS) {
1740                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1741                 goto err_up;
1742         }
1743
1744         /* Enable receiving broadcast packets */
1745         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1746         if (ret != I40E_SUCCESS)
1747                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1748
1749         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1750                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1751                                                 true, NULL);
1752                 if (ret != I40E_SUCCESS)
1753                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1754         }
1755
1756         /* Apply link configure */
1757         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1758                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1759                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1760                                 ETH_LINK_SPEED_40G)) {
1761                 PMD_DRV_LOG(ERR, "Invalid link setting");
1762                 goto err_up;
1763         }
1764         ret = i40e_apply_link_speed(dev);
1765         if (I40E_SUCCESS != ret) {
1766                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1767                 goto err_up;
1768         }
1769
1770         if (!rte_intr_allow_others(intr_handle)) {
1771                 rte_intr_callback_unregister(intr_handle,
1772                                              i40e_dev_interrupt_handler,
1773                                              (void *)dev);
1774                 /* configure and enable device interrupt */
1775                 i40e_pf_config_irq0(hw, FALSE);
1776                 i40e_pf_enable_irq0(hw);
1777
1778                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1779                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1780                                      " no intr multiplex\n");
1781         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1782                 ret = i40e_aq_set_phy_int_mask(hw,
1783                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1784                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1785                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1786                 if (ret != I40E_SUCCESS)
1787                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1788
1789                 /* Call get_link_info aq commond to enable LSE */
1790                 i40e_dev_link_update(dev, 0);
1791         }
1792
1793         /* enable uio intr after callback register */
1794         rte_intr_enable(intr_handle);
1795
1796         return I40E_SUCCESS;
1797
1798 err_up:
1799         i40e_dev_switch_queues(pf, FALSE);
1800         i40e_dev_clear_queues(dev);
1801
1802         return ret;
1803 }
1804
1805 static void
1806 i40e_dev_stop(struct rte_eth_dev *dev)
1807 {
1808         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1809         struct i40e_vsi *main_vsi = pf->main_vsi;
1810         struct i40e_mirror_rule *p_mirror;
1811         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1812         int i;
1813
1814         /* Disable all queues */
1815         i40e_dev_switch_queues(pf, FALSE);
1816
1817         /* un-map queues with interrupt registers */
1818         i40e_vsi_disable_queues_intr(main_vsi);
1819         i40e_vsi_queues_unbind_intr(main_vsi);
1820
1821         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1822                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1823                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1824         }
1825
1826         if (pf->fdir.fdir_vsi) {
1827                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1828                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1829         }
1830         /* Clear all queues and release memory */
1831         i40e_dev_clear_queues(dev);
1832
1833         /* Set link down */
1834         i40e_dev_set_link_down(dev);
1835
1836         /* Remove all mirror rules */
1837         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1838                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1839                 rte_free(p_mirror);
1840         }
1841         pf->nb_mirror_rule = 0;
1842
1843         if (!rte_intr_allow_others(intr_handle))
1844                 /* resume to the default handler */
1845                 rte_intr_callback_register(intr_handle,
1846                                            i40e_dev_interrupt_handler,
1847                                            (void *)dev);
1848
1849         /* Clean datapath event and queue/vec mapping */
1850         rte_intr_efd_disable(intr_handle);
1851         if (intr_handle->intr_vec) {
1852                 rte_free(intr_handle->intr_vec);
1853                 intr_handle->intr_vec = NULL;
1854         }
1855 }
1856
1857 static void
1858 i40e_dev_close(struct rte_eth_dev *dev)
1859 {
1860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862         uint32_t reg;
1863         int i;
1864
1865         PMD_INIT_FUNC_TRACE();
1866
1867         i40e_dev_stop(dev);
1868         hw->adapter_stopped = 1;
1869         i40e_dev_free_queues(dev);
1870
1871         /* Disable interrupt */
1872         i40e_pf_disable_irq0(hw);
1873         rte_intr_disable(&(dev->pci_dev->intr_handle));
1874
1875         /* shutdown and destroy the HMC */
1876         i40e_shutdown_lan_hmc(hw);
1877
1878         /* release all the existing VSIs and VEBs */
1879         i40e_fdir_teardown(pf);
1880         i40e_vsi_release(pf->main_vsi);
1881
1882         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1883                 i40e_vsi_release(pf->vmdq[i].vsi);
1884                 pf->vmdq[i].vsi = NULL;
1885         }
1886
1887         rte_free(pf->vmdq);
1888         pf->vmdq = NULL;
1889
1890         /* shutdown the adminq */
1891         i40e_aq_queue_shutdown(hw, true);
1892         i40e_shutdown_adminq(hw);
1893
1894         i40e_res_pool_destroy(&pf->qp_pool);
1895         i40e_res_pool_destroy(&pf->msix_pool);
1896
1897         /* force a PF reset to clean anything leftover */
1898         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1899         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1900                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1901         I40E_WRITE_FLUSH(hw);
1902 }
1903
1904 static void
1905 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_vsi *vsi = pf->main_vsi;
1910         int status;
1911
1912         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1913                                                      true, NULL, true);
1914         if (status != I40E_SUCCESS)
1915                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1916
1917         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1918                                                         TRUE, NULL);
1919         if (status != I40E_SUCCESS)
1920                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1921
1922 }
1923
1924 static void
1925 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1926 {
1927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct i40e_vsi *vsi = pf->main_vsi;
1930         int status;
1931
1932         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1933                                                      false, NULL, true);
1934         if (status != I40E_SUCCESS)
1935                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1936
1937         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1938                                                         false, NULL);
1939         if (status != I40E_SUCCESS)
1940                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1941 }
1942
1943 static void
1944 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1945 {
1946         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1947         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         struct i40e_vsi *vsi = pf->main_vsi;
1949         int ret;
1950
1951         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1952         if (ret != I40E_SUCCESS)
1953                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1954 }
1955
1956 static void
1957 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1958 {
1959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         struct i40e_vsi *vsi = pf->main_vsi;
1962         int ret;
1963
1964         if (dev->data->promiscuous == 1)
1965                 return; /* must remain in all_multicast mode */
1966
1967         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1968                                 vsi->seid, FALSE, NULL);
1969         if (ret != I40E_SUCCESS)
1970                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1971 }
1972
1973 /*
1974  * Set device link up.
1975  */
1976 static int
1977 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1978 {
1979         /* re-apply link speed setting */
1980         return i40e_apply_link_speed(dev);
1981 }
1982
1983 /*
1984  * Set device link down.
1985  */
1986 static int
1987 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1988 {
1989         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1990         uint8_t abilities = 0;
1991         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992
1993         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1994                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1995         return i40e_phy_conf_link(hw, abilities, speed);
1996 }
1997
1998 int
1999 i40e_dev_link_update(struct rte_eth_dev *dev,
2000                      int wait_to_complete)
2001 {
2002 #define CHECK_INTERVAL 100  /* 100ms */
2003 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2004         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005         struct i40e_link_status link_status;
2006         struct rte_eth_link link, old;
2007         int status;
2008         unsigned rep_cnt = MAX_REPEAT_TIME;
2009         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2010
2011         memset(&link, 0, sizeof(link));
2012         memset(&old, 0, sizeof(old));
2013         memset(&link_status, 0, sizeof(link_status));
2014         rte_i40e_dev_atomic_read_link_status(dev, &old);
2015
2016         do {
2017                 /* Get link status information from hardware */
2018                 status = i40e_aq_get_link_info(hw, enable_lse,
2019                                                 &link_status, NULL);
2020                 if (status != I40E_SUCCESS) {
2021                         link.link_speed = ETH_SPEED_NUM_100M;
2022                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2023                         PMD_DRV_LOG(ERR, "Failed to get link info");
2024                         goto out;
2025                 }
2026
2027                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2028                 if (!wait_to_complete)
2029                         break;
2030
2031                 rte_delay_ms(CHECK_INTERVAL);
2032         } while (!link.link_status && rep_cnt--);
2033
2034         if (!link.link_status)
2035                 goto out;
2036
2037         /* i40e uses full duplex only */
2038         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2039
2040         /* Parse the link status */
2041         switch (link_status.link_speed) {
2042         case I40E_LINK_SPEED_100MB:
2043                 link.link_speed = ETH_SPEED_NUM_100M;
2044                 break;
2045         case I40E_LINK_SPEED_1GB:
2046                 link.link_speed = ETH_SPEED_NUM_1G;
2047                 break;
2048         case I40E_LINK_SPEED_10GB:
2049                 link.link_speed = ETH_SPEED_NUM_10G;
2050                 break;
2051         case I40E_LINK_SPEED_20GB:
2052                 link.link_speed = ETH_SPEED_NUM_20G;
2053                 break;
2054         case I40E_LINK_SPEED_25GB:
2055                 link.link_speed = ETH_SPEED_NUM_25G;
2056                 break;
2057         case I40E_LINK_SPEED_40GB:
2058                 link.link_speed = ETH_SPEED_NUM_40G;
2059                 break;
2060         default:
2061                 link.link_speed = ETH_SPEED_NUM_100M;
2062                 break;
2063         }
2064
2065         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2066                         ETH_LINK_SPEED_FIXED);
2067
2068 out:
2069         rte_i40e_dev_atomic_write_link_status(dev, &link);
2070         if (link.link_status == old.link_status)
2071                 return -1;
2072
2073         return 0;
2074 }
2075
2076 /* Get all the statistics of a VSI */
2077 void
2078 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2079 {
2080         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2081         struct i40e_eth_stats *nes = &vsi->eth_stats;
2082         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2084
2085         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2086                             vsi->offset_loaded, &oes->rx_bytes,
2087                             &nes->rx_bytes);
2088         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2089                             vsi->offset_loaded, &oes->rx_unicast,
2090                             &nes->rx_unicast);
2091         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2092                             vsi->offset_loaded, &oes->rx_multicast,
2093                             &nes->rx_multicast);
2094         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2095                             vsi->offset_loaded, &oes->rx_broadcast,
2096                             &nes->rx_broadcast);
2097         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2098                             &oes->rx_discards, &nes->rx_discards);
2099         /* GLV_REPC not supported */
2100         /* GLV_RMPC not supported */
2101         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2102                             &oes->rx_unknown_protocol,
2103                             &nes->rx_unknown_protocol);
2104         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2105                             vsi->offset_loaded, &oes->tx_bytes,
2106                             &nes->tx_bytes);
2107         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2108                             vsi->offset_loaded, &oes->tx_unicast,
2109                             &nes->tx_unicast);
2110         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2111                             vsi->offset_loaded, &oes->tx_multicast,
2112                             &nes->tx_multicast);
2113         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2114                             vsi->offset_loaded,  &oes->tx_broadcast,
2115                             &nes->tx_broadcast);
2116         /* GLV_TDPC not supported */
2117         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2118                             &oes->tx_errors, &nes->tx_errors);
2119         vsi->offset_loaded = true;
2120
2121         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2122                     vsi->vsi_id);
2123         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2124         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2125         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2126         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2127         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2128         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2129                     nes->rx_unknown_protocol);
2130         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2131         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2132         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2133         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2134         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2135         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2136         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2137                     vsi->vsi_id);
2138 }
2139
2140 static void
2141 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2142 {
2143         unsigned int i;
2144         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2145         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2146
2147         /* Get statistics of struct i40e_eth_stats */
2148         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2149                             I40E_GLPRT_GORCL(hw->port),
2150                             pf->offset_loaded, &os->eth.rx_bytes,
2151                             &ns->eth.rx_bytes);
2152         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2153                             I40E_GLPRT_UPRCL(hw->port),
2154                             pf->offset_loaded, &os->eth.rx_unicast,
2155                             &ns->eth.rx_unicast);
2156         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2157                             I40E_GLPRT_MPRCL(hw->port),
2158                             pf->offset_loaded, &os->eth.rx_multicast,
2159                             &ns->eth.rx_multicast);
2160         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2161                             I40E_GLPRT_BPRCL(hw->port),
2162                             pf->offset_loaded, &os->eth.rx_broadcast,
2163                             &ns->eth.rx_broadcast);
2164         /* Workaround: CRC size should not be included in byte statistics,
2165          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2166          */
2167         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2168                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2169
2170         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2171                             pf->offset_loaded, &os->eth.rx_discards,
2172                             &ns->eth.rx_discards);
2173         /* GLPRT_REPC not supported */
2174         /* GLPRT_RMPC not supported */
2175         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2176                             pf->offset_loaded,
2177                             &os->eth.rx_unknown_protocol,
2178                             &ns->eth.rx_unknown_protocol);
2179         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2180                             I40E_GLPRT_GOTCL(hw->port),
2181                             pf->offset_loaded, &os->eth.tx_bytes,
2182                             &ns->eth.tx_bytes);
2183         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2184                             I40E_GLPRT_UPTCL(hw->port),
2185                             pf->offset_loaded, &os->eth.tx_unicast,
2186                             &ns->eth.tx_unicast);
2187         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2188                             I40E_GLPRT_MPTCL(hw->port),
2189                             pf->offset_loaded, &os->eth.tx_multicast,
2190                             &ns->eth.tx_multicast);
2191         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2192                             I40E_GLPRT_BPTCL(hw->port),
2193                             pf->offset_loaded, &os->eth.tx_broadcast,
2194                             &ns->eth.tx_broadcast);
2195         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2196                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2197         /* GLPRT_TEPC not supported */
2198
2199         /* additional port specific stats */
2200         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2201                             pf->offset_loaded, &os->tx_dropped_link_down,
2202                             &ns->tx_dropped_link_down);
2203         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2204                             pf->offset_loaded, &os->crc_errors,
2205                             &ns->crc_errors);
2206         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2207                             pf->offset_loaded, &os->illegal_bytes,
2208                             &ns->illegal_bytes);
2209         /* GLPRT_ERRBC not supported */
2210         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2211                             pf->offset_loaded, &os->mac_local_faults,
2212                             &ns->mac_local_faults);
2213         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2214                             pf->offset_loaded, &os->mac_remote_faults,
2215                             &ns->mac_remote_faults);
2216         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2217                             pf->offset_loaded, &os->rx_length_errors,
2218                             &ns->rx_length_errors);
2219         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2220                             pf->offset_loaded, &os->link_xon_rx,
2221                             &ns->link_xon_rx);
2222         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2223                             pf->offset_loaded, &os->link_xoff_rx,
2224                             &ns->link_xoff_rx);
2225         for (i = 0; i < 8; i++) {
2226                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2227                                     pf->offset_loaded,
2228                                     &os->priority_xon_rx[i],
2229                                     &ns->priority_xon_rx[i]);
2230                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2231                                     pf->offset_loaded,
2232                                     &os->priority_xoff_rx[i],
2233                                     &ns->priority_xoff_rx[i]);
2234         }
2235         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2236                             pf->offset_loaded, &os->link_xon_tx,
2237                             &ns->link_xon_tx);
2238         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2239                             pf->offset_loaded, &os->link_xoff_tx,
2240                             &ns->link_xoff_tx);
2241         for (i = 0; i < 8; i++) {
2242                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2243                                     pf->offset_loaded,
2244                                     &os->priority_xon_tx[i],
2245                                     &ns->priority_xon_tx[i]);
2246                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2247                                     pf->offset_loaded,
2248                                     &os->priority_xoff_tx[i],
2249                                     &ns->priority_xoff_tx[i]);
2250                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2251                                     pf->offset_loaded,
2252                                     &os->priority_xon_2_xoff[i],
2253                                     &ns->priority_xon_2_xoff[i]);
2254         }
2255         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2256                             I40E_GLPRT_PRC64L(hw->port),
2257                             pf->offset_loaded, &os->rx_size_64,
2258                             &ns->rx_size_64);
2259         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2260                             I40E_GLPRT_PRC127L(hw->port),
2261                             pf->offset_loaded, &os->rx_size_127,
2262                             &ns->rx_size_127);
2263         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2264                             I40E_GLPRT_PRC255L(hw->port),
2265                             pf->offset_loaded, &os->rx_size_255,
2266                             &ns->rx_size_255);
2267         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2268                             I40E_GLPRT_PRC511L(hw->port),
2269                             pf->offset_loaded, &os->rx_size_511,
2270                             &ns->rx_size_511);
2271         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2272                             I40E_GLPRT_PRC1023L(hw->port),
2273                             pf->offset_loaded, &os->rx_size_1023,
2274                             &ns->rx_size_1023);
2275         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2276                             I40E_GLPRT_PRC1522L(hw->port),
2277                             pf->offset_loaded, &os->rx_size_1522,
2278                             &ns->rx_size_1522);
2279         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2280                             I40E_GLPRT_PRC9522L(hw->port),
2281                             pf->offset_loaded, &os->rx_size_big,
2282                             &ns->rx_size_big);
2283         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2284                             pf->offset_loaded, &os->rx_undersize,
2285                             &ns->rx_undersize);
2286         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2287                             pf->offset_loaded, &os->rx_fragments,
2288                             &ns->rx_fragments);
2289         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2290                             pf->offset_loaded, &os->rx_oversize,
2291                             &ns->rx_oversize);
2292         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2293                             pf->offset_loaded, &os->rx_jabber,
2294                             &ns->rx_jabber);
2295         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2296                             I40E_GLPRT_PTC64L(hw->port),
2297                             pf->offset_loaded, &os->tx_size_64,
2298                             &ns->tx_size_64);
2299         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2300                             I40E_GLPRT_PTC127L(hw->port),
2301                             pf->offset_loaded, &os->tx_size_127,
2302                             &ns->tx_size_127);
2303         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2304                             I40E_GLPRT_PTC255L(hw->port),
2305                             pf->offset_loaded, &os->tx_size_255,
2306                             &ns->tx_size_255);
2307         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2308                             I40E_GLPRT_PTC511L(hw->port),
2309                             pf->offset_loaded, &os->tx_size_511,
2310                             &ns->tx_size_511);
2311         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2312                             I40E_GLPRT_PTC1023L(hw->port),
2313                             pf->offset_loaded, &os->tx_size_1023,
2314                             &ns->tx_size_1023);
2315         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2316                             I40E_GLPRT_PTC1522L(hw->port),
2317                             pf->offset_loaded, &os->tx_size_1522,
2318                             &ns->tx_size_1522);
2319         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2320                             I40E_GLPRT_PTC9522L(hw->port),
2321                             pf->offset_loaded, &os->tx_size_big,
2322                             &ns->tx_size_big);
2323         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2324                            pf->offset_loaded,
2325                            &os->fd_sb_match, &ns->fd_sb_match);
2326         /* GLPRT_MSPDC not supported */
2327         /* GLPRT_XEC not supported */
2328
2329         pf->offset_loaded = true;
2330
2331         if (pf->main_vsi)
2332                 i40e_update_vsi_stats(pf->main_vsi);
2333 }
2334
2335 /* Get all statistics of a port */
2336 static void
2337 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2338 {
2339         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2340         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2342         unsigned i;
2343
2344         /* call read registers - updates values, now write them to struct */
2345         i40e_read_stats_registers(pf, hw);
2346
2347         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2348                         pf->main_vsi->eth_stats.rx_multicast +
2349                         pf->main_vsi->eth_stats.rx_broadcast -
2350                         pf->main_vsi->eth_stats.rx_discards;
2351         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2352                         pf->main_vsi->eth_stats.tx_multicast +
2353                         pf->main_vsi->eth_stats.tx_broadcast;
2354         stats->ibytes   = ns->eth.rx_bytes;
2355         stats->obytes   = ns->eth.tx_bytes;
2356         stats->oerrors  = ns->eth.tx_errors +
2357                         pf->main_vsi->eth_stats.tx_errors;
2358
2359         /* Rx Errors */
2360         stats->imissed  = ns->eth.rx_discards +
2361                         pf->main_vsi->eth_stats.rx_discards;
2362         stats->ierrors  = ns->crc_errors +
2363                         ns->rx_length_errors + ns->rx_undersize +
2364                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2365
2366         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2367         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2368         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2369         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2370         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2371         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2372         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2373                     ns->eth.rx_unknown_protocol);
2374         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2375         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2376         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2377         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2378         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2379         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2380
2381         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2382                     ns->tx_dropped_link_down);
2383         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2384         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2385                     ns->illegal_bytes);
2386         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2387         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2388                     ns->mac_local_faults);
2389         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2390                     ns->mac_remote_faults);
2391         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2392                     ns->rx_length_errors);
2393         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2394         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2395         for (i = 0; i < 8; i++) {
2396                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2397                                 i, ns->priority_xon_rx[i]);
2398                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2399                                 i, ns->priority_xoff_rx[i]);
2400         }
2401         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2402         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2403         for (i = 0; i < 8; i++) {
2404                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2405                                 i, ns->priority_xon_tx[i]);
2406                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2407                                 i, ns->priority_xoff_tx[i]);
2408                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2409                                 i, ns->priority_xon_2_xoff[i]);
2410         }
2411         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2412         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2413         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2414         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2415         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2416         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2417         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2418         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2419         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2420         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2421         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2422         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2423         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2424         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2425         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2426         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2427         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2428         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2429         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2430                         ns->mac_short_packet_dropped);
2431         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2432                     ns->checksum_error);
2433         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2434         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2435 }
2436
2437 /* Reset the statistics */
2438 static void
2439 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2440 {
2441         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2442         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443
2444         /* Mark PF and VSI stats to update the offset, aka "reset" */
2445         pf->offset_loaded = false;
2446         if (pf->main_vsi)
2447                 pf->main_vsi->offset_loaded = false;
2448
2449         /* read the stats, reading current register values into offset */
2450         i40e_read_stats_registers(pf, hw);
2451 }
2452
2453 static uint32_t
2454 i40e_xstats_calc_num(void)
2455 {
2456         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2457                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2458                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2459 }
2460
2461 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2462                                      struct rte_eth_xstat_name *xstats_names,
2463                                      __rte_unused unsigned limit)
2464 {
2465         unsigned count = 0;
2466         unsigned i, prio;
2467
2468         if (xstats_names == NULL)
2469                 return i40e_xstats_calc_num();
2470
2471         /* Note: limit checked in rte_eth_xstats_names() */
2472
2473         /* Get stats from i40e_eth_stats struct */
2474         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2475                 snprintf(xstats_names[count].name,
2476                          sizeof(xstats_names[count].name),
2477                          "%s", rte_i40e_stats_strings[i].name);
2478                 count++;
2479         }
2480
2481         /* Get individiual stats from i40e_hw_port struct */
2482         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2483                 snprintf(xstats_names[count].name,
2484                         sizeof(xstats_names[count].name),
2485                          "%s", rte_i40e_hw_port_strings[i].name);
2486                 count++;
2487         }
2488
2489         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2490                 for (prio = 0; prio < 8; prio++) {
2491                         snprintf(xstats_names[count].name,
2492                                  sizeof(xstats_names[count].name),
2493                                  "rx_priority%u_%s", prio,
2494                                  rte_i40e_rxq_prio_strings[i].name);
2495                         count++;
2496                 }
2497         }
2498
2499         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2500                 for (prio = 0; prio < 8; prio++) {
2501                         snprintf(xstats_names[count].name,
2502                                  sizeof(xstats_names[count].name),
2503                                  "tx_priority%u_%s", prio,
2504                                  rte_i40e_txq_prio_strings[i].name);
2505                         count++;
2506                 }
2507         }
2508         return count;
2509 }
2510
2511 static int
2512 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2513                     unsigned n)
2514 {
2515         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2516         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2517         unsigned i, count, prio;
2518         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2519
2520         count = i40e_xstats_calc_num();
2521         if (n < count)
2522                 return count;
2523
2524         i40e_read_stats_registers(pf, hw);
2525
2526         if (xstats == NULL)
2527                 return 0;
2528
2529         count = 0;
2530
2531         /* Get stats from i40e_eth_stats struct */
2532         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2533                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2534                         rte_i40e_stats_strings[i].offset);
2535                 count++;
2536         }
2537
2538         /* Get individiual stats from i40e_hw_port struct */
2539         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2540                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2541                         rte_i40e_hw_port_strings[i].offset);
2542                 count++;
2543         }
2544
2545         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2546                 for (prio = 0; prio < 8; prio++) {
2547                         xstats[count].value =
2548                                 *(uint64_t *)(((char *)hw_stats) +
2549                                 rte_i40e_rxq_prio_strings[i].offset +
2550                                 (sizeof(uint64_t) * prio));
2551                         count++;
2552                 }
2553         }
2554
2555         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2556                 for (prio = 0; prio < 8; prio++) {
2557                         xstats[count].value =
2558                                 *(uint64_t *)(((char *)hw_stats) +
2559                                 rte_i40e_txq_prio_strings[i].offset +
2560                                 (sizeof(uint64_t) * prio));
2561                         count++;
2562                 }
2563         }
2564
2565         return count;
2566 }
2567
2568 static int
2569 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2570                                  __rte_unused uint16_t queue_id,
2571                                  __rte_unused uint8_t stat_idx,
2572                                  __rte_unused uint8_t is_rx)
2573 {
2574         PMD_INIT_FUNC_TRACE();
2575
2576         return -ENOSYS;
2577 }
2578
2579 static void
2580 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2581 {
2582         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2583         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584         struct i40e_vsi *vsi = pf->main_vsi;
2585
2586         dev_info->max_rx_queues = vsi->nb_qps;
2587         dev_info->max_tx_queues = vsi->nb_qps;
2588         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2589         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2590         dev_info->max_mac_addrs = vsi->max_macaddrs;
2591         dev_info->max_vfs = dev->pci_dev->max_vfs;
2592         dev_info->rx_offload_capa =
2593                 DEV_RX_OFFLOAD_VLAN_STRIP |
2594                 DEV_RX_OFFLOAD_QINQ_STRIP |
2595                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2596                 DEV_RX_OFFLOAD_UDP_CKSUM |
2597                 DEV_RX_OFFLOAD_TCP_CKSUM;
2598         dev_info->tx_offload_capa =
2599                 DEV_TX_OFFLOAD_VLAN_INSERT |
2600                 DEV_TX_OFFLOAD_QINQ_INSERT |
2601                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2602                 DEV_TX_OFFLOAD_UDP_CKSUM |
2603                 DEV_TX_OFFLOAD_TCP_CKSUM |
2604                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2605                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2606                 DEV_TX_OFFLOAD_TCP_TSO |
2607                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2608                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2609                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2610                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2611         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2612                                                 sizeof(uint32_t);
2613         dev_info->reta_size = pf->hash_lut_size;
2614         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2615
2616         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2617                 .rx_thresh = {
2618                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2619                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2620                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2621                 },
2622                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2623                 .rx_drop_en = 0,
2624         };
2625
2626         dev_info->default_txconf = (struct rte_eth_txconf) {
2627                 .tx_thresh = {
2628                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2629                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2630                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2631                 },
2632                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2633                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2634                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2635                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2636         };
2637
2638         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2639                 .nb_max = I40E_MAX_RING_DESC,
2640                 .nb_min = I40E_MIN_RING_DESC,
2641                 .nb_align = I40E_ALIGN_RING_DESC,
2642         };
2643
2644         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2645                 .nb_max = I40E_MAX_RING_DESC,
2646                 .nb_min = I40E_MIN_RING_DESC,
2647                 .nb_align = I40E_ALIGN_RING_DESC,
2648         };
2649
2650         if (pf->flags & I40E_FLAG_VMDQ) {
2651                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2652                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2653                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2654                                                 pf->max_nb_vmdq_vsi;
2655                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2656                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2657                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2658         }
2659
2660         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2661                 /* For XL710 */
2662                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2663         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2664                 /* For XXV710 */
2665                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2666         else
2667                 /* For X710 */
2668                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2669 }
2670
2671 static int
2672 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2673 {
2674         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2675         struct i40e_vsi *vsi = pf->main_vsi;
2676         PMD_INIT_FUNC_TRACE();
2677
2678         if (on)
2679                 return i40e_vsi_add_vlan(vsi, vlan_id);
2680         else
2681                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2682 }
2683
2684 static int
2685 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2686                    enum rte_vlan_type vlan_type,
2687                    uint16_t tpid)
2688 {
2689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2690         uint64_t reg_r = 0, reg_w = 0;
2691         uint16_t reg_id = 0;
2692         int ret = 0;
2693         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2694
2695         switch (vlan_type) {
2696         case ETH_VLAN_TYPE_OUTER:
2697                 if (qinq)
2698                         reg_id = 2;
2699                 else
2700                         reg_id = 3;
2701                 break;
2702         case ETH_VLAN_TYPE_INNER:
2703                 if (qinq)
2704                         reg_id = 3;
2705                 else {
2706                         ret = -EINVAL;
2707                         PMD_DRV_LOG(ERR,
2708                                 "Unsupported vlan type in single vlan.\n");
2709                         return ret;
2710                 }
2711                 break;
2712         default:
2713                 ret = -EINVAL;
2714                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2715                 return ret;
2716         }
2717         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2718                                           &reg_r, NULL);
2719         if (ret != I40E_SUCCESS) {
2720                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2721                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2722                 ret = -EIO;
2723                 return ret;
2724         }
2725         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2726                     "0x%08"PRIx64"", reg_id, reg_r);
2727
2728         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2729         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2730         if (reg_r == reg_w) {
2731                 ret = 0;
2732                 PMD_DRV_LOG(DEBUG, "No need to write");
2733                 return ret;
2734         }
2735
2736         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2737                                            reg_w, NULL);
2738         if (ret != I40E_SUCCESS) {
2739                 ret = -EIO;
2740                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2741                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2742                 return ret;
2743         }
2744         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2745                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2746
2747         return ret;
2748 }
2749
2750 static void
2751 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2752 {
2753         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2754         struct i40e_vsi *vsi = pf->main_vsi;
2755
2756         if (mask & ETH_VLAN_FILTER_MASK) {
2757                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2758                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2759                 else
2760                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2761         }
2762
2763         if (mask & ETH_VLAN_STRIP_MASK) {
2764                 /* Enable or disable VLAN stripping */
2765                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2766                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2767                 else
2768                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2769         }
2770
2771         if (mask & ETH_VLAN_EXTEND_MASK) {
2772                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2773                         i40e_vsi_config_double_vlan(vsi, TRUE);
2774                         /* Set global registers with default ether type value */
2775                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2776                                            ETHER_TYPE_VLAN);
2777                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2778                                            ETHER_TYPE_VLAN);
2779                 }
2780                 else
2781                         i40e_vsi_config_double_vlan(vsi, FALSE);
2782         }
2783 }
2784
2785 static void
2786 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2787                           __rte_unused uint16_t queue,
2788                           __rte_unused int on)
2789 {
2790         PMD_INIT_FUNC_TRACE();
2791 }
2792
2793 static int
2794 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2795 {
2796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2797         struct i40e_vsi *vsi = pf->main_vsi;
2798         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2799         struct i40e_vsi_vlan_pvid_info info;
2800
2801         memset(&info, 0, sizeof(info));
2802         info.on = on;
2803         if (info.on)
2804                 info.config.pvid = pvid;
2805         else {
2806                 info.config.reject.tagged =
2807                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2808                 info.config.reject.untagged =
2809                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2810         }
2811
2812         return i40e_vsi_vlan_pvid_set(vsi, &info);
2813 }
2814
2815 static int
2816 i40e_dev_led_on(struct rte_eth_dev *dev)
2817 {
2818         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819         uint32_t mode = i40e_led_get(hw);
2820
2821         if (mode == 0)
2822                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2823
2824         return 0;
2825 }
2826
2827 static int
2828 i40e_dev_led_off(struct rte_eth_dev *dev)
2829 {
2830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831         uint32_t mode = i40e_led_get(hw);
2832
2833         if (mode != 0)
2834                 i40e_led_set(hw, 0, false);
2835
2836         return 0;
2837 }
2838
2839 static int
2840 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2841 {
2842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2844
2845         fc_conf->pause_time = pf->fc_conf.pause_time;
2846         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2847         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2848
2849          /* Return current mode according to actual setting*/
2850         switch (hw->fc.current_mode) {
2851         case I40E_FC_FULL:
2852                 fc_conf->mode = RTE_FC_FULL;
2853                 break;
2854         case I40E_FC_TX_PAUSE:
2855                 fc_conf->mode = RTE_FC_TX_PAUSE;
2856                 break;
2857         case I40E_FC_RX_PAUSE:
2858                 fc_conf->mode = RTE_FC_RX_PAUSE;
2859                 break;
2860         case I40E_FC_NONE:
2861         default:
2862                 fc_conf->mode = RTE_FC_NONE;
2863         };
2864
2865         return 0;
2866 }
2867
2868 static int
2869 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2870 {
2871         uint32_t mflcn_reg, fctrl_reg, reg;
2872         uint32_t max_high_water;
2873         uint8_t i, aq_failure;
2874         int err;
2875         struct i40e_hw *hw;
2876         struct i40e_pf *pf;
2877         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2878                 [RTE_FC_NONE] = I40E_FC_NONE,
2879                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2880                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2881                 [RTE_FC_FULL] = I40E_FC_FULL
2882         };
2883
2884         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2885
2886         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2887         if ((fc_conf->high_water > max_high_water) ||
2888                         (fc_conf->high_water < fc_conf->low_water)) {
2889                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2890                         "High_water must <= %d.", max_high_water);
2891                 return -EINVAL;
2892         }
2893
2894         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2896         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2897
2898         pf->fc_conf.pause_time = fc_conf->pause_time;
2899         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2900         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2901
2902         PMD_INIT_FUNC_TRACE();
2903
2904         /* All the link flow control related enable/disable register
2905          * configuration is handle by the F/W
2906          */
2907         err = i40e_set_fc(hw, &aq_failure, true);
2908         if (err < 0)
2909                 return -ENOSYS;
2910
2911         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2912                 /* Configure flow control refresh threshold,
2913                  * the value for stat_tx_pause_refresh_timer[8]
2914                  * is used for global pause operation.
2915                  */
2916
2917                 I40E_WRITE_REG(hw,
2918                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2919                                pf->fc_conf.pause_time);
2920
2921                 /* configure the timer value included in transmitted pause
2922                  * frame,
2923                  * the value for stat_tx_pause_quanta[8] is used for global
2924                  * pause operation
2925                  */
2926                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2927                                pf->fc_conf.pause_time);
2928
2929                 fctrl_reg = I40E_READ_REG(hw,
2930                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2931
2932                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2933                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2934                 else
2935                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2936
2937                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2938                                fctrl_reg);
2939         } else {
2940                 /* Configure pause time (2 TCs per register) */
2941                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2942                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2943                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2944
2945                 /* Configure flow control refresh threshold value */
2946                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2947                                pf->fc_conf.pause_time / 2);
2948
2949                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2950
2951                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2952                  *depending on configuration
2953                  */
2954                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2955                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2956                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2957                 } else {
2958                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2959                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2960                 }
2961
2962                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2963         }
2964
2965         /* config the water marker both based on the packets and bytes */
2966         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2967                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2968                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2969         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2970                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2971                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2972         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2973                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2974                        << I40E_KILOSHIFT);
2975         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2976                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2977                        << I40E_KILOSHIFT);
2978
2979         I40E_WRITE_FLUSH(hw);
2980
2981         return 0;
2982 }
2983
2984 static int
2985 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2986                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2987 {
2988         PMD_INIT_FUNC_TRACE();
2989
2990         return -ENOSYS;
2991 }
2992
2993 /* Add a MAC address, and update filters */
2994 static void
2995 i40e_macaddr_add(struct rte_eth_dev *dev,
2996                  struct ether_addr *mac_addr,
2997                  __rte_unused uint32_t index,
2998                  uint32_t pool)
2999 {
3000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3001         struct i40e_mac_filter_info mac_filter;
3002         struct i40e_vsi *vsi;
3003         int ret;
3004
3005         /* If VMDQ not enabled or configured, return */
3006         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3007                           !pf->nb_cfg_vmdq_vsi)) {
3008                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3009                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3010                         pool);
3011                 return;
3012         }
3013
3014         if (pool > pf->nb_cfg_vmdq_vsi) {
3015                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3016                                 pool, pf->nb_cfg_vmdq_vsi);
3017                 return;
3018         }
3019
3020         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3021         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3022                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3023         else
3024                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3025
3026         if (pool == 0)
3027                 vsi = pf->main_vsi;
3028         else
3029                 vsi = pf->vmdq[pool - 1].vsi;
3030
3031         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3032         if (ret != I40E_SUCCESS) {
3033                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3034                 return;
3035         }
3036 }
3037
3038 /* Remove a MAC address, and update filters */
3039 static void
3040 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3041 {
3042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3043         struct i40e_vsi *vsi;
3044         struct rte_eth_dev_data *data = dev->data;
3045         struct ether_addr *macaddr;
3046         int ret;
3047         uint32_t i;
3048         uint64_t pool_sel;
3049
3050         macaddr = &(data->mac_addrs[index]);
3051
3052         pool_sel = dev->data->mac_pool_sel[index];
3053
3054         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3055                 if (pool_sel & (1ULL << i)) {
3056                         if (i == 0)
3057                                 vsi = pf->main_vsi;
3058                         else {
3059                                 /* No VMDQ pool enabled or configured */
3060                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3061                                         (i > pf->nb_cfg_vmdq_vsi)) {
3062                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3063                                                         "/configured");
3064                                         return;
3065                                 }
3066                                 vsi = pf->vmdq[i - 1].vsi;
3067                         }
3068                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3069
3070                         if (ret) {
3071                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3072                                 return;
3073                         }
3074                 }
3075         }
3076 }
3077
3078 /* Set perfect match or hash match of MAC and VLAN for a VF */
3079 static int
3080 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3081                  struct rte_eth_mac_filter *filter,
3082                  bool add)
3083 {
3084         struct i40e_hw *hw;
3085         struct i40e_mac_filter_info mac_filter;
3086         struct ether_addr old_mac;
3087         struct ether_addr *new_mac;
3088         struct i40e_pf_vf *vf = NULL;
3089         uint16_t vf_id;
3090         int ret;
3091
3092         if (pf == NULL) {
3093                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3094                 return -EINVAL;
3095         }
3096         hw = I40E_PF_TO_HW(pf);
3097
3098         if (filter == NULL) {
3099                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3100                 return -EINVAL;
3101         }
3102
3103         new_mac = &filter->mac_addr;
3104
3105         if (is_zero_ether_addr(new_mac)) {
3106                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3107                 return -EINVAL;
3108         }
3109
3110         vf_id = filter->dst_id;
3111
3112         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3113                 PMD_DRV_LOG(ERR, "Invalid argument.");
3114                 return -EINVAL;
3115         }
3116         vf = &pf->vfs[vf_id];
3117
3118         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3119                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3120                 return -EINVAL;
3121         }
3122
3123         if (add) {
3124                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3125                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3126                                 ETHER_ADDR_LEN);
3127                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3128                                  ETHER_ADDR_LEN);
3129
3130                 mac_filter.filter_type = filter->filter_type;
3131                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3132                 if (ret != I40E_SUCCESS) {
3133                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3134                         return -1;
3135                 }
3136                 ether_addr_copy(new_mac, &pf->dev_addr);
3137         } else {
3138                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3139                                 ETHER_ADDR_LEN);
3140                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3141                 if (ret != I40E_SUCCESS) {
3142                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3143                         return -1;
3144                 }
3145
3146                 /* Clear device address as it has been removed */
3147                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3148                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3149         }
3150
3151         return 0;
3152 }
3153
3154 /* MAC filter handle */
3155 static int
3156 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3157                 void *arg)
3158 {
3159         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3160         struct rte_eth_mac_filter *filter;
3161         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3162         int ret = I40E_NOT_SUPPORTED;
3163
3164         filter = (struct rte_eth_mac_filter *)(arg);
3165
3166         switch (filter_op) {
3167         case RTE_ETH_FILTER_NOP:
3168                 ret = I40E_SUCCESS;
3169                 break;
3170         case RTE_ETH_FILTER_ADD:
3171                 i40e_pf_disable_irq0(hw);
3172                 if (filter->is_vf)
3173                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3174                 i40e_pf_enable_irq0(hw);
3175                 break;
3176         case RTE_ETH_FILTER_DELETE:
3177                 i40e_pf_disable_irq0(hw);
3178                 if (filter->is_vf)
3179                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3180                 i40e_pf_enable_irq0(hw);
3181                 break;
3182         default:
3183                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3184                 ret = I40E_ERR_PARAM;
3185                 break;
3186         }
3187
3188         return ret;
3189 }
3190
3191 static int
3192 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3193 {
3194         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3195         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3196         int ret;
3197
3198         if (!lut)
3199                 return -EINVAL;
3200
3201         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3202                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3203                                           lut, lut_size);
3204                 if (ret) {
3205                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3206                         return ret;
3207                 }
3208         } else {
3209                 uint32_t *lut_dw = (uint32_t *)lut;
3210                 uint16_t i, lut_size_dw = lut_size / 4;
3211
3212                 for (i = 0; i < lut_size_dw; i++)
3213                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3214         }
3215
3216         return 0;
3217 }
3218
3219 static int
3220 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3221 {
3222         struct i40e_pf *pf;
3223         struct i40e_hw *hw;
3224         int ret;
3225
3226         if (!vsi || !lut)
3227                 return -EINVAL;
3228
3229         pf = I40E_VSI_TO_PF(vsi);
3230         hw = I40E_VSI_TO_HW(vsi);
3231
3232         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3233                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3234                                           lut, lut_size);
3235                 if (ret) {
3236                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3237                         return ret;
3238                 }
3239         } else {
3240                 uint32_t *lut_dw = (uint32_t *)lut;
3241                 uint16_t i, lut_size_dw = lut_size / 4;
3242
3243                 for (i = 0; i < lut_size_dw; i++)
3244                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3245                 I40E_WRITE_FLUSH(hw);
3246         }
3247
3248         return 0;
3249 }
3250
3251 static int
3252 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3253                          struct rte_eth_rss_reta_entry64 *reta_conf,
3254                          uint16_t reta_size)
3255 {
3256         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3257         uint16_t i, lut_size = pf->hash_lut_size;
3258         uint16_t idx, shift;
3259         uint8_t *lut;
3260         int ret;
3261
3262         if (reta_size != lut_size ||
3263                 reta_size > ETH_RSS_RETA_SIZE_512) {
3264                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3265                         "(%d) doesn't match the number hardware can supported "
3266                                         "(%d)\n", reta_size, lut_size);
3267                 return -EINVAL;
3268         }
3269
3270         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3271         if (!lut) {
3272                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3273                 return -ENOMEM;
3274         }
3275         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3276         if (ret)
3277                 goto out;
3278         for (i = 0; i < reta_size; i++) {
3279                 idx = i / RTE_RETA_GROUP_SIZE;
3280                 shift = i % RTE_RETA_GROUP_SIZE;
3281                 if (reta_conf[idx].mask & (1ULL << shift))
3282                         lut[i] = reta_conf[idx].reta[shift];
3283         }
3284         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3285
3286 out:
3287         rte_free(lut);
3288
3289         return ret;
3290 }
3291
3292 static int
3293 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3294                         struct rte_eth_rss_reta_entry64 *reta_conf,
3295                         uint16_t reta_size)
3296 {
3297         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3298         uint16_t i, lut_size = pf->hash_lut_size;
3299         uint16_t idx, shift;
3300         uint8_t *lut;
3301         int ret;
3302
3303         if (reta_size != lut_size ||
3304                 reta_size > ETH_RSS_RETA_SIZE_512) {
3305                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3306                         "(%d) doesn't match the number hardware can supported "
3307                                         "(%d)\n", reta_size, lut_size);
3308                 return -EINVAL;
3309         }
3310
3311         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3312         if (!lut) {
3313                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3314                 return -ENOMEM;
3315         }
3316
3317         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3318         if (ret)
3319                 goto out;
3320         for (i = 0; i < reta_size; i++) {
3321                 idx = i / RTE_RETA_GROUP_SIZE;
3322                 shift = i % RTE_RETA_GROUP_SIZE;
3323                 if (reta_conf[idx].mask & (1ULL << shift))
3324                         reta_conf[idx].reta[shift] = lut[i];
3325         }
3326
3327 out:
3328         rte_free(lut);
3329
3330         return ret;
3331 }
3332
3333 /**
3334  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3335  * @hw:   pointer to the HW structure
3336  * @mem:  pointer to mem struct to fill out
3337  * @size: size of memory requested
3338  * @alignment: what to align the allocation to
3339  **/
3340 enum i40e_status_code
3341 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3342                         struct i40e_dma_mem *mem,
3343                         u64 size,
3344                         u32 alignment)
3345 {
3346         const struct rte_memzone *mz = NULL;
3347         char z_name[RTE_MEMZONE_NAMESIZE];
3348
3349         if (!mem)
3350                 return I40E_ERR_PARAM;
3351
3352         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3353         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3354                                          alignment, RTE_PGSIZE_2M);
3355         if (!mz)
3356                 return I40E_ERR_NO_MEMORY;
3357
3358         mem->size = size;
3359         mem->va = mz->addr;
3360         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3361         mem->zone = (const void *)mz;
3362         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3363                     "%"PRIu64, mz->name, mem->pa);
3364
3365         return I40E_SUCCESS;
3366 }
3367
3368 /**
3369  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3370  * @hw:   pointer to the HW structure
3371  * @mem:  ptr to mem struct to free
3372  **/
3373 enum i40e_status_code
3374 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3375                     struct i40e_dma_mem *mem)
3376 {
3377         if (!mem)
3378                 return I40E_ERR_PARAM;
3379
3380         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3381                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3382                     mem->pa);
3383         rte_memzone_free((const struct rte_memzone *)mem->zone);
3384         mem->zone = NULL;
3385         mem->va = NULL;
3386         mem->pa = (u64)0;
3387
3388         return I40E_SUCCESS;
3389 }
3390
3391 /**
3392  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3393  * @hw:   pointer to the HW structure
3394  * @mem:  pointer to mem struct to fill out
3395  * @size: size of memory requested
3396  **/
3397 enum i40e_status_code
3398 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3399                          struct i40e_virt_mem *mem,
3400                          u32 size)
3401 {
3402         if (!mem)
3403                 return I40E_ERR_PARAM;
3404
3405         mem->size = size;
3406         mem->va = rte_zmalloc("i40e", size, 0);
3407
3408         if (mem->va)
3409                 return I40E_SUCCESS;
3410         else
3411                 return I40E_ERR_NO_MEMORY;
3412 }
3413
3414 /**
3415  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3416  * @hw:   pointer to the HW structure
3417  * @mem:  pointer to mem struct to free
3418  **/
3419 enum i40e_status_code
3420 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3421                      struct i40e_virt_mem *mem)
3422 {
3423         if (!mem)
3424                 return I40E_ERR_PARAM;
3425
3426         rte_free(mem->va);
3427         mem->va = NULL;
3428
3429         return I40E_SUCCESS;
3430 }
3431
3432 void
3433 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3434 {
3435         rte_spinlock_init(&sp->spinlock);
3436 }
3437
3438 void
3439 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3440 {
3441         rte_spinlock_lock(&sp->spinlock);
3442 }
3443
3444 void
3445 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3446 {
3447         rte_spinlock_unlock(&sp->spinlock);
3448 }
3449
3450 void
3451 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3452 {
3453         return;
3454 }
3455
3456 /**
3457  * Get the hardware capabilities, which will be parsed
3458  * and saved into struct i40e_hw.
3459  */
3460 static int
3461 i40e_get_cap(struct i40e_hw *hw)
3462 {
3463         struct i40e_aqc_list_capabilities_element_resp *buf;
3464         uint16_t len, size = 0;
3465         int ret;
3466
3467         /* Calculate a huge enough buff for saving response data temporarily */
3468         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3469                                                 I40E_MAX_CAP_ELE_NUM;
3470         buf = rte_zmalloc("i40e", len, 0);
3471         if (!buf) {
3472                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3473                 return I40E_ERR_NO_MEMORY;
3474         }
3475
3476         /* Get, parse the capabilities and save it to hw */
3477         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3478                         i40e_aqc_opc_list_func_capabilities, NULL);
3479         if (ret != I40E_SUCCESS)
3480                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3481
3482         /* Free the temporary buffer after being used */
3483         rte_free(buf);
3484
3485         return ret;
3486 }
3487
3488 static int
3489 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3490 {
3491         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3492         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3493         uint16_t qp_count = 0, vsi_count = 0;
3494
3495         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3496                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3497                 return -EINVAL;
3498         }
3499         /* Add the parameter init for LFC */
3500         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3501         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3502         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3503
3504         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3505         pf->max_num_vsi = hw->func_caps.num_vsis;
3506         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3507         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3508         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3509
3510         /* FDir queue/VSI allocation */
3511         pf->fdir_qp_offset = 0;
3512         if (hw->func_caps.fd) {
3513                 pf->flags |= I40E_FLAG_FDIR;
3514                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3515         } else {
3516                 pf->fdir_nb_qps = 0;
3517         }
3518         qp_count += pf->fdir_nb_qps;
3519         vsi_count += 1;
3520
3521         /* LAN queue/VSI allocation */
3522         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3523         if (!hw->func_caps.rss) {
3524                 pf->lan_nb_qps = 1;
3525         } else {
3526                 pf->flags |= I40E_FLAG_RSS;
3527                 if (hw->mac.type == I40E_MAC_X722)
3528                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3529                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3530         }
3531         qp_count += pf->lan_nb_qps;
3532         vsi_count += 1;
3533
3534         /* VF queue/VSI allocation */
3535         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3536         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3537                 pf->flags |= I40E_FLAG_SRIOV;
3538                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3539                 pf->vf_num = dev->pci_dev->max_vfs;
3540                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3541                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3542                             pf->vf_nb_qps * pf->vf_num);
3543         } else {
3544                 pf->vf_nb_qps = 0;
3545                 pf->vf_num = 0;
3546         }
3547         qp_count += pf->vf_nb_qps * pf->vf_num;
3548         vsi_count += pf->vf_num;
3549
3550         /* VMDq queue/VSI allocation */
3551         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3552         pf->vmdq_nb_qps = 0;
3553         pf->max_nb_vmdq_vsi = 0;
3554         if (hw->func_caps.vmdq) {
3555                 if (qp_count < hw->func_caps.num_tx_qp &&
3556                         vsi_count < hw->func_caps.num_vsis) {
3557                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3558                                 qp_count) / pf->vmdq_nb_qp_max;
3559
3560                         /* Limit the maximum number of VMDq vsi to the maximum
3561                          * ethdev can support
3562                          */
3563                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3564                                 hw->func_caps.num_vsis - vsi_count);
3565                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3566                                 ETH_64_POOLS);
3567                         if (pf->max_nb_vmdq_vsi) {
3568                                 pf->flags |= I40E_FLAG_VMDQ;
3569                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3570                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3571                                             "per VMDQ VSI, in total %u queues",
3572                                             pf->max_nb_vmdq_vsi,
3573                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3574                                             pf->max_nb_vmdq_vsi);
3575                         } else {
3576                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3577                                             "VMDq");
3578                         }
3579                 } else {
3580                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3581                 }
3582         }
3583         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3584         vsi_count += pf->max_nb_vmdq_vsi;
3585
3586         if (hw->func_caps.dcb)
3587                 pf->flags |= I40E_FLAG_DCB;
3588
3589         if (qp_count > hw->func_caps.num_tx_qp) {
3590                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3591                             "the hardware maximum %u", qp_count,
3592                             hw->func_caps.num_tx_qp);
3593                 return -EINVAL;
3594         }
3595         if (vsi_count > hw->func_caps.num_vsis) {
3596                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3597                             "the hardware maximum %u", vsi_count,
3598                             hw->func_caps.num_vsis);
3599                 return -EINVAL;
3600         }
3601
3602         return 0;
3603 }
3604
3605 static int
3606 i40e_pf_get_switch_config(struct i40e_pf *pf)
3607 {
3608         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3609         struct i40e_aqc_get_switch_config_resp *switch_config;
3610         struct i40e_aqc_switch_config_element_resp *element;
3611         uint16_t start_seid = 0, num_reported;
3612         int ret;
3613
3614         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3615                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3616         if (!switch_config) {
3617                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3618                 return -ENOMEM;
3619         }
3620
3621         /* Get the switch configurations */
3622         ret = i40e_aq_get_switch_config(hw, switch_config,
3623                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3624         if (ret != I40E_SUCCESS) {
3625                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3626                 goto fail;
3627         }
3628         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3629         if (num_reported != 1) { /* The number should be 1 */
3630                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3631                 goto fail;
3632         }
3633
3634         /* Parse the switch configuration elements */
3635         element = &(switch_config->element[0]);
3636         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3637                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3638                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3639         } else
3640                 PMD_DRV_LOG(INFO, "Unknown element type");
3641
3642 fail:
3643         rte_free(switch_config);
3644
3645         return ret;
3646 }
3647
3648 static int
3649 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3650                         uint32_t num)
3651 {
3652         struct pool_entry *entry;
3653
3654         if (pool == NULL || num == 0)
3655                 return -EINVAL;
3656
3657         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3658         if (entry == NULL) {
3659                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3660                 return -ENOMEM;
3661         }
3662
3663         /* queue heap initialize */
3664         pool->num_free = num;
3665         pool->num_alloc = 0;
3666         pool->base = base;
3667         LIST_INIT(&pool->alloc_list);
3668         LIST_INIT(&pool->free_list);
3669
3670         /* Initialize element  */
3671         entry->base = 0;
3672         entry->len = num;
3673
3674         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3675         return 0;
3676 }
3677
3678 static void
3679 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3680 {
3681         struct pool_entry *entry, *next_entry;
3682
3683         if (pool == NULL)
3684                 return;
3685
3686         for (entry = LIST_FIRST(&pool->alloc_list);
3687                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3688                         entry = next_entry) {
3689                 LIST_REMOVE(entry, next);
3690                 rte_free(entry);
3691         }
3692
3693         for (entry = LIST_FIRST(&pool->free_list);
3694                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3695                         entry = next_entry) {
3696                 LIST_REMOVE(entry, next);
3697                 rte_free(entry);
3698         }
3699
3700         pool->num_free = 0;
3701         pool->num_alloc = 0;
3702         pool->base = 0;
3703         LIST_INIT(&pool->alloc_list);
3704         LIST_INIT(&pool->free_list);
3705 }
3706
3707 static int
3708 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3709                        uint32_t base)
3710 {
3711         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3712         uint32_t pool_offset;
3713         int insert;
3714
3715         if (pool == NULL) {
3716                 PMD_DRV_LOG(ERR, "Invalid parameter");
3717                 return -EINVAL;
3718         }
3719
3720         pool_offset = base - pool->base;
3721         /* Lookup in alloc list */
3722         LIST_FOREACH(entry, &pool->alloc_list, next) {
3723                 if (entry->base == pool_offset) {
3724                         valid_entry = entry;
3725                         LIST_REMOVE(entry, next);
3726                         break;
3727                 }
3728         }
3729
3730         /* Not find, return */
3731         if (valid_entry == NULL) {
3732                 PMD_DRV_LOG(ERR, "Failed to find entry");
3733                 return -EINVAL;
3734         }
3735
3736         /**
3737          * Found it, move it to free list  and try to merge.
3738          * In order to make merge easier, always sort it by qbase.
3739          * Find adjacent prev and last entries.
3740          */
3741         prev = next = NULL;
3742         LIST_FOREACH(entry, &pool->free_list, next) {
3743                 if (entry->base > valid_entry->base) {
3744                         next = entry;
3745                         break;
3746                 }
3747                 prev = entry;
3748         }
3749
3750         insert = 0;
3751         /* Try to merge with next one*/
3752         if (next != NULL) {
3753                 /* Merge with next one */
3754                 if (valid_entry->base + valid_entry->len == next->base) {
3755                         next->base = valid_entry->base;
3756                         next->len += valid_entry->len;
3757                         rte_free(valid_entry);
3758                         valid_entry = next;
3759                         insert = 1;
3760                 }
3761         }
3762
3763         if (prev != NULL) {
3764                 /* Merge with previous one */
3765                 if (prev->base + prev->len == valid_entry->base) {
3766                         prev->len += valid_entry->len;
3767                         /* If it merge with next one, remove next node */
3768                         if (insert == 1) {
3769                                 LIST_REMOVE(valid_entry, next);
3770                                 rte_free(valid_entry);
3771                         } else {
3772                                 rte_free(valid_entry);
3773                                 insert = 1;
3774                         }
3775                 }
3776         }
3777
3778         /* Not find any entry to merge, insert */
3779         if (insert == 0) {
3780                 if (prev != NULL)
3781                         LIST_INSERT_AFTER(prev, valid_entry, next);
3782                 else if (next != NULL)
3783                         LIST_INSERT_BEFORE(next, valid_entry, next);
3784                 else /* It's empty list, insert to head */
3785                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3786         }
3787
3788         pool->num_free += valid_entry->len;
3789         pool->num_alloc -= valid_entry->len;
3790
3791         return 0;
3792 }
3793
3794 static int
3795 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3796                        uint16_t num)
3797 {
3798         struct pool_entry *entry, *valid_entry;
3799
3800         if (pool == NULL || num == 0) {
3801                 PMD_DRV_LOG(ERR, "Invalid parameter");
3802                 return -EINVAL;
3803         }
3804
3805         if (pool->num_free < num) {
3806                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3807                             num, pool->num_free);
3808                 return -ENOMEM;
3809         }
3810
3811         valid_entry = NULL;
3812         /* Lookup  in free list and find most fit one */
3813         LIST_FOREACH(entry, &pool->free_list, next) {
3814                 if (entry->len >= num) {
3815                         /* Find best one */
3816                         if (entry->len == num) {
3817                                 valid_entry = entry;
3818                                 break;
3819                         }
3820                         if (valid_entry == NULL || valid_entry->len > entry->len)
3821                                 valid_entry = entry;
3822                 }
3823         }
3824
3825         /* Not find one to satisfy the request, return */
3826         if (valid_entry == NULL) {
3827                 PMD_DRV_LOG(ERR, "No valid entry found");
3828                 return -ENOMEM;
3829         }
3830         /**
3831          * The entry have equal queue number as requested,
3832          * remove it from alloc_list.
3833          */
3834         if (valid_entry->len == num) {
3835                 LIST_REMOVE(valid_entry, next);
3836         } else {
3837                 /**
3838                  * The entry have more numbers than requested,
3839                  * create a new entry for alloc_list and minus its
3840                  * queue base and number in free_list.
3841                  */
3842                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3843                 if (entry == NULL) {
3844                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3845                                     "resource pool");
3846                         return -ENOMEM;
3847                 }
3848                 entry->base = valid_entry->base;
3849                 entry->len = num;
3850                 valid_entry->base += num;
3851                 valid_entry->len -= num;
3852                 valid_entry = entry;
3853         }
3854
3855         /* Insert it into alloc list, not sorted */
3856         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3857
3858         pool->num_free -= valid_entry->len;
3859         pool->num_alloc += valid_entry->len;
3860
3861         return valid_entry->base + pool->base;
3862 }
3863
3864 /**
3865  * bitmap_is_subset - Check whether src2 is subset of src1
3866  **/
3867 static inline int
3868 bitmap_is_subset(uint8_t src1, uint8_t src2)
3869 {
3870         return !((src1 ^ src2) & src2);
3871 }
3872
3873 static enum i40e_status_code
3874 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3875 {
3876         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3877
3878         /* If DCB is not supported, only default TC is supported */
3879         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3880                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3881                 return I40E_NOT_SUPPORTED;
3882         }
3883
3884         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3885                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3886                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3887                             enabled_tcmap);
3888                 return I40E_NOT_SUPPORTED;
3889         }
3890         return I40E_SUCCESS;
3891 }
3892
3893 int
3894 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3895                                 struct i40e_vsi_vlan_pvid_info *info)
3896 {
3897         struct i40e_hw *hw;
3898         struct i40e_vsi_context ctxt;
3899         uint8_t vlan_flags = 0;
3900         int ret;
3901
3902         if (vsi == NULL || info == NULL) {
3903                 PMD_DRV_LOG(ERR, "invalid parameters");
3904                 return I40E_ERR_PARAM;
3905         }
3906
3907         if (info->on) {
3908                 vsi->info.pvid = info->config.pvid;
3909                 /**
3910                  * If insert pvid is enabled, only tagged pkts are
3911                  * allowed to be sent out.
3912                  */
3913                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3914                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3915         } else {
3916                 vsi->info.pvid = 0;
3917                 if (info->config.reject.tagged == 0)
3918                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3919
3920                 if (info->config.reject.untagged == 0)
3921                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3922         }
3923         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3924                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3925         vsi->info.port_vlan_flags |= vlan_flags;
3926         vsi->info.valid_sections =
3927                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3928         memset(&ctxt, 0, sizeof(ctxt));
3929         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3930         ctxt.seid = vsi->seid;
3931
3932         hw = I40E_VSI_TO_HW(vsi);
3933         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3934         if (ret != I40E_SUCCESS)
3935                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3936
3937         return ret;
3938 }
3939
3940 static int
3941 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3942 {
3943         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3944         int i, ret;
3945         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3946
3947         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3948         if (ret != I40E_SUCCESS)
3949                 return ret;
3950
3951         if (!vsi->seid) {
3952                 PMD_DRV_LOG(ERR, "seid not valid");
3953                 return -EINVAL;
3954         }
3955
3956         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3957         tc_bw_data.tc_valid_bits = enabled_tcmap;
3958         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3959                 tc_bw_data.tc_bw_credits[i] =
3960                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3961
3962         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3963         if (ret != I40E_SUCCESS) {
3964                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3965                 return ret;
3966         }
3967
3968         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3969                                         sizeof(vsi->info.qs_handle));
3970         return I40E_SUCCESS;
3971 }
3972
3973 static enum i40e_status_code
3974 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3975                                  struct i40e_aqc_vsi_properties_data *info,
3976                                  uint8_t enabled_tcmap)
3977 {
3978         enum i40e_status_code ret;
3979         int i, total_tc = 0;
3980         uint16_t qpnum_per_tc, bsf, qp_idx;
3981
3982         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3983         if (ret != I40E_SUCCESS)
3984                 return ret;
3985
3986         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3987                 if (enabled_tcmap & (1 << i))
3988                         total_tc++;
3989         vsi->enabled_tc = enabled_tcmap;
3990
3991         /* Number of queues per enabled TC */
3992         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3993         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3994         bsf = rte_bsf32(qpnum_per_tc);
3995
3996         /* Adjust the queue number to actual queues that can be applied */
3997         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3998                 vsi->nb_qps = qpnum_per_tc * total_tc;
3999
4000         /**
4001          * Configure TC and queue mapping parameters, for enabled TC,
4002          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4003          * default queue will serve it.
4004          */
4005         qp_idx = 0;
4006         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4007                 if (vsi->enabled_tc & (1 << i)) {
4008                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4009                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4010                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4011                         qp_idx += qpnum_per_tc;
4012                 } else
4013                         info->tc_mapping[i] = 0;
4014         }
4015
4016         /* Associate queue number with VSI */
4017         if (vsi->type == I40E_VSI_SRIOV) {
4018                 info->mapping_flags |=
4019                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4020                 for (i = 0; i < vsi->nb_qps; i++)
4021                         info->queue_mapping[i] =
4022                                 rte_cpu_to_le_16(vsi->base_queue + i);
4023         } else {
4024                 info->mapping_flags |=
4025                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4026                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4027         }
4028         info->valid_sections |=
4029                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4030
4031         return I40E_SUCCESS;
4032 }
4033
4034 static int
4035 i40e_veb_release(struct i40e_veb *veb)
4036 {
4037         struct i40e_vsi *vsi;
4038         struct i40e_hw *hw;
4039
4040         if (veb == NULL)
4041                 return -EINVAL;
4042
4043         if (!TAILQ_EMPTY(&veb->head)) {
4044                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4045                 return -EACCES;
4046         }
4047         /* associate_vsi field is NULL for floating VEB */
4048         if (veb->associate_vsi != NULL) {
4049                 vsi = veb->associate_vsi;
4050                 hw = I40E_VSI_TO_HW(vsi);
4051
4052                 vsi->uplink_seid = veb->uplink_seid;
4053                 vsi->veb = NULL;
4054         } else {
4055                 veb->associate_pf->main_vsi->floating_veb = NULL;
4056                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4057         }
4058
4059         i40e_aq_delete_element(hw, veb->seid, NULL);
4060         rte_free(veb);
4061         return I40E_SUCCESS;
4062 }
4063
4064 /* Setup a veb */
4065 static struct i40e_veb *
4066 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4067 {
4068         struct i40e_veb *veb;
4069         int ret;
4070         struct i40e_hw *hw;
4071
4072         if (pf == NULL) {
4073                 PMD_DRV_LOG(ERR,
4074                             "veb setup failed, associated PF shouldn't null");
4075                 return NULL;
4076         }
4077         hw = I40E_PF_TO_HW(pf);
4078
4079         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4080         if (!veb) {
4081                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4082                 goto fail;
4083         }
4084
4085         veb->associate_vsi = vsi;
4086         veb->associate_pf = pf;
4087         TAILQ_INIT(&veb->head);
4088         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4089
4090         /* create floating veb if vsi is NULL */
4091         if (vsi != NULL) {
4092                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4093                                       I40E_DEFAULT_TCMAP, false,
4094                                       &veb->seid, false, NULL);
4095         } else {
4096                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4097                                       true, &veb->seid, false, NULL);
4098         }
4099
4100         if (ret != I40E_SUCCESS) {
4101                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4102                             hw->aq.asq_last_status);
4103                 goto fail;
4104         }
4105
4106         /* get statistics index */
4107         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4108                                 &veb->stats_idx, NULL, NULL, NULL);
4109         if (ret != I40E_SUCCESS) {
4110                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4111                             hw->aq.asq_last_status);
4112                 goto fail;
4113         }
4114         /* Get VEB bandwidth, to be implemented */
4115         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4116         if (vsi)
4117                 vsi->uplink_seid = veb->seid;
4118
4119         return veb;
4120 fail:
4121         rte_free(veb);
4122         return NULL;
4123 }
4124
4125 int
4126 i40e_vsi_release(struct i40e_vsi *vsi)
4127 {
4128         struct i40e_pf *pf;
4129         struct i40e_hw *hw;
4130         struct i40e_vsi_list *vsi_list;
4131         void *temp;
4132         int ret;
4133         struct i40e_mac_filter *f;
4134         uint16_t user_param;
4135
4136         if (!vsi)
4137                 return I40E_SUCCESS;
4138
4139         user_param = vsi->user_param;
4140
4141         pf = I40E_VSI_TO_PF(vsi);
4142         hw = I40E_VSI_TO_HW(vsi);
4143
4144         /* VSI has child to attach, release child first */
4145         if (vsi->veb) {
4146                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4147                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4148                                 return -1;
4149                 }
4150                 i40e_veb_release(vsi->veb);
4151         }
4152
4153         if (vsi->floating_veb) {
4154                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4155                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4156                                 return -1;
4157                 }
4158         }
4159
4160         /* Remove all macvlan filters of the VSI */
4161         i40e_vsi_remove_all_macvlan_filter(vsi);
4162         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4163                 rte_free(f);
4164
4165         if (vsi->type != I40E_VSI_MAIN &&
4166             ((vsi->type != I40E_VSI_SRIOV) ||
4167             !pf->floating_veb_list[user_param])) {
4168                 /* Remove vsi from parent's sibling list */
4169                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4170                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4171                         return I40E_ERR_PARAM;
4172                 }
4173                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4174                                 &vsi->sib_vsi_list, list);
4175
4176                 /* Remove all switch element of the VSI */
4177                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4178                 if (ret != I40E_SUCCESS)
4179                         PMD_DRV_LOG(ERR, "Failed to delete element");
4180         }
4181
4182         if ((vsi->type == I40E_VSI_SRIOV) &&
4183             pf->floating_veb_list[user_param]) {
4184                 /* Remove vsi from parent's sibling list */
4185                 if (vsi->parent_vsi == NULL ||
4186                     vsi->parent_vsi->floating_veb == NULL) {
4187                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4188                         return I40E_ERR_PARAM;
4189                 }
4190                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4191                              &vsi->sib_vsi_list, list);
4192
4193                 /* Remove all switch element of the VSI */
4194                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4195                 if (ret != I40E_SUCCESS)
4196                         PMD_DRV_LOG(ERR, "Failed to delete element");
4197         }
4198
4199         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4200
4201         if (vsi->type != I40E_VSI_SRIOV)
4202                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4203         rte_free(vsi);
4204
4205         return I40E_SUCCESS;
4206 }
4207
4208 static int
4209 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4210 {
4211         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4212         struct i40e_aqc_remove_macvlan_element_data def_filter;
4213         struct i40e_mac_filter_info filter;
4214         int ret;
4215
4216         if (vsi->type != I40E_VSI_MAIN)
4217                 return I40E_ERR_CONFIG;
4218         memset(&def_filter, 0, sizeof(def_filter));
4219         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4220                                         ETH_ADDR_LEN);
4221         def_filter.vlan_tag = 0;
4222         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4223                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4224         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4225         if (ret != I40E_SUCCESS) {
4226                 struct i40e_mac_filter *f;
4227                 struct ether_addr *mac;
4228
4229                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4230                             "macvlan filter");
4231                 /* It needs to add the permanent mac into mac list */
4232                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4233                 if (f == NULL) {
4234                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4235                         return I40E_ERR_NO_MEMORY;
4236                 }
4237                 mac = &f->mac_info.mac_addr;
4238                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4239                                 ETH_ADDR_LEN);
4240                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4241                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4242                 vsi->mac_num++;
4243
4244                 return ret;
4245         }
4246         (void)rte_memcpy(&filter.mac_addr,
4247                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4248         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4249         return i40e_vsi_add_mac(vsi, &filter);
4250 }
4251
4252 /*
4253  * i40e_vsi_get_bw_config - Query VSI BW Information
4254  * @vsi: the VSI to be queried
4255  *
4256  * Returns 0 on success, negative value on failure
4257  */
4258 static enum i40e_status_code
4259 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4260 {
4261         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4262         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4263         struct i40e_hw *hw = &vsi->adapter->hw;
4264         i40e_status ret;
4265         int i;
4266         uint32_t bw_max;
4267
4268         memset(&bw_config, 0, sizeof(bw_config));
4269         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4270         if (ret != I40E_SUCCESS) {
4271                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4272                             hw->aq.asq_last_status);
4273                 return ret;
4274         }
4275
4276         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4277         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4278                                         &ets_sla_config, NULL);
4279         if (ret != I40E_SUCCESS) {
4280                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4281                             "configuration %u", hw->aq.asq_last_status);
4282                 return ret;
4283         }
4284
4285         /* store and print out BW info */
4286         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4287         vsi->bw_info.bw_max = bw_config.max_bw;
4288         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4289         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4290         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4291                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4292                      I40E_16_BIT_WIDTH);
4293         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4294                 vsi->bw_info.bw_ets_share_credits[i] =
4295                                 ets_sla_config.share_credits[i];
4296                 vsi->bw_info.bw_ets_credits[i] =
4297                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4298                 /* 4 bits per TC, 4th bit is reserved */
4299                 vsi->bw_info.bw_ets_max[i] =
4300                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4301                                   RTE_LEN2MASK(3, uint8_t));
4302                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4303                             vsi->bw_info.bw_ets_share_credits[i]);
4304                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4305                             vsi->bw_info.bw_ets_credits[i]);
4306                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4307                             vsi->bw_info.bw_ets_max[i]);
4308         }
4309
4310         return I40E_SUCCESS;
4311 }
4312
4313 /* i40e_enable_pf_lb
4314  * @pf: pointer to the pf structure
4315  *
4316  * allow loopback on pf
4317  */
4318 static inline void
4319 i40e_enable_pf_lb(struct i40e_pf *pf)
4320 {
4321         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4322         struct i40e_vsi_context ctxt;
4323         int ret;
4324
4325         /* Use the FW API if FW >= v5.0 */
4326         if (hw->aq.fw_maj_ver < 5) {
4327                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4328                 return;
4329         }
4330
4331         memset(&ctxt, 0, sizeof(ctxt));
4332         ctxt.seid = pf->main_vsi_seid;
4333         ctxt.pf_num = hw->pf_id;
4334         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4335         if (ret) {
4336                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4337                             ret, hw->aq.asq_last_status);
4338                 return;
4339         }
4340         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4341         ctxt.info.valid_sections =
4342                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4343         ctxt.info.switch_id |=
4344                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4345
4346         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4347         if (ret)
4348                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4349                             hw->aq.asq_last_status);
4350 }
4351
4352 /* Setup a VSI */
4353 struct i40e_vsi *
4354 i40e_vsi_setup(struct i40e_pf *pf,
4355                enum i40e_vsi_type type,
4356                struct i40e_vsi *uplink_vsi,
4357                uint16_t user_param)
4358 {
4359         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4360         struct i40e_vsi *vsi;
4361         struct i40e_mac_filter_info filter;
4362         int ret;
4363         struct i40e_vsi_context ctxt;
4364         struct ether_addr broadcast =
4365                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4366
4367         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4368             uplink_vsi == NULL) {
4369                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4370                             "VSI link shouldn't be NULL");
4371                 return NULL;
4372         }
4373
4374         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4375                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4376                             "uplink VSI should be NULL");
4377                 return NULL;
4378         }
4379
4380         /* two situations
4381          * 1.type is not MAIN and uplink vsi is not NULL
4382          * If uplink vsi didn't setup VEB, create one first under veb field
4383          * 2.type is SRIOV and the uplink is NULL
4384          * If floating VEB is NULL, create one veb under floating veb field
4385          */
4386
4387         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4388             uplink_vsi->veb == NULL) {
4389                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4390
4391                 if (uplink_vsi->veb == NULL) {
4392                         PMD_DRV_LOG(ERR, "VEB setup failed");
4393                         return NULL;
4394                 }
4395                 /* set ALLOWLOOPBACk on pf, when veb is created */
4396                 i40e_enable_pf_lb(pf);
4397         }
4398
4399         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4400             pf->main_vsi->floating_veb == NULL) {
4401                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4402
4403                 if (pf->main_vsi->floating_veb == NULL) {
4404                         PMD_DRV_LOG(ERR, "VEB setup failed");
4405                         return NULL;
4406                 }
4407         }
4408
4409         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4410         if (!vsi) {
4411                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4412                 return NULL;
4413         }
4414         TAILQ_INIT(&vsi->mac_list);
4415         vsi->type = type;
4416         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4417         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4418         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4419         vsi->user_param = user_param;
4420         /* Allocate queues */
4421         switch (vsi->type) {
4422         case I40E_VSI_MAIN  :
4423                 vsi->nb_qps = pf->lan_nb_qps;
4424                 break;
4425         case I40E_VSI_SRIOV :
4426                 vsi->nb_qps = pf->vf_nb_qps;
4427                 break;
4428         case I40E_VSI_VMDQ2:
4429                 vsi->nb_qps = pf->vmdq_nb_qps;
4430                 break;
4431         case I40E_VSI_FDIR:
4432                 vsi->nb_qps = pf->fdir_nb_qps;
4433                 break;
4434         default:
4435                 goto fail_mem;
4436         }
4437         /*
4438          * The filter status descriptor is reported in rx queue 0,
4439          * while the tx queue for fdir filter programming has no
4440          * such constraints, can be non-zero queues.
4441          * To simplify it, choose FDIR vsi use queue 0 pair.
4442          * To make sure it will use queue 0 pair, queue allocation
4443          * need be done before this function is called
4444          */
4445         if (type != I40E_VSI_FDIR) {
4446                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4447                         if (ret < 0) {
4448                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4449                                                 vsi->seid, ret);
4450                                 goto fail_mem;
4451                         }
4452                         vsi->base_queue = ret;
4453         } else
4454                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4455
4456         /* VF has MSIX interrupt in VF range, don't allocate here */
4457         if (type == I40E_VSI_MAIN) {
4458                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4459                                           RTE_MIN(vsi->nb_qps,
4460                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4461                 if (ret < 0) {
4462                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4463                                     vsi->seid, ret);
4464                         goto fail_queue_alloc;
4465                 }
4466                 vsi->msix_intr = ret;
4467                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4468         } else if (type != I40E_VSI_SRIOV) {
4469                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4470                 if (ret < 0) {
4471                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4472                         goto fail_queue_alloc;
4473                 }
4474                 vsi->msix_intr = ret;
4475                 vsi->nb_msix = 1;
4476         } else {
4477                 vsi->msix_intr = 0;
4478                 vsi->nb_msix = 0;
4479         }
4480
4481         /* Add VSI */
4482         if (type == I40E_VSI_MAIN) {
4483                 /* For main VSI, no need to add since it's default one */
4484                 vsi->uplink_seid = pf->mac_seid;
4485                 vsi->seid = pf->main_vsi_seid;
4486                 /* Bind queues with specific MSIX interrupt */
4487                 /**
4488                  * Needs 2 interrupt at least, one for misc cause which will
4489                  * enabled from OS side, Another for queues binding the
4490                  * interrupt from device side only.
4491                  */
4492
4493                 /* Get default VSI parameters from hardware */
4494                 memset(&ctxt, 0, sizeof(ctxt));
4495                 ctxt.seid = vsi->seid;
4496                 ctxt.pf_num = hw->pf_id;
4497                 ctxt.uplink_seid = vsi->uplink_seid;
4498                 ctxt.vf_num = 0;
4499                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4500                 if (ret != I40E_SUCCESS) {
4501                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4502                         goto fail_msix_alloc;
4503                 }
4504                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4505                         sizeof(struct i40e_aqc_vsi_properties_data));
4506                 vsi->vsi_id = ctxt.vsi_number;
4507                 vsi->info.valid_sections = 0;
4508
4509                 /* Configure tc, enabled TC0 only */
4510                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4511                         I40E_SUCCESS) {
4512                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4513                         goto fail_msix_alloc;
4514                 }
4515
4516                 /* TC, queue mapping */
4517                 memset(&ctxt, 0, sizeof(ctxt));
4518                 vsi->info.valid_sections |=
4519                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4520                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4521                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4522                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4523                         sizeof(struct i40e_aqc_vsi_properties_data));
4524                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4525                                                 I40E_DEFAULT_TCMAP);
4526                 if (ret != I40E_SUCCESS) {
4527                         PMD_DRV_LOG(ERR, "Failed to configure "
4528                                     "TC queue mapping");
4529                         goto fail_msix_alloc;
4530                 }
4531                 ctxt.seid = vsi->seid;
4532                 ctxt.pf_num = hw->pf_id;
4533                 ctxt.uplink_seid = vsi->uplink_seid;
4534                 ctxt.vf_num = 0;
4535
4536                 /* Update VSI parameters */
4537                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4538                 if (ret != I40E_SUCCESS) {
4539                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4540                         goto fail_msix_alloc;
4541                 }
4542
4543                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4544                                                 sizeof(vsi->info.tc_mapping));
4545                 (void)rte_memcpy(&vsi->info.queue_mapping,
4546                                 &ctxt.info.queue_mapping,
4547                         sizeof(vsi->info.queue_mapping));
4548                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4549                 vsi->info.valid_sections = 0;
4550
4551                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4552                                 ETH_ADDR_LEN);
4553
4554                 /**
4555                  * Updating default filter settings are necessary to prevent
4556                  * reception of tagged packets.
4557                  * Some old firmware configurations load a default macvlan
4558                  * filter which accepts both tagged and untagged packets.
4559                  * The updating is to use a normal filter instead if needed.
4560                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4561                  * The firmware with correct configurations load the default
4562                  * macvlan filter which is expected and cannot be removed.
4563                  */
4564                 i40e_update_default_filter_setting(vsi);
4565                 i40e_config_qinq(hw, vsi);
4566         } else if (type == I40E_VSI_SRIOV) {
4567                 memset(&ctxt, 0, sizeof(ctxt));
4568                 /**
4569                  * For other VSI, the uplink_seid equals to uplink VSI's
4570                  * uplink_seid since they share same VEB
4571                  */
4572                 if (uplink_vsi == NULL)
4573                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4574                 else
4575                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4576                 ctxt.pf_num = hw->pf_id;
4577                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4578                 ctxt.uplink_seid = vsi->uplink_seid;
4579                 ctxt.connection_type = 0x1;
4580                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4581
4582                 /* Use the VEB configuration if FW >= v5.0 */
4583                 if (hw->aq.fw_maj_ver >= 5) {
4584                         /* Configure switch ID */
4585                         ctxt.info.valid_sections |=
4586                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4587                         ctxt.info.switch_id =
4588                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4589                 }
4590
4591                 /* Configure port/vlan */
4592                 ctxt.info.valid_sections |=
4593                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4594                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4595                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4596                                                 I40E_DEFAULT_TCMAP);
4597                 if (ret != I40E_SUCCESS) {
4598                         PMD_DRV_LOG(ERR, "Failed to configure "
4599                                     "TC queue mapping");
4600                         goto fail_msix_alloc;
4601                 }
4602                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4603                 ctxt.info.valid_sections |=
4604                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4605                 /**
4606                  * Since VSI is not created yet, only configure parameter,
4607                  * will add vsi below.
4608                  */
4609
4610                 i40e_config_qinq(hw, vsi);
4611         } else if (type == I40E_VSI_VMDQ2) {
4612                 memset(&ctxt, 0, sizeof(ctxt));
4613                 /*
4614                  * For other VSI, the uplink_seid equals to uplink VSI's
4615                  * uplink_seid since they share same VEB
4616                  */
4617                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4618                 ctxt.pf_num = hw->pf_id;
4619                 ctxt.vf_num = 0;
4620                 ctxt.uplink_seid = vsi->uplink_seid;
4621                 ctxt.connection_type = 0x1;
4622                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4623
4624                 ctxt.info.valid_sections |=
4625                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4626                 /* user_param carries flag to enable loop back */
4627                 if (user_param) {
4628                         ctxt.info.switch_id =
4629                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4630                         ctxt.info.switch_id |=
4631                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4632                 }
4633
4634                 /* Configure port/vlan */
4635                 ctxt.info.valid_sections |=
4636                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4637                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4638                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4639                                                 I40E_DEFAULT_TCMAP);
4640                 if (ret != I40E_SUCCESS) {
4641                         PMD_DRV_LOG(ERR, "Failed to configure "
4642                                         "TC queue mapping");
4643                         goto fail_msix_alloc;
4644                 }
4645                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4646                 ctxt.info.valid_sections |=
4647                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4648         } else if (type == I40E_VSI_FDIR) {
4649                 memset(&ctxt, 0, sizeof(ctxt));
4650                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4651                 ctxt.pf_num = hw->pf_id;
4652                 ctxt.vf_num = 0;
4653                 ctxt.uplink_seid = vsi->uplink_seid;
4654                 ctxt.connection_type = 0x1;     /* regular data port */
4655                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4656                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4657                                                 I40E_DEFAULT_TCMAP);
4658                 if (ret != I40E_SUCCESS) {
4659                         PMD_DRV_LOG(ERR, "Failed to configure "
4660                                         "TC queue mapping.");
4661                         goto fail_msix_alloc;
4662                 }
4663                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4664                 ctxt.info.valid_sections |=
4665                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4666         } else {
4667                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4668                 goto fail_msix_alloc;
4669         }
4670
4671         if (vsi->type != I40E_VSI_MAIN) {
4672                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4673                 if (ret != I40E_SUCCESS) {
4674                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4675                                     hw->aq.asq_last_status);
4676                         goto fail_msix_alloc;
4677                 }
4678                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4679                 vsi->info.valid_sections = 0;
4680                 vsi->seid = ctxt.seid;
4681                 vsi->vsi_id = ctxt.vsi_number;
4682                 vsi->sib_vsi_list.vsi = vsi;
4683                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4684                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4685                                           &vsi->sib_vsi_list, list);
4686                 } else {
4687                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4688                                           &vsi->sib_vsi_list, list);
4689                 }
4690         }
4691
4692         /* MAC/VLAN configuration */
4693         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4694         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4695
4696         ret = i40e_vsi_add_mac(vsi, &filter);
4697         if (ret != I40E_SUCCESS) {
4698                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4699                 goto fail_msix_alloc;
4700         }
4701
4702         /* Get VSI BW information */
4703         i40e_vsi_get_bw_config(vsi);
4704         return vsi;
4705 fail_msix_alloc:
4706         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4707 fail_queue_alloc:
4708         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4709 fail_mem:
4710         rte_free(vsi);
4711         return NULL;
4712 }
4713
4714 /* Configure vlan filter on or off */
4715 int
4716 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4717 {
4718         int i, num;
4719         struct i40e_mac_filter *f;
4720         void *temp;
4721         struct i40e_mac_filter_info *mac_filter;
4722         enum rte_mac_filter_type desired_filter;
4723         int ret = I40E_SUCCESS;
4724
4725         if (on) {
4726                 /* Filter to match MAC and VLAN */
4727                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4728         } else {
4729                 /* Filter to match only MAC */
4730                 desired_filter = RTE_MAC_PERFECT_MATCH;
4731         }
4732
4733         num = vsi->mac_num;
4734
4735         mac_filter = rte_zmalloc("mac_filter_info_data",
4736                                  num * sizeof(*mac_filter), 0);
4737         if (mac_filter == NULL) {
4738                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4739                 return I40E_ERR_NO_MEMORY;
4740         }
4741
4742         i = 0;
4743
4744         /* Remove all existing mac */
4745         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4746                 mac_filter[i] = f->mac_info;
4747                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4748                 if (ret) {
4749                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4750                                     on ? "enable" : "disable");
4751                         goto DONE;
4752                 }
4753                 i++;
4754         }
4755
4756         /* Override with new filter */
4757         for (i = 0; i < num; i++) {
4758                 mac_filter[i].filter_type = desired_filter;
4759                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4760                 if (ret) {
4761                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4762                                     on ? "enable" : "disable");
4763                         goto DONE;
4764                 }
4765         }
4766
4767 DONE:
4768         rte_free(mac_filter);
4769         return ret;
4770 }
4771
4772 /* Configure vlan stripping on or off */
4773 int
4774 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4775 {
4776         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4777         struct i40e_vsi_context ctxt;
4778         uint8_t vlan_flags;
4779         int ret = I40E_SUCCESS;
4780
4781         /* Check if it has been already on or off */
4782         if (vsi->info.valid_sections &
4783                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4784                 if (on) {
4785                         if ((vsi->info.port_vlan_flags &
4786                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4787                                 return 0; /* already on */
4788                 } else {
4789                         if ((vsi->info.port_vlan_flags &
4790                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4791                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4792                                 return 0; /* already off */
4793                 }
4794         }
4795
4796         if (on)
4797                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4798         else
4799                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4800         vsi->info.valid_sections =
4801                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4802         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4803         vsi->info.port_vlan_flags |= vlan_flags;
4804         ctxt.seid = vsi->seid;
4805         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4806         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4807         if (ret)
4808                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4809                             on ? "enable" : "disable");
4810
4811         return ret;
4812 }
4813
4814 static int
4815 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4816 {
4817         struct rte_eth_dev_data *data = dev->data;
4818         int ret;
4819         int mask = 0;
4820
4821         /* Apply vlan offload setting */
4822         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4823         i40e_vlan_offload_set(dev, mask);
4824
4825         /* Apply double-vlan setting, not implemented yet */
4826
4827         /* Apply pvid setting */
4828         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4829                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4830         if (ret)
4831                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4832
4833         return ret;
4834 }
4835
4836 static int
4837 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4838 {
4839         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4840
4841         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4842 }
4843
4844 static int
4845 i40e_update_flow_control(struct i40e_hw *hw)
4846 {
4847 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4848         struct i40e_link_status link_status;
4849         uint32_t rxfc = 0, txfc = 0, reg;
4850         uint8_t an_info;
4851         int ret;
4852
4853         memset(&link_status, 0, sizeof(link_status));
4854         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4855         if (ret != I40E_SUCCESS) {
4856                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4857                 goto write_reg; /* Disable flow control */
4858         }
4859
4860         an_info = hw->phy.link_info.an_info;
4861         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4862                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4863                 ret = I40E_ERR_NOT_READY;
4864                 goto write_reg; /* Disable flow control */
4865         }
4866         /**
4867          * If link auto negotiation is enabled, flow control needs to
4868          * be configured according to it
4869          */
4870         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4871         case I40E_LINK_PAUSE_RXTX:
4872                 rxfc = 1;
4873                 txfc = 1;
4874                 hw->fc.current_mode = I40E_FC_FULL;
4875                 break;
4876         case I40E_AQ_LINK_PAUSE_RX:
4877                 rxfc = 1;
4878                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4879                 break;
4880         case I40E_AQ_LINK_PAUSE_TX:
4881                 txfc = 1;
4882                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4883                 break;
4884         default:
4885                 hw->fc.current_mode = I40E_FC_NONE;
4886                 break;
4887         }
4888
4889 write_reg:
4890         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4891                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4892         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4893         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4894         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4895         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4896
4897         return ret;
4898 }
4899
4900 /* PF setup */
4901 static int
4902 i40e_pf_setup(struct i40e_pf *pf)
4903 {
4904         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4905         struct i40e_filter_control_settings settings;
4906         struct i40e_vsi *vsi;
4907         int ret;
4908
4909         /* Clear all stats counters */
4910         pf->offset_loaded = FALSE;
4911         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4912         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4913
4914         ret = i40e_pf_get_switch_config(pf);
4915         if (ret != I40E_SUCCESS) {
4916                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4917                 return ret;
4918         }
4919         if (pf->flags & I40E_FLAG_FDIR) {
4920                 /* make queue allocated first, let FDIR use queue pair 0*/
4921                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4922                 if (ret != I40E_FDIR_QUEUE_ID) {
4923                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4924                                     " ret =%d", ret);
4925                         pf->flags &= ~I40E_FLAG_FDIR;
4926                 }
4927         }
4928         /*  main VSI setup */
4929         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4930         if (!vsi) {
4931                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4932                 return I40E_ERR_NOT_READY;
4933         }
4934         pf->main_vsi = vsi;
4935
4936         /* Configure filter control */
4937         memset(&settings, 0, sizeof(settings));
4938         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4939                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4940         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4941                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4942         else {
4943                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4944                                                 hw->func_caps.rss_table_size);
4945                 return I40E_ERR_PARAM;
4946         }
4947         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4948                         "size: %u\n", hw->func_caps.rss_table_size);
4949         pf->hash_lut_size = hw->func_caps.rss_table_size;
4950
4951         /* Enable ethtype and macvlan filters */
4952         settings.enable_ethtype = TRUE;
4953         settings.enable_macvlan = TRUE;
4954         ret = i40e_set_filter_control(hw, &settings);
4955         if (ret)
4956                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4957                                                                 ret);
4958
4959         /* Update flow control according to the auto negotiation */
4960         i40e_update_flow_control(hw);
4961
4962         return I40E_SUCCESS;
4963 }
4964
4965 int
4966 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4967 {
4968         uint32_t reg;
4969         uint16_t j;
4970
4971         /**
4972          * Set or clear TX Queue Disable flags,
4973          * which is required by hardware.
4974          */
4975         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4976         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4977
4978         /* Wait until the request is finished */
4979         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4980                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4981                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4982                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4983                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4984                                                         & 0x1))) {
4985                         break;
4986                 }
4987         }
4988         if (on) {
4989                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4990                         return I40E_SUCCESS; /* already on, skip next steps */
4991
4992                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4993                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4994         } else {
4995                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4996                         return I40E_SUCCESS; /* already off, skip next steps */
4997                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4998         }
4999         /* Write the register */
5000         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5001         /* Check the result */
5002         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5003                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5004                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5005                 if (on) {
5006                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5007                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5008                                 break;
5009                 } else {
5010                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5011                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5012                                 break;
5013                 }
5014         }
5015         /* Check if it is timeout */
5016         if (j >= I40E_CHK_Q_ENA_COUNT) {
5017                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5018                             (on ? "enable" : "disable"), q_idx);
5019                 return I40E_ERR_TIMEOUT;
5020         }
5021
5022         return I40E_SUCCESS;
5023 }
5024
5025 /* Swith on or off the tx queues */
5026 static int
5027 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5028 {
5029         struct rte_eth_dev_data *dev_data = pf->dev_data;
5030         struct i40e_tx_queue *txq;
5031         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5032         uint16_t i;
5033         int ret;
5034
5035         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5036                 txq = dev_data->tx_queues[i];
5037                 /* Don't operate the queue if not configured or
5038                  * if starting only per queue */
5039                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5040                         continue;
5041                 if (on)
5042                         ret = i40e_dev_tx_queue_start(dev, i);
5043                 else
5044                         ret = i40e_dev_tx_queue_stop(dev, i);
5045                 if ( ret != I40E_SUCCESS)
5046                         return ret;
5047         }
5048
5049         return I40E_SUCCESS;
5050 }
5051
5052 int
5053 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5054 {
5055         uint32_t reg;
5056         uint16_t j;
5057
5058         /* Wait until the request is finished */
5059         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5060                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5061                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5062                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5063                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5064                         break;
5065         }
5066
5067         if (on) {
5068                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5069                         return I40E_SUCCESS; /* Already on, skip next steps */
5070                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5071         } else {
5072                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5073                         return I40E_SUCCESS; /* Already off, skip next steps */
5074                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5075         }
5076
5077         /* Write the register */
5078         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5079         /* Check the result */
5080         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5081                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5082                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5083                 if (on) {
5084                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5085                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5086                                 break;
5087                 } else {
5088                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5089                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5090                                 break;
5091                 }
5092         }
5093
5094         /* Check if it is timeout */
5095         if (j >= I40E_CHK_Q_ENA_COUNT) {
5096                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5097                             (on ? "enable" : "disable"), q_idx);
5098                 return I40E_ERR_TIMEOUT;
5099         }
5100
5101         return I40E_SUCCESS;
5102 }
5103 /* Switch on or off the rx queues */
5104 static int
5105 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5106 {
5107         struct rte_eth_dev_data *dev_data = pf->dev_data;
5108         struct i40e_rx_queue *rxq;
5109         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5110         uint16_t i;
5111         int ret;
5112
5113         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5114                 rxq = dev_data->rx_queues[i];
5115                 /* Don't operate the queue if not configured or
5116                  * if starting only per queue */
5117                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5118                         continue;
5119                 if (on)
5120                         ret = i40e_dev_rx_queue_start(dev, i);
5121                 else
5122                         ret = i40e_dev_rx_queue_stop(dev, i);
5123                 if (ret != I40E_SUCCESS)
5124                         return ret;
5125         }
5126
5127         return I40E_SUCCESS;
5128 }
5129
5130 /* Switch on or off all the rx/tx queues */
5131 int
5132 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5133 {
5134         int ret;
5135
5136         if (on) {
5137                 /* enable rx queues before enabling tx queues */
5138                 ret = i40e_dev_switch_rx_queues(pf, on);
5139                 if (ret) {
5140                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5141                         return ret;
5142                 }
5143                 ret = i40e_dev_switch_tx_queues(pf, on);
5144         } else {
5145                 /* Stop tx queues before stopping rx queues */
5146                 ret = i40e_dev_switch_tx_queues(pf, on);
5147                 if (ret) {
5148                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5149                         return ret;
5150                 }
5151                 ret = i40e_dev_switch_rx_queues(pf, on);
5152         }
5153
5154         return ret;
5155 }
5156
5157 /* Initialize VSI for TX */
5158 static int
5159 i40e_dev_tx_init(struct i40e_pf *pf)
5160 {
5161         struct rte_eth_dev_data *data = pf->dev_data;
5162         uint16_t i;
5163         uint32_t ret = I40E_SUCCESS;
5164         struct i40e_tx_queue *txq;
5165
5166         for (i = 0; i < data->nb_tx_queues; i++) {
5167                 txq = data->tx_queues[i];
5168                 if (!txq || !txq->q_set)
5169                         continue;
5170                 ret = i40e_tx_queue_init(txq);
5171                 if (ret != I40E_SUCCESS)
5172                         break;
5173         }
5174         if (ret == I40E_SUCCESS)
5175                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5176                                      ->eth_dev);
5177
5178         return ret;
5179 }
5180
5181 /* Initialize VSI for RX */
5182 static int
5183 i40e_dev_rx_init(struct i40e_pf *pf)
5184 {
5185         struct rte_eth_dev_data *data = pf->dev_data;
5186         int ret = I40E_SUCCESS;
5187         uint16_t i;
5188         struct i40e_rx_queue *rxq;
5189
5190         i40e_pf_config_mq_rx(pf);
5191         for (i = 0; i < data->nb_rx_queues; i++) {
5192                 rxq = data->rx_queues[i];
5193                 if (!rxq || !rxq->q_set)
5194                         continue;
5195
5196                 ret = i40e_rx_queue_init(rxq);
5197                 if (ret != I40E_SUCCESS) {
5198                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5199                                     "initialization");
5200                         break;
5201                 }
5202         }
5203         if (ret == I40E_SUCCESS)
5204                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5205                                      ->eth_dev);
5206
5207         return ret;
5208 }
5209
5210 static int
5211 i40e_dev_rxtx_init(struct i40e_pf *pf)
5212 {
5213         int err;
5214
5215         err = i40e_dev_tx_init(pf);
5216         if (err) {
5217                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5218                 return err;
5219         }
5220         err = i40e_dev_rx_init(pf);
5221         if (err) {
5222                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5223                 return err;
5224         }
5225
5226         return err;
5227 }
5228
5229 static int
5230 i40e_vmdq_setup(struct rte_eth_dev *dev)
5231 {
5232         struct rte_eth_conf *conf = &dev->data->dev_conf;
5233         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5234         int i, err, conf_vsis, j, loop;
5235         struct i40e_vsi *vsi;
5236         struct i40e_vmdq_info *vmdq_info;
5237         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5238         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5239
5240         /*
5241          * Disable interrupt to avoid message from VF. Furthermore, it will
5242          * avoid race condition in VSI creation/destroy.
5243          */
5244         i40e_pf_disable_irq0(hw);
5245
5246         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5247                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5248                 return -ENOTSUP;
5249         }
5250
5251         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5252         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5253                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5254                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5255                         pf->max_nb_vmdq_vsi);
5256                 return -ENOTSUP;
5257         }
5258
5259         if (pf->vmdq != NULL) {
5260                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5261                 return 0;
5262         }
5263
5264         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5265                                 sizeof(*vmdq_info) * conf_vsis, 0);
5266
5267         if (pf->vmdq == NULL) {
5268                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5269                 return -ENOMEM;
5270         }
5271
5272         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5273
5274         /* Create VMDQ VSI */
5275         for (i = 0; i < conf_vsis; i++) {
5276                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5277                                 vmdq_conf->enable_loop_back);
5278                 if (vsi == NULL) {
5279                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5280                         err = -1;
5281                         goto err_vsi_setup;
5282                 }
5283                 vmdq_info = &pf->vmdq[i];
5284                 vmdq_info->pf = pf;
5285                 vmdq_info->vsi = vsi;
5286         }
5287         pf->nb_cfg_vmdq_vsi = conf_vsis;
5288
5289         /* Configure Vlan */
5290         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5291         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5292                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5293                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5294                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5295                                         vmdq_conf->pool_map[i].vlan_id, j);
5296
5297                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5298                                                 vmdq_conf->pool_map[i].vlan_id);
5299                                 if (err) {
5300                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5301                                         err = -1;
5302                                         goto err_vsi_setup;
5303                                 }
5304                         }
5305                 }
5306         }
5307
5308         i40e_pf_enable_irq0(hw);
5309
5310         return 0;
5311
5312 err_vsi_setup:
5313         for (i = 0; i < conf_vsis; i++)
5314                 if (pf->vmdq[i].vsi == NULL)
5315                         break;
5316                 else
5317                         i40e_vsi_release(pf->vmdq[i].vsi);
5318
5319         rte_free(pf->vmdq);
5320         pf->vmdq = NULL;
5321         i40e_pf_enable_irq0(hw);
5322         return err;
5323 }
5324
5325 static void
5326 i40e_stat_update_32(struct i40e_hw *hw,
5327                    uint32_t reg,
5328                    bool offset_loaded,
5329                    uint64_t *offset,
5330                    uint64_t *stat)
5331 {
5332         uint64_t new_data;
5333
5334         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5335         if (!offset_loaded)
5336                 *offset = new_data;
5337
5338         if (new_data >= *offset)
5339                 *stat = (uint64_t)(new_data - *offset);
5340         else
5341                 *stat = (uint64_t)((new_data +
5342                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5343 }
5344
5345 static void
5346 i40e_stat_update_48(struct i40e_hw *hw,
5347                    uint32_t hireg,
5348                    uint32_t loreg,
5349                    bool offset_loaded,
5350                    uint64_t *offset,
5351                    uint64_t *stat)
5352 {
5353         uint64_t new_data;
5354
5355         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5356         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5357                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5358
5359         if (!offset_loaded)
5360                 *offset = new_data;
5361
5362         if (new_data >= *offset)
5363                 *stat = new_data - *offset;
5364         else
5365                 *stat = (uint64_t)((new_data +
5366                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5367
5368         *stat &= I40E_48_BIT_MASK;
5369 }
5370
5371 /* Disable IRQ0 */
5372 void
5373 i40e_pf_disable_irq0(struct i40e_hw *hw)
5374 {
5375         /* Disable all interrupt types */
5376         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5377         I40E_WRITE_FLUSH(hw);
5378 }
5379
5380 /* Enable IRQ0 */
5381 void
5382 i40e_pf_enable_irq0(struct i40e_hw *hw)
5383 {
5384         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5385                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5386                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5387                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5388         I40E_WRITE_FLUSH(hw);
5389 }
5390
5391 static void
5392 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5393 {
5394         /* read pending request and disable first */
5395         i40e_pf_disable_irq0(hw);
5396         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5397         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5398                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5399
5400         if (no_queue)
5401                 /* Link no queues with irq0 */
5402                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5403                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5404 }
5405
5406 static void
5407 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5408 {
5409         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5411         int i;
5412         uint16_t abs_vf_id;
5413         uint32_t index, offset, val;
5414
5415         if (!pf->vfs)
5416                 return;
5417         /**
5418          * Try to find which VF trigger a reset, use absolute VF id to access
5419          * since the reg is global register.
5420          */
5421         for (i = 0; i < pf->vf_num; i++) {
5422                 abs_vf_id = hw->func_caps.vf_base_id + i;
5423                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5424                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5425                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5426                 /* VFR event occured */
5427                 if (val & (0x1 << offset)) {
5428                         int ret;
5429
5430                         /* Clear the event first */
5431                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5432                                                         (0x1 << offset));
5433                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5434                         /**
5435                          * Only notify a VF reset event occured,
5436                          * don't trigger another SW reset
5437                          */
5438                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5439                         if (ret != I40E_SUCCESS)
5440                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5441                 }
5442         }
5443 }
5444
5445 static void
5446 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5447 {
5448         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5449         struct i40e_virtchnl_pf_event event;
5450         int i;
5451
5452         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5453         event.event_data.link_event.link_status =
5454                 dev->data->dev_link.link_status;
5455         event.event_data.link_event.link_speed =
5456                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5457
5458         for (i = 0; i < pf->vf_num; i++)
5459                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5460                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5461 }
5462
5463 static void
5464 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5465 {
5466         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5467         struct i40e_arq_event_info info;
5468         uint16_t pending, opcode;
5469         int ret;
5470
5471         info.buf_len = I40E_AQ_BUF_SZ;
5472         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5473         if (!info.msg_buf) {
5474                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5475                 return;
5476         }
5477
5478         pending = 1;
5479         while (pending) {
5480                 ret = i40e_clean_arq_element(hw, &info, &pending);
5481
5482                 if (ret != I40E_SUCCESS) {
5483                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5484                                     "aq_err: %u", hw->aq.asq_last_status);
5485                         break;
5486                 }
5487                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5488
5489                 switch (opcode) {
5490                 case i40e_aqc_opc_send_msg_to_pf:
5491                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5492                         i40e_pf_host_handle_vf_msg(dev,
5493                                         rte_le_to_cpu_16(info.desc.retval),
5494                                         rte_le_to_cpu_32(info.desc.cookie_high),
5495                                         rte_le_to_cpu_32(info.desc.cookie_low),
5496                                         info.msg_buf,
5497                                         info.msg_len);
5498                         break;
5499                 case i40e_aqc_opc_get_link_status:
5500                         ret = i40e_dev_link_update(dev, 0);
5501                         if (!ret) {
5502                                 i40e_notify_all_vfs_link_status(dev);
5503                                 _rte_eth_dev_callback_process(dev,
5504                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5505                         }
5506                         break;
5507                 default:
5508                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5509                                     opcode);
5510                         break;
5511                 }
5512         }
5513         rte_free(info.msg_buf);
5514 }
5515
5516 /**
5517  * Interrupt handler triggered by NIC  for handling
5518  * specific interrupt.
5519  *
5520  * @param handle
5521  *  Pointer to interrupt handle.
5522  * @param param
5523  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5524  *
5525  * @return
5526  *  void
5527  */
5528 static void
5529 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5530                            void *param)
5531 {
5532         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5533         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5534         uint32_t icr0;
5535
5536         /* Disable interrupt */
5537         i40e_pf_disable_irq0(hw);
5538
5539         /* read out interrupt causes */
5540         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5541
5542         /* No interrupt event indicated */
5543         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5544                 PMD_DRV_LOG(INFO, "No interrupt event");
5545                 goto done;
5546         }
5547 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5548         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5549                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5550         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5551                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5552         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5553                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5554         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5555                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5556         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5557                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5558         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5559                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5560         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5561                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5562 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5563
5564         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5565                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5566                 i40e_dev_handle_vfr_event(dev);
5567         }
5568         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5569                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5570                 i40e_dev_handle_aq_msg(dev);
5571         }
5572
5573 done:
5574         /* Enable interrupt */
5575         i40e_pf_enable_irq0(hw);
5576         rte_intr_enable(&(dev->pci_dev->intr_handle));
5577 }
5578
5579 static int
5580 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5581                          struct i40e_macvlan_filter *filter,
5582                          int total)
5583 {
5584         int ele_num, ele_buff_size;
5585         int num, actual_num, i;
5586         uint16_t flags;
5587         int ret = I40E_SUCCESS;
5588         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5589         struct i40e_aqc_add_macvlan_element_data *req_list;
5590
5591         if (filter == NULL  || total == 0)
5592                 return I40E_ERR_PARAM;
5593         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5594         ele_buff_size = hw->aq.asq_buf_size;
5595
5596         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5597         if (req_list == NULL) {
5598                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5599                 return I40E_ERR_NO_MEMORY;
5600         }
5601
5602         num = 0;
5603         do {
5604                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5605                 memset(req_list, 0, ele_buff_size);
5606
5607                 for (i = 0; i < actual_num; i++) {
5608                         (void)rte_memcpy(req_list[i].mac_addr,
5609                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5610                         req_list[i].vlan_tag =
5611                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5612
5613                         switch (filter[num + i].filter_type) {
5614                         case RTE_MAC_PERFECT_MATCH:
5615                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5616                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5617                                 break;
5618                         case RTE_MACVLAN_PERFECT_MATCH:
5619                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5620                                 break;
5621                         case RTE_MAC_HASH_MATCH:
5622                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5623                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5624                                 break;
5625                         case RTE_MACVLAN_HASH_MATCH:
5626                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5627                                 break;
5628                         default:
5629                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5630                                 ret = I40E_ERR_PARAM;
5631                                 goto DONE;
5632                         }
5633
5634                         req_list[i].queue_number = 0;
5635
5636                         req_list[i].flags = rte_cpu_to_le_16(flags);
5637                 }
5638
5639                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5640                                                 actual_num, NULL);
5641                 if (ret != I40E_SUCCESS) {
5642                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5643                         goto DONE;
5644                 }
5645                 num += actual_num;
5646         } while (num < total);
5647
5648 DONE:
5649         rte_free(req_list);
5650         return ret;
5651 }
5652
5653 static int
5654 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5655                             struct i40e_macvlan_filter *filter,
5656                             int total)
5657 {
5658         int ele_num, ele_buff_size;
5659         int num, actual_num, i;
5660         uint16_t flags;
5661         int ret = I40E_SUCCESS;
5662         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5663         struct i40e_aqc_remove_macvlan_element_data *req_list;
5664
5665         if (filter == NULL  || total == 0)
5666                 return I40E_ERR_PARAM;
5667
5668         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5669         ele_buff_size = hw->aq.asq_buf_size;
5670
5671         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5672         if (req_list == NULL) {
5673                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5674                 return I40E_ERR_NO_MEMORY;
5675         }
5676
5677         num = 0;
5678         do {
5679                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5680                 memset(req_list, 0, ele_buff_size);
5681
5682                 for (i = 0; i < actual_num; i++) {
5683                         (void)rte_memcpy(req_list[i].mac_addr,
5684                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5685                         req_list[i].vlan_tag =
5686                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5687
5688                         switch (filter[num + i].filter_type) {
5689                         case RTE_MAC_PERFECT_MATCH:
5690                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5691                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5692                                 break;
5693                         case RTE_MACVLAN_PERFECT_MATCH:
5694                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5695                                 break;
5696                         case RTE_MAC_HASH_MATCH:
5697                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5698                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5699                                 break;
5700                         case RTE_MACVLAN_HASH_MATCH:
5701                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5702                                 break;
5703                         default:
5704                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5705                                 ret = I40E_ERR_PARAM;
5706                                 goto DONE;
5707                         }
5708                         req_list[i].flags = rte_cpu_to_le_16(flags);
5709                 }
5710
5711                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5712                                                 actual_num, NULL);
5713                 if (ret != I40E_SUCCESS) {
5714                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5715                         goto DONE;
5716                 }
5717                 num += actual_num;
5718         } while (num < total);
5719
5720 DONE:
5721         rte_free(req_list);
5722         return ret;
5723 }
5724
5725 /* Find out specific MAC filter */
5726 static struct i40e_mac_filter *
5727 i40e_find_mac_filter(struct i40e_vsi *vsi,
5728                          struct ether_addr *macaddr)
5729 {
5730         struct i40e_mac_filter *f;
5731
5732         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5733                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5734                         return f;
5735         }
5736
5737         return NULL;
5738 }
5739
5740 static bool
5741 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5742                          uint16_t vlan_id)
5743 {
5744         uint32_t vid_idx, vid_bit;
5745
5746         if (vlan_id > ETH_VLAN_ID_MAX)
5747                 return 0;
5748
5749         vid_idx = I40E_VFTA_IDX(vlan_id);
5750         vid_bit = I40E_VFTA_BIT(vlan_id);
5751
5752         if (vsi->vfta[vid_idx] & vid_bit)
5753                 return 1;
5754         else
5755                 return 0;
5756 }
5757
5758 static void
5759 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5760                          uint16_t vlan_id, bool on)
5761 {
5762         uint32_t vid_idx, vid_bit;
5763
5764         if (vlan_id > ETH_VLAN_ID_MAX)
5765                 return;
5766
5767         vid_idx = I40E_VFTA_IDX(vlan_id);
5768         vid_bit = I40E_VFTA_BIT(vlan_id);
5769
5770         if (on)
5771                 vsi->vfta[vid_idx] |= vid_bit;
5772         else
5773                 vsi->vfta[vid_idx] &= ~vid_bit;
5774 }
5775
5776 /**
5777  * Find all vlan options for specific mac addr,
5778  * return with actual vlan found.
5779  */
5780 static inline int
5781 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5782                            struct i40e_macvlan_filter *mv_f,
5783                            int num, struct ether_addr *addr)
5784 {
5785         int i;
5786         uint32_t j, k;
5787
5788         /**
5789          * Not to use i40e_find_vlan_filter to decrease the loop time,
5790          * although the code looks complex.
5791           */
5792         if (num < vsi->vlan_num)
5793                 return I40E_ERR_PARAM;
5794
5795         i = 0;
5796         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5797                 if (vsi->vfta[j]) {
5798                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5799                                 if (vsi->vfta[j] & (1 << k)) {
5800                                         if (i > num - 1) {
5801                                                 PMD_DRV_LOG(ERR, "vlan number "
5802                                                             "not match");
5803                                                 return I40E_ERR_PARAM;
5804                                         }
5805                                         (void)rte_memcpy(&mv_f[i].macaddr,
5806                                                         addr, ETH_ADDR_LEN);
5807                                         mv_f[i].vlan_id =
5808                                                 j * I40E_UINT32_BIT_SIZE + k;
5809                                         i++;
5810                                 }
5811                         }
5812                 }
5813         }
5814         return I40E_SUCCESS;
5815 }
5816
5817 static inline int
5818 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5819                            struct i40e_macvlan_filter *mv_f,
5820                            int num,
5821                            uint16_t vlan)
5822 {
5823         int i = 0;
5824         struct i40e_mac_filter *f;
5825
5826         if (num < vsi->mac_num)
5827                 return I40E_ERR_PARAM;
5828
5829         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5830                 if (i > num - 1) {
5831                         PMD_DRV_LOG(ERR, "buffer number not match");
5832                         return I40E_ERR_PARAM;
5833                 }
5834                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5835                                 ETH_ADDR_LEN);
5836                 mv_f[i].vlan_id = vlan;
5837                 mv_f[i].filter_type = f->mac_info.filter_type;
5838                 i++;
5839         }
5840
5841         return I40E_SUCCESS;
5842 }
5843
5844 static int
5845 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5846 {
5847         int i, num;
5848         struct i40e_mac_filter *f;
5849         struct i40e_macvlan_filter *mv_f;
5850         int ret = I40E_SUCCESS;
5851
5852         if (vsi == NULL || vsi->mac_num == 0)
5853                 return I40E_ERR_PARAM;
5854
5855         /* Case that no vlan is set */
5856         if (vsi->vlan_num == 0)
5857                 num = vsi->mac_num;
5858         else
5859                 num = vsi->mac_num * vsi->vlan_num;
5860
5861         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5862         if (mv_f == NULL) {
5863                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5864                 return I40E_ERR_NO_MEMORY;
5865         }
5866
5867         i = 0;
5868         if (vsi->vlan_num == 0) {
5869                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5870                         (void)rte_memcpy(&mv_f[i].macaddr,
5871                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5872                         mv_f[i].vlan_id = 0;
5873                         i++;
5874                 }
5875         } else {
5876                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5877                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5878                                         vsi->vlan_num, &f->mac_info.mac_addr);
5879                         if (ret != I40E_SUCCESS)
5880                                 goto DONE;
5881                         i += vsi->vlan_num;
5882                 }
5883         }
5884
5885         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5886 DONE:
5887         rte_free(mv_f);
5888
5889         return ret;
5890 }
5891
5892 int
5893 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5894 {
5895         struct i40e_macvlan_filter *mv_f;
5896         int mac_num;
5897         int ret = I40E_SUCCESS;
5898
5899         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5900                 return I40E_ERR_PARAM;
5901
5902         /* If it's already set, just return */
5903         if (i40e_find_vlan_filter(vsi,vlan))
5904                 return I40E_SUCCESS;
5905
5906         mac_num = vsi->mac_num;
5907
5908         if (mac_num == 0) {
5909                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5910                 return I40E_ERR_PARAM;
5911         }
5912
5913         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5914
5915         if (mv_f == NULL) {
5916                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5917                 return I40E_ERR_NO_MEMORY;
5918         }
5919
5920         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5921
5922         if (ret != I40E_SUCCESS)
5923                 goto DONE;
5924
5925         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5926
5927         if (ret != I40E_SUCCESS)
5928                 goto DONE;
5929
5930         i40e_set_vlan_filter(vsi, vlan, 1);
5931
5932         vsi->vlan_num++;
5933         ret = I40E_SUCCESS;
5934 DONE:
5935         rte_free(mv_f);
5936         return ret;
5937 }
5938
5939 int
5940 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5941 {
5942         struct i40e_macvlan_filter *mv_f;
5943         int mac_num;
5944         int ret = I40E_SUCCESS;
5945
5946         /**
5947          * Vlan 0 is the generic filter for untagged packets
5948          * and can't be removed.
5949          */
5950         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5951                 return I40E_ERR_PARAM;
5952
5953         /* If can't find it, just return */
5954         if (!i40e_find_vlan_filter(vsi, vlan))
5955                 return I40E_ERR_PARAM;
5956
5957         mac_num = vsi->mac_num;
5958
5959         if (mac_num == 0) {
5960                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5961                 return I40E_ERR_PARAM;
5962         }
5963
5964         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5965
5966         if (mv_f == NULL) {
5967                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5968                 return I40E_ERR_NO_MEMORY;
5969         }
5970
5971         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5972
5973         if (ret != I40E_SUCCESS)
5974                 goto DONE;
5975
5976         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5977
5978         if (ret != I40E_SUCCESS)
5979                 goto DONE;
5980
5981         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5982         if (vsi->vlan_num == 1) {
5983                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5984                 if (ret != I40E_SUCCESS)
5985                         goto DONE;
5986
5987                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5988                 if (ret != I40E_SUCCESS)
5989                         goto DONE;
5990         }
5991
5992         i40e_set_vlan_filter(vsi, vlan, 0);
5993
5994         vsi->vlan_num--;
5995         ret = I40E_SUCCESS;
5996 DONE:
5997         rte_free(mv_f);
5998         return ret;
5999 }
6000
6001 int
6002 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6003 {
6004         struct i40e_mac_filter *f;
6005         struct i40e_macvlan_filter *mv_f;
6006         int i, vlan_num = 0;
6007         int ret = I40E_SUCCESS;
6008
6009         /* If it's add and we've config it, return */
6010         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6011         if (f != NULL)
6012                 return I40E_SUCCESS;
6013         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6014                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6015
6016                 /**
6017                  * If vlan_num is 0, that's the first time to add mac,
6018                  * set mask for vlan_id 0.
6019                  */
6020                 if (vsi->vlan_num == 0) {
6021                         i40e_set_vlan_filter(vsi, 0, 1);
6022                         vsi->vlan_num = 1;
6023                 }
6024                 vlan_num = vsi->vlan_num;
6025         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6026                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6027                 vlan_num = 1;
6028
6029         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6030         if (mv_f == NULL) {
6031                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6032                 return I40E_ERR_NO_MEMORY;
6033         }
6034
6035         for (i = 0; i < vlan_num; i++) {
6036                 mv_f[i].filter_type = mac_filter->filter_type;
6037                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6038                                 ETH_ADDR_LEN);
6039         }
6040
6041         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6042                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6043                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6044                                         &mac_filter->mac_addr);
6045                 if (ret != I40E_SUCCESS)
6046                         goto DONE;
6047         }
6048
6049         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6050         if (ret != I40E_SUCCESS)
6051                 goto DONE;
6052
6053         /* Add the mac addr into mac list */
6054         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6055         if (f == NULL) {
6056                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6057                 ret = I40E_ERR_NO_MEMORY;
6058                 goto DONE;
6059         }
6060         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6061                         ETH_ADDR_LEN);
6062         f->mac_info.filter_type = mac_filter->filter_type;
6063         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6064         vsi->mac_num++;
6065
6066         ret = I40E_SUCCESS;
6067 DONE:
6068         rte_free(mv_f);
6069
6070         return ret;
6071 }
6072
6073 int
6074 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6075 {
6076         struct i40e_mac_filter *f;
6077         struct i40e_macvlan_filter *mv_f;
6078         int i, vlan_num;
6079         enum rte_mac_filter_type filter_type;
6080         int ret = I40E_SUCCESS;
6081
6082         /* Can't find it, return an error */
6083         f = i40e_find_mac_filter(vsi, addr);
6084         if (f == NULL)
6085                 return I40E_ERR_PARAM;
6086
6087         vlan_num = vsi->vlan_num;
6088         filter_type = f->mac_info.filter_type;
6089         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6090                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6091                 if (vlan_num == 0) {
6092                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6093                         return I40E_ERR_PARAM;
6094                 }
6095         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6096                         filter_type == RTE_MAC_HASH_MATCH)
6097                 vlan_num = 1;
6098
6099         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6100         if (mv_f == NULL) {
6101                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6102                 return I40E_ERR_NO_MEMORY;
6103         }
6104
6105         for (i = 0; i < vlan_num; i++) {
6106                 mv_f[i].filter_type = filter_type;
6107                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6108                                 ETH_ADDR_LEN);
6109         }
6110         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6111                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6112                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6113                 if (ret != I40E_SUCCESS)
6114                         goto DONE;
6115         }
6116
6117         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6118         if (ret != I40E_SUCCESS)
6119                 goto DONE;
6120
6121         /* Remove the mac addr into mac list */
6122         TAILQ_REMOVE(&vsi->mac_list, f, next);
6123         rte_free(f);
6124         vsi->mac_num--;
6125
6126         ret = I40E_SUCCESS;
6127 DONE:
6128         rte_free(mv_f);
6129         return ret;
6130 }
6131
6132 /* Configure hash enable flags for RSS */
6133 uint64_t
6134 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6135 {
6136         uint64_t hena = 0;
6137
6138         if (!flags)
6139                 return hena;
6140
6141         if (flags & ETH_RSS_FRAG_IPV4)
6142                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6143         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6144                 if (type == I40E_MAC_X722) {
6145                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6146                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6147                 } else
6148                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6149         }
6150         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6151                 if (type == I40E_MAC_X722) {
6152                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6153                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6154                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6155                 } else
6156                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6157         }
6158         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6159                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6160         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6161                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6162         if (flags & ETH_RSS_FRAG_IPV6)
6163                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6164         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6165                 if (type == I40E_MAC_X722) {
6166                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6167                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6168                 } else
6169                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6170         }
6171         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6172                 if (type == I40E_MAC_X722) {
6173                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6174                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6175                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6176                 } else
6177                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6178         }
6179         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6180                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6181         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6182                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6183         if (flags & ETH_RSS_L2_PAYLOAD)
6184                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6185
6186         return hena;
6187 }
6188
6189 /* Parse the hash enable flags */
6190 uint64_t
6191 i40e_parse_hena(uint64_t flags)
6192 {
6193         uint64_t rss_hf = 0;
6194
6195         if (!flags)
6196                 return rss_hf;
6197         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6198                 rss_hf |= ETH_RSS_FRAG_IPV4;
6199         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6200                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6201 #ifdef X722_SUPPORT
6202         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6203                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6204 #endif
6205         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6206                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6207 #ifdef X722_SUPPORT
6208         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6209                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6210         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6211                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6212 #endif
6213         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6214                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6215         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6216                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6217         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6218                 rss_hf |= ETH_RSS_FRAG_IPV6;
6219         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6220                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6221 #ifdef X722_SUPPORT
6222         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6223                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6224 #endif
6225         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6226                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6227 #ifdef X722_SUPPORT
6228         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6229                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6230         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6231                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6232 #endif
6233         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6234                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6235         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6236                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6237         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6238                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6239
6240         return rss_hf;
6241 }
6242
6243 /* Disable RSS */
6244 static void
6245 i40e_pf_disable_rss(struct i40e_pf *pf)
6246 {
6247         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6248         uint64_t hena;
6249
6250         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6251         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6252         if (hw->mac.type == I40E_MAC_X722)
6253                 hena &= ~I40E_RSS_HENA_ALL_X722;
6254         else
6255                 hena &= ~I40E_RSS_HENA_ALL;
6256         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6257         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6258         I40E_WRITE_FLUSH(hw);
6259 }
6260
6261 static int
6262 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6263 {
6264         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6265         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6266         int ret = 0;
6267
6268         if (!key || key_len == 0) {
6269                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6270                 return 0;
6271         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6272                 sizeof(uint32_t)) {
6273                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6274                 return -EINVAL;
6275         }
6276
6277         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6278                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6279                         (struct i40e_aqc_get_set_rss_key_data *)key;
6280
6281                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6282                 if (ret)
6283                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6284                                      "via AQ");
6285         } else {
6286                 uint32_t *hash_key = (uint32_t *)key;
6287                 uint16_t i;
6288
6289                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6290                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6291                 I40E_WRITE_FLUSH(hw);
6292         }
6293
6294         return ret;
6295 }
6296
6297 static int
6298 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6299 {
6300         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6301         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6302         int ret;
6303
6304         if (!key || !key_len)
6305                 return -EINVAL;
6306
6307         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6308                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6309                         (struct i40e_aqc_get_set_rss_key_data *)key);
6310                 if (ret) {
6311                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6312                         return ret;
6313                 }
6314         } else {
6315                 uint32_t *key_dw = (uint32_t *)key;
6316                 uint16_t i;
6317
6318                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6319                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6320         }
6321         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6322
6323         return 0;
6324 }
6325
6326 static int
6327 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6328 {
6329         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6330         uint64_t rss_hf;
6331         uint64_t hena;
6332         int ret;
6333
6334         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6335                                rss_conf->rss_key_len);
6336         if (ret)
6337                 return ret;
6338
6339         rss_hf = rss_conf->rss_hf;
6340         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6341         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6342         if (hw->mac.type == I40E_MAC_X722)
6343                 hena &= ~I40E_RSS_HENA_ALL_X722;
6344         else
6345                 hena &= ~I40E_RSS_HENA_ALL;
6346         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6347         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6348         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6349         I40E_WRITE_FLUSH(hw);
6350
6351         return 0;
6352 }
6353
6354 static int
6355 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6356                          struct rte_eth_rss_conf *rss_conf)
6357 {
6358         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6360         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6361         uint64_t hena;
6362
6363         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6364         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6365         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6366                  ? I40E_RSS_HENA_ALL_X722
6367                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6368                 if (rss_hf != 0) /* Enable RSS */
6369                         return -EINVAL;
6370                 return 0; /* Nothing to do */
6371         }
6372         /* RSS enabled */
6373         if (rss_hf == 0) /* Disable RSS */
6374                 return -EINVAL;
6375
6376         return i40e_hw_rss_hash_set(pf, rss_conf);
6377 }
6378
6379 static int
6380 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6381                            struct rte_eth_rss_conf *rss_conf)
6382 {
6383         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6384         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6385         uint64_t hena;
6386
6387         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6388                          &rss_conf->rss_key_len);
6389
6390         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6391         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6392         rss_conf->rss_hf = i40e_parse_hena(hena);
6393
6394         return 0;
6395 }
6396
6397 static int
6398 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6399 {
6400         switch (filter_type) {
6401         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6402                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6403                 break;
6404         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6405                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6406                 break;
6407         case RTE_TUNNEL_FILTER_IMAC_TENID:
6408                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6409                 break;
6410         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6411                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6412                 break;
6413         case ETH_TUNNEL_FILTER_IMAC:
6414                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6415                 break;
6416         case ETH_TUNNEL_FILTER_OIP:
6417                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6418                 break;
6419         case ETH_TUNNEL_FILTER_IIP:
6420                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6421                 break;
6422         default:
6423                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6424                 return -EINVAL;
6425         }
6426
6427         return 0;
6428 }
6429
6430 static int
6431 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6432                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6433                         uint8_t add)
6434 {
6435         uint16_t ip_type;
6436         uint32_t ipv4_addr;
6437         uint8_t i, tun_type = 0;
6438         /* internal varialbe to convert ipv6 byte order */
6439         uint32_t convert_ipv6[4];
6440         int val, ret = 0;
6441         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6442         struct i40e_vsi *vsi = pf->main_vsi;
6443         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6444         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6445
6446         cld_filter = rte_zmalloc("tunnel_filter",
6447                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6448                 0);
6449
6450         if (NULL == cld_filter) {
6451                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6452                 return -EINVAL;
6453         }
6454         pfilter = cld_filter;
6455
6456         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6457         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6458
6459         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6460         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6461                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6462                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6463                 rte_memcpy(&pfilter->ipaddr.v4.data,
6464                                 &rte_cpu_to_le_32(ipv4_addr),
6465                                 sizeof(pfilter->ipaddr.v4.data));
6466         } else {
6467                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6468                 for (i = 0; i < 4; i++) {
6469                         convert_ipv6[i] =
6470                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6471                 }
6472                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6473                                 sizeof(pfilter->ipaddr.v6.data));
6474         }
6475
6476         /* check tunneled type */
6477         switch (tunnel_filter->tunnel_type) {
6478         case RTE_TUNNEL_TYPE_VXLAN:
6479                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6480                 break;
6481         case RTE_TUNNEL_TYPE_NVGRE:
6482                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6483                 break;
6484         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6485                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6486                 break;
6487         default:
6488                 /* Other tunnel types is not supported. */
6489                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6490                 rte_free(cld_filter);
6491                 return -EINVAL;
6492         }
6493
6494         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6495                                                 &pfilter->flags);
6496         if (val < 0) {
6497                 rte_free(cld_filter);
6498                 return -EINVAL;
6499         }
6500
6501         pfilter->flags |= rte_cpu_to_le_16(
6502                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6503                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6504         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6505         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6506
6507         if (add)
6508                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6509         else
6510                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6511                                                 cld_filter, 1);
6512
6513         rte_free(cld_filter);
6514         return ret;
6515 }
6516
6517 static int
6518 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6519 {
6520         uint8_t i;
6521
6522         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6523                 if (pf->vxlan_ports[i] == port)
6524                         return i;
6525         }
6526
6527         return -1;
6528 }
6529
6530 static int
6531 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6532 {
6533         int  idx, ret;
6534         uint8_t filter_idx;
6535         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6536
6537         idx = i40e_get_vxlan_port_idx(pf, port);
6538
6539         /* Check if port already exists */
6540         if (idx >= 0) {
6541                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6542                 return -EINVAL;
6543         }
6544
6545         /* Now check if there is space to add the new port */
6546         idx = i40e_get_vxlan_port_idx(pf, 0);
6547         if (idx < 0) {
6548                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6549                         "not adding port %d", port);
6550                 return -ENOSPC;
6551         }
6552
6553         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6554                                         &filter_idx, NULL);
6555         if (ret < 0) {
6556                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6557                 return -1;
6558         }
6559
6560         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6561                          port,  filter_idx);
6562
6563         /* New port: add it and mark its index in the bitmap */
6564         pf->vxlan_ports[idx] = port;
6565         pf->vxlan_bitmap |= (1 << idx);
6566
6567         if (!(pf->flags & I40E_FLAG_VXLAN))
6568                 pf->flags |= I40E_FLAG_VXLAN;
6569
6570         return 0;
6571 }
6572
6573 static int
6574 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6575 {
6576         int idx;
6577         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6578
6579         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6580                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6581                 return -EINVAL;
6582         }
6583
6584         idx = i40e_get_vxlan_port_idx(pf, port);
6585
6586         if (idx < 0) {
6587                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6588                 return -EINVAL;
6589         }
6590
6591         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6592                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6593                 return -1;
6594         }
6595
6596         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6597                         port, idx);
6598
6599         pf->vxlan_ports[idx] = 0;
6600         pf->vxlan_bitmap &= ~(1 << idx);
6601
6602         if (!pf->vxlan_bitmap)
6603                 pf->flags &= ~I40E_FLAG_VXLAN;
6604
6605         return 0;
6606 }
6607
6608 /* Add UDP tunneling port */
6609 static int
6610 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6611                              struct rte_eth_udp_tunnel *udp_tunnel)
6612 {
6613         int ret = 0;
6614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6615
6616         if (udp_tunnel == NULL)
6617                 return -EINVAL;
6618
6619         switch (udp_tunnel->prot_type) {
6620         case RTE_TUNNEL_TYPE_VXLAN:
6621                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6622                 break;
6623
6624         case RTE_TUNNEL_TYPE_GENEVE:
6625         case RTE_TUNNEL_TYPE_TEREDO:
6626                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6627                 ret = -1;
6628                 break;
6629
6630         default:
6631                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6632                 ret = -1;
6633                 break;
6634         }
6635
6636         return ret;
6637 }
6638
6639 /* Remove UDP tunneling port */
6640 static int
6641 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6642                              struct rte_eth_udp_tunnel *udp_tunnel)
6643 {
6644         int ret = 0;
6645         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6646
6647         if (udp_tunnel == NULL)
6648                 return -EINVAL;
6649
6650         switch (udp_tunnel->prot_type) {
6651         case RTE_TUNNEL_TYPE_VXLAN:
6652                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6653                 break;
6654         case RTE_TUNNEL_TYPE_GENEVE:
6655         case RTE_TUNNEL_TYPE_TEREDO:
6656                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6657                 ret = -1;
6658                 break;
6659         default:
6660                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6661                 ret = -1;
6662                 break;
6663         }
6664
6665         return ret;
6666 }
6667
6668 /* Calculate the maximum number of contiguous PF queues that are configured */
6669 static int
6670 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6671 {
6672         struct rte_eth_dev_data *data = pf->dev_data;
6673         int i, num;
6674         struct i40e_rx_queue *rxq;
6675
6676         num = 0;
6677         for (i = 0; i < pf->lan_nb_qps; i++) {
6678                 rxq = data->rx_queues[i];
6679                 if (rxq && rxq->q_set)
6680                         num++;
6681                 else
6682                         break;
6683         }
6684
6685         return num;
6686 }
6687
6688 /* Configure RSS */
6689 static int
6690 i40e_pf_config_rss(struct i40e_pf *pf)
6691 {
6692         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6693         struct rte_eth_rss_conf rss_conf;
6694         uint32_t i, lut = 0;
6695         uint16_t j, num;
6696
6697         /*
6698          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6699          * It's necessary to calulate the actual PF queues that are configured.
6700          */
6701         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6702                 num = i40e_pf_calc_configured_queues_num(pf);
6703         else
6704                 num = pf->dev_data->nb_rx_queues;
6705
6706         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6707         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6708                         num);
6709
6710         if (num == 0) {
6711                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6712                 return -ENOTSUP;
6713         }
6714
6715         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6716                 if (j == num)
6717                         j = 0;
6718                 lut = (lut << 8) | (j & ((0x1 <<
6719                         hw->func_caps.rss_table_entry_width) - 1));
6720                 if ((i & 3) == 3)
6721                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6722         }
6723
6724         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6725         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6726                 i40e_pf_disable_rss(pf);
6727                 return 0;
6728         }
6729         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6730                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6731                 /* Random default keys */
6732                 static uint32_t rss_key_default[] = {0x6b793944,
6733                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6734                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6735                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6736
6737                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6738                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6739                                                         sizeof(uint32_t);
6740         }
6741
6742         return i40e_hw_rss_hash_set(pf, &rss_conf);
6743 }
6744
6745 static int
6746 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6747                                struct rte_eth_tunnel_filter_conf *filter)
6748 {
6749         if (pf == NULL || filter == NULL) {
6750                 PMD_DRV_LOG(ERR, "Invalid parameter");
6751                 return -EINVAL;
6752         }
6753
6754         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6755                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6756                 return -EINVAL;
6757         }
6758
6759         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6760                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6761                 return -EINVAL;
6762         }
6763
6764         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6765                 (is_zero_ether_addr(&filter->outer_mac))) {
6766                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6767                 return -EINVAL;
6768         }
6769
6770         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6771                 (is_zero_ether_addr(&filter->inner_mac))) {
6772                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6773                 return -EINVAL;
6774         }
6775
6776         return 0;
6777 }
6778
6779 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6780 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6781 static int
6782 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6783 {
6784         uint32_t val, reg;
6785         int ret = -EINVAL;
6786
6787         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6788         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6789
6790         if (len == 3) {
6791                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6792         } else if (len == 4) {
6793                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6794         } else {
6795                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6796                 return ret;
6797         }
6798
6799         if (reg != val) {
6800                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6801                                                    reg, NULL);
6802                 if (ret != 0)
6803                         return ret;
6804         } else {
6805                 ret = 0;
6806         }
6807         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6808                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6809
6810         return ret;
6811 }
6812
6813 static int
6814 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6815 {
6816         int ret = -EINVAL;
6817
6818         if (!hw || !cfg)
6819                 return -EINVAL;
6820
6821         switch (cfg->cfg_type) {
6822         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6823                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6824                 break;
6825         default:
6826                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6827                 break;
6828         }
6829
6830         return ret;
6831 }
6832
6833 static int
6834 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6835                                enum rte_filter_op filter_op,
6836                                void *arg)
6837 {
6838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6839         int ret = I40E_ERR_PARAM;
6840
6841         switch (filter_op) {
6842         case RTE_ETH_FILTER_SET:
6843                 ret = i40e_dev_global_config_set(hw,
6844                         (struct rte_eth_global_cfg *)arg);
6845                 break;
6846         default:
6847                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6848                 break;
6849         }
6850
6851         return ret;
6852 }
6853
6854 static int
6855 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6856                           enum rte_filter_op filter_op,
6857                           void *arg)
6858 {
6859         struct rte_eth_tunnel_filter_conf *filter;
6860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6861         int ret = I40E_SUCCESS;
6862
6863         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6864
6865         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6866                 return I40E_ERR_PARAM;
6867
6868         switch (filter_op) {
6869         case RTE_ETH_FILTER_NOP:
6870                 if (!(pf->flags & I40E_FLAG_VXLAN))
6871                         ret = I40E_NOT_SUPPORTED;
6872                 break;
6873         case RTE_ETH_FILTER_ADD:
6874                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6875                 break;
6876         case RTE_ETH_FILTER_DELETE:
6877                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6878                 break;
6879         default:
6880                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6881                 ret = I40E_ERR_PARAM;
6882                 break;
6883         }
6884
6885         return ret;
6886 }
6887
6888 static int
6889 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6890 {
6891         int ret = 0;
6892         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6893
6894         /* RSS setup */
6895         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6896                 ret = i40e_pf_config_rss(pf);
6897         else
6898                 i40e_pf_disable_rss(pf);
6899
6900         return ret;
6901 }
6902
6903 /* Get the symmetric hash enable configurations per port */
6904 static void
6905 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6906 {
6907         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6908
6909         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6910 }
6911
6912 /* Set the symmetric hash enable configurations per port */
6913 static void
6914 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6915 {
6916         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6917
6918         if (enable > 0) {
6919                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6920                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6921                                                         "been enabled");
6922                         return;
6923                 }
6924                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6925         } else {
6926                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6927                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6928                                                         "been disabled");
6929                         return;
6930                 }
6931                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6932         }
6933         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6934         I40E_WRITE_FLUSH(hw);
6935 }
6936
6937 /*
6938  * Get global configurations of hash function type and symmetric hash enable
6939  * per flow type (pctype). Note that global configuration means it affects all
6940  * the ports on the same NIC.
6941  */
6942 static int
6943 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6944                                    struct rte_eth_hash_global_conf *g_cfg)
6945 {
6946         uint32_t reg, mask = I40E_FLOW_TYPES;
6947         uint16_t i;
6948         enum i40e_filter_pctype pctype;
6949
6950         memset(g_cfg, 0, sizeof(*g_cfg));
6951         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6952         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6953                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6954         else
6955                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6956         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6957                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6958
6959         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6960                 if (!(mask & (1UL << i)))
6961                         continue;
6962                 mask &= ~(1UL << i);
6963                 /* Bit set indicats the coresponding flow type is supported */
6964                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6965                 /* if flowtype is invalid, continue */
6966                 if (!I40E_VALID_FLOW(i))
6967                         continue;
6968                 pctype = i40e_flowtype_to_pctype(i);
6969                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6970                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6971                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6972         }
6973
6974         return 0;
6975 }
6976
6977 static int
6978 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6979 {
6980         uint32_t i;
6981         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6982
6983         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6984                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6985                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6986                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6987                                                 g_cfg->hash_func);
6988                 return -EINVAL;
6989         }
6990
6991         /*
6992          * As i40e supports less than 32 flow types, only first 32 bits need to
6993          * be checked.
6994          */
6995         mask0 = g_cfg->valid_bit_mask[0];
6996         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6997                 if (i == 0) {
6998                         /* Check if any unsupported flow type configured */
6999                         if ((mask0 | i40e_mask) ^ i40e_mask)
7000                                 goto mask_err;
7001                 } else {
7002                         if (g_cfg->valid_bit_mask[i])
7003                                 goto mask_err;
7004                 }
7005         }
7006
7007         return 0;
7008
7009 mask_err:
7010         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7011
7012         return -EINVAL;
7013 }
7014
7015 /*
7016  * Set global configurations of hash function type and symmetric hash enable
7017  * per flow type (pctype). Note any modifying global configuration will affect
7018  * all the ports on the same NIC.
7019  */
7020 static int
7021 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7022                                    struct rte_eth_hash_global_conf *g_cfg)
7023 {
7024         int ret;
7025         uint16_t i;
7026         uint32_t reg;
7027         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7028         enum i40e_filter_pctype pctype;
7029
7030         /* Check the input parameters */
7031         ret = i40e_hash_global_config_check(g_cfg);
7032         if (ret < 0)
7033                 return ret;
7034
7035         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7036                 if (!(mask0 & (1UL << i)))
7037                         continue;
7038                 mask0 &= ~(1UL << i);
7039                 /* if flowtype is invalid, continue */
7040                 if (!I40E_VALID_FLOW(i))
7041                         continue;
7042                 pctype = i40e_flowtype_to_pctype(i);
7043                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7044                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7045                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7046         }
7047
7048         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7049         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7050                 /* Toeplitz */
7051                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7052                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7053                                                                 "Toeplitz");
7054                         goto out;
7055                 }
7056                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7057         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7058                 /* Simple XOR */
7059                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7060                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7061                                                         "Simple XOR");
7062                         goto out;
7063                 }
7064                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7065         } else
7066                 /* Use the default, and keep it as it is */
7067                 goto out;
7068
7069         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7070
7071 out:
7072         I40E_WRITE_FLUSH(hw);
7073
7074         return 0;
7075 }
7076
7077 /**
7078  * Valid input sets for hash and flow director filters per PCTYPE
7079  */
7080 static uint64_t
7081 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7082                 enum rte_filter_type filter)
7083 {
7084         uint64_t valid;
7085
7086         static const uint64_t valid_hash_inset_table[] = {
7087                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7088                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7089                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7090                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7091                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7092                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7093                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7094                         I40E_INSET_FLEX_PAYLOAD,
7095                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7096                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7097                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7098                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7099                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7100                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7101                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7102                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7103                         I40E_INSET_FLEX_PAYLOAD,
7104 #ifdef X722_SUPPORT
7105                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7106                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7107                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7108                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7109                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7110                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7111                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7112                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7113                         I40E_INSET_FLEX_PAYLOAD,
7114                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7118                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7119                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7120                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7121                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7122                         I40E_INSET_FLEX_PAYLOAD,
7123 #endif
7124                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7125                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7126                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7127                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7128                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7129                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7130                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7131                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7132                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7133 #ifdef X722_SUPPORT
7134                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7135                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7136                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7137                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7138                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7139                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7140                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7141                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7142                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7143 #endif
7144                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7145                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7146                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7147                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7148                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7149                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7150                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7151                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7152                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7153                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7154                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7155                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7156                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7157                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7158                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7159                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7160                         I40E_INSET_FLEX_PAYLOAD,
7161                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7162                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7163                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7164                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7165                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7166                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7167                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7168                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7169                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7170                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7171                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7172                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7173                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7174                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7175                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7176                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7177 #ifdef X722_SUPPORT
7178                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7179                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7180                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7181                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7182                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7183                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7184                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7185                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7186                         I40E_INSET_FLEX_PAYLOAD,
7187                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7188                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7189                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7190                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7191                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7192                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7193                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7194                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7195                         I40E_INSET_FLEX_PAYLOAD,
7196 #endif
7197                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7198                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7199                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7200                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7201                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7202                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7203                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7204                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7205                         I40E_INSET_FLEX_PAYLOAD,
7206 #ifdef X722_SUPPORT
7207                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7208                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7209                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7210                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7211                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7212                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7213                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7214                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7215                         I40E_INSET_FLEX_PAYLOAD,
7216 #endif
7217                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7218                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7219                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7220                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7221                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7222                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7223                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7224                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7225                         I40E_INSET_FLEX_PAYLOAD,
7226                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7227                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7228                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7229                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7230                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7231                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7232                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7233                         I40E_INSET_FLEX_PAYLOAD,
7234                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7235                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7236                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7237                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7238                         I40E_INSET_FLEX_PAYLOAD,
7239         };
7240
7241         /**
7242          * Flow director supports only fields defined in
7243          * union rte_eth_fdir_flow.
7244          */
7245         static const uint64_t valid_fdir_inset_table[] = {
7246                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7247                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7248                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7249                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7250                 I40E_INSET_IPV4_TTL,
7251                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7252                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7253                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7254                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7255                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7256 #ifdef X722_SUPPORT
7257                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7258                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7259                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7260                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7261                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7262                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7263                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7264                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7265                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7266                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7267 #endif
7268                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7269                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7270                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7271                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7272                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7273 #ifdef X722_SUPPORT
7274                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7275                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7276                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7277                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7278                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7279 #endif
7280                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7281                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7282                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7283                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7284                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7285                 I40E_INSET_SCTP_VT,
7286                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7287                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7288                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7289                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7290                 I40E_INSET_IPV4_TTL,
7291                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7292                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7293                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7294                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7295                 I40E_INSET_IPV6_HOP_LIMIT,
7296                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7297                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7298                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7299                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7300                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7301 #ifdef X722_SUPPORT
7302                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7303                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7304                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7305                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7306                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7307                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7309                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7310                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7311                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7312 #endif
7313                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7314                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7315                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7316                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7317                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7318 #ifdef X722_SUPPORT
7319                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7320                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7321                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7322                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7323                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7324 #endif
7325                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7326                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7327                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7328                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7329                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7330                 I40E_INSET_SCTP_VT,
7331                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7332                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7333                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7334                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7335                 I40E_INSET_IPV6_HOP_LIMIT,
7336                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7337                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7338                 I40E_INSET_LAST_ETHER_TYPE,
7339         };
7340
7341         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7342                 return 0;
7343         if (filter == RTE_ETH_FILTER_HASH)
7344                 valid = valid_hash_inset_table[pctype];
7345         else
7346                 valid = valid_fdir_inset_table[pctype];
7347
7348         return valid;
7349 }
7350
7351 /**
7352  * Validate if the input set is allowed for a specific PCTYPE
7353  */
7354 static int
7355 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7356                 enum rte_filter_type filter, uint64_t inset)
7357 {
7358         uint64_t valid;
7359
7360         valid = i40e_get_valid_input_set(pctype, filter);
7361         if (inset & (~valid))
7362                 return -EINVAL;
7363
7364         return 0;
7365 }
7366
7367 /* default input set fields combination per pctype */
7368 static uint64_t
7369 i40e_get_default_input_set(uint16_t pctype)
7370 {
7371         static const uint64_t default_inset_table[] = {
7372                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7373                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7374                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7375                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7376                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7377 #ifdef X722_SUPPORT
7378                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7379                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7380                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7381                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7382                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7383                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7384 #endif
7385                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7386                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7387                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7388 #ifdef X722_SUPPORT
7389                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7390                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7391                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7392 #endif
7393                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7394                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7395                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7396                         I40E_INSET_SCTP_VT,
7397                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7398                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7399                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7400                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7401                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7402                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7403                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7404 #ifdef X722_SUPPORT
7405                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7406                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7407                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7408                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7409                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7411 #endif
7412                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7413                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7414                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7415 #ifdef X722_SUPPORT
7416                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7417                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7418                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7419 #endif
7420                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7421                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7422                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7423                         I40E_INSET_SCTP_VT,
7424                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7425                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7426                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7427                         I40E_INSET_LAST_ETHER_TYPE,
7428         };
7429
7430         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7431                 return 0;
7432
7433         return default_inset_table[pctype];
7434 }
7435
7436 /**
7437  * Parse the input set from index to logical bit masks
7438  */
7439 static int
7440 i40e_parse_input_set(uint64_t *inset,
7441                      enum i40e_filter_pctype pctype,
7442                      enum rte_eth_input_set_field *field,
7443                      uint16_t size)
7444 {
7445         uint16_t i, j;
7446         int ret = -EINVAL;
7447
7448         static const struct {
7449                 enum rte_eth_input_set_field field;
7450                 uint64_t inset;
7451         } inset_convert_table[] = {
7452                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7453                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7454                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7455                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7456                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7457                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7458                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7459                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7460                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7461                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7462                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7463                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7464                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7465                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7466                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7467                         I40E_INSET_IPV6_NEXT_HDR},
7468                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7469                         I40E_INSET_IPV6_HOP_LIMIT},
7470                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7471                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7472                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7473                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7474                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7475                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7476                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7477                         I40E_INSET_SCTP_VT},
7478                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7479                         I40E_INSET_TUNNEL_DMAC},
7480                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7481                         I40E_INSET_VLAN_TUNNEL},
7482                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7483                         I40E_INSET_TUNNEL_ID},
7484                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7485                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7486                         I40E_INSET_FLEX_PAYLOAD_W1},
7487                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7488                         I40E_INSET_FLEX_PAYLOAD_W2},
7489                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7490                         I40E_INSET_FLEX_PAYLOAD_W3},
7491                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7492                         I40E_INSET_FLEX_PAYLOAD_W4},
7493                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7494                         I40E_INSET_FLEX_PAYLOAD_W5},
7495                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7496                         I40E_INSET_FLEX_PAYLOAD_W6},
7497                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7498                         I40E_INSET_FLEX_PAYLOAD_W7},
7499                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7500                         I40E_INSET_FLEX_PAYLOAD_W8},
7501         };
7502
7503         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7504                 return ret;
7505
7506         /* Only one item allowed for default or all */
7507         if (size == 1) {
7508                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7509                         *inset = i40e_get_default_input_set(pctype);
7510                         return 0;
7511                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7512                         *inset = I40E_INSET_NONE;
7513                         return 0;
7514                 }
7515         }
7516
7517         for (i = 0, *inset = 0; i < size; i++) {
7518                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7519                         if (field[i] == inset_convert_table[j].field) {
7520                                 *inset |= inset_convert_table[j].inset;
7521                                 break;
7522                         }
7523                 }
7524
7525                 /* It contains unsupported input set, return immediately */
7526                 if (j == RTE_DIM(inset_convert_table))
7527                         return ret;
7528         }
7529
7530         return 0;
7531 }
7532
7533 /**
7534  * Translate the input set from bit masks to register aware bit masks
7535  * and vice versa
7536  */
7537 static uint64_t
7538 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7539 {
7540         uint64_t val = 0;
7541         uint16_t i;
7542
7543         struct inset_map {
7544                 uint64_t inset;
7545                 uint64_t inset_reg;
7546         };
7547
7548         static const struct inset_map inset_map_common[] = {
7549                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7550                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7551                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7552                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7553                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7554                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7555                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7556                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7557                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7558                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7559                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7560                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7561                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7562                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7563                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7564                 {I40E_INSET_TUNNEL_DMAC,
7565                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7566                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7567                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7568                 {I40E_INSET_TUNNEL_SRC_PORT,
7569                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7570                 {I40E_INSET_TUNNEL_DST_PORT,
7571                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7572                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7573                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7574                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7575                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7576                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7577                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7578                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7579                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7580                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7581         };
7582
7583     /* some different registers map in x722*/
7584         static const struct inset_map inset_map_diff_x722[] = {
7585                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7586                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7587                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7588                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7589         };
7590
7591         static const struct inset_map inset_map_diff_not_x722[] = {
7592                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7593                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7594                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7595                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7596         };
7597
7598         if (input == 0)
7599                 return val;
7600
7601         /* Translate input set to register aware inset */
7602         if (type == I40E_MAC_X722) {
7603                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7604                         if (input & inset_map_diff_x722[i].inset)
7605                                 val |= inset_map_diff_x722[i].inset_reg;
7606                 }
7607         } else {
7608                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7609                         if (input & inset_map_diff_not_x722[i].inset)
7610                                 val |= inset_map_diff_not_x722[i].inset_reg;
7611                 }
7612         }
7613
7614         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7615                 if (input & inset_map_common[i].inset)
7616                         val |= inset_map_common[i].inset_reg;
7617         }
7618
7619         return val;
7620 }
7621
7622 static int
7623 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7624 {
7625         uint8_t i, idx = 0;
7626         uint64_t inset_need_mask = inset;
7627
7628         static const struct {
7629                 uint64_t inset;
7630                 uint32_t mask;
7631         } inset_mask_map[] = {
7632                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7633                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7634                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7635                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7636                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7637                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7638                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7639                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7640         };
7641
7642         if (!inset || !mask || !nb_elem)
7643                 return 0;
7644
7645         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7646                 /* Clear the inset bit, if no MASK is required,
7647                  * for example proto + ttl
7648                  */
7649                 if ((inset & inset_mask_map[i].inset) ==
7650                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7651                         inset_need_mask &= ~inset_mask_map[i].inset;
7652                 if (!inset_need_mask)
7653                         return 0;
7654         }
7655         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7656                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7657                     inset_mask_map[i].inset) {
7658                         if (idx >= nb_elem) {
7659                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7660                                 return -EINVAL;
7661                         }
7662                         mask[idx] = inset_mask_map[i].mask;
7663                         idx++;
7664                 }
7665         }
7666
7667         return idx;
7668 }
7669
7670 static void
7671 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7672 {
7673         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7674
7675         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7676         if (reg != val)
7677                 i40e_write_rx_ctl(hw, addr, val);
7678         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7679                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7680 }
7681
7682 static void
7683 i40e_filter_input_set_init(struct i40e_pf *pf)
7684 {
7685         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7686         enum i40e_filter_pctype pctype;
7687         uint64_t input_set, inset_reg;
7688         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7689         int num, i;
7690
7691         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7692              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7693                 if (hw->mac.type == I40E_MAC_X722) {
7694                         if (!I40E_VALID_PCTYPE_X722(pctype))
7695                                 continue;
7696                 } else {
7697                         if (!I40E_VALID_PCTYPE(pctype))
7698                                 continue;
7699                 }
7700
7701                 input_set = i40e_get_default_input_set(pctype);
7702
7703                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7704                                                    I40E_INSET_MASK_NUM_REG);
7705                 if (num < 0)
7706                         return;
7707                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7708                                         input_set);
7709
7710                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7711                                       (uint32_t)(inset_reg & UINT32_MAX));
7712                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7713                                      (uint32_t)((inset_reg >>
7714                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7715                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7716                                       (uint32_t)(inset_reg & UINT32_MAX));
7717                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7718                                      (uint32_t)((inset_reg >>
7719                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7720
7721                 for (i = 0; i < num; i++) {
7722                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7723                                              mask_reg[i]);
7724                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7725                                              mask_reg[i]);
7726                 }
7727                 /*clear unused mask registers of the pctype */
7728                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7729                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7730                                              0);
7731                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7732                                              0);
7733                 }
7734                 I40E_WRITE_FLUSH(hw);
7735
7736                 /* store the default input set */
7737                 pf->hash_input_set[pctype] = input_set;
7738                 pf->fdir.input_set[pctype] = input_set;
7739         }
7740 }
7741
7742 int
7743 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7744                          struct rte_eth_input_set_conf *conf)
7745 {
7746         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7747         enum i40e_filter_pctype pctype;
7748         uint64_t input_set, inset_reg = 0;
7749         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7750         int ret, i, num;
7751
7752         if (!conf) {
7753                 PMD_DRV_LOG(ERR, "Invalid pointer");
7754                 return -EFAULT;
7755         }
7756         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7757             conf->op != RTE_ETH_INPUT_SET_ADD) {
7758                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7759                 return -EINVAL;
7760         }
7761
7762         if (!I40E_VALID_FLOW(conf->flow_type)) {
7763                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7764                 return -EINVAL;
7765         }
7766
7767         if (hw->mac.type == I40E_MAC_X722) {
7768                 /* get translated pctype value in fd pctype register */
7769                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7770                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7771                         conf->flow_type)));
7772         } else
7773                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7774
7775         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7776                                    conf->inset_size);
7777         if (ret) {
7778                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7779                 return -EINVAL;
7780         }
7781         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7782                                     input_set) != 0) {
7783                 PMD_DRV_LOG(ERR, "Invalid input set");
7784                 return -EINVAL;
7785         }
7786         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7787                 /* get inset value in register */
7788                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7789                 inset_reg <<= I40E_32_BIT_WIDTH;
7790                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7791                 input_set |= pf->hash_input_set[pctype];
7792         }
7793         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7794                                            I40E_INSET_MASK_NUM_REG);
7795         if (num < 0)
7796                 return -EINVAL;
7797
7798         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7799
7800         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7801                               (uint32_t)(inset_reg & UINT32_MAX));
7802         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7803                              (uint32_t)((inset_reg >>
7804                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7805
7806         for (i = 0; i < num; i++)
7807                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7808                                      mask_reg[i]);
7809         /*clear unused mask registers of the pctype */
7810         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7811                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7812                                      0);
7813         I40E_WRITE_FLUSH(hw);
7814
7815         pf->hash_input_set[pctype] = input_set;
7816         return 0;
7817 }
7818
7819 int
7820 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7821                          struct rte_eth_input_set_conf *conf)
7822 {
7823         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7824         enum i40e_filter_pctype pctype;
7825         uint64_t input_set, inset_reg = 0;
7826         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7827         int ret, i, num;
7828
7829         if (!hw || !conf) {
7830                 PMD_DRV_LOG(ERR, "Invalid pointer");
7831                 return -EFAULT;
7832         }
7833         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7834             conf->op != RTE_ETH_INPUT_SET_ADD) {
7835                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7836                 return -EINVAL;
7837         }
7838
7839         if (!I40E_VALID_FLOW(conf->flow_type)) {
7840                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7841                 return -EINVAL;
7842         }
7843
7844         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7845
7846         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7847                                    conf->inset_size);
7848         if (ret) {
7849                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7850                 return -EINVAL;
7851         }
7852         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7853                                     input_set) != 0) {
7854                 PMD_DRV_LOG(ERR, "Invalid input set");
7855                 return -EINVAL;
7856         }
7857
7858         /* get inset value in register */
7859         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7860         inset_reg <<= I40E_32_BIT_WIDTH;
7861         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7862
7863         /* Can not change the inset reg for flex payload for fdir,
7864          * it is done by writing I40E_PRTQF_FD_FLXINSET
7865          * in i40e_set_flex_mask_on_pctype.
7866          */
7867         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7868                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7869         else
7870                 input_set |= pf->fdir.input_set[pctype];
7871         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7872                                            I40E_INSET_MASK_NUM_REG);
7873         if (num < 0)
7874                 return -EINVAL;
7875
7876         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7877
7878         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7879                               (uint32_t)(inset_reg & UINT32_MAX));
7880         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7881                              (uint32_t)((inset_reg >>
7882                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7883
7884         for (i = 0; i < num; i++)
7885                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7886                                      mask_reg[i]);
7887         /*clear unused mask registers of the pctype */
7888         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7889                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7890                                      0);
7891         I40E_WRITE_FLUSH(hw);
7892
7893         pf->fdir.input_set[pctype] = input_set;
7894         return 0;
7895 }
7896
7897 static int
7898 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7899 {
7900         int ret = 0;
7901
7902         if (!hw || !info) {
7903                 PMD_DRV_LOG(ERR, "Invalid pointer");
7904                 return -EFAULT;
7905         }
7906
7907         switch (info->info_type) {
7908         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7909                 i40e_get_symmetric_hash_enable_per_port(hw,
7910                                         &(info->info.enable));
7911                 break;
7912         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7913                 ret = i40e_get_hash_filter_global_config(hw,
7914                                 &(info->info.global_conf));
7915                 break;
7916         default:
7917                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7918                                                         info->info_type);
7919                 ret = -EINVAL;
7920                 break;
7921         }
7922
7923         return ret;
7924 }
7925
7926 static int
7927 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7928 {
7929         int ret = 0;
7930
7931         if (!hw || !info) {
7932                 PMD_DRV_LOG(ERR, "Invalid pointer");
7933                 return -EFAULT;
7934         }
7935
7936         switch (info->info_type) {
7937         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7938                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7939                 break;
7940         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7941                 ret = i40e_set_hash_filter_global_config(hw,
7942                                 &(info->info.global_conf));
7943                 break;
7944         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7945                 ret = i40e_hash_filter_inset_select(hw,
7946                                                &(info->info.input_set_conf));
7947                 break;
7948
7949         default:
7950                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7951                                                         info->info_type);
7952                 ret = -EINVAL;
7953                 break;
7954         }
7955
7956         return ret;
7957 }
7958
7959 /* Operations for hash function */
7960 static int
7961 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7962                       enum rte_filter_op filter_op,
7963                       void *arg)
7964 {
7965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7966         int ret = 0;
7967
7968         switch (filter_op) {
7969         case RTE_ETH_FILTER_NOP:
7970                 break;
7971         case RTE_ETH_FILTER_GET:
7972                 ret = i40e_hash_filter_get(hw,
7973                         (struct rte_eth_hash_filter_info *)arg);
7974                 break;
7975         case RTE_ETH_FILTER_SET:
7976                 ret = i40e_hash_filter_set(hw,
7977                         (struct rte_eth_hash_filter_info *)arg);
7978                 break;
7979         default:
7980                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7981                                                                 filter_op);
7982                 ret = -ENOTSUP;
7983                 break;
7984         }
7985
7986         return ret;
7987 }
7988
7989 /*
7990  * Configure ethertype filter, which can director packet by filtering
7991  * with mac address and ether_type or only ether_type
7992  */
7993 static int
7994 i40e_ethertype_filter_set(struct i40e_pf *pf,
7995                         struct rte_eth_ethertype_filter *filter,
7996                         bool add)
7997 {
7998         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7999         struct i40e_control_filter_stats stats;
8000         uint16_t flags = 0;
8001         int ret;
8002
8003         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8004                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8005                 return -EINVAL;
8006         }
8007         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8008                 filter->ether_type == ETHER_TYPE_IPv6) {
8009                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8010                         " control packet filter.", filter->ether_type);
8011                 return -EINVAL;
8012         }
8013         if (filter->ether_type == ETHER_TYPE_VLAN)
8014                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8015                         " not supported.");
8016
8017         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8018                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8019         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8020                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8021         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8022
8023         memset(&stats, 0, sizeof(stats));
8024         ret = i40e_aq_add_rem_control_packet_filter(hw,
8025                         filter->mac_addr.addr_bytes,
8026                         filter->ether_type, flags,
8027                         pf->main_vsi->seid,
8028                         filter->queue, add, &stats, NULL);
8029
8030         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8031                          " mac_etype_used = %u, etype_used = %u,"
8032                          " mac_etype_free = %u, etype_free = %u\n",
8033                          ret, stats.mac_etype_used, stats.etype_used,
8034                          stats.mac_etype_free, stats.etype_free);
8035         if (ret < 0)
8036                 return -ENOSYS;
8037         return 0;
8038 }
8039
8040 /*
8041  * Handle operations for ethertype filter.
8042  */
8043 static int
8044 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8045                                 enum rte_filter_op filter_op,
8046                                 void *arg)
8047 {
8048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8049         int ret = 0;
8050
8051         if (filter_op == RTE_ETH_FILTER_NOP)
8052                 return ret;
8053
8054         if (arg == NULL) {
8055                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8056                             filter_op);
8057                 return -EINVAL;
8058         }
8059
8060         switch (filter_op) {
8061         case RTE_ETH_FILTER_ADD:
8062                 ret = i40e_ethertype_filter_set(pf,
8063                         (struct rte_eth_ethertype_filter *)arg,
8064                         TRUE);
8065                 break;
8066         case RTE_ETH_FILTER_DELETE:
8067                 ret = i40e_ethertype_filter_set(pf,
8068                         (struct rte_eth_ethertype_filter *)arg,
8069                         FALSE);
8070                 break;
8071         default:
8072                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8073                 ret = -ENOSYS;
8074                 break;
8075         }
8076         return ret;
8077 }
8078
8079 static int
8080 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8081                      enum rte_filter_type filter_type,
8082                      enum rte_filter_op filter_op,
8083                      void *arg)
8084 {
8085         int ret = 0;
8086
8087         if (dev == NULL)
8088                 return -EINVAL;
8089
8090         switch (filter_type) {
8091         case RTE_ETH_FILTER_NONE:
8092                 /* For global configuration */
8093                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8094                 break;
8095         case RTE_ETH_FILTER_HASH:
8096                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8097                 break;
8098         case RTE_ETH_FILTER_MACVLAN:
8099                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8100                 break;
8101         case RTE_ETH_FILTER_ETHERTYPE:
8102                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8103                 break;
8104         case RTE_ETH_FILTER_TUNNEL:
8105                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8106                 break;
8107         case RTE_ETH_FILTER_FDIR:
8108                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8109                 break;
8110         default:
8111                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8112                                                         filter_type);
8113                 ret = -EINVAL;
8114                 break;
8115         }
8116
8117         return ret;
8118 }
8119
8120 /*
8121  * Check and enable Extended Tag.
8122  * Enabling Extended Tag is important for 40G performance.
8123  */
8124 static void
8125 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8126 {
8127         uint32_t buf = 0;
8128         int ret;
8129
8130         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8131                                       PCI_DEV_CAP_REG);
8132         if (ret < 0) {
8133                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8134                             PCI_DEV_CAP_REG);
8135                 return;
8136         }
8137         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8138                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8139                 return;
8140         }
8141
8142         buf = 0;
8143         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8144                                       PCI_DEV_CTRL_REG);
8145         if (ret < 0) {
8146                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8147                             PCI_DEV_CTRL_REG);
8148                 return;
8149         }
8150         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8151                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8152                 return;
8153         }
8154         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8155         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8156                                        PCI_DEV_CTRL_REG);
8157         if (ret < 0) {
8158                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8159                             PCI_DEV_CTRL_REG);
8160                 return;
8161         }
8162 }
8163
8164 /*
8165  * As some registers wouldn't be reset unless a global hardware reset,
8166  * hardware initialization is needed to put those registers into an
8167  * expected initial state.
8168  */
8169 static void
8170 i40e_hw_init(struct rte_eth_dev *dev)
8171 {
8172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8173
8174         i40e_enable_extended_tag(dev);
8175
8176         /* clear the PF Queue Filter control register */
8177         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8178
8179         /* Disable symmetric hash per port */
8180         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8181 }
8182
8183 enum i40e_filter_pctype
8184 i40e_flowtype_to_pctype(uint16_t flow_type)
8185 {
8186         static const enum i40e_filter_pctype pctype_table[] = {
8187                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8188                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8189                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8190                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8191                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8192                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8193                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8194                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8195                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8196                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8197                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8198                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8199                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8200                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8201                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8202                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8203                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8204                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8205                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8206         };
8207
8208         return pctype_table[flow_type];
8209 }
8210
8211 uint16_t
8212 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8213 {
8214         static const uint16_t flowtype_table[] = {
8215                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8216                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8217                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8218 #ifdef X722_SUPPORT
8219                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8220                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8221                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8222                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8223 #endif
8224                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8225                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8226 #ifdef X722_SUPPORT
8227                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8228                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8229 #endif
8230                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8231                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8232                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8233                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8234                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8235                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8236                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8237 #ifdef X722_SUPPORT
8238                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8239                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8240                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8241                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8242 #endif
8243                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8244                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8245 #ifdef X722_SUPPORT
8246                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8247                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8248 #endif
8249                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8250                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8251                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8252                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8253                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8254         };
8255
8256         return flowtype_table[pctype];
8257 }
8258
8259 /*
8260  * On X710, performance number is far from the expectation on recent firmware
8261  * versions; on XL710, performance number is also far from the expectation on
8262  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8263  * mode is enabled and port MAC address is equal to the packet destination MAC
8264  * address. The fix for this issue may not be integrated in the following
8265  * firmware version. So the workaround in software driver is needed. It needs
8266  * to modify the initial values of 3 internal only registers for both X710 and
8267  * XL710. Note that the values for X710 or XL710 could be different, and the
8268  * workaround can be removed when it is fixed in firmware in the future.
8269  */
8270
8271 /* For both X710 and XL710 */
8272 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8273 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8274
8275 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8276 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8277
8278 /* For X710 */
8279 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8280 /* For XL710 */
8281 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8282 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8283
8284 static int
8285 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8286 {
8287         enum i40e_status_code status;
8288         struct i40e_aq_get_phy_abilities_resp phy_ab;
8289         int ret = -ENOTSUP;
8290
8291         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8292                                               NULL);
8293
8294         if (status)
8295                 return ret;
8296
8297         return 0;
8298 }
8299
8300
8301 static void
8302 i40e_configure_registers(struct i40e_hw *hw)
8303 {
8304         static struct {
8305                 uint32_t addr;
8306                 uint64_t val;
8307         } reg_table[] = {
8308                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8309                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8310                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8311         };
8312         uint64_t reg;
8313         uint32_t i;
8314         int ret;
8315
8316         for (i = 0; i < RTE_DIM(reg_table); i++) {
8317                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8318                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8319                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8320                                 reg_table[i].val =
8321                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8322                         else /* For X710 */
8323                                 reg_table[i].val =
8324                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8325                 }
8326
8327                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8328                                                         &reg, NULL);
8329                 if (ret < 0) {
8330                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8331                                                         reg_table[i].addr);
8332                         break;
8333                 }
8334                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8335                                                 reg_table[i].addr, reg);
8336                 if (reg == reg_table[i].val)
8337                         continue;
8338
8339                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8340                                                 reg_table[i].val, NULL);
8341                 if (ret < 0) {
8342                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8343                                 "address of 0x%"PRIx32, reg_table[i].val,
8344                                                         reg_table[i].addr);
8345                         break;
8346                 }
8347                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8348                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8349         }
8350 }
8351
8352 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8353 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8354 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8355 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8356 static int
8357 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8358 {
8359         uint32_t reg;
8360         int ret;
8361
8362         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8363                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8364                 return -EINVAL;
8365         }
8366
8367         /* Configure for double VLAN RX stripping */
8368         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8369         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8370                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8371                 ret = i40e_aq_debug_write_register(hw,
8372                                                    I40E_VSI_TSR(vsi->vsi_id),
8373                                                    reg, NULL);
8374                 if (ret < 0) {
8375                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8376                                     vsi->vsi_id);
8377                         return I40E_ERR_CONFIG;
8378                 }
8379         }
8380
8381         /* Configure for double VLAN TX insertion */
8382         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8383         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8384                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8385                 ret = i40e_aq_debug_write_register(hw,
8386                                                    I40E_VSI_L2TAGSTXVALID(
8387                                                    vsi->vsi_id), reg, NULL);
8388                 if (ret < 0) {
8389                         PMD_DRV_LOG(ERR, "Failed to update "
8390                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8391                         return I40E_ERR_CONFIG;
8392                 }
8393         }
8394
8395         return 0;
8396 }
8397
8398 /**
8399  * i40e_aq_add_mirror_rule
8400  * @hw: pointer to the hardware structure
8401  * @seid: VEB seid to add mirror rule to
8402  * @dst_id: destination vsi seid
8403  * @entries: Buffer which contains the entities to be mirrored
8404  * @count: number of entities contained in the buffer
8405  * @rule_id:the rule_id of the rule to be added
8406  *
8407  * Add a mirror rule for a given veb.
8408  *
8409  **/
8410 static enum i40e_status_code
8411 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8412                         uint16_t seid, uint16_t dst_id,
8413                         uint16_t rule_type, uint16_t *entries,
8414                         uint16_t count, uint16_t *rule_id)
8415 {
8416         struct i40e_aq_desc desc;
8417         struct i40e_aqc_add_delete_mirror_rule cmd;
8418         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8419                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8420                 &desc.params.raw;
8421         uint16_t buff_len;
8422         enum i40e_status_code status;
8423
8424         i40e_fill_default_direct_cmd_desc(&desc,
8425                                           i40e_aqc_opc_add_mirror_rule);
8426         memset(&cmd, 0, sizeof(cmd));
8427
8428         buff_len = sizeof(uint16_t) * count;
8429         desc.datalen = rte_cpu_to_le_16(buff_len);
8430         if (buff_len > 0)
8431                 desc.flags |= rte_cpu_to_le_16(
8432                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8433         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8434                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8435         cmd.num_entries = rte_cpu_to_le_16(count);
8436         cmd.seid = rte_cpu_to_le_16(seid);
8437         cmd.destination = rte_cpu_to_le_16(dst_id);
8438
8439         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8440         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8441         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8442                          "rule_id = %u"
8443                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8444                          hw->aq.asq_last_status, resp->rule_id,
8445                          resp->mirror_rules_used, resp->mirror_rules_free);
8446         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8447
8448         return status;
8449 }
8450
8451 /**
8452  * i40e_aq_del_mirror_rule
8453  * @hw: pointer to the hardware structure
8454  * @seid: VEB seid to add mirror rule to
8455  * @entries: Buffer which contains the entities to be mirrored
8456  * @count: number of entities contained in the buffer
8457  * @rule_id:the rule_id of the rule to be delete
8458  *
8459  * Delete a mirror rule for a given veb.
8460  *
8461  **/
8462 static enum i40e_status_code
8463 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8464                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8465                 uint16_t count, uint16_t rule_id)
8466 {
8467         struct i40e_aq_desc desc;
8468         struct i40e_aqc_add_delete_mirror_rule cmd;
8469         uint16_t buff_len = 0;
8470         enum i40e_status_code status;
8471         void *buff = NULL;
8472
8473         i40e_fill_default_direct_cmd_desc(&desc,
8474                                           i40e_aqc_opc_delete_mirror_rule);
8475         memset(&cmd, 0, sizeof(cmd));
8476         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8477                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8478                                                           I40E_AQ_FLAG_RD));
8479                 cmd.num_entries = count;
8480                 buff_len = sizeof(uint16_t) * count;
8481                 desc.datalen = rte_cpu_to_le_16(buff_len);
8482                 buff = (void *)entries;
8483         } else
8484                 /* rule id is filled in destination field for deleting mirror rule */
8485                 cmd.destination = rte_cpu_to_le_16(rule_id);
8486
8487         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8488                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8489         cmd.seid = rte_cpu_to_le_16(seid);
8490
8491         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8492         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8493
8494         return status;
8495 }
8496
8497 /**
8498  * i40e_mirror_rule_set
8499  * @dev: pointer to the hardware structure
8500  * @mirror_conf: mirror rule info
8501  * @sw_id: mirror rule's sw_id
8502  * @on: enable/disable
8503  *
8504  * set a mirror rule.
8505  *
8506  **/
8507 static int
8508 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8509                         struct rte_eth_mirror_conf *mirror_conf,
8510                         uint8_t sw_id, uint8_t on)
8511 {
8512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8514         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8515         struct i40e_mirror_rule *parent = NULL;
8516         uint16_t seid, dst_seid, rule_id;
8517         uint16_t i, j = 0;
8518         int ret;
8519
8520         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8521
8522         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8523                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8524                         " without veb or vfs.");
8525                 return -ENOSYS;
8526         }
8527         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8528                 PMD_DRV_LOG(ERR, "mirror table is full.");
8529                 return -ENOSPC;
8530         }
8531         if (mirror_conf->dst_pool > pf->vf_num) {
8532                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8533                                  mirror_conf->dst_pool);
8534                 return -EINVAL;
8535         }
8536
8537         seid = pf->main_vsi->veb->seid;
8538
8539         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8540                 if (sw_id <= it->index) {
8541                         mirr_rule = it;
8542                         break;
8543                 }
8544                 parent = it;
8545         }
8546         if (mirr_rule && sw_id == mirr_rule->index) {
8547                 if (on) {
8548                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8549                         return -EEXIST;
8550                 } else {
8551                         ret = i40e_aq_del_mirror_rule(hw, seid,
8552                                         mirr_rule->rule_type,
8553                                         mirr_rule->entries,
8554                                         mirr_rule->num_entries, mirr_rule->id);
8555                         if (ret < 0) {
8556                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8557                                                    " ret = %d, aq_err = %d.",
8558                                                    ret, hw->aq.asq_last_status);
8559                                 return -ENOSYS;
8560                         }
8561                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8562                         rte_free(mirr_rule);
8563                         pf->nb_mirror_rule--;
8564                         return 0;
8565                 }
8566         } else if (!on) {
8567                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8568                 return -ENOENT;
8569         }
8570
8571         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8572                                 sizeof(struct i40e_mirror_rule) , 0);
8573         if (!mirr_rule) {
8574                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8575                 return I40E_ERR_NO_MEMORY;
8576         }
8577         switch (mirror_conf->rule_type) {
8578         case ETH_MIRROR_VLAN:
8579                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8580                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8581                                 mirr_rule->entries[j] =
8582                                         mirror_conf->vlan.vlan_id[i];
8583                                 j++;
8584                         }
8585                 }
8586                 if (j == 0) {
8587                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8588                         rte_free(mirr_rule);
8589                         return -EINVAL;
8590                 }
8591                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8592                 break;
8593         case ETH_MIRROR_VIRTUAL_POOL_UP:
8594         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8595                 /* check if the specified pool bit is out of range */
8596                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8597                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8598                         rte_free(mirr_rule);
8599                         return -EINVAL;
8600                 }
8601                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8602                         if (mirror_conf->pool_mask & (1ULL << i)) {
8603                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8604                                 j++;
8605                         }
8606                 }
8607                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8608                         /* add pf vsi to entries */
8609                         mirr_rule->entries[j] = pf->main_vsi_seid;
8610                         j++;
8611                 }
8612                 if (j == 0) {
8613                         PMD_DRV_LOG(ERR, "pool is not specified.");
8614                         rte_free(mirr_rule);
8615                         return -EINVAL;
8616                 }
8617                 /* egress and ingress in aq commands means from switch but not port */
8618                 mirr_rule->rule_type =
8619                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8620                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8621                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8622                 break;
8623         case ETH_MIRROR_UPLINK_PORT:
8624                 /* egress and ingress in aq commands means from switch but not port*/
8625                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8626                 break;
8627         case ETH_MIRROR_DOWNLINK_PORT:
8628                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8629                 break;
8630         default:
8631                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8632                         mirror_conf->rule_type);
8633                 rte_free(mirr_rule);
8634                 return -EINVAL;
8635         }
8636
8637         /* If the dst_pool is equal to vf_num, consider it as PF */
8638         if (mirror_conf->dst_pool == pf->vf_num)
8639                 dst_seid = pf->main_vsi_seid;
8640         else
8641                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8642
8643         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8644                                       mirr_rule->rule_type, mirr_rule->entries,
8645                                       j, &rule_id);
8646         if (ret < 0) {
8647                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8648                                    " ret = %d, aq_err = %d.",
8649                                    ret, hw->aq.asq_last_status);
8650                 rte_free(mirr_rule);
8651                 return -ENOSYS;
8652         }
8653
8654         mirr_rule->index = sw_id;
8655         mirr_rule->num_entries = j;
8656         mirr_rule->id = rule_id;
8657         mirr_rule->dst_vsi_seid = dst_seid;
8658
8659         if (parent)
8660                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8661         else
8662                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8663
8664         pf->nb_mirror_rule++;
8665         return 0;
8666 }
8667
8668 /**
8669  * i40e_mirror_rule_reset
8670  * @dev: pointer to the device
8671  * @sw_id: mirror rule's sw_id
8672  *
8673  * reset a mirror rule.
8674  *
8675  **/
8676 static int
8677 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8678 {
8679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8681         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8682         uint16_t seid;
8683         int ret;
8684
8685         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8686
8687         seid = pf->main_vsi->veb->seid;
8688
8689         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8690                 if (sw_id == it->index) {
8691                         mirr_rule = it;
8692                         break;
8693                 }
8694         }
8695         if (mirr_rule) {
8696                 ret = i40e_aq_del_mirror_rule(hw, seid,
8697                                 mirr_rule->rule_type,
8698                                 mirr_rule->entries,
8699                                 mirr_rule->num_entries, mirr_rule->id);
8700                 if (ret < 0) {
8701                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8702                                            " status = %d, aq_err = %d.",
8703                                            ret, hw->aq.asq_last_status);
8704                         return -ENOSYS;
8705                 }
8706                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8707                 rte_free(mirr_rule);
8708                 pf->nb_mirror_rule--;
8709         } else {
8710                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8711                 return -ENOENT;
8712         }
8713         return 0;
8714 }
8715
8716 static uint64_t
8717 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8718 {
8719         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8720         uint64_t systim_cycles;
8721
8722         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8723         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8724                         << 32;
8725
8726         return systim_cycles;
8727 }
8728
8729 static uint64_t
8730 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8731 {
8732         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8733         uint64_t rx_tstamp;
8734
8735         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8736         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8737                         << 32;
8738
8739         return rx_tstamp;
8740 }
8741
8742 static uint64_t
8743 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8744 {
8745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8746         uint64_t tx_tstamp;
8747
8748         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8749         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8750                         << 32;
8751
8752         return tx_tstamp;
8753 }
8754
8755 static void
8756 i40e_start_timecounters(struct rte_eth_dev *dev)
8757 {
8758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8759         struct i40e_adapter *adapter =
8760                         (struct i40e_adapter *)dev->data->dev_private;
8761         struct rte_eth_link link;
8762         uint32_t tsync_inc_l;
8763         uint32_t tsync_inc_h;
8764
8765         /* Get current link speed. */
8766         memset(&link, 0, sizeof(link));
8767         i40e_dev_link_update(dev, 1);
8768         rte_i40e_dev_atomic_read_link_status(dev, &link);
8769
8770         switch (link.link_speed) {
8771         case ETH_SPEED_NUM_40G:
8772                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8773                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8774                 break;
8775         case ETH_SPEED_NUM_10G:
8776                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8777                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8778                 break;
8779         case ETH_SPEED_NUM_1G:
8780                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8781                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8782                 break;
8783         default:
8784                 tsync_inc_l = 0x0;
8785                 tsync_inc_h = 0x0;
8786         }
8787
8788         /* Set the timesync increment value. */
8789         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8790         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8791
8792         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8793         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8794         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8795
8796         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8797         adapter->systime_tc.cc_shift = 0;
8798         adapter->systime_tc.nsec_mask = 0;
8799
8800         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8801         adapter->rx_tstamp_tc.cc_shift = 0;
8802         adapter->rx_tstamp_tc.nsec_mask = 0;
8803
8804         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8805         adapter->tx_tstamp_tc.cc_shift = 0;
8806         adapter->tx_tstamp_tc.nsec_mask = 0;
8807 }
8808
8809 static int
8810 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8811 {
8812         struct i40e_adapter *adapter =
8813                         (struct i40e_adapter *)dev->data->dev_private;
8814
8815         adapter->systime_tc.nsec += delta;
8816         adapter->rx_tstamp_tc.nsec += delta;
8817         adapter->tx_tstamp_tc.nsec += delta;
8818
8819         return 0;
8820 }
8821
8822 static int
8823 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8824 {
8825         uint64_t ns;
8826         struct i40e_adapter *adapter =
8827                         (struct i40e_adapter *)dev->data->dev_private;
8828
8829         ns = rte_timespec_to_ns(ts);
8830
8831         /* Set the timecounters to a new value. */
8832         adapter->systime_tc.nsec = ns;
8833         adapter->rx_tstamp_tc.nsec = ns;
8834         adapter->tx_tstamp_tc.nsec = ns;
8835
8836         return 0;
8837 }
8838
8839 static int
8840 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8841 {
8842         uint64_t ns, systime_cycles;
8843         struct i40e_adapter *adapter =
8844                         (struct i40e_adapter *)dev->data->dev_private;
8845
8846         systime_cycles = i40e_read_systime_cyclecounter(dev);
8847         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8848         *ts = rte_ns_to_timespec(ns);
8849
8850         return 0;
8851 }
8852
8853 static int
8854 i40e_timesync_enable(struct rte_eth_dev *dev)
8855 {
8856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8857         uint32_t tsync_ctl_l;
8858         uint32_t tsync_ctl_h;
8859
8860         /* Stop the timesync system time. */
8861         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8862         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8863         /* Reset the timesync system time value. */
8864         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8865         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8866
8867         i40e_start_timecounters(dev);
8868
8869         /* Clear timesync registers. */
8870         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8871         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8872         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8873         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8874         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8875         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8876
8877         /* Enable timestamping of PTP packets. */
8878         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8879         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8880
8881         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8882         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8883         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8884
8885         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8886         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8887
8888         return 0;
8889 }
8890
8891 static int
8892 i40e_timesync_disable(struct rte_eth_dev *dev)
8893 {
8894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8895         uint32_t tsync_ctl_l;
8896         uint32_t tsync_ctl_h;
8897
8898         /* Disable timestamping of transmitted PTP packets. */
8899         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8900         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8901
8902         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8903         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8904
8905         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8906         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8907
8908         /* Reset the timesync increment value. */
8909         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8910         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8911
8912         return 0;
8913 }
8914
8915 static int
8916 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8917                                 struct timespec *timestamp, uint32_t flags)
8918 {
8919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8920         struct i40e_adapter *adapter =
8921                 (struct i40e_adapter *)dev->data->dev_private;
8922
8923         uint32_t sync_status;
8924         uint32_t index = flags & 0x03;
8925         uint64_t rx_tstamp_cycles;
8926         uint64_t ns;
8927
8928         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8929         if ((sync_status & (1 << index)) == 0)
8930                 return -EINVAL;
8931
8932         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8933         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8934         *timestamp = rte_ns_to_timespec(ns);
8935
8936         return 0;
8937 }
8938
8939 static int
8940 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8941                                 struct timespec *timestamp)
8942 {
8943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8944         struct i40e_adapter *adapter =
8945                 (struct i40e_adapter *)dev->data->dev_private;
8946
8947         uint32_t sync_status;
8948         uint64_t tx_tstamp_cycles;
8949         uint64_t ns;
8950
8951         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8952         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8953                 return -EINVAL;
8954
8955         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8956         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8957         *timestamp = rte_ns_to_timespec(ns);
8958
8959         return 0;
8960 }
8961
8962 /*
8963  * i40e_parse_dcb_configure - parse dcb configure from user
8964  * @dev: the device being configured
8965  * @dcb_cfg: pointer of the result of parse
8966  * @*tc_map: bit map of enabled traffic classes
8967  *
8968  * Returns 0 on success, negative value on failure
8969  */
8970 static int
8971 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8972                          struct i40e_dcbx_config *dcb_cfg,
8973                          uint8_t *tc_map)
8974 {
8975         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8976         uint8_t i, tc_bw, bw_lf;
8977
8978         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8979
8980         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8981         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8982                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8983                 return -EINVAL;
8984         }
8985
8986         /* assume each tc has the same bw */
8987         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8988         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8989                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8990         /* to ensure the sum of tcbw is equal to 100 */
8991         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8992         for (i = 0; i < bw_lf; i++)
8993                 dcb_cfg->etscfg.tcbwtable[i]++;
8994
8995         /* assume each tc has the same Transmission Selection Algorithm */
8996         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8997                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8998
8999         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9000                 dcb_cfg->etscfg.prioritytable[i] =
9001                                 dcb_rx_conf->dcb_tc[i];
9002
9003         /* FW needs one App to configure HW */
9004         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9005         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9006         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9007         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9008
9009         if (dcb_rx_conf->nb_tcs == 0)
9010                 *tc_map = 1; /* tc0 only */
9011         else
9012                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9013
9014         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9015                 dcb_cfg->pfc.willing = 0;
9016                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9017                 dcb_cfg->pfc.pfcenable = *tc_map;
9018         }
9019         return 0;
9020 }
9021
9022
9023 static enum i40e_status_code
9024 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9025                               struct i40e_aqc_vsi_properties_data *info,
9026                               uint8_t enabled_tcmap)
9027 {
9028         enum i40e_status_code ret;
9029         int i, total_tc = 0;
9030         uint16_t qpnum_per_tc, bsf, qp_idx;
9031         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9032         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9033         uint16_t used_queues;
9034
9035         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9036         if (ret != I40E_SUCCESS)
9037                 return ret;
9038
9039         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9040                 if (enabled_tcmap & (1 << i))
9041                         total_tc++;
9042         }
9043         if (total_tc == 0)
9044                 total_tc = 1;
9045         vsi->enabled_tc = enabled_tcmap;
9046
9047         /* different VSI has different queues assigned */
9048         if (vsi->type == I40E_VSI_MAIN)
9049                 used_queues = dev_data->nb_rx_queues -
9050                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9051         else if (vsi->type == I40E_VSI_VMDQ2)
9052                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9053         else {
9054                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9055                 return I40E_ERR_NO_AVAILABLE_VSI;
9056         }
9057
9058         qpnum_per_tc = used_queues / total_tc;
9059         /* Number of queues per enabled TC */
9060         if (qpnum_per_tc == 0) {
9061                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9062                 return I40E_ERR_INVALID_QP_ID;
9063         }
9064         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9065                                 I40E_MAX_Q_PER_TC);
9066         bsf = rte_bsf32(qpnum_per_tc);
9067
9068         /**
9069          * Configure TC and queue mapping parameters, for enabled TC,
9070          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9071          * default queue will serve it.
9072          */
9073         qp_idx = 0;
9074         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9075                 if (vsi->enabled_tc & (1 << i)) {
9076                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9077                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9078                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9079                         qp_idx += qpnum_per_tc;
9080                 } else
9081                         info->tc_mapping[i] = 0;
9082         }
9083
9084         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9085         if (vsi->type == I40E_VSI_SRIOV) {
9086                 info->mapping_flags |=
9087                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9088                 for (i = 0; i < vsi->nb_qps; i++)
9089                         info->queue_mapping[i] =
9090                                 rte_cpu_to_le_16(vsi->base_queue + i);
9091         } else {
9092                 info->mapping_flags |=
9093                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9094                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9095         }
9096         info->valid_sections |=
9097                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9098
9099         return I40E_SUCCESS;
9100 }
9101
9102 /*
9103  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9104  * @veb: VEB to be configured
9105  * @tc_map: enabled TC bitmap
9106  *
9107  * Returns 0 on success, negative value on failure
9108  */
9109 static enum i40e_status_code
9110 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9111 {
9112         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9113         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9114         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9115         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9116         enum i40e_status_code ret = I40E_SUCCESS;
9117         int i;
9118         uint32_t bw_max;
9119
9120         /* Check if enabled_tc is same as existing or new TCs */
9121         if (veb->enabled_tc == tc_map)
9122                 return ret;
9123
9124         /* configure tc bandwidth */
9125         memset(&veb_bw, 0, sizeof(veb_bw));
9126         veb_bw.tc_valid_bits = tc_map;
9127         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9128         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9129                 if (tc_map & BIT_ULL(i))
9130                         veb_bw.tc_bw_share_credits[i] = 1;
9131         }
9132         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9133                                                    &veb_bw, NULL);
9134         if (ret) {
9135                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9136                                   " per TC failed = %d",
9137                                   hw->aq.asq_last_status);
9138                 return ret;
9139         }
9140
9141         memset(&ets_query, 0, sizeof(ets_query));
9142         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9143                                                    &ets_query, NULL);
9144         if (ret != I40E_SUCCESS) {
9145                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9146                                  " configuration %u", hw->aq.asq_last_status);
9147                 return ret;
9148         }
9149         memset(&bw_query, 0, sizeof(bw_query));
9150         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9151                                                   &bw_query, NULL);
9152         if (ret != I40E_SUCCESS) {
9153                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9154                                  " configuration %u", hw->aq.asq_last_status);
9155                 return ret;
9156         }
9157
9158         /* store and print out BW info */
9159         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9160         veb->bw_info.bw_max = ets_query.tc_bw_max;
9161         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9162         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9163         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9164                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9165                      I40E_16_BIT_WIDTH);
9166         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9167                 veb->bw_info.bw_ets_share_credits[i] =
9168                                 bw_query.tc_bw_share_credits[i];
9169                 veb->bw_info.bw_ets_credits[i] =
9170                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9171                 /* 4 bits per TC, 4th bit is reserved */
9172                 veb->bw_info.bw_ets_max[i] =
9173                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9174                                   RTE_LEN2MASK(3, uint8_t));
9175                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9176                             veb->bw_info.bw_ets_share_credits[i]);
9177                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9178                             veb->bw_info.bw_ets_credits[i]);
9179                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9180                             veb->bw_info.bw_ets_max[i]);
9181         }
9182
9183         veb->enabled_tc = tc_map;
9184
9185         return ret;
9186 }
9187
9188
9189 /*
9190  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9191  * @vsi: VSI to be configured
9192  * @tc_map: enabled TC bitmap
9193  *
9194  * Returns 0 on success, negative value on failure
9195  */
9196 static enum i40e_status_code
9197 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9198 {
9199         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9200         struct i40e_vsi_context ctxt;
9201         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9202         enum i40e_status_code ret = I40E_SUCCESS;
9203         int i;
9204
9205         /* Check if enabled_tc is same as existing or new TCs */
9206         if (vsi->enabled_tc == tc_map)
9207                 return ret;
9208
9209         /* configure tc bandwidth */
9210         memset(&bw_data, 0, sizeof(bw_data));
9211         bw_data.tc_valid_bits = tc_map;
9212         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9213         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9214                 if (tc_map & BIT_ULL(i))
9215                         bw_data.tc_bw_credits[i] = 1;
9216         }
9217         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9218         if (ret) {
9219                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9220                         " per TC failed = %d",
9221                         hw->aq.asq_last_status);
9222                 goto out;
9223         }
9224         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9225                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9226
9227         /* Update Queue Pairs Mapping for currently enabled UPs */
9228         ctxt.seid = vsi->seid;
9229         ctxt.pf_num = hw->pf_id;
9230         ctxt.vf_num = 0;
9231         ctxt.uplink_seid = vsi->uplink_seid;
9232         ctxt.info = vsi->info;
9233         i40e_get_cap(hw);
9234         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9235         if (ret)
9236                 goto out;
9237
9238         /* Update the VSI after updating the VSI queue-mapping information */
9239         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9240         if (ret) {
9241                 PMD_INIT_LOG(ERR, "Failed to configure "
9242                             "TC queue mapping = %d",
9243                             hw->aq.asq_last_status);
9244                 goto out;
9245         }
9246         /* update the local VSI info with updated queue map */
9247         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9248                                         sizeof(vsi->info.tc_mapping));
9249         (void)rte_memcpy(&vsi->info.queue_mapping,
9250                         &ctxt.info.queue_mapping,
9251                 sizeof(vsi->info.queue_mapping));
9252         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9253         vsi->info.valid_sections = 0;
9254
9255         /* query and update current VSI BW information */
9256         ret = i40e_vsi_get_bw_config(vsi);
9257         if (ret) {
9258                 PMD_INIT_LOG(ERR,
9259                          "Failed updating vsi bw info, err %s aq_err %s",
9260                          i40e_stat_str(hw, ret),
9261                          i40e_aq_str(hw, hw->aq.asq_last_status));
9262                 goto out;
9263         }
9264
9265         vsi->enabled_tc = tc_map;
9266
9267 out:
9268         return ret;
9269 }
9270
9271 /*
9272  * i40e_dcb_hw_configure - program the dcb setting to hw
9273  * @pf: pf the configuration is taken on
9274  * @new_cfg: new configuration
9275  * @tc_map: enabled TC bitmap
9276  *
9277  * Returns 0 on success, negative value on failure
9278  */
9279 static enum i40e_status_code
9280 i40e_dcb_hw_configure(struct i40e_pf *pf,
9281                       struct i40e_dcbx_config *new_cfg,
9282                       uint8_t tc_map)
9283 {
9284         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9285         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9286         struct i40e_vsi *main_vsi = pf->main_vsi;
9287         struct i40e_vsi_list *vsi_list;
9288         enum i40e_status_code ret;
9289         int i;
9290         uint32_t val;
9291
9292         /* Use the FW API if FW > v4.4*/
9293         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9294               (hw->aq.fw_maj_ver >= 5))) {
9295                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9296                                   " to configure DCB");
9297                 return I40E_ERR_FIRMWARE_API_VERSION;
9298         }
9299
9300         /* Check if need reconfiguration */
9301         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9302                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9303                 return I40E_SUCCESS;
9304         }
9305
9306         /* Copy the new config to the current config */
9307         *old_cfg = *new_cfg;
9308         old_cfg->etsrec = old_cfg->etscfg;
9309         ret = i40e_set_dcb_config(hw);
9310         if (ret) {
9311                 PMD_INIT_LOG(ERR,
9312                          "Set DCB Config failed, err %s aq_err %s\n",
9313                          i40e_stat_str(hw, ret),
9314                          i40e_aq_str(hw, hw->aq.asq_last_status));
9315                 return ret;
9316         }
9317         /* set receive Arbiter to RR mode and ETS scheme by default */
9318         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9319                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9320                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9321                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9322                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9323                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9324                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9325                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9326                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9327                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9328                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9329                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9330                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9331         }
9332         /* get local mib to check whether it is configured correctly */
9333         /* IEEE mode */
9334         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9335         /* Get Local DCB Config */
9336         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9337                                      &hw->local_dcbx_config);
9338
9339         /* if Veb is created, need to update TC of it at first */
9340         if (main_vsi->veb) {
9341                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9342                 if (ret)
9343                         PMD_INIT_LOG(WARNING,
9344                                  "Failed configuring TC for VEB seid=%d\n",
9345                                  main_vsi->veb->seid);
9346         }
9347         /* Update each VSI */
9348         i40e_vsi_config_tc(main_vsi, tc_map);
9349         if (main_vsi->veb) {
9350                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9351                         /* Beside main VSI and VMDQ VSIs, only enable default
9352                          * TC for other VSIs
9353                          */
9354                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9355                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9356                                                          tc_map);
9357                         else
9358                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9359                                                          I40E_DEFAULT_TCMAP);
9360                         if (ret)
9361                                 PMD_INIT_LOG(WARNING,
9362                                          "Failed configuring TC for VSI seid=%d\n",
9363                                          vsi_list->vsi->seid);
9364                         /* continue */
9365                 }
9366         }
9367         return I40E_SUCCESS;
9368 }
9369
9370 /*
9371  * i40e_dcb_init_configure - initial dcb config
9372  * @dev: device being configured
9373  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9374  *
9375  * Returns 0 on success, negative value on failure
9376  */
9377 static int
9378 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9379 {
9380         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9381         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9382         int ret = 0;
9383
9384         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9385                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9386                 return -ENOTSUP;
9387         }
9388
9389         /* DCB initialization:
9390          * Update DCB configuration from the Firmware and configure
9391          * LLDP MIB change event.
9392          */
9393         if (sw_dcb == TRUE) {
9394                 ret = i40e_init_dcb(hw);
9395                 /* If lldp agent is stopped, the return value from
9396                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9397                  * adminq status. Otherwise, it should return success.
9398                  */
9399                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9400                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9401                         memset(&hw->local_dcbx_config, 0,
9402                                 sizeof(struct i40e_dcbx_config));
9403                         /* set dcb default configuration */
9404                         hw->local_dcbx_config.etscfg.willing = 0;
9405                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9406                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9407                         hw->local_dcbx_config.etscfg.tsatable[0] =
9408                                                 I40E_IEEE_TSA_ETS;
9409                         hw->local_dcbx_config.etsrec =
9410                                 hw->local_dcbx_config.etscfg;
9411                         hw->local_dcbx_config.pfc.willing = 0;
9412                         hw->local_dcbx_config.pfc.pfccap =
9413                                                 I40E_MAX_TRAFFIC_CLASS;
9414                         /* FW needs one App to configure HW */
9415                         hw->local_dcbx_config.numapps = 1;
9416                         hw->local_dcbx_config.app[0].selector =
9417                                                 I40E_APP_SEL_ETHTYPE;
9418                         hw->local_dcbx_config.app[0].priority = 3;
9419                         hw->local_dcbx_config.app[0].protocolid =
9420                                                 I40E_APP_PROTOID_FCOE;
9421                         ret = i40e_set_dcb_config(hw);
9422                         if (ret) {
9423                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9424                                         " err = %d, aq_err = %d.", ret,
9425                                           hw->aq.asq_last_status);
9426                                 return -ENOSYS;
9427                         }
9428                 } else {
9429                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9430                                           " err = %d, aq_err = %d.", ret,
9431                                           hw->aq.asq_last_status);
9432                         return -ENOTSUP;
9433                 }
9434         } else {
9435                 ret = i40e_aq_start_lldp(hw, NULL);
9436                 if (ret != I40E_SUCCESS)
9437                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9438
9439                 ret = i40e_init_dcb(hw);
9440                 if (!ret) {
9441                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9442                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9443                                                   " DCBX offload.");
9444                                 return -ENOTSUP;
9445                         }
9446                 } else {
9447                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9448                                           " aq_err = %d.", ret,
9449                                           hw->aq.asq_last_status);
9450                         return -ENOTSUP;
9451                 }
9452         }
9453         return 0;
9454 }
9455
9456 /*
9457  * i40e_dcb_setup - setup dcb related config
9458  * @dev: device being configured
9459  *
9460  * Returns 0 on success, negative value on failure
9461  */
9462 static int
9463 i40e_dcb_setup(struct rte_eth_dev *dev)
9464 {
9465         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9466         struct i40e_dcbx_config dcb_cfg;
9467         uint8_t tc_map = 0;
9468         int ret = 0;
9469
9470         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9471                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9472                 return -ENOTSUP;
9473         }
9474
9475         if (pf->vf_num != 0)
9476                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9477
9478         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9479         if (ret) {
9480                 PMD_INIT_LOG(ERR, "invalid dcb config");
9481                 return -EINVAL;
9482         }
9483         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9484         if (ret) {
9485                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9486                 return -ENOSYS;
9487         }
9488
9489         return 0;
9490 }
9491
9492 static int
9493 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9494                       struct rte_eth_dcb_info *dcb_info)
9495 {
9496         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9497         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9498         struct i40e_vsi *vsi = pf->main_vsi;
9499         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9500         uint16_t bsf, tc_mapping;
9501         int i, j = 0;
9502
9503         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9504                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9505         else
9506                 dcb_info->nb_tcs = 1;
9507         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9508                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9509         for (i = 0; i < dcb_info->nb_tcs; i++)
9510                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9511
9512         /* get queue mapping if vmdq is disabled */
9513         if (!pf->nb_cfg_vmdq_vsi) {
9514                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9515                         if (!(vsi->enabled_tc & (1 << i)))
9516                                 continue;
9517                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9518                         dcb_info->tc_queue.tc_rxq[j][i].base =
9519                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9520                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9521                         dcb_info->tc_queue.tc_txq[j][i].base =
9522                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9523                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9524                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9525                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9526                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9527                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9528                 }
9529                 return 0;
9530         }
9531
9532         /* get queue mapping if vmdq is enabled */
9533         do {
9534                 vsi = pf->vmdq[j].vsi;
9535                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9536                         if (!(vsi->enabled_tc & (1 << i)))
9537                                 continue;
9538                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9539                         dcb_info->tc_queue.tc_rxq[j][i].base =
9540                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9541                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9542                         dcb_info->tc_queue.tc_txq[j][i].base =
9543                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9544                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9545                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9546                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9547                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9548                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9549                 }
9550                 j++;
9551         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9552         return 0;
9553 }
9554
9555 static int
9556 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9557 {
9558         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9560         uint16_t interval =
9561                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9562         uint16_t msix_intr;
9563
9564         msix_intr = intr_handle->intr_vec[queue_id];
9565         if (msix_intr == I40E_MISC_VEC_ID)
9566                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9567                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9568                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9569                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9570                                (interval <<
9571                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9572         else
9573                 I40E_WRITE_REG(hw,
9574                                I40E_PFINT_DYN_CTLN(msix_intr -
9575                                                    I40E_RX_VEC_START),
9576                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9577                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9578                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9579                                (interval <<
9580                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9581
9582         I40E_WRITE_FLUSH(hw);
9583         rte_intr_enable(&dev->pci_dev->intr_handle);
9584
9585         return 0;
9586 }
9587
9588 static int
9589 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9590 {
9591         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9593         uint16_t msix_intr;
9594
9595         msix_intr = intr_handle->intr_vec[queue_id];
9596         if (msix_intr == I40E_MISC_VEC_ID)
9597                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9598         else
9599                 I40E_WRITE_REG(hw,
9600                                I40E_PFINT_DYN_CTLN(msix_intr -
9601                                                    I40E_RX_VEC_START),
9602                                0);
9603         I40E_WRITE_FLUSH(hw);
9604
9605         return 0;
9606 }
9607
9608 static int i40e_get_regs(struct rte_eth_dev *dev,
9609                          struct rte_dev_reg_info *regs)
9610 {
9611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9612         uint32_t *ptr_data = regs->data;
9613         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9614         const struct i40e_reg_info *reg_info;
9615
9616         if (ptr_data == NULL) {
9617                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9618                 regs->width = sizeof(uint32_t);
9619                 return 0;
9620         }
9621
9622         /* The first few registers have to be read using AQ operations */
9623         reg_idx = 0;
9624         while (i40e_regs_adminq[reg_idx].name) {
9625                 reg_info = &i40e_regs_adminq[reg_idx++];
9626                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9627                         for (arr_idx2 = 0;
9628                                         arr_idx2 <= reg_info->count2;
9629                                         arr_idx2++) {
9630                                 reg_offset = arr_idx * reg_info->stride1 +
9631                                         arr_idx2 * reg_info->stride2;
9632                                 reg_offset += reg_info->base_addr;
9633                                 ptr_data[reg_offset >> 2] =
9634                                         i40e_read_rx_ctl(hw, reg_offset);
9635                         }
9636         }
9637
9638         /* The remaining registers can be read using primitives */
9639         reg_idx = 0;
9640         while (i40e_regs_others[reg_idx].name) {
9641                 reg_info = &i40e_regs_others[reg_idx++];
9642                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9643                         for (arr_idx2 = 0;
9644                                         arr_idx2 <= reg_info->count2;
9645                                         arr_idx2++) {
9646                                 reg_offset = arr_idx * reg_info->stride1 +
9647                                         arr_idx2 * reg_info->stride2;
9648                                 reg_offset += reg_info->base_addr;
9649                                 ptr_data[reg_offset >> 2] =
9650                                         I40E_READ_REG(hw, reg_offset);
9651                         }
9652         }
9653
9654         return 0;
9655 }
9656
9657 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9658 {
9659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9660
9661         /* Convert word count to byte count */
9662         return hw->nvm.sr_size << 1;
9663 }
9664
9665 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9666                            struct rte_dev_eeprom_info *eeprom)
9667 {
9668         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9669         uint16_t *data = eeprom->data;
9670         uint16_t offset, length, cnt_words;
9671         int ret_code;
9672
9673         offset = eeprom->offset >> 1;
9674         length = eeprom->length >> 1;
9675         cnt_words = length;
9676
9677         if (offset > hw->nvm.sr_size ||
9678                 offset + length > hw->nvm.sr_size) {
9679                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9680                 return -EINVAL;
9681         }
9682
9683         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9684
9685         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9686         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9687                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9688                 return -EIO;
9689         }
9690
9691         return 0;
9692 }
9693
9694 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9695                                       struct ether_addr *mac_addr)
9696 {
9697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9698
9699         if (!is_valid_assigned_ether_addr(mac_addr)) {
9700                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9701                 return;
9702         }
9703
9704         /* Flags: 0x3 updates port address */
9705         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9706 }
9707
9708 static int
9709 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9710 {
9711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9712         struct rte_eth_dev_data *dev_data = pf->dev_data;
9713         uint32_t frame_size = mtu + ETHER_HDR_LEN
9714                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9715         int ret = 0;
9716
9717         /* check if mtu is within the allowed range */
9718         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9719                 return -EINVAL;
9720
9721         /* mtu setting is forbidden if port is start */
9722         if (dev_data->dev_started) {
9723                 PMD_DRV_LOG(ERR,
9724                             "port %d must be stopped before configuration\n",
9725                             dev_data->port_id);
9726                 return -EBUSY;
9727         }
9728
9729         if (frame_size > ETHER_MAX_LEN)
9730                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9731         else
9732                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9733
9734         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9735
9736         return ret;
9737 }