4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_bus_pci.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_ethdev_pci.h>
50 #include <rte_memzone.h>
51 #include <rte_malloc.h>
52 #include <rte_memcpy.h>
53 #include <rte_alarm.h>
55 #include <rte_eth_ctrl.h>
56 #include <rte_tailq.h>
57 #include <rte_hash_crc.h>
59 #include "i40e_logs.h"
60 #include "base/i40e_prototype.h"
61 #include "base/i40e_adminq_cmd.h"
62 #include "base/i40e_type.h"
63 #include "base/i40e_register.h"
64 #include "base/i40e_dcb.h"
65 #include "i40e_ethdev.h"
66 #include "i40e_rxtx.h"
68 #include "i40e_regs.h"
69 #include "rte_pmd_i40e.h"
71 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
72 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
74 #define I40E_CLEAR_PXE_WAIT_MS 200
76 /* Maximun number of capability elements */
77 #define I40E_MAX_CAP_ELE_NUM 128
79 /* Wait count and interval */
80 #define I40E_CHK_Q_ENA_COUNT 1000
81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
83 /* Maximun number of VSI */
84 #define I40E_MAX_NUM_VSIS (384UL)
86 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
88 /* Flow control default timer */
89 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
91 /* Flow control enable fwd bit */
92 #define I40E_PRTMAC_FWD_CTRL 0x00000001
94 /* Receive Packet Buffer size */
95 #define I40E_RXPBSIZE (968 * 1024)
98 #define I40E_KILOSHIFT 10
100 /* Flow control default high water */
101 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
103 /* Flow control default low water */
104 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
106 /* Receive Average Packet Size in Byte*/
107 #define I40E_PACKET_AVERAGE_SIZE 128
109 /* Mask of PF interrupt causes */
110 #define I40E_PFINT_ICR0_ENA_MASK ( \
111 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
112 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_GRST_MASK | \
114 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
115 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
116 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
117 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
118 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
119 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
121 #define I40E_FLOW_TYPES ( \
122 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
127 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
130 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
131 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
132 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
134 /* Additional timesync values. */
135 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
136 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
137 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
138 #define I40E_PRTTSYN_TSYNENA 0x80000000
139 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
140 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 * Below are values for writing un-exposed registers suggested
146 /* Destination MAC address */
147 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
148 /* Source MAC address */
149 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
150 /* Outer (S-Tag) VLAN tag in the outer L2 header */
151 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
152 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
154 /* Single VLAN tag in the inner L2 header */
155 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
156 /* Source IPv4 address */
157 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
158 /* Destination IPv4 address */
159 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
160 /* Source IPv4 address for X722 */
161 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
162 /* Destination IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
164 /* IPv4 Protocol for X722 */
165 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
166 /* IPv4 Time to Live for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
168 /* IPv4 Type of Service (TOS) */
169 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
171 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
172 /* IPv4 Time to Live */
173 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
174 /* Source IPv6 address */
175 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
176 /* Destination IPv6 address */
177 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
178 /* IPv6 Traffic Class (TC) */
179 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
180 /* IPv6 Next Header */
181 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
183 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
185 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
186 /* Destination L4 port */
187 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
188 /* SCTP verification tag */
189 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
190 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
191 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
192 /* Source port of tunneling UDP */
193 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
194 /* Destination port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
196 /* UDP Tunneling ID, NVGRE/GRE key */
197 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
198 /* Last ether type */
199 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
200 /* Tunneling outer destination IPv4 address */
201 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
202 /* Tunneling outer destination IPv6 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
204 /* 1st word of flex payload */
205 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
206 /* 2nd word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
208 /* 3rd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
210 /* 4th word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
212 /* 5th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
214 /* 6th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
216 /* 7th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
218 /* 8th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
220 /* all 8 words flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
222 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
224 #define I40E_TRANSLATE_INSET 0
225 #define I40E_TRANSLATE_REG 1
227 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
228 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
229 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
230 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
231 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
232 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
234 /* PCI offset for querying capability */
235 #define PCI_DEV_CAP_REG 0xA4
236 /* PCI offset for enabling/disabling Extended Tag */
237 #define PCI_DEV_CTRL_REG 0xA8
238 /* Bit mask of Extended Tag capability */
239 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
240 /* Bit shift of Extended Tag enable/disable */
241 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
242 /* Bit mask of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
245 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
246 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
247 static int i40e_dev_configure(struct rte_eth_dev *dev);
248 static int i40e_dev_start(struct rte_eth_dev *dev);
249 static void i40e_dev_stop(struct rte_eth_dev *dev);
250 static void i40e_dev_close(struct rte_eth_dev *dev);
251 static int i40e_dev_reset(struct rte_eth_dev *dev);
252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
258 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
261 struct rte_eth_xstat *xstats, unsigned n);
262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
263 struct rte_eth_xstat_name *xstats_names,
265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
271 char *fw_version, size_t fw_size);
272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
273 struct rte_eth_dev_info *dev_info);
274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
278 enum rte_vlan_type vlan_type,
280 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
288 struct rte_eth_fc_conf *fc_conf);
289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_pfc_conf *pfc_conf);
293 static int i40e_macaddr_add(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
299 struct rte_eth_rss_reta_entry64 *reta_conf,
301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
305 static int i40e_get_cap(struct i40e_hw *hw);
306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
307 static int i40e_pf_setup(struct i40e_pf *pf);
308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
310 static int i40e_dcb_setup(struct rte_eth_dev *dev);
311 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
312 bool offset_loaded, uint64_t *offset, uint64_t *stat);
313 static void i40e_stat_update_48(struct i40e_hw *hw,
319 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
320 static void i40e_dev_interrupt_handler(void *param);
321 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
322 uint32_t base, uint32_t num);
323 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
324 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
326 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
328 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
329 static int i40e_veb_release(struct i40e_veb *veb);
330 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
331 struct i40e_vsi *vsi);
332 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
333 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
334 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
335 struct i40e_macvlan_filter *mv_f,
338 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
339 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
340 struct rte_eth_rss_conf *rss_conf);
341 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
342 struct rte_eth_rss_conf *rss_conf);
343 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
344 struct rte_eth_udp_tunnel *udp_tunnel);
345 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
346 struct rte_eth_udp_tunnel *udp_tunnel);
347 static void i40e_filter_input_set_init(struct i40e_pf *pf);
348 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
349 enum rte_filter_op filter_op,
351 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
352 enum rte_filter_type filter_type,
353 enum rte_filter_op filter_op,
355 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
356 struct rte_eth_dcb_info *dcb_info);
357 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
358 static void i40e_configure_registers(struct i40e_hw *hw);
359 static void i40e_hw_init(struct rte_eth_dev *dev);
360 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
361 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
368 struct rte_eth_mirror_conf *mirror_conf,
369 uint8_t sw_id, uint8_t on);
370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp,
377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp);
379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
384 struct timespec *timestamp);
385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
386 const struct timespec *timestamp);
388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
393 static int i40e_get_regs(struct rte_eth_dev *dev,
394 struct rte_dev_reg_info *regs);
396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
399 struct rte_dev_eeprom_info *eeprom);
401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
402 struct ether_addr *mac_addr);
404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
406 static int i40e_ethertype_filter_convert(
407 const struct rte_eth_ethertype_filter *input,
408 struct i40e_ethertype_filter *filter);
409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
410 struct i40e_ethertype_filter *filter);
412 static int i40e_tunnel_filter_convert(
413 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
414 struct i40e_tunnel_filter *tunnel_filter);
415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
416 struct i40e_tunnel_filter *tunnel_filter);
417 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
419 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
420 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
421 static void i40e_filter_restore(struct i40e_pf *pf);
422 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
424 int i40e_logtype_init;
425 int i40e_logtype_driver;
427 static const struct rte_pci_id pci_id_i40e_map[] = {
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
448 { .vendor_id = 0, /* sentinel */ },
451 static const struct eth_dev_ops i40e_eth_dev_ops = {
452 .dev_configure = i40e_dev_configure,
453 .dev_start = i40e_dev_start,
454 .dev_stop = i40e_dev_stop,
455 .dev_close = i40e_dev_close,
456 .dev_reset = i40e_dev_reset,
457 .promiscuous_enable = i40e_dev_promiscuous_enable,
458 .promiscuous_disable = i40e_dev_promiscuous_disable,
459 .allmulticast_enable = i40e_dev_allmulticast_enable,
460 .allmulticast_disable = i40e_dev_allmulticast_disable,
461 .dev_set_link_up = i40e_dev_set_link_up,
462 .dev_set_link_down = i40e_dev_set_link_down,
463 .link_update = i40e_dev_link_update,
464 .stats_get = i40e_dev_stats_get,
465 .xstats_get = i40e_dev_xstats_get,
466 .xstats_get_names = i40e_dev_xstats_get_names,
467 .stats_reset = i40e_dev_stats_reset,
468 .xstats_reset = i40e_dev_stats_reset,
469 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
470 .fw_version_get = i40e_fw_version_get,
471 .dev_infos_get = i40e_dev_info_get,
472 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
473 .vlan_filter_set = i40e_vlan_filter_set,
474 .vlan_tpid_set = i40e_vlan_tpid_set,
475 .vlan_offload_set = i40e_vlan_offload_set,
476 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
477 .vlan_pvid_set = i40e_vlan_pvid_set,
478 .rx_queue_start = i40e_dev_rx_queue_start,
479 .rx_queue_stop = i40e_dev_rx_queue_stop,
480 .tx_queue_start = i40e_dev_tx_queue_start,
481 .tx_queue_stop = i40e_dev_tx_queue_stop,
482 .rx_queue_setup = i40e_dev_rx_queue_setup,
483 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
484 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
485 .rx_queue_release = i40e_dev_rx_queue_release,
486 .rx_queue_count = i40e_dev_rx_queue_count,
487 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
488 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
489 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .filter_ctrl = i40e_dev_filter_ctrl,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .mirror_rule_set = i40e_mirror_rule_set,
509 .mirror_rule_reset = i40e_mirror_rule_reset,
510 .timesync_enable = i40e_timesync_enable,
511 .timesync_disable = i40e_timesync_disable,
512 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
513 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
514 .get_dcb_info = i40e_dev_get_dcb_info,
515 .timesync_adjust_time = i40e_timesync_adjust_time,
516 .timesync_read_time = i40e_timesync_read_time,
517 .timesync_write_time = i40e_timesync_write_time,
518 .get_reg = i40e_get_regs,
519 .get_eeprom_length = i40e_get_eeprom_length,
520 .get_eeprom = i40e_get_eeprom,
521 .mac_addr_set = i40e_set_default_mac_addr,
522 .mtu_set = i40e_dev_mtu_set,
523 .tm_ops_get = i40e_tm_ops_get,
526 /* store statistics names and its offset in stats structure */
527 struct rte_i40e_xstats_name_off {
528 char name[RTE_ETH_XSTATS_NAME_SIZE];
532 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
533 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
534 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
535 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
536 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
537 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
538 rx_unknown_protocol)},
539 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
540 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
541 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
542 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
545 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
546 sizeof(rte_i40e_stats_strings[0]))
548 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
549 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
550 tx_dropped_link_down)},
551 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
552 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
554 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
555 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
557 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
559 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
561 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
562 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
563 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
564 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
565 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
566 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
582 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
583 mac_short_packet_dropped)},
584 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
587 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
588 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
600 {"rx_flow_director_atr_match_packets",
601 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
602 {"rx_flow_director_sb_match_packets",
603 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
604 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
606 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
608 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
610 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
614 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
615 sizeof(rte_i40e_hw_port_strings[0]))
617 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
618 {"xon_packets", offsetof(struct i40e_hw_port_stats,
620 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
624 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
625 sizeof(rte_i40e_rxq_prio_strings[0]))
627 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
628 {"xon_packets", offsetof(struct i40e_hw_port_stats,
630 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
632 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
633 priority_xon_2_xoff)},
636 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
637 sizeof(rte_i40e_txq_prio_strings[0]))
639 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
640 struct rte_pci_device *pci_dev)
642 return rte_eth_dev_pci_generic_probe(pci_dev,
643 sizeof(struct i40e_adapter), eth_i40e_dev_init);
646 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
648 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
651 static struct rte_pci_driver rte_i40e_pmd = {
652 .id_table = pci_id_i40e_map,
653 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
654 RTE_PCI_DRV_IOVA_AS_VA,
655 .probe = eth_i40e_pci_probe,
656 .remove = eth_i40e_pci_remove,
660 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
661 struct rte_eth_link *link)
663 struct rte_eth_link *dst = link;
664 struct rte_eth_link *src = &(dev->data->dev_link);
666 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
667 *(uint64_t *)src) == 0)
674 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
675 struct rte_eth_link *link)
677 struct rte_eth_link *dst = &(dev->data->dev_link);
678 struct rte_eth_link *src = link;
680 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
681 *(uint64_t *)src) == 0)
688 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
690 i40e_write_rx_ctl(hw, reg_addr, reg_val);
691 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
696 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
697 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
698 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
700 #ifndef I40E_GLQF_ORT
701 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
703 #ifndef I40E_GLQF_PIT
704 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
706 #ifndef I40E_GLQF_L3_MAP
707 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
710 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
713 * Force global configuration for flexible payload
714 * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
715 * This should be removed from code once proper
716 * configuration API is added to avoid configuration conflicts
717 * between ports of the same device.
719 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
720 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
721 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
722 i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
725 * Initialize registers for parsing packet type of QinQ
726 * This should be removed from code once proper
727 * configuration API is added to avoid configuration conflicts
728 * between ports of the same device.
730 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
731 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
732 i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
735 static inline void i40e_config_automask(struct i40e_pf *pf)
737 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
740 /* INTENA flag is not auto-cleared for interrupt */
741 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
742 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
743 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
745 /* If support multi-driver, PF will use INT0. */
746 if (!pf->support_multi_driver)
747 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
749 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
752 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
755 * Add a ethertype filter to drop all flow control frames transmitted
759 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
761 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
762 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
763 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
764 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
767 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
768 I40E_FLOW_CONTROL_ETHERTYPE, flags,
769 pf->main_vsi_seid, 0,
773 "Failed to add filter to drop flow control frames from VSIs.");
777 floating_veb_list_handler(__rte_unused const char *key,
778 const char *floating_veb_value,
782 unsigned int count = 0;
785 bool *vf_floating_veb = opaque;
787 while (isblank(*floating_veb_value))
788 floating_veb_value++;
790 /* Reset floating VEB configuration for VFs */
791 for (idx = 0; idx < I40E_MAX_VF; idx++)
792 vf_floating_veb[idx] = false;
796 while (isblank(*floating_veb_value))
797 floating_veb_value++;
798 if (*floating_veb_value == '\0')
801 idx = strtoul(floating_veb_value, &end, 10);
802 if (errno || end == NULL)
804 while (isblank(*end))
808 } else if ((*end == ';') || (*end == '\0')) {
810 if (min == I40E_MAX_VF)
812 if (max >= I40E_MAX_VF)
813 max = I40E_MAX_VF - 1;
814 for (idx = min; idx <= max; idx++) {
815 vf_floating_veb[idx] = true;
822 floating_veb_value = end + 1;
823 } while (*end != '\0');
832 config_vf_floating_veb(struct rte_devargs *devargs,
833 uint16_t floating_veb,
834 bool *vf_floating_veb)
836 struct rte_kvargs *kvlist;
838 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
842 /* All the VFs attach to the floating VEB by default
843 * when the floating VEB is enabled.
845 for (i = 0; i < I40E_MAX_VF; i++)
846 vf_floating_veb[i] = true;
851 kvlist = rte_kvargs_parse(devargs->args, NULL);
855 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
856 rte_kvargs_free(kvlist);
859 /* When the floating_veb_list parameter exists, all the VFs
860 * will attach to the legacy VEB firstly, then configure VFs
861 * to the floating VEB according to the floating_veb_list.
863 if (rte_kvargs_process(kvlist, floating_veb_list,
864 floating_veb_list_handler,
865 vf_floating_veb) < 0) {
866 rte_kvargs_free(kvlist);
869 rte_kvargs_free(kvlist);
873 i40e_check_floating_handler(__rte_unused const char *key,
875 __rte_unused void *opaque)
877 if (strcmp(value, "1"))
884 is_floating_veb_supported(struct rte_devargs *devargs)
886 struct rte_kvargs *kvlist;
887 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
892 kvlist = rte_kvargs_parse(devargs->args, NULL);
896 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
897 rte_kvargs_free(kvlist);
900 /* Floating VEB is enabled when there's key-value:
901 * enable_floating_veb=1
903 if (rte_kvargs_process(kvlist, floating_veb_key,
904 i40e_check_floating_handler, NULL) < 0) {
905 rte_kvargs_free(kvlist);
908 rte_kvargs_free(kvlist);
914 config_floating_veb(struct rte_eth_dev *dev)
916 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
917 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
918 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
920 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
922 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
924 is_floating_veb_supported(pci_dev->device.devargs);
925 config_vf_floating_veb(pci_dev->device.devargs,
927 pf->floating_veb_list);
929 pf->floating_veb = false;
933 #define I40E_L2_TAGS_S_TAG_SHIFT 1
934 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
937 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
940 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
941 char ethertype_hash_name[RTE_HASH_NAMESIZE];
944 struct rte_hash_parameters ethertype_hash_params = {
945 .name = ethertype_hash_name,
946 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
947 .key_len = sizeof(struct i40e_ethertype_filter_input),
948 .hash_func = rte_hash_crc,
949 .hash_func_init_val = 0,
950 .socket_id = rte_socket_id(),
953 /* Initialize ethertype filter rule list and hash */
954 TAILQ_INIT(ðertype_rule->ethertype_list);
955 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
956 "ethertype_%s", dev->device->name);
957 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
958 if (!ethertype_rule->hash_table) {
959 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
962 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
963 sizeof(struct i40e_ethertype_filter *) *
964 I40E_MAX_ETHERTYPE_FILTER_NUM,
966 if (!ethertype_rule->hash_map) {
968 "Failed to allocate memory for ethertype hash map!");
970 goto err_ethertype_hash_map_alloc;
975 err_ethertype_hash_map_alloc:
976 rte_hash_free(ethertype_rule->hash_table);
982 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
984 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
985 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
986 char tunnel_hash_name[RTE_HASH_NAMESIZE];
989 struct rte_hash_parameters tunnel_hash_params = {
990 .name = tunnel_hash_name,
991 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
992 .key_len = sizeof(struct i40e_tunnel_filter_input),
993 .hash_func = rte_hash_crc,
994 .hash_func_init_val = 0,
995 .socket_id = rte_socket_id(),
998 /* Initialize tunnel filter rule list and hash */
999 TAILQ_INIT(&tunnel_rule->tunnel_list);
1000 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1001 "tunnel_%s", dev->device->name);
1002 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1003 if (!tunnel_rule->hash_table) {
1004 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1007 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1008 sizeof(struct i40e_tunnel_filter *) *
1009 I40E_MAX_TUNNEL_FILTER_NUM,
1011 if (!tunnel_rule->hash_map) {
1013 "Failed to allocate memory for tunnel hash map!");
1015 goto err_tunnel_hash_map_alloc;
1020 err_tunnel_hash_map_alloc:
1021 rte_hash_free(tunnel_rule->hash_table);
1027 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1029 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1030 struct i40e_fdir_info *fdir_info = &pf->fdir;
1031 char fdir_hash_name[RTE_HASH_NAMESIZE];
1034 struct rte_hash_parameters fdir_hash_params = {
1035 .name = fdir_hash_name,
1036 .entries = I40E_MAX_FDIR_FILTER_NUM,
1037 .key_len = sizeof(struct i40e_fdir_input),
1038 .hash_func = rte_hash_crc,
1039 .hash_func_init_val = 0,
1040 .socket_id = rte_socket_id(),
1043 /* Initialize flow director filter rule list and hash */
1044 TAILQ_INIT(&fdir_info->fdir_list);
1045 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1046 "fdir_%s", dev->device->name);
1047 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1048 if (!fdir_info->hash_table) {
1049 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1052 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1053 sizeof(struct i40e_fdir_filter *) *
1054 I40E_MAX_FDIR_FILTER_NUM,
1056 if (!fdir_info->hash_map) {
1058 "Failed to allocate memory for fdir hash map!");
1060 goto err_fdir_hash_map_alloc;
1064 err_fdir_hash_map_alloc:
1065 rte_hash_free(fdir_info->hash_table);
1071 i40e_init_customized_info(struct i40e_pf *pf)
1075 /* Initialize customized pctype */
1076 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1077 pf->customized_pctype[i].index = i;
1078 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1079 pf->customized_pctype[i].valid = false;
1082 pf->gtp_support = false;
1086 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1088 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1090 struct i40e_queue_regions *info = &pf->queue_region;
1093 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1094 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1096 memset(info, 0, sizeof(struct i40e_queue_regions));
1099 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
1102 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1107 unsigned long support_multi_driver;
1110 pf = (struct i40e_pf *)opaque;
1113 support_multi_driver = strtoul(value, &end, 10);
1114 if (errno != 0 || end == value || *end != 0) {
1115 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1119 if (support_multi_driver == 1 || support_multi_driver == 0)
1120 pf->support_multi_driver = (bool)support_multi_driver;
1122 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1123 "enable global configuration by default."
1124 ETH_I40E_SUPPORT_MULTI_DRIVER);
1129 i40e_support_multi_driver(struct rte_eth_dev *dev)
1131 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1132 static const char *const valid_keys[] = {
1133 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1134 struct rte_kvargs *kvlist;
1136 /* Enable global configuration by default */
1137 pf->support_multi_driver = false;
1139 if (!dev->device->devargs)
1142 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1146 if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1147 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1148 "the first invalid or last valid one is used !",
1149 ETH_I40E_SUPPORT_MULTI_DRIVER);
1151 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1152 i40e_parse_multi_drv_handler, pf) < 0) {
1153 rte_kvargs_free(kvlist);
1157 rte_kvargs_free(kvlist);
1162 eth_i40e_dev_init(struct rte_eth_dev *dev)
1164 struct rte_pci_device *pci_dev;
1165 struct rte_intr_handle *intr_handle;
1166 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1167 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168 struct i40e_vsi *vsi;
1171 uint8_t aq_fail = 0;
1173 PMD_INIT_FUNC_TRACE();
1175 dev->dev_ops = &i40e_eth_dev_ops;
1176 dev->rx_pkt_burst = i40e_recv_pkts;
1177 dev->tx_pkt_burst = i40e_xmit_pkts;
1178 dev->tx_pkt_prepare = i40e_prep_pkts;
1180 /* for secondary processes, we don't initialise any further as primary
1181 * has already done this work. Only check we don't need a different
1183 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1184 i40e_set_rx_function(dev);
1185 i40e_set_tx_function(dev);
1188 i40e_set_default_ptype_table(dev);
1189 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1190 intr_handle = &pci_dev->intr_handle;
1192 rte_eth_copy_pci_info(dev, pci_dev);
1194 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1195 pf->adapter->eth_dev = dev;
1196 pf->dev_data = dev->data;
1198 hw->back = I40E_PF_TO_ADAPTER(pf);
1199 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1202 "Hardware is not available, as address is NULL");
1206 hw->vendor_id = pci_dev->id.vendor_id;
1207 hw->device_id = pci_dev->id.device_id;
1208 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1209 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1210 hw->bus.device = pci_dev->addr.devid;
1211 hw->bus.func = pci_dev->addr.function;
1212 hw->adapter_stopped = 0;
1215 * Switch Tag value should not be identical to either the First Tag
1216 * or Second Tag values. So set something other than common Ethertype
1217 * for internal switching.
1219 hw->switch_tag = 0xffff;
1221 /* Check if need to support multi-driver */
1222 i40e_support_multi_driver(dev);
1224 /* Make sure all is clean before doing PF reset */
1227 /* Initialize the hardware */
1230 /* Reset here to make sure all is clean for each PF */
1231 ret = i40e_pf_reset(hw);
1233 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1237 /* Initialize the shared code (base driver) */
1238 ret = i40e_init_shared_code(hw);
1240 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1244 i40e_config_automask(pf);
1246 i40e_set_default_pctype_table(dev);
1249 * To work around the NVM issue, initialize registers
1250 * for flexible payload and packet type of QinQ by
1251 * software. It should be removed once issues are fixed
1254 if (!pf->support_multi_driver)
1255 i40e_GLQF_reg_init(hw);
1257 /* Initialize the input set for filters (hash and fd) to default value */
1258 i40e_filter_input_set_init(pf);
1260 /* Initialize the parameters for adminq */
1261 i40e_init_adminq_parameter(hw);
1262 ret = i40e_init_adminq(hw);
1263 if (ret != I40E_SUCCESS) {
1264 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1267 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1268 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1269 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1270 ((hw->nvm.version >> 12) & 0xf),
1271 ((hw->nvm.version >> 4) & 0xff),
1272 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1274 /* initialise the L3_MAP register */
1275 if (!pf->support_multi_driver) {
1276 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1279 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1282 "Global register 0x%08x is changed with 0x28",
1283 I40E_GLQF_L3_MAP(40));
1284 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1287 /* Need the special FW version to support floating VEB */
1288 config_floating_veb(dev);
1289 /* Clear PXE mode */
1290 i40e_clear_pxe_mode(hw);
1291 i40e_dev_sync_phy_type(hw);
1294 * On X710, performance number is far from the expectation on recent
1295 * firmware versions. The fix for this issue may not be integrated in
1296 * the following firmware version. So the workaround in software driver
1297 * is needed. It needs to modify the initial values of 3 internal only
1298 * registers. Note that the workaround can be removed when it is fixed
1299 * in firmware in the future.
1301 i40e_configure_registers(hw);
1303 /* Get hw capabilities */
1304 ret = i40e_get_cap(hw);
1305 if (ret != I40E_SUCCESS) {
1306 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1307 goto err_get_capabilities;
1310 /* Initialize parameters for PF */
1311 ret = i40e_pf_parameter_init(dev);
1313 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1314 goto err_parameter_init;
1317 /* Initialize the queue management */
1318 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1320 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1321 goto err_qp_pool_init;
1323 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1324 hw->func_caps.num_msix_vectors - 1);
1326 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1327 goto err_msix_pool_init;
1330 /* Initialize lan hmc */
1331 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1332 hw->func_caps.num_rx_qp, 0, 0);
1333 if (ret != I40E_SUCCESS) {
1334 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1335 goto err_init_lan_hmc;
1338 /* Configure lan hmc */
1339 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1340 if (ret != I40E_SUCCESS) {
1341 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1342 goto err_configure_lan_hmc;
1345 /* Get and check the mac address */
1346 i40e_get_mac_addr(hw, hw->mac.addr);
1347 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1348 PMD_INIT_LOG(ERR, "mac address is not valid");
1350 goto err_get_mac_addr;
1352 /* Copy the permanent MAC address */
1353 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1354 (struct ether_addr *) hw->mac.perm_addr);
1356 /* Disable flow control */
1357 hw->fc.requested_mode = I40E_FC_NONE;
1358 i40e_set_fc(hw, &aq_fail, TRUE);
1360 /* Set the global registers with default ether type value */
1361 if (!pf->support_multi_driver) {
1362 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1364 if (ret != I40E_SUCCESS) {
1366 "Failed to set the default outer "
1368 goto err_setup_pf_switch;
1372 /* PF setup, which includes VSI setup */
1373 ret = i40e_pf_setup(pf);
1375 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1376 goto err_setup_pf_switch;
1379 /* reset all stats of the device, including pf and main vsi */
1380 i40e_dev_stats_reset(dev);
1384 /* Disable double vlan by default */
1385 i40e_vsi_config_double_vlan(vsi, FALSE);
1387 /* Disable S-TAG identification when floating_veb is disabled */
1388 if (!pf->floating_veb) {
1389 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1390 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1391 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1392 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1396 if (!vsi->max_macaddrs)
1397 len = ETHER_ADDR_LEN;
1399 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1401 /* Should be after VSI initialized */
1402 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1403 if (!dev->data->mac_addrs) {
1405 "Failed to allocated memory for storing mac address");
1408 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1409 &dev->data->mac_addrs[0]);
1411 /* Init dcb to sw mode by default */
1412 ret = i40e_dcb_init_configure(dev, TRUE);
1413 if (ret != I40E_SUCCESS) {
1414 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1415 pf->flags &= ~I40E_FLAG_DCB;
1417 /* Update HW struct after DCB configuration */
1420 /* initialize pf host driver to setup SRIOV resource if applicable */
1421 i40e_pf_host_init(dev);
1423 /* register callback func to eal lib */
1424 rte_intr_callback_register(intr_handle,
1425 i40e_dev_interrupt_handler, dev);
1427 /* configure and enable device interrupt */
1428 i40e_pf_config_irq0(hw, TRUE);
1429 i40e_pf_enable_irq0(hw);
1431 /* enable uio intr after callback register */
1432 rte_intr_enable(intr_handle);
1434 * Add an ethertype filter to drop all flow control frames transmitted
1435 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1438 i40e_add_tx_flow_control_drop_filter(pf);
1440 /* Set the max frame size to 0x2600 by default,
1441 * in case other drivers changed the default value.
1443 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1445 /* initialize mirror rule list */
1446 TAILQ_INIT(&pf->mirror_list);
1448 /* initialize Traffic Manager configuration */
1449 i40e_tm_conf_init(dev);
1451 /* Initialize customized information */
1452 i40e_init_customized_info(pf);
1454 ret = i40e_init_ethtype_filter_list(dev);
1456 goto err_init_ethtype_filter_list;
1457 ret = i40e_init_tunnel_filter_list(dev);
1459 goto err_init_tunnel_filter_list;
1460 ret = i40e_init_fdir_filter_list(dev);
1462 goto err_init_fdir_filter_list;
1464 /* initialize queue region configuration */
1465 i40e_init_queue_region_conf(dev);
1469 err_init_fdir_filter_list:
1470 rte_free(pf->tunnel.hash_table);
1471 rte_free(pf->tunnel.hash_map);
1472 err_init_tunnel_filter_list:
1473 rte_free(pf->ethertype.hash_table);
1474 rte_free(pf->ethertype.hash_map);
1475 err_init_ethtype_filter_list:
1476 rte_free(dev->data->mac_addrs);
1478 i40e_vsi_release(pf->main_vsi);
1479 err_setup_pf_switch:
1481 err_configure_lan_hmc:
1482 (void)i40e_shutdown_lan_hmc(hw);
1484 i40e_res_pool_destroy(&pf->msix_pool);
1486 i40e_res_pool_destroy(&pf->qp_pool);
1489 err_get_capabilities:
1490 (void)i40e_shutdown_adminq(hw);
1496 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1498 struct i40e_ethertype_filter *p_ethertype;
1499 struct i40e_ethertype_rule *ethertype_rule;
1501 ethertype_rule = &pf->ethertype;
1502 /* Remove all ethertype filter rules and hash */
1503 if (ethertype_rule->hash_map)
1504 rte_free(ethertype_rule->hash_map);
1505 if (ethertype_rule->hash_table)
1506 rte_hash_free(ethertype_rule->hash_table);
1508 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1509 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1510 p_ethertype, rules);
1511 rte_free(p_ethertype);
1516 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1518 struct i40e_tunnel_filter *p_tunnel;
1519 struct i40e_tunnel_rule *tunnel_rule;
1521 tunnel_rule = &pf->tunnel;
1522 /* Remove all tunnel director rules and hash */
1523 if (tunnel_rule->hash_map)
1524 rte_free(tunnel_rule->hash_map);
1525 if (tunnel_rule->hash_table)
1526 rte_hash_free(tunnel_rule->hash_table);
1528 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1529 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1535 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1537 struct i40e_fdir_filter *p_fdir;
1538 struct i40e_fdir_info *fdir_info;
1540 fdir_info = &pf->fdir;
1541 /* Remove all flow director rules and hash */
1542 if (fdir_info->hash_map)
1543 rte_free(fdir_info->hash_map);
1544 if (fdir_info->hash_table)
1545 rte_hash_free(fdir_info->hash_table);
1547 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1548 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1554 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1557 struct rte_pci_device *pci_dev;
1558 struct rte_intr_handle *intr_handle;
1560 struct i40e_filter_control_settings settings;
1561 struct rte_flow *p_flow;
1563 uint8_t aq_fail = 0;
1566 PMD_INIT_FUNC_TRACE();
1568 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1571 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1572 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1574 intr_handle = &pci_dev->intr_handle;
1576 if (hw->adapter_stopped == 0)
1577 i40e_dev_close(dev);
1579 dev->dev_ops = NULL;
1580 dev->rx_pkt_burst = NULL;
1581 dev->tx_pkt_burst = NULL;
1583 /* Clear PXE mode */
1584 i40e_clear_pxe_mode(hw);
1586 /* Unconfigure filter control */
1587 memset(&settings, 0, sizeof(settings));
1588 ret = i40e_set_filter_control(hw, &settings);
1590 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1593 /* Disable flow control */
1594 hw->fc.requested_mode = I40E_FC_NONE;
1595 i40e_set_fc(hw, &aq_fail, TRUE);
1597 /* uninitialize pf host driver */
1598 i40e_pf_host_uninit(dev);
1600 rte_free(dev->data->mac_addrs);
1601 dev->data->mac_addrs = NULL;
1603 /* disable uio intr before callback unregister */
1604 rte_intr_disable(intr_handle);
1606 /* unregister callback func to eal lib */
1608 ret = rte_intr_callback_unregister(intr_handle,
1609 i40e_dev_interrupt_handler, dev);
1612 } else if (ret != -EAGAIN) {
1614 "intr callback unregister failed: %d",
1618 i40e_msec_delay(500);
1619 } while (retries++ < 5);
1621 i40e_rm_ethtype_filter_list(pf);
1622 i40e_rm_tunnel_filter_list(pf);
1623 i40e_rm_fdir_filter_list(pf);
1625 /* Remove all flows */
1626 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1627 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1631 /* Remove all Traffic Manager configuration */
1632 i40e_tm_conf_uninit(dev);
1638 i40e_dev_configure(struct rte_eth_dev *dev)
1640 struct i40e_adapter *ad =
1641 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1642 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1643 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1644 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1647 ret = i40e_dev_sync_phy_type(hw);
1651 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1652 * bulk allocation or vector Rx preconditions we will reset it.
1654 ad->rx_bulk_alloc_allowed = true;
1655 ad->rx_vec_allowed = true;
1656 ad->tx_simple_allowed = true;
1657 ad->tx_vec_allowed = true;
1659 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1660 ret = i40e_fdir_setup(pf);
1661 if (ret != I40E_SUCCESS) {
1662 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1665 ret = i40e_fdir_configure(dev);
1667 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1671 i40e_fdir_teardown(pf);
1673 ret = i40e_dev_init_vlan(dev);
1678 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1679 * RSS setting have different requirements.
1680 * General PMD driver call sequence are NIC init, configure,
1681 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1682 * will try to lookup the VSI that specific queue belongs to if VMDQ
1683 * applicable. So, VMDQ setting has to be done before
1684 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1685 * For RSS setting, it will try to calculate actual configured RX queue
1686 * number, which will be available after rx_queue_setup(). dev_start()
1687 * function is good to place RSS setup.
1689 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1690 ret = i40e_vmdq_setup(dev);
1695 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1696 ret = i40e_dcb_setup(dev);
1698 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1703 TAILQ_INIT(&pf->flow_list);
1708 /* need to release vmdq resource if exists */
1709 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1710 i40e_vsi_release(pf->vmdq[i].vsi);
1711 pf->vmdq[i].vsi = NULL;
1716 /* need to release fdir resource if exists */
1717 i40e_fdir_teardown(pf);
1722 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1724 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1725 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1726 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1727 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1728 uint16_t msix_vect = vsi->msix_intr;
1731 for (i = 0; i < vsi->nb_qps; i++) {
1732 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1733 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1737 if (vsi->type != I40E_VSI_SRIOV) {
1738 if (!rte_intr_allow_others(intr_handle)) {
1739 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1740 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1742 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1745 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1746 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1748 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1753 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1754 vsi->user_param + (msix_vect - 1);
1756 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1757 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1759 I40E_WRITE_FLUSH(hw);
1763 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1764 int base_queue, int nb_queue,
1769 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1770 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1772 /* Bind all RX queues to allocated MSIX interrupt */
1773 for (i = 0; i < nb_queue; i++) {
1774 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1775 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1776 ((base_queue + i + 1) <<
1777 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1778 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1779 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1781 if (i == nb_queue - 1)
1782 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1783 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1786 /* Write first RX queue to Link list register as the head element */
1787 if (vsi->type != I40E_VSI_SRIOV) {
1789 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL,
1790 pf->support_multi_driver);
1792 if (msix_vect == I40E_MISC_VEC_ID) {
1793 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1795 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1797 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1799 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1802 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1804 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1806 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1808 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1815 if (msix_vect == I40E_MISC_VEC_ID) {
1817 I40E_VPINT_LNKLST0(vsi->user_param),
1819 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1821 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1823 /* num_msix_vectors_vf needs to minus irq0 */
1824 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1825 vsi->user_param + (msix_vect - 1);
1827 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1829 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1831 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1835 I40E_WRITE_FLUSH(hw);
1839 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1841 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1842 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1843 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1844 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1845 uint16_t msix_vect = vsi->msix_intr;
1846 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1847 uint16_t queue_idx = 0;
1851 for (i = 0; i < vsi->nb_qps; i++) {
1852 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1853 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1856 /* VF bind interrupt */
1857 if (vsi->type == I40E_VSI_SRIOV) {
1858 __vsi_queues_bind_intr(vsi, msix_vect,
1859 vsi->base_queue, vsi->nb_qps,
1864 /* PF & VMDq bind interrupt */
1865 if (rte_intr_dp_is_en(intr_handle)) {
1866 if (vsi->type == I40E_VSI_MAIN) {
1869 } else if (vsi->type == I40E_VSI_VMDQ2) {
1870 struct i40e_vsi *main_vsi =
1871 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1872 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1877 for (i = 0; i < vsi->nb_used_qps; i++) {
1879 if (!rte_intr_allow_others(intr_handle))
1880 /* allow to share MISC_VEC_ID */
1881 msix_vect = I40E_MISC_VEC_ID;
1883 /* no enough msix_vect, map all to one */
1884 __vsi_queues_bind_intr(vsi, msix_vect,
1885 vsi->base_queue + i,
1886 vsi->nb_used_qps - i,
1888 for (; !!record && i < vsi->nb_used_qps; i++)
1889 intr_handle->intr_vec[queue_idx + i] =
1893 /* 1:1 queue/msix_vect mapping */
1894 __vsi_queues_bind_intr(vsi, msix_vect,
1895 vsi->base_queue + i, 1,
1898 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1906 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1908 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1909 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1910 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1911 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1912 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1913 uint16_t msix_intr, i;
1915 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1916 for (i = 0; i < vsi->nb_msix; i++) {
1917 msix_intr = vsi->msix_intr + i;
1918 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1919 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1920 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1921 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1924 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1925 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1926 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1927 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1929 I40E_WRITE_FLUSH(hw);
1933 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1935 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1936 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1937 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1938 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1939 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1940 uint16_t msix_intr, i;
1942 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1943 for (i = 0; i < vsi->nb_msix; i++) {
1944 msix_intr = vsi->msix_intr + i;
1945 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1946 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1949 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1950 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1952 I40E_WRITE_FLUSH(hw);
1955 static inline uint8_t
1956 i40e_parse_link_speeds(uint16_t link_speeds)
1958 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1960 if (link_speeds & ETH_LINK_SPEED_40G)
1961 link_speed |= I40E_LINK_SPEED_40GB;
1962 if (link_speeds & ETH_LINK_SPEED_25G)
1963 link_speed |= I40E_LINK_SPEED_25GB;
1964 if (link_speeds & ETH_LINK_SPEED_20G)
1965 link_speed |= I40E_LINK_SPEED_20GB;
1966 if (link_speeds & ETH_LINK_SPEED_10G)
1967 link_speed |= I40E_LINK_SPEED_10GB;
1968 if (link_speeds & ETH_LINK_SPEED_1G)
1969 link_speed |= I40E_LINK_SPEED_1GB;
1970 if (link_speeds & ETH_LINK_SPEED_100M)
1971 link_speed |= I40E_LINK_SPEED_100MB;
1977 i40e_phy_conf_link(struct i40e_hw *hw,
1979 uint8_t force_speed,
1982 enum i40e_status_code status;
1983 struct i40e_aq_get_phy_abilities_resp phy_ab;
1984 struct i40e_aq_set_phy_config phy_conf;
1985 enum i40e_aq_phy_type cnt;
1986 uint8_t avail_speed;
1987 uint32_t phy_type_mask = 0;
1989 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1990 I40E_AQ_PHY_FLAG_PAUSE_RX |
1991 I40E_AQ_PHY_FLAG_PAUSE_RX |
1992 I40E_AQ_PHY_FLAG_LOW_POWER;
1995 /* To get phy capabilities of available speeds. */
1996 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
1999 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2003 avail_speed = phy_ab.link_speed;
2005 /* To get the current phy config. */
2006 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2009 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2014 /* If link needs to go up and it is in autoneg mode the speed is OK,
2015 * no need to set up again.
2017 if (is_up && phy_ab.phy_type != 0 &&
2018 abilities & I40E_AQ_PHY_AN_ENABLED &&
2019 phy_ab.link_speed != 0)
2020 return I40E_SUCCESS;
2022 memset(&phy_conf, 0, sizeof(phy_conf));
2024 /* bits 0-2 use the values from get_phy_abilities_resp */
2026 abilities |= phy_ab.abilities & mask;
2028 phy_conf.abilities = abilities;
2030 /* If link needs to go up, but the force speed is not supported,
2031 * Warn users and config the default available speeds.
2033 if (is_up && !(force_speed & avail_speed)) {
2034 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2035 phy_conf.link_speed = avail_speed;
2037 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2040 /* PHY type mask needs to include each type except PHY type extension */
2041 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2042 phy_type_mask |= 1 << cnt;
2044 /* use get_phy_abilities_resp value for the rest */
2045 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2046 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2047 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2048 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2049 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2050 phy_conf.eee_capability = phy_ab.eee_capability;
2051 phy_conf.eeer = phy_ab.eeer_val;
2052 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2054 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2055 phy_ab.abilities, phy_ab.link_speed);
2056 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2057 phy_conf.abilities, phy_conf.link_speed);
2059 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2063 return I40E_SUCCESS;
2067 i40e_apply_link_speed(struct rte_eth_dev *dev)
2070 uint8_t abilities = 0;
2071 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072 struct rte_eth_conf *conf = &dev->data->dev_conf;
2074 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2075 conf->link_speeds = ETH_LINK_SPEED_40G |
2076 ETH_LINK_SPEED_25G |
2077 ETH_LINK_SPEED_20G |
2078 ETH_LINK_SPEED_10G |
2080 ETH_LINK_SPEED_100M;
2082 speed = i40e_parse_link_speeds(conf->link_speeds);
2083 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2084 I40E_AQ_PHY_AN_ENABLED |
2085 I40E_AQ_PHY_LINK_ENABLED;
2087 return i40e_phy_conf_link(hw, abilities, speed, true);
2091 i40e_dev_start(struct rte_eth_dev *dev)
2093 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095 struct i40e_vsi *main_vsi = pf->main_vsi;
2097 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2098 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2099 uint32_t intr_vector = 0;
2100 struct i40e_vsi *vsi;
2102 hw->adapter_stopped = 0;
2104 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2106 "Invalid link_speeds for port %u, autonegotiation disabled",
2107 dev->data->port_id);
2111 rte_intr_disable(intr_handle);
2113 if ((rte_intr_cap_multiple(intr_handle) ||
2114 !RTE_ETH_DEV_SRIOV(dev).active) &&
2115 dev->data->dev_conf.intr_conf.rxq != 0) {
2116 intr_vector = dev->data->nb_rx_queues;
2117 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2122 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2123 intr_handle->intr_vec =
2124 rte_zmalloc("intr_vec",
2125 dev->data->nb_rx_queues * sizeof(int),
2127 if (!intr_handle->intr_vec) {
2129 "Failed to allocate %d rx_queues intr_vec",
2130 dev->data->nb_rx_queues);
2135 /* Initialize VSI */
2136 ret = i40e_dev_rxtx_init(pf);
2137 if (ret != I40E_SUCCESS) {
2138 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2142 /* Map queues with MSIX interrupt */
2143 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2144 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2145 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2146 i40e_vsi_enable_queues_intr(main_vsi);
2148 /* Map VMDQ VSI queues with MSIX interrupt */
2149 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2150 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2151 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2152 I40E_ITR_INDEX_DEFAULT);
2153 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2156 /* enable FDIR MSIX interrupt */
2157 if (pf->fdir.fdir_vsi) {
2158 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2159 I40E_ITR_INDEX_NONE);
2160 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2163 /* Enable all queues which have been configured */
2164 ret = i40e_dev_switch_queues(pf, TRUE);
2165 if (ret != I40E_SUCCESS) {
2166 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2170 /* Enable receiving broadcast packets */
2171 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2172 if (ret != I40E_SUCCESS)
2173 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2175 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2176 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2178 if (ret != I40E_SUCCESS)
2179 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2182 /* Enable the VLAN promiscuous mode. */
2184 for (i = 0; i < pf->vf_num; i++) {
2185 vsi = pf->vfs[i].vsi;
2186 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2191 /* Apply link configure */
2192 ret = i40e_apply_link_speed(dev);
2193 if (I40E_SUCCESS != ret) {
2194 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2198 if (!rte_intr_allow_others(intr_handle)) {
2199 rte_intr_callback_unregister(intr_handle,
2200 i40e_dev_interrupt_handler,
2202 /* configure and enable device interrupt */
2203 i40e_pf_config_irq0(hw, FALSE);
2204 i40e_pf_enable_irq0(hw);
2206 if (dev->data->dev_conf.intr_conf.lsc != 0)
2208 "lsc won't enable because of no intr multiplex");
2210 ret = i40e_aq_set_phy_int_mask(hw,
2211 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2212 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2213 I40E_AQ_EVENT_MEDIA_NA), NULL);
2214 if (ret != I40E_SUCCESS)
2215 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2217 /* Call get_link_info aq commond to enable/disable LSE */
2218 i40e_dev_link_update(dev, 0);
2221 /* enable uio intr after callback register */
2222 rte_intr_enable(intr_handle);
2224 i40e_filter_restore(pf);
2226 if (pf->tm_conf.root && !pf->tm_conf.committed)
2227 PMD_DRV_LOG(WARNING,
2228 "please call hierarchy_commit() "
2229 "before starting the port");
2231 return I40E_SUCCESS;
2234 i40e_dev_switch_queues(pf, FALSE);
2235 i40e_dev_clear_queues(dev);
2241 i40e_dev_stop(struct rte_eth_dev *dev)
2243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245 struct i40e_vsi *main_vsi = pf->main_vsi;
2246 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2247 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2250 if (hw->adapter_stopped == 1)
2252 /* Disable all queues */
2253 i40e_dev_switch_queues(pf, FALSE);
2255 /* un-map queues with interrupt registers */
2256 i40e_vsi_disable_queues_intr(main_vsi);
2257 i40e_vsi_queues_unbind_intr(main_vsi);
2259 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2260 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2261 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2264 if (pf->fdir.fdir_vsi) {
2265 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2266 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2268 /* Clear all queues and release memory */
2269 i40e_dev_clear_queues(dev);
2272 i40e_dev_set_link_down(dev);
2274 if (!rte_intr_allow_others(intr_handle))
2275 /* resume to the default handler */
2276 rte_intr_callback_register(intr_handle,
2277 i40e_dev_interrupt_handler,
2280 /* Clean datapath event and queue/vec mapping */
2281 rte_intr_efd_disable(intr_handle);
2282 if (intr_handle->intr_vec) {
2283 rte_free(intr_handle->intr_vec);
2284 intr_handle->intr_vec = NULL;
2287 /* reset hierarchy commit */
2288 pf->tm_conf.committed = false;
2290 hw->adapter_stopped = 1;
2294 i40e_dev_close(struct rte_eth_dev *dev)
2296 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2297 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2299 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2300 struct i40e_mirror_rule *p_mirror;
2305 PMD_INIT_FUNC_TRACE();
2309 /* Remove all mirror rules */
2310 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2311 ret = i40e_aq_del_mirror_rule(hw,
2312 pf->main_vsi->veb->seid,
2313 p_mirror->rule_type,
2315 p_mirror->num_entries,
2318 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2319 "status = %d, aq_err = %d.", ret,
2320 hw->aq.asq_last_status);
2322 /* remove mirror software resource anyway */
2323 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2325 pf->nb_mirror_rule--;
2328 i40e_dev_free_queues(dev);
2330 /* Disable interrupt */
2331 i40e_pf_disable_irq0(hw);
2332 rte_intr_disable(intr_handle);
2334 i40e_fdir_teardown(pf);
2336 /* shutdown and destroy the HMC */
2337 i40e_shutdown_lan_hmc(hw);
2339 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2340 i40e_vsi_release(pf->vmdq[i].vsi);
2341 pf->vmdq[i].vsi = NULL;
2346 /* release all the existing VSIs and VEBs */
2347 i40e_vsi_release(pf->main_vsi);
2349 /* shutdown the adminq */
2350 i40e_aq_queue_shutdown(hw, true);
2351 i40e_shutdown_adminq(hw);
2353 i40e_res_pool_destroy(&pf->qp_pool);
2354 i40e_res_pool_destroy(&pf->msix_pool);
2356 /* force a PF reset to clean anything leftover */
2357 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2358 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2359 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2360 I40E_WRITE_FLUSH(hw);
2364 * Reset PF device only to re-initialize resources in PMD layer
2367 i40e_dev_reset(struct rte_eth_dev *dev)
2371 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2372 * its VF to make them align with it. The detailed notification
2373 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2374 * To avoid unexpected behavior in VF, currently reset of PF with
2375 * SR-IOV activation is not supported. It might be supported later.
2377 if (dev->data->sriov.active)
2380 ret = eth_i40e_dev_uninit(dev);
2384 ret = eth_i40e_dev_init(dev);
2390 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2392 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2393 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394 struct i40e_vsi *vsi = pf->main_vsi;
2397 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2399 if (status != I40E_SUCCESS)
2400 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2402 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2404 if (status != I40E_SUCCESS)
2405 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2410 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2412 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2413 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414 struct i40e_vsi *vsi = pf->main_vsi;
2417 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2419 if (status != I40E_SUCCESS)
2420 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2422 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2424 if (status != I40E_SUCCESS)
2425 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2429 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2431 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2432 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433 struct i40e_vsi *vsi = pf->main_vsi;
2436 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2437 if (ret != I40E_SUCCESS)
2438 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2442 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2445 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446 struct i40e_vsi *vsi = pf->main_vsi;
2449 if (dev->data->promiscuous == 1)
2450 return; /* must remain in all_multicast mode */
2452 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2453 vsi->seid, FALSE, NULL);
2454 if (ret != I40E_SUCCESS)
2455 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2459 * Set device link up.
2462 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2464 /* re-apply link speed setting */
2465 return i40e_apply_link_speed(dev);
2469 * Set device link down.
2472 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2474 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2475 uint8_t abilities = 0;
2476 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2478 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2479 return i40e_phy_conf_link(hw, abilities, speed, false);
2482 static __rte_always_inline void
2483 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2485 /* Link status registers and values*/
2486 #define I40E_PRTMAC_LINKSTA 0x001E2420
2487 #define I40E_REG_LINK_UP 0x40000080
2488 #define I40E_PRTMAC_MACC 0x001E24E0
2489 #define I40E_REG_MACC_25GB 0x00020000
2490 #define I40E_REG_SPEED_MASK 0x38000000
2491 #define I40E_REG_SPEED_100MB 0x00000000
2492 #define I40E_REG_SPEED_1GB 0x08000000
2493 #define I40E_REG_SPEED_10GB 0x10000000
2494 #define I40E_REG_SPEED_20GB 0x20000000
2495 #define I40E_REG_SPEED_25_40GB 0x18000000
2496 uint32_t link_speed;
2499 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2500 link_speed = reg_val & I40E_REG_SPEED_MASK;
2501 reg_val &= I40E_REG_LINK_UP;
2502 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2504 if (unlikely(link->link_status == 0))
2507 /* Parse the link status */
2508 switch (link_speed) {
2509 case I40E_REG_SPEED_100MB:
2510 link->link_speed = ETH_SPEED_NUM_100M;
2512 case I40E_REG_SPEED_1GB:
2513 link->link_speed = ETH_SPEED_NUM_1G;
2515 case I40E_REG_SPEED_10GB:
2516 link->link_speed = ETH_SPEED_NUM_10G;
2518 case I40E_REG_SPEED_20GB:
2519 link->link_speed = ETH_SPEED_NUM_20G;
2521 case I40E_REG_SPEED_25_40GB:
2522 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2524 if (reg_val & I40E_REG_MACC_25GB)
2525 link->link_speed = ETH_SPEED_NUM_25G;
2527 link->link_speed = ETH_SPEED_NUM_40G;
2531 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2536 static __rte_always_inline void
2537 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2540 #define CHECK_INTERVAL 100 /* 100ms */
2541 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2542 uint32_t rep_cnt = MAX_REPEAT_TIME;
2543 struct i40e_link_status link_status;
2546 memset(&link_status, 0, sizeof(link_status));
2549 /* Get link status information from hardware */
2550 status = i40e_aq_get_link_info(hw, enable_lse,
2551 &link_status, NULL);
2552 if (unlikely(status != I40E_SUCCESS)) {
2553 link->link_speed = ETH_SPEED_NUM_100M;
2554 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2555 PMD_DRV_LOG(ERR, "Failed to get link info");
2559 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2560 if (unlikely(link->link_status != 0))
2563 rte_delay_ms(CHECK_INTERVAL);
2564 } while (--rep_cnt);
2566 /* Parse the link status */
2567 switch (link_status.link_speed) {
2568 case I40E_LINK_SPEED_100MB:
2569 link->link_speed = ETH_SPEED_NUM_100M;
2571 case I40E_LINK_SPEED_1GB:
2572 link->link_speed = ETH_SPEED_NUM_1G;
2574 case I40E_LINK_SPEED_10GB:
2575 link->link_speed = ETH_SPEED_NUM_10G;
2577 case I40E_LINK_SPEED_20GB:
2578 link->link_speed = ETH_SPEED_NUM_20G;
2580 case I40E_LINK_SPEED_25GB:
2581 link->link_speed = ETH_SPEED_NUM_25G;
2583 case I40E_LINK_SPEED_40GB:
2584 link->link_speed = ETH_SPEED_NUM_40G;
2587 link->link_speed = ETH_SPEED_NUM_100M;
2593 i40e_dev_link_update(struct rte_eth_dev *dev,
2594 int wait_to_complete)
2596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2597 struct rte_eth_link link, old;
2598 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2600 memset(&link, 0, sizeof(link));
2601 memset(&old, 0, sizeof(old));
2603 rte_i40e_dev_atomic_read_link_status(dev, &old);
2605 /* i40e uses full duplex only */
2606 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2607 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2608 ETH_LINK_SPEED_FIXED);
2610 if (!wait_to_complete)
2611 update_link_no_wait(hw, &link);
2613 update_link_wait(hw, &link, enable_lse);
2615 rte_i40e_dev_atomic_write_link_status(dev, &link);
2616 if (link.link_status == old.link_status)
2619 i40e_notify_all_vfs_link_status(dev);
2624 /* Get all the statistics of a VSI */
2626 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2628 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2629 struct i40e_eth_stats *nes = &vsi->eth_stats;
2630 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2631 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2633 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2634 vsi->offset_loaded, &oes->rx_bytes,
2636 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2637 vsi->offset_loaded, &oes->rx_unicast,
2639 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2640 vsi->offset_loaded, &oes->rx_multicast,
2641 &nes->rx_multicast);
2642 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2643 vsi->offset_loaded, &oes->rx_broadcast,
2644 &nes->rx_broadcast);
2645 /* exclude CRC bytes */
2646 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2647 nes->rx_broadcast) * ETHER_CRC_LEN;
2649 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2650 &oes->rx_discards, &nes->rx_discards);
2651 /* GLV_REPC not supported */
2652 /* GLV_RMPC not supported */
2653 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2654 &oes->rx_unknown_protocol,
2655 &nes->rx_unknown_protocol);
2656 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2657 vsi->offset_loaded, &oes->tx_bytes,
2659 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2660 vsi->offset_loaded, &oes->tx_unicast,
2662 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2663 vsi->offset_loaded, &oes->tx_multicast,
2664 &nes->tx_multicast);
2665 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2666 vsi->offset_loaded, &oes->tx_broadcast,
2667 &nes->tx_broadcast);
2668 /* GLV_TDPC not supported */
2669 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2670 &oes->tx_errors, &nes->tx_errors);
2671 vsi->offset_loaded = true;
2673 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2675 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2676 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2677 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2678 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2679 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2680 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2681 nes->rx_unknown_protocol);
2682 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2683 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2684 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2685 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2686 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2687 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2688 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2693 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2696 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2697 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2699 /* Get rx/tx bytes of internal transfer packets */
2700 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2701 I40E_GLV_GORCL(hw->port),
2703 &pf->internal_stats_offset.rx_bytes,
2704 &pf->internal_stats.rx_bytes);
2706 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2707 I40E_GLV_GOTCL(hw->port),
2709 &pf->internal_stats_offset.tx_bytes,
2710 &pf->internal_stats.tx_bytes);
2711 /* Get total internal rx packet count */
2712 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2713 I40E_GLV_UPRCL(hw->port),
2715 &pf->internal_stats_offset.rx_unicast,
2716 &pf->internal_stats.rx_unicast);
2717 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2718 I40E_GLV_MPRCL(hw->port),
2720 &pf->internal_stats_offset.rx_multicast,
2721 &pf->internal_stats.rx_multicast);
2722 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2723 I40E_GLV_BPRCL(hw->port),
2725 &pf->internal_stats_offset.rx_broadcast,
2726 &pf->internal_stats.rx_broadcast);
2727 /* Get total internal tx packet count */
2728 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2729 I40E_GLV_UPTCL(hw->port),
2731 &pf->internal_stats_offset.tx_unicast,
2732 &pf->internal_stats.tx_unicast);
2733 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2734 I40E_GLV_MPTCL(hw->port),
2736 &pf->internal_stats_offset.tx_multicast,
2737 &pf->internal_stats.tx_multicast);
2738 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2739 I40E_GLV_BPTCL(hw->port),
2741 &pf->internal_stats_offset.tx_broadcast,
2742 &pf->internal_stats.tx_broadcast);
2744 /* exclude CRC size */
2745 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2746 pf->internal_stats.rx_multicast +
2747 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2749 /* Get statistics of struct i40e_eth_stats */
2750 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2751 I40E_GLPRT_GORCL(hw->port),
2752 pf->offset_loaded, &os->eth.rx_bytes,
2754 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2755 I40E_GLPRT_UPRCL(hw->port),
2756 pf->offset_loaded, &os->eth.rx_unicast,
2757 &ns->eth.rx_unicast);
2758 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2759 I40E_GLPRT_MPRCL(hw->port),
2760 pf->offset_loaded, &os->eth.rx_multicast,
2761 &ns->eth.rx_multicast);
2762 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2763 I40E_GLPRT_BPRCL(hw->port),
2764 pf->offset_loaded, &os->eth.rx_broadcast,
2765 &ns->eth.rx_broadcast);
2766 /* Workaround: CRC size should not be included in byte statistics,
2767 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2769 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2770 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2772 /* exclude internal rx bytes
2773 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2774 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2776 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2778 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2779 ns->eth.rx_bytes = 0;
2781 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2783 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2784 ns->eth.rx_unicast = 0;
2786 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2788 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2789 ns->eth.rx_multicast = 0;
2791 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2793 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2794 ns->eth.rx_broadcast = 0;
2796 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2798 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2799 pf->offset_loaded, &os->eth.rx_discards,
2800 &ns->eth.rx_discards);
2801 /* GLPRT_REPC not supported */
2802 /* GLPRT_RMPC not supported */
2803 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2805 &os->eth.rx_unknown_protocol,
2806 &ns->eth.rx_unknown_protocol);
2807 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2808 I40E_GLPRT_GOTCL(hw->port),
2809 pf->offset_loaded, &os->eth.tx_bytes,
2811 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2812 I40E_GLPRT_UPTCL(hw->port),
2813 pf->offset_loaded, &os->eth.tx_unicast,
2814 &ns->eth.tx_unicast);
2815 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2816 I40E_GLPRT_MPTCL(hw->port),
2817 pf->offset_loaded, &os->eth.tx_multicast,
2818 &ns->eth.tx_multicast);
2819 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2820 I40E_GLPRT_BPTCL(hw->port),
2821 pf->offset_loaded, &os->eth.tx_broadcast,
2822 &ns->eth.tx_broadcast);
2823 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2824 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2826 /* exclude internal tx bytes
2827 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2828 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2830 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2832 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2833 ns->eth.tx_bytes = 0;
2835 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2837 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2838 ns->eth.tx_unicast = 0;
2840 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2842 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2843 ns->eth.tx_multicast = 0;
2845 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2847 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2848 ns->eth.tx_broadcast = 0;
2850 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2852 /* GLPRT_TEPC not supported */
2854 /* additional port specific stats */
2855 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2856 pf->offset_loaded, &os->tx_dropped_link_down,
2857 &ns->tx_dropped_link_down);
2858 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2859 pf->offset_loaded, &os->crc_errors,
2861 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2862 pf->offset_loaded, &os->illegal_bytes,
2863 &ns->illegal_bytes);
2864 /* GLPRT_ERRBC not supported */
2865 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2866 pf->offset_loaded, &os->mac_local_faults,
2867 &ns->mac_local_faults);
2868 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2869 pf->offset_loaded, &os->mac_remote_faults,
2870 &ns->mac_remote_faults);
2871 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2872 pf->offset_loaded, &os->rx_length_errors,
2873 &ns->rx_length_errors);
2874 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2875 pf->offset_loaded, &os->link_xon_rx,
2877 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2878 pf->offset_loaded, &os->link_xoff_rx,
2880 for (i = 0; i < 8; i++) {
2881 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2883 &os->priority_xon_rx[i],
2884 &ns->priority_xon_rx[i]);
2885 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2887 &os->priority_xoff_rx[i],
2888 &ns->priority_xoff_rx[i]);
2890 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2891 pf->offset_loaded, &os->link_xon_tx,
2893 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2894 pf->offset_loaded, &os->link_xoff_tx,
2896 for (i = 0; i < 8; i++) {
2897 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2899 &os->priority_xon_tx[i],
2900 &ns->priority_xon_tx[i]);
2901 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2903 &os->priority_xoff_tx[i],
2904 &ns->priority_xoff_tx[i]);
2905 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2907 &os->priority_xon_2_xoff[i],
2908 &ns->priority_xon_2_xoff[i]);
2910 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2911 I40E_GLPRT_PRC64L(hw->port),
2912 pf->offset_loaded, &os->rx_size_64,
2914 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2915 I40E_GLPRT_PRC127L(hw->port),
2916 pf->offset_loaded, &os->rx_size_127,
2918 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2919 I40E_GLPRT_PRC255L(hw->port),
2920 pf->offset_loaded, &os->rx_size_255,
2922 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2923 I40E_GLPRT_PRC511L(hw->port),
2924 pf->offset_loaded, &os->rx_size_511,
2926 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2927 I40E_GLPRT_PRC1023L(hw->port),
2928 pf->offset_loaded, &os->rx_size_1023,
2930 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2931 I40E_GLPRT_PRC1522L(hw->port),
2932 pf->offset_loaded, &os->rx_size_1522,
2934 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2935 I40E_GLPRT_PRC9522L(hw->port),
2936 pf->offset_loaded, &os->rx_size_big,
2938 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2939 pf->offset_loaded, &os->rx_undersize,
2941 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2942 pf->offset_loaded, &os->rx_fragments,
2944 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2945 pf->offset_loaded, &os->rx_oversize,
2947 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2948 pf->offset_loaded, &os->rx_jabber,
2950 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2951 I40E_GLPRT_PTC64L(hw->port),
2952 pf->offset_loaded, &os->tx_size_64,
2954 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2955 I40E_GLPRT_PTC127L(hw->port),
2956 pf->offset_loaded, &os->tx_size_127,
2958 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2959 I40E_GLPRT_PTC255L(hw->port),
2960 pf->offset_loaded, &os->tx_size_255,
2962 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2963 I40E_GLPRT_PTC511L(hw->port),
2964 pf->offset_loaded, &os->tx_size_511,
2966 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2967 I40E_GLPRT_PTC1023L(hw->port),
2968 pf->offset_loaded, &os->tx_size_1023,
2970 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2971 I40E_GLPRT_PTC1522L(hw->port),
2972 pf->offset_loaded, &os->tx_size_1522,
2974 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2975 I40E_GLPRT_PTC9522L(hw->port),
2976 pf->offset_loaded, &os->tx_size_big,
2978 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2980 &os->fd_sb_match, &ns->fd_sb_match);
2981 /* GLPRT_MSPDC not supported */
2982 /* GLPRT_XEC not supported */
2984 pf->offset_loaded = true;
2987 i40e_update_vsi_stats(pf->main_vsi);
2990 /* Get all statistics of a port */
2992 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2994 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2995 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2996 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2999 /* call read registers - updates values, now write them to struct */
3000 i40e_read_stats_registers(pf, hw);
3002 stats->ipackets = ns->eth.rx_unicast +
3003 ns->eth.rx_multicast +
3004 ns->eth.rx_broadcast -
3005 ns->eth.rx_discards -
3006 pf->main_vsi->eth_stats.rx_discards;
3007 stats->opackets = ns->eth.tx_unicast +
3008 ns->eth.tx_multicast +
3009 ns->eth.tx_broadcast;
3010 stats->ibytes = ns->eth.rx_bytes;
3011 stats->obytes = ns->eth.tx_bytes;
3012 stats->oerrors = ns->eth.tx_errors +
3013 pf->main_vsi->eth_stats.tx_errors;
3016 stats->imissed = ns->eth.rx_discards +
3017 pf->main_vsi->eth_stats.rx_discards;
3018 stats->ierrors = ns->crc_errors +
3019 ns->rx_length_errors + ns->rx_undersize +
3020 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3022 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3023 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3024 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3025 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3026 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3027 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3028 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3029 ns->eth.rx_unknown_protocol);
3030 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3031 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3032 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3033 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3034 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3035 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3037 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3038 ns->tx_dropped_link_down);
3039 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3040 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3042 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3043 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3044 ns->mac_local_faults);
3045 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3046 ns->mac_remote_faults);
3047 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3048 ns->rx_length_errors);
3049 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3050 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3051 for (i = 0; i < 8; i++) {
3052 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3053 i, ns->priority_xon_rx[i]);
3054 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3055 i, ns->priority_xoff_rx[i]);
3057 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3058 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3059 for (i = 0; i < 8; i++) {
3060 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3061 i, ns->priority_xon_tx[i]);
3062 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3063 i, ns->priority_xoff_tx[i]);
3064 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3065 i, ns->priority_xon_2_xoff[i]);
3067 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3068 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3069 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3070 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3071 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3072 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3073 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3074 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3075 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3076 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3077 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3078 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3079 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3080 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3081 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3082 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3083 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3084 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3085 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3086 ns->mac_short_packet_dropped);
3087 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3088 ns->checksum_error);
3089 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3090 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3094 /* Reset the statistics */
3096 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3098 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3099 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3101 /* Mark PF and VSI stats to update the offset, aka "reset" */
3102 pf->offset_loaded = false;
3104 pf->main_vsi->offset_loaded = false;
3106 /* read the stats, reading current register values into offset */
3107 i40e_read_stats_registers(pf, hw);
3111 i40e_xstats_calc_num(void)
3113 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3114 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3115 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3118 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3119 struct rte_eth_xstat_name *xstats_names,
3120 __rte_unused unsigned limit)
3125 if (xstats_names == NULL)
3126 return i40e_xstats_calc_num();
3128 /* Note: limit checked in rte_eth_xstats_names() */
3130 /* Get stats from i40e_eth_stats struct */
3131 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3132 snprintf(xstats_names[count].name,
3133 sizeof(xstats_names[count].name),
3134 "%s", rte_i40e_stats_strings[i].name);
3138 /* Get individiual stats from i40e_hw_port struct */
3139 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3140 snprintf(xstats_names[count].name,
3141 sizeof(xstats_names[count].name),
3142 "%s", rte_i40e_hw_port_strings[i].name);
3146 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3147 for (prio = 0; prio < 8; prio++) {
3148 snprintf(xstats_names[count].name,
3149 sizeof(xstats_names[count].name),
3150 "rx_priority%u_%s", prio,
3151 rte_i40e_rxq_prio_strings[i].name);
3156 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3157 for (prio = 0; prio < 8; prio++) {
3158 snprintf(xstats_names[count].name,
3159 sizeof(xstats_names[count].name),
3160 "tx_priority%u_%s", prio,
3161 rte_i40e_txq_prio_strings[i].name);
3169 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3172 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3173 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3174 unsigned i, count, prio;
3175 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3177 count = i40e_xstats_calc_num();
3181 i40e_read_stats_registers(pf, hw);
3188 /* Get stats from i40e_eth_stats struct */
3189 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3190 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3191 rte_i40e_stats_strings[i].offset);
3192 xstats[count].id = count;
3196 /* Get individiual stats from i40e_hw_port struct */
3197 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3198 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3199 rte_i40e_hw_port_strings[i].offset);
3200 xstats[count].id = count;
3204 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3205 for (prio = 0; prio < 8; prio++) {
3206 xstats[count].value =
3207 *(uint64_t *)(((char *)hw_stats) +
3208 rte_i40e_rxq_prio_strings[i].offset +
3209 (sizeof(uint64_t) * prio));
3210 xstats[count].id = count;
3215 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3216 for (prio = 0; prio < 8; prio++) {
3217 xstats[count].value =
3218 *(uint64_t *)(((char *)hw_stats) +
3219 rte_i40e_txq_prio_strings[i].offset +
3220 (sizeof(uint64_t) * prio));
3221 xstats[count].id = count;
3230 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3231 __rte_unused uint16_t queue_id,
3232 __rte_unused uint8_t stat_idx,
3233 __rte_unused uint8_t is_rx)
3235 PMD_INIT_FUNC_TRACE();
3241 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3243 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3249 full_ver = hw->nvm.oem_ver;
3250 ver = (u8)(full_ver >> 24);
3251 build = (u16)((full_ver >> 8) & 0xffff);
3252 patch = (u8)(full_ver & 0xff);
3254 ret = snprintf(fw_version, fw_size,
3255 "%d.%d%d 0x%08x %d.%d.%d",
3256 ((hw->nvm.version >> 12) & 0xf),
3257 ((hw->nvm.version >> 4) & 0xff),
3258 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3261 ret += 1; /* add the size of '\0' */
3262 if (fw_size < (u32)ret)
3269 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3271 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3272 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3273 struct i40e_vsi *vsi = pf->main_vsi;
3274 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3276 dev_info->pci_dev = pci_dev;
3277 dev_info->max_rx_queues = vsi->nb_qps;
3278 dev_info->max_tx_queues = vsi->nb_qps;
3279 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3280 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3281 dev_info->max_mac_addrs = vsi->max_macaddrs;
3282 dev_info->max_vfs = pci_dev->max_vfs;
3283 dev_info->rx_offload_capa =
3284 DEV_RX_OFFLOAD_VLAN_STRIP |
3285 DEV_RX_OFFLOAD_QINQ_STRIP |
3286 DEV_RX_OFFLOAD_IPV4_CKSUM |
3287 DEV_RX_OFFLOAD_UDP_CKSUM |
3288 DEV_RX_OFFLOAD_TCP_CKSUM;
3289 dev_info->tx_offload_capa =
3290 DEV_TX_OFFLOAD_VLAN_INSERT |
3291 DEV_TX_OFFLOAD_QINQ_INSERT |
3292 DEV_TX_OFFLOAD_IPV4_CKSUM |
3293 DEV_TX_OFFLOAD_UDP_CKSUM |
3294 DEV_TX_OFFLOAD_TCP_CKSUM |
3295 DEV_TX_OFFLOAD_SCTP_CKSUM |
3296 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3297 DEV_TX_OFFLOAD_TCP_TSO |
3298 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3299 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3300 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3301 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3302 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3304 dev_info->reta_size = pf->hash_lut_size;
3305 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3307 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3309 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3310 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3311 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3313 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3317 dev_info->default_txconf = (struct rte_eth_txconf) {
3319 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3320 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3321 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3323 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3324 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3325 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3326 ETH_TXQ_FLAGS_NOOFFLOADS,
3329 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3330 .nb_max = I40E_MAX_RING_DESC,
3331 .nb_min = I40E_MIN_RING_DESC,
3332 .nb_align = I40E_ALIGN_RING_DESC,
3335 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3336 .nb_max = I40E_MAX_RING_DESC,
3337 .nb_min = I40E_MIN_RING_DESC,
3338 .nb_align = I40E_ALIGN_RING_DESC,
3339 .nb_seg_max = I40E_TX_MAX_SEG,
3340 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3343 if (pf->flags & I40E_FLAG_VMDQ) {
3344 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3345 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3346 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3347 pf->max_nb_vmdq_vsi;
3348 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3349 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3350 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3353 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3355 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3356 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3358 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3361 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3365 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3367 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3368 struct i40e_vsi *vsi = pf->main_vsi;
3369 PMD_INIT_FUNC_TRACE();
3372 return i40e_vsi_add_vlan(vsi, vlan_id);
3374 return i40e_vsi_delete_vlan(vsi, vlan_id);
3378 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3379 enum rte_vlan_type vlan_type,
3380 uint16_t tpid, int qinq)
3382 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385 uint16_t reg_id = 3;
3389 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3393 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3395 if (ret != I40E_SUCCESS) {
3397 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3402 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3405 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3406 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3407 if (reg_r == reg_w) {
3408 PMD_DRV_LOG(DEBUG, "No need to write");
3412 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3414 if (ret != I40E_SUCCESS) {
3416 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3421 "Global register 0x%08x is changed with value 0x%08x",
3422 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3428 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3429 enum rte_vlan_type vlan_type,
3432 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3433 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3434 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3437 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3438 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3439 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3441 "Unsupported vlan type.");
3445 if (pf->support_multi_driver) {
3446 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3450 /* 802.1ad frames ability is added in NVM API 1.7*/
3451 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3453 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3454 hw->first_tag = rte_cpu_to_le_16(tpid);
3455 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3456 hw->second_tag = rte_cpu_to_le_16(tpid);
3458 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3459 hw->second_tag = rte_cpu_to_le_16(tpid);
3461 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3462 if (ret != I40E_SUCCESS) {
3464 "Set switch config failed aq_err: %d",
3465 hw->aq.asq_last_status);
3469 /* If NVM API < 1.7, keep the register setting */
3470 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3472 i40e_global_cfg_warning(I40E_WARNING_TPID);
3478 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3481 struct i40e_vsi *vsi = pf->main_vsi;
3483 if (mask & ETH_VLAN_FILTER_MASK) {
3484 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3485 i40e_vsi_config_vlan_filter(vsi, TRUE);
3487 i40e_vsi_config_vlan_filter(vsi, FALSE);
3490 if (mask & ETH_VLAN_STRIP_MASK) {
3491 /* Enable or disable VLAN stripping */
3492 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3493 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3495 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3498 if (mask & ETH_VLAN_EXTEND_MASK) {
3499 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3500 i40e_vsi_config_double_vlan(vsi, TRUE);
3501 /* Set global registers with default ethertype. */
3502 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3504 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3508 i40e_vsi_config_double_vlan(vsi, FALSE);
3515 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3516 __rte_unused uint16_t queue,
3517 __rte_unused int on)
3519 PMD_INIT_FUNC_TRACE();
3523 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3525 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3526 struct i40e_vsi *vsi = pf->main_vsi;
3527 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3528 struct i40e_vsi_vlan_pvid_info info;
3530 memset(&info, 0, sizeof(info));
3533 info.config.pvid = pvid;
3535 info.config.reject.tagged =
3536 data->dev_conf.txmode.hw_vlan_reject_tagged;
3537 info.config.reject.untagged =
3538 data->dev_conf.txmode.hw_vlan_reject_untagged;
3541 return i40e_vsi_vlan_pvid_set(vsi, &info);
3545 i40e_dev_led_on(struct rte_eth_dev *dev)
3547 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548 uint32_t mode = i40e_led_get(hw);
3551 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3557 i40e_dev_led_off(struct rte_eth_dev *dev)
3559 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3560 uint32_t mode = i40e_led_get(hw);
3563 i40e_led_set(hw, 0, false);
3569 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3574 fc_conf->pause_time = pf->fc_conf.pause_time;
3576 /* read out from register, in case they are modified by other port */
3577 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3578 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3579 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3580 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3582 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3583 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3585 /* Return current mode according to actual setting*/
3586 switch (hw->fc.current_mode) {
3588 fc_conf->mode = RTE_FC_FULL;
3590 case I40E_FC_TX_PAUSE:
3591 fc_conf->mode = RTE_FC_TX_PAUSE;
3593 case I40E_FC_RX_PAUSE:
3594 fc_conf->mode = RTE_FC_RX_PAUSE;
3598 fc_conf->mode = RTE_FC_NONE;
3605 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3607 uint32_t mflcn_reg, fctrl_reg, reg;
3608 uint32_t max_high_water;
3609 uint8_t i, aq_failure;
3613 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3614 [RTE_FC_NONE] = I40E_FC_NONE,
3615 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3616 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3617 [RTE_FC_FULL] = I40E_FC_FULL
3620 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3622 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3623 if ((fc_conf->high_water > max_high_water) ||
3624 (fc_conf->high_water < fc_conf->low_water)) {
3626 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3631 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3632 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3633 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3635 pf->fc_conf.pause_time = fc_conf->pause_time;
3636 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3637 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3639 PMD_INIT_FUNC_TRACE();
3641 /* All the link flow control related enable/disable register
3642 * configuration is handle by the F/W
3644 err = i40e_set_fc(hw, &aq_failure, true);
3648 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3649 /* Configure flow control refresh threshold,
3650 * the value for stat_tx_pause_refresh_timer[8]
3651 * is used for global pause operation.
3655 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3656 pf->fc_conf.pause_time);
3658 /* configure the timer value included in transmitted pause
3660 * the value for stat_tx_pause_quanta[8] is used for global
3663 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3664 pf->fc_conf.pause_time);
3666 fctrl_reg = I40E_READ_REG(hw,
3667 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3669 if (fc_conf->mac_ctrl_frame_fwd != 0)
3670 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3672 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3674 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3677 /* Configure pause time (2 TCs per register) */
3678 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3679 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3680 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3682 /* Configure flow control refresh threshold value */
3683 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3684 pf->fc_conf.pause_time / 2);
3686 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3688 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3689 *depending on configuration
3691 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3692 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3693 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3695 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3696 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3699 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3702 if (!pf->support_multi_driver) {
3703 /* config water marker both based on the packets and bytes */
3704 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3705 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3706 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3707 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3708 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3709 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3710 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3711 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3713 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3714 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3716 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3719 "Water marker configuration is not supported.");
3722 I40E_WRITE_FLUSH(hw);
3728 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3729 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3731 PMD_INIT_FUNC_TRACE();
3736 /* Add a MAC address, and update filters */
3738 i40e_macaddr_add(struct rte_eth_dev *dev,
3739 struct ether_addr *mac_addr,
3740 __rte_unused uint32_t index,
3743 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3744 struct i40e_mac_filter_info mac_filter;
3745 struct i40e_vsi *vsi;
3748 /* If VMDQ not enabled or configured, return */
3749 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3750 !pf->nb_cfg_vmdq_vsi)) {
3751 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3752 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3757 if (pool > pf->nb_cfg_vmdq_vsi) {
3758 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3759 pool, pf->nb_cfg_vmdq_vsi);
3763 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3764 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3765 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3767 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3772 vsi = pf->vmdq[pool - 1].vsi;
3774 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3775 if (ret != I40E_SUCCESS) {
3776 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3782 /* Remove a MAC address, and update filters */
3784 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3786 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3787 struct i40e_vsi *vsi;
3788 struct rte_eth_dev_data *data = dev->data;
3789 struct ether_addr *macaddr;
3794 macaddr = &(data->mac_addrs[index]);
3796 pool_sel = dev->data->mac_pool_sel[index];
3798 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3799 if (pool_sel & (1ULL << i)) {
3803 /* No VMDQ pool enabled or configured */
3804 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3805 (i > pf->nb_cfg_vmdq_vsi)) {
3807 "No VMDQ pool enabled/configured");
3810 vsi = pf->vmdq[i - 1].vsi;
3812 ret = i40e_vsi_delete_mac(vsi, macaddr);
3815 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3822 /* Set perfect match or hash match of MAC and VLAN for a VF */
3824 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3825 struct rte_eth_mac_filter *filter,
3829 struct i40e_mac_filter_info mac_filter;
3830 struct ether_addr old_mac;
3831 struct ether_addr *new_mac;
3832 struct i40e_pf_vf *vf = NULL;
3837 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3840 hw = I40E_PF_TO_HW(pf);
3842 if (filter == NULL) {
3843 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3847 new_mac = &filter->mac_addr;
3849 if (is_zero_ether_addr(new_mac)) {
3850 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3854 vf_id = filter->dst_id;
3856 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3857 PMD_DRV_LOG(ERR, "Invalid argument.");
3860 vf = &pf->vfs[vf_id];
3862 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3863 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3868 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3869 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3871 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3874 mac_filter.filter_type = filter->filter_type;
3875 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3876 if (ret != I40E_SUCCESS) {
3877 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3880 ether_addr_copy(new_mac, &pf->dev_addr);
3882 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3884 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3885 if (ret != I40E_SUCCESS) {
3886 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3890 /* Clear device address as it has been removed */
3891 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3892 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3898 /* MAC filter handle */
3900 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3903 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3904 struct rte_eth_mac_filter *filter;
3905 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3906 int ret = I40E_NOT_SUPPORTED;
3908 filter = (struct rte_eth_mac_filter *)(arg);
3910 switch (filter_op) {
3911 case RTE_ETH_FILTER_NOP:
3914 case RTE_ETH_FILTER_ADD:
3915 i40e_pf_disable_irq0(hw);
3917 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3918 i40e_pf_enable_irq0(hw);
3920 case RTE_ETH_FILTER_DELETE:
3921 i40e_pf_disable_irq0(hw);
3923 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3924 i40e_pf_enable_irq0(hw);
3927 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3928 ret = I40E_ERR_PARAM;
3936 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3938 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3939 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3945 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3946 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3949 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3953 uint32_t *lut_dw = (uint32_t *)lut;
3954 uint16_t i, lut_size_dw = lut_size / 4;
3956 for (i = 0; i < lut_size_dw; i++)
3957 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3964 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3973 pf = I40E_VSI_TO_PF(vsi);
3974 hw = I40E_VSI_TO_HW(vsi);
3976 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3977 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3980 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3984 uint32_t *lut_dw = (uint32_t *)lut;
3985 uint16_t i, lut_size_dw = lut_size / 4;
3987 for (i = 0; i < lut_size_dw; i++)
3988 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3989 I40E_WRITE_FLUSH(hw);
3996 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3997 struct rte_eth_rss_reta_entry64 *reta_conf,
4000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4001 uint16_t i, lut_size = pf->hash_lut_size;
4002 uint16_t idx, shift;
4006 if (reta_size != lut_size ||
4007 reta_size > ETH_RSS_RETA_SIZE_512) {
4009 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4010 reta_size, lut_size);
4014 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4016 PMD_DRV_LOG(ERR, "No memory can be allocated");
4019 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4022 for (i = 0; i < reta_size; i++) {
4023 idx = i / RTE_RETA_GROUP_SIZE;
4024 shift = i % RTE_RETA_GROUP_SIZE;
4025 if (reta_conf[idx].mask & (1ULL << shift))
4026 lut[i] = reta_conf[idx].reta[shift];
4028 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4037 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4038 struct rte_eth_rss_reta_entry64 *reta_conf,
4041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4042 uint16_t i, lut_size = pf->hash_lut_size;
4043 uint16_t idx, shift;
4047 if (reta_size != lut_size ||
4048 reta_size > ETH_RSS_RETA_SIZE_512) {
4050 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4051 reta_size, lut_size);
4055 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4057 PMD_DRV_LOG(ERR, "No memory can be allocated");
4061 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4064 for (i = 0; i < reta_size; i++) {
4065 idx = i / RTE_RETA_GROUP_SIZE;
4066 shift = i % RTE_RETA_GROUP_SIZE;
4067 if (reta_conf[idx].mask & (1ULL << shift))
4068 reta_conf[idx].reta[shift] = lut[i];
4078 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4079 * @hw: pointer to the HW structure
4080 * @mem: pointer to mem struct to fill out
4081 * @size: size of memory requested
4082 * @alignment: what to align the allocation to
4084 enum i40e_status_code
4085 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4086 struct i40e_dma_mem *mem,
4090 const struct rte_memzone *mz = NULL;
4091 char z_name[RTE_MEMZONE_NAMESIZE];
4094 return I40E_ERR_PARAM;
4096 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4097 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
4098 alignment, RTE_PGSIZE_2M);
4100 return I40E_ERR_NO_MEMORY;
4105 mem->zone = (const void *)mz;
4107 "memzone %s allocated with physical address: %"PRIu64,
4110 return I40E_SUCCESS;
4114 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4115 * @hw: pointer to the HW structure
4116 * @mem: ptr to mem struct to free
4118 enum i40e_status_code
4119 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4120 struct i40e_dma_mem *mem)
4123 return I40E_ERR_PARAM;
4126 "memzone %s to be freed with physical address: %"PRIu64,
4127 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4128 rte_memzone_free((const struct rte_memzone *)mem->zone);
4133 return I40E_SUCCESS;
4137 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4138 * @hw: pointer to the HW structure
4139 * @mem: pointer to mem struct to fill out
4140 * @size: size of memory requested
4142 enum i40e_status_code
4143 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4144 struct i40e_virt_mem *mem,
4148 return I40E_ERR_PARAM;
4151 mem->va = rte_zmalloc("i40e", size, 0);
4154 return I40E_SUCCESS;
4156 return I40E_ERR_NO_MEMORY;
4160 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4161 * @hw: pointer to the HW structure
4162 * @mem: pointer to mem struct to free
4164 enum i40e_status_code
4165 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4166 struct i40e_virt_mem *mem)
4169 return I40E_ERR_PARAM;
4174 return I40E_SUCCESS;
4178 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4180 rte_spinlock_init(&sp->spinlock);
4184 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4186 rte_spinlock_lock(&sp->spinlock);
4190 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4192 rte_spinlock_unlock(&sp->spinlock);
4196 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4202 * Get the hardware capabilities, which will be parsed
4203 * and saved into struct i40e_hw.
4206 i40e_get_cap(struct i40e_hw *hw)
4208 struct i40e_aqc_list_capabilities_element_resp *buf;
4209 uint16_t len, size = 0;
4212 /* Calculate a huge enough buff for saving response data temporarily */
4213 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4214 I40E_MAX_CAP_ELE_NUM;
4215 buf = rte_zmalloc("i40e", len, 0);
4217 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4218 return I40E_ERR_NO_MEMORY;
4221 /* Get, parse the capabilities and save it to hw */
4222 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4223 i40e_aqc_opc_list_func_capabilities, NULL);
4224 if (ret != I40E_SUCCESS)
4225 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4227 /* Free the temporary buffer after being used */
4234 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4236 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4237 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4238 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4239 uint16_t qp_count = 0, vsi_count = 0;
4241 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4242 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4245 /* Add the parameter init for LFC */
4246 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4247 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4248 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4250 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4251 pf->max_num_vsi = hw->func_caps.num_vsis;
4252 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4253 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4254 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4256 /* FDir queue/VSI allocation */
4257 pf->fdir_qp_offset = 0;
4258 if (hw->func_caps.fd) {
4259 pf->flags |= I40E_FLAG_FDIR;
4260 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4262 pf->fdir_nb_qps = 0;
4264 qp_count += pf->fdir_nb_qps;
4267 /* LAN queue/VSI allocation */
4268 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4269 if (!hw->func_caps.rss) {
4272 pf->flags |= I40E_FLAG_RSS;
4273 if (hw->mac.type == I40E_MAC_X722)
4274 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4275 pf->lan_nb_qps = pf->lan_nb_qp_max;
4277 qp_count += pf->lan_nb_qps;
4280 /* VF queue/VSI allocation */
4281 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4282 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4283 pf->flags |= I40E_FLAG_SRIOV;
4284 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4285 pf->vf_num = pci_dev->max_vfs;
4287 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4288 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4293 qp_count += pf->vf_nb_qps * pf->vf_num;
4294 vsi_count += pf->vf_num;
4296 /* VMDq queue/VSI allocation */
4297 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4298 pf->vmdq_nb_qps = 0;
4299 pf->max_nb_vmdq_vsi = 0;
4300 if (hw->func_caps.vmdq) {
4301 if (qp_count < hw->func_caps.num_tx_qp &&
4302 vsi_count < hw->func_caps.num_vsis) {
4303 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4304 qp_count) / pf->vmdq_nb_qp_max;
4306 /* Limit the maximum number of VMDq vsi to the maximum
4307 * ethdev can support
4309 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4310 hw->func_caps.num_vsis - vsi_count);
4311 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4313 if (pf->max_nb_vmdq_vsi) {
4314 pf->flags |= I40E_FLAG_VMDQ;
4315 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4317 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4318 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4319 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4322 "No enough queues left for VMDq");
4325 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4328 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4329 vsi_count += pf->max_nb_vmdq_vsi;
4331 if (hw->func_caps.dcb)
4332 pf->flags |= I40E_FLAG_DCB;
4334 if (qp_count > hw->func_caps.num_tx_qp) {
4336 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4337 qp_count, hw->func_caps.num_tx_qp);
4340 if (vsi_count > hw->func_caps.num_vsis) {
4342 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4343 vsi_count, hw->func_caps.num_vsis);
4351 i40e_pf_get_switch_config(struct i40e_pf *pf)
4353 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4354 struct i40e_aqc_get_switch_config_resp *switch_config;
4355 struct i40e_aqc_switch_config_element_resp *element;
4356 uint16_t start_seid = 0, num_reported;
4359 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4360 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4361 if (!switch_config) {
4362 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4366 /* Get the switch configurations */
4367 ret = i40e_aq_get_switch_config(hw, switch_config,
4368 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4369 if (ret != I40E_SUCCESS) {
4370 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4373 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4374 if (num_reported != 1) { /* The number should be 1 */
4375 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4379 /* Parse the switch configuration elements */
4380 element = &(switch_config->element[0]);
4381 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4382 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4383 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4385 PMD_DRV_LOG(INFO, "Unknown element type");
4388 rte_free(switch_config);
4394 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4397 struct pool_entry *entry;
4399 if (pool == NULL || num == 0)
4402 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4403 if (entry == NULL) {
4404 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4408 /* queue heap initialize */
4409 pool->num_free = num;
4410 pool->num_alloc = 0;
4412 LIST_INIT(&pool->alloc_list);
4413 LIST_INIT(&pool->free_list);
4415 /* Initialize element */
4419 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4424 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4426 struct pool_entry *entry, *next_entry;
4431 for (entry = LIST_FIRST(&pool->alloc_list);
4432 entry && (next_entry = LIST_NEXT(entry, next), 1);
4433 entry = next_entry) {
4434 LIST_REMOVE(entry, next);
4438 for (entry = LIST_FIRST(&pool->free_list);
4439 entry && (next_entry = LIST_NEXT(entry, next), 1);
4440 entry = next_entry) {
4441 LIST_REMOVE(entry, next);
4446 pool->num_alloc = 0;
4448 LIST_INIT(&pool->alloc_list);
4449 LIST_INIT(&pool->free_list);
4453 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4456 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4457 uint32_t pool_offset;
4461 PMD_DRV_LOG(ERR, "Invalid parameter");
4465 pool_offset = base - pool->base;
4466 /* Lookup in alloc list */
4467 LIST_FOREACH(entry, &pool->alloc_list, next) {
4468 if (entry->base == pool_offset) {
4469 valid_entry = entry;
4470 LIST_REMOVE(entry, next);
4475 /* Not find, return */
4476 if (valid_entry == NULL) {
4477 PMD_DRV_LOG(ERR, "Failed to find entry");
4482 * Found it, move it to free list and try to merge.
4483 * In order to make merge easier, always sort it by qbase.
4484 * Find adjacent prev and last entries.
4487 LIST_FOREACH(entry, &pool->free_list, next) {
4488 if (entry->base > valid_entry->base) {
4496 /* Try to merge with next one*/
4498 /* Merge with next one */
4499 if (valid_entry->base + valid_entry->len == next->base) {
4500 next->base = valid_entry->base;
4501 next->len += valid_entry->len;
4502 rte_free(valid_entry);
4509 /* Merge with previous one */
4510 if (prev->base + prev->len == valid_entry->base) {
4511 prev->len += valid_entry->len;
4512 /* If it merge with next one, remove next node */
4514 LIST_REMOVE(valid_entry, next);
4515 rte_free(valid_entry);
4517 rte_free(valid_entry);
4523 /* Not find any entry to merge, insert */
4526 LIST_INSERT_AFTER(prev, valid_entry, next);
4527 else if (next != NULL)
4528 LIST_INSERT_BEFORE(next, valid_entry, next);
4529 else /* It's empty list, insert to head */
4530 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4533 pool->num_free += valid_entry->len;
4534 pool->num_alloc -= valid_entry->len;
4540 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4543 struct pool_entry *entry, *valid_entry;
4545 if (pool == NULL || num == 0) {
4546 PMD_DRV_LOG(ERR, "Invalid parameter");
4550 if (pool->num_free < num) {
4551 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4552 num, pool->num_free);
4557 /* Lookup in free list and find most fit one */
4558 LIST_FOREACH(entry, &pool->free_list, next) {
4559 if (entry->len >= num) {
4561 if (entry->len == num) {
4562 valid_entry = entry;
4565 if (valid_entry == NULL || valid_entry->len > entry->len)
4566 valid_entry = entry;
4570 /* Not find one to satisfy the request, return */
4571 if (valid_entry == NULL) {
4572 PMD_DRV_LOG(ERR, "No valid entry found");
4576 * The entry have equal queue number as requested,
4577 * remove it from alloc_list.
4579 if (valid_entry->len == num) {
4580 LIST_REMOVE(valid_entry, next);
4583 * The entry have more numbers than requested,
4584 * create a new entry for alloc_list and minus its
4585 * queue base and number in free_list.
4587 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4588 if (entry == NULL) {
4590 "Failed to allocate memory for resource pool");
4593 entry->base = valid_entry->base;
4595 valid_entry->base += num;
4596 valid_entry->len -= num;
4597 valid_entry = entry;
4600 /* Insert it into alloc list, not sorted */
4601 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4603 pool->num_free -= valid_entry->len;
4604 pool->num_alloc += valid_entry->len;
4606 return valid_entry->base + pool->base;
4610 * bitmap_is_subset - Check whether src2 is subset of src1
4613 bitmap_is_subset(uint8_t src1, uint8_t src2)
4615 return !((src1 ^ src2) & src2);
4618 static enum i40e_status_code
4619 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4621 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4623 /* If DCB is not supported, only default TC is supported */
4624 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4625 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4626 return I40E_NOT_SUPPORTED;
4629 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4631 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4632 hw->func_caps.enabled_tcmap, enabled_tcmap);
4633 return I40E_NOT_SUPPORTED;
4635 return I40E_SUCCESS;
4639 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4640 struct i40e_vsi_vlan_pvid_info *info)
4643 struct i40e_vsi_context ctxt;
4644 uint8_t vlan_flags = 0;
4647 if (vsi == NULL || info == NULL) {
4648 PMD_DRV_LOG(ERR, "invalid parameters");
4649 return I40E_ERR_PARAM;
4653 vsi->info.pvid = info->config.pvid;
4655 * If insert pvid is enabled, only tagged pkts are
4656 * allowed to be sent out.
4658 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4659 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4662 if (info->config.reject.tagged == 0)
4663 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4665 if (info->config.reject.untagged == 0)
4666 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4668 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4669 I40E_AQ_VSI_PVLAN_MODE_MASK);
4670 vsi->info.port_vlan_flags |= vlan_flags;
4671 vsi->info.valid_sections =
4672 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4673 memset(&ctxt, 0, sizeof(ctxt));
4674 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4675 ctxt.seid = vsi->seid;
4677 hw = I40E_VSI_TO_HW(vsi);
4678 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4679 if (ret != I40E_SUCCESS)
4680 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4686 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4688 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4690 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4692 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4693 if (ret != I40E_SUCCESS)
4697 PMD_DRV_LOG(ERR, "seid not valid");
4701 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4702 tc_bw_data.tc_valid_bits = enabled_tcmap;
4703 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4704 tc_bw_data.tc_bw_credits[i] =
4705 (enabled_tcmap & (1 << i)) ? 1 : 0;
4707 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4708 if (ret != I40E_SUCCESS) {
4709 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4713 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4714 sizeof(vsi->info.qs_handle));
4715 return I40E_SUCCESS;
4718 static enum i40e_status_code
4719 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4720 struct i40e_aqc_vsi_properties_data *info,
4721 uint8_t enabled_tcmap)
4723 enum i40e_status_code ret;
4724 int i, total_tc = 0;
4725 uint16_t qpnum_per_tc, bsf, qp_idx;
4727 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4728 if (ret != I40E_SUCCESS)
4731 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4732 if (enabled_tcmap & (1 << i))
4736 vsi->enabled_tc = enabled_tcmap;
4738 /* Number of queues per enabled TC */
4739 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4740 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4741 bsf = rte_bsf32(qpnum_per_tc);
4743 /* Adjust the queue number to actual queues that can be applied */
4744 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4745 vsi->nb_qps = qpnum_per_tc * total_tc;
4748 * Configure TC and queue mapping parameters, for enabled TC,
4749 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4750 * default queue will serve it.
4753 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4754 if (vsi->enabled_tc & (1 << i)) {
4755 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4756 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4757 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4758 qp_idx += qpnum_per_tc;
4760 info->tc_mapping[i] = 0;
4763 /* Associate queue number with VSI */
4764 if (vsi->type == I40E_VSI_SRIOV) {
4765 info->mapping_flags |=
4766 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4767 for (i = 0; i < vsi->nb_qps; i++)
4768 info->queue_mapping[i] =
4769 rte_cpu_to_le_16(vsi->base_queue + i);
4771 info->mapping_flags |=
4772 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4773 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4775 info->valid_sections |=
4776 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4778 return I40E_SUCCESS;
4782 i40e_veb_release(struct i40e_veb *veb)
4784 struct i40e_vsi *vsi;
4790 if (!TAILQ_EMPTY(&veb->head)) {
4791 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4794 /* associate_vsi field is NULL for floating VEB */
4795 if (veb->associate_vsi != NULL) {
4796 vsi = veb->associate_vsi;
4797 hw = I40E_VSI_TO_HW(vsi);
4799 vsi->uplink_seid = veb->uplink_seid;
4802 veb->associate_pf->main_vsi->floating_veb = NULL;
4803 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4806 i40e_aq_delete_element(hw, veb->seid, NULL);
4808 return I40E_SUCCESS;
4812 static struct i40e_veb *
4813 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4815 struct i40e_veb *veb;
4821 "veb setup failed, associated PF shouldn't null");
4824 hw = I40E_PF_TO_HW(pf);
4826 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4828 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4832 veb->associate_vsi = vsi;
4833 veb->associate_pf = pf;
4834 TAILQ_INIT(&veb->head);
4835 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4837 /* create floating veb if vsi is NULL */
4839 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4840 I40E_DEFAULT_TCMAP, false,
4841 &veb->seid, false, NULL);
4843 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4844 true, &veb->seid, false, NULL);
4847 if (ret != I40E_SUCCESS) {
4848 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4849 hw->aq.asq_last_status);
4852 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4854 /* get statistics index */
4855 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4856 &veb->stats_idx, NULL, NULL, NULL);
4857 if (ret != I40E_SUCCESS) {
4858 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4859 hw->aq.asq_last_status);
4862 /* Get VEB bandwidth, to be implemented */
4863 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4865 vsi->uplink_seid = veb->seid;
4874 i40e_vsi_release(struct i40e_vsi *vsi)
4878 struct i40e_vsi_list *vsi_list;
4881 struct i40e_mac_filter *f;
4882 uint16_t user_param;
4885 return I40E_SUCCESS;
4890 user_param = vsi->user_param;
4892 pf = I40E_VSI_TO_PF(vsi);
4893 hw = I40E_VSI_TO_HW(vsi);
4895 /* VSI has child to attach, release child first */
4897 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4898 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4901 i40e_veb_release(vsi->veb);
4904 if (vsi->floating_veb) {
4905 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4906 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4911 /* Remove all macvlan filters of the VSI */
4912 i40e_vsi_remove_all_macvlan_filter(vsi);
4913 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4916 if (vsi->type != I40E_VSI_MAIN &&
4917 ((vsi->type != I40E_VSI_SRIOV) ||
4918 !pf->floating_veb_list[user_param])) {
4919 /* Remove vsi from parent's sibling list */
4920 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4921 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4922 return I40E_ERR_PARAM;
4924 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4925 &vsi->sib_vsi_list, list);
4927 /* Remove all switch element of the VSI */
4928 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4929 if (ret != I40E_SUCCESS)
4930 PMD_DRV_LOG(ERR, "Failed to delete element");
4933 if ((vsi->type == I40E_VSI_SRIOV) &&
4934 pf->floating_veb_list[user_param]) {
4935 /* Remove vsi from parent's sibling list */
4936 if (vsi->parent_vsi == NULL ||
4937 vsi->parent_vsi->floating_veb == NULL) {
4938 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4939 return I40E_ERR_PARAM;
4941 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4942 &vsi->sib_vsi_list, list);
4944 /* Remove all switch element of the VSI */
4945 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4946 if (ret != I40E_SUCCESS)
4947 PMD_DRV_LOG(ERR, "Failed to delete element");
4950 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4952 if (vsi->type != I40E_VSI_SRIOV)
4953 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4956 return I40E_SUCCESS;
4960 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4962 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4963 struct i40e_aqc_remove_macvlan_element_data def_filter;
4964 struct i40e_mac_filter_info filter;
4967 if (vsi->type != I40E_VSI_MAIN)
4968 return I40E_ERR_CONFIG;
4969 memset(&def_filter, 0, sizeof(def_filter));
4970 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4972 def_filter.vlan_tag = 0;
4973 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4974 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4975 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4976 if (ret != I40E_SUCCESS) {
4977 struct i40e_mac_filter *f;
4978 struct ether_addr *mac;
4981 "Cannot remove the default macvlan filter");
4982 /* It needs to add the permanent mac into mac list */
4983 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4985 PMD_DRV_LOG(ERR, "failed to allocate memory");
4986 return I40E_ERR_NO_MEMORY;
4988 mac = &f->mac_info.mac_addr;
4989 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4991 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4992 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4997 rte_memcpy(&filter.mac_addr,
4998 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4999 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5000 return i40e_vsi_add_mac(vsi, &filter);
5004 * i40e_vsi_get_bw_config - Query VSI BW Information
5005 * @vsi: the VSI to be queried
5007 * Returns 0 on success, negative value on failure
5009 static enum i40e_status_code
5010 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5012 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5013 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5014 struct i40e_hw *hw = &vsi->adapter->hw;
5019 memset(&bw_config, 0, sizeof(bw_config));
5020 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5021 if (ret != I40E_SUCCESS) {
5022 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5023 hw->aq.asq_last_status);
5027 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5028 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5029 &ets_sla_config, NULL);
5030 if (ret != I40E_SUCCESS) {
5032 "VSI failed to get TC bandwdith configuration %u",
5033 hw->aq.asq_last_status);
5037 /* store and print out BW info */
5038 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5039 vsi->bw_info.bw_max = bw_config.max_bw;
5040 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5041 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5042 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5043 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5045 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5046 vsi->bw_info.bw_ets_share_credits[i] =
5047 ets_sla_config.share_credits[i];
5048 vsi->bw_info.bw_ets_credits[i] =
5049 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5050 /* 4 bits per TC, 4th bit is reserved */
5051 vsi->bw_info.bw_ets_max[i] =
5052 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5053 RTE_LEN2MASK(3, uint8_t));
5054 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5055 vsi->bw_info.bw_ets_share_credits[i]);
5056 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5057 vsi->bw_info.bw_ets_credits[i]);
5058 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5059 vsi->bw_info.bw_ets_max[i]);
5062 return I40E_SUCCESS;
5065 /* i40e_enable_pf_lb
5066 * @pf: pointer to the pf structure
5068 * allow loopback on pf
5071 i40e_enable_pf_lb(struct i40e_pf *pf)
5073 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5074 struct i40e_vsi_context ctxt;
5077 /* Use the FW API if FW >= v5.0 */
5078 if (hw->aq.fw_maj_ver < 5) {
5079 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5083 memset(&ctxt, 0, sizeof(ctxt));
5084 ctxt.seid = pf->main_vsi_seid;
5085 ctxt.pf_num = hw->pf_id;
5086 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5088 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5089 ret, hw->aq.asq_last_status);
5092 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5093 ctxt.info.valid_sections =
5094 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5095 ctxt.info.switch_id |=
5096 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5098 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5100 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5101 hw->aq.asq_last_status);
5106 i40e_vsi_setup(struct i40e_pf *pf,
5107 enum i40e_vsi_type type,
5108 struct i40e_vsi *uplink_vsi,
5109 uint16_t user_param)
5111 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5112 struct i40e_vsi *vsi;
5113 struct i40e_mac_filter_info filter;
5115 struct i40e_vsi_context ctxt;
5116 struct ether_addr broadcast =
5117 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5119 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5120 uplink_vsi == NULL) {
5122 "VSI setup failed, VSI link shouldn't be NULL");
5126 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5128 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5133 * 1.type is not MAIN and uplink vsi is not NULL
5134 * If uplink vsi didn't setup VEB, create one first under veb field
5135 * 2.type is SRIOV and the uplink is NULL
5136 * If floating VEB is NULL, create one veb under floating veb field
5139 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5140 uplink_vsi->veb == NULL) {
5141 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5143 if (uplink_vsi->veb == NULL) {
5144 PMD_DRV_LOG(ERR, "VEB setup failed");
5147 /* set ALLOWLOOPBACk on pf, when veb is created */
5148 i40e_enable_pf_lb(pf);
5151 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5152 pf->main_vsi->floating_veb == NULL) {
5153 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5155 if (pf->main_vsi->floating_veb == NULL) {
5156 PMD_DRV_LOG(ERR, "VEB setup failed");
5161 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5163 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5166 TAILQ_INIT(&vsi->mac_list);
5168 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5169 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5170 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5171 vsi->user_param = user_param;
5172 vsi->vlan_anti_spoof_on = 0;
5173 vsi->vlan_filter_on = 0;
5174 /* Allocate queues */
5175 switch (vsi->type) {
5176 case I40E_VSI_MAIN :
5177 vsi->nb_qps = pf->lan_nb_qps;
5179 case I40E_VSI_SRIOV :
5180 vsi->nb_qps = pf->vf_nb_qps;
5182 case I40E_VSI_VMDQ2:
5183 vsi->nb_qps = pf->vmdq_nb_qps;
5186 vsi->nb_qps = pf->fdir_nb_qps;
5192 * The filter status descriptor is reported in rx queue 0,
5193 * while the tx queue for fdir filter programming has no
5194 * such constraints, can be non-zero queues.
5195 * To simplify it, choose FDIR vsi use queue 0 pair.
5196 * To make sure it will use queue 0 pair, queue allocation
5197 * need be done before this function is called
5199 if (type != I40E_VSI_FDIR) {
5200 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5202 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5206 vsi->base_queue = ret;
5208 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5210 /* VF has MSIX interrupt in VF range, don't allocate here */
5211 if (type == I40E_VSI_MAIN) {
5212 if (pf->support_multi_driver) {
5213 /* If support multi-driver, need to use INT0 instead of
5214 * allocating from msix pool. The Msix pool is init from
5215 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5216 * to 1 without calling i40e_res_pool_alloc.
5221 ret = i40e_res_pool_alloc(&pf->msix_pool,
5222 RTE_MIN(vsi->nb_qps,
5223 RTE_MAX_RXTX_INTR_VEC_ID));
5226 "VSI MAIN %d get heap failed %d",
5228 goto fail_queue_alloc;
5230 vsi->msix_intr = ret;
5231 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5232 RTE_MAX_RXTX_INTR_VEC_ID);
5234 } else if (type != I40E_VSI_SRIOV) {
5235 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5237 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5238 goto fail_queue_alloc;
5240 vsi->msix_intr = ret;
5248 if (type == I40E_VSI_MAIN) {
5249 /* For main VSI, no need to add since it's default one */
5250 vsi->uplink_seid = pf->mac_seid;
5251 vsi->seid = pf->main_vsi_seid;
5252 /* Bind queues with specific MSIX interrupt */
5254 * Needs 2 interrupt at least, one for misc cause which will
5255 * enabled from OS side, Another for queues binding the
5256 * interrupt from device side only.
5259 /* Get default VSI parameters from hardware */
5260 memset(&ctxt, 0, sizeof(ctxt));
5261 ctxt.seid = vsi->seid;
5262 ctxt.pf_num = hw->pf_id;
5263 ctxt.uplink_seid = vsi->uplink_seid;
5265 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5266 if (ret != I40E_SUCCESS) {
5267 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5268 goto fail_msix_alloc;
5270 rte_memcpy(&vsi->info, &ctxt.info,
5271 sizeof(struct i40e_aqc_vsi_properties_data));
5272 vsi->vsi_id = ctxt.vsi_number;
5273 vsi->info.valid_sections = 0;
5275 /* Configure tc, enabled TC0 only */
5276 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5278 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5279 goto fail_msix_alloc;
5282 /* TC, queue mapping */
5283 memset(&ctxt, 0, sizeof(ctxt));
5284 vsi->info.valid_sections |=
5285 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5286 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5287 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5288 rte_memcpy(&ctxt.info, &vsi->info,
5289 sizeof(struct i40e_aqc_vsi_properties_data));
5290 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5291 I40E_DEFAULT_TCMAP);
5292 if (ret != I40E_SUCCESS) {
5294 "Failed to configure TC queue mapping");
5295 goto fail_msix_alloc;
5297 ctxt.seid = vsi->seid;
5298 ctxt.pf_num = hw->pf_id;
5299 ctxt.uplink_seid = vsi->uplink_seid;
5302 /* Update VSI parameters */
5303 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5304 if (ret != I40E_SUCCESS) {
5305 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5306 goto fail_msix_alloc;
5309 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5310 sizeof(vsi->info.tc_mapping));
5311 rte_memcpy(&vsi->info.queue_mapping,
5312 &ctxt.info.queue_mapping,
5313 sizeof(vsi->info.queue_mapping));
5314 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5315 vsi->info.valid_sections = 0;
5317 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5321 * Updating default filter settings are necessary to prevent
5322 * reception of tagged packets.
5323 * Some old firmware configurations load a default macvlan
5324 * filter which accepts both tagged and untagged packets.
5325 * The updating is to use a normal filter instead if needed.
5326 * For NVM 4.2.2 or after, the updating is not needed anymore.
5327 * The firmware with correct configurations load the default
5328 * macvlan filter which is expected and cannot be removed.
5330 i40e_update_default_filter_setting(vsi);
5331 i40e_config_qinq(hw, vsi);
5332 } else if (type == I40E_VSI_SRIOV) {
5333 memset(&ctxt, 0, sizeof(ctxt));
5335 * For other VSI, the uplink_seid equals to uplink VSI's
5336 * uplink_seid since they share same VEB
5338 if (uplink_vsi == NULL)
5339 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5341 vsi->uplink_seid = uplink_vsi->uplink_seid;
5342 ctxt.pf_num = hw->pf_id;
5343 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5344 ctxt.uplink_seid = vsi->uplink_seid;
5345 ctxt.connection_type = 0x1;
5346 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5348 /* Use the VEB configuration if FW >= v5.0 */
5349 if (hw->aq.fw_maj_ver >= 5) {
5350 /* Configure switch ID */
5351 ctxt.info.valid_sections |=
5352 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5353 ctxt.info.switch_id =
5354 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5357 /* Configure port/vlan */
5358 ctxt.info.valid_sections |=
5359 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5360 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5361 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5362 hw->func_caps.enabled_tcmap);
5363 if (ret != I40E_SUCCESS) {
5365 "Failed to configure TC queue mapping");
5366 goto fail_msix_alloc;
5369 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5370 ctxt.info.valid_sections |=
5371 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5373 * Since VSI is not created yet, only configure parameter,
5374 * will add vsi below.
5377 i40e_config_qinq(hw, vsi);
5378 } else if (type == I40E_VSI_VMDQ2) {
5379 memset(&ctxt, 0, sizeof(ctxt));
5381 * For other VSI, the uplink_seid equals to uplink VSI's
5382 * uplink_seid since they share same VEB
5384 vsi->uplink_seid = uplink_vsi->uplink_seid;
5385 ctxt.pf_num = hw->pf_id;
5387 ctxt.uplink_seid = vsi->uplink_seid;
5388 ctxt.connection_type = 0x1;
5389 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5391 ctxt.info.valid_sections |=
5392 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5393 /* user_param carries flag to enable loop back */
5395 ctxt.info.switch_id =
5396 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5397 ctxt.info.switch_id |=
5398 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5401 /* Configure port/vlan */
5402 ctxt.info.valid_sections |=
5403 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5404 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5405 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5406 I40E_DEFAULT_TCMAP);
5407 if (ret != I40E_SUCCESS) {
5409 "Failed to configure TC queue mapping");
5410 goto fail_msix_alloc;
5412 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5413 ctxt.info.valid_sections |=
5414 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5415 } else if (type == I40E_VSI_FDIR) {
5416 memset(&ctxt, 0, sizeof(ctxt));
5417 vsi->uplink_seid = uplink_vsi->uplink_seid;
5418 ctxt.pf_num = hw->pf_id;
5420 ctxt.uplink_seid = vsi->uplink_seid;
5421 ctxt.connection_type = 0x1; /* regular data port */
5422 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5423 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5424 I40E_DEFAULT_TCMAP);
5425 if (ret != I40E_SUCCESS) {
5427 "Failed to configure TC queue mapping.");
5428 goto fail_msix_alloc;
5430 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5431 ctxt.info.valid_sections |=
5432 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5434 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5435 goto fail_msix_alloc;
5438 if (vsi->type != I40E_VSI_MAIN) {
5439 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5440 if (ret != I40E_SUCCESS) {
5441 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5442 hw->aq.asq_last_status);
5443 goto fail_msix_alloc;
5445 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5446 vsi->info.valid_sections = 0;
5447 vsi->seid = ctxt.seid;
5448 vsi->vsi_id = ctxt.vsi_number;
5449 vsi->sib_vsi_list.vsi = vsi;
5450 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5451 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5452 &vsi->sib_vsi_list, list);
5454 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5455 &vsi->sib_vsi_list, list);
5459 /* MAC/VLAN configuration */
5460 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5461 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5463 ret = i40e_vsi_add_mac(vsi, &filter);
5464 if (ret != I40E_SUCCESS) {
5465 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5466 goto fail_msix_alloc;
5469 /* Get VSI BW information */
5470 i40e_vsi_get_bw_config(vsi);
5473 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5475 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5481 /* Configure vlan filter on or off */
5483 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5486 struct i40e_mac_filter *f;
5488 struct i40e_mac_filter_info *mac_filter;
5489 enum rte_mac_filter_type desired_filter;
5490 int ret = I40E_SUCCESS;
5493 /* Filter to match MAC and VLAN */
5494 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5496 /* Filter to match only MAC */
5497 desired_filter = RTE_MAC_PERFECT_MATCH;
5502 mac_filter = rte_zmalloc("mac_filter_info_data",
5503 num * sizeof(*mac_filter), 0);
5504 if (mac_filter == NULL) {
5505 PMD_DRV_LOG(ERR, "failed to allocate memory");
5506 return I40E_ERR_NO_MEMORY;
5511 /* Remove all existing mac */
5512 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5513 mac_filter[i] = f->mac_info;
5514 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5516 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5517 on ? "enable" : "disable");
5523 /* Override with new filter */
5524 for (i = 0; i < num; i++) {
5525 mac_filter[i].filter_type = desired_filter;
5526 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5528 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5529 on ? "enable" : "disable");
5535 rte_free(mac_filter);
5539 /* Configure vlan stripping on or off */
5541 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5543 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5544 struct i40e_vsi_context ctxt;
5546 int ret = I40E_SUCCESS;
5548 /* Check if it has been already on or off */
5549 if (vsi->info.valid_sections &
5550 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5552 if ((vsi->info.port_vlan_flags &
5553 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5554 return 0; /* already on */
5556 if ((vsi->info.port_vlan_flags &
5557 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5558 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5559 return 0; /* already off */
5564 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5566 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5567 vsi->info.valid_sections =
5568 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5569 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5570 vsi->info.port_vlan_flags |= vlan_flags;
5571 ctxt.seid = vsi->seid;
5572 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5573 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5575 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5576 on ? "enable" : "disable");
5582 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5584 struct rte_eth_dev_data *data = dev->data;
5588 /* Apply vlan offload setting */
5589 mask = ETH_VLAN_STRIP_MASK |
5590 ETH_VLAN_FILTER_MASK |
5591 ETH_VLAN_EXTEND_MASK;
5592 ret = i40e_vlan_offload_set(dev, mask);
5594 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5598 /* Apply pvid setting */
5599 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5600 data->dev_conf.txmode.hw_vlan_insert_pvid);
5602 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5608 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5610 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5612 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5616 i40e_update_flow_control(struct i40e_hw *hw)
5618 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5619 struct i40e_link_status link_status;
5620 uint32_t rxfc = 0, txfc = 0, reg;
5624 memset(&link_status, 0, sizeof(link_status));
5625 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5626 if (ret != I40E_SUCCESS) {
5627 PMD_DRV_LOG(ERR, "Failed to get link status information");
5628 goto write_reg; /* Disable flow control */
5631 an_info = hw->phy.link_info.an_info;
5632 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5633 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5634 ret = I40E_ERR_NOT_READY;
5635 goto write_reg; /* Disable flow control */
5638 * If link auto negotiation is enabled, flow control needs to
5639 * be configured according to it
5641 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5642 case I40E_LINK_PAUSE_RXTX:
5645 hw->fc.current_mode = I40E_FC_FULL;
5647 case I40E_AQ_LINK_PAUSE_RX:
5649 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5651 case I40E_AQ_LINK_PAUSE_TX:
5653 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5656 hw->fc.current_mode = I40E_FC_NONE;
5661 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5662 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5663 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5664 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5665 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5666 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5673 i40e_pf_setup(struct i40e_pf *pf)
5675 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5676 struct i40e_filter_control_settings settings;
5677 struct i40e_vsi *vsi;
5680 /* Clear all stats counters */
5681 pf->offset_loaded = FALSE;
5682 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5683 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5684 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5685 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5687 ret = i40e_pf_get_switch_config(pf);
5688 if (ret != I40E_SUCCESS) {
5689 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5692 if (pf->flags & I40E_FLAG_FDIR) {
5693 /* make queue allocated first, let FDIR use queue pair 0*/
5694 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5695 if (ret != I40E_FDIR_QUEUE_ID) {
5697 "queue allocation fails for FDIR: ret =%d",
5699 pf->flags &= ~I40E_FLAG_FDIR;
5702 /* main VSI setup */
5703 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5705 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5706 return I40E_ERR_NOT_READY;
5710 /* Configure filter control */
5711 memset(&settings, 0, sizeof(settings));
5712 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5713 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5714 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5715 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5717 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5718 hw->func_caps.rss_table_size);
5719 return I40E_ERR_PARAM;
5721 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5722 hw->func_caps.rss_table_size);
5723 pf->hash_lut_size = hw->func_caps.rss_table_size;
5725 /* Enable ethtype and macvlan filters */
5726 settings.enable_ethtype = TRUE;
5727 settings.enable_macvlan = TRUE;
5728 ret = i40e_set_filter_control(hw, &settings);
5730 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5733 /* Update flow control according to the auto negotiation */
5734 i40e_update_flow_control(hw);
5736 return I40E_SUCCESS;
5740 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5746 * Set or clear TX Queue Disable flags,
5747 * which is required by hardware.
5749 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5750 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5752 /* Wait until the request is finished */
5753 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5754 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5755 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5756 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5757 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5763 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5764 return I40E_SUCCESS; /* already on, skip next steps */
5766 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5767 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5769 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5770 return I40E_SUCCESS; /* already off, skip next steps */
5771 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5773 /* Write the register */
5774 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5775 /* Check the result */
5776 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5777 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5778 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5780 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5781 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5784 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5785 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5789 /* Check if it is timeout */
5790 if (j >= I40E_CHK_Q_ENA_COUNT) {
5791 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5792 (on ? "enable" : "disable"), q_idx);
5793 return I40E_ERR_TIMEOUT;
5796 return I40E_SUCCESS;
5799 /* Swith on or off the tx queues */
5801 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5803 struct rte_eth_dev_data *dev_data = pf->dev_data;
5804 struct i40e_tx_queue *txq;
5805 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5809 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5810 txq = dev_data->tx_queues[i];
5811 /* Don't operate the queue if not configured or
5812 * if starting only per queue */
5813 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5816 ret = i40e_dev_tx_queue_start(dev, i);
5818 ret = i40e_dev_tx_queue_stop(dev, i);
5819 if ( ret != I40E_SUCCESS)
5823 return I40E_SUCCESS;
5827 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5832 /* Wait until the request is finished */
5833 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5834 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5835 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5836 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5837 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5842 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5843 return I40E_SUCCESS; /* Already on, skip next steps */
5844 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5846 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5847 return I40E_SUCCESS; /* Already off, skip next steps */
5848 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5851 /* Write the register */
5852 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5853 /* Check the result */
5854 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5855 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5856 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5858 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5859 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5862 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5863 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5868 /* Check if it is timeout */
5869 if (j >= I40E_CHK_Q_ENA_COUNT) {
5870 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5871 (on ? "enable" : "disable"), q_idx);
5872 return I40E_ERR_TIMEOUT;
5875 return I40E_SUCCESS;
5877 /* Switch on or off the rx queues */
5879 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5881 struct rte_eth_dev_data *dev_data = pf->dev_data;
5882 struct i40e_rx_queue *rxq;
5883 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5887 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5888 rxq = dev_data->rx_queues[i];
5889 /* Don't operate the queue if not configured or
5890 * if starting only per queue */
5891 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5894 ret = i40e_dev_rx_queue_start(dev, i);
5896 ret = i40e_dev_rx_queue_stop(dev, i);
5897 if (ret != I40E_SUCCESS)
5901 return I40E_SUCCESS;
5904 /* Switch on or off all the rx/tx queues */
5906 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5911 /* enable rx queues before enabling tx queues */
5912 ret = i40e_dev_switch_rx_queues(pf, on);
5914 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5917 ret = i40e_dev_switch_tx_queues(pf, on);
5919 /* Stop tx queues before stopping rx queues */
5920 ret = i40e_dev_switch_tx_queues(pf, on);
5922 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5925 ret = i40e_dev_switch_rx_queues(pf, on);
5931 /* Initialize VSI for TX */
5933 i40e_dev_tx_init(struct i40e_pf *pf)
5935 struct rte_eth_dev_data *data = pf->dev_data;
5937 uint32_t ret = I40E_SUCCESS;
5938 struct i40e_tx_queue *txq;
5940 for (i = 0; i < data->nb_tx_queues; i++) {
5941 txq = data->tx_queues[i];
5942 if (!txq || !txq->q_set)
5944 ret = i40e_tx_queue_init(txq);
5945 if (ret != I40E_SUCCESS)
5948 if (ret == I40E_SUCCESS)
5949 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5955 /* Initialize VSI for RX */
5957 i40e_dev_rx_init(struct i40e_pf *pf)
5959 struct rte_eth_dev_data *data = pf->dev_data;
5960 int ret = I40E_SUCCESS;
5962 struct i40e_rx_queue *rxq;
5964 i40e_pf_config_mq_rx(pf);
5965 for (i = 0; i < data->nb_rx_queues; i++) {
5966 rxq = data->rx_queues[i];
5967 if (!rxq || !rxq->q_set)
5970 ret = i40e_rx_queue_init(rxq);
5971 if (ret != I40E_SUCCESS) {
5973 "Failed to do RX queue initialization");
5977 if (ret == I40E_SUCCESS)
5978 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5985 i40e_dev_rxtx_init(struct i40e_pf *pf)
5989 err = i40e_dev_tx_init(pf);
5991 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5994 err = i40e_dev_rx_init(pf);
5996 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6004 i40e_vmdq_setup(struct rte_eth_dev *dev)
6006 struct rte_eth_conf *conf = &dev->data->dev_conf;
6007 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6008 int i, err, conf_vsis, j, loop;
6009 struct i40e_vsi *vsi;
6010 struct i40e_vmdq_info *vmdq_info;
6011 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6012 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6015 * Disable interrupt to avoid message from VF. Furthermore, it will
6016 * avoid race condition in VSI creation/destroy.
6018 i40e_pf_disable_irq0(hw);
6020 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6021 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6025 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6026 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6027 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6028 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6029 pf->max_nb_vmdq_vsi);
6033 if (pf->vmdq != NULL) {
6034 PMD_INIT_LOG(INFO, "VMDQ already configured");
6038 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6039 sizeof(*vmdq_info) * conf_vsis, 0);
6041 if (pf->vmdq == NULL) {
6042 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6046 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6048 /* Create VMDQ VSI */
6049 for (i = 0; i < conf_vsis; i++) {
6050 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6051 vmdq_conf->enable_loop_back);
6053 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6057 vmdq_info = &pf->vmdq[i];
6059 vmdq_info->vsi = vsi;
6061 pf->nb_cfg_vmdq_vsi = conf_vsis;
6063 /* Configure Vlan */
6064 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6065 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6066 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6067 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6068 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6069 vmdq_conf->pool_map[i].vlan_id, j);
6071 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6072 vmdq_conf->pool_map[i].vlan_id);
6074 PMD_INIT_LOG(ERR, "Failed to add vlan");
6082 i40e_pf_enable_irq0(hw);
6087 for (i = 0; i < conf_vsis; i++)
6088 if (pf->vmdq[i].vsi == NULL)
6091 i40e_vsi_release(pf->vmdq[i].vsi);
6095 i40e_pf_enable_irq0(hw);
6100 i40e_stat_update_32(struct i40e_hw *hw,
6108 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6112 if (new_data >= *offset)
6113 *stat = (uint64_t)(new_data - *offset);
6115 *stat = (uint64_t)((new_data +
6116 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6120 i40e_stat_update_48(struct i40e_hw *hw,
6129 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6130 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6131 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6136 if (new_data >= *offset)
6137 *stat = new_data - *offset;
6139 *stat = (uint64_t)((new_data +
6140 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6142 *stat &= I40E_48_BIT_MASK;
6147 i40e_pf_disable_irq0(struct i40e_hw *hw)
6149 /* Disable all interrupt types */
6150 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6151 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6152 I40E_WRITE_FLUSH(hw);
6157 i40e_pf_enable_irq0(struct i40e_hw *hw)
6159 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6160 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6161 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6162 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6163 I40E_WRITE_FLUSH(hw);
6167 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6169 /* read pending request and disable first */
6170 i40e_pf_disable_irq0(hw);
6171 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6172 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6173 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6176 /* Link no queues with irq0 */
6177 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6178 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6182 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6184 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6185 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6188 uint32_t index, offset, val;
6193 * Try to find which VF trigger a reset, use absolute VF id to access
6194 * since the reg is global register.
6196 for (i = 0; i < pf->vf_num; i++) {
6197 abs_vf_id = hw->func_caps.vf_base_id + i;
6198 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6199 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6200 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6201 /* VFR event occurred */
6202 if (val & (0x1 << offset)) {
6205 /* Clear the event first */
6206 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6208 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6210 * Only notify a VF reset event occurred,
6211 * don't trigger another SW reset
6213 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6214 if (ret != I40E_SUCCESS)
6215 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6221 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6223 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6226 for (i = 0; i < pf->vf_num; i++)
6227 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6231 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6233 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6234 struct i40e_arq_event_info info;
6235 uint16_t pending, opcode;
6238 info.buf_len = I40E_AQ_BUF_SZ;
6239 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6240 if (!info.msg_buf) {
6241 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6247 ret = i40e_clean_arq_element(hw, &info, &pending);
6249 if (ret != I40E_SUCCESS) {
6251 "Failed to read msg from AdminQ, aq_err: %u",
6252 hw->aq.asq_last_status);
6255 opcode = rte_le_to_cpu_16(info.desc.opcode);
6258 case i40e_aqc_opc_send_msg_to_pf:
6259 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6260 i40e_pf_host_handle_vf_msg(dev,
6261 rte_le_to_cpu_16(info.desc.retval),
6262 rte_le_to_cpu_32(info.desc.cookie_high),
6263 rte_le_to_cpu_32(info.desc.cookie_low),
6267 case i40e_aqc_opc_get_link_status:
6268 ret = i40e_dev_link_update(dev, 0);
6270 _rte_eth_dev_callback_process(dev,
6271 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
6274 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6279 rte_free(info.msg_buf);
6283 * Interrupt handler triggered by NIC for handling
6284 * specific interrupt.
6287 * Pointer to interrupt handle.
6289 * The address of parameter (struct rte_eth_dev *) regsitered before.
6295 i40e_dev_interrupt_handler(void *param)
6297 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6298 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6301 /* Disable interrupt */
6302 i40e_pf_disable_irq0(hw);
6304 /* read out interrupt causes */
6305 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6307 /* No interrupt event indicated */
6308 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6309 PMD_DRV_LOG(INFO, "No interrupt event");
6312 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6313 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6314 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6315 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6316 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6317 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6318 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6319 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6320 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6321 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6322 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6323 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6324 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6325 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6327 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6328 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6329 i40e_dev_handle_vfr_event(dev);
6331 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6332 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6333 i40e_dev_handle_aq_msg(dev);
6337 /* Enable interrupt */
6338 i40e_pf_enable_irq0(hw);
6339 rte_intr_enable(dev->intr_handle);
6343 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6344 struct i40e_macvlan_filter *filter,
6347 int ele_num, ele_buff_size;
6348 int num, actual_num, i;
6350 int ret = I40E_SUCCESS;
6351 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6352 struct i40e_aqc_add_macvlan_element_data *req_list;
6354 if (filter == NULL || total == 0)
6355 return I40E_ERR_PARAM;
6356 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6357 ele_buff_size = hw->aq.asq_buf_size;
6359 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6360 if (req_list == NULL) {
6361 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6362 return I40E_ERR_NO_MEMORY;
6367 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6368 memset(req_list, 0, ele_buff_size);
6370 for (i = 0; i < actual_num; i++) {
6371 rte_memcpy(req_list[i].mac_addr,
6372 &filter[num + i].macaddr, ETH_ADDR_LEN);
6373 req_list[i].vlan_tag =
6374 rte_cpu_to_le_16(filter[num + i].vlan_id);
6376 switch (filter[num + i].filter_type) {
6377 case RTE_MAC_PERFECT_MATCH:
6378 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6379 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6381 case RTE_MACVLAN_PERFECT_MATCH:
6382 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6384 case RTE_MAC_HASH_MATCH:
6385 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6386 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6388 case RTE_MACVLAN_HASH_MATCH:
6389 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6392 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6393 ret = I40E_ERR_PARAM;
6397 req_list[i].queue_number = 0;
6399 req_list[i].flags = rte_cpu_to_le_16(flags);
6402 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6404 if (ret != I40E_SUCCESS) {
6405 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6409 } while (num < total);
6417 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6418 struct i40e_macvlan_filter *filter,
6421 int ele_num, ele_buff_size;
6422 int num, actual_num, i;
6424 int ret = I40E_SUCCESS;
6425 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6426 struct i40e_aqc_remove_macvlan_element_data *req_list;
6428 if (filter == NULL || total == 0)
6429 return I40E_ERR_PARAM;
6431 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6432 ele_buff_size = hw->aq.asq_buf_size;
6434 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6435 if (req_list == NULL) {
6436 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6437 return I40E_ERR_NO_MEMORY;
6442 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6443 memset(req_list, 0, ele_buff_size);
6445 for (i = 0; i < actual_num; i++) {
6446 rte_memcpy(req_list[i].mac_addr,
6447 &filter[num + i].macaddr, ETH_ADDR_LEN);
6448 req_list[i].vlan_tag =
6449 rte_cpu_to_le_16(filter[num + i].vlan_id);
6451 switch (filter[num + i].filter_type) {
6452 case RTE_MAC_PERFECT_MATCH:
6453 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6454 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6456 case RTE_MACVLAN_PERFECT_MATCH:
6457 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6459 case RTE_MAC_HASH_MATCH:
6460 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6461 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6463 case RTE_MACVLAN_HASH_MATCH:
6464 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6467 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6468 ret = I40E_ERR_PARAM;
6471 req_list[i].flags = rte_cpu_to_le_16(flags);
6474 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6476 if (ret != I40E_SUCCESS) {
6477 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6481 } while (num < total);
6488 /* Find out specific MAC filter */
6489 static struct i40e_mac_filter *
6490 i40e_find_mac_filter(struct i40e_vsi *vsi,
6491 struct ether_addr *macaddr)
6493 struct i40e_mac_filter *f;
6495 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6496 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6504 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6507 uint32_t vid_idx, vid_bit;
6509 if (vlan_id > ETH_VLAN_ID_MAX)
6512 vid_idx = I40E_VFTA_IDX(vlan_id);
6513 vid_bit = I40E_VFTA_BIT(vlan_id);
6515 if (vsi->vfta[vid_idx] & vid_bit)
6522 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6523 uint16_t vlan_id, bool on)
6525 uint32_t vid_idx, vid_bit;
6527 vid_idx = I40E_VFTA_IDX(vlan_id);
6528 vid_bit = I40E_VFTA_BIT(vlan_id);
6531 vsi->vfta[vid_idx] |= vid_bit;
6533 vsi->vfta[vid_idx] &= ~vid_bit;
6537 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6538 uint16_t vlan_id, bool on)
6540 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6541 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6544 if (vlan_id > ETH_VLAN_ID_MAX)
6547 i40e_store_vlan_filter(vsi, vlan_id, on);
6549 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6552 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6555 ret = i40e_aq_add_vlan(hw, vsi->seid,
6556 &vlan_data, 1, NULL);
6557 if (ret != I40E_SUCCESS)
6558 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6560 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6561 &vlan_data, 1, NULL);
6562 if (ret != I40E_SUCCESS)
6564 "Failed to remove vlan filter");
6569 * Find all vlan options for specific mac addr,
6570 * return with actual vlan found.
6573 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6574 struct i40e_macvlan_filter *mv_f,
6575 int num, struct ether_addr *addr)
6581 * Not to use i40e_find_vlan_filter to decrease the loop time,
6582 * although the code looks complex.
6584 if (num < vsi->vlan_num)
6585 return I40E_ERR_PARAM;
6588 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6590 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6591 if (vsi->vfta[j] & (1 << k)) {
6594 "vlan number doesn't match");
6595 return I40E_ERR_PARAM;
6597 rte_memcpy(&mv_f[i].macaddr,
6598 addr, ETH_ADDR_LEN);
6600 j * I40E_UINT32_BIT_SIZE + k;
6606 return I40E_SUCCESS;
6610 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6611 struct i40e_macvlan_filter *mv_f,
6616 struct i40e_mac_filter *f;
6618 if (num < vsi->mac_num)
6619 return I40E_ERR_PARAM;
6621 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6623 PMD_DRV_LOG(ERR, "buffer number not match");
6624 return I40E_ERR_PARAM;
6626 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6628 mv_f[i].vlan_id = vlan;
6629 mv_f[i].filter_type = f->mac_info.filter_type;
6633 return I40E_SUCCESS;
6637 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6640 struct i40e_mac_filter *f;
6641 struct i40e_macvlan_filter *mv_f;
6642 int ret = I40E_SUCCESS;
6644 if (vsi == NULL || vsi->mac_num == 0)
6645 return I40E_ERR_PARAM;
6647 /* Case that no vlan is set */
6648 if (vsi->vlan_num == 0)
6651 num = vsi->mac_num * vsi->vlan_num;
6653 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6655 PMD_DRV_LOG(ERR, "failed to allocate memory");
6656 return I40E_ERR_NO_MEMORY;
6660 if (vsi->vlan_num == 0) {
6661 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6662 rte_memcpy(&mv_f[i].macaddr,
6663 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6664 mv_f[i].filter_type = f->mac_info.filter_type;
6665 mv_f[i].vlan_id = 0;
6669 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6670 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6671 vsi->vlan_num, &f->mac_info.mac_addr);
6672 if (ret != I40E_SUCCESS)
6674 for (j = i; j < i + vsi->vlan_num; j++)
6675 mv_f[j].filter_type = f->mac_info.filter_type;
6680 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6688 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6690 struct i40e_macvlan_filter *mv_f;
6692 int ret = I40E_SUCCESS;
6694 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6695 return I40E_ERR_PARAM;
6697 /* If it's already set, just return */
6698 if (i40e_find_vlan_filter(vsi,vlan))
6699 return I40E_SUCCESS;
6701 mac_num = vsi->mac_num;
6704 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6705 return I40E_ERR_PARAM;
6708 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6711 PMD_DRV_LOG(ERR, "failed to allocate memory");
6712 return I40E_ERR_NO_MEMORY;
6715 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6717 if (ret != I40E_SUCCESS)
6720 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6722 if (ret != I40E_SUCCESS)
6725 i40e_set_vlan_filter(vsi, vlan, 1);
6735 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6737 struct i40e_macvlan_filter *mv_f;
6739 int ret = I40E_SUCCESS;
6742 * Vlan 0 is the generic filter for untagged packets
6743 * and can't be removed.
6745 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6746 return I40E_ERR_PARAM;
6748 /* If can't find it, just return */
6749 if (!i40e_find_vlan_filter(vsi, vlan))
6750 return I40E_ERR_PARAM;
6752 mac_num = vsi->mac_num;
6755 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6756 return I40E_ERR_PARAM;
6759 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6762 PMD_DRV_LOG(ERR, "failed to allocate memory");
6763 return I40E_ERR_NO_MEMORY;
6766 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6768 if (ret != I40E_SUCCESS)
6771 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6773 if (ret != I40E_SUCCESS)
6776 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6777 if (vsi->vlan_num == 1) {
6778 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6779 if (ret != I40E_SUCCESS)
6782 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6783 if (ret != I40E_SUCCESS)
6787 i40e_set_vlan_filter(vsi, vlan, 0);
6797 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6799 struct i40e_mac_filter *f;
6800 struct i40e_macvlan_filter *mv_f;
6801 int i, vlan_num = 0;
6802 int ret = I40E_SUCCESS;
6804 /* If it's add and we've config it, return */
6805 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6807 return I40E_SUCCESS;
6808 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6809 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6812 * If vlan_num is 0, that's the first time to add mac,
6813 * set mask for vlan_id 0.
6815 if (vsi->vlan_num == 0) {
6816 i40e_set_vlan_filter(vsi, 0, 1);
6819 vlan_num = vsi->vlan_num;
6820 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6821 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6824 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6826 PMD_DRV_LOG(ERR, "failed to allocate memory");
6827 return I40E_ERR_NO_MEMORY;
6830 for (i = 0; i < vlan_num; i++) {
6831 mv_f[i].filter_type = mac_filter->filter_type;
6832 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6836 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6837 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6838 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6839 &mac_filter->mac_addr);
6840 if (ret != I40E_SUCCESS)
6844 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6845 if (ret != I40E_SUCCESS)
6848 /* Add the mac addr into mac list */
6849 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6851 PMD_DRV_LOG(ERR, "failed to allocate memory");
6852 ret = I40E_ERR_NO_MEMORY;
6855 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6857 f->mac_info.filter_type = mac_filter->filter_type;
6858 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6869 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6871 struct i40e_mac_filter *f;
6872 struct i40e_macvlan_filter *mv_f;
6874 enum rte_mac_filter_type filter_type;
6875 int ret = I40E_SUCCESS;
6877 /* Can't find it, return an error */
6878 f = i40e_find_mac_filter(vsi, addr);
6880 return I40E_ERR_PARAM;
6882 vlan_num = vsi->vlan_num;
6883 filter_type = f->mac_info.filter_type;
6884 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6885 filter_type == RTE_MACVLAN_HASH_MATCH) {
6886 if (vlan_num == 0) {
6887 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6888 return I40E_ERR_PARAM;
6890 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6891 filter_type == RTE_MAC_HASH_MATCH)
6894 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6896 PMD_DRV_LOG(ERR, "failed to allocate memory");
6897 return I40E_ERR_NO_MEMORY;
6900 for (i = 0; i < vlan_num; i++) {
6901 mv_f[i].filter_type = filter_type;
6902 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6905 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6906 filter_type == RTE_MACVLAN_HASH_MATCH) {
6907 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6908 if (ret != I40E_SUCCESS)
6912 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6913 if (ret != I40E_SUCCESS)
6916 /* Remove the mac addr into mac list */
6917 TAILQ_REMOVE(&vsi->mac_list, f, next);
6927 /* Configure hash enable flags for RSS */
6929 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6937 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6938 if (flags & (1ULL << i))
6939 hena |= adapter->pctypes_tbl[i];
6945 /* Parse the hash enable flags */
6947 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6949 uint64_t rss_hf = 0;
6955 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6956 if (flags & adapter->pctypes_tbl[i])
6957 rss_hf |= (1ULL << i);
6964 i40e_pf_disable_rss(struct i40e_pf *pf)
6966 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6968 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6969 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6970 I40E_WRITE_FLUSH(hw);
6974 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6976 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6977 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6980 if (!key || key_len == 0) {
6981 PMD_DRV_LOG(DEBUG, "No key to be configured");
6983 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6985 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6989 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6990 struct i40e_aqc_get_set_rss_key_data *key_dw =
6991 (struct i40e_aqc_get_set_rss_key_data *)key;
6993 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6995 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6997 uint32_t *hash_key = (uint32_t *)key;
7000 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7001 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
7002 I40E_WRITE_FLUSH(hw);
7009 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7011 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7012 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7015 if (!key || !key_len)
7018 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7019 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7020 (struct i40e_aqc_get_set_rss_key_data *)key);
7022 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7026 uint32_t *key_dw = (uint32_t *)key;
7029 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7030 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
7032 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
7038 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7040 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7044 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7045 rss_conf->rss_key_len);
7049 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7050 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7051 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7052 I40E_WRITE_FLUSH(hw);
7058 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7059 struct rte_eth_rss_conf *rss_conf)
7061 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7062 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7063 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7066 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7067 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7069 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7070 if (rss_hf != 0) /* Enable RSS */
7072 return 0; /* Nothing to do */
7075 if (rss_hf == 0) /* Disable RSS */
7078 return i40e_hw_rss_hash_set(pf, rss_conf);
7082 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7083 struct rte_eth_rss_conf *rss_conf)
7085 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7086 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7089 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7090 &rss_conf->rss_key_len);
7092 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7093 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7094 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7100 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7102 switch (filter_type) {
7103 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7104 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7106 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7107 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7109 case RTE_TUNNEL_FILTER_IMAC_TENID:
7110 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7112 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7113 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7115 case ETH_TUNNEL_FILTER_IMAC:
7116 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7118 case ETH_TUNNEL_FILTER_OIP:
7119 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7121 case ETH_TUNNEL_FILTER_IIP:
7122 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7125 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7132 /* Convert tunnel filter structure */
7134 i40e_tunnel_filter_convert(
7135 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7136 struct i40e_tunnel_filter *tunnel_filter)
7138 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7139 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7140 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7141 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7142 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7143 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7144 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7145 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7146 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7148 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7149 tunnel_filter->input.flags = cld_filter->element.flags;
7150 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7151 tunnel_filter->queue = cld_filter->element.queue_number;
7152 rte_memcpy(tunnel_filter->input.general_fields,
7153 cld_filter->general_fields,
7154 sizeof(cld_filter->general_fields));
7159 /* Check if there exists the tunnel filter */
7160 struct i40e_tunnel_filter *
7161 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7162 const struct i40e_tunnel_filter_input *input)
7166 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7170 return tunnel_rule->hash_map[ret];
7173 /* Add a tunnel filter into the SW list */
7175 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7176 struct i40e_tunnel_filter *tunnel_filter)
7178 struct i40e_tunnel_rule *rule = &pf->tunnel;
7181 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7184 "Failed to insert tunnel filter to hash table %d!",
7188 rule->hash_map[ret] = tunnel_filter;
7190 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7195 /* Delete a tunnel filter from the SW list */
7197 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7198 struct i40e_tunnel_filter_input *input)
7200 struct i40e_tunnel_rule *rule = &pf->tunnel;
7201 struct i40e_tunnel_filter *tunnel_filter;
7204 ret = rte_hash_del_key(rule->hash_table, input);
7207 "Failed to delete tunnel filter to hash table %d!",
7211 tunnel_filter = rule->hash_map[ret];
7212 rule->hash_map[ret] = NULL;
7214 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7215 rte_free(tunnel_filter);
7221 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7222 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7226 uint32_t ipv4_addr, ipv4_addr_le;
7227 uint8_t i, tun_type = 0;
7228 /* internal varialbe to convert ipv6 byte order */
7229 uint32_t convert_ipv6[4];
7231 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7232 struct i40e_vsi *vsi = pf->main_vsi;
7233 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7234 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7235 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7236 struct i40e_tunnel_filter *tunnel, *node;
7237 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7239 cld_filter = rte_zmalloc("tunnel_filter",
7240 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7243 if (NULL == cld_filter) {
7244 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7247 pfilter = cld_filter;
7249 ether_addr_copy(&tunnel_filter->outer_mac,
7250 (struct ether_addr *)&pfilter->element.outer_mac);
7251 ether_addr_copy(&tunnel_filter->inner_mac,
7252 (struct ether_addr *)&pfilter->element.inner_mac);
7254 pfilter->element.inner_vlan =
7255 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7256 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7257 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7258 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7259 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7260 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7262 sizeof(pfilter->element.ipaddr.v4.data));
7264 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7265 for (i = 0; i < 4; i++) {
7267 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7269 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7271 sizeof(pfilter->element.ipaddr.v6.data));
7274 /* check tunneled type */
7275 switch (tunnel_filter->tunnel_type) {
7276 case RTE_TUNNEL_TYPE_VXLAN:
7277 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7279 case RTE_TUNNEL_TYPE_NVGRE:
7280 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7282 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7283 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7286 /* Other tunnel types is not supported. */
7287 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7288 rte_free(cld_filter);
7292 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7293 &pfilter->element.flags);
7295 rte_free(cld_filter);
7299 pfilter->element.flags |= rte_cpu_to_le_16(
7300 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7301 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7302 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7303 pfilter->element.queue_number =
7304 rte_cpu_to_le_16(tunnel_filter->queue_id);
7306 /* Check if there is the filter in SW list */
7307 memset(&check_filter, 0, sizeof(check_filter));
7308 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7309 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7311 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7312 rte_free(cld_filter);
7316 if (!add && !node) {
7317 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7318 rte_free(cld_filter);
7323 ret = i40e_aq_add_cloud_filters(hw,
7324 vsi->seid, &cld_filter->element, 1);
7326 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7327 rte_free(cld_filter);
7330 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7331 if (tunnel == NULL) {
7332 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7333 rte_free(cld_filter);
7337 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7338 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7342 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7343 &cld_filter->element, 1);
7345 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7346 rte_free(cld_filter);
7349 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7352 rte_free(cld_filter);
7356 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7357 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7358 #define I40E_TR_GENEVE_KEY_MASK 0x8
7359 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7360 #define I40E_TR_GRE_KEY_MASK 0x400
7361 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7362 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7365 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7367 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7368 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7369 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7370 enum i40e_status_code status = I40E_SUCCESS;
7372 if (pf->support_multi_driver) {
7373 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7374 return I40E_NOT_SUPPORTED;
7377 memset(&filter_replace, 0,
7378 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7379 memset(&filter_replace_buf, 0,
7380 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7382 /* create L1 filter */
7383 filter_replace.old_filter_type =
7384 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7385 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7386 filter_replace.tr_bit = 0;
7388 /* Prepare the buffer, 3 entries */
7389 filter_replace_buf.data[0] =
7390 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7391 filter_replace_buf.data[0] |=
7392 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7393 filter_replace_buf.data[2] = 0xFF;
7394 filter_replace_buf.data[3] = 0xFF;
7395 filter_replace_buf.data[4] =
7396 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7397 filter_replace_buf.data[4] |=
7398 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7399 filter_replace_buf.data[7] = 0xF0;
7400 filter_replace_buf.data[8]
7401 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7402 filter_replace_buf.data[8] |=
7403 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7404 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7405 I40E_TR_GENEVE_KEY_MASK |
7406 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7407 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7408 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7409 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7411 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7412 &filter_replace_buf);
7414 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7419 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7421 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7422 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7423 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7424 enum i40e_status_code status = I40E_SUCCESS;
7426 if (pf->support_multi_driver) {
7427 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7428 return I40E_NOT_SUPPORTED;
7432 memset(&filter_replace, 0,
7433 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7434 memset(&filter_replace_buf, 0,
7435 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7436 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7437 I40E_AQC_MIRROR_CLOUD_FILTER;
7438 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7439 filter_replace.new_filter_type =
7440 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7441 /* Prepare the buffer, 2 entries */
7442 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7443 filter_replace_buf.data[0] |=
7444 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7445 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7446 filter_replace_buf.data[4] |=
7447 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7448 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7449 &filter_replace_buf);
7454 memset(&filter_replace, 0,
7455 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7456 memset(&filter_replace_buf, 0,
7457 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7459 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7460 I40E_AQC_MIRROR_CLOUD_FILTER;
7461 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7462 filter_replace.new_filter_type =
7463 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7464 /* Prepare the buffer, 2 entries */
7465 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7466 filter_replace_buf.data[0] |=
7467 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7468 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7469 filter_replace_buf.data[4] |=
7470 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7472 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7473 &filter_replace_buf);
7475 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7479 static enum i40e_status_code
7480 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7482 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7483 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7484 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7485 enum i40e_status_code status = I40E_SUCCESS;
7487 if (pf->support_multi_driver) {
7488 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7489 return I40E_NOT_SUPPORTED;
7493 memset(&filter_replace, 0,
7494 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7495 memset(&filter_replace_buf, 0,
7496 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7497 /* create L1 filter */
7498 filter_replace.old_filter_type =
7499 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7500 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7501 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7502 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7503 /* Prepare the buffer, 2 entries */
7504 filter_replace_buf.data[0] =
7505 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7506 filter_replace_buf.data[0] |=
7507 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7508 filter_replace_buf.data[2] = 0xFF;
7509 filter_replace_buf.data[3] = 0xFF;
7510 filter_replace_buf.data[4] =
7511 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7512 filter_replace_buf.data[4] |=
7513 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7514 filter_replace_buf.data[6] = 0xFF;
7515 filter_replace_buf.data[7] = 0xFF;
7516 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7517 &filter_replace_buf);
7520 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7521 "cloud l1 type is changed from 0x%x to 0x%x",
7522 filter_replace.old_filter_type,
7523 filter_replace.new_filter_type);
7526 memset(&filter_replace, 0,
7527 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7528 memset(&filter_replace_buf, 0,
7529 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7530 /* create L1 filter */
7531 filter_replace.old_filter_type =
7532 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7533 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7534 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7535 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7536 /* Prepare the buffer, 2 entries */
7537 filter_replace_buf.data[0] =
7538 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7539 filter_replace_buf.data[0] |=
7540 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7541 filter_replace_buf.data[2] = 0xFF;
7542 filter_replace_buf.data[3] = 0xFF;
7543 filter_replace_buf.data[4] =
7544 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7545 filter_replace_buf.data[4] |=
7546 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7547 filter_replace_buf.data[6] = 0xFF;
7548 filter_replace_buf.data[7] = 0xFF;
7550 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7551 &filter_replace_buf);
7553 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7554 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7555 "cloud l1 type is changed from 0x%x to 0x%x",
7556 filter_replace.old_filter_type,
7557 filter_replace.new_filter_type);
7563 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7565 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7566 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7567 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7568 enum i40e_status_code status = I40E_SUCCESS;
7570 if (pf->support_multi_driver) {
7571 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7572 return I40E_NOT_SUPPORTED;
7576 memset(&filter_replace, 0,
7577 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7578 memset(&filter_replace_buf, 0,
7579 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7580 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7581 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7582 filter_replace.new_filter_type =
7583 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7584 /* Prepare the buffer, 2 entries */
7585 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7586 filter_replace_buf.data[0] |=
7587 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7588 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7589 filter_replace_buf.data[4] |=
7590 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7591 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7592 &filter_replace_buf);
7595 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7596 "cloud filter type is changed from 0x%x to 0x%x",
7597 filter_replace.old_filter_type,
7598 filter_replace.new_filter_type);
7601 memset(&filter_replace, 0,
7602 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7603 memset(&filter_replace_buf, 0,
7604 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7605 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7606 filter_replace.old_filter_type =
7607 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7608 filter_replace.new_filter_type =
7609 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7610 /* Prepare the buffer, 2 entries */
7611 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7612 filter_replace_buf.data[0] |=
7613 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7614 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7615 filter_replace_buf.data[4] |=
7616 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7618 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7619 &filter_replace_buf);
7621 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7622 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7623 "cloud filter type is changed from 0x%x to 0x%x",
7624 filter_replace.old_filter_type,
7625 filter_replace.new_filter_type);
7631 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7632 struct i40e_tunnel_filter_conf *tunnel_filter,
7636 uint32_t ipv4_addr, ipv4_addr_le;
7637 uint8_t i, tun_type = 0;
7638 /* internal variable to convert ipv6 byte order */
7639 uint32_t convert_ipv6[4];
7641 struct i40e_pf_vf *vf = NULL;
7642 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7643 struct i40e_vsi *vsi;
7644 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7645 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7646 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7647 struct i40e_tunnel_filter *tunnel, *node;
7648 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7650 bool big_buffer = 0;
7652 cld_filter = rte_zmalloc("tunnel_filter",
7653 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7656 if (cld_filter == NULL) {
7657 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7660 pfilter = cld_filter;
7662 ether_addr_copy(&tunnel_filter->outer_mac,
7663 (struct ether_addr *)&pfilter->element.outer_mac);
7664 ether_addr_copy(&tunnel_filter->inner_mac,
7665 (struct ether_addr *)&pfilter->element.inner_mac);
7667 pfilter->element.inner_vlan =
7668 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7669 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7670 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7671 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7672 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7673 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7675 sizeof(pfilter->element.ipaddr.v4.data));
7677 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7678 for (i = 0; i < 4; i++) {
7680 rte_cpu_to_le_32(rte_be_to_cpu_32(
7681 tunnel_filter->ip_addr.ipv6_addr[i]));
7683 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7685 sizeof(pfilter->element.ipaddr.v6.data));
7688 /* check tunneled type */
7689 switch (tunnel_filter->tunnel_type) {
7690 case I40E_TUNNEL_TYPE_VXLAN:
7691 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7693 case I40E_TUNNEL_TYPE_NVGRE:
7694 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7696 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7697 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7699 case I40E_TUNNEL_TYPE_MPLSoUDP:
7700 if (!pf->mpls_replace_flag) {
7701 i40e_replace_mpls_l1_filter(pf);
7702 i40e_replace_mpls_cloud_filter(pf);
7703 pf->mpls_replace_flag = 1;
7705 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7706 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7708 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7709 (teid_le & 0xF) << 12;
7710 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7713 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7715 case I40E_TUNNEL_TYPE_MPLSoGRE:
7716 if (!pf->mpls_replace_flag) {
7717 i40e_replace_mpls_l1_filter(pf);
7718 i40e_replace_mpls_cloud_filter(pf);
7719 pf->mpls_replace_flag = 1;
7721 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7722 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7724 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7725 (teid_le & 0xF) << 12;
7726 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7729 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7731 case I40E_TUNNEL_TYPE_GTPC:
7732 if (!pf->gtp_replace_flag) {
7733 i40e_replace_gtp_l1_filter(pf);
7734 i40e_replace_gtp_cloud_filter(pf);
7735 pf->gtp_replace_flag = 1;
7737 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7738 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7739 (teid_le >> 16) & 0xFFFF;
7740 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7742 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7746 case I40E_TUNNEL_TYPE_GTPU:
7747 if (!pf->gtp_replace_flag) {
7748 i40e_replace_gtp_l1_filter(pf);
7749 i40e_replace_gtp_cloud_filter(pf);
7750 pf->gtp_replace_flag = 1;
7752 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7753 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7754 (teid_le >> 16) & 0xFFFF;
7755 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7757 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7761 case I40E_TUNNEL_TYPE_QINQ:
7762 if (!pf->qinq_replace_flag) {
7763 ret = i40e_cloud_filter_qinq_create(pf);
7766 "QinQ tunnel filter already created.");
7767 pf->qinq_replace_flag = 1;
7769 /* Add in the General fields the values of
7770 * the Outer and Inner VLAN
7771 * Big Buffer should be set, see changes in
7772 * i40e_aq_add_cloud_filters
7774 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7775 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7779 /* Other tunnel types is not supported. */
7780 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7781 rte_free(cld_filter);
7785 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7786 pfilter->element.flags =
7787 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7788 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7789 pfilter->element.flags =
7790 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7791 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7792 pfilter->element.flags =
7793 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7794 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7795 pfilter->element.flags =
7796 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7797 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7798 pfilter->element.flags |=
7799 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7801 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7802 &pfilter->element.flags);
7804 rte_free(cld_filter);
7809 pfilter->element.flags |= rte_cpu_to_le_16(
7810 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7811 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7812 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7813 pfilter->element.queue_number =
7814 rte_cpu_to_le_16(tunnel_filter->queue_id);
7816 if (!tunnel_filter->is_to_vf)
7819 if (tunnel_filter->vf_id >= pf->vf_num) {
7820 PMD_DRV_LOG(ERR, "Invalid argument.");
7821 rte_free(cld_filter);
7824 vf = &pf->vfs[tunnel_filter->vf_id];
7828 /* Check if there is the filter in SW list */
7829 memset(&check_filter, 0, sizeof(check_filter));
7830 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7831 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7832 check_filter.vf_id = tunnel_filter->vf_id;
7833 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7835 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7836 rte_free(cld_filter);
7840 if (!add && !node) {
7841 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7842 rte_free(cld_filter);
7848 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7849 vsi->seid, cld_filter, 1);
7851 ret = i40e_aq_add_cloud_filters(hw,
7852 vsi->seid, &cld_filter->element, 1);
7854 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7855 rte_free(cld_filter);
7858 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7859 if (tunnel == NULL) {
7860 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7861 rte_free(cld_filter);
7865 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7866 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7871 ret = i40e_aq_remove_cloud_filters_big_buffer(
7872 hw, vsi->seid, cld_filter, 1);
7874 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7875 &cld_filter->element, 1);
7877 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7878 rte_free(cld_filter);
7881 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7884 rte_free(cld_filter);
7889 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7893 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7894 if (pf->vxlan_ports[i] == port)
7902 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7906 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7908 idx = i40e_get_vxlan_port_idx(pf, port);
7910 /* Check if port already exists */
7912 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7916 /* Now check if there is space to add the new port */
7917 idx = i40e_get_vxlan_port_idx(pf, 0);
7920 "Maximum number of UDP ports reached, not adding port %d",
7925 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7928 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7932 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7935 /* New port: add it and mark its index in the bitmap */
7936 pf->vxlan_ports[idx] = port;
7937 pf->vxlan_bitmap |= (1 << idx);
7939 if (!(pf->flags & I40E_FLAG_VXLAN))
7940 pf->flags |= I40E_FLAG_VXLAN;
7946 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7949 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7951 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7952 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7956 idx = i40e_get_vxlan_port_idx(pf, port);
7959 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7963 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7964 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7968 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7971 pf->vxlan_ports[idx] = 0;
7972 pf->vxlan_bitmap &= ~(1 << idx);
7974 if (!pf->vxlan_bitmap)
7975 pf->flags &= ~I40E_FLAG_VXLAN;
7980 /* Add UDP tunneling port */
7982 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7983 struct rte_eth_udp_tunnel *udp_tunnel)
7986 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7988 if (udp_tunnel == NULL)
7991 switch (udp_tunnel->prot_type) {
7992 case RTE_TUNNEL_TYPE_VXLAN:
7993 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7996 case RTE_TUNNEL_TYPE_GENEVE:
7997 case RTE_TUNNEL_TYPE_TEREDO:
7998 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8003 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8011 /* Remove UDP tunneling port */
8013 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8014 struct rte_eth_udp_tunnel *udp_tunnel)
8017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8019 if (udp_tunnel == NULL)
8022 switch (udp_tunnel->prot_type) {
8023 case RTE_TUNNEL_TYPE_VXLAN:
8024 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8026 case RTE_TUNNEL_TYPE_GENEVE:
8027 case RTE_TUNNEL_TYPE_TEREDO:
8028 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8032 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8040 /* Calculate the maximum number of contiguous PF queues that are configured */
8042 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8044 struct rte_eth_dev_data *data = pf->dev_data;
8046 struct i40e_rx_queue *rxq;
8049 for (i = 0; i < pf->lan_nb_qps; i++) {
8050 rxq = data->rx_queues[i];
8051 if (rxq && rxq->q_set)
8062 i40e_pf_config_rss(struct i40e_pf *pf)
8064 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8065 struct rte_eth_rss_conf rss_conf;
8066 uint32_t i, lut = 0;
8070 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8071 * It's necessary to calculate the actual PF queues that are configured.
8073 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8074 num = i40e_pf_calc_configured_queues_num(pf);
8076 num = pf->dev_data->nb_rx_queues;
8078 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8079 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8083 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8087 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8090 lut = (lut << 8) | (j & ((0x1 <<
8091 hw->func_caps.rss_table_entry_width) - 1));
8093 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8096 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8097 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8098 i40e_pf_disable_rss(pf);
8101 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8102 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8103 /* Random default keys */
8104 static uint32_t rss_key_default[] = {0x6b793944,
8105 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8106 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8107 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8109 rss_conf.rss_key = (uint8_t *)rss_key_default;
8110 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8114 return i40e_hw_rss_hash_set(pf, &rss_conf);
8118 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8119 struct rte_eth_tunnel_filter_conf *filter)
8121 if (pf == NULL || filter == NULL) {
8122 PMD_DRV_LOG(ERR, "Invalid parameter");
8126 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8127 PMD_DRV_LOG(ERR, "Invalid queue ID");
8131 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8132 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8136 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8137 (is_zero_ether_addr(&filter->outer_mac))) {
8138 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8142 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8143 (is_zero_ether_addr(&filter->inner_mac))) {
8144 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8151 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8152 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8154 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8156 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8160 if (pf->support_multi_driver) {
8161 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8165 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8166 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8169 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8170 } else if (len == 4) {
8171 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8173 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8178 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8182 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8183 "with value 0x%08x",
8184 I40E_GL_PRS_FVBM(2), reg);
8185 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8189 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8190 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8196 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8203 switch (cfg->cfg_type) {
8204 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8205 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8208 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8216 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8217 enum rte_filter_op filter_op,
8220 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8221 int ret = I40E_ERR_PARAM;
8223 switch (filter_op) {
8224 case RTE_ETH_FILTER_SET:
8225 ret = i40e_dev_global_config_set(hw,
8226 (struct rte_eth_global_cfg *)arg);
8229 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8237 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8238 enum rte_filter_op filter_op,
8241 struct rte_eth_tunnel_filter_conf *filter;
8242 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8243 int ret = I40E_SUCCESS;
8245 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8247 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8248 return I40E_ERR_PARAM;
8250 switch (filter_op) {
8251 case RTE_ETH_FILTER_NOP:
8252 if (!(pf->flags & I40E_FLAG_VXLAN))
8253 ret = I40E_NOT_SUPPORTED;
8255 case RTE_ETH_FILTER_ADD:
8256 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8258 case RTE_ETH_FILTER_DELETE:
8259 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8262 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8263 ret = I40E_ERR_PARAM;
8271 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8274 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8277 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8278 ret = i40e_pf_config_rss(pf);
8280 i40e_pf_disable_rss(pf);
8285 /* Get the symmetric hash enable configurations per port */
8287 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8289 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8291 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8294 /* Set the symmetric hash enable configurations per port */
8296 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8298 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8301 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8303 "Symmetric hash has already been enabled");
8306 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8308 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8310 "Symmetric hash has already been disabled");
8313 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8315 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8316 I40E_WRITE_FLUSH(hw);
8320 * Get global configurations of hash function type and symmetric hash enable
8321 * per flow type (pctype). Note that global configuration means it affects all
8322 * the ports on the same NIC.
8325 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8326 struct rte_eth_hash_global_conf *g_cfg)
8328 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8332 memset(g_cfg, 0, sizeof(*g_cfg));
8333 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8334 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8335 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8337 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8338 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8339 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8342 * We work only with lowest 32 bits which is not correct, but to work
8343 * properly the valid_bit_mask size should be increased up to 64 bits
8344 * and this will brake ABI. This modification will be done in next
8347 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8349 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8350 if (!adapter->pctypes_tbl[i])
8352 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8353 j < I40E_FILTER_PCTYPE_MAX; j++) {
8354 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8355 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8356 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8357 g_cfg->sym_hash_enable_mask[0] |=
8368 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8369 const struct rte_eth_hash_global_conf *g_cfg)
8372 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8374 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8375 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8376 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8377 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8383 * As i40e supports less than 32 flow types, only first 32 bits need to
8386 mask0 = g_cfg->valid_bit_mask[0];
8387 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8389 /* Check if any unsupported flow type configured */
8390 if ((mask0 | i40e_mask) ^ i40e_mask)
8393 if (g_cfg->valid_bit_mask[i])
8401 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8407 * Set global configurations of hash function type and symmetric hash enable
8408 * per flow type (pctype). Note any modifying global configuration will affect
8409 * all the ports on the same NIC.
8412 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8413 struct rte_eth_hash_global_conf *g_cfg)
8415 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8416 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8421 * We work only with lowest 32 bits which is not correct, but to work
8422 * properly the valid_bit_mask size should be increased up to 64 bits
8423 * and this will brake ABI. This modification will be done in next
8426 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8427 (uint32_t)adapter->flow_types_mask;
8429 if (pf->support_multi_driver) {
8430 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8434 /* Check the input parameters */
8435 ret = i40e_hash_global_config_check(adapter, g_cfg);
8439 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8440 if (mask0 & (1UL << i)) {
8441 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8442 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8444 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8445 j < I40E_FILTER_PCTYPE_MAX; j++) {
8446 if (adapter->pctypes_tbl[i] & (1ULL << j))
8447 i40e_write_global_rx_ctl(hw,
8451 i40e_global_cfg_warning(I40E_WARNING_HSYM);
8455 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8456 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8458 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8460 "Hash function already set to Toeplitz");
8463 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8464 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8466 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8468 "Hash function already set to Simple XOR");
8471 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8473 /* Use the default, and keep it as it is */
8476 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8477 i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8480 I40E_WRITE_FLUSH(hw);
8486 * Valid input sets for hash and flow director filters per PCTYPE
8489 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8490 enum rte_filter_type filter)
8494 static const uint64_t valid_hash_inset_table[] = {
8495 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8496 I40E_INSET_DMAC | I40E_INSET_SMAC |
8497 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8498 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8499 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8500 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8501 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8502 I40E_INSET_FLEX_PAYLOAD,
8503 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8504 I40E_INSET_DMAC | I40E_INSET_SMAC |
8505 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8506 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8507 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8508 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8509 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8510 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8511 I40E_INSET_FLEX_PAYLOAD,
8512 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8513 I40E_INSET_DMAC | I40E_INSET_SMAC |
8514 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8515 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8516 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8517 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8518 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8519 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8520 I40E_INSET_FLEX_PAYLOAD,
8521 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8522 I40E_INSET_DMAC | I40E_INSET_SMAC |
8523 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8524 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8525 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8526 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8527 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8528 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8529 I40E_INSET_FLEX_PAYLOAD,
8530 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8531 I40E_INSET_DMAC | I40E_INSET_SMAC |
8532 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8533 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8534 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8535 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8536 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8537 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8538 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8539 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8540 I40E_INSET_DMAC | I40E_INSET_SMAC |
8541 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8542 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8543 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8544 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8545 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8546 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8547 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8548 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8549 I40E_INSET_DMAC | I40E_INSET_SMAC |
8550 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8551 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8552 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8553 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8554 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8555 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8556 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8557 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8558 I40E_INSET_DMAC | I40E_INSET_SMAC |
8559 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8560 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8561 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8562 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8563 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8564 I40E_INSET_FLEX_PAYLOAD,
8565 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8566 I40E_INSET_DMAC | I40E_INSET_SMAC |
8567 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8568 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8569 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8570 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8571 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8572 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8573 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8574 I40E_INSET_DMAC | I40E_INSET_SMAC |
8575 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8576 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8577 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8578 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8579 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8580 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8581 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8582 I40E_INSET_DMAC | I40E_INSET_SMAC |
8583 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8584 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8585 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8586 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8587 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8588 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8589 I40E_INSET_FLEX_PAYLOAD,
8590 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8591 I40E_INSET_DMAC | I40E_INSET_SMAC |
8592 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8593 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8594 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8595 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8596 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8597 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8598 I40E_INSET_FLEX_PAYLOAD,
8599 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8600 I40E_INSET_DMAC | I40E_INSET_SMAC |
8601 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8602 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8603 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8604 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8605 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8606 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8607 I40E_INSET_FLEX_PAYLOAD,
8608 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8609 I40E_INSET_DMAC | I40E_INSET_SMAC |
8610 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8611 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8612 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8613 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8614 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8615 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8616 I40E_INSET_FLEX_PAYLOAD,
8617 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8618 I40E_INSET_DMAC | I40E_INSET_SMAC |
8619 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8620 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8621 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8622 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8623 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8624 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8625 I40E_INSET_FLEX_PAYLOAD,
8626 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8627 I40E_INSET_DMAC | I40E_INSET_SMAC |
8628 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8629 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8630 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8631 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8632 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8633 I40E_INSET_FLEX_PAYLOAD,
8634 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8635 I40E_INSET_DMAC | I40E_INSET_SMAC |
8636 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8637 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8638 I40E_INSET_FLEX_PAYLOAD,
8642 * Flow director supports only fields defined in
8643 * union rte_eth_fdir_flow.
8645 static const uint64_t valid_fdir_inset_table[] = {
8646 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8647 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8648 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8649 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8650 I40E_INSET_IPV4_TTL,
8651 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8652 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8653 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8654 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8655 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8656 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8657 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8658 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8659 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8660 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8661 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8662 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8663 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8664 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8665 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8666 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8667 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8668 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8669 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8670 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8671 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8672 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8673 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8674 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8675 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8676 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8677 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8678 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8679 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8680 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8682 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8683 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8684 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8685 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8686 I40E_INSET_IPV4_TTL,
8687 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8688 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8689 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8690 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8691 I40E_INSET_IPV6_HOP_LIMIT,
8692 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8693 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8694 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8695 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8696 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8697 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8698 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8699 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8700 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8701 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8702 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8703 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8704 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8705 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8706 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8707 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8708 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8709 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8710 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8711 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8712 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8713 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8714 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8715 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8716 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8717 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8718 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8719 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8720 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8721 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8723 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8724 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8725 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8726 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8727 I40E_INSET_IPV6_HOP_LIMIT,
8728 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8729 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8730 I40E_INSET_LAST_ETHER_TYPE,
8733 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8735 if (filter == RTE_ETH_FILTER_HASH)
8736 valid = valid_hash_inset_table[pctype];
8738 valid = valid_fdir_inset_table[pctype];
8744 * Validate if the input set is allowed for a specific PCTYPE
8747 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8748 enum rte_filter_type filter, uint64_t inset)
8752 valid = i40e_get_valid_input_set(pctype, filter);
8753 if (inset & (~valid))
8759 /* default input set fields combination per pctype */
8761 i40e_get_default_input_set(uint16_t pctype)
8763 static const uint64_t default_inset_table[] = {
8764 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8765 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8766 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8767 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8768 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8769 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8770 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8771 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8772 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8773 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8774 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8775 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8776 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8777 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8778 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8779 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8780 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8781 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8782 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8783 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8785 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8786 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8787 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8788 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8789 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8790 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8791 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8792 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8793 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8794 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8795 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8796 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8797 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8798 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8799 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8800 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8801 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8802 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8803 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8804 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8805 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8806 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8808 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8809 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8810 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8811 I40E_INSET_LAST_ETHER_TYPE,
8814 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8817 return default_inset_table[pctype];
8821 * Parse the input set from index to logical bit masks
8824 i40e_parse_input_set(uint64_t *inset,
8825 enum i40e_filter_pctype pctype,
8826 enum rte_eth_input_set_field *field,
8832 static const struct {
8833 enum rte_eth_input_set_field field;
8835 } inset_convert_table[] = {
8836 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8837 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8838 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8839 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8840 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8841 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8842 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8843 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8844 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8845 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8846 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8847 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8848 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8849 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8850 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8851 I40E_INSET_IPV6_NEXT_HDR},
8852 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8853 I40E_INSET_IPV6_HOP_LIMIT},
8854 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8855 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8856 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8857 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8858 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8859 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8860 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8861 I40E_INSET_SCTP_VT},
8862 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8863 I40E_INSET_TUNNEL_DMAC},
8864 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8865 I40E_INSET_VLAN_TUNNEL},
8866 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8867 I40E_INSET_TUNNEL_ID},
8868 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8869 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8870 I40E_INSET_FLEX_PAYLOAD_W1},
8871 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8872 I40E_INSET_FLEX_PAYLOAD_W2},
8873 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8874 I40E_INSET_FLEX_PAYLOAD_W3},
8875 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8876 I40E_INSET_FLEX_PAYLOAD_W4},
8877 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8878 I40E_INSET_FLEX_PAYLOAD_W5},
8879 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8880 I40E_INSET_FLEX_PAYLOAD_W6},
8881 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8882 I40E_INSET_FLEX_PAYLOAD_W7},
8883 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8884 I40E_INSET_FLEX_PAYLOAD_W8},
8887 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8890 /* Only one item allowed for default or all */
8892 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8893 *inset = i40e_get_default_input_set(pctype);
8895 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8896 *inset = I40E_INSET_NONE;
8901 for (i = 0, *inset = 0; i < size; i++) {
8902 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8903 if (field[i] == inset_convert_table[j].field) {
8904 *inset |= inset_convert_table[j].inset;
8909 /* It contains unsupported input set, return immediately */
8910 if (j == RTE_DIM(inset_convert_table))
8918 * Translate the input set from bit masks to register aware bit masks
8922 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8932 static const struct inset_map inset_map_common[] = {
8933 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8934 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8935 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8936 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8937 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8938 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8939 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8940 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8941 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8942 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8943 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8944 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8945 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8946 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8947 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8948 {I40E_INSET_TUNNEL_DMAC,
8949 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8950 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8951 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8952 {I40E_INSET_TUNNEL_SRC_PORT,
8953 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8954 {I40E_INSET_TUNNEL_DST_PORT,
8955 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8956 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8957 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8958 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8959 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8960 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8961 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8962 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8963 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8964 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8967 /* some different registers map in x722*/
8968 static const struct inset_map inset_map_diff_x722[] = {
8969 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8970 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8971 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8972 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8975 static const struct inset_map inset_map_diff_not_x722[] = {
8976 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8977 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8978 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8979 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8985 /* Translate input set to register aware inset */
8986 if (type == I40E_MAC_X722) {
8987 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8988 if (input & inset_map_diff_x722[i].inset)
8989 val |= inset_map_diff_x722[i].inset_reg;
8992 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8993 if (input & inset_map_diff_not_x722[i].inset)
8994 val |= inset_map_diff_not_x722[i].inset_reg;
8998 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8999 if (input & inset_map_common[i].inset)
9000 val |= inset_map_common[i].inset_reg;
9007 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9010 uint64_t inset_need_mask = inset;
9012 static const struct {
9015 } inset_mask_map[] = {
9016 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9017 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9018 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9019 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9020 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9021 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9022 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9023 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9026 if (!inset || !mask || !nb_elem)
9029 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9030 /* Clear the inset bit, if no MASK is required,
9031 * for example proto + ttl
9033 if ((inset & inset_mask_map[i].inset) ==
9034 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9035 inset_need_mask &= ~inset_mask_map[i].inset;
9036 if (!inset_need_mask)
9039 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9040 if ((inset_need_mask & inset_mask_map[i].inset) ==
9041 inset_mask_map[i].inset) {
9042 if (idx >= nb_elem) {
9043 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9046 mask[idx] = inset_mask_map[i].mask;
9055 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9057 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9059 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9061 i40e_write_rx_ctl(hw, addr, val);
9062 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9063 (uint32_t)i40e_read_rx_ctl(hw, addr));
9067 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9069 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9071 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9073 i40e_write_global_rx_ctl(hw, addr, val);
9074 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9075 (uint32_t)i40e_read_rx_ctl(hw, addr));
9079 i40e_filter_input_set_init(struct i40e_pf *pf)
9081 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9082 enum i40e_filter_pctype pctype;
9083 uint64_t input_set, inset_reg;
9084 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9088 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9089 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9090 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9092 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9095 input_set = i40e_get_default_input_set(pctype);
9097 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9098 I40E_INSET_MASK_NUM_REG);
9101 if (pf->support_multi_driver && num > 0) {
9102 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9105 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9108 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9109 (uint32_t)(inset_reg & UINT32_MAX));
9110 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9111 (uint32_t)((inset_reg >>
9112 I40E_32_BIT_WIDTH) & UINT32_MAX));
9113 if (!pf->support_multi_driver) {
9114 i40e_check_write_global_reg(hw,
9115 I40E_GLQF_HASH_INSET(0, pctype),
9116 (uint32_t)(inset_reg & UINT32_MAX));
9117 i40e_check_write_global_reg(hw,
9118 I40E_GLQF_HASH_INSET(1, pctype),
9119 (uint32_t)((inset_reg >>
9120 I40E_32_BIT_WIDTH) & UINT32_MAX));
9122 for (i = 0; i < num; i++) {
9123 i40e_check_write_global_reg(hw,
9124 I40E_GLQF_FD_MSK(i, pctype),
9126 i40e_check_write_global_reg(hw,
9127 I40E_GLQF_HASH_MSK(i, pctype),
9130 /*clear unused mask registers of the pctype */
9131 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9132 i40e_check_write_global_reg(hw,
9133 I40E_GLQF_FD_MSK(i, pctype),
9135 i40e_check_write_global_reg(hw,
9136 I40E_GLQF_HASH_MSK(i, pctype),
9140 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9142 I40E_WRITE_FLUSH(hw);
9144 /* store the default input set */
9145 if (!pf->support_multi_driver)
9146 pf->hash_input_set[pctype] = input_set;
9147 pf->fdir.input_set[pctype] = input_set;
9150 if (!pf->support_multi_driver) {
9151 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9152 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9153 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9158 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9159 struct rte_eth_input_set_conf *conf)
9161 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9162 enum i40e_filter_pctype pctype;
9163 uint64_t input_set, inset_reg = 0;
9164 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9168 PMD_DRV_LOG(ERR, "Invalid pointer");
9171 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9172 conf->op != RTE_ETH_INPUT_SET_ADD) {
9173 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9177 if (pf->support_multi_driver) {
9178 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9182 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9183 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9184 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9188 if (hw->mac.type == I40E_MAC_X722) {
9189 /* get translated pctype value in fd pctype register */
9190 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9191 I40E_GLQF_FD_PCTYPES((int)pctype));
9194 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9197 PMD_DRV_LOG(ERR, "Failed to parse input set");
9201 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9202 /* get inset value in register */
9203 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9204 inset_reg <<= I40E_32_BIT_WIDTH;
9205 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9206 input_set |= pf->hash_input_set[pctype];
9208 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9209 I40E_INSET_MASK_NUM_REG);
9213 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9215 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9216 (uint32_t)(inset_reg & UINT32_MAX));
9217 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9218 (uint32_t)((inset_reg >>
9219 I40E_32_BIT_WIDTH) & UINT32_MAX));
9220 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9222 for (i = 0; i < num; i++)
9223 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9225 /*clear unused mask registers of the pctype */
9226 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9227 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9229 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9230 I40E_WRITE_FLUSH(hw);
9232 pf->hash_input_set[pctype] = input_set;
9237 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9238 struct rte_eth_input_set_conf *conf)
9240 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9241 enum i40e_filter_pctype pctype;
9242 uint64_t input_set, inset_reg = 0;
9243 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9247 PMD_DRV_LOG(ERR, "Invalid pointer");
9250 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9251 conf->op != RTE_ETH_INPUT_SET_ADD) {
9252 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9256 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9258 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9259 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9263 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9266 PMD_DRV_LOG(ERR, "Failed to parse input set");
9270 /* get inset value in register */
9271 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9272 inset_reg <<= I40E_32_BIT_WIDTH;
9273 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9275 /* Can not change the inset reg for flex payload for fdir,
9276 * it is done by writing I40E_PRTQF_FD_FLXINSET
9277 * in i40e_set_flex_mask_on_pctype.
9279 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9280 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9282 input_set |= pf->fdir.input_set[pctype];
9283 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9284 I40E_INSET_MASK_NUM_REG);
9287 if (pf->support_multi_driver && num > 0) {
9288 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9292 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9294 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9295 (uint32_t)(inset_reg & UINT32_MAX));
9296 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9297 (uint32_t)((inset_reg >>
9298 I40E_32_BIT_WIDTH) & UINT32_MAX));
9300 if (!pf->support_multi_driver) {
9301 for (i = 0; i < num; i++)
9302 i40e_check_write_global_reg(hw,
9303 I40E_GLQF_FD_MSK(i, pctype),
9305 /*clear unused mask registers of the pctype */
9306 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9307 i40e_check_write_global_reg(hw,
9308 I40E_GLQF_FD_MSK(i, pctype),
9310 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9312 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9314 I40E_WRITE_FLUSH(hw);
9316 pf->fdir.input_set[pctype] = input_set;
9321 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9326 PMD_DRV_LOG(ERR, "Invalid pointer");
9330 switch (info->info_type) {
9331 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9332 i40e_get_symmetric_hash_enable_per_port(hw,
9333 &(info->info.enable));
9335 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9336 ret = i40e_get_hash_filter_global_config(hw,
9337 &(info->info.global_conf));
9340 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9350 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9355 PMD_DRV_LOG(ERR, "Invalid pointer");
9359 switch (info->info_type) {
9360 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9361 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9363 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9364 ret = i40e_set_hash_filter_global_config(hw,
9365 &(info->info.global_conf));
9367 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9368 ret = i40e_hash_filter_inset_select(hw,
9369 &(info->info.input_set_conf));
9373 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9382 /* Operations for hash function */
9384 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9385 enum rte_filter_op filter_op,
9388 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9391 switch (filter_op) {
9392 case RTE_ETH_FILTER_NOP:
9394 case RTE_ETH_FILTER_GET:
9395 ret = i40e_hash_filter_get(hw,
9396 (struct rte_eth_hash_filter_info *)arg);
9398 case RTE_ETH_FILTER_SET:
9399 ret = i40e_hash_filter_set(hw,
9400 (struct rte_eth_hash_filter_info *)arg);
9403 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9412 /* Convert ethertype filter structure */
9414 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9415 struct i40e_ethertype_filter *filter)
9417 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9418 filter->input.ether_type = input->ether_type;
9419 filter->flags = input->flags;
9420 filter->queue = input->queue;
9425 /* Check if there exists the ehtertype filter */
9426 struct i40e_ethertype_filter *
9427 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9428 const struct i40e_ethertype_filter_input *input)
9432 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9436 return ethertype_rule->hash_map[ret];
9439 /* Add ethertype filter in SW list */
9441 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9442 struct i40e_ethertype_filter *filter)
9444 struct i40e_ethertype_rule *rule = &pf->ethertype;
9447 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9450 "Failed to insert ethertype filter"
9451 " to hash table %d!",
9455 rule->hash_map[ret] = filter;
9457 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9462 /* Delete ethertype filter in SW list */
9464 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9465 struct i40e_ethertype_filter_input *input)
9467 struct i40e_ethertype_rule *rule = &pf->ethertype;
9468 struct i40e_ethertype_filter *filter;
9471 ret = rte_hash_del_key(rule->hash_table, input);
9474 "Failed to delete ethertype filter"
9475 " to hash table %d!",
9479 filter = rule->hash_map[ret];
9480 rule->hash_map[ret] = NULL;
9482 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9489 * Configure ethertype filter, which can director packet by filtering
9490 * with mac address and ether_type or only ether_type
9493 i40e_ethertype_filter_set(struct i40e_pf *pf,
9494 struct rte_eth_ethertype_filter *filter,
9497 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9498 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9499 struct i40e_ethertype_filter *ethertype_filter, *node;
9500 struct i40e_ethertype_filter check_filter;
9501 struct i40e_control_filter_stats stats;
9505 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9506 PMD_DRV_LOG(ERR, "Invalid queue ID");
9509 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9510 filter->ether_type == ETHER_TYPE_IPv6) {
9512 "unsupported ether_type(0x%04x) in control packet filter.",
9513 filter->ether_type);
9516 if (filter->ether_type == ETHER_TYPE_VLAN)
9517 PMD_DRV_LOG(WARNING,
9518 "filter vlan ether_type in first tag is not supported.");
9520 /* Check if there is the filter in SW list */
9521 memset(&check_filter, 0, sizeof(check_filter));
9522 i40e_ethertype_filter_convert(filter, &check_filter);
9523 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9524 &check_filter.input);
9526 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9530 if (!add && !node) {
9531 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9535 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9536 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9537 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9538 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9539 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9541 memset(&stats, 0, sizeof(stats));
9542 ret = i40e_aq_add_rem_control_packet_filter(hw,
9543 filter->mac_addr.addr_bytes,
9544 filter->ether_type, flags,
9546 filter->queue, add, &stats, NULL);
9549 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9550 ret, stats.mac_etype_used, stats.etype_used,
9551 stats.mac_etype_free, stats.etype_free);
9555 /* Add or delete a filter in SW list */
9557 ethertype_filter = rte_zmalloc("ethertype_filter",
9558 sizeof(*ethertype_filter), 0);
9559 if (ethertype_filter == NULL) {
9560 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9564 rte_memcpy(ethertype_filter, &check_filter,
9565 sizeof(check_filter));
9566 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9568 rte_free(ethertype_filter);
9570 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9577 * Handle operations for ethertype filter.
9580 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9581 enum rte_filter_op filter_op,
9584 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9587 if (filter_op == RTE_ETH_FILTER_NOP)
9591 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9596 switch (filter_op) {
9597 case RTE_ETH_FILTER_ADD:
9598 ret = i40e_ethertype_filter_set(pf,
9599 (struct rte_eth_ethertype_filter *)arg,
9602 case RTE_ETH_FILTER_DELETE:
9603 ret = i40e_ethertype_filter_set(pf,
9604 (struct rte_eth_ethertype_filter *)arg,
9608 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9616 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9617 enum rte_filter_type filter_type,
9618 enum rte_filter_op filter_op,
9626 switch (filter_type) {
9627 case RTE_ETH_FILTER_NONE:
9628 /* For global configuration */
9629 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9631 case RTE_ETH_FILTER_HASH:
9632 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9634 case RTE_ETH_FILTER_MACVLAN:
9635 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9637 case RTE_ETH_FILTER_ETHERTYPE:
9638 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9640 case RTE_ETH_FILTER_TUNNEL:
9641 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9643 case RTE_ETH_FILTER_FDIR:
9644 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9646 case RTE_ETH_FILTER_GENERIC:
9647 if (filter_op != RTE_ETH_FILTER_GET)
9649 *(const void **)arg = &i40e_flow_ops;
9652 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9662 * Check and enable Extended Tag.
9663 * Enabling Extended Tag is important for 40G performance.
9666 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9668 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9672 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9675 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9679 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9680 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9685 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9688 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9692 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9693 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9696 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9697 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9700 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9707 * As some registers wouldn't be reset unless a global hardware reset,
9708 * hardware initialization is needed to put those registers into an
9709 * expected initial state.
9712 i40e_hw_init(struct rte_eth_dev *dev)
9714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9716 i40e_enable_extended_tag(dev);
9718 /* clear the PF Queue Filter control register */
9719 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9721 /* Disable symmetric hash per port */
9722 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9726 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9727 * however this function will return only one highest pctype index,
9728 * which is not quite correct. This is known problem of i40e driver
9729 * and needs to be fixed later.
9731 enum i40e_filter_pctype
9732 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9735 uint64_t pctype_mask;
9737 if (flow_type < I40E_FLOW_TYPE_MAX) {
9738 pctype_mask = adapter->pctypes_tbl[flow_type];
9739 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9740 if (pctype_mask & (1ULL << i))
9741 return (enum i40e_filter_pctype)i;
9744 return I40E_FILTER_PCTYPE_INVALID;
9748 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9749 enum i40e_filter_pctype pctype)
9752 uint64_t pctype_mask = 1ULL << pctype;
9754 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9756 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9760 return RTE_ETH_FLOW_UNKNOWN;
9764 * On X710, performance number is far from the expectation on recent firmware
9765 * versions; on XL710, performance number is also far from the expectation on
9766 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9767 * mode is enabled and port MAC address is equal to the packet destination MAC
9768 * address. The fix for this issue may not be integrated in the following
9769 * firmware version. So the workaround in software driver is needed. It needs
9770 * to modify the initial values of 3 internal only registers for both X710 and
9771 * XL710. Note that the values for X710 or XL710 could be different, and the
9772 * workaround can be removed when it is fixed in firmware in the future.
9775 /* For both X710 and XL710 */
9776 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9777 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9778 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9780 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9781 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9784 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9785 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9788 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9790 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9791 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9795 * The value is not impacted from the link speed, its value is set according
9796 * to the total number of ports for a better pipe-monitor configuration.
9799 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
9801 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
9802 .device_id = (dev), \
9803 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
9805 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
9806 .device_id = (dev), \
9807 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
9809 static const struct {
9812 } swr_pm_table[] = {
9813 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
9814 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
9815 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
9816 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
9818 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
9819 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
9820 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
9821 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
9822 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
9823 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
9824 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
9828 if (value == NULL) {
9829 PMD_DRV_LOG(ERR, "value is NULL");
9833 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
9834 if (hw->device_id == swr_pm_table[i].device_id) {
9835 *value = swr_pm_table[i].val;
9837 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
9839 hw->device_id, *value);
9848 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9850 enum i40e_status_code status;
9851 struct i40e_aq_get_phy_abilities_resp phy_ab;
9855 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9859 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9862 rte_delay_us(100000);
9864 status = i40e_aq_get_phy_capabilities(hw, false,
9865 true, &phy_ab, NULL);
9873 i40e_configure_registers(struct i40e_hw *hw)
9879 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9880 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9881 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9887 for (i = 0; i < RTE_DIM(reg_table); i++) {
9888 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9889 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9891 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9892 else /* For X710/XL710/XXV710 */
9893 if (hw->aq.fw_maj_ver < 6)
9895 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9898 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9901 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9902 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9904 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9905 else /* For X710/XL710/XXV710 */
9907 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9910 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9913 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
9914 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
9915 "GL_SWR_PM_UP_THR value fixup",
9920 reg_table[i].val = cfg_val;
9923 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9926 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9930 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9931 reg_table[i].addr, reg);
9932 if (reg == reg_table[i].val)
9935 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9936 reg_table[i].val, NULL);
9939 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9940 reg_table[i].val, reg_table[i].addr);
9943 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9944 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9948 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9949 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9950 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9951 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9953 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9958 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9959 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9963 /* Configure for double VLAN RX stripping */
9964 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9965 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9966 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9967 ret = i40e_aq_debug_write_register(hw,
9968 I40E_VSI_TSR(vsi->vsi_id),
9971 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9973 return I40E_ERR_CONFIG;
9977 /* Configure for double VLAN TX insertion */
9978 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9979 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9980 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9981 ret = i40e_aq_debug_write_register(hw,
9982 I40E_VSI_L2TAGSTXVALID(
9983 vsi->vsi_id), reg, NULL);
9986 "Failed to update VSI_L2TAGSTXVALID[%d]",
9988 return I40E_ERR_CONFIG;
9996 * i40e_aq_add_mirror_rule
9997 * @hw: pointer to the hardware structure
9998 * @seid: VEB seid to add mirror rule to
9999 * @dst_id: destination vsi seid
10000 * @entries: Buffer which contains the entities to be mirrored
10001 * @count: number of entities contained in the buffer
10002 * @rule_id:the rule_id of the rule to be added
10004 * Add a mirror rule for a given veb.
10007 static enum i40e_status_code
10008 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10009 uint16_t seid, uint16_t dst_id,
10010 uint16_t rule_type, uint16_t *entries,
10011 uint16_t count, uint16_t *rule_id)
10013 struct i40e_aq_desc desc;
10014 struct i40e_aqc_add_delete_mirror_rule cmd;
10015 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10016 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10019 enum i40e_status_code status;
10021 i40e_fill_default_direct_cmd_desc(&desc,
10022 i40e_aqc_opc_add_mirror_rule);
10023 memset(&cmd, 0, sizeof(cmd));
10025 buff_len = sizeof(uint16_t) * count;
10026 desc.datalen = rte_cpu_to_le_16(buff_len);
10028 desc.flags |= rte_cpu_to_le_16(
10029 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10030 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10031 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10032 cmd.num_entries = rte_cpu_to_le_16(count);
10033 cmd.seid = rte_cpu_to_le_16(seid);
10034 cmd.destination = rte_cpu_to_le_16(dst_id);
10036 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10037 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10039 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10040 hw->aq.asq_last_status, resp->rule_id,
10041 resp->mirror_rules_used, resp->mirror_rules_free);
10042 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10048 * i40e_aq_del_mirror_rule
10049 * @hw: pointer to the hardware structure
10050 * @seid: VEB seid to add mirror rule to
10051 * @entries: Buffer which contains the entities to be mirrored
10052 * @count: number of entities contained in the buffer
10053 * @rule_id:the rule_id of the rule to be delete
10055 * Delete a mirror rule for a given veb.
10058 static enum i40e_status_code
10059 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10060 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10061 uint16_t count, uint16_t rule_id)
10063 struct i40e_aq_desc desc;
10064 struct i40e_aqc_add_delete_mirror_rule cmd;
10065 uint16_t buff_len = 0;
10066 enum i40e_status_code status;
10069 i40e_fill_default_direct_cmd_desc(&desc,
10070 i40e_aqc_opc_delete_mirror_rule);
10071 memset(&cmd, 0, sizeof(cmd));
10072 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10073 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10075 cmd.num_entries = count;
10076 buff_len = sizeof(uint16_t) * count;
10077 desc.datalen = rte_cpu_to_le_16(buff_len);
10078 buff = (void *)entries;
10080 /* rule id is filled in destination field for deleting mirror rule */
10081 cmd.destination = rte_cpu_to_le_16(rule_id);
10083 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10084 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10085 cmd.seid = rte_cpu_to_le_16(seid);
10087 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10088 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10094 * i40e_mirror_rule_set
10095 * @dev: pointer to the hardware structure
10096 * @mirror_conf: mirror rule info
10097 * @sw_id: mirror rule's sw_id
10098 * @on: enable/disable
10100 * set a mirror rule.
10104 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10105 struct rte_eth_mirror_conf *mirror_conf,
10106 uint8_t sw_id, uint8_t on)
10108 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10109 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10110 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10111 struct i40e_mirror_rule *parent = NULL;
10112 uint16_t seid, dst_seid, rule_id;
10116 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10118 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10120 "mirror rule can not be configured without veb or vfs.");
10123 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10124 PMD_DRV_LOG(ERR, "mirror table is full.");
10127 if (mirror_conf->dst_pool > pf->vf_num) {
10128 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10129 mirror_conf->dst_pool);
10133 seid = pf->main_vsi->veb->seid;
10135 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10136 if (sw_id <= it->index) {
10142 if (mirr_rule && sw_id == mirr_rule->index) {
10144 PMD_DRV_LOG(ERR, "mirror rule exists.");
10147 ret = i40e_aq_del_mirror_rule(hw, seid,
10148 mirr_rule->rule_type,
10149 mirr_rule->entries,
10150 mirr_rule->num_entries, mirr_rule->id);
10153 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10154 ret, hw->aq.asq_last_status);
10157 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10158 rte_free(mirr_rule);
10159 pf->nb_mirror_rule--;
10163 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10167 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10168 sizeof(struct i40e_mirror_rule) , 0);
10170 PMD_DRV_LOG(ERR, "failed to allocate memory");
10171 return I40E_ERR_NO_MEMORY;
10173 switch (mirror_conf->rule_type) {
10174 case ETH_MIRROR_VLAN:
10175 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10176 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10177 mirr_rule->entries[j] =
10178 mirror_conf->vlan.vlan_id[i];
10183 PMD_DRV_LOG(ERR, "vlan is not specified.");
10184 rte_free(mirr_rule);
10187 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10189 case ETH_MIRROR_VIRTUAL_POOL_UP:
10190 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10191 /* check if the specified pool bit is out of range */
10192 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10193 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10194 rte_free(mirr_rule);
10197 for (i = 0, j = 0; i < pf->vf_num; i++) {
10198 if (mirror_conf->pool_mask & (1ULL << i)) {
10199 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10203 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10204 /* add pf vsi to entries */
10205 mirr_rule->entries[j] = pf->main_vsi_seid;
10209 PMD_DRV_LOG(ERR, "pool is not specified.");
10210 rte_free(mirr_rule);
10213 /* egress and ingress in aq commands means from switch but not port */
10214 mirr_rule->rule_type =
10215 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10216 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10217 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10219 case ETH_MIRROR_UPLINK_PORT:
10220 /* egress and ingress in aq commands means from switch but not port*/
10221 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10223 case ETH_MIRROR_DOWNLINK_PORT:
10224 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10227 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10228 mirror_conf->rule_type);
10229 rte_free(mirr_rule);
10233 /* If the dst_pool is equal to vf_num, consider it as PF */
10234 if (mirror_conf->dst_pool == pf->vf_num)
10235 dst_seid = pf->main_vsi_seid;
10237 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10239 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10240 mirr_rule->rule_type, mirr_rule->entries,
10244 "failed to add mirror rule: ret = %d, aq_err = %d.",
10245 ret, hw->aq.asq_last_status);
10246 rte_free(mirr_rule);
10250 mirr_rule->index = sw_id;
10251 mirr_rule->num_entries = j;
10252 mirr_rule->id = rule_id;
10253 mirr_rule->dst_vsi_seid = dst_seid;
10256 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10258 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10260 pf->nb_mirror_rule++;
10265 * i40e_mirror_rule_reset
10266 * @dev: pointer to the device
10267 * @sw_id: mirror rule's sw_id
10269 * reset a mirror rule.
10273 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10275 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10276 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10277 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10281 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10283 seid = pf->main_vsi->veb->seid;
10285 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10286 if (sw_id == it->index) {
10292 ret = i40e_aq_del_mirror_rule(hw, seid,
10293 mirr_rule->rule_type,
10294 mirr_rule->entries,
10295 mirr_rule->num_entries, mirr_rule->id);
10298 "failed to remove mirror rule: status = %d, aq_err = %d.",
10299 ret, hw->aq.asq_last_status);
10302 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10303 rte_free(mirr_rule);
10304 pf->nb_mirror_rule--;
10306 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10313 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10315 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10316 uint64_t systim_cycles;
10318 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10319 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10322 return systim_cycles;
10326 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10328 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10329 uint64_t rx_tstamp;
10331 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10332 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10339 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10342 uint64_t tx_tstamp;
10344 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10345 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10352 i40e_start_timecounters(struct rte_eth_dev *dev)
10354 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10355 struct i40e_adapter *adapter =
10356 (struct i40e_adapter *)dev->data->dev_private;
10357 struct rte_eth_link link;
10358 uint32_t tsync_inc_l;
10359 uint32_t tsync_inc_h;
10361 /* Get current link speed. */
10362 memset(&link, 0, sizeof(link));
10363 i40e_dev_link_update(dev, 1);
10364 rte_i40e_dev_atomic_read_link_status(dev, &link);
10366 switch (link.link_speed) {
10367 case ETH_SPEED_NUM_40G:
10368 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10369 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10371 case ETH_SPEED_NUM_10G:
10372 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10373 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10375 case ETH_SPEED_NUM_1G:
10376 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10377 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10384 /* Set the timesync increment value. */
10385 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10386 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10388 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10389 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10390 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10392 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10393 adapter->systime_tc.cc_shift = 0;
10394 adapter->systime_tc.nsec_mask = 0;
10396 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10397 adapter->rx_tstamp_tc.cc_shift = 0;
10398 adapter->rx_tstamp_tc.nsec_mask = 0;
10400 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10401 adapter->tx_tstamp_tc.cc_shift = 0;
10402 adapter->tx_tstamp_tc.nsec_mask = 0;
10406 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10408 struct i40e_adapter *adapter =
10409 (struct i40e_adapter *)dev->data->dev_private;
10411 adapter->systime_tc.nsec += delta;
10412 adapter->rx_tstamp_tc.nsec += delta;
10413 adapter->tx_tstamp_tc.nsec += delta;
10419 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10422 struct i40e_adapter *adapter =
10423 (struct i40e_adapter *)dev->data->dev_private;
10425 ns = rte_timespec_to_ns(ts);
10427 /* Set the timecounters to a new value. */
10428 adapter->systime_tc.nsec = ns;
10429 adapter->rx_tstamp_tc.nsec = ns;
10430 adapter->tx_tstamp_tc.nsec = ns;
10436 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10438 uint64_t ns, systime_cycles;
10439 struct i40e_adapter *adapter =
10440 (struct i40e_adapter *)dev->data->dev_private;
10442 systime_cycles = i40e_read_systime_cyclecounter(dev);
10443 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10444 *ts = rte_ns_to_timespec(ns);
10450 i40e_timesync_enable(struct rte_eth_dev *dev)
10452 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10453 uint32_t tsync_ctl_l;
10454 uint32_t tsync_ctl_h;
10456 /* Stop the timesync system time. */
10457 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10458 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10459 /* Reset the timesync system time value. */
10460 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10461 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10463 i40e_start_timecounters(dev);
10465 /* Clear timesync registers. */
10466 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10467 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10468 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10469 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10470 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10471 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10473 /* Enable timestamping of PTP packets. */
10474 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10475 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10477 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10478 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10479 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10481 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10482 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10488 i40e_timesync_disable(struct rte_eth_dev *dev)
10490 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10491 uint32_t tsync_ctl_l;
10492 uint32_t tsync_ctl_h;
10494 /* Disable timestamping of transmitted PTP packets. */
10495 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10496 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10498 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10499 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10501 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10502 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10504 /* Reset the timesync increment value. */
10505 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10506 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10512 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10513 struct timespec *timestamp, uint32_t flags)
10515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10516 struct i40e_adapter *adapter =
10517 (struct i40e_adapter *)dev->data->dev_private;
10519 uint32_t sync_status;
10520 uint32_t index = flags & 0x03;
10521 uint64_t rx_tstamp_cycles;
10524 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10525 if ((sync_status & (1 << index)) == 0)
10528 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10529 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10530 *timestamp = rte_ns_to_timespec(ns);
10536 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10537 struct timespec *timestamp)
10539 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10540 struct i40e_adapter *adapter =
10541 (struct i40e_adapter *)dev->data->dev_private;
10543 uint32_t sync_status;
10544 uint64_t tx_tstamp_cycles;
10547 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10548 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10551 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10552 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10553 *timestamp = rte_ns_to_timespec(ns);
10559 * i40e_parse_dcb_configure - parse dcb configure from user
10560 * @dev: the device being configured
10561 * @dcb_cfg: pointer of the result of parse
10562 * @*tc_map: bit map of enabled traffic classes
10564 * Returns 0 on success, negative value on failure
10567 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10568 struct i40e_dcbx_config *dcb_cfg,
10571 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10572 uint8_t i, tc_bw, bw_lf;
10574 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10576 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10577 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10578 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10582 /* assume each tc has the same bw */
10583 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10584 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10585 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10586 /* to ensure the sum of tcbw is equal to 100 */
10587 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10588 for (i = 0; i < bw_lf; i++)
10589 dcb_cfg->etscfg.tcbwtable[i]++;
10591 /* assume each tc has the same Transmission Selection Algorithm */
10592 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10593 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10595 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10596 dcb_cfg->etscfg.prioritytable[i] =
10597 dcb_rx_conf->dcb_tc[i];
10599 /* FW needs one App to configure HW */
10600 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10601 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10602 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10603 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10605 if (dcb_rx_conf->nb_tcs == 0)
10606 *tc_map = 1; /* tc0 only */
10608 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10610 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10611 dcb_cfg->pfc.willing = 0;
10612 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10613 dcb_cfg->pfc.pfcenable = *tc_map;
10619 static enum i40e_status_code
10620 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10621 struct i40e_aqc_vsi_properties_data *info,
10622 uint8_t enabled_tcmap)
10624 enum i40e_status_code ret;
10625 int i, total_tc = 0;
10626 uint16_t qpnum_per_tc, bsf, qp_idx;
10627 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10628 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10629 uint16_t used_queues;
10631 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10632 if (ret != I40E_SUCCESS)
10635 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10636 if (enabled_tcmap & (1 << i))
10641 vsi->enabled_tc = enabled_tcmap;
10643 /* different VSI has different queues assigned */
10644 if (vsi->type == I40E_VSI_MAIN)
10645 used_queues = dev_data->nb_rx_queues -
10646 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10647 else if (vsi->type == I40E_VSI_VMDQ2)
10648 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10650 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10651 return I40E_ERR_NO_AVAILABLE_VSI;
10654 qpnum_per_tc = used_queues / total_tc;
10655 /* Number of queues per enabled TC */
10656 if (qpnum_per_tc == 0) {
10657 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10658 return I40E_ERR_INVALID_QP_ID;
10660 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10661 I40E_MAX_Q_PER_TC);
10662 bsf = rte_bsf32(qpnum_per_tc);
10665 * Configure TC and queue mapping parameters, for enabled TC,
10666 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10667 * default queue will serve it.
10670 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10671 if (vsi->enabled_tc & (1 << i)) {
10672 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10673 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10674 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10675 qp_idx += qpnum_per_tc;
10677 info->tc_mapping[i] = 0;
10680 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10681 if (vsi->type == I40E_VSI_SRIOV) {
10682 info->mapping_flags |=
10683 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10684 for (i = 0; i < vsi->nb_qps; i++)
10685 info->queue_mapping[i] =
10686 rte_cpu_to_le_16(vsi->base_queue + i);
10688 info->mapping_flags |=
10689 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10690 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10692 info->valid_sections |=
10693 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10695 return I40E_SUCCESS;
10699 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10700 * @veb: VEB to be configured
10701 * @tc_map: enabled TC bitmap
10703 * Returns 0 on success, negative value on failure
10705 static enum i40e_status_code
10706 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10708 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10709 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10710 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10711 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10712 enum i40e_status_code ret = I40E_SUCCESS;
10716 /* Check if enabled_tc is same as existing or new TCs */
10717 if (veb->enabled_tc == tc_map)
10720 /* configure tc bandwidth */
10721 memset(&veb_bw, 0, sizeof(veb_bw));
10722 veb_bw.tc_valid_bits = tc_map;
10723 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10724 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10725 if (tc_map & BIT_ULL(i))
10726 veb_bw.tc_bw_share_credits[i] = 1;
10728 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10732 "AQ command Config switch_comp BW allocation per TC failed = %d",
10733 hw->aq.asq_last_status);
10737 memset(&ets_query, 0, sizeof(ets_query));
10738 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10740 if (ret != I40E_SUCCESS) {
10742 "Failed to get switch_comp ETS configuration %u",
10743 hw->aq.asq_last_status);
10746 memset(&bw_query, 0, sizeof(bw_query));
10747 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10749 if (ret != I40E_SUCCESS) {
10751 "Failed to get switch_comp bandwidth configuration %u",
10752 hw->aq.asq_last_status);
10756 /* store and print out BW info */
10757 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10758 veb->bw_info.bw_max = ets_query.tc_bw_max;
10759 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10760 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10761 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10762 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10763 I40E_16_BIT_WIDTH);
10764 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10765 veb->bw_info.bw_ets_share_credits[i] =
10766 bw_query.tc_bw_share_credits[i];
10767 veb->bw_info.bw_ets_credits[i] =
10768 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10769 /* 4 bits per TC, 4th bit is reserved */
10770 veb->bw_info.bw_ets_max[i] =
10771 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10772 RTE_LEN2MASK(3, uint8_t));
10773 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10774 veb->bw_info.bw_ets_share_credits[i]);
10775 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10776 veb->bw_info.bw_ets_credits[i]);
10777 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10778 veb->bw_info.bw_ets_max[i]);
10781 veb->enabled_tc = tc_map;
10788 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10789 * @vsi: VSI to be configured
10790 * @tc_map: enabled TC bitmap
10792 * Returns 0 on success, negative value on failure
10794 static enum i40e_status_code
10795 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10797 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10798 struct i40e_vsi_context ctxt;
10799 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10800 enum i40e_status_code ret = I40E_SUCCESS;
10803 /* Check if enabled_tc is same as existing or new TCs */
10804 if (vsi->enabled_tc == tc_map)
10807 /* configure tc bandwidth */
10808 memset(&bw_data, 0, sizeof(bw_data));
10809 bw_data.tc_valid_bits = tc_map;
10810 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10811 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10812 if (tc_map & BIT_ULL(i))
10813 bw_data.tc_bw_credits[i] = 1;
10815 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10818 "AQ command Config VSI BW allocation per TC failed = %d",
10819 hw->aq.asq_last_status);
10822 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10823 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10825 /* Update Queue Pairs Mapping for currently enabled UPs */
10826 ctxt.seid = vsi->seid;
10827 ctxt.pf_num = hw->pf_id;
10829 ctxt.uplink_seid = vsi->uplink_seid;
10830 ctxt.info = vsi->info;
10832 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10836 /* Update the VSI after updating the VSI queue-mapping information */
10837 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10839 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10840 hw->aq.asq_last_status);
10843 /* update the local VSI info with updated queue map */
10844 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10845 sizeof(vsi->info.tc_mapping));
10846 rte_memcpy(&vsi->info.queue_mapping,
10847 &ctxt.info.queue_mapping,
10848 sizeof(vsi->info.queue_mapping));
10849 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10850 vsi->info.valid_sections = 0;
10852 /* query and update current VSI BW information */
10853 ret = i40e_vsi_get_bw_config(vsi);
10856 "Failed updating vsi bw info, err %s aq_err %s",
10857 i40e_stat_str(hw, ret),
10858 i40e_aq_str(hw, hw->aq.asq_last_status));
10862 vsi->enabled_tc = tc_map;
10869 * i40e_dcb_hw_configure - program the dcb setting to hw
10870 * @pf: pf the configuration is taken on
10871 * @new_cfg: new configuration
10872 * @tc_map: enabled TC bitmap
10874 * Returns 0 on success, negative value on failure
10876 static enum i40e_status_code
10877 i40e_dcb_hw_configure(struct i40e_pf *pf,
10878 struct i40e_dcbx_config *new_cfg,
10881 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10882 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10883 struct i40e_vsi *main_vsi = pf->main_vsi;
10884 struct i40e_vsi_list *vsi_list;
10885 enum i40e_status_code ret;
10889 /* Use the FW API if FW > v4.4*/
10890 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10891 (hw->aq.fw_maj_ver >= 5))) {
10893 "FW < v4.4, can not use FW LLDP API to configure DCB");
10894 return I40E_ERR_FIRMWARE_API_VERSION;
10897 /* Check if need reconfiguration */
10898 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10899 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10900 return I40E_SUCCESS;
10903 /* Copy the new config to the current config */
10904 *old_cfg = *new_cfg;
10905 old_cfg->etsrec = old_cfg->etscfg;
10906 ret = i40e_set_dcb_config(hw);
10908 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10909 i40e_stat_str(hw, ret),
10910 i40e_aq_str(hw, hw->aq.asq_last_status));
10913 /* set receive Arbiter to RR mode and ETS scheme by default */
10914 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10915 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10916 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10917 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10918 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10919 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10920 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10921 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10922 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10923 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10924 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10925 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10926 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10928 /* get local mib to check whether it is configured correctly */
10930 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10931 /* Get Local DCB Config */
10932 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10933 &hw->local_dcbx_config);
10935 /* if Veb is created, need to update TC of it at first */
10936 if (main_vsi->veb) {
10937 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10939 PMD_INIT_LOG(WARNING,
10940 "Failed configuring TC for VEB seid=%d",
10941 main_vsi->veb->seid);
10943 /* Update each VSI */
10944 i40e_vsi_config_tc(main_vsi, tc_map);
10945 if (main_vsi->veb) {
10946 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10947 /* Beside main VSI and VMDQ VSIs, only enable default
10948 * TC for other VSIs
10950 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10951 ret = i40e_vsi_config_tc(vsi_list->vsi,
10954 ret = i40e_vsi_config_tc(vsi_list->vsi,
10955 I40E_DEFAULT_TCMAP);
10957 PMD_INIT_LOG(WARNING,
10958 "Failed configuring TC for VSI seid=%d",
10959 vsi_list->vsi->seid);
10963 return I40E_SUCCESS;
10967 * i40e_dcb_init_configure - initial dcb config
10968 * @dev: device being configured
10969 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10971 * Returns 0 on success, negative value on failure
10974 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10976 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10977 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10980 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10981 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10985 /* DCB initialization:
10986 * Update DCB configuration from the Firmware and configure
10987 * LLDP MIB change event.
10989 if (sw_dcb == TRUE) {
10990 ret = i40e_init_dcb(hw);
10991 /* If lldp agent is stopped, the return value from
10992 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10993 * adminq status. Otherwise, it should return success.
10995 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10996 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10997 memset(&hw->local_dcbx_config, 0,
10998 sizeof(struct i40e_dcbx_config));
10999 /* set dcb default configuration */
11000 hw->local_dcbx_config.etscfg.willing = 0;
11001 hw->local_dcbx_config.etscfg.maxtcs = 0;
11002 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11003 hw->local_dcbx_config.etscfg.tsatable[0] =
11005 /* all UPs mapping to TC0 */
11006 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11007 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11008 hw->local_dcbx_config.etsrec =
11009 hw->local_dcbx_config.etscfg;
11010 hw->local_dcbx_config.pfc.willing = 0;
11011 hw->local_dcbx_config.pfc.pfccap =
11012 I40E_MAX_TRAFFIC_CLASS;
11013 /* FW needs one App to configure HW */
11014 hw->local_dcbx_config.numapps = 1;
11015 hw->local_dcbx_config.app[0].selector =
11016 I40E_APP_SEL_ETHTYPE;
11017 hw->local_dcbx_config.app[0].priority = 3;
11018 hw->local_dcbx_config.app[0].protocolid =
11019 I40E_APP_PROTOID_FCOE;
11020 ret = i40e_set_dcb_config(hw);
11023 "default dcb config fails. err = %d, aq_err = %d.",
11024 ret, hw->aq.asq_last_status);
11029 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11030 ret, hw->aq.asq_last_status);
11034 ret = i40e_aq_start_lldp(hw, NULL);
11035 if (ret != I40E_SUCCESS)
11036 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11038 ret = i40e_init_dcb(hw);
11040 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11042 "HW doesn't support DCBX offload.");
11047 "DCBX configuration failed, err = %d, aq_err = %d.",
11048 ret, hw->aq.asq_last_status);
11056 * i40e_dcb_setup - setup dcb related config
11057 * @dev: device being configured
11059 * Returns 0 on success, negative value on failure
11062 i40e_dcb_setup(struct rte_eth_dev *dev)
11064 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11065 struct i40e_dcbx_config dcb_cfg;
11066 uint8_t tc_map = 0;
11069 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11070 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11074 if (pf->vf_num != 0)
11075 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11077 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11079 PMD_INIT_LOG(ERR, "invalid dcb config");
11082 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11084 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11092 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11093 struct rte_eth_dcb_info *dcb_info)
11095 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11096 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11097 struct i40e_vsi *vsi = pf->main_vsi;
11098 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11099 uint16_t bsf, tc_mapping;
11102 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11103 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11105 dcb_info->nb_tcs = 1;
11106 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11107 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11108 for (i = 0; i < dcb_info->nb_tcs; i++)
11109 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11111 /* get queue mapping if vmdq is disabled */
11112 if (!pf->nb_cfg_vmdq_vsi) {
11113 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11114 if (!(vsi->enabled_tc & (1 << i)))
11116 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11117 dcb_info->tc_queue.tc_rxq[j][i].base =
11118 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11119 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11120 dcb_info->tc_queue.tc_txq[j][i].base =
11121 dcb_info->tc_queue.tc_rxq[j][i].base;
11122 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11123 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11124 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11125 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11126 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11131 /* get queue mapping if vmdq is enabled */
11133 vsi = pf->vmdq[j].vsi;
11134 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11135 if (!(vsi->enabled_tc & (1 << i)))
11137 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11138 dcb_info->tc_queue.tc_rxq[j][i].base =
11139 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11140 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11141 dcb_info->tc_queue.tc_txq[j][i].base =
11142 dcb_info->tc_queue.tc_rxq[j][i].base;
11143 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11144 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11145 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11146 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11147 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11150 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11155 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11157 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11158 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11159 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11160 uint16_t msix_intr;
11162 msix_intr = intr_handle->intr_vec[queue_id];
11163 if (msix_intr == I40E_MISC_VEC_ID)
11164 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11165 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11166 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11167 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11170 I40E_PFINT_DYN_CTLN(msix_intr -
11171 I40E_RX_VEC_START),
11172 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11173 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11174 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11176 I40E_WRITE_FLUSH(hw);
11177 rte_intr_enable(&pci_dev->intr_handle);
11183 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11185 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11186 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11188 uint16_t msix_intr;
11190 msix_intr = intr_handle->intr_vec[queue_id];
11191 if (msix_intr == I40E_MISC_VEC_ID)
11192 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11193 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11196 I40E_PFINT_DYN_CTLN(msix_intr -
11197 I40E_RX_VEC_START),
11198 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11199 I40E_WRITE_FLUSH(hw);
11204 static int i40e_get_regs(struct rte_eth_dev *dev,
11205 struct rte_dev_reg_info *regs)
11207 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11208 uint32_t *ptr_data = regs->data;
11209 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11210 const struct i40e_reg_info *reg_info;
11212 if (ptr_data == NULL) {
11213 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11214 regs->width = sizeof(uint32_t);
11218 /* The first few registers have to be read using AQ operations */
11220 while (i40e_regs_adminq[reg_idx].name) {
11221 reg_info = &i40e_regs_adminq[reg_idx++];
11222 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11224 arr_idx2 <= reg_info->count2;
11226 reg_offset = arr_idx * reg_info->stride1 +
11227 arr_idx2 * reg_info->stride2;
11228 reg_offset += reg_info->base_addr;
11229 ptr_data[reg_offset >> 2] =
11230 i40e_read_rx_ctl(hw, reg_offset);
11234 /* The remaining registers can be read using primitives */
11236 while (i40e_regs_others[reg_idx].name) {
11237 reg_info = &i40e_regs_others[reg_idx++];
11238 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11240 arr_idx2 <= reg_info->count2;
11242 reg_offset = arr_idx * reg_info->stride1 +
11243 arr_idx2 * reg_info->stride2;
11244 reg_offset += reg_info->base_addr;
11245 ptr_data[reg_offset >> 2] =
11246 I40E_READ_REG(hw, reg_offset);
11253 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11257 /* Convert word count to byte count */
11258 return hw->nvm.sr_size << 1;
11261 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11262 struct rte_dev_eeprom_info *eeprom)
11264 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11265 uint16_t *data = eeprom->data;
11266 uint16_t offset, length, cnt_words;
11269 offset = eeprom->offset >> 1;
11270 length = eeprom->length >> 1;
11271 cnt_words = length;
11273 if (offset > hw->nvm.sr_size ||
11274 offset + length > hw->nvm.sr_size) {
11275 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11279 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11281 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11282 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11283 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11290 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11291 struct ether_addr *mac_addr)
11293 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11294 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11295 struct i40e_vsi *vsi = pf->main_vsi;
11296 struct i40e_mac_filter_info mac_filter;
11297 struct i40e_mac_filter *f;
11300 if (!is_valid_assigned_ether_addr(mac_addr)) {
11301 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11305 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11306 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11311 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11315 mac_filter = f->mac_info;
11316 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11317 if (ret != I40E_SUCCESS) {
11318 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11321 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11322 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11323 if (ret != I40E_SUCCESS) {
11324 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11327 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11329 i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11330 mac_addr->addr_bytes, NULL);
11334 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11336 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11337 struct rte_eth_dev_data *dev_data = pf->dev_data;
11338 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11341 /* check if mtu is within the allowed range */
11342 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11345 /* mtu setting is forbidden if port is start */
11346 if (dev_data->dev_started) {
11347 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11348 dev_data->port_id);
11352 if (frame_size > ETHER_MAX_LEN)
11353 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11355 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11357 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11362 /* Restore ethertype filter */
11364 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11366 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11367 struct i40e_ethertype_filter_list
11368 *ethertype_list = &pf->ethertype.ethertype_list;
11369 struct i40e_ethertype_filter *f;
11370 struct i40e_control_filter_stats stats;
11373 TAILQ_FOREACH(f, ethertype_list, rules) {
11375 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11376 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11377 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11378 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11379 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11381 memset(&stats, 0, sizeof(stats));
11382 i40e_aq_add_rem_control_packet_filter(hw,
11383 f->input.mac_addr.addr_bytes,
11384 f->input.ether_type,
11385 flags, pf->main_vsi->seid,
11386 f->queue, 1, &stats, NULL);
11388 PMD_DRV_LOG(INFO, "Ethertype filter:"
11389 " mac_etype_used = %u, etype_used = %u,"
11390 " mac_etype_free = %u, etype_free = %u",
11391 stats.mac_etype_used, stats.etype_used,
11392 stats.mac_etype_free, stats.etype_free);
11395 /* Restore tunnel filter */
11397 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11399 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11400 struct i40e_vsi *vsi;
11401 struct i40e_pf_vf *vf;
11402 struct i40e_tunnel_filter_list
11403 *tunnel_list = &pf->tunnel.tunnel_list;
11404 struct i40e_tunnel_filter *f;
11405 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11406 bool big_buffer = 0;
11408 TAILQ_FOREACH(f, tunnel_list, rules) {
11410 vsi = pf->main_vsi;
11412 vf = &pf->vfs[f->vf_id];
11415 memset(&cld_filter, 0, sizeof(cld_filter));
11416 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11417 (struct ether_addr *)&cld_filter.element.outer_mac);
11418 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11419 (struct ether_addr *)&cld_filter.element.inner_mac);
11420 cld_filter.element.inner_vlan = f->input.inner_vlan;
11421 cld_filter.element.flags = f->input.flags;
11422 cld_filter.element.tenant_id = f->input.tenant_id;
11423 cld_filter.element.queue_number = f->queue;
11424 rte_memcpy(cld_filter.general_fields,
11425 f->input.general_fields,
11426 sizeof(f->input.general_fields));
11428 if (((f->input.flags &
11429 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11430 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11432 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11433 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11435 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11436 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11440 i40e_aq_add_cloud_filters_big_buffer(hw,
11441 vsi->seid, &cld_filter, 1);
11443 i40e_aq_add_cloud_filters(hw, vsi->seid,
11444 &cld_filter.element, 1);
11449 i40e_filter_restore(struct i40e_pf *pf)
11451 i40e_ethertype_filter_restore(pf);
11452 i40e_tunnel_filter_restore(pf);
11453 i40e_fdir_filter_restore(pf);
11457 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11459 if (strcmp(dev->device->driver->name, drv->driver.name))
11466 is_i40e_supported(struct rte_eth_dev *dev)
11468 return is_device_supported(dev, &rte_i40e_pmd);
11471 struct i40e_customized_pctype*
11472 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11476 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11477 if (pf->customized_pctype[i].index == index)
11478 return &pf->customized_pctype[i];
11484 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11485 uint32_t pkg_size, uint32_t proto_num,
11486 struct rte_pmd_i40e_proto_info *proto,
11487 enum rte_pmd_i40e_package_op op)
11489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11490 uint32_t pctype_num;
11491 struct rte_pmd_i40e_ptype_info *pctype;
11492 uint32_t buff_size;
11493 struct i40e_customized_pctype *new_pctype = NULL;
11495 uint8_t pctype_value;
11500 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11501 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11502 PMD_DRV_LOG(ERR, "Unsupported operation.");
11506 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11507 (uint8_t *)&pctype_num, sizeof(pctype_num),
11508 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11510 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11514 PMD_DRV_LOG(INFO, "No new pctype added");
11518 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11519 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11521 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11524 /* get information about new pctype list */
11525 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11526 (uint8_t *)pctype, buff_size,
11527 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11529 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11534 /* Update customized pctype. */
11535 for (i = 0; i < pctype_num; i++) {
11536 pctype_value = pctype[i].ptype_id;
11537 memset(name, 0, sizeof(name));
11538 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11539 proto_id = pctype[i].protocols[j];
11540 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11542 for (n = 0; n < proto_num; n++) {
11543 if (proto[n].proto_id != proto_id)
11545 strcat(name, proto[n].name);
11550 name[strlen(name) - 1] = '\0';
11551 if (!strcmp(name, "GTPC"))
11553 i40e_find_customized_pctype(pf,
11554 I40E_CUSTOMIZED_GTPC);
11555 else if (!strcmp(name, "GTPU_IPV4"))
11557 i40e_find_customized_pctype(pf,
11558 I40E_CUSTOMIZED_GTPU_IPV4);
11559 else if (!strcmp(name, "GTPU_IPV6"))
11561 i40e_find_customized_pctype(pf,
11562 I40E_CUSTOMIZED_GTPU_IPV6);
11563 else if (!strcmp(name, "GTPU"))
11565 i40e_find_customized_pctype(pf,
11566 I40E_CUSTOMIZED_GTPU);
11568 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11569 new_pctype->pctype = pctype_value;
11570 new_pctype->valid = true;
11572 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11573 new_pctype->valid = false;
11583 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11584 uint32_t pkg_size, uint32_t proto_num,
11585 struct rte_pmd_i40e_proto_info *proto,
11586 enum rte_pmd_i40e_package_op op)
11588 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11589 uint16_t port_id = dev->data->port_id;
11590 uint32_t ptype_num;
11591 struct rte_pmd_i40e_ptype_info *ptype;
11592 uint32_t buff_size;
11594 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11599 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11600 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11601 PMD_DRV_LOG(ERR, "Unsupported operation.");
11605 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11606 rte_pmd_i40e_ptype_mapping_reset(port_id);
11610 /* get information about new ptype num */
11611 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11612 (uint8_t *)&ptype_num, sizeof(ptype_num),
11613 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11615 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11619 PMD_DRV_LOG(INFO, "No new ptype added");
11623 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11624 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11626 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11630 /* get information about new ptype list */
11631 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11632 (uint8_t *)ptype, buff_size,
11633 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11635 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11640 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11641 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11642 if (!ptype_mapping) {
11643 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11648 /* Update ptype mapping table. */
11649 for (i = 0; i < ptype_num; i++) {
11650 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11651 ptype_mapping[i].sw_ptype = 0;
11653 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11654 proto_id = ptype[i].protocols[j];
11655 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11657 for (n = 0; n < proto_num; n++) {
11658 if (proto[n].proto_id != proto_id)
11660 memset(name, 0, sizeof(name));
11661 strcpy(name, proto[n].name);
11662 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11663 ptype_mapping[i].sw_ptype |=
11664 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11666 } else if (!strncmp(name, "IPV4FRAG", 8) &&
11668 ptype_mapping[i].sw_ptype |=
11669 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11670 ptype_mapping[i].sw_ptype |=
11671 RTE_PTYPE_INNER_L4_FRAG;
11672 } else if (!strncmp(name, "IPV4", 4) &&
11674 ptype_mapping[i].sw_ptype |=
11675 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11676 else if (!strncmp(name, "IPV6", 4) &&
11678 ptype_mapping[i].sw_ptype |=
11679 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11681 } else if (!strncmp(name, "IPV6FRAG", 8) &&
11683 ptype_mapping[i].sw_ptype |=
11684 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11685 ptype_mapping[i].sw_ptype |=
11686 RTE_PTYPE_INNER_L4_FRAG;
11687 } else if (!strncmp(name, "IPV6", 4) &&
11689 ptype_mapping[i].sw_ptype |=
11690 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11691 else if (!strncmp(name, "GTPC", 4))
11692 ptype_mapping[i].sw_ptype |=
11693 RTE_PTYPE_TUNNEL_GTPC;
11694 else if (!strncmp(name, "GTPU", 4))
11695 ptype_mapping[i].sw_ptype |=
11696 RTE_PTYPE_TUNNEL_GTPU;
11697 else if (!strncmp(name, "UDP", 3))
11698 ptype_mapping[i].sw_ptype |=
11699 RTE_PTYPE_INNER_L4_UDP;
11700 else if (!strncmp(name, "TCP", 3))
11701 ptype_mapping[i].sw_ptype |=
11702 RTE_PTYPE_INNER_L4_TCP;
11703 else if (!strncmp(name, "SCTP", 4))
11704 ptype_mapping[i].sw_ptype |=
11705 RTE_PTYPE_INNER_L4_SCTP;
11706 else if (!strncmp(name, "ICMP", 4) ||
11707 !strncmp(name, "ICMPV6", 6))
11708 ptype_mapping[i].sw_ptype |=
11709 RTE_PTYPE_INNER_L4_ICMP;
11716 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11719 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11721 rte_free(ptype_mapping);
11727 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11728 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11731 uint32_t proto_num;
11732 struct rte_pmd_i40e_proto_info *proto;
11733 uint32_t buff_size;
11737 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11738 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11739 PMD_DRV_LOG(ERR, "Unsupported operation.");
11743 /* get information about protocol number */
11744 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11745 (uint8_t *)&proto_num, sizeof(proto_num),
11746 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11748 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11752 PMD_DRV_LOG(INFO, "No new protocol added");
11756 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11757 proto = rte_zmalloc("new_proto", buff_size, 0);
11759 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11763 /* get information about protocol list */
11764 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11765 (uint8_t *)proto, buff_size,
11766 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11768 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11773 /* Check if GTP is supported. */
11774 for (i = 0; i < proto_num; i++) {
11775 if (!strncmp(proto[i].name, "GTP", 3)) {
11776 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11777 pf->gtp_support = true;
11779 pf->gtp_support = false;
11784 /* Update customized pctype info */
11785 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11786 proto_num, proto, op);
11788 PMD_DRV_LOG(INFO, "No pctype is updated.");
11790 /* Update customized ptype info */
11791 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11792 proto_num, proto, op);
11794 PMD_DRV_LOG(INFO, "No ptype is updated.");
11799 /* Create a QinQ cloud filter
11801 * The Fortville NIC has limited resources for tunnel filters,
11802 * so we can only reuse existing filters.
11804 * In step 1 we define which Field Vector fields can be used for
11806 * As we do not have the inner tag defined as a field,
11807 * we have to define it first, by reusing one of L1 entries.
11809 * In step 2 we are replacing one of existing filter types with
11810 * a new one for QinQ.
11811 * As we reusing L1 and replacing L2, some of the default filter
11812 * types will disappear,which depends on L1 and L2 entries we reuse.
11814 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11816 * 1. Create L1 filter of outer vlan (12b) which will be in use
11817 * later when we define the cloud filter.
11818 * a. Valid_flags.replace_cloud = 0
11819 * b. Old_filter = 10 (Stag_Inner_Vlan)
11820 * c. New_filter = 0x10
11821 * d. TR bit = 0xff (optional, not used here)
11822 * e. Buffer – 2 entries:
11823 * i. Byte 0 = 8 (outer vlan FV index).
11825 * Byte 2-3 = 0x0fff
11826 * ii. Byte 0 = 37 (inner vlan FV index).
11828 * Byte 2-3 = 0x0fff
11831 * 2. Create cloud filter using two L1 filters entries: stag and
11832 * new filter(outer vlan+ inner vlan)
11833 * a. Valid_flags.replace_cloud = 1
11834 * b. Old_filter = 1 (instead of outer IP)
11835 * c. New_filter = 0x10
11836 * d. Buffer – 2 entries:
11837 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11838 * Byte 1-3 = 0 (rsv)
11839 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11840 * Byte 9-11 = 0 (rsv)
11843 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11845 int ret = -ENOTSUP;
11846 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11847 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11848 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11850 if (pf->support_multi_driver) {
11851 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11856 memset(&filter_replace, 0,
11857 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11858 memset(&filter_replace_buf, 0,
11859 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11861 /* create L1 filter */
11862 filter_replace.old_filter_type =
11863 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11864 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11865 filter_replace.tr_bit = 0;
11867 /* Prepare the buffer, 2 entries */
11868 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11869 filter_replace_buf.data[0] |=
11870 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11871 /* Field Vector 12b mask */
11872 filter_replace_buf.data[2] = 0xff;
11873 filter_replace_buf.data[3] = 0x0f;
11874 filter_replace_buf.data[4] =
11875 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11876 filter_replace_buf.data[4] |=
11877 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11878 /* Field Vector 12b mask */
11879 filter_replace_buf.data[6] = 0xff;
11880 filter_replace_buf.data[7] = 0x0f;
11881 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11882 &filter_replace_buf);
11883 if (ret != I40E_SUCCESS)
11885 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11886 "cloud l1 type is changed from 0x%x to 0x%x",
11887 filter_replace.old_filter_type,
11888 filter_replace.new_filter_type);
11890 /* Apply the second L2 cloud filter */
11891 memset(&filter_replace, 0,
11892 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11893 memset(&filter_replace_buf, 0,
11894 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11896 /* create L2 filter, input for L2 filter will be L1 filter */
11897 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11898 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11899 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11901 /* Prepare the buffer, 2 entries */
11902 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11903 filter_replace_buf.data[0] |=
11904 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11905 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11906 filter_replace_buf.data[4] |=
11907 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11908 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11909 &filter_replace_buf);
11911 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11912 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11913 "cloud filter type is changed from 0x%x to 0x%x",
11914 filter_replace.old_filter_type,
11915 filter_replace.new_filter_type);
11920 RTE_INIT(i40e_init_log);
11922 i40e_init_log(void)
11924 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11925 if (i40e_logtype_init >= 0)
11926 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11927 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11928 if (i40e_logtype_driver >= 0)
11929 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11932 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
11933 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");