drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control enable fwd bit */
  87 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  88
  89 /* Receive Packet Buffer size */
  90 #define I40E_RXPBSIZE (968 * 1024)
  91
  92 /* Kilobytes shift */
  93 #define I40E_KILOSHIFT 10
  94
  95 /* Flow control default high water */
  96 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  97
  98 /* Flow control default low water */
  99 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(
 377                 __rte_unused struct rte_intr_handle *handle, void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 426                                                      uint16_t seid,
 427                                                      uint16_t rule_type,
 428                                                      uint16_t *entries,
 429                                                      uint16_t count,
 430                                                      uint16_t rule_id);
 431 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 432                         struct rte_eth_mirror_conf *mirror_conf,
 433                         uint8_t sw_id, uint8_t on);
 434 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 435
 436 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 437 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 438 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 439                                            struct timespec *timestamp,
 440                                            uint32_t flags);
 441 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 442                                            struct timespec *timestamp);
 443 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 444
 445 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 446
 447 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 448                                    struct timespec *timestamp);
 449 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 450                                     const struct timespec *timestamp);
 451
 452 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 453                                          uint16_t queue_id);
 454 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 455                                           uint16_t queue_id);
 456
 457 static int i40e_get_regs(struct rte_eth_dev *dev,
 458                          struct rte_dev_reg_info *regs);
 459
 460 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 461
 462 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 463                            struct rte_dev_eeprom_info *eeprom);
 464
 465 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 466                                       struct ether_addr *mac_addr);
 467
 468 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 469 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 470
 471 static const struct rte_pci_id pci_id_i40e_map[] = {
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 486         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 487         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 488         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 489         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 490         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 491         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 492         { .vendor_id = 0, /* sentinel */ },
 493 };
 494
 495 static const struct eth_dev_ops i40e_eth_dev_ops = {
 496         .dev_configure                = i40e_dev_configure,
 497         .dev_start                    = i40e_dev_start,
 498         .dev_stop                     = i40e_dev_stop,
 499         .dev_close                    = i40e_dev_close,
 500         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 501         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 502         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 503         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 504         .dev_set_link_up              = i40e_dev_set_link_up,
 505         .dev_set_link_down            = i40e_dev_set_link_down,
 506         .link_update                  = i40e_dev_link_update,
 507         .stats_get                    = i40e_dev_stats_get,
 508         .xstats_get                   = i40e_dev_xstats_get,
 509         .xstats_get_names             = i40e_dev_xstats_get_names,
 510         .stats_reset                  = i40e_dev_stats_reset,
 511         .xstats_reset                 = i40e_dev_stats_reset,
 512         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 513         .dev_infos_get                = i40e_dev_info_get,
 514         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 515         .vlan_filter_set              = i40e_vlan_filter_set,
 516         .vlan_tpid_set                = i40e_vlan_tpid_set,
 517         .vlan_offload_set             = i40e_vlan_offload_set,
 518         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 519         .vlan_pvid_set                = i40e_vlan_pvid_set,
 520         .rx_queue_start               = i40e_dev_rx_queue_start,
 521         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 522         .tx_queue_start               = i40e_dev_tx_queue_start,
 523         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 524         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 525         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 526         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 527         .rx_queue_release             = i40e_dev_rx_queue_release,
 528         .rx_queue_count               = i40e_dev_rx_queue_count,
 529         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 530         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 531         .tx_queue_release             = i40e_dev_tx_queue_release,
 532         .dev_led_on                   = i40e_dev_led_on,
 533         .dev_led_off                  = i40e_dev_led_off,
 534         .flow_ctrl_get                = i40e_flow_ctrl_get,
 535         .flow_ctrl_set                = i40e_flow_ctrl_set,
 536         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 537         .mac_addr_add                 = i40e_macaddr_add,
 538         .mac_addr_remove              = i40e_macaddr_remove,
 539         .reta_update                  = i40e_dev_rss_reta_update,
 540         .reta_query                   = i40e_dev_rss_reta_query,
 541         .rss_hash_update              = i40e_dev_rss_hash_update,
 542         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 543         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 544         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 545         .filter_ctrl                  = i40e_dev_filter_ctrl,
 546         .rxq_info_get                 = i40e_rxq_info_get,
 547         .txq_info_get                 = i40e_txq_info_get,
 548         .mirror_rule_set              = i40e_mirror_rule_set,
 549         .mirror_rule_reset            = i40e_mirror_rule_reset,
 550         .timesync_enable              = i40e_timesync_enable,
 551         .timesync_disable             = i40e_timesync_disable,
 552         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 553         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 554         .get_dcb_info                 = i40e_dev_get_dcb_info,
 555         .timesync_adjust_time         = i40e_timesync_adjust_time,
 556         .timesync_read_time           = i40e_timesync_read_time,
 557         .timesync_write_time          = i40e_timesync_write_time,
 558         .get_reg                      = i40e_get_regs,
 559         .get_eeprom_length            = i40e_get_eeprom_length,
 560         .get_eeprom                   = i40e_get_eeprom,
 561         .mac_addr_set                 = i40e_set_default_mac_addr,
 562         .mtu_set                      = i40e_dev_mtu_set,
 563 };
 564
 565 /* store statistics names and its offset in stats structure */
 566 struct rte_i40e_xstats_name_off {
 567         char name[RTE_ETH_XSTATS_NAME_SIZE];
 568         unsigned offset;
 569 };
 570
 571 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 572         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 573         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 574         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 575         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 576         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 577                 rx_unknown_protocol)},
 578         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 579         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 580         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 581         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 582 };
 583
 584 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 585                 sizeof(rte_i40e_stats_strings[0]))
 586
 587 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 588         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 589                 tx_dropped_link_down)},
 590         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 591         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 592                 illegal_bytes)},
 593         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 594         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 595                 mac_local_faults)},
 596         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 597                 mac_remote_faults)},
 598         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 599                 rx_length_errors)},
 600         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 601         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 602         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 603         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 604         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 605         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 606                 rx_size_127)},
 607         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 608                 rx_size_255)},
 609         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 610                 rx_size_511)},
 611         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 612                 rx_size_1023)},
 613         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 614                 rx_size_1522)},
 615         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 616                 rx_size_big)},
 617         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 618                 rx_undersize)},
 619         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 620                 rx_oversize)},
 621         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 622                 mac_short_packet_dropped)},
 623         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 624                 rx_fragments)},
 625         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 626         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 627         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 628                 tx_size_127)},
 629         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 630                 tx_size_255)},
 631         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 632                 tx_size_511)},
 633         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 634                 tx_size_1023)},
 635         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 636                 tx_size_1522)},
 637         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 638                 tx_size_big)},
 639         {"rx_flow_director_atr_match_packets",
 640                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 641         {"rx_flow_director_sb_match_packets",
 642                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 643         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 644                 tx_lpi_status)},
 645         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 646                 rx_lpi_status)},
 647         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 648                 tx_lpi_count)},
 649         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 650                 rx_lpi_count)},
 651 };
 652
 653 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 654                 sizeof(rte_i40e_hw_port_strings[0]))
 655
 656 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 657         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_rx)},
 659         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 660                 priority_xoff_rx)},
 661 };
 662
 663 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 664                 sizeof(rte_i40e_rxq_prio_strings[0]))
 665
 666 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 667         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 668                 priority_xon_tx)},
 669         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 670                 priority_xoff_tx)},
 671         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 672                 priority_xon_2_xoff)},
 673 };
 674
 675 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 676                 sizeof(rte_i40e_txq_prio_strings[0]))
 677
 678 static struct eth_driver rte_i40e_pmd = {
 679         .pci_drv = {
 680                 .id_table = pci_id_i40e_map,
 681                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 682                         RTE_PCI_DRV_DETACHABLE,
 683                 .probe = rte_eth_dev_pci_probe,
 684                 .remove = rte_eth_dev_pci_remove,
 685         },
 686         .eth_dev_init = eth_i40e_dev_init,
 687         .eth_dev_uninit = eth_i40e_dev_uninit,
 688         .dev_private_size = sizeof(struct i40e_adapter),
 689 };
 690
 691 static inline int
 692 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 693                                      struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = link;
 696         struct rte_eth_link *src = &(dev->data->dev_link);
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 static inline int
 706 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 707                                       struct rte_eth_link *link)
 708 {
 709         struct rte_eth_link *dst = &(dev->data->dev_link);
 710         struct rte_eth_link *src = link;
 711
 712         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 713                                         *(uint64_t *)src) == 0)
 714                 return -1;
 715
 716         return 0;
 717 }
 718
 719 static inline void
 720 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 721 {
 722         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 723         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 724                     "with value 0x%08x",
 725                     reg_addr, reg_val);
 726 }
 727
 728 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 729 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 730
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737
 738 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 739 {
 740         /*
 741          * Force global configuration for flexible payload
 742          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 743          * This should be removed from code once proper
 744          * configuration API is added to avoid configuration conflicts
 745          * between ports of the same device.
 746          */
 747         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 750         i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
 751
 752         /*
 753          * Initialize registers for parsing packet type of QinQ
 754          * This should be removed from code once proper
 755          * configuration API is added to avoid configuration conflicts
 756          * between ports of the same device.
 757          */
 758         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 759         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 760         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 761 }
 762
 763 static inline void i40e_config_automask(struct i40e_pf *pf)
 764 {
 765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 766         uint32_t val;
 767
 768         /* INTENA flag is not auto-cleared for interrupt */
 769         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 770         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 771                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 772
 773         /* If support multi-driver, PF will use INT0. */
 774         if (!pf->support_multi_driver)
 775                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 776
 777         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 778 }
 779
 780 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 781
 782 /*
 783  * Add a ethertype filter to drop all flow control frames transmitted
 784  * from VSIs.
 785 */
 786 static void
 787 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 788 {
 789         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 790         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 791                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 792                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 793         int ret;
 794
 795         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 796                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 797                                 pf->main_vsi_seid, 0,
 798                                 TRUE, NULL, NULL);
 799         if (ret)
 800                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 801                                   " frames from VSIs.");
 802 }
 803
 804 static int
 805 floating_veb_list_handler(__rte_unused const char *key,
 806                           const char *floating_veb_value,
 807                           void *opaque)
 808 {
 809         int idx = 0;
 810         unsigned int count = 0;
 811         char *end = NULL;
 812         int min, max;
 813         bool *vf_floating_veb = opaque;
 814
 815         while (isblank(*floating_veb_value))
 816                 floating_veb_value++;
 817
 818         /* Reset floating VEB configuration for VFs */
 819         for (idx = 0; idx < I40E_MAX_VF; idx++)
 820                 vf_floating_veb[idx] = false;
 821
 822         min = I40E_MAX_VF;
 823         do {
 824                 while (isblank(*floating_veb_value))
 825                         floating_veb_value++;
 826                 if (*floating_veb_value == '\0')
 827                         return -1;
 828                 errno = 0;
 829                 idx = strtoul(floating_veb_value, &end, 10);
 830                 if (errno || end == NULL)
 831                         return -1;
 832                 while (isblank(*end))
 833                         end++;
 834                 if (*end == '-') {
 835                         min = idx;
 836                 } else if ((*end == ';') || (*end == '\0')) {
 837                         max = idx;
 838                         if (min == I40E_MAX_VF)
 839                                 min = idx;
 840                         if (max >= I40E_MAX_VF)
 841                                 max = I40E_MAX_VF - 1;
 842                         for (idx = min; idx <= max; idx++) {
 843                                 vf_floating_veb[idx] = true;
 844                                 count++;
 845                         }
 846                         min = I40E_MAX_VF;
 847                 } else {
 848                         return -1;
 849                 }
 850                 floating_veb_value = end + 1;
 851         } while (*end != '\0');
 852
 853         if (count == 0)
 854                 return -1;
 855
 856         return 0;
 857 }
 858
 859 static void
 860 config_vf_floating_veb(struct rte_devargs *devargs,
 861                        uint16_t floating_veb,
 862                        bool *vf_floating_veb)
 863 {
 864         struct rte_kvargs *kvlist;
 865         int i;
 866         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 867
 868         if (!floating_veb)
 869                 return;
 870         /* All the VFs attach to the floating VEB by default
 871          * when the floating VEB is enabled.
 872          */
 873         for (i = 0; i < I40E_MAX_VF; i++)
 874                 vf_floating_veb[i] = true;
 875
 876         if (devargs == NULL)
 877                 return;
 878
 879         kvlist = rte_kvargs_parse(devargs->args, NULL);
 880         if (kvlist == NULL)
 881                 return;
 882
 883         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 884                 rte_kvargs_free(kvlist);
 885                 return;
 886         }
 887         /* When the floating_veb_list parameter exists, all the VFs
 888          * will attach to the legacy VEB firstly, then configure VFs
 889          * to the floating VEB according to the floating_veb_list.
 890          */
 891         if (rte_kvargs_process(kvlist, floating_veb_list,
 892                                floating_veb_list_handler,
 893                                vf_floating_veb) < 0) {
 894                 rte_kvargs_free(kvlist);
 895                 return;
 896         }
 897         rte_kvargs_free(kvlist);
 898 }
 899
 900 static int
 901 i40e_check_floating_handler(__rte_unused const char *key,
 902                             const char *value,
 903                             __rte_unused void *opaque)
 904 {
 905         if (strcmp(value, "1"))
 906                 return -1;
 907
 908         return 0;
 909 }
 910
 911 static int
 912 is_floating_veb_supported(struct rte_devargs *devargs)
 913 {
 914         struct rte_kvargs *kvlist;
 915         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 916
 917         if (devargs == NULL)
 918                 return 0;
 919
 920         kvlist = rte_kvargs_parse(devargs->args, NULL);
 921         if (kvlist == NULL)
 922                 return 0;
 923
 924         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 925                 rte_kvargs_free(kvlist);
 926                 return 0;
 927         }
 928         /* Floating VEB is enabled when there's key-value:
 929          * enable_floating_veb=1
 930          */
 931         if (rte_kvargs_process(kvlist, floating_veb_key,
 932                                i40e_check_floating_handler, NULL) < 0) {
 933                 rte_kvargs_free(kvlist);
 934                 return 0;
 935         }
 936         rte_kvargs_free(kvlist);
 937
 938         return 1;
 939 }
 940
 941 static void
 942 config_floating_veb(struct rte_eth_dev *dev)
 943 {
 944         struct rte_pci_device *pci_dev = dev->pci_dev;
 945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 946         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 947
 948         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 949
 950         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 951                 pf->floating_veb =
 952                         is_floating_veb_supported(pci_dev->device.devargs);
 953                 config_vf_floating_veb(pci_dev->device.devargs,
 954                                        pf->floating_veb,
 955                                        pf->floating_veb_list);
 956         } else {
 957                 pf->floating_veb = false;
 958         }
 959 }
 960
 961 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 962 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 963
 964 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
 965 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
 966                               ETH_I40E_SUPPORT_MULTI_DRIVER "=0|1");
 967
 968 static int
 969 i40e_parse_multi_drv_handler(__rte_unused const char *key,
 970                               const char *value,
 971                               void *opaque)
 972 {
 973         struct i40e_pf *pf;
 974         unsigned long support_multi_driver;
 975         char *end;
 976
 977         pf = (struct i40e_pf *)opaque;
 978
 979         errno = 0;
 980         support_multi_driver = strtoul(value, &end, 10);
 981         if (errno != 0 || end == value || *end != 0) {
 982                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
 983                 return -(EINVAL);
 984         }
 985
 986         if (support_multi_driver == 1 || support_multi_driver == 0)
 987                 pf->support_multi_driver = (bool)support_multi_driver;
 988         else
 989                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
 990                             "enable global configuration by default."
 991                             ETH_I40E_SUPPORT_MULTI_DRIVER);
 992         return 0;
 993 }
 994
 995 static int
 996 i40e_support_multi_driver(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct rte_pci_device *pci_dev = dev->pci_dev;
1000         static const char *valid_keys[] = {
1001                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1002         struct rte_kvargs *kvlist;
1003
1004         /* Enable global configuration by default */
1005         pf->support_multi_driver = false;
1006
1007         if (!pci_dev->device.devargs)
1008                 return 0;
1009
1010         kvlist = rte_kvargs_parse(pci_dev->device.devargs->args, valid_keys);
1011         if (!kvlist)
1012                 return -EINVAL;
1013
1014         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1015                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1016                             "the first invalid or last valid one is used !",
1017                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1018
1019         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1020                                i40e_parse_multi_drv_handler, pf) < 0) {
1021                 rte_kvargs_free(kvlist);
1022                 return -EINVAL;
1023         }
1024
1025         rte_kvargs_free(kvlist);
1026         return 0;
1027 }
1028
1029 static int
1030 eth_i40e_dev_init(struct rte_eth_dev *dev)
1031 {
1032         struct rte_pci_device *pci_dev;
1033         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1034         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1035         struct i40e_vsi *vsi;
1036         int ret;
1037         uint32_t len;
1038         uint8_t aq_fail = 0;
1039
1040         PMD_INIT_FUNC_TRACE();
1041
1042         dev->dev_ops = &i40e_eth_dev_ops;
1043         dev->rx_pkt_burst = i40e_recv_pkts;
1044         dev->tx_pkt_burst = i40e_xmit_pkts;
1045
1046         /* for secondary processes, we don't initialise any further as primary
1047          * has already done this work. Only check we don't need a different
1048          * RX function */
1049         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1050                 i40e_set_rx_function(dev);
1051                 i40e_set_tx_function(dev);
1052                 return 0;
1053         }
1054         pci_dev = dev->pci_dev;
1055
1056         rte_eth_copy_pci_info(dev, pci_dev);
1057
1058         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1059         pf->adapter->eth_dev = dev;
1060         pf->dev_data = dev->data;
1061
1062         hw->back = I40E_PF_TO_ADAPTER(pf);
1063         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1064         if (!hw->hw_addr) {
1065                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1066                              "as address is NULL");
1067                 return -ENODEV;
1068         }
1069
1070         hw->vendor_id = pci_dev->id.vendor_id;
1071         hw->device_id = pci_dev->id.device_id;
1072         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1073         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1074         hw->bus.device = pci_dev->addr.devid;
1075         hw->bus.func = pci_dev->addr.function;
1076         hw->adapter_stopped = 0;
1077
1078         /* Check if need to support multi-driver */
1079         i40e_support_multi_driver(dev);
1080
1081         /* Make sure all is clean before doing PF reset */
1082         i40e_clear_hw(hw);
1083
1084         /* Initialize the hardware */
1085         i40e_hw_init(dev);
1086
1087         /* Reset here to make sure all is clean for each PF */
1088         ret = i40e_pf_reset(hw);
1089         if (ret) {
1090                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1091                 return ret;
1092         }
1093
1094         /* Initialize the shared code (base driver) */
1095         ret = i40e_init_shared_code(hw);
1096         if (ret) {
1097                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1098                 return ret;
1099         }
1100
1101         i40e_config_automask(pf);
1102
1103         /*
1104          * To work around the NVM issue, initialize registers
1105          * for flexible payload and packet type of QinQ by
1106          * software. It should be removed once issues are fixed
1107          * in NVM.
1108          */
1109         if (!pf->support_multi_driver)
1110                 i40e_GLQF_reg_init(hw);
1111
1112         /* Initialize the input set for filters (hash and fd) to default value */
1113         i40e_filter_input_set_init(pf);
1114
1115         /* Initialize the parameters for adminq */
1116         i40e_init_adminq_parameter(hw);
1117         ret = i40e_init_adminq(hw);
1118         if (ret != I40E_SUCCESS) {
1119                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1120                 return -EIO;
1121         }
1122         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1123                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1124                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1125                      ((hw->nvm.version >> 12) & 0xf),
1126                      ((hw->nvm.version >> 4) & 0xff),
1127                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1128
1129         /* Need the special FW version to support floating VEB */
1130         config_floating_veb(dev);
1131         /* Clear PXE mode */
1132         i40e_clear_pxe_mode(hw);
1133         ret = i40e_dev_sync_phy_type(hw);
1134         if (ret) {
1135                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1136                 goto err_sync_phy_type;
1137         }
1138         /*
1139          * On X710, performance number is far from the expectation on recent
1140          * firmware versions. The fix for this issue may not be integrated in
1141          * the following firmware version. So the workaround in software driver
1142          * is needed. It needs to modify the initial values of 3 internal only
1143          * registers. Note that the workaround can be removed when it is fixed
1144          * in firmware in the future.
1145          */
1146         i40e_configure_registers(hw);
1147
1148         /* Get hw capabilities */
1149         ret = i40e_get_cap(hw);
1150         if (ret != I40E_SUCCESS) {
1151                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1152                 goto err_get_capabilities;
1153         }
1154
1155         /* Initialize parameters for PF */
1156         ret = i40e_pf_parameter_init(dev);
1157         if (ret != 0) {
1158                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1159                 goto err_parameter_init;
1160         }
1161
1162         /* Initialize the queue management */
1163         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1164         if (ret < 0) {
1165                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1166                 goto err_qp_pool_init;
1167         }
1168         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1169                                 hw->func_caps.num_msix_vectors - 1);
1170         if (ret < 0) {
1171                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1172                 goto err_msix_pool_init;
1173         }
1174
1175         /* Initialize lan hmc */
1176         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1177                                 hw->func_caps.num_rx_qp, 0, 0);
1178         if (ret != I40E_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1180                 goto err_init_lan_hmc;
1181         }
1182
1183         /* Configure lan hmc */
1184         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1185         if (ret != I40E_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1187                 goto err_configure_lan_hmc;
1188         }
1189
1190         /* Get and check the mac address */
1191         i40e_get_mac_addr(hw, hw->mac.addr);
1192         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1193                 PMD_INIT_LOG(ERR, "mac address is not valid");
1194                 ret = -EIO;
1195                 goto err_get_mac_addr;
1196         }
1197         /* Copy the permanent MAC address */
1198         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1199                         (struct ether_addr *) hw->mac.perm_addr);
1200
1201         /* Disable flow control */
1202         hw->fc.requested_mode = I40E_FC_NONE;
1203         i40e_set_fc(hw, &aq_fail, TRUE);
1204
1205         /* Set the global registers with default ether type value */
1206         if (!pf->support_multi_driver) {
1207                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1208                                          ETHER_TYPE_VLAN);
1209                 if (ret != I40E_SUCCESS) {
1210                         PMD_INIT_LOG(ERR, "Failed to set the default outer "
1211                                      "VLAN ether type");
1212                         goto err_setup_pf_switch;
1213                 }
1214         }
1215
1216         /* PF setup, which includes VSI setup */
1217         ret = i40e_pf_setup(pf);
1218         if (ret) {
1219                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* reset all stats of the device, including pf and main vsi */
1224         i40e_dev_stats_reset(dev);
1225
1226         vsi = pf->main_vsi;
1227
1228         /* Disable double vlan by default */
1229         i40e_vsi_config_double_vlan(vsi, FALSE);
1230
1231         /* Disable S-TAG identification when floating_veb is disabled */
1232         if (!pf->floating_veb) {
1233                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1234                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1235                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1236                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1237                 }
1238         }
1239
1240         if (!vsi->max_macaddrs)
1241                 len = ETHER_ADDR_LEN;
1242         else
1243                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1244
1245         /* Should be after VSI initialized */
1246         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1247         if (!dev->data->mac_addrs) {
1248                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1249                                         "for storing mac address");
1250                 goto err_mac_alloc;
1251         }
1252         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1253                                         &dev->data->mac_addrs[0]);
1254
1255         /* initialize pf host driver to setup SRIOV resource if applicable */
1256         i40e_pf_host_init(dev);
1257
1258         /* register callback func to eal lib */
1259         rte_intr_callback_register(&(pci_dev->intr_handle),
1260                 i40e_dev_interrupt_handler, (void *)dev);
1261
1262         /* configure and enable device interrupt */
1263         i40e_pf_config_irq0(hw, TRUE);
1264         i40e_pf_enable_irq0(hw);
1265
1266         /* enable uio intr after callback register */
1267         rte_intr_enable(&(pci_dev->intr_handle));
1268         /*
1269          * Add an ethertype filter to drop all flow control frames transmitted
1270          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1271          * frames to wire.
1272          */
1273         i40e_add_tx_flow_control_drop_filter(pf);
1274
1275         /* Set the max frame size to 0x2600 by default,
1276          * in case other drivers changed the default value.
1277          */
1278         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1279
1280         /* initialize mirror rule list */
1281         TAILQ_INIT(&pf->mirror_list);
1282
1283         /* Init dcb to sw mode by default */
1284         ret = i40e_dcb_init_configure(dev, TRUE);
1285         if (ret != I40E_SUCCESS) {
1286                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1287                 pf->flags &= ~I40E_FLAG_DCB;
1288         }
1289
1290         return 0;
1291
1292 err_mac_alloc:
1293         i40e_vsi_release(pf->main_vsi);
1294 err_setup_pf_switch:
1295 err_get_mac_addr:
1296 err_configure_lan_hmc:
1297         (void)i40e_shutdown_lan_hmc(hw);
1298 err_init_lan_hmc:
1299         i40e_res_pool_destroy(&pf->msix_pool);
1300 err_msix_pool_init:
1301         i40e_res_pool_destroy(&pf->qp_pool);
1302 err_qp_pool_init:
1303 err_parameter_init:
1304 err_get_capabilities:
1305 err_sync_phy_type:
1306         (void)i40e_shutdown_adminq(hw);
1307
1308         return ret;
1309 }
1310
1311 static int
1312 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1313 {
1314         struct rte_pci_device *pci_dev;
1315         struct i40e_hw *hw;
1316         struct i40e_filter_control_settings settings;
1317         int ret;
1318         uint8_t aq_fail = 0;
1319         int retries = 0;
1320
1321         PMD_INIT_FUNC_TRACE();
1322
1323         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1324                 return 0;
1325
1326         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327         pci_dev = dev->pci_dev;
1328
1329         if (hw->adapter_stopped == 0)
1330                 i40e_dev_close(dev);
1331
1332         dev->dev_ops = NULL;
1333         dev->rx_pkt_burst = NULL;
1334         dev->tx_pkt_burst = NULL;
1335
1336         /* Clear PXE mode */
1337         i40e_clear_pxe_mode(hw);
1338
1339         /* Unconfigure filter control */
1340         memset(&settings, 0, sizeof(settings));
1341         ret = i40e_set_filter_control(hw, &settings);
1342         if (ret)
1343                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1344                                         ret);
1345
1346         /* Disable flow control */
1347         hw->fc.requested_mode = I40E_FC_NONE;
1348         i40e_set_fc(hw, &aq_fail, TRUE);
1349
1350         /* uninitialize pf host driver */
1351         i40e_pf_host_uninit(dev);
1352
1353         rte_free(dev->data->mac_addrs);
1354         dev->data->mac_addrs = NULL;
1355
1356         /* disable uio intr before callback unregister */
1357         rte_intr_disable(&(pci_dev->intr_handle));
1358
1359         /* unregister callback func to eal lib */
1360         do {
1361                 ret = rte_intr_callback_unregister(&(pci_dev->intr_handle),
1362                                 i40e_dev_interrupt_handler, (void *)dev);
1363                 if (ret >= 0) {
1364                         break;
1365                 } else if (ret != -EAGAIN) {
1366                         PMD_INIT_LOG(ERR,
1367                                  "intr callback unregister failed: %d",
1368                                  ret);
1369                         return ret;
1370                 }
1371                 i40e_msec_delay(500);
1372         } while (retries++ < 5);
1373
1374         return 0;
1375 }
1376
1377 static int
1378 i40e_dev_configure(struct rte_eth_dev *dev)
1379 {
1380         struct i40e_adapter *ad =
1381                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1382         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1383         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1384         int i, ret;
1385
1386         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1387          * bulk allocation or vector Rx preconditions we will reset it.
1388          */
1389         ad->rx_bulk_alloc_allowed = true;
1390         ad->rx_vec_allowed = true;
1391         ad->tx_simple_allowed = true;
1392         ad->tx_vec_allowed = true;
1393
1394         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1395                 ret = i40e_fdir_setup(pf);
1396                 if (ret != I40E_SUCCESS) {
1397                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1398                         return -ENOTSUP;
1399                 }
1400                 ret = i40e_fdir_configure(dev);
1401                 if (ret < 0) {
1402                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1403                         goto err;
1404                 }
1405         } else
1406                 i40e_fdir_teardown(pf);
1407
1408         ret = i40e_dev_init_vlan(dev);
1409         if (ret < 0)
1410                 goto err;
1411
1412         /* VMDQ setup.
1413          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1414          *  RSS setting have different requirements.
1415          *  General PMD driver call sequence are NIC init, configure,
1416          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1417          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1418          *  applicable. So, VMDQ setting has to be done before
1419          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1420          *  For RSS setting, it will try to calculate actual configured RX queue
1421          *  number, which will be available after rx_queue_setup(). dev_start()
1422          *  function is good to place RSS setup.
1423          */
1424         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1425                 ret = i40e_vmdq_setup(dev);
1426                 if (ret)
1427                         goto err;
1428         }
1429
1430         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1431                 ret = i40e_dcb_setup(dev);
1432                 if (ret) {
1433                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1434                         goto err_dcb;
1435                 }
1436         }
1437
1438         return 0;
1439
1440 err_dcb:
1441         /* need to release vmdq resource if exists */
1442         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1443                 i40e_vsi_release(pf->vmdq[i].vsi);
1444                 pf->vmdq[i].vsi = NULL;
1445         }
1446         rte_free(pf->vmdq);
1447         pf->vmdq = NULL;
1448 err:
1449         /* need to release fdir resource if exists */
1450         i40e_fdir_teardown(pf);
1451         return ret;
1452 }
1453
1454 void
1455 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1456 {
1457         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1458         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1459         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1460         uint16_t msix_vect = vsi->msix_intr;
1461         uint16_t i;
1462
1463         for (i = 0; i < vsi->nb_qps; i++) {
1464                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1465                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1466                 rte_wmb();
1467         }
1468
1469         if (vsi->type != I40E_VSI_SRIOV) {
1470                 if (!rte_intr_allow_others(intr_handle)) {
1471                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1472                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1473                         I40E_WRITE_REG(hw,
1474                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1475                                        0);
1476                 } else {
1477                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1478                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1479                         I40E_WRITE_REG(hw,
1480                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1481                                                        msix_vect - 1), 0);
1482                 }
1483         } else {
1484                 uint32_t reg;
1485                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1486                         vsi->user_param + (msix_vect - 1);
1487
1488                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1489                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1490         }
1491         I40E_WRITE_FLUSH(hw);
1492 }
1493
1494 static void
1495 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1496                        int base_queue, int nb_queue)
1497 {
1498         int i;
1499         uint32_t val;
1500         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1501         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1502
1503         /* Bind all RX queues to allocated MSIX interrupt */
1504         for (i = 0; i < nb_queue; i++) {
1505                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1506                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1507                         ((base_queue + i + 1) <<
1508                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1509                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1510                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1511
1512                 if (i == nb_queue - 1)
1513                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1514                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1515         }
1516
1517         /* Write first RX queue to Link list register as the head element */
1518         if (vsi->type != I40E_VSI_SRIOV) {
1519                 uint16_t interval =
1520                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL,
1521                                                pf->support_multi_driver);
1522
1523                 if (msix_vect == I40E_MISC_VEC_ID) {
1524                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1525                                        (base_queue <<
1526                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1527                                        (0x0 <<
1528                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1529                         I40E_WRITE_REG(hw,
1530                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1531                                        interval);
1532                 } else {
1533                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1534                                        (base_queue <<
1535                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1536                                        (0x0 <<
1537                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1538                         I40E_WRITE_REG(hw,
1539                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1540                                                        msix_vect - 1),
1541                                        interval);
1542                 }
1543         } else {
1544                 uint32_t reg;
1545
1546                 if (msix_vect == I40E_MISC_VEC_ID) {
1547                         I40E_WRITE_REG(hw,
1548                                        I40E_VPINT_LNKLST0(vsi->user_param),
1549                                        (base_queue <<
1550                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1551                                        (0x0 <<
1552                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1553                 } else {
1554                         /* num_msix_vectors_vf needs to minus irq0 */
1555                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1556                                 vsi->user_param + (msix_vect - 1);
1557
1558                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1559                                        (base_queue <<
1560                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1561                                        (0x0 <<
1562                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1563                 }
1564         }
1565
1566         I40E_WRITE_FLUSH(hw);
1567 }
1568
1569 void
1570 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1571 {
1572         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1573         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1574         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1575         uint16_t msix_vect = vsi->msix_intr;
1576         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1577         uint16_t queue_idx = 0;
1578         int record = 0;
1579         int i;
1580
1581         for (i = 0; i < vsi->nb_qps; i++) {
1582                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1583                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1584         }
1585
1586         /* VF bind interrupt */
1587         if (vsi->type == I40E_VSI_SRIOV) {
1588                 __vsi_queues_bind_intr(vsi, msix_vect,
1589                                        vsi->base_queue, vsi->nb_qps);
1590                 return;
1591         }
1592
1593         /* PF & VMDq bind interrupt */
1594         if (rte_intr_dp_is_en(intr_handle)) {
1595                 if (vsi->type == I40E_VSI_MAIN) {
1596                         queue_idx = 0;
1597                         record = 1;
1598                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1599                         struct i40e_vsi *main_vsi =
1600                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1601                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1602                         record = 1;
1603                 }
1604         }
1605
1606         for (i = 0; i < vsi->nb_used_qps; i++) {
1607                 if (nb_msix <= 1) {
1608                         if (!rte_intr_allow_others(intr_handle))
1609                                 /* allow to share MISC_VEC_ID */
1610                                 msix_vect = I40E_MISC_VEC_ID;
1611
1612                         /* no enough msix_vect, map all to one */
1613                         __vsi_queues_bind_intr(vsi, msix_vect,
1614                                                vsi->base_queue + i,
1615                                                vsi->nb_used_qps - i);
1616                         for (; !!record && i < vsi->nb_used_qps; i++)
1617                                 intr_handle->intr_vec[queue_idx + i] =
1618                                         msix_vect;
1619                         break;
1620                 }
1621                 /* 1:1 queue/msix_vect mapping */
1622                 __vsi_queues_bind_intr(vsi, msix_vect,
1623                                        vsi->base_queue + i, 1);
1624                 if (!!record)
1625                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1626
1627                 msix_vect++;
1628                 nb_msix--;
1629         }
1630 }
1631
1632 static void
1633 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1634 {
1635         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1636         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1638         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1639         uint16_t msix_intr, i;
1640
1641         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1642                 for (i = 0; i < vsi->nb_msix; i++) {
1643                         msix_intr = vsi->msix_intr + i;
1644                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1645                                        I40E_PFINT_DYN_CTLN_INTENA_MASK |
1646                                        I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1647                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1648                 }
1649         else
1650                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1651                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1652                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1653                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1654
1655         I40E_WRITE_FLUSH(hw);
1656 }
1657
1658 static void
1659 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1660 {
1661         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1662         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1663         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1664         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1665         uint16_t msix_intr, i;
1666
1667         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1668                 for (i = 0; i < vsi->nb_msix; i++) {
1669                         msix_intr = vsi->msix_intr + i;
1670                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1671                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1672                 }
1673         else
1674                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1675                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1676
1677         I40E_WRITE_FLUSH(hw);
1678 }
1679
1680 static inline uint8_t
1681 i40e_parse_link_speeds(uint16_t link_speeds)
1682 {
1683         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1684
1685         if (link_speeds & ETH_LINK_SPEED_40G)
1686                 link_speed |= I40E_LINK_SPEED_40GB;
1687         if (link_speeds & ETH_LINK_SPEED_25G)
1688                 link_speed |= I40E_LINK_SPEED_25GB;
1689         if (link_speeds & ETH_LINK_SPEED_20G)
1690                 link_speed |= I40E_LINK_SPEED_20GB;
1691         if (link_speeds & ETH_LINK_SPEED_10G)
1692                 link_speed |= I40E_LINK_SPEED_10GB;
1693         if (link_speeds & ETH_LINK_SPEED_1G)
1694                 link_speed |= I40E_LINK_SPEED_1GB;
1695         if (link_speeds & ETH_LINK_SPEED_100M)
1696                 link_speed |= I40E_LINK_SPEED_100MB;
1697
1698         return link_speed;
1699 }
1700
1701 static int
1702 i40e_phy_conf_link(struct i40e_hw *hw,
1703                    uint8_t abilities,
1704                    uint8_t force_speed,
1705                    bool is_up)
1706 {
1707         enum i40e_status_code status;
1708         struct i40e_aq_get_phy_abilities_resp phy_ab;
1709         struct i40e_aq_set_phy_config phy_conf;
1710         enum i40e_aq_phy_type cnt;
1711         uint32_t phy_type_mask = 0;
1712
1713         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1714                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1715                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1716                         I40E_AQ_PHY_FLAG_LOW_POWER;
1717         const uint8_t advt = I40E_LINK_SPEED_40GB |
1718                         I40E_LINK_SPEED_25GB |
1719                         I40E_LINK_SPEED_10GB |
1720                         I40E_LINK_SPEED_1GB |
1721                         I40E_LINK_SPEED_100MB;
1722         int ret = -ENOTSUP;
1723
1724
1725         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1726                                               NULL);
1727         if (status)
1728                 return ret;
1729
1730         /* If link already up, no need to set up again */
1731         if (is_up && phy_ab.phy_type != 0)
1732                 return I40E_SUCCESS;
1733
1734         memset(&phy_conf, 0, sizeof(phy_conf));
1735
1736         /* bits 0-2 use the values from get_phy_abilities_resp */
1737         abilities &= ~mask;
1738         abilities |= phy_ab.abilities & mask;
1739
1740         /* update ablities and speed */
1741         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1742                 phy_conf.link_speed = advt;
1743         else
1744                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1745
1746         phy_conf.abilities = abilities;
1747
1748
1749
1750         /* To enable link, phy_type mask needs to include each type */
1751         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1752                 phy_type_mask |= 1 << cnt;
1753
1754         /* use get_phy_abilities_resp value for the rest */
1755         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1756         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1757                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1758                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1759         phy_conf.fec_config = phy_ab.mod_type_ext;
1760         phy_conf.eee_capability = phy_ab.eee_capability;
1761         phy_conf.eeer = phy_ab.eeer_val;
1762         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1763
1764         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1765                     phy_ab.abilities, phy_ab.link_speed);
1766         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1767                     phy_conf.abilities, phy_conf.link_speed);
1768
1769         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1770         if (status)
1771                 return ret;
1772
1773         return I40E_SUCCESS;
1774 }
1775
1776 static int
1777 i40e_apply_link_speed(struct rte_eth_dev *dev)
1778 {
1779         uint8_t speed;
1780         uint8_t abilities = 0;
1781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782         struct rte_eth_conf *conf = &dev->data->dev_conf;
1783
1784         speed = i40e_parse_link_speeds(conf->link_speeds);
1785         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1786         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1787                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1788         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1789
1790         return i40e_phy_conf_link(hw, abilities, speed, true);
1791 }
1792
1793 static int
1794 i40e_dev_start(struct rte_eth_dev *dev)
1795 {
1796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798         struct i40e_vsi *main_vsi = pf->main_vsi;
1799         int ret, i;
1800         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1801         uint32_t intr_vector = 0;
1802
1803         hw->adapter_stopped = 0;
1804
1805         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1806                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1807                              dev->data->port_id);
1808                 return -EINVAL;
1809         }
1810
1811         rte_intr_disable(intr_handle);
1812
1813         if ((rte_intr_cap_multiple(intr_handle) ||
1814              !RTE_ETH_DEV_SRIOV(dev).active) &&
1815             dev->data->dev_conf.intr_conf.rxq != 0) {
1816                 intr_vector = dev->data->nb_rx_queues;
1817                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1818                         return -1;
1819         }
1820
1821         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1822                 intr_handle->intr_vec =
1823                         rte_zmalloc("intr_vec",
1824                                     dev->data->nb_rx_queues * sizeof(int),
1825                                     0);
1826                 if (!intr_handle->intr_vec) {
1827                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1828                                      " intr_vec\n", dev->data->nb_rx_queues);
1829                         return -ENOMEM;
1830                 }
1831         }
1832
1833         /* Initialize VSI */
1834         ret = i40e_dev_rxtx_init(pf);
1835         if (ret != I40E_SUCCESS) {
1836                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1837                 goto err_up;
1838         }
1839
1840         /* Map queues with MSIX interrupt */
1841         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1842                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1843         i40e_vsi_queues_bind_intr(main_vsi);
1844         i40e_vsi_enable_queues_intr(main_vsi);
1845
1846         /* Map VMDQ VSI queues with MSIX interrupt */
1847         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1848                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1849                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1850                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1851         }
1852
1853         /* enable FDIR MSIX interrupt */
1854         if (pf->fdir.fdir_vsi) {
1855                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1856                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1857         }
1858
1859         /* Enable all queues which have been configured */
1860         ret = i40e_dev_switch_queues(pf, TRUE);
1861         if (ret != I40E_SUCCESS) {
1862                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1863                 goto err_up;
1864         }
1865
1866         /* Enable receiving broadcast packets */
1867         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1868         if (ret != I40E_SUCCESS)
1869                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1870
1871         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1872                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1873                                                 true, NULL);
1874                 if (ret != I40E_SUCCESS)
1875                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1876         }
1877
1878         /* Apply link configure */
1879         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1880                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1881                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1882                                 ETH_LINK_SPEED_40G)) {
1883                 PMD_DRV_LOG(ERR, "Invalid link setting");
1884                 goto err_up;
1885         }
1886         ret = i40e_apply_link_speed(dev);
1887         if (I40E_SUCCESS != ret) {
1888                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1889                 goto err_up;
1890         }
1891
1892         if (!rte_intr_allow_others(intr_handle)) {
1893                 rte_intr_callback_unregister(intr_handle,
1894                                              i40e_dev_interrupt_handler,
1895                                              (void *)dev);
1896                 /* configure and enable device interrupt */
1897                 i40e_pf_config_irq0(hw, FALSE);
1898                 i40e_pf_enable_irq0(hw);
1899
1900                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1901                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1902                                      " no intr multiplex\n");
1903         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1904                 ret = i40e_aq_set_phy_int_mask(hw,
1905                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1906                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1907                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1908                 if (ret != I40E_SUCCESS)
1909                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1910
1911                 /* Call get_link_info aq commond to enable LSE */
1912                 i40e_dev_link_update(dev, 0);
1913         }
1914
1915         /* enable uio intr after callback register */
1916         rte_intr_enable(intr_handle);
1917
1918         return I40E_SUCCESS;
1919
1920 err_up:
1921         i40e_dev_switch_queues(pf, FALSE);
1922         i40e_dev_clear_queues(dev);
1923
1924         return ret;
1925 }
1926
1927 static void
1928 i40e_dev_stop(struct rte_eth_dev *dev)
1929 {
1930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1931         struct i40e_vsi *main_vsi = pf->main_vsi;
1932         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1933         int i;
1934
1935         /* Disable all queues */
1936         i40e_dev_switch_queues(pf, FALSE);
1937
1938         /* un-map queues with interrupt registers */
1939         i40e_vsi_disable_queues_intr(main_vsi);
1940         i40e_vsi_queues_unbind_intr(main_vsi);
1941
1942         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1943                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1944                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1945         }
1946
1947         if (pf->fdir.fdir_vsi) {
1948                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1949                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1950         }
1951         /* Clear all queues and release memory */
1952         i40e_dev_clear_queues(dev);
1953
1954         /* Set link down */
1955         i40e_dev_set_link_down(dev);
1956
1957         if (!rte_intr_allow_others(intr_handle))
1958                 /* resume to the default handler */
1959                 rte_intr_callback_register(intr_handle,
1960                                            i40e_dev_interrupt_handler,
1961                                            (void *)dev);
1962
1963         /* Clean datapath event and queue/vec mapping */
1964         rte_intr_efd_disable(intr_handle);
1965         if (intr_handle->intr_vec) {
1966                 rte_free(intr_handle->intr_vec);
1967                 intr_handle->intr_vec = NULL;
1968         }
1969 }
1970
1971 static void
1972 i40e_dev_close(struct rte_eth_dev *dev)
1973 {
1974         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1975         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976         struct i40e_mirror_rule *p_mirror;
1977         uint32_t reg;
1978         int i;
1979         int ret;
1980
1981         PMD_INIT_FUNC_TRACE();
1982
1983         i40e_dev_stop(dev);
1984         hw->adapter_stopped = 1;
1985
1986         /* Remove all mirror rules */
1987         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1988                 ret = i40e_aq_del_mirror_rule(hw,
1989                                               pf->main_vsi->veb->seid,
1990                                               p_mirror->rule_type,
1991                                               p_mirror->entries,
1992                                               p_mirror->num_entries,
1993                                               p_mirror->id);
1994                 if (ret < 0)
1995                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
1996                                     "status = %d, aq_err = %d.", ret,
1997                                     hw->aq.asq_last_status);
1998
1999                 /* remove mirror software resource anyway */
2000                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2001                 rte_free(p_mirror);
2002                 pf->nb_mirror_rule--;
2003         }
2004
2005         i40e_dev_free_queues(dev);
2006
2007         /* Disable interrupt */
2008         i40e_pf_disable_irq0(hw);
2009         rte_intr_disable(&(dev->pci_dev->intr_handle));
2010
2011         i40e_fdir_teardown(pf);
2012
2013         /* shutdown and destroy the HMC */
2014         i40e_shutdown_lan_hmc(hw);
2015
2016         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2017                 i40e_vsi_release(pf->vmdq[i].vsi);
2018                 pf->vmdq[i].vsi = NULL;
2019         }
2020         rte_free(pf->vmdq);
2021         pf->vmdq = NULL;
2022
2023         /* release all the existing VSIs and VEBs */
2024         i40e_vsi_release(pf->main_vsi);
2025
2026         /* shutdown the adminq */
2027         i40e_aq_queue_shutdown(hw, true);
2028         i40e_shutdown_adminq(hw);
2029
2030         i40e_res_pool_destroy(&pf->qp_pool);
2031         i40e_res_pool_destroy(&pf->msix_pool);
2032
2033         /* force a PF reset to clean anything leftover */
2034         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2035         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2036                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2037         I40E_WRITE_FLUSH(hw);
2038 }
2039
2040 static void
2041 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2042 {
2043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         struct i40e_vsi *vsi = pf->main_vsi;
2046         int status;
2047
2048         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2049                                                      true, NULL, true);
2050         if (status != I40E_SUCCESS)
2051                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2052
2053         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2054                                                         TRUE, NULL);
2055         if (status != I40E_SUCCESS)
2056                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2057
2058 }
2059
2060 static void
2061 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2062 {
2063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2064         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct i40e_vsi *vsi = pf->main_vsi;
2066         int status;
2067
2068         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2069                                                      false, NULL, true);
2070         if (status != I40E_SUCCESS)
2071                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2072
2073         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2074                                                         false, NULL);
2075         if (status != I40E_SUCCESS)
2076                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2077 }
2078
2079 static void
2080 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2081 {
2082         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2083         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2084         struct i40e_vsi *vsi = pf->main_vsi;
2085         int ret;
2086
2087         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2088         if (ret != I40E_SUCCESS)
2089                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2090 }
2091
2092 static void
2093 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2094 {
2095         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         struct i40e_vsi *vsi = pf->main_vsi;
2098         int ret;
2099
2100         if (dev->data->promiscuous == 1)
2101                 return; /* must remain in all_multicast mode */
2102
2103         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2104                                 vsi->seid, FALSE, NULL);
2105         if (ret != I40E_SUCCESS)
2106                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2107 }
2108
2109 /*
2110  * Set device link up.
2111  */
2112 static int
2113 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2114 {
2115         /* re-apply link speed setting */
2116         return i40e_apply_link_speed(dev);
2117 }
2118
2119 /*
2120  * Set device link down.
2121  */
2122 static int
2123 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2124 {
2125         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2126         uint8_t abilities = 0;
2127         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2128
2129         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2130         return i40e_phy_conf_link(hw, abilities, speed, false);
2131 }
2132
2133 static inline void __attribute__((always_inline))
2134 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2135 {
2136 /* Link status registers and values*/
2137 #define I40E_PRTMAC_LINKSTA             0x001E2420
2138 #define I40E_REG_LINK_UP                0x40000080
2139 #define I40E_PRTMAC_MACC                0x001E24E0
2140 #define I40E_REG_MACC_25GB              0x00020000
2141 #define I40E_REG_SPEED_MASK             0x38000000
2142 #define I40E_REG_SPEED_100MB            0x00000000
2143 #define I40E_REG_SPEED_1GB              0x08000000
2144 #define I40E_REG_SPEED_10GB             0x10000000
2145 #define I40E_REG_SPEED_20GB             0x20000000
2146 #define I40E_REG_SPEED_25_40GB          0x18000000
2147         uint32_t link_speed;
2148         uint32_t reg_val;
2149
2150         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2151         link_speed = reg_val & I40E_REG_SPEED_MASK;
2152         reg_val &= I40E_REG_LINK_UP;
2153         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2154
2155         if (unlikely(link->link_status == 0))
2156                 return;
2157
2158         /* Parse the link status */
2159         switch (link_speed) {
2160         case I40E_REG_SPEED_100MB:
2161                 link->link_speed = ETH_SPEED_NUM_100M;
2162                 break;
2163         case I40E_REG_SPEED_1GB:
2164                 link->link_speed = ETH_SPEED_NUM_1G;
2165                 break;
2166         case I40E_REG_SPEED_10GB:
2167                 link->link_speed = ETH_SPEED_NUM_10G;
2168                 break;
2169         case I40E_REG_SPEED_20GB:
2170                 link->link_speed = ETH_SPEED_NUM_20G;
2171                 break;
2172         case I40E_REG_SPEED_25_40GB:
2173                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2174
2175                 if (reg_val & I40E_REG_MACC_25GB)
2176                         link->link_speed = ETH_SPEED_NUM_25G;
2177                 else
2178                         link->link_speed = ETH_SPEED_NUM_40G;
2179
2180                 break;
2181         default:
2182                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2183                 break;
2184         }
2185 }
2186
2187 static inline void __attribute__((always_inline))
2188 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2189         bool enable_lse)
2190 {
2191 #define CHECK_INTERVAL             100  /* 100ms */
2192 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2193         uint32_t rep_cnt = MAX_REPEAT_TIME;
2194         struct i40e_link_status link_status;
2195         int status;
2196
2197         memset(&link_status, 0, sizeof(link_status));
2198
2199         do {
2200                 /* Get link status information from hardware */
2201                 status = i40e_aq_get_link_info(hw, enable_lse,
2202                                                 &link_status, NULL);
2203                 if (unlikely(status != I40E_SUCCESS)) {
2204                         link->link_speed = ETH_SPEED_NUM_100M;
2205                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2206                         PMD_DRV_LOG(ERR, "Failed to get link info");
2207                         return;
2208                 }
2209
2210                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2211                 if (unlikely(link->link_status != 0))
2212                         break;
2213
2214                 rte_delay_ms(CHECK_INTERVAL);
2215         } while (--rep_cnt);
2216
2217         /* Parse the link status */
2218         switch (link_status.link_speed) {
2219         case I40E_LINK_SPEED_100MB:
2220                 link->link_speed = ETH_SPEED_NUM_100M;
2221                 break;
2222         case I40E_LINK_SPEED_1GB:
2223                 link->link_speed = ETH_SPEED_NUM_1G;
2224                 break;
2225         case I40E_LINK_SPEED_10GB:
2226                 link->link_speed = ETH_SPEED_NUM_10G;
2227                 break;
2228         case I40E_LINK_SPEED_20GB:
2229                 link->link_speed = ETH_SPEED_NUM_20G;
2230                 break;
2231         case I40E_LINK_SPEED_25GB:
2232                 link->link_speed = ETH_SPEED_NUM_25G;
2233                 break;
2234         case I40E_LINK_SPEED_40GB:
2235                 link->link_speed = ETH_SPEED_NUM_40G;
2236                 break;
2237         default:
2238                 link->link_speed = ETH_SPEED_NUM_100M;
2239                 break;
2240         }
2241 }
2242
2243 int
2244 i40e_dev_link_update(struct rte_eth_dev *dev,
2245                      int wait_to_complete)
2246 {
2247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         struct rte_eth_link link, old;
2249         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2250
2251         memset(&link, 0, sizeof(link));
2252         memset(&old, 0, sizeof(old));
2253
2254         rte_i40e_dev_atomic_read_link_status(dev, &old);
2255
2256         /* i40e uses full duplex only */
2257         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2258         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2259                         ETH_LINK_SPEED_FIXED);
2260
2261         if (!wait_to_complete)
2262                 update_link_no_wait(hw, &link);
2263         else
2264                 update_link_wait(hw, &link, enable_lse);
2265
2266         rte_i40e_dev_atomic_write_link_status(dev, &link);
2267         if (link.link_status == old.link_status)
2268                 return -1;
2269
2270         i40e_notify_all_vfs_link_status(dev);
2271
2272         return 0;
2273 }
2274
2275 /* Get all the statistics of a VSI */
2276 void
2277 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2278 {
2279         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2280         struct i40e_eth_stats *nes = &vsi->eth_stats;
2281         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2282         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2283
2284         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2285                             vsi->offset_loaded, &oes->rx_bytes,
2286                             &nes->rx_bytes);
2287         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2288                             vsi->offset_loaded, &oes->rx_unicast,
2289                             &nes->rx_unicast);
2290         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2291                             vsi->offset_loaded, &oes->rx_multicast,
2292                             &nes->rx_multicast);
2293         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2294                             vsi->offset_loaded, &oes->rx_broadcast,
2295                             &nes->rx_broadcast);
2296         /* exclude CRC bytes */
2297         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2298                 nes->rx_broadcast) * ETHER_CRC_LEN;
2299
2300         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2301                             &oes->rx_discards, &nes->rx_discards);
2302         /* GLV_REPC not supported */
2303         /* GLV_RMPC not supported */
2304         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2305                             &oes->rx_unknown_protocol,
2306                             &nes->rx_unknown_protocol);
2307         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2308                             vsi->offset_loaded, &oes->tx_bytes,
2309                             &nes->tx_bytes);
2310         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2311                             vsi->offset_loaded, &oes->tx_unicast,
2312                             &nes->tx_unicast);
2313         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2314                             vsi->offset_loaded, &oes->tx_multicast,
2315                             &nes->tx_multicast);
2316         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2317                             vsi->offset_loaded,  &oes->tx_broadcast,
2318                             &nes->tx_broadcast);
2319         /* exclude CRC bytes */
2320         nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2321                 nes->tx_broadcast) * ETHER_CRC_LEN;
2322         /* GLV_TDPC not supported */
2323         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2324                             &oes->tx_errors, &nes->tx_errors);
2325         vsi->offset_loaded = true;
2326
2327         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2328                     vsi->vsi_id);
2329         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2330         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2331         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2332         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2333         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2334         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2335                     nes->rx_unknown_protocol);
2336         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2337         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2338         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2339         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2340         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2341         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2342         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2343                     vsi->vsi_id);
2344 }
2345
2346 static void
2347 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2348 {
2349         unsigned int i;
2350         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2351         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2352
2353         /* Get rx/tx bytes of internal transfer packets */
2354         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2355                         I40E_GLV_GORCL(hw->port),
2356                         pf->offset_loaded,
2357                         &pf->internal_rx_bytes_offset,
2358                         &pf->internal_rx_bytes);
2359
2360         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2361                         I40E_GLV_GOTCL(hw->port),
2362                         pf->offset_loaded,
2363                         &pf->internal_tx_bytes_offset,
2364                         &pf->internal_tx_bytes);
2365
2366         /* Get statistics of struct i40e_eth_stats */
2367         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2368                             I40E_GLPRT_GORCL(hw->port),
2369                             pf->offset_loaded, &os->eth.rx_bytes,
2370                             &ns->eth.rx_bytes);
2371         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2372                             I40E_GLPRT_UPRCL(hw->port),
2373                             pf->offset_loaded, &os->eth.rx_unicast,
2374                             &ns->eth.rx_unicast);
2375         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2376                             I40E_GLPRT_MPRCL(hw->port),
2377                             pf->offset_loaded, &os->eth.rx_multicast,
2378                             &ns->eth.rx_multicast);
2379         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2380                             I40E_GLPRT_BPRCL(hw->port),
2381                             pf->offset_loaded, &os->eth.rx_broadcast,
2382                             &ns->eth.rx_broadcast);
2383         /* Workaround: CRC size should not be included in byte statistics,
2384          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2385          */
2386         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2387                 ns->eth.rx_broadcast) * ETHER_CRC_LEN + pf->internal_rx_bytes;
2388
2389         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2390                             pf->offset_loaded, &os->eth.rx_discards,
2391                             &ns->eth.rx_discards);
2392         /* GLPRT_REPC not supported */
2393         /* GLPRT_RMPC not supported */
2394         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2395                             pf->offset_loaded,
2396                             &os->eth.rx_unknown_protocol,
2397                             &ns->eth.rx_unknown_protocol);
2398         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2399                             I40E_GLPRT_GOTCL(hw->port),
2400                             pf->offset_loaded, &os->eth.tx_bytes,
2401                             &ns->eth.tx_bytes);
2402         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2403                             I40E_GLPRT_UPTCL(hw->port),
2404                             pf->offset_loaded, &os->eth.tx_unicast,
2405                             &ns->eth.tx_unicast);
2406         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2407                             I40E_GLPRT_MPTCL(hw->port),
2408                             pf->offset_loaded, &os->eth.tx_multicast,
2409                             &ns->eth.tx_multicast);
2410         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2411                             I40E_GLPRT_BPTCL(hw->port),
2412                             pf->offset_loaded, &os->eth.tx_broadcast,
2413                             &ns->eth.tx_broadcast);
2414         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2415                 ns->eth.tx_broadcast) * ETHER_CRC_LEN + pf->internal_tx_bytes;
2416         /* GLPRT_TEPC not supported */
2417
2418         /* additional port specific stats */
2419         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2420                             pf->offset_loaded, &os->tx_dropped_link_down,
2421                             &ns->tx_dropped_link_down);
2422         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2423                             pf->offset_loaded, &os->crc_errors,
2424                             &ns->crc_errors);
2425         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2426                             pf->offset_loaded, &os->illegal_bytes,
2427                             &ns->illegal_bytes);
2428         /* GLPRT_ERRBC not supported */
2429         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2430                             pf->offset_loaded, &os->mac_local_faults,
2431                             &ns->mac_local_faults);
2432         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2433                             pf->offset_loaded, &os->mac_remote_faults,
2434                             &ns->mac_remote_faults);
2435         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2436                             pf->offset_loaded, &os->rx_length_errors,
2437                             &ns->rx_length_errors);
2438         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2439                             pf->offset_loaded, &os->link_xon_rx,
2440                             &ns->link_xon_rx);
2441         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2442                             pf->offset_loaded, &os->link_xoff_rx,
2443                             &ns->link_xoff_rx);
2444         for (i = 0; i < 8; i++) {
2445                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2446                                     pf->offset_loaded,
2447                                     &os->priority_xon_rx[i],
2448                                     &ns->priority_xon_rx[i]);
2449                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2450                                     pf->offset_loaded,
2451                                     &os->priority_xoff_rx[i],
2452                                     &ns->priority_xoff_rx[i]);
2453         }
2454         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2455                             pf->offset_loaded, &os->link_xon_tx,
2456                             &ns->link_xon_tx);
2457         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2458                             pf->offset_loaded, &os->link_xoff_tx,
2459                             &ns->link_xoff_tx);
2460         for (i = 0; i < 8; i++) {
2461                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2462                                     pf->offset_loaded,
2463                                     &os->priority_xon_tx[i],
2464                                     &ns->priority_xon_tx[i]);
2465                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2466                                     pf->offset_loaded,
2467                                     &os->priority_xoff_tx[i],
2468                                     &ns->priority_xoff_tx[i]);
2469                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2470                                     pf->offset_loaded,
2471                                     &os->priority_xon_2_xoff[i],
2472                                     &ns->priority_xon_2_xoff[i]);
2473         }
2474         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2475                             I40E_GLPRT_PRC64L(hw->port),
2476                             pf->offset_loaded, &os->rx_size_64,
2477                             &ns->rx_size_64);
2478         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2479                             I40E_GLPRT_PRC127L(hw->port),
2480                             pf->offset_loaded, &os->rx_size_127,
2481                             &ns->rx_size_127);
2482         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2483                             I40E_GLPRT_PRC255L(hw->port),
2484                             pf->offset_loaded, &os->rx_size_255,
2485                             &ns->rx_size_255);
2486         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2487                             I40E_GLPRT_PRC511L(hw->port),
2488                             pf->offset_loaded, &os->rx_size_511,
2489                             &ns->rx_size_511);
2490         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2491                             I40E_GLPRT_PRC1023L(hw->port),
2492                             pf->offset_loaded, &os->rx_size_1023,
2493                             &ns->rx_size_1023);
2494         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2495                             I40E_GLPRT_PRC1522L(hw->port),
2496                             pf->offset_loaded, &os->rx_size_1522,
2497                             &ns->rx_size_1522);
2498         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2499                             I40E_GLPRT_PRC9522L(hw->port),
2500                             pf->offset_loaded, &os->rx_size_big,
2501                             &ns->rx_size_big);
2502         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2503                             pf->offset_loaded, &os->rx_undersize,
2504                             &ns->rx_undersize);
2505         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2506                             pf->offset_loaded, &os->rx_fragments,
2507                             &ns->rx_fragments);
2508         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2509                             pf->offset_loaded, &os->rx_oversize,
2510                             &ns->rx_oversize);
2511         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2512                             pf->offset_loaded, &os->rx_jabber,
2513                             &ns->rx_jabber);
2514         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2515                             I40E_GLPRT_PTC64L(hw->port),
2516                             pf->offset_loaded, &os->tx_size_64,
2517                             &ns->tx_size_64);
2518         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2519                             I40E_GLPRT_PTC127L(hw->port),
2520                             pf->offset_loaded, &os->tx_size_127,
2521                             &ns->tx_size_127);
2522         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2523                             I40E_GLPRT_PTC255L(hw->port),
2524                             pf->offset_loaded, &os->tx_size_255,
2525                             &ns->tx_size_255);
2526         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2527                             I40E_GLPRT_PTC511L(hw->port),
2528                             pf->offset_loaded, &os->tx_size_511,
2529                             &ns->tx_size_511);
2530         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2531                             I40E_GLPRT_PTC1023L(hw->port),
2532                             pf->offset_loaded, &os->tx_size_1023,
2533                             &ns->tx_size_1023);
2534         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2535                             I40E_GLPRT_PTC1522L(hw->port),
2536                             pf->offset_loaded, &os->tx_size_1522,
2537                             &ns->tx_size_1522);
2538         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2539                             I40E_GLPRT_PTC9522L(hw->port),
2540                             pf->offset_loaded, &os->tx_size_big,
2541                             &ns->tx_size_big);
2542         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2543                            pf->offset_loaded,
2544                            &os->fd_sb_match, &ns->fd_sb_match);
2545         /* GLPRT_MSPDC not supported */
2546         /* GLPRT_XEC not supported */
2547
2548         pf->offset_loaded = true;
2549
2550         if (pf->main_vsi)
2551                 i40e_update_vsi_stats(pf->main_vsi);
2552 }
2553
2554 /* Get all statistics of a port */
2555 static void
2556 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2557 {
2558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2561         unsigned i;
2562
2563         /* call read registers - updates values, now write them to struct */
2564         i40e_read_stats_registers(pf, hw);
2565
2566         stats->ipackets = ns->eth.rx_unicast +
2567                         ns->eth.rx_multicast +
2568                         ns->eth.rx_broadcast -
2569                         ns->eth.rx_discards -
2570                         pf->main_vsi->eth_stats.rx_discards;
2571         stats->opackets = ns->eth.tx_unicast +
2572                         ns->eth.tx_multicast +
2573                         ns->eth.tx_broadcast;
2574         stats->ibytes   = ns->eth.rx_bytes;
2575         stats->obytes   = ns->eth.tx_bytes;
2576         stats->oerrors  = ns->eth.tx_errors +
2577                         pf->main_vsi->eth_stats.tx_errors;
2578
2579         /* Rx Errors */
2580         stats->imissed  = ns->eth.rx_discards +
2581                         pf->main_vsi->eth_stats.rx_discards;
2582         stats->ierrors  = ns->crc_errors +
2583                         ns->rx_length_errors + ns->rx_undersize +
2584                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2585
2586         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2587         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2588         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2589         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2590         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2591         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2592         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2593                     ns->eth.rx_unknown_protocol);
2594         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2595         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2596         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2597         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2598         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2599         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2600
2601         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2602                     ns->tx_dropped_link_down);
2603         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2604         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2605                     ns->illegal_bytes);
2606         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2607         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2608                     ns->mac_local_faults);
2609         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2610                     ns->mac_remote_faults);
2611         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2612                     ns->rx_length_errors);
2613         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2614         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2615         for (i = 0; i < 8; i++) {
2616                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2617                                 i, ns->priority_xon_rx[i]);
2618                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2619                                 i, ns->priority_xoff_rx[i]);
2620         }
2621         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2622         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2623         for (i = 0; i < 8; i++) {
2624                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2625                                 i, ns->priority_xon_tx[i]);
2626                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2627                                 i, ns->priority_xoff_tx[i]);
2628                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2629                                 i, ns->priority_xon_2_xoff[i]);
2630         }
2631         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2632         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2633         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2634         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2635         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2636         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2637         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2638         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2639         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2640         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2641         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2642         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2643         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2644         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2645         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2646         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2647         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2648         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2649         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2650                         ns->mac_short_packet_dropped);
2651         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2652                     ns->checksum_error);
2653         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2654         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2655 }
2656
2657 /* Reset the statistics */
2658 static void
2659 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2660 {
2661         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2663
2664         /* Mark PF and VSI stats to update the offset, aka "reset" */
2665         pf->offset_loaded = false;
2666         if (pf->main_vsi)
2667                 pf->main_vsi->offset_loaded = false;
2668
2669         /* read the stats, reading current register values into offset */
2670         i40e_read_stats_registers(pf, hw);
2671 }
2672
2673 static uint32_t
2674 i40e_xstats_calc_num(void)
2675 {
2676         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2677                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2678                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2679 }
2680
2681 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2682                                      struct rte_eth_xstat_name *xstats_names,
2683                                      __rte_unused unsigned limit)
2684 {
2685         unsigned count = 0;
2686         unsigned i, prio;
2687
2688         if (xstats_names == NULL)
2689                 return i40e_xstats_calc_num();
2690
2691         /* Note: limit checked in rte_eth_xstats_names() */
2692
2693         /* Get stats from i40e_eth_stats struct */
2694         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2695                 snprintf(xstats_names[count].name,
2696                          sizeof(xstats_names[count].name),
2697                          "%s", rte_i40e_stats_strings[i].name);
2698                 count++;
2699         }
2700
2701         /* Get individiual stats from i40e_hw_port struct */
2702         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2703                 snprintf(xstats_names[count].name,
2704                         sizeof(xstats_names[count].name),
2705                          "%s", rte_i40e_hw_port_strings[i].name);
2706                 count++;
2707         }
2708
2709         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2710                 for (prio = 0; prio < 8; prio++) {
2711                         snprintf(xstats_names[count].name,
2712                                  sizeof(xstats_names[count].name),
2713                                  "rx_priority%u_%s", prio,
2714                                  rte_i40e_rxq_prio_strings[i].name);
2715                         count++;
2716                 }
2717         }
2718
2719         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2720                 for (prio = 0; prio < 8; prio++) {
2721                         snprintf(xstats_names[count].name,
2722                                  sizeof(xstats_names[count].name),
2723                                  "tx_priority%u_%s", prio,
2724                                  rte_i40e_txq_prio_strings[i].name);
2725                         count++;
2726                 }
2727         }
2728         return count;
2729 }
2730
2731 static int
2732 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2733                     unsigned n)
2734 {
2735         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2736         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2737         unsigned i, count, prio;
2738         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2739
2740         count = i40e_xstats_calc_num();
2741         if (n < count)
2742                 return count;
2743
2744         i40e_read_stats_registers(pf, hw);
2745
2746         if (xstats == NULL)
2747                 return 0;
2748
2749         count = 0;
2750
2751         /* Get stats from i40e_eth_stats struct */
2752         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2753                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2754                         rte_i40e_stats_strings[i].offset);
2755                 xstats[count].id = count;
2756                 count++;
2757         }
2758
2759         /* Get individiual stats from i40e_hw_port struct */
2760         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2761                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2762                         rte_i40e_hw_port_strings[i].offset);
2763                 xstats[count].id = count;
2764                 count++;
2765         }
2766
2767         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2768                 for (prio = 0; prio < 8; prio++) {
2769                         xstats[count].value =
2770                                 *(uint64_t *)(((char *)hw_stats) +
2771                                 rte_i40e_rxq_prio_strings[i].offset +
2772                                 (sizeof(uint64_t) * prio));
2773                         xstats[count].id = count;
2774                         count++;
2775                 }
2776         }
2777
2778         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2779                 for (prio = 0; prio < 8; prio++) {
2780                         xstats[count].value =
2781                                 *(uint64_t *)(((char *)hw_stats) +
2782                                 rte_i40e_txq_prio_strings[i].offset +
2783                                 (sizeof(uint64_t) * prio));
2784                         xstats[count].id = count;
2785                         count++;
2786                 }
2787         }
2788
2789         return count;
2790 }
2791
2792 static int
2793 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2794                                  __rte_unused uint16_t queue_id,
2795                                  __rte_unused uint8_t stat_idx,
2796                                  __rte_unused uint8_t is_rx)
2797 {
2798         PMD_INIT_FUNC_TRACE();
2799
2800         return -ENOSYS;
2801 }
2802
2803 static void
2804 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2805 {
2806         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2807         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         struct i40e_vsi *vsi = pf->main_vsi;
2809
2810         dev_info->max_rx_queues = vsi->nb_qps;
2811         dev_info->max_tx_queues = vsi->nb_qps;
2812         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2813         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2814         dev_info->max_mac_addrs = vsi->max_macaddrs;
2815         dev_info->max_vfs = dev->pci_dev->max_vfs;
2816         dev_info->rx_offload_capa =
2817                 DEV_RX_OFFLOAD_VLAN_STRIP |
2818                 DEV_RX_OFFLOAD_QINQ_STRIP |
2819                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2820                 DEV_RX_OFFLOAD_UDP_CKSUM |
2821                 DEV_RX_OFFLOAD_TCP_CKSUM;
2822         dev_info->tx_offload_capa =
2823                 DEV_TX_OFFLOAD_VLAN_INSERT |
2824                 DEV_TX_OFFLOAD_QINQ_INSERT |
2825                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2826                 DEV_TX_OFFLOAD_UDP_CKSUM |
2827                 DEV_TX_OFFLOAD_TCP_CKSUM |
2828                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2829                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2830                 DEV_TX_OFFLOAD_TCP_TSO |
2831                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2832                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2833                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2834                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2835         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2836                                                 sizeof(uint32_t);
2837         dev_info->reta_size = pf->hash_lut_size;
2838         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2839
2840         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2841                 .rx_thresh = {
2842                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2843                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2844                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2845                 },
2846                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2847                 .rx_drop_en = 0,
2848         };
2849
2850         dev_info->default_txconf = (struct rte_eth_txconf) {
2851                 .tx_thresh = {
2852                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2853                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2854                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2855                 },
2856                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2857                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2858                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2859                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2860         };
2861
2862         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2863                 .nb_max = I40E_MAX_RING_DESC,
2864                 .nb_min = I40E_MIN_RING_DESC,
2865                 .nb_align = I40E_ALIGN_RING_DESC,
2866         };
2867
2868         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2869                 .nb_max = I40E_MAX_RING_DESC,
2870                 .nb_min = I40E_MIN_RING_DESC,
2871                 .nb_align = I40E_ALIGN_RING_DESC,
2872         };
2873
2874         if (pf->flags & I40E_FLAG_VMDQ) {
2875                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2876                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2877                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2878                                                 pf->max_nb_vmdq_vsi;
2879                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2880                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2881                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2882         }
2883
2884         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2885                 /* For XL710 */
2886                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2887         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2888                 /* For XXV710 */
2889                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2890         else
2891                 /* For X710 */
2892                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2893 }
2894
2895 static int
2896 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2897 {
2898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899         struct i40e_vsi *vsi = pf->main_vsi;
2900         PMD_INIT_FUNC_TRACE();
2901
2902         if (on)
2903                 return i40e_vsi_add_vlan(vsi, vlan_id);
2904         else
2905                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2906 }
2907
2908 static int
2909 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2910                    enum rte_vlan_type vlan_type,
2911                    uint16_t tpid)
2912 {
2913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2915         uint64_t reg_r = 0, reg_w = 0;
2916         uint16_t reg_id = 0;
2917         int ret = 0;
2918         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2919
2920         if (pf->support_multi_driver) {
2921                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
2922                 return -ENOTSUP;
2923         }
2924
2925         switch (vlan_type) {
2926         case ETH_VLAN_TYPE_OUTER:
2927                 if (qinq)
2928                         reg_id = 2;
2929                 else
2930                         reg_id = 3;
2931                 break;
2932         case ETH_VLAN_TYPE_INNER:
2933                 if (qinq)
2934                         reg_id = 3;
2935                 else {
2936                         ret = -EINVAL;
2937                         PMD_DRV_LOG(ERR,
2938                                 "Unsupported vlan type in single vlan.\n");
2939                         return ret;
2940                 }
2941                 break;
2942         default:
2943                 ret = -EINVAL;
2944                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2945                 return ret;
2946         }
2947         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2948                                           &reg_r, NULL);
2949         if (ret != I40E_SUCCESS) {
2950                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2951                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2952                 ret = -EIO;
2953                 return ret;
2954         }
2955         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2956                     "0x%08"PRIx64"", reg_id, reg_r);
2957
2958         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2959         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2960         if (reg_r == reg_w) {
2961                 ret = 0;
2962                 PMD_DRV_LOG(DEBUG, "No need to write");
2963                 return ret;
2964         }
2965
2966         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2967                                            reg_w, NULL);
2968         if (ret != I40E_SUCCESS) {
2969                 ret = -EIO;
2970                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2971                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2972                 return ret;
2973         }
2974         PMD_DRV_LOG(DEBUG,
2975                     "Global register 0x%08x is changed with value 0x%08x",
2976                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
2977
2978         i40e_global_cfg_warning(I40E_WARNING_TPID);
2979
2980         return ret;
2981 }
2982
2983 static void
2984 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2985 {
2986         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2987         struct i40e_vsi *vsi = pf->main_vsi;
2988
2989         if (mask & ETH_VLAN_FILTER_MASK) {
2990                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2991                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2992                 else
2993                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2994         }
2995
2996         if (mask & ETH_VLAN_STRIP_MASK) {
2997                 /* Enable or disable VLAN stripping */
2998                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2999                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3000                 else
3001                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3002         }
3003
3004         if (mask & ETH_VLAN_EXTEND_MASK) {
3005                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3006                         i40e_vsi_config_double_vlan(vsi, TRUE);
3007                         /* Set global registers with default ether type value */
3008                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3009                                            ETHER_TYPE_VLAN);
3010                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3011                                            ETHER_TYPE_VLAN);
3012                 }
3013                 else
3014                         i40e_vsi_config_double_vlan(vsi, FALSE);
3015         }
3016 }
3017
3018 static void
3019 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3020                           __rte_unused uint16_t queue,
3021                           __rte_unused int on)
3022 {
3023         PMD_INIT_FUNC_TRACE();
3024 }
3025
3026 static int
3027 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3028 {
3029         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3030         struct i40e_vsi *vsi = pf->main_vsi;
3031         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3032         struct i40e_vsi_vlan_pvid_info info;
3033
3034         memset(&info, 0, sizeof(info));
3035         info.on = on;
3036         if (info.on)
3037                 info.config.pvid = pvid;
3038         else {
3039                 info.config.reject.tagged =
3040                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3041                 info.config.reject.untagged =
3042                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3043         }
3044
3045         return i40e_vsi_vlan_pvid_set(vsi, &info);
3046 }
3047
3048 static int
3049 i40e_dev_led_on(struct rte_eth_dev *dev)
3050 {
3051         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3052         uint32_t mode = i40e_led_get(hw);
3053
3054         if (mode == 0)
3055                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3056
3057         return 0;
3058 }
3059
3060 static int
3061 i40e_dev_led_off(struct rte_eth_dev *dev)
3062 {
3063         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3064         uint32_t mode = i40e_led_get(hw);
3065
3066         if (mode != 0)
3067                 i40e_led_set(hw, 0, false);
3068
3069         return 0;
3070 }
3071
3072 static int
3073 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3074 {
3075         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3077
3078         fc_conf->pause_time = pf->fc_conf.pause_time;
3079
3080         /* read out from register, in case they are modified by other port */
3081         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3082                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3083         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3084                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3085
3086         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3087         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3088
3089          /* Return current mode according to actual setting*/
3090         switch (hw->fc.current_mode) {
3091         case I40E_FC_FULL:
3092                 fc_conf->mode = RTE_FC_FULL;
3093                 break;
3094         case I40E_FC_TX_PAUSE:
3095                 fc_conf->mode = RTE_FC_TX_PAUSE;
3096                 break;
3097         case I40E_FC_RX_PAUSE:
3098                 fc_conf->mode = RTE_FC_RX_PAUSE;
3099                 break;
3100         case I40E_FC_NONE:
3101         default:
3102                 fc_conf->mode = RTE_FC_NONE;
3103         };
3104
3105         return 0;
3106 }
3107
3108 static int
3109 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3110 {
3111         uint32_t mflcn_reg, fctrl_reg, reg;
3112         uint32_t max_high_water;
3113         uint8_t i, aq_failure;
3114         int err;
3115         struct i40e_hw *hw;
3116         struct i40e_pf *pf;
3117         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3118                 [RTE_FC_NONE] = I40E_FC_NONE,
3119                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3120                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3121                 [RTE_FC_FULL] = I40E_FC_FULL
3122         };
3123
3124         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3125
3126         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3127         if ((fc_conf->high_water > max_high_water) ||
3128                         (fc_conf->high_water < fc_conf->low_water)) {
3129                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3130                         "High_water must <= %d.", max_high_water);
3131                 return -EINVAL;
3132         }
3133
3134         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3136         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3137
3138         pf->fc_conf.pause_time = fc_conf->pause_time;
3139         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3140         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3141
3142         PMD_INIT_FUNC_TRACE();
3143
3144         /* All the link flow control related enable/disable register
3145          * configuration is handle by the F/W
3146          */
3147         err = i40e_set_fc(hw, &aq_failure, true);
3148         if (err < 0)
3149                 return -ENOSYS;
3150
3151         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3152                 /* Configure flow control refresh threshold,
3153                  * the value for stat_tx_pause_refresh_timer[8]
3154                  * is used for global pause operation.
3155                  */
3156
3157                 I40E_WRITE_REG(hw,
3158                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3159                                pf->fc_conf.pause_time);
3160
3161                 /* configure the timer value included in transmitted pause
3162                  * frame,
3163                  * the value for stat_tx_pause_quanta[8] is used for global
3164                  * pause operation
3165                  */
3166                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3167                                pf->fc_conf.pause_time);
3168
3169                 fctrl_reg = I40E_READ_REG(hw,
3170                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3171
3172                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3173                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3174                 else
3175                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3176
3177                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3178                                fctrl_reg);
3179         } else {
3180                 /* Configure pause time (2 TCs per register) */
3181                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3182                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3183                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3184
3185                 /* Configure flow control refresh threshold value */
3186                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3187                                pf->fc_conf.pause_time / 2);
3188
3189                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3190
3191                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3192                  *depending on configuration
3193                  */
3194                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3195                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3196                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3197                 } else {
3198                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3199                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3200                 }
3201
3202                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3203         }
3204
3205         if (!pf->support_multi_driver) {
3206                 /* config water marker both based on the packets and bytes */
3207                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3208                                 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3209                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3210                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3211                                 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3212                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3213                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3214                                  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3215                                  << I40E_KILOSHIFT);
3216                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3217                                   pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3218                                   << I40E_KILOSHIFT);
3219                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3220         } else {
3221                 PMD_DRV_LOG(ERR,
3222                             "Water marker configuration is not supported.");
3223         }
3224
3225         I40E_WRITE_FLUSH(hw);
3226
3227         return 0;
3228 }
3229
3230 static int
3231 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3232                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3233 {
3234         PMD_INIT_FUNC_TRACE();
3235
3236         return -ENOSYS;
3237 }
3238
3239 /* Add a MAC address, and update filters */
3240 static void
3241 i40e_macaddr_add(struct rte_eth_dev *dev,
3242                  struct ether_addr *mac_addr,
3243                  __rte_unused uint32_t index,
3244                  uint32_t pool)
3245 {
3246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3247         struct i40e_mac_filter_info mac_filter;
3248         struct i40e_vsi *vsi;
3249         int ret;
3250
3251         /* If VMDQ not enabled or configured, return */
3252         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3253                           !pf->nb_cfg_vmdq_vsi)) {
3254                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3255                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3256                         pool);
3257                 return;
3258         }
3259
3260         if (pool > pf->nb_cfg_vmdq_vsi) {
3261                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3262                                 pool, pf->nb_cfg_vmdq_vsi);
3263                 return;
3264         }
3265
3266         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3267         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3268                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3269         else
3270                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3271
3272         if (pool == 0)
3273                 vsi = pf->main_vsi;
3274         else
3275                 vsi = pf->vmdq[pool - 1].vsi;
3276
3277         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3278         if (ret != I40E_SUCCESS) {
3279                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3280                 return;
3281         }
3282 }
3283
3284 /* Remove a MAC address, and update filters */
3285 static void
3286 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3287 {
3288         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3289         struct i40e_vsi *vsi;
3290         struct rte_eth_dev_data *data = dev->data;
3291         struct ether_addr *macaddr;
3292         int ret;
3293         uint32_t i;
3294         uint64_t pool_sel;
3295
3296         macaddr = &(data->mac_addrs[index]);
3297
3298         pool_sel = dev->data->mac_pool_sel[index];
3299
3300         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3301                 if (pool_sel & (1ULL << i)) {
3302                         if (i == 0)
3303                                 vsi = pf->main_vsi;
3304                         else {
3305                                 /* No VMDQ pool enabled or configured */
3306                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3307                                         (i > pf->nb_cfg_vmdq_vsi)) {
3308                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3309                                                         "/configured");
3310                                         return;
3311                                 }
3312                                 vsi = pf->vmdq[i - 1].vsi;
3313                         }
3314                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3315
3316                         if (ret) {
3317                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3318                                 return;
3319                         }
3320                 }
3321         }
3322 }
3323
3324 /* Set perfect match or hash match of MAC and VLAN for a VF */
3325 static int
3326 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3327                  struct rte_eth_mac_filter *filter,
3328                  bool add)
3329 {
3330         struct i40e_hw *hw;
3331         struct i40e_mac_filter_info mac_filter;
3332         struct ether_addr old_mac;
3333         struct ether_addr *new_mac;
3334         struct i40e_pf_vf *vf = NULL;
3335         uint16_t vf_id;
3336         int ret;
3337
3338         if (pf == NULL) {
3339                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3340                 return -EINVAL;
3341         }
3342         hw = I40E_PF_TO_HW(pf);
3343
3344         if (filter == NULL) {
3345                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3346                 return -EINVAL;
3347         }
3348
3349         new_mac = &filter->mac_addr;
3350
3351         if (is_zero_ether_addr(new_mac)) {
3352                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3353                 return -EINVAL;
3354         }
3355
3356         vf_id = filter->dst_id;
3357
3358         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3359                 PMD_DRV_LOG(ERR, "Invalid argument.");
3360                 return -EINVAL;
3361         }
3362         vf = &pf->vfs[vf_id];
3363
3364         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3365                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3366                 return -EINVAL;
3367         }
3368
3369         if (add) {
3370                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3371                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3372                                 ETHER_ADDR_LEN);
3373                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3374                                  ETHER_ADDR_LEN);
3375
3376                 mac_filter.filter_type = filter->filter_type;
3377                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3378                 if (ret != I40E_SUCCESS) {
3379                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3380                         return -1;
3381                 }
3382                 ether_addr_copy(new_mac, &pf->dev_addr);
3383         } else {
3384                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3385                                 ETHER_ADDR_LEN);
3386                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3387                 if (ret != I40E_SUCCESS) {
3388                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3389                         return -1;
3390                 }
3391
3392                 /* Clear device address as it has been removed */
3393                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3394                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3395         }
3396
3397         return 0;
3398 }
3399
3400 /* MAC filter handle */
3401 static int
3402 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3403                 void *arg)
3404 {
3405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3406         struct rte_eth_mac_filter *filter;
3407         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3408         int ret = I40E_NOT_SUPPORTED;
3409
3410         filter = (struct rte_eth_mac_filter *)(arg);
3411
3412         switch (filter_op) {
3413         case RTE_ETH_FILTER_NOP:
3414                 ret = I40E_SUCCESS;
3415                 break;
3416         case RTE_ETH_FILTER_ADD:
3417                 i40e_pf_disable_irq0(hw);
3418                 if (filter->is_vf)
3419                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3420                 i40e_pf_enable_irq0(hw);
3421                 break;
3422         case RTE_ETH_FILTER_DELETE:
3423                 i40e_pf_disable_irq0(hw);
3424                 if (filter->is_vf)
3425                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3426                 i40e_pf_enable_irq0(hw);
3427                 break;
3428         default:
3429                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3430                 ret = I40E_ERR_PARAM;
3431                 break;
3432         }
3433
3434         return ret;
3435 }
3436
3437 static int
3438 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3439 {
3440         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3441         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3442         int ret;
3443
3444         if (!lut)
3445                 return -EINVAL;
3446
3447         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3448                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3449                                           lut, lut_size);
3450                 if (ret) {
3451                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3452                         return ret;
3453                 }
3454         } else {
3455                 uint32_t *lut_dw = (uint32_t *)lut;
3456                 uint16_t i, lut_size_dw = lut_size / 4;
3457
3458                 for (i = 0; i < lut_size_dw; i++)
3459                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3460         }
3461
3462         return 0;
3463 }
3464
3465 static int
3466 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3467 {
3468         struct i40e_pf *pf;
3469         struct i40e_hw *hw;
3470         int ret;
3471
3472         if (!vsi || !lut)
3473                 return -EINVAL;
3474
3475         pf = I40E_VSI_TO_PF(vsi);
3476         hw = I40E_VSI_TO_HW(vsi);
3477
3478         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3479                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3480                                           lut, lut_size);
3481                 if (ret) {
3482                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3483                         return ret;
3484                 }
3485         } else {
3486                 uint32_t *lut_dw = (uint32_t *)lut;
3487                 uint16_t i, lut_size_dw = lut_size / 4;
3488
3489                 for (i = 0; i < lut_size_dw; i++)
3490                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3491                 I40E_WRITE_FLUSH(hw);
3492         }
3493
3494         return 0;
3495 }
3496
3497 static int
3498 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3499                          struct rte_eth_rss_reta_entry64 *reta_conf,
3500                          uint16_t reta_size)
3501 {
3502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3503         uint16_t i, lut_size = pf->hash_lut_size;
3504         uint16_t idx, shift;
3505         uint8_t *lut;
3506         int ret;
3507
3508         if (reta_size != lut_size ||
3509                 reta_size > ETH_RSS_RETA_SIZE_512) {
3510                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3511                         "(%d) doesn't match the number hardware can supported "
3512                                         "(%d)\n", reta_size, lut_size);
3513                 return -EINVAL;
3514         }
3515
3516         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3517         if (!lut) {
3518                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3519                 return -ENOMEM;
3520         }
3521         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3522         if (ret)
3523                 goto out;
3524         for (i = 0; i < reta_size; i++) {
3525                 idx = i / RTE_RETA_GROUP_SIZE;
3526                 shift = i % RTE_RETA_GROUP_SIZE;
3527                 if (reta_conf[idx].mask & (1ULL << shift))
3528                         lut[i] = reta_conf[idx].reta[shift];
3529         }
3530         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3531
3532 out:
3533         rte_free(lut);
3534
3535         return ret;
3536 }
3537
3538 static int
3539 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3540                         struct rte_eth_rss_reta_entry64 *reta_conf,
3541                         uint16_t reta_size)
3542 {
3543         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3544         uint16_t i, lut_size = pf->hash_lut_size;
3545         uint16_t idx, shift;
3546         uint8_t *lut;
3547         int ret;
3548
3549         if (reta_size != lut_size ||
3550                 reta_size > ETH_RSS_RETA_SIZE_512) {
3551                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3552                         "(%d) doesn't match the number hardware can supported "
3553                                         "(%d)\n", reta_size, lut_size);
3554                 return -EINVAL;
3555         }
3556
3557         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3558         if (!lut) {
3559                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3560                 return -ENOMEM;
3561         }
3562
3563         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3564         if (ret)
3565                 goto out;
3566         for (i = 0; i < reta_size; i++) {
3567                 idx = i / RTE_RETA_GROUP_SIZE;
3568                 shift = i % RTE_RETA_GROUP_SIZE;
3569                 if (reta_conf[idx].mask & (1ULL << shift))
3570                         reta_conf[idx].reta[shift] = lut[i];
3571         }
3572
3573 out:
3574         rte_free(lut);
3575
3576         return ret;
3577 }
3578
3579 /**
3580  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3581  * @hw:   pointer to the HW structure
3582  * @mem:  pointer to mem struct to fill out
3583  * @size: size of memory requested
3584  * @alignment: what to align the allocation to
3585  **/
3586 enum i40e_status_code
3587 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3588                         struct i40e_dma_mem *mem,
3589                         u64 size,
3590                         u32 alignment)
3591 {
3592         const struct rte_memzone *mz = NULL;
3593         char z_name[RTE_MEMZONE_NAMESIZE];
3594
3595         if (!mem)
3596                 return I40E_ERR_PARAM;
3597
3598         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3599         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3600                                          alignment, RTE_PGSIZE_2M);
3601         if (!mz)
3602                 return I40E_ERR_NO_MEMORY;
3603
3604         mem->size = size;
3605         mem->va = mz->addr;
3606         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3607         mem->zone = (const void *)mz;
3608         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3609                     "%"PRIu64, mz->name, mem->pa);
3610
3611         return I40E_SUCCESS;
3612 }
3613
3614 /**
3615  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3616  * @hw:   pointer to the HW structure
3617  * @mem:  ptr to mem struct to free
3618  **/
3619 enum i40e_status_code
3620 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3621                     struct i40e_dma_mem *mem)
3622 {
3623         if (!mem)
3624                 return I40E_ERR_PARAM;
3625
3626         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3627                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3628                     mem->pa);
3629         rte_memzone_free((const struct rte_memzone *)mem->zone);
3630         mem->zone = NULL;
3631         mem->va = NULL;
3632         mem->pa = (u64)0;
3633
3634         return I40E_SUCCESS;
3635 }
3636
3637 /**
3638  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3639  * @hw:   pointer to the HW structure
3640  * @mem:  pointer to mem struct to fill out
3641  * @size: size of memory requested
3642  **/
3643 enum i40e_status_code
3644 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3645                          struct i40e_virt_mem *mem,
3646                          u32 size)
3647 {
3648         if (!mem)
3649                 return I40E_ERR_PARAM;
3650
3651         mem->size = size;
3652         mem->va = rte_zmalloc("i40e", size, 0);
3653
3654         if (mem->va)
3655                 return I40E_SUCCESS;
3656         else
3657                 return I40E_ERR_NO_MEMORY;
3658 }
3659
3660 /**
3661  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3662  * @hw:   pointer to the HW structure
3663  * @mem:  pointer to mem struct to free
3664  **/
3665 enum i40e_status_code
3666 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3667                      struct i40e_virt_mem *mem)
3668 {
3669         if (!mem)
3670                 return I40E_ERR_PARAM;
3671
3672         rte_free(mem->va);
3673         mem->va = NULL;
3674
3675         return I40E_SUCCESS;
3676 }
3677
3678 void
3679 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3680 {
3681         rte_spinlock_init(&sp->spinlock);
3682 }
3683
3684 void
3685 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3686 {
3687         rte_spinlock_lock(&sp->spinlock);
3688 }
3689
3690 void
3691 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3692 {
3693         rte_spinlock_unlock(&sp->spinlock);
3694 }
3695
3696 void
3697 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3698 {
3699         return;
3700 }
3701
3702 /**
3703  * Get the hardware capabilities, which will be parsed
3704  * and saved into struct i40e_hw.
3705  */
3706 static int
3707 i40e_get_cap(struct i40e_hw *hw)
3708 {
3709         struct i40e_aqc_list_capabilities_element_resp *buf;
3710         uint16_t len, size = 0;
3711         int ret;
3712
3713         /* Calculate a huge enough buff for saving response data temporarily */
3714         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3715                                                 I40E_MAX_CAP_ELE_NUM;
3716         buf = rte_zmalloc("i40e", len, 0);
3717         if (!buf) {
3718                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3719                 return I40E_ERR_NO_MEMORY;
3720         }
3721
3722         /* Get, parse the capabilities and save it to hw */
3723         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3724                         i40e_aqc_opc_list_func_capabilities, NULL);
3725         if (ret != I40E_SUCCESS)
3726                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3727
3728         /* Free the temporary buffer after being used */
3729         rte_free(buf);
3730
3731         return ret;
3732 }
3733
3734 static int
3735 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3736 {
3737         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3739         uint16_t qp_count = 0, vsi_count = 0;
3740
3741         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3742                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3743                 return -EINVAL;
3744         }
3745         /* Add the parameter init for LFC */
3746         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3747         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3748         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3749
3750         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3751         pf->max_num_vsi = hw->func_caps.num_vsis;
3752         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3753         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3754         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3755
3756         /* FDir queue/VSI allocation */
3757         pf->fdir_qp_offset = 0;
3758         if (hw->func_caps.fd) {
3759                 pf->flags |= I40E_FLAG_FDIR;
3760                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3761         } else {
3762                 pf->fdir_nb_qps = 0;
3763         }
3764         qp_count += pf->fdir_nb_qps;
3765         vsi_count += 1;
3766
3767         /* LAN queue/VSI allocation */
3768         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3769         if (!hw->func_caps.rss) {
3770                 pf->lan_nb_qps = 1;
3771         } else {
3772                 pf->flags |= I40E_FLAG_RSS;
3773                 if (hw->mac.type == I40E_MAC_X722)
3774                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3775                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3776         }
3777         qp_count += pf->lan_nb_qps;
3778         vsi_count += 1;
3779
3780         /* VF queue/VSI allocation */
3781         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3782         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3783                 pf->flags |= I40E_FLAG_SRIOV;
3784                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3785                 pf->vf_num = dev->pci_dev->max_vfs;
3786                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3787                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3788                             pf->vf_nb_qps * pf->vf_num);
3789         } else {
3790                 pf->vf_nb_qps = 0;
3791                 pf->vf_num = 0;
3792         }
3793         qp_count += pf->vf_nb_qps * pf->vf_num;
3794         vsi_count += pf->vf_num;
3795
3796         /* VMDq queue/VSI allocation */
3797         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3798         pf->vmdq_nb_qps = 0;
3799         pf->max_nb_vmdq_vsi = 0;
3800         if (hw->func_caps.vmdq) {
3801                 if (qp_count < hw->func_caps.num_tx_qp &&
3802                         vsi_count < hw->func_caps.num_vsis) {
3803                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3804                                 qp_count) / pf->vmdq_nb_qp_max;
3805
3806                         /* Limit the maximum number of VMDq vsi to the maximum
3807                          * ethdev can support
3808                          */
3809                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3810                                 hw->func_caps.num_vsis - vsi_count);
3811                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3812                                 ETH_64_POOLS);
3813                         if (pf->max_nb_vmdq_vsi) {
3814                                 pf->flags |= I40E_FLAG_VMDQ;
3815                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3816                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3817                                             "per VMDQ VSI, in total %u queues",
3818                                             pf->max_nb_vmdq_vsi,
3819                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3820                                             pf->max_nb_vmdq_vsi);
3821                         } else {
3822                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3823                                             "VMDq");
3824                         }
3825                 } else {
3826                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3827                 }
3828         }
3829         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3830         vsi_count += pf->max_nb_vmdq_vsi;
3831
3832         if (hw->func_caps.dcb)
3833                 pf->flags |= I40E_FLAG_DCB;
3834
3835         if (qp_count > hw->func_caps.num_tx_qp) {
3836                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3837                             "the hardware maximum %u", qp_count,
3838                             hw->func_caps.num_tx_qp);
3839                 return -EINVAL;
3840         }
3841         if (vsi_count > hw->func_caps.num_vsis) {
3842                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3843                             "the hardware maximum %u", vsi_count,
3844                             hw->func_caps.num_vsis);
3845                 return -EINVAL;
3846         }
3847
3848         return 0;
3849 }
3850
3851 static int
3852 i40e_pf_get_switch_config(struct i40e_pf *pf)
3853 {
3854         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3855         struct i40e_aqc_get_switch_config_resp *switch_config;
3856         struct i40e_aqc_switch_config_element_resp *element;
3857         uint16_t start_seid = 0, num_reported;
3858         int ret;
3859
3860         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3861                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3862         if (!switch_config) {
3863                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3864                 return -ENOMEM;
3865         }
3866
3867         /* Get the switch configurations */
3868         ret = i40e_aq_get_switch_config(hw, switch_config,
3869                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3870         if (ret != I40E_SUCCESS) {
3871                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3872                 goto fail;
3873         }
3874         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3875         if (num_reported != 1) { /* The number should be 1 */
3876                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3877                 goto fail;
3878         }
3879
3880         /* Parse the switch configuration elements */
3881         element = &(switch_config->element[0]);
3882         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3883                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3884                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3885         } else
3886                 PMD_DRV_LOG(INFO, "Unknown element type");
3887
3888 fail:
3889         rte_free(switch_config);
3890
3891         return ret;
3892 }
3893
3894 static int
3895 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3896                         uint32_t num)
3897 {
3898         struct pool_entry *entry;
3899
3900         if (pool == NULL || num == 0)
3901                 return -EINVAL;
3902
3903         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3904         if (entry == NULL) {
3905                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3906                 return -ENOMEM;
3907         }
3908
3909         /* queue heap initialize */
3910         pool->num_free = num;
3911         pool->num_alloc = 0;
3912         pool->base = base;
3913         LIST_INIT(&pool->alloc_list);
3914         LIST_INIT(&pool->free_list);
3915
3916         /* Initialize element  */
3917         entry->base = 0;
3918         entry->len = num;
3919
3920         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3921         return 0;
3922 }
3923
3924 static void
3925 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3926 {
3927         struct pool_entry *entry, *next_entry;
3928
3929         if (pool == NULL)
3930                 return;
3931
3932         for (entry = LIST_FIRST(&pool->alloc_list);
3933                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3934                         entry = next_entry) {
3935                 LIST_REMOVE(entry, next);
3936                 rte_free(entry);
3937         }
3938
3939         for (entry = LIST_FIRST(&pool->free_list);
3940                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3941                         entry = next_entry) {
3942                 LIST_REMOVE(entry, next);
3943                 rte_free(entry);
3944         }
3945
3946         pool->num_free = 0;
3947         pool->num_alloc = 0;
3948         pool->base = 0;
3949         LIST_INIT(&pool->alloc_list);
3950         LIST_INIT(&pool->free_list);
3951 }
3952
3953 static int
3954 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3955                        uint32_t base)
3956 {
3957         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3958         uint32_t pool_offset;
3959         int insert;
3960
3961         if (pool == NULL) {
3962                 PMD_DRV_LOG(ERR, "Invalid parameter");
3963                 return -EINVAL;
3964         }
3965
3966         pool_offset = base - pool->base;
3967         /* Lookup in alloc list */
3968         LIST_FOREACH(entry, &pool->alloc_list, next) {
3969                 if (entry->base == pool_offset) {
3970                         valid_entry = entry;
3971                         LIST_REMOVE(entry, next);
3972                         break;
3973                 }
3974         }
3975
3976         /* Not find, return */
3977         if (valid_entry == NULL) {
3978                 PMD_DRV_LOG(ERR, "Failed to find entry");
3979                 return -EINVAL;
3980         }
3981
3982         /**
3983          * Found it, move it to free list  and try to merge.
3984          * In order to make merge easier, always sort it by qbase.
3985          * Find adjacent prev and last entries.
3986          */
3987         prev = next = NULL;
3988         LIST_FOREACH(entry, &pool->free_list, next) {
3989                 if (entry->base > valid_entry->base) {
3990                         next = entry;
3991                         break;
3992                 }
3993                 prev = entry;
3994         }
3995
3996         insert = 0;
3997         /* Try to merge with next one*/
3998         if (next != NULL) {
3999                 /* Merge with next one */
4000                 if (valid_entry->base + valid_entry->len == next->base) {
4001                         next->base = valid_entry->base;
4002                         next->len += valid_entry->len;
4003                         rte_free(valid_entry);
4004                         valid_entry = next;
4005                         insert = 1;
4006                 }
4007         }
4008
4009         if (prev != NULL) {
4010                 /* Merge with previous one */
4011                 if (prev->base + prev->len == valid_entry->base) {
4012                         prev->len += valid_entry->len;
4013                         /* If it merge with next one, remove next node */
4014                         if (insert == 1) {
4015                                 LIST_REMOVE(valid_entry, next);
4016                                 rte_free(valid_entry);
4017                         } else {
4018                                 rte_free(valid_entry);
4019                                 insert = 1;
4020                         }
4021                 }
4022         }
4023
4024         /* Not find any entry to merge, insert */
4025         if (insert == 0) {
4026                 if (prev != NULL)
4027                         LIST_INSERT_AFTER(prev, valid_entry, next);
4028                 else if (next != NULL)
4029                         LIST_INSERT_BEFORE(next, valid_entry, next);
4030                 else /* It's empty list, insert to head */
4031                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4032         }
4033
4034         pool->num_free += valid_entry->len;
4035         pool->num_alloc -= valid_entry->len;
4036
4037         return 0;
4038 }
4039
4040 static int
4041 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4042                        uint16_t num)
4043 {
4044         struct pool_entry *entry, *valid_entry;
4045
4046         if (pool == NULL || num == 0) {
4047                 PMD_DRV_LOG(ERR, "Invalid parameter");
4048                 return -EINVAL;
4049         }
4050
4051         if (pool->num_free < num) {
4052                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4053                             num, pool->num_free);
4054                 return -ENOMEM;
4055         }
4056
4057         valid_entry = NULL;
4058         /* Lookup  in free list and find most fit one */
4059         LIST_FOREACH(entry, &pool->free_list, next) {
4060                 if (entry->len >= num) {
4061                         /* Find best one */
4062                         if (entry->len == num) {
4063                                 valid_entry = entry;
4064                                 break;
4065                         }
4066                         if (valid_entry == NULL || valid_entry->len > entry->len)
4067                                 valid_entry = entry;
4068                 }
4069         }
4070
4071         /* Not find one to satisfy the request, return */
4072         if (valid_entry == NULL) {
4073                 PMD_DRV_LOG(ERR, "No valid entry found");
4074                 return -ENOMEM;
4075         }
4076         /**
4077          * The entry have equal queue number as requested,
4078          * remove it from alloc_list.
4079          */
4080         if (valid_entry->len == num) {
4081                 LIST_REMOVE(valid_entry, next);
4082         } else {
4083                 /**
4084                  * The entry have more numbers than requested,
4085                  * create a new entry for alloc_list and minus its
4086                  * queue base and number in free_list.
4087                  */
4088                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4089                 if (entry == NULL) {
4090                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4091                                     "resource pool");
4092                         return -ENOMEM;
4093                 }
4094                 entry->base = valid_entry->base;
4095                 entry->len = num;
4096                 valid_entry->base += num;
4097                 valid_entry->len -= num;
4098                 valid_entry = entry;
4099         }
4100
4101         /* Insert it into alloc list, not sorted */
4102         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4103
4104         pool->num_free -= valid_entry->len;
4105         pool->num_alloc += valid_entry->len;
4106
4107         return valid_entry->base + pool->base;
4108 }
4109
4110 /**
4111  * bitmap_is_subset - Check whether src2 is subset of src1
4112  **/
4113 static inline int
4114 bitmap_is_subset(uint8_t src1, uint8_t src2)
4115 {
4116         return !((src1 ^ src2) & src2);
4117 }
4118
4119 static enum i40e_status_code
4120 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4121 {
4122         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4123
4124         /* If DCB is not supported, only default TC is supported */
4125         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4126                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4127                 return I40E_NOT_SUPPORTED;
4128         }
4129
4130         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4131                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4132                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4133                             enabled_tcmap);
4134                 return I40E_NOT_SUPPORTED;
4135         }
4136         return I40E_SUCCESS;
4137 }
4138
4139 int
4140 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4141                                 struct i40e_vsi_vlan_pvid_info *info)
4142 {
4143         struct i40e_hw *hw;
4144         struct i40e_vsi_context ctxt;
4145         uint8_t vlan_flags = 0;
4146         int ret;
4147
4148         if (vsi == NULL || info == NULL) {
4149                 PMD_DRV_LOG(ERR, "invalid parameters");
4150                 return I40E_ERR_PARAM;
4151         }
4152
4153         if (info->on) {
4154                 vsi->info.pvid = info->config.pvid;
4155                 /**
4156                  * If insert pvid is enabled, only tagged pkts are
4157                  * allowed to be sent out.
4158                  */
4159                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4160                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4161         } else {
4162                 vsi->info.pvid = 0;
4163                 if (info->config.reject.tagged == 0)
4164                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4165
4166                 if (info->config.reject.untagged == 0)
4167                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4168         }
4169         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4170                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4171         vsi->info.port_vlan_flags |= vlan_flags;
4172         vsi->info.valid_sections =
4173                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4174         memset(&ctxt, 0, sizeof(ctxt));
4175         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4176         ctxt.seid = vsi->seid;
4177
4178         hw = I40E_VSI_TO_HW(vsi);
4179         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4180         if (ret != I40E_SUCCESS)
4181                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4182
4183         return ret;
4184 }
4185
4186 static int
4187 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4188 {
4189         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4190         int i, ret;
4191         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4192
4193         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4194         if (ret != I40E_SUCCESS)
4195                 return ret;
4196
4197         if (!vsi->seid) {
4198                 PMD_DRV_LOG(ERR, "seid not valid");
4199                 return -EINVAL;
4200         }
4201
4202         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4203         tc_bw_data.tc_valid_bits = enabled_tcmap;
4204         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4205                 tc_bw_data.tc_bw_credits[i] =
4206                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4207
4208         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4209         if (ret != I40E_SUCCESS) {
4210                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4211                 return ret;
4212         }
4213
4214         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4215                                         sizeof(vsi->info.qs_handle));
4216         return I40E_SUCCESS;
4217 }
4218
4219 static enum i40e_status_code
4220 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4221                                  struct i40e_aqc_vsi_properties_data *info,
4222                                  uint8_t enabled_tcmap)
4223 {
4224         enum i40e_status_code ret;
4225         int i, total_tc = 0;
4226         uint16_t qpnum_per_tc, bsf, qp_idx;
4227
4228         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4229         if (ret != I40E_SUCCESS)
4230                 return ret;
4231
4232         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4233                 if (enabled_tcmap & (1 << i))
4234                         total_tc++;
4235         if (total_tc == 0)
4236                 total_tc = 1;
4237         vsi->enabled_tc = enabled_tcmap;
4238
4239         /* Number of queues per enabled TC */
4240         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4241         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4242         bsf = rte_bsf32(qpnum_per_tc);
4243
4244         /* Adjust the queue number to actual queues that can be applied */
4245         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4246                 vsi->nb_qps = qpnum_per_tc * total_tc;
4247
4248         /**
4249          * Configure TC and queue mapping parameters, for enabled TC,
4250          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4251          * default queue will serve it.
4252          */
4253         qp_idx = 0;
4254         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4255                 if (vsi->enabled_tc & (1 << i)) {
4256                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4257                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4258                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4259                         qp_idx += qpnum_per_tc;
4260                 } else
4261                         info->tc_mapping[i] = 0;
4262         }
4263
4264         /* Associate queue number with VSI */
4265         if (vsi->type == I40E_VSI_SRIOV) {
4266                 info->mapping_flags |=
4267                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4268                 for (i = 0; i < vsi->nb_qps; i++)
4269                         info->queue_mapping[i] =
4270                                 rte_cpu_to_le_16(vsi->base_queue + i);
4271         } else {
4272                 info->mapping_flags |=
4273                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4274                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4275         }
4276         info->valid_sections |=
4277                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4278
4279         return I40E_SUCCESS;
4280 }
4281
4282 static int
4283 i40e_veb_release(struct i40e_veb *veb)
4284 {
4285         struct i40e_vsi *vsi;
4286         struct i40e_hw *hw;
4287
4288         if (veb == NULL)
4289                 return -EINVAL;
4290
4291         if (!TAILQ_EMPTY(&veb->head)) {
4292                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4293                 return -EACCES;
4294         }
4295         /* associate_vsi field is NULL for floating VEB */
4296         if (veb->associate_vsi != NULL) {
4297                 vsi = veb->associate_vsi;
4298                 hw = I40E_VSI_TO_HW(vsi);
4299
4300                 vsi->uplink_seid = veb->uplink_seid;
4301                 vsi->veb = NULL;
4302         } else {
4303                 veb->associate_pf->main_vsi->floating_veb = NULL;
4304                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4305         }
4306
4307         i40e_aq_delete_element(hw, veb->seid, NULL);
4308         rte_free(veb);
4309         return I40E_SUCCESS;
4310 }
4311
4312 /* Setup a veb */
4313 static struct i40e_veb *
4314 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4315 {
4316         struct i40e_veb *veb;
4317         int ret;
4318         struct i40e_hw *hw;
4319
4320         if (pf == NULL) {
4321                 PMD_DRV_LOG(ERR,
4322                             "veb setup failed, associated PF shouldn't null");
4323                 return NULL;
4324         }
4325         hw = I40E_PF_TO_HW(pf);
4326
4327         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4328         if (!veb) {
4329                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4330                 goto fail;
4331         }
4332
4333         veb->associate_vsi = vsi;
4334         veb->associate_pf = pf;
4335         TAILQ_INIT(&veb->head);
4336         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4337
4338         /* create floating veb if vsi is NULL */
4339         if (vsi != NULL) {
4340                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4341                                       I40E_DEFAULT_TCMAP, false,
4342                                       &veb->seid, false, NULL);
4343         } else {
4344                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4345                                       true, &veb->seid, false, NULL);
4346         }
4347
4348         if (ret != I40E_SUCCESS) {
4349                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4350                             hw->aq.asq_last_status);
4351                 goto fail;
4352         }
4353         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4354
4355         /* get statistics index */
4356         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4357                                 &veb->stats_idx, NULL, NULL, NULL);
4358         if (ret != I40E_SUCCESS) {
4359                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4360                             hw->aq.asq_last_status);
4361                 goto fail;
4362         }
4363         /* Get VEB bandwidth, to be implemented */
4364         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4365         if (vsi)
4366                 vsi->uplink_seid = veb->seid;
4367
4368         return veb;
4369 fail:
4370         rte_free(veb);
4371         return NULL;
4372 }
4373
4374 int
4375 i40e_vsi_release(struct i40e_vsi *vsi)
4376 {
4377         struct i40e_pf *pf;
4378         struct i40e_hw *hw;
4379         struct i40e_vsi_list *vsi_list;
4380         void *temp;
4381         int ret;
4382         struct i40e_mac_filter *f;
4383         uint16_t user_param;
4384
4385         if (!vsi)
4386                 return I40E_SUCCESS;
4387
4388         if (!vsi->adapter)
4389                 return -EFAULT;
4390
4391         user_param = vsi->user_param;
4392
4393         pf = I40E_VSI_TO_PF(vsi);
4394         hw = I40E_VSI_TO_HW(vsi);
4395
4396         /* VSI has child to attach, release child first */
4397         if (vsi->veb) {
4398                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4399                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4400                                 return -1;
4401                 }
4402                 i40e_veb_release(vsi->veb);
4403         }
4404
4405         if (vsi->floating_veb) {
4406                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4407                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4408                                 return -1;
4409                 }
4410         }
4411
4412         /* Remove all macvlan filters of the VSI */
4413         i40e_vsi_remove_all_macvlan_filter(vsi);
4414         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4415                 rte_free(f);
4416
4417         if (vsi->type != I40E_VSI_MAIN &&
4418             ((vsi->type != I40E_VSI_SRIOV) ||
4419             !pf->floating_veb_list[user_param])) {
4420                 /* Remove vsi from parent's sibling list */
4421                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4422                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4423                         return I40E_ERR_PARAM;
4424                 }
4425                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4426                                 &vsi->sib_vsi_list, list);
4427
4428                 /* Remove all switch element of the VSI */
4429                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4430                 if (ret != I40E_SUCCESS)
4431                         PMD_DRV_LOG(ERR, "Failed to delete element");
4432         }
4433
4434         if ((vsi->type == I40E_VSI_SRIOV) &&
4435             pf->floating_veb_list[user_param]) {
4436                 /* Remove vsi from parent's sibling list */
4437                 if (vsi->parent_vsi == NULL ||
4438                     vsi->parent_vsi->floating_veb == NULL) {
4439                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4440                         return I40E_ERR_PARAM;
4441                 }
4442                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4443                              &vsi->sib_vsi_list, list);
4444
4445                 /* Remove all switch element of the VSI */
4446                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4447                 if (ret != I40E_SUCCESS)
4448                         PMD_DRV_LOG(ERR, "Failed to delete element");
4449         }
4450
4451         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4452
4453         if (vsi->type != I40E_VSI_SRIOV)
4454                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4455         rte_free(vsi);
4456
4457         return I40E_SUCCESS;
4458 }
4459
4460 static int
4461 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4462 {
4463         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4464         struct i40e_aqc_remove_macvlan_element_data def_filter;
4465         struct i40e_mac_filter_info filter;
4466         int ret;
4467
4468         if (vsi->type != I40E_VSI_MAIN)
4469                 return I40E_ERR_CONFIG;
4470         memset(&def_filter, 0, sizeof(def_filter));
4471         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4472                                         ETH_ADDR_LEN);
4473         def_filter.vlan_tag = 0;
4474         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4475                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4476         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4477         if (ret != I40E_SUCCESS) {
4478                 struct i40e_mac_filter *f;
4479                 struct ether_addr *mac;
4480
4481                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4482                             "macvlan filter");
4483                 /* It needs to add the permanent mac into mac list */
4484                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4485                 if (f == NULL) {
4486                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4487                         return I40E_ERR_NO_MEMORY;
4488                 }
4489                 mac = &f->mac_info.mac_addr;
4490                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4491                                 ETH_ADDR_LEN);
4492                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4493                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4494                 vsi->mac_num++;
4495
4496                 return ret;
4497         }
4498         (void)rte_memcpy(&filter.mac_addr,
4499                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4500         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4501         return i40e_vsi_add_mac(vsi, &filter);
4502 }
4503
4504 /*
4505  * i40e_vsi_get_bw_config - Query VSI BW Information
4506  * @vsi: the VSI to be queried
4507  *
4508  * Returns 0 on success, negative value on failure
4509  */
4510 static enum i40e_status_code
4511 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4512 {
4513         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4514         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4515         struct i40e_hw *hw = &vsi->adapter->hw;
4516         i40e_status ret;
4517         int i;
4518         uint32_t bw_max;
4519
4520         memset(&bw_config, 0, sizeof(bw_config));
4521         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4522         if (ret != I40E_SUCCESS) {
4523                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4524                             hw->aq.asq_last_status);
4525                 return ret;
4526         }
4527
4528         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4529         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4530                                         &ets_sla_config, NULL);
4531         if (ret != I40E_SUCCESS) {
4532                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4533                             "configuration %u", hw->aq.asq_last_status);
4534                 return ret;
4535         }
4536
4537         /* store and print out BW info */
4538         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4539         vsi->bw_info.bw_max = bw_config.max_bw;
4540         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4541         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4542         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4543                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4544                      I40E_16_BIT_WIDTH);
4545         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4546                 vsi->bw_info.bw_ets_share_credits[i] =
4547                                 ets_sla_config.share_credits[i];
4548                 vsi->bw_info.bw_ets_credits[i] =
4549                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4550                 /* 4 bits per TC, 4th bit is reserved */
4551                 vsi->bw_info.bw_ets_max[i] =
4552                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4553                                   RTE_LEN2MASK(3, uint8_t));
4554                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4555                             vsi->bw_info.bw_ets_share_credits[i]);
4556                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4557                             vsi->bw_info.bw_ets_credits[i]);
4558                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4559                             vsi->bw_info.bw_ets_max[i]);
4560         }
4561
4562         return I40E_SUCCESS;
4563 }
4564
4565 /* i40e_enable_pf_lb
4566  * @pf: pointer to the pf structure
4567  *
4568  * allow loopback on pf
4569  */
4570 static inline void
4571 i40e_enable_pf_lb(struct i40e_pf *pf)
4572 {
4573         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4574         struct i40e_vsi_context ctxt;
4575         int ret;
4576
4577         /* Use the FW API if FW >= v5.0 */
4578         if (hw->aq.fw_maj_ver < 5) {
4579                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4580                 return;
4581         }
4582
4583         memset(&ctxt, 0, sizeof(ctxt));
4584         ctxt.seid = pf->main_vsi_seid;
4585         ctxt.pf_num = hw->pf_id;
4586         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4587         if (ret) {
4588                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4589                             ret, hw->aq.asq_last_status);
4590                 return;
4591         }
4592         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4593         ctxt.info.valid_sections =
4594                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4595         ctxt.info.switch_id |=
4596                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4597
4598         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4599         if (ret)
4600                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4601                             hw->aq.asq_last_status);
4602 }
4603
4604 /* Setup a VSI */
4605 struct i40e_vsi *
4606 i40e_vsi_setup(struct i40e_pf *pf,
4607                enum i40e_vsi_type type,
4608                struct i40e_vsi *uplink_vsi,
4609                uint16_t user_param)
4610 {
4611         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4612         struct i40e_vsi *vsi;
4613         struct i40e_mac_filter_info filter;
4614         int ret;
4615         struct i40e_vsi_context ctxt;
4616         struct ether_addr broadcast =
4617                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4618
4619         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4620             uplink_vsi == NULL) {
4621                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4622                             "VSI link shouldn't be NULL");
4623                 return NULL;
4624         }
4625
4626         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4627                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4628                             "uplink VSI should be NULL");
4629                 return NULL;
4630         }
4631
4632         /* two situations
4633          * 1.type is not MAIN and uplink vsi is not NULL
4634          * If uplink vsi didn't setup VEB, create one first under veb field
4635          * 2.type is SRIOV and the uplink is NULL
4636          * If floating VEB is NULL, create one veb under floating veb field
4637          */
4638
4639         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4640             uplink_vsi->veb == NULL) {
4641                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4642
4643                 if (uplink_vsi->veb == NULL) {
4644                         PMD_DRV_LOG(ERR, "VEB setup failed");
4645                         return NULL;
4646                 }
4647                 /* set ALLOWLOOPBACk on pf, when veb is created */
4648                 i40e_enable_pf_lb(pf);
4649         }
4650
4651         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4652             pf->main_vsi->floating_veb == NULL) {
4653                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4654
4655                 if (pf->main_vsi->floating_veb == NULL) {
4656                         PMD_DRV_LOG(ERR, "VEB setup failed");
4657                         return NULL;
4658                 }
4659         }
4660
4661         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4662         if (!vsi) {
4663                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4664                 return NULL;
4665         }
4666         TAILQ_INIT(&vsi->mac_list);
4667         vsi->type = type;
4668         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4669         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4670         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4671         vsi->user_param = user_param;
4672         /* Allocate queues */
4673         switch (vsi->type) {
4674         case I40E_VSI_MAIN  :
4675                 vsi->nb_qps = pf->lan_nb_qps;
4676                 break;
4677         case I40E_VSI_SRIOV :
4678                 vsi->nb_qps = pf->vf_nb_qps;
4679                 break;
4680         case I40E_VSI_VMDQ2:
4681                 vsi->nb_qps = pf->vmdq_nb_qps;
4682                 break;
4683         case I40E_VSI_FDIR:
4684                 vsi->nb_qps = pf->fdir_nb_qps;
4685                 break;
4686         default:
4687                 goto fail_mem;
4688         }
4689         /*
4690          * The filter status descriptor is reported in rx queue 0,
4691          * while the tx queue for fdir filter programming has no
4692          * such constraints, can be non-zero queues.
4693          * To simplify it, choose FDIR vsi use queue 0 pair.
4694          * To make sure it will use queue 0 pair, queue allocation
4695          * need be done before this function is called
4696          */
4697         if (type != I40E_VSI_FDIR) {
4698                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4699                         if (ret < 0) {
4700                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4701                                                 vsi->seid, ret);
4702                                 goto fail_mem;
4703                         }
4704                         vsi->base_queue = ret;
4705         } else
4706                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4707
4708         /* VF has MSIX interrupt in VF range, don't allocate here */
4709         if (type == I40E_VSI_MAIN) {
4710                 if (pf->support_multi_driver) {
4711                         /* If support multi-driver, need to use INT0 instead of
4712                          * allocating from msix pool. The Msix pool is init from
4713                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
4714                          * to 1 without calling i40e_res_pool_alloc.
4715                          */
4716                         vsi->msix_intr = 0;
4717                         vsi->nb_msix = 1;
4718                 } else {
4719                         ret = i40e_res_pool_alloc(&pf->msix_pool,
4720                                                   RTE_MIN(vsi->nb_qps,
4721                                                      RTE_MAX_RXTX_INTR_VEC_ID));
4722                         if (ret < 0) {
4723                                 PMD_DRV_LOG(ERR,
4724                                             "VSI MAIN %d get heap failed %d",
4725                                             vsi->seid, ret);
4726                                 goto fail_queue_alloc;
4727                         }
4728                         vsi->msix_intr = ret;
4729                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
4730                                                RTE_MAX_RXTX_INTR_VEC_ID);
4731                 }
4732         } else if (type != I40E_VSI_SRIOV) {
4733                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4734                 if (ret < 0) {
4735                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4736                         goto fail_queue_alloc;
4737                 }
4738                 vsi->msix_intr = ret;
4739                 vsi->nb_msix = 1;
4740         } else {
4741                 vsi->msix_intr = 0;
4742                 vsi->nb_msix = 0;
4743         }
4744
4745         /* Add VSI */
4746         if (type == I40E_VSI_MAIN) {
4747                 /* For main VSI, no need to add since it's default one */
4748                 vsi->uplink_seid = pf->mac_seid;
4749                 vsi->seid = pf->main_vsi_seid;
4750                 /* Bind queues with specific MSIX interrupt */
4751                 /**
4752                  * Needs 2 interrupt at least, one for misc cause which will
4753                  * enabled from OS side, Another for queues binding the
4754                  * interrupt from device side only.
4755                  */
4756
4757                 /* Get default VSI parameters from hardware */
4758                 memset(&ctxt, 0, sizeof(ctxt));
4759                 ctxt.seid = vsi->seid;
4760                 ctxt.pf_num = hw->pf_id;
4761                 ctxt.uplink_seid = vsi->uplink_seid;
4762                 ctxt.vf_num = 0;
4763                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4764                 if (ret != I40E_SUCCESS) {
4765                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4766                         goto fail_msix_alloc;
4767                 }
4768                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4769                         sizeof(struct i40e_aqc_vsi_properties_data));
4770                 vsi->vsi_id = ctxt.vsi_number;
4771                 vsi->info.valid_sections = 0;
4772
4773                 /* Configure tc, enabled TC0 only */
4774                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4775                         I40E_SUCCESS) {
4776                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4777                         goto fail_msix_alloc;
4778                 }
4779
4780                 /* TC, queue mapping */
4781                 memset(&ctxt, 0, sizeof(ctxt));
4782                 vsi->info.valid_sections |=
4783                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4784                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4785                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4786                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4787                         sizeof(struct i40e_aqc_vsi_properties_data));
4788                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4789                                                 I40E_DEFAULT_TCMAP);
4790                 if (ret != I40E_SUCCESS) {
4791                         PMD_DRV_LOG(ERR, "Failed to configure "
4792                                     "TC queue mapping");
4793                         goto fail_msix_alloc;
4794                 }
4795                 ctxt.seid = vsi->seid;
4796                 ctxt.pf_num = hw->pf_id;
4797                 ctxt.uplink_seid = vsi->uplink_seid;
4798                 ctxt.vf_num = 0;
4799
4800                 /* Update VSI parameters */
4801                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4802                 if (ret != I40E_SUCCESS) {
4803                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4804                         goto fail_msix_alloc;
4805                 }
4806
4807                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4808                                                 sizeof(vsi->info.tc_mapping));
4809                 (void)rte_memcpy(&vsi->info.queue_mapping,
4810                                 &ctxt.info.queue_mapping,
4811                         sizeof(vsi->info.queue_mapping));
4812                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4813                 vsi->info.valid_sections = 0;
4814
4815                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4816                                 ETH_ADDR_LEN);
4817
4818                 /**
4819                  * Updating default filter settings are necessary to prevent
4820                  * reception of tagged packets.
4821                  * Some old firmware configurations load a default macvlan
4822                  * filter which accepts both tagged and untagged packets.
4823                  * The updating is to use a normal filter instead if needed.
4824                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4825                  * The firmware with correct configurations load the default
4826                  * macvlan filter which is expected and cannot be removed.
4827                  */
4828                 i40e_update_default_filter_setting(vsi);
4829                 i40e_config_qinq(hw, vsi);
4830         } else if (type == I40E_VSI_SRIOV) {
4831                 memset(&ctxt, 0, sizeof(ctxt));
4832                 /**
4833                  * For other VSI, the uplink_seid equals to uplink VSI's
4834                  * uplink_seid since they share same VEB
4835                  */
4836                 if (uplink_vsi == NULL)
4837                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4838                 else
4839                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4840                 ctxt.pf_num = hw->pf_id;
4841                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4842                 ctxt.uplink_seid = vsi->uplink_seid;
4843                 ctxt.connection_type = 0x1;
4844                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4845
4846                 /* Use the VEB configuration if FW >= v5.0 */
4847                 if (hw->aq.fw_maj_ver >= 5) {
4848                         /* Configure switch ID */
4849                         ctxt.info.valid_sections |=
4850                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4851                         ctxt.info.switch_id =
4852                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4853                 }
4854
4855                 /* Configure port/vlan */
4856                 ctxt.info.valid_sections |=
4857                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4858                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4859                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4860                                                 I40E_DEFAULT_TCMAP);
4861                 if (ret != I40E_SUCCESS) {
4862                         PMD_DRV_LOG(ERR, "Failed to configure "
4863                                     "TC queue mapping");
4864                         goto fail_msix_alloc;
4865                 }
4866                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4867                 ctxt.info.valid_sections |=
4868                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4869                 /**
4870                  * Since VSI is not created yet, only configure parameter,
4871                  * will add vsi below.
4872                  */
4873
4874                 i40e_config_qinq(hw, vsi);
4875         } else if (type == I40E_VSI_VMDQ2) {
4876                 memset(&ctxt, 0, sizeof(ctxt));
4877                 /*
4878                  * For other VSI, the uplink_seid equals to uplink VSI's
4879                  * uplink_seid since they share same VEB
4880                  */
4881                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4882                 ctxt.pf_num = hw->pf_id;
4883                 ctxt.vf_num = 0;
4884                 ctxt.uplink_seid = vsi->uplink_seid;
4885                 ctxt.connection_type = 0x1;
4886                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4887
4888                 ctxt.info.valid_sections |=
4889                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4890                 /* user_param carries flag to enable loop back */
4891                 if (user_param) {
4892                         ctxt.info.switch_id =
4893                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4894                         ctxt.info.switch_id |=
4895                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4896                 }
4897
4898                 /* Configure port/vlan */
4899                 ctxt.info.valid_sections |=
4900                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4901                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4902                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4903                                                 I40E_DEFAULT_TCMAP);
4904                 if (ret != I40E_SUCCESS) {
4905                         PMD_DRV_LOG(ERR, "Failed to configure "
4906                                         "TC queue mapping");
4907                         goto fail_msix_alloc;
4908                 }
4909                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4910                 ctxt.info.valid_sections |=
4911                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4912         } else if (type == I40E_VSI_FDIR) {
4913                 memset(&ctxt, 0, sizeof(ctxt));
4914                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4915                 ctxt.pf_num = hw->pf_id;
4916                 ctxt.vf_num = 0;
4917                 ctxt.uplink_seid = vsi->uplink_seid;
4918                 ctxt.connection_type = 0x1;     /* regular data port */
4919                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4920                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4921                                                 I40E_DEFAULT_TCMAP);
4922                 if (ret != I40E_SUCCESS) {
4923                         PMD_DRV_LOG(ERR, "Failed to configure "
4924                                         "TC queue mapping.");
4925                         goto fail_msix_alloc;
4926                 }
4927                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4928                 ctxt.info.valid_sections |=
4929                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4930         } else {
4931                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4932                 goto fail_msix_alloc;
4933         }
4934
4935         if (vsi->type != I40E_VSI_MAIN) {
4936                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4937                 if (ret != I40E_SUCCESS) {
4938                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4939                                     hw->aq.asq_last_status);
4940                         goto fail_msix_alloc;
4941                 }
4942                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4943                 vsi->info.valid_sections = 0;
4944                 vsi->seid = ctxt.seid;
4945                 vsi->vsi_id = ctxt.vsi_number;
4946                 vsi->sib_vsi_list.vsi = vsi;
4947                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4948                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4949                                           &vsi->sib_vsi_list, list);
4950                 } else {
4951                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4952                                           &vsi->sib_vsi_list, list);
4953                 }
4954         }
4955
4956         /* MAC/VLAN configuration */
4957         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4958         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4959
4960         ret = i40e_vsi_add_mac(vsi, &filter);
4961         if (ret != I40E_SUCCESS) {
4962                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4963                 goto fail_msix_alloc;
4964         }
4965
4966         /* Get VSI BW information */
4967         i40e_vsi_get_bw_config(vsi);
4968         return vsi;
4969 fail_msix_alloc:
4970         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4971 fail_queue_alloc:
4972         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4973 fail_mem:
4974         rte_free(vsi);
4975         return NULL;
4976 }
4977
4978 /* Configure vlan filter on or off */
4979 int
4980 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4981 {
4982         int i, num;
4983         struct i40e_mac_filter *f;
4984         void *temp;
4985         struct i40e_mac_filter_info *mac_filter;
4986         enum rte_mac_filter_type desired_filter;
4987         int ret = I40E_SUCCESS;
4988
4989         if (on) {
4990                 /* Filter to match MAC and VLAN */
4991                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4992         } else {
4993                 /* Filter to match only MAC */
4994                 desired_filter = RTE_MAC_PERFECT_MATCH;
4995         }
4996
4997         num = vsi->mac_num;
4998
4999         mac_filter = rte_zmalloc("mac_filter_info_data",
5000                                  num * sizeof(*mac_filter), 0);
5001         if (mac_filter == NULL) {
5002                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5003                 return I40E_ERR_NO_MEMORY;
5004         }
5005
5006         i = 0;
5007
5008         /* Remove all existing mac */
5009         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5010                 mac_filter[i] = f->mac_info;
5011                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5012                 if (ret) {
5013                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5014                                     on ? "enable" : "disable");
5015                         goto DONE;
5016                 }
5017                 i++;
5018         }
5019
5020         /* Override with new filter */
5021         for (i = 0; i < num; i++) {
5022                 mac_filter[i].filter_type = desired_filter;
5023                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5024                 if (ret) {
5025                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5026                                     on ? "enable" : "disable");
5027                         goto DONE;
5028                 }
5029         }
5030
5031 DONE:
5032         rte_free(mac_filter);
5033         return ret;
5034 }
5035
5036 /* Configure vlan stripping on or off */
5037 int
5038 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5039 {
5040         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5041         struct i40e_vsi_context ctxt;
5042         uint8_t vlan_flags;
5043         int ret = I40E_SUCCESS;
5044
5045         /* Check if it has been already on or off */
5046         if (vsi->info.valid_sections &
5047                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5048                 if (on) {
5049                         if ((vsi->info.port_vlan_flags &
5050                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5051                                 return 0; /* already on */
5052                 } else {
5053                         if ((vsi->info.port_vlan_flags &
5054                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5055                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5056                                 return 0; /* already off */
5057                 }
5058         }
5059
5060         if (on)
5061                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5062         else
5063                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5064         vsi->info.valid_sections =
5065                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5066         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5067         vsi->info.port_vlan_flags |= vlan_flags;
5068         ctxt.seid = vsi->seid;
5069         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5070         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5071         if (ret)
5072                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5073                             on ? "enable" : "disable");
5074
5075         return ret;
5076 }
5077
5078 static int
5079 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5080 {
5081         struct rte_eth_dev_data *data = dev->data;
5082         int ret;
5083         int mask = 0;
5084
5085         /* Apply vlan offload setting */
5086         mask = ETH_VLAN_STRIP_MASK |
5087                ETH_VLAN_FILTER_MASK |
5088                ETH_VLAN_EXTEND_MASK;
5089         i40e_vlan_offload_set(dev, mask);
5090
5091         /* Apply pvid setting */
5092         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5093                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5094         if (ret)
5095                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5096
5097         return ret;
5098 }
5099
5100 static int
5101 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5102 {
5103         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5104
5105         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5106 }
5107
5108 static int
5109 i40e_update_flow_control(struct i40e_hw *hw)
5110 {
5111 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5112         struct i40e_link_status link_status;
5113         uint32_t rxfc = 0, txfc = 0, reg;
5114         uint8_t an_info;
5115         int ret;
5116
5117         memset(&link_status, 0, sizeof(link_status));
5118         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5119         if (ret != I40E_SUCCESS) {
5120                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5121                 goto write_reg; /* Disable flow control */
5122         }
5123
5124         an_info = hw->phy.link_info.an_info;
5125         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5126                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5127                 ret = I40E_ERR_NOT_READY;
5128                 goto write_reg; /* Disable flow control */
5129         }
5130         /**
5131          * If link auto negotiation is enabled, flow control needs to
5132          * be configured according to it
5133          */
5134         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5135         case I40E_LINK_PAUSE_RXTX:
5136                 rxfc = 1;
5137                 txfc = 1;
5138                 hw->fc.current_mode = I40E_FC_FULL;
5139                 break;
5140         case I40E_AQ_LINK_PAUSE_RX:
5141                 rxfc = 1;
5142                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5143                 break;
5144         case I40E_AQ_LINK_PAUSE_TX:
5145                 txfc = 1;
5146                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5147                 break;
5148         default:
5149                 hw->fc.current_mode = I40E_FC_NONE;
5150                 break;
5151         }
5152
5153 write_reg:
5154         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5155                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5156         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5157         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5158         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5159         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5160
5161         return ret;
5162 }
5163
5164 /* PF setup */
5165 static int
5166 i40e_pf_setup(struct i40e_pf *pf)
5167 {
5168         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5169         struct i40e_filter_control_settings settings;
5170         struct i40e_vsi *vsi;
5171         int ret;
5172
5173         /* Clear all stats counters */
5174         pf->offset_loaded = FALSE;
5175         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5176         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5177         pf->internal_rx_bytes = 0;
5178         pf->internal_tx_bytes = 0;
5179         pf->internal_rx_bytes_offset = 0;
5180         pf->internal_tx_bytes_offset = 0;
5181
5182         ret = i40e_pf_get_switch_config(pf);
5183         if (ret != I40E_SUCCESS) {
5184                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5185                 return ret;
5186         }
5187         if (pf->flags & I40E_FLAG_FDIR) {
5188                 /* make queue allocated first, let FDIR use queue pair 0*/
5189                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5190                 if (ret != I40E_FDIR_QUEUE_ID) {
5191                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5192                                     " ret =%d", ret);
5193                         pf->flags &= ~I40E_FLAG_FDIR;
5194                 }
5195         }
5196         /*  main VSI setup */
5197         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5198         if (!vsi) {
5199                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5200                 return I40E_ERR_NOT_READY;
5201         }
5202         pf->main_vsi = vsi;
5203
5204         /* Configure filter control */
5205         memset(&settings, 0, sizeof(settings));
5206         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5207                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5208         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5209                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5210         else {
5211                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5212                                                 hw->func_caps.rss_table_size);
5213                 return I40E_ERR_PARAM;
5214         }
5215         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5216                         "size: %u\n", hw->func_caps.rss_table_size);
5217         pf->hash_lut_size = hw->func_caps.rss_table_size;
5218
5219         /* Enable ethtype and macvlan filters */
5220         settings.enable_ethtype = TRUE;
5221         settings.enable_macvlan = TRUE;
5222         ret = i40e_set_filter_control(hw, &settings);
5223         if (ret)
5224                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5225                                                                 ret);
5226
5227         /* Update flow control according to the auto negotiation */
5228         i40e_update_flow_control(hw);
5229
5230         return I40E_SUCCESS;
5231 }
5232
5233 int
5234 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5235 {
5236         uint32_t reg;
5237         uint16_t j;
5238
5239         /**
5240          * Set or clear TX Queue Disable flags,
5241          * which is required by hardware.
5242          */
5243         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5244         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5245
5246         /* Wait until the request is finished */
5247         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5248                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5249                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5250                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5251                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5252                                                         & 0x1))) {
5253                         break;
5254                 }
5255         }
5256         if (on) {
5257                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5258                         return I40E_SUCCESS; /* already on, skip next steps */
5259
5260                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5261                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5262         } else {
5263                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5264                         return I40E_SUCCESS; /* already off, skip next steps */
5265                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5266         }
5267         /* Write the register */
5268         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5269         /* Check the result */
5270         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5271                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5272                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5273                 if (on) {
5274                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5275                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5276                                 break;
5277                 } else {
5278                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5279                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5280                                 break;
5281                 }
5282         }
5283         /* Check if it is timeout */
5284         if (j >= I40E_CHK_Q_ENA_COUNT) {
5285                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5286                             (on ? "enable" : "disable"), q_idx);
5287                 return I40E_ERR_TIMEOUT;
5288         }
5289
5290         return I40E_SUCCESS;
5291 }
5292
5293 /* Swith on or off the tx queues */
5294 static int
5295 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5296 {
5297         struct rte_eth_dev_data *dev_data = pf->dev_data;
5298         struct i40e_tx_queue *txq;
5299         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5300         uint16_t i;
5301         int ret;
5302
5303         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5304                 txq = dev_data->tx_queues[i];
5305                 /* Don't operate the queue if not configured or
5306                  * if starting only per queue */
5307                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5308                         continue;
5309                 if (on)
5310                         ret = i40e_dev_tx_queue_start(dev, i);
5311                 else
5312                         ret = i40e_dev_tx_queue_stop(dev, i);
5313                 if ( ret != I40E_SUCCESS)
5314                         return ret;
5315         }
5316
5317         return I40E_SUCCESS;
5318 }
5319
5320 int
5321 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5322 {
5323         uint32_t reg;
5324         uint16_t j;
5325
5326         /* Wait until the request is finished */
5327         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5328                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5329                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5330                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5331                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5332                         break;
5333         }
5334
5335         if (on) {
5336                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5337                         return I40E_SUCCESS; /* Already on, skip next steps */
5338                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5339         } else {
5340                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5341                         return I40E_SUCCESS; /* Already off, skip next steps */
5342                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5343         }
5344
5345         /* Write the register */
5346         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5347         /* Check the result */
5348         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5349                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5350                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5351                 if (on) {
5352                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5353                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5354                                 break;
5355                 } else {
5356                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5357                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5358                                 break;
5359                 }
5360         }
5361
5362         /* Check if it is timeout */
5363         if (j >= I40E_CHK_Q_ENA_COUNT) {
5364                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5365                             (on ? "enable" : "disable"), q_idx);
5366                 return I40E_ERR_TIMEOUT;
5367         }
5368
5369         return I40E_SUCCESS;
5370 }
5371 /* Switch on or off the rx queues */
5372 static int
5373 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5374 {
5375         struct rte_eth_dev_data *dev_data = pf->dev_data;
5376         struct i40e_rx_queue *rxq;
5377         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5378         uint16_t i;
5379         int ret;
5380
5381         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5382                 rxq = dev_data->rx_queues[i];
5383                 /* Don't operate the queue if not configured or
5384                  * if starting only per queue */
5385                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5386                         continue;
5387                 if (on)
5388                         ret = i40e_dev_rx_queue_start(dev, i);
5389                 else
5390                         ret = i40e_dev_rx_queue_stop(dev, i);
5391                 if (ret != I40E_SUCCESS)
5392                         return ret;
5393         }
5394
5395         return I40E_SUCCESS;
5396 }
5397
5398 /* Switch on or off all the rx/tx queues */
5399 int
5400 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5401 {
5402         int ret;
5403
5404         if (on) {
5405                 /* enable rx queues before enabling tx queues */
5406                 ret = i40e_dev_switch_rx_queues(pf, on);
5407                 if (ret) {
5408                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5409                         return ret;
5410                 }
5411                 ret = i40e_dev_switch_tx_queues(pf, on);
5412         } else {
5413                 /* Stop tx queues before stopping rx queues */
5414                 ret = i40e_dev_switch_tx_queues(pf, on);
5415                 if (ret) {
5416                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5417                         return ret;
5418                 }
5419                 ret = i40e_dev_switch_rx_queues(pf, on);
5420         }
5421
5422         return ret;
5423 }
5424
5425 /* Initialize VSI for TX */
5426 static int
5427 i40e_dev_tx_init(struct i40e_pf *pf)
5428 {
5429         struct rte_eth_dev_data *data = pf->dev_data;
5430         uint16_t i;
5431         uint32_t ret = I40E_SUCCESS;
5432         struct i40e_tx_queue *txq;
5433
5434         for (i = 0; i < data->nb_tx_queues; i++) {
5435                 txq = data->tx_queues[i];
5436                 if (!txq || !txq->q_set)
5437                         continue;
5438                 ret = i40e_tx_queue_init(txq);
5439                 if (ret != I40E_SUCCESS)
5440                         break;
5441         }
5442         if (ret == I40E_SUCCESS)
5443                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5444                                      ->eth_dev);
5445
5446         return ret;
5447 }
5448
5449 /* Initialize VSI for RX */
5450 static int
5451 i40e_dev_rx_init(struct i40e_pf *pf)
5452 {
5453         struct rte_eth_dev_data *data = pf->dev_data;
5454         int ret = I40E_SUCCESS;
5455         uint16_t i;
5456         struct i40e_rx_queue *rxq;
5457
5458         i40e_pf_config_mq_rx(pf);
5459         for (i = 0; i < data->nb_rx_queues; i++) {
5460                 rxq = data->rx_queues[i];
5461                 if (!rxq || !rxq->q_set)
5462                         continue;
5463
5464                 ret = i40e_rx_queue_init(rxq);
5465                 if (ret != I40E_SUCCESS) {
5466                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5467                                     "initialization");
5468                         break;
5469                 }
5470         }
5471         if (ret == I40E_SUCCESS)
5472                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5473                                      ->eth_dev);
5474
5475         return ret;
5476 }
5477
5478 static int
5479 i40e_dev_rxtx_init(struct i40e_pf *pf)
5480 {
5481         int err;
5482
5483         err = i40e_dev_tx_init(pf);
5484         if (err) {
5485                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5486                 return err;
5487         }
5488         err = i40e_dev_rx_init(pf);
5489         if (err) {
5490                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5491                 return err;
5492         }
5493
5494         return err;
5495 }
5496
5497 static int
5498 i40e_vmdq_setup(struct rte_eth_dev *dev)
5499 {
5500         struct rte_eth_conf *conf = &dev->data->dev_conf;
5501         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5502         int i, err, conf_vsis, j, loop;
5503         struct i40e_vsi *vsi;
5504         struct i40e_vmdq_info *vmdq_info;
5505         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5506         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5507
5508         /*
5509          * Disable interrupt to avoid message from VF. Furthermore, it will
5510          * avoid race condition in VSI creation/destroy.
5511          */
5512         i40e_pf_disable_irq0(hw);
5513
5514         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5515                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5516                 return -ENOTSUP;
5517         }
5518
5519         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5520         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5521                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5522                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5523                         pf->max_nb_vmdq_vsi);
5524                 return -ENOTSUP;
5525         }
5526
5527         if (pf->vmdq != NULL) {
5528                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5529                 return 0;
5530         }
5531
5532         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5533                                 sizeof(*vmdq_info) * conf_vsis, 0);
5534
5535         if (pf->vmdq == NULL) {
5536                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5537                 return -ENOMEM;
5538         }
5539
5540         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5541
5542         /* Create VMDQ VSI */
5543         for (i = 0; i < conf_vsis; i++) {
5544                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5545                                 vmdq_conf->enable_loop_back);
5546                 if (vsi == NULL) {
5547                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5548                         err = -1;
5549                         goto err_vsi_setup;
5550                 }
5551                 vmdq_info = &pf->vmdq[i];
5552                 vmdq_info->pf = pf;
5553                 vmdq_info->vsi = vsi;
5554         }
5555         pf->nb_cfg_vmdq_vsi = conf_vsis;
5556
5557         /* Configure Vlan */
5558         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5559         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5560                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5561                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5562                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5563                                         vmdq_conf->pool_map[i].vlan_id, j);
5564
5565                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5566                                                 vmdq_conf->pool_map[i].vlan_id);
5567                                 if (err) {
5568                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5569                                         err = -1;
5570                                         goto err_vsi_setup;
5571                                 }
5572                         }
5573                 }
5574         }
5575
5576         i40e_pf_enable_irq0(hw);
5577
5578         return 0;
5579
5580 err_vsi_setup:
5581         for (i = 0; i < conf_vsis; i++)
5582                 if (pf->vmdq[i].vsi == NULL)
5583                         break;
5584                 else
5585                         i40e_vsi_release(pf->vmdq[i].vsi);
5586
5587         rte_free(pf->vmdq);
5588         pf->vmdq = NULL;
5589         i40e_pf_enable_irq0(hw);
5590         return err;
5591 }
5592
5593 static void
5594 i40e_stat_update_32(struct i40e_hw *hw,
5595                    uint32_t reg,
5596                    bool offset_loaded,
5597                    uint64_t *offset,
5598                    uint64_t *stat)
5599 {
5600         uint64_t new_data;
5601
5602         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5603         if (!offset_loaded)
5604                 *offset = new_data;
5605
5606         if (new_data >= *offset)
5607                 *stat = (uint64_t)(new_data - *offset);
5608         else
5609                 *stat = (uint64_t)((new_data +
5610                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5611 }
5612
5613 static void
5614 i40e_stat_update_48(struct i40e_hw *hw,
5615                    uint32_t hireg,
5616                    uint32_t loreg,
5617                    bool offset_loaded,
5618                    uint64_t *offset,
5619                    uint64_t *stat)
5620 {
5621         uint64_t new_data;
5622
5623         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5624         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5625                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5626
5627         if (!offset_loaded)
5628                 *offset = new_data;
5629
5630         if (new_data >= *offset)
5631                 *stat = new_data - *offset;
5632         else
5633                 *stat = (uint64_t)((new_data +
5634                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5635
5636         *stat &= I40E_48_BIT_MASK;
5637 }
5638
5639 /* Disable IRQ0 */
5640 void
5641 i40e_pf_disable_irq0(struct i40e_hw *hw)
5642 {
5643         /* Disable all interrupt types */
5644         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5645                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5646         I40E_WRITE_FLUSH(hw);
5647 }
5648
5649 /* Enable IRQ0 */
5650 void
5651 i40e_pf_enable_irq0(struct i40e_hw *hw)
5652 {
5653         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5654                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5655                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5656                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5657         I40E_WRITE_FLUSH(hw);
5658 }
5659
5660 static void
5661 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5662 {
5663         /* read pending request and disable first */
5664         i40e_pf_disable_irq0(hw);
5665         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5666         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5667                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5668
5669         if (no_queue)
5670                 /* Link no queues with irq0 */
5671                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5672                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5673 }
5674
5675 static void
5676 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5677 {
5678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5680         int i;
5681         uint16_t abs_vf_id;
5682         uint32_t index, offset, val;
5683
5684         if (!pf->vfs)
5685                 return;
5686         /**
5687          * Try to find which VF trigger a reset, use absolute VF id to access
5688          * since the reg is global register.
5689          */
5690         for (i = 0; i < pf->vf_num; i++) {
5691                 abs_vf_id = hw->func_caps.vf_base_id + i;
5692                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5693                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5694                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5695                 /* VFR event occured */
5696                 if (val & (0x1 << offset)) {
5697                         int ret;
5698
5699                         /* Clear the event first */
5700                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5701                                                         (0x1 << offset));
5702                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5703                         /**
5704                          * Only notify a VF reset event occured,
5705                          * don't trigger another SW reset
5706                          */
5707                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5708                         if (ret != I40E_SUCCESS)
5709                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5710                 }
5711         }
5712 }
5713
5714 static void
5715 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5716 {
5717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5718         struct i40e_virtchnl_pf_event event;
5719         int i;
5720
5721         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5722         event.event_data.link_event.link_status =
5723                 dev->data->dev_link.link_status;
5724         event.event_data.link_event.link_speed =
5725                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5726
5727         for (i = 0; i < pf->vf_num; i++)
5728                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5729                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5730 }
5731
5732 static void
5733 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5734 {
5735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5736         struct i40e_arq_event_info info;
5737         uint16_t pending, opcode;
5738         int ret;
5739
5740         info.buf_len = I40E_AQ_BUF_SZ;
5741         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5742         if (!info.msg_buf) {
5743                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5744                 return;
5745         }
5746
5747         pending = 1;
5748         while (pending) {
5749                 ret = i40e_clean_arq_element(hw, &info, &pending);
5750
5751                 if (ret != I40E_SUCCESS) {
5752                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5753                                     "aq_err: %u", hw->aq.asq_last_status);
5754                         break;
5755                 }
5756                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5757
5758                 switch (opcode) {
5759                 case i40e_aqc_opc_send_msg_to_pf:
5760                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5761                         i40e_pf_host_handle_vf_msg(dev,
5762                                         rte_le_to_cpu_16(info.desc.retval),
5763                                         rte_le_to_cpu_32(info.desc.cookie_high),
5764                                         rte_le_to_cpu_32(info.desc.cookie_low),
5765                                         info.msg_buf,
5766                                         info.msg_len);
5767                         break;
5768                 case i40e_aqc_opc_get_link_status:
5769                         ret = i40e_dev_link_update(dev, 0);
5770                         if (!ret)
5771                                 _rte_eth_dev_callback_process(dev,
5772                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5773                         break;
5774                 default:
5775                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5776                                     opcode);
5777                         break;
5778                 }
5779         }
5780         rte_free(info.msg_buf);
5781 }
5782
5783 /**
5784  * Interrupt handler triggered by NIC  for handling
5785  * specific interrupt.
5786  *
5787  * @param handle
5788  *  Pointer to interrupt handle.
5789  * @param param
5790  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5791  *
5792  * @return
5793  *  void
5794  */
5795 static void
5796 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5797                            void *param)
5798 {
5799         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5800         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5801         uint32_t icr0;
5802
5803         /* Disable interrupt */
5804         i40e_pf_disable_irq0(hw);
5805
5806         /* read out interrupt causes */
5807         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5808
5809         /* No interrupt event indicated */
5810         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5811                 PMD_DRV_LOG(INFO, "No interrupt event");
5812                 goto done;
5813         }
5814 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5815         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5816                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5817         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5818                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5819         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5820                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5821         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5822                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5823         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5824                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5825         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5826                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5827         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5828                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5829 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5830
5831         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5832                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5833                 i40e_dev_handle_vfr_event(dev);
5834         }
5835         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5836                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5837                 i40e_dev_handle_aq_msg(dev);
5838         }
5839
5840 done:
5841         /* Enable interrupt */
5842         i40e_pf_enable_irq0(hw);
5843         rte_intr_enable(&(dev->pci_dev->intr_handle));
5844 }
5845
5846 static int
5847 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5848                          struct i40e_macvlan_filter *filter,
5849                          int total)
5850 {
5851         int ele_num, ele_buff_size;
5852         int num, actual_num, i;
5853         uint16_t flags;
5854         int ret = I40E_SUCCESS;
5855         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5856         struct i40e_aqc_add_macvlan_element_data *req_list;
5857
5858         if (filter == NULL  || total == 0)
5859                 return I40E_ERR_PARAM;
5860         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5861         ele_buff_size = hw->aq.asq_buf_size;
5862
5863         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5864         if (req_list == NULL) {
5865                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5866                 return I40E_ERR_NO_MEMORY;
5867         }
5868
5869         num = 0;
5870         do {
5871                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5872                 memset(req_list, 0, ele_buff_size);
5873
5874                 for (i = 0; i < actual_num; i++) {
5875                         (void)rte_memcpy(req_list[i].mac_addr,
5876                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5877                         req_list[i].vlan_tag =
5878                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5879
5880                         switch (filter[num + i].filter_type) {
5881                         case RTE_MAC_PERFECT_MATCH:
5882                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5883                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5884                                 break;
5885                         case RTE_MACVLAN_PERFECT_MATCH:
5886                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5887                                 break;
5888                         case RTE_MAC_HASH_MATCH:
5889                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5890                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5891                                 break;
5892                         case RTE_MACVLAN_HASH_MATCH:
5893                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5894                                 break;
5895                         default:
5896                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5897                                 ret = I40E_ERR_PARAM;
5898                                 goto DONE;
5899                         }
5900
5901                         req_list[i].queue_number = 0;
5902
5903                         req_list[i].flags = rte_cpu_to_le_16(flags);
5904                 }
5905
5906                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5907                                                 actual_num, NULL);
5908                 if (ret != I40E_SUCCESS) {
5909                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5910                         goto DONE;
5911                 }
5912                 num += actual_num;
5913         } while (num < total);
5914
5915 DONE:
5916         rte_free(req_list);
5917         return ret;
5918 }
5919
5920 static int
5921 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5922                             struct i40e_macvlan_filter *filter,
5923                             int total)
5924 {
5925         int ele_num, ele_buff_size;
5926         int num, actual_num, i;
5927         uint16_t flags;
5928         int ret = I40E_SUCCESS;
5929         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5930         struct i40e_aqc_remove_macvlan_element_data *req_list;
5931
5932         if (filter == NULL  || total == 0)
5933                 return I40E_ERR_PARAM;
5934
5935         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5936         ele_buff_size = hw->aq.asq_buf_size;
5937
5938         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5939         if (req_list == NULL) {
5940                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5941                 return I40E_ERR_NO_MEMORY;
5942         }
5943
5944         num = 0;
5945         do {
5946                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5947                 memset(req_list, 0, ele_buff_size);
5948
5949                 for (i = 0; i < actual_num; i++) {
5950                         (void)rte_memcpy(req_list[i].mac_addr,
5951                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5952                         req_list[i].vlan_tag =
5953                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5954
5955                         switch (filter[num + i].filter_type) {
5956                         case RTE_MAC_PERFECT_MATCH:
5957                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5958                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5959                                 break;
5960                         case RTE_MACVLAN_PERFECT_MATCH:
5961                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5962                                 break;
5963                         case RTE_MAC_HASH_MATCH:
5964                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5965                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5966                                 break;
5967                         case RTE_MACVLAN_HASH_MATCH:
5968                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5969                                 break;
5970                         default:
5971                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5972                                 ret = I40E_ERR_PARAM;
5973                                 goto DONE;
5974                         }
5975                         req_list[i].flags = rte_cpu_to_le_16(flags);
5976                 }
5977
5978                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5979                                                 actual_num, NULL);
5980                 if (ret != I40E_SUCCESS) {
5981                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5982                         goto DONE;
5983                 }
5984                 num += actual_num;
5985         } while (num < total);
5986
5987 DONE:
5988         rte_free(req_list);
5989         return ret;
5990 }
5991
5992 /* Find out specific MAC filter */
5993 static struct i40e_mac_filter *
5994 i40e_find_mac_filter(struct i40e_vsi *vsi,
5995                          struct ether_addr *macaddr)
5996 {
5997         struct i40e_mac_filter *f;
5998
5999         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6000                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6001                         return f;
6002         }
6003
6004         return NULL;
6005 }
6006
6007 static bool
6008 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6009                          uint16_t vlan_id)
6010 {
6011         uint32_t vid_idx, vid_bit;
6012
6013         if (vlan_id > ETH_VLAN_ID_MAX)
6014                 return 0;
6015
6016         vid_idx = I40E_VFTA_IDX(vlan_id);
6017         vid_bit = I40E_VFTA_BIT(vlan_id);
6018
6019         if (vsi->vfta[vid_idx] & vid_bit)
6020                 return 1;
6021         else
6022                 return 0;
6023 }
6024
6025 static void
6026 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6027                          uint16_t vlan_id, bool on)
6028 {
6029         uint32_t vid_idx, vid_bit;
6030
6031         if (vlan_id > ETH_VLAN_ID_MAX)
6032                 return;
6033
6034         vid_idx = I40E_VFTA_IDX(vlan_id);
6035         vid_bit = I40E_VFTA_BIT(vlan_id);
6036
6037         if (on)
6038                 vsi->vfta[vid_idx] |= vid_bit;
6039         else
6040                 vsi->vfta[vid_idx] &= ~vid_bit;
6041 }
6042
6043 /**
6044  * Find all vlan options for specific mac addr,
6045  * return with actual vlan found.
6046  */
6047 static inline int
6048 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6049                            struct i40e_macvlan_filter *mv_f,
6050                            int num, struct ether_addr *addr)
6051 {
6052         int i;
6053         uint32_t j, k;
6054
6055         /**
6056          * Not to use i40e_find_vlan_filter to decrease the loop time,
6057          * although the code looks complex.
6058           */
6059         if (num < vsi->vlan_num)
6060                 return I40E_ERR_PARAM;
6061
6062         i = 0;
6063         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6064                 if (vsi->vfta[j]) {
6065                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6066                                 if (vsi->vfta[j] & (1 << k)) {
6067                                         if (i > num - 1) {
6068                                                 PMD_DRV_LOG(ERR, "vlan number "
6069                                                             "not match");
6070                                                 return I40E_ERR_PARAM;
6071                                         }
6072                                         (void)rte_memcpy(&mv_f[i].macaddr,
6073                                                         addr, ETH_ADDR_LEN);
6074                                         mv_f[i].vlan_id =
6075                                                 j * I40E_UINT32_BIT_SIZE + k;
6076                                         i++;
6077                                 }
6078                         }
6079                 }
6080         }
6081         return I40E_SUCCESS;
6082 }
6083
6084 static inline int
6085 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6086                            struct i40e_macvlan_filter *mv_f,
6087                            int num,
6088                            uint16_t vlan)
6089 {
6090         int i = 0;
6091         struct i40e_mac_filter *f;
6092
6093         if (num < vsi->mac_num)
6094                 return I40E_ERR_PARAM;
6095
6096         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6097                 if (i > num - 1) {
6098                         PMD_DRV_LOG(ERR, "buffer number not match");
6099                         return I40E_ERR_PARAM;
6100                 }
6101                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6102                                 ETH_ADDR_LEN);
6103                 mv_f[i].vlan_id = vlan;
6104                 mv_f[i].filter_type = f->mac_info.filter_type;
6105                 i++;
6106         }
6107
6108         return I40E_SUCCESS;
6109 }
6110
6111 static int
6112 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6113 {
6114         int i, j, num;
6115         struct i40e_mac_filter *f;
6116         struct i40e_macvlan_filter *mv_f;
6117         int ret = I40E_SUCCESS;
6118
6119         if (vsi == NULL || vsi->mac_num == 0)
6120                 return I40E_ERR_PARAM;
6121
6122         /* Case that no vlan is set */
6123         if (vsi->vlan_num == 0)
6124                 num = vsi->mac_num;
6125         else
6126                 num = vsi->mac_num * vsi->vlan_num;
6127
6128         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6129         if (mv_f == NULL) {
6130                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6131                 return I40E_ERR_NO_MEMORY;
6132         }
6133
6134         i = 0;
6135         if (vsi->vlan_num == 0) {
6136                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6137                         (void)rte_memcpy(&mv_f[i].macaddr,
6138                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6139                         mv_f[i].filter_type = f->mac_info.filter_type;
6140                         mv_f[i].vlan_id = 0;
6141                         i++;
6142                 }
6143         } else {
6144                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6145                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6146                                         vsi->vlan_num, &f->mac_info.mac_addr);
6147                         if (ret != I40E_SUCCESS)
6148                                 goto DONE;
6149                         for (j = i; j < i + vsi->vlan_num; j++)
6150                                 mv_f[j].filter_type = f->mac_info.filter_type;
6151                         i += vsi->vlan_num;
6152                 }
6153         }
6154
6155         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6156 DONE:
6157         rte_free(mv_f);
6158
6159         return ret;
6160 }
6161
6162 int
6163 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6164 {
6165         struct i40e_macvlan_filter *mv_f;
6166         int mac_num;
6167         int ret = I40E_SUCCESS;
6168
6169         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6170                 return I40E_ERR_PARAM;
6171
6172         /* If it's already set, just return */
6173         if (i40e_find_vlan_filter(vsi,vlan))
6174                 return I40E_SUCCESS;
6175
6176         mac_num = vsi->mac_num;
6177
6178         if (mac_num == 0) {
6179                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6180                 return I40E_ERR_PARAM;
6181         }
6182
6183         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6184
6185         if (mv_f == NULL) {
6186                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6187                 return I40E_ERR_NO_MEMORY;
6188         }
6189
6190         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6191
6192         if (ret != I40E_SUCCESS)
6193                 goto DONE;
6194
6195         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6196
6197         if (ret != I40E_SUCCESS)
6198                 goto DONE;
6199
6200         i40e_set_vlan_filter(vsi, vlan, 1);
6201
6202         vsi->vlan_num++;
6203         ret = I40E_SUCCESS;
6204 DONE:
6205         rte_free(mv_f);
6206         return ret;
6207 }
6208
6209 int
6210 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6211 {
6212         struct i40e_macvlan_filter *mv_f;
6213         int mac_num;
6214         int ret = I40E_SUCCESS;
6215
6216         /**
6217          * Vlan 0 is the generic filter for untagged packets
6218          * and can't be removed.
6219          */
6220         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6221                 return I40E_ERR_PARAM;
6222
6223         /* If can't find it, just return */
6224         if (!i40e_find_vlan_filter(vsi, vlan))
6225                 return I40E_ERR_PARAM;
6226
6227         mac_num = vsi->mac_num;
6228
6229         if (mac_num == 0) {
6230                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6231                 return I40E_ERR_PARAM;
6232         }
6233
6234         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6235
6236         if (mv_f == NULL) {
6237                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6238                 return I40E_ERR_NO_MEMORY;
6239         }
6240
6241         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6242
6243         if (ret != I40E_SUCCESS)
6244                 goto DONE;
6245
6246         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6247
6248         if (ret != I40E_SUCCESS)
6249                 goto DONE;
6250
6251         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6252         if (vsi->vlan_num == 1) {
6253                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6254                 if (ret != I40E_SUCCESS)
6255                         goto DONE;
6256
6257                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6258                 if (ret != I40E_SUCCESS)
6259                         goto DONE;
6260         }
6261
6262         i40e_set_vlan_filter(vsi, vlan, 0);
6263
6264         vsi->vlan_num--;
6265         ret = I40E_SUCCESS;
6266 DONE:
6267         rte_free(mv_f);
6268         return ret;
6269 }
6270
6271 int
6272 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6273 {
6274         struct i40e_mac_filter *f;
6275         struct i40e_macvlan_filter *mv_f;
6276         int i, vlan_num = 0;
6277         int ret = I40E_SUCCESS;
6278
6279         /* If it's add and we've config it, return */
6280         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6281         if (f != NULL)
6282                 return I40E_SUCCESS;
6283         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6284                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6285
6286                 /**
6287                  * If vlan_num is 0, that's the first time to add mac,
6288                  * set mask for vlan_id 0.
6289                  */
6290                 if (vsi->vlan_num == 0) {
6291                         i40e_set_vlan_filter(vsi, 0, 1);
6292                         vsi->vlan_num = 1;
6293                 }
6294                 vlan_num = vsi->vlan_num;
6295         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6296                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6297                 vlan_num = 1;
6298
6299         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6300         if (mv_f == NULL) {
6301                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6302                 return I40E_ERR_NO_MEMORY;
6303         }
6304
6305         for (i = 0; i < vlan_num; i++) {
6306                 mv_f[i].filter_type = mac_filter->filter_type;
6307                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6308                                 ETH_ADDR_LEN);
6309         }
6310
6311         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6312                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6313                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6314                                         &mac_filter->mac_addr);
6315                 if (ret != I40E_SUCCESS)
6316                         goto DONE;
6317         }
6318
6319         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6320         if (ret != I40E_SUCCESS)
6321                 goto DONE;
6322
6323         /* Add the mac addr into mac list */
6324         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6325         if (f == NULL) {
6326                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6327                 ret = I40E_ERR_NO_MEMORY;
6328                 goto DONE;
6329         }
6330         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6331                         ETH_ADDR_LEN);
6332         f->mac_info.filter_type = mac_filter->filter_type;
6333         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6334         vsi->mac_num++;
6335
6336         ret = I40E_SUCCESS;
6337 DONE:
6338         rte_free(mv_f);
6339
6340         return ret;
6341 }
6342
6343 int
6344 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6345 {
6346         struct i40e_mac_filter *f;
6347         struct i40e_macvlan_filter *mv_f;
6348         int i, vlan_num;
6349         enum rte_mac_filter_type filter_type;
6350         int ret = I40E_SUCCESS;
6351
6352         /* Can't find it, return an error */
6353         f = i40e_find_mac_filter(vsi, addr);
6354         if (f == NULL)
6355                 return I40E_ERR_PARAM;
6356
6357         vlan_num = vsi->vlan_num;
6358         filter_type = f->mac_info.filter_type;
6359         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6360                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6361                 if (vlan_num == 0) {
6362                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6363                         return I40E_ERR_PARAM;
6364                 }
6365         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6366                         filter_type == RTE_MAC_HASH_MATCH)
6367                 vlan_num = 1;
6368
6369         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6370         if (mv_f == NULL) {
6371                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6372                 return I40E_ERR_NO_MEMORY;
6373         }
6374
6375         for (i = 0; i < vlan_num; i++) {
6376                 mv_f[i].filter_type = filter_type;
6377                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6378                                 ETH_ADDR_LEN);
6379         }
6380         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6381                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6382                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6383                 if (ret != I40E_SUCCESS)
6384                         goto DONE;
6385         }
6386
6387         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6388         if (ret != I40E_SUCCESS)
6389                 goto DONE;
6390
6391         /* Remove the mac addr into mac list */
6392         TAILQ_REMOVE(&vsi->mac_list, f, next);
6393         rte_free(f);
6394         vsi->mac_num--;
6395
6396         ret = I40E_SUCCESS;
6397 DONE:
6398         rte_free(mv_f);
6399         return ret;
6400 }
6401
6402 /* Configure hash enable flags for RSS */
6403 uint64_t
6404 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6405 {
6406         uint64_t hena = 0;
6407
6408         if (!flags)
6409                 return hena;
6410
6411         if (flags & ETH_RSS_FRAG_IPV4)
6412                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6413         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6414                 if (type == I40E_MAC_X722) {
6415                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6416                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6417                 } else
6418                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6419         }
6420         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6421                 if (type == I40E_MAC_X722) {
6422                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6423                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6424                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6425                 } else
6426                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6427         }
6428         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6429                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6430         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6431                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6432         if (flags & ETH_RSS_FRAG_IPV6)
6433                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6434         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6435                 if (type == I40E_MAC_X722) {
6436                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6437                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6438                 } else
6439                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6440         }
6441         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6442                 if (type == I40E_MAC_X722) {
6443                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6444                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6445                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6446                 } else
6447                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6448         }
6449         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6450                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6451         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6452                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6453         if (flags & ETH_RSS_L2_PAYLOAD)
6454                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6455
6456         return hena;
6457 }
6458
6459 /* Parse the hash enable flags */
6460 uint64_t
6461 i40e_parse_hena(uint64_t flags)
6462 {
6463         uint64_t rss_hf = 0;
6464
6465         if (!flags)
6466                 return rss_hf;
6467         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6468                 rss_hf |= ETH_RSS_FRAG_IPV4;
6469         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6470                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6471 #ifdef X722_SUPPORT
6472         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6473                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6474 #endif
6475         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6476                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6477 #ifdef X722_SUPPORT
6478         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6479                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6480         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6481                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6482 #endif
6483         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6484                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6485         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6486                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6487         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6488                 rss_hf |= ETH_RSS_FRAG_IPV6;
6489         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6490                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6491 #ifdef X722_SUPPORT
6492         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6493                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6494 #endif
6495         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6496                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6497 #ifdef X722_SUPPORT
6498         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6499                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6500         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6501                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6502 #endif
6503         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6504                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6505         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6506                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6507         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6508                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6509
6510         return rss_hf;
6511 }
6512
6513 /* Disable RSS */
6514 static void
6515 i40e_pf_disable_rss(struct i40e_pf *pf)
6516 {
6517         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6518         uint64_t hena;
6519
6520         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6521         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6522         if (hw->mac.type == I40E_MAC_X722)
6523                 hena &= ~I40E_RSS_HENA_ALL_X722;
6524         else
6525                 hena &= ~I40E_RSS_HENA_ALL;
6526         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6527         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6528         I40E_WRITE_FLUSH(hw);
6529 }
6530
6531 static int
6532 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6533 {
6534         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6535         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6536         int ret = 0;
6537
6538         if (!key || key_len == 0) {
6539                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6540                 return 0;
6541         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6542                 sizeof(uint32_t)) {
6543                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6544                 return -EINVAL;
6545         }
6546
6547         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6548                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6549                         (struct i40e_aqc_get_set_rss_key_data *)key;
6550
6551                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6552                 if (ret)
6553                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6554                                      "via AQ");
6555         } else {
6556                 uint32_t *hash_key = (uint32_t *)key;
6557                 uint16_t i;
6558
6559                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6560                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6561                 I40E_WRITE_FLUSH(hw);
6562         }
6563
6564         return ret;
6565 }
6566
6567 static int
6568 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6569 {
6570         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6571         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6572         int ret;
6573
6574         if (!key || !key_len)
6575                 return -EINVAL;
6576
6577         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6578                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6579                         (struct i40e_aqc_get_set_rss_key_data *)key);
6580                 if (ret) {
6581                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6582                         return ret;
6583                 }
6584         } else {
6585                 uint32_t *key_dw = (uint32_t *)key;
6586                 uint16_t i;
6587
6588                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6589                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6590         }
6591         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6592
6593         return 0;
6594 }
6595
6596 static int
6597 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6598 {
6599         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6600         uint64_t rss_hf;
6601         uint64_t hena;
6602         int ret;
6603
6604         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6605                                rss_conf->rss_key_len);
6606         if (ret)
6607                 return ret;
6608
6609         rss_hf = rss_conf->rss_hf;
6610         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6611         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6612         if (hw->mac.type == I40E_MAC_X722)
6613                 hena &= ~I40E_RSS_HENA_ALL_X722;
6614         else
6615                 hena &= ~I40E_RSS_HENA_ALL;
6616         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6617         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6618         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6619         I40E_WRITE_FLUSH(hw);
6620
6621         return 0;
6622 }
6623
6624 static int
6625 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6626                          struct rte_eth_rss_conf *rss_conf)
6627 {
6628         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6630         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6631         uint64_t hena;
6632
6633         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6634         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6635         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6636                  ? I40E_RSS_HENA_ALL_X722
6637                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6638                 if (rss_hf != 0) /* Enable RSS */
6639                         return -EINVAL;
6640                 return 0; /* Nothing to do */
6641         }
6642         /* RSS enabled */
6643         if (rss_hf == 0) /* Disable RSS */
6644                 return -EINVAL;
6645
6646         return i40e_hw_rss_hash_set(pf, rss_conf);
6647 }
6648
6649 static int
6650 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6651                            struct rte_eth_rss_conf *rss_conf)
6652 {
6653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6655         uint64_t hena;
6656
6657         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6658                          &rss_conf->rss_key_len);
6659
6660         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6661         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6662         rss_conf->rss_hf = i40e_parse_hena(hena);
6663
6664         return 0;
6665 }
6666
6667 static int
6668 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6669 {
6670         switch (filter_type) {
6671         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6672                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6673                 break;
6674         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6675                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6676                 break;
6677         case RTE_TUNNEL_FILTER_IMAC_TENID:
6678                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6679                 break;
6680         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6681                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6682                 break;
6683         case ETH_TUNNEL_FILTER_IMAC:
6684                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6685                 break;
6686         case ETH_TUNNEL_FILTER_OIP:
6687                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6688                 break;
6689         case ETH_TUNNEL_FILTER_IIP:
6690                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6691                 break;
6692         default:
6693                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6694                 return -EINVAL;
6695         }
6696
6697         return 0;
6698 }
6699
6700 static int
6701 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6702                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6703                         uint8_t add)
6704 {
6705         uint16_t ip_type;
6706         uint32_t ipv4_addr, ipv4_addr_le;
6707         uint8_t i, tun_type = 0;
6708         /* internal varialbe to convert ipv6 byte order */
6709         uint32_t convert_ipv6[4];
6710         int val, ret = 0;
6711         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6712         struct i40e_vsi *vsi = pf->main_vsi;
6713         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6714         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6715
6716         cld_filter = rte_zmalloc("tunnel_filter",
6717                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6718                 0);
6719
6720         if (NULL == cld_filter) {
6721                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6722                 return -EINVAL;
6723         }
6724         pfilter = cld_filter;
6725
6726         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6727         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6728
6729         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6730         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6731                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6732                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6733                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
6734                 rte_memcpy(&pfilter->ipaddr.v4.data,
6735                                 &ipv4_addr_le,
6736                                 sizeof(pfilter->ipaddr.v4.data));
6737         } else {
6738                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6739                 for (i = 0; i < 4; i++) {
6740                         convert_ipv6[i] =
6741                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6742                 }
6743                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6744                                 sizeof(pfilter->ipaddr.v6.data));
6745         }
6746
6747         /* check tunneled type */
6748         switch (tunnel_filter->tunnel_type) {
6749         case RTE_TUNNEL_TYPE_VXLAN:
6750                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6751                 break;
6752         case RTE_TUNNEL_TYPE_NVGRE:
6753                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6754                 break;
6755         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6756                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6757                 break;
6758         default:
6759                 /* Other tunnel types is not supported. */
6760                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6761                 rte_free(cld_filter);
6762                 return -EINVAL;
6763         }
6764
6765         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6766                                                 &pfilter->flags);
6767         if (val < 0) {
6768                 rte_free(cld_filter);
6769                 return -EINVAL;
6770         }
6771
6772         pfilter->flags |= rte_cpu_to_le_16(
6773                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6774                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6775         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6776         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6777
6778         if (add)
6779                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6780         else
6781                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6782                                                 cld_filter, 1);
6783
6784         rte_free(cld_filter);
6785         return ret;
6786 }
6787
6788 static int
6789 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6790 {
6791         uint8_t i;
6792
6793         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6794                 if (pf->vxlan_ports[i] == port)
6795                         return i;
6796         }
6797
6798         return -1;
6799 }
6800
6801 static int
6802 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6803 {
6804         int  idx, ret;
6805         uint8_t filter_idx;
6806         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6807
6808         idx = i40e_get_vxlan_port_idx(pf, port);
6809
6810         /* Check if port already exists */
6811         if (idx >= 0) {
6812                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6813                 return -EINVAL;
6814         }
6815
6816         /* Now check if there is space to add the new port */
6817         idx = i40e_get_vxlan_port_idx(pf, 0);
6818         if (idx < 0) {
6819                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6820                         "not adding port %d", port);
6821                 return -ENOSPC;
6822         }
6823
6824         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6825                                         &filter_idx, NULL);
6826         if (ret < 0) {
6827                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6828                 return -1;
6829         }
6830
6831         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6832                          port,  filter_idx);
6833
6834         /* New port: add it and mark its index in the bitmap */
6835         pf->vxlan_ports[idx] = port;
6836         pf->vxlan_bitmap |= (1 << idx);
6837
6838         if (!(pf->flags & I40E_FLAG_VXLAN))
6839                 pf->flags |= I40E_FLAG_VXLAN;
6840
6841         return 0;
6842 }
6843
6844 static int
6845 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6846 {
6847         int idx;
6848         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6849
6850         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6851                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6852                 return -EINVAL;
6853         }
6854
6855         idx = i40e_get_vxlan_port_idx(pf, port);
6856
6857         if (idx < 0) {
6858                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6859                 return -EINVAL;
6860         }
6861
6862         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6863                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6864                 return -1;
6865         }
6866
6867         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6868                         port, idx);
6869
6870         pf->vxlan_ports[idx] = 0;
6871         pf->vxlan_bitmap &= ~(1 << idx);
6872
6873         if (!pf->vxlan_bitmap)
6874                 pf->flags &= ~I40E_FLAG_VXLAN;
6875
6876         return 0;
6877 }
6878
6879 /* Add UDP tunneling port */
6880 static int
6881 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6882                              struct rte_eth_udp_tunnel *udp_tunnel)
6883 {
6884         int ret = 0;
6885         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6886
6887         if (udp_tunnel == NULL)
6888                 return -EINVAL;
6889
6890         switch (udp_tunnel->prot_type) {
6891         case RTE_TUNNEL_TYPE_VXLAN:
6892                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6893                 break;
6894
6895         case RTE_TUNNEL_TYPE_GENEVE:
6896         case RTE_TUNNEL_TYPE_TEREDO:
6897                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6898                 ret = -1;
6899                 break;
6900
6901         default:
6902                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6903                 ret = -1;
6904                 break;
6905         }
6906
6907         return ret;
6908 }
6909
6910 /* Remove UDP tunneling port */
6911 static int
6912 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6913                              struct rte_eth_udp_tunnel *udp_tunnel)
6914 {
6915         int ret = 0;
6916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6917
6918         if (udp_tunnel == NULL)
6919                 return -EINVAL;
6920
6921         switch (udp_tunnel->prot_type) {
6922         case RTE_TUNNEL_TYPE_VXLAN:
6923                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6924                 break;
6925         case RTE_TUNNEL_TYPE_GENEVE:
6926         case RTE_TUNNEL_TYPE_TEREDO:
6927                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6928                 ret = -1;
6929                 break;
6930         default:
6931                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6932                 ret = -1;
6933                 break;
6934         }
6935
6936         return ret;
6937 }
6938
6939 /* Calculate the maximum number of contiguous PF queues that are configured */
6940 static int
6941 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6942 {
6943         struct rte_eth_dev_data *data = pf->dev_data;
6944         int i, num;
6945         struct i40e_rx_queue *rxq;
6946
6947         num = 0;
6948         for (i = 0; i < pf->lan_nb_qps; i++) {
6949                 rxq = data->rx_queues[i];
6950                 if (rxq && rxq->q_set)
6951                         num++;
6952                 else
6953                         break;
6954         }
6955
6956         return num;
6957 }
6958
6959 /* Configure RSS */
6960 static int
6961 i40e_pf_config_rss(struct i40e_pf *pf)
6962 {
6963         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6964         struct rte_eth_rss_conf rss_conf;
6965         uint32_t i, lut = 0;
6966         uint16_t j, num;
6967
6968         /*
6969          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6970          * It's necessary to calulate the actual PF queues that are configured.
6971          */
6972         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6973                 num = i40e_pf_calc_configured_queues_num(pf);
6974         else
6975                 num = pf->dev_data->nb_rx_queues;
6976
6977         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6978         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6979                         num);
6980
6981         if (num == 0) {
6982                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6983                 return -ENOTSUP;
6984         }
6985
6986         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6987                 if (j == num)
6988                         j = 0;
6989                 lut = (lut << 8) | (j & ((0x1 <<
6990                         hw->func_caps.rss_table_entry_width) - 1));
6991                 if ((i & 3) == 3)
6992                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6993         }
6994
6995         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6996         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6997                 i40e_pf_disable_rss(pf);
6998                 return 0;
6999         }
7000         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7001                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7002                 /* Random default keys */
7003                 static uint32_t rss_key_default[] = {0x6b793944,
7004                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7005                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7006                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7007
7008                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7009                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7010                                                         sizeof(uint32_t);
7011         }
7012
7013         return i40e_hw_rss_hash_set(pf, &rss_conf);
7014 }
7015
7016 static int
7017 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7018                                struct rte_eth_tunnel_filter_conf *filter)
7019 {
7020         if (pf == NULL || filter == NULL) {
7021                 PMD_DRV_LOG(ERR, "Invalid parameter");
7022                 return -EINVAL;
7023         }
7024
7025         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7026                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7027                 return -EINVAL;
7028         }
7029
7030         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7031                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7032                 return -EINVAL;
7033         }
7034
7035         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7036                 (is_zero_ether_addr(&filter->outer_mac))) {
7037                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7038                 return -EINVAL;
7039         }
7040
7041         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7042                 (is_zero_ether_addr(&filter->inner_mac))) {
7043                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7044                 return -EINVAL;
7045         }
7046
7047         return 0;
7048 }
7049
7050 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7051 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7052 static int
7053 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7054 {
7055         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7056         uint32_t val, reg;
7057         int ret = -EINVAL;
7058
7059         if (pf->support_multi_driver) {
7060                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
7061                 return -ENOTSUP;
7062         }
7063
7064         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7065         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7066
7067         if (len == 3) {
7068                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7069         } else if (len == 4) {
7070                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7071         } else {
7072                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7073                 return ret;
7074         }
7075
7076         if (reg != val) {
7077                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7078                                                    reg, NULL);
7079                 if (ret != 0)
7080                         return ret;
7081                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
7082                             "with value 0x%08x",
7083                             I40E_GL_PRS_FVBM(2), reg);
7084                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
7085         } else {
7086                 ret = 0;
7087         }
7088         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7089                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7090
7091         return ret;
7092 }
7093
7094 static int
7095 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7096 {
7097         int ret = -EINVAL;
7098
7099         if (!hw || !cfg)
7100                 return -EINVAL;
7101
7102         switch (cfg->cfg_type) {
7103         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7104                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7105                 break;
7106         default:
7107                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7108                 break;
7109         }
7110
7111         return ret;
7112 }
7113
7114 static int
7115 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7116                                enum rte_filter_op filter_op,
7117                                void *arg)
7118 {
7119         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7120         int ret = I40E_ERR_PARAM;
7121
7122         switch (filter_op) {
7123         case RTE_ETH_FILTER_SET:
7124                 ret = i40e_dev_global_config_set(hw,
7125                         (struct rte_eth_global_cfg *)arg);
7126                 break;
7127         default:
7128                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7129                 break;
7130         }
7131
7132         return ret;
7133 }
7134
7135 static int
7136 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7137                           enum rte_filter_op filter_op,
7138                           void *arg)
7139 {
7140         struct rte_eth_tunnel_filter_conf *filter;
7141         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7142         int ret = I40E_SUCCESS;
7143
7144         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7145
7146         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7147                 return I40E_ERR_PARAM;
7148
7149         switch (filter_op) {
7150         case RTE_ETH_FILTER_NOP:
7151                 if (!(pf->flags & I40E_FLAG_VXLAN))
7152                         ret = I40E_NOT_SUPPORTED;
7153                 break;
7154         case RTE_ETH_FILTER_ADD:
7155                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7156                 break;
7157         case RTE_ETH_FILTER_DELETE:
7158                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7159                 break;
7160         default:
7161                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7162                 ret = I40E_ERR_PARAM;
7163                 break;
7164         }
7165
7166         return ret;
7167 }
7168
7169 static int
7170 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7171 {
7172         int ret = 0;
7173         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7174
7175         /* RSS setup */
7176         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7177                 ret = i40e_pf_config_rss(pf);
7178         else
7179                 i40e_pf_disable_rss(pf);
7180
7181         return ret;
7182 }
7183
7184 /* Get the symmetric hash enable configurations per port */
7185 static void
7186 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7187 {
7188         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7189
7190         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7191 }
7192
7193 /* Set the symmetric hash enable configurations per port */
7194 static void
7195 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7196 {
7197         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7198
7199         if (enable > 0) {
7200                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7201                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7202                                                         "been enabled");
7203                         return;
7204                 }
7205                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7206         } else {
7207                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7208                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7209                                                         "been disabled");
7210                         return;
7211                 }
7212                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7213         }
7214         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7215         I40E_WRITE_FLUSH(hw);
7216 }
7217
7218 /*
7219  * Get global configurations of hash function type and symmetric hash enable
7220  * per flow type (pctype). Note that global configuration means it affects all
7221  * the ports on the same NIC.
7222  */
7223 static int
7224 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7225                                    struct rte_eth_hash_global_conf *g_cfg)
7226 {
7227         uint32_t reg, mask = I40E_FLOW_TYPES;
7228         uint16_t i;
7229         enum i40e_filter_pctype pctype;
7230
7231         memset(g_cfg, 0, sizeof(*g_cfg));
7232         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7233         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7234                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7235         else
7236                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7237         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7238                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7239
7240         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7241                 if (!(mask & (1UL << i)))
7242                         continue;
7243                 mask &= ~(1UL << i);
7244                 /* Bit set indicats the coresponding flow type is supported */
7245                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7246                 /* if flowtype is invalid, continue */
7247                 if (!I40E_VALID_FLOW(i))
7248                         continue;
7249                 pctype = i40e_flowtype_to_pctype(i);
7250                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7251                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7252                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7253         }
7254
7255         return 0;
7256 }
7257
7258 static int
7259 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7260 {
7261         uint32_t i;
7262         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7263
7264         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7265                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7266                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7267                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7268                                                 g_cfg->hash_func);
7269                 return -EINVAL;
7270         }
7271
7272         /*
7273          * As i40e supports less than 32 flow types, only first 32 bits need to
7274          * be checked.
7275          */
7276         mask0 = g_cfg->valid_bit_mask[0];
7277         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7278                 if (i == 0) {
7279                         /* Check if any unsupported flow type configured */
7280                         if ((mask0 | i40e_mask) ^ i40e_mask)
7281                                 goto mask_err;
7282                 } else {
7283                         if (g_cfg->valid_bit_mask[i])
7284                                 goto mask_err;
7285                 }
7286         }
7287
7288         return 0;
7289
7290 mask_err:
7291         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7292
7293         return -EINVAL;
7294 }
7295
7296 /*
7297  * Set global configurations of hash function type and symmetric hash enable
7298  * per flow type (pctype). Note any modifying global configuration will affect
7299  * all the ports on the same NIC.
7300  */
7301 static int
7302 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7303                                    struct rte_eth_hash_global_conf *g_cfg)
7304 {
7305         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7306         int ret;
7307         uint16_t i;
7308         uint32_t reg;
7309         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7310         enum i40e_filter_pctype pctype;
7311
7312         if (pf->support_multi_driver) {
7313                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
7314                 return -ENOTSUP;
7315         }
7316
7317         /* Check the input parameters */
7318         ret = i40e_hash_global_config_check(g_cfg);
7319         if (ret < 0)
7320                 return ret;
7321
7322         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7323                 if (!(mask0 & (1UL << i)))
7324                         continue;
7325                 mask0 &= ~(1UL << i);
7326                 /* if flowtype is invalid, continue */
7327                 if (!I40E_VALID_FLOW(i))
7328                         continue;
7329                 pctype = i40e_flowtype_to_pctype(i);
7330                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7331                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7332                 if (hw->mac.type == I40E_MAC_X722) {
7333                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7334                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7335                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7336                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7337                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7338                                   reg);
7339                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7340                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7341                                   reg);
7342                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7343                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7344                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7345                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7346                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7347                                   reg);
7348                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7349                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7350                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7351                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7352                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7353                                   reg);
7354                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7355                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7356                                   reg);
7357                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7358                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7359                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7360                                 i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(
7361                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7362                                   reg);
7363                         } else {
7364                                 i40e_write_global_rx_ctl(hw,
7365                                                          I40E_GLQF_HSYM(pctype),
7366                                                          reg);
7367                         }
7368                 } else {
7369                         i40e_write_global_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7370                                                  reg);
7371                 }
7372                 i40e_global_cfg_warning(I40E_WARNING_HSYM);
7373         }
7374
7375         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7376         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7377                 /* Toeplitz */
7378                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7379                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7380                                                                 "Toeplitz");
7381                         goto out;
7382                 }
7383                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7384         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7385                 /* Simple XOR */
7386                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7387                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7388                                                         "Simple XOR");
7389                         goto out;
7390                 }
7391                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7392         } else
7393                 /* Use the default, and keep it as it is */
7394                 goto out;
7395
7396         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
7397         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
7398
7399 out:
7400         I40E_WRITE_FLUSH(hw);
7401
7402         return 0;
7403 }
7404
7405 /**
7406  * Valid input sets for hash and flow director filters per PCTYPE
7407  */
7408 static uint64_t
7409 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7410                 enum rte_filter_type filter)
7411 {
7412         uint64_t valid;
7413
7414         static const uint64_t valid_hash_inset_table[] = {
7415                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7416                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7417                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7418                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7419                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7420                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7421                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7422                         I40E_INSET_FLEX_PAYLOAD,
7423                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7424                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7425                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7426                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7427                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7428                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7429                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7430                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7431                         I40E_INSET_FLEX_PAYLOAD,
7432 #ifdef X722_SUPPORT
7433                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7434                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7435                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7436                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7437                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7438                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7439                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7440                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7441                         I40E_INSET_FLEX_PAYLOAD,
7442                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7443                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7444                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7445                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7446                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7447                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7448                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7449                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7450                         I40E_INSET_FLEX_PAYLOAD,
7451 #endif
7452                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7453                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7454                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7455                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7456                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7457                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7458                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7459                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7460                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7461 #ifdef X722_SUPPORT
7462                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7463                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7464                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7465                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7466                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7467                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7468                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7469                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7470                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7471 #endif
7472                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7473                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7474                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7475                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7476                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7477                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7478                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7479                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7480                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7481                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7482                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7483                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7484                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7485                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7486                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7487                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7488                         I40E_INSET_FLEX_PAYLOAD,
7489                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7490                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7491                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7492                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7493                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7494                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7495                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7496                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7497                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7498                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7499                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7500                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7501                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7502                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7503                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7504                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7505 #ifdef X722_SUPPORT
7506                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7507                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7508                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7509                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7510                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7511                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7512                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7513                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7514                         I40E_INSET_FLEX_PAYLOAD,
7515                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7516                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7517                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7518                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7519                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7520                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7521                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7522                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7523                         I40E_INSET_FLEX_PAYLOAD,
7524 #endif
7525                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7526                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7527                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7528                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7529                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7530                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7531                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7532                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7533                         I40E_INSET_FLEX_PAYLOAD,
7534 #ifdef X722_SUPPORT
7535                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7536                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7537                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7538                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7539                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7540                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7541                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7542                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7543                         I40E_INSET_FLEX_PAYLOAD,
7544 #endif
7545                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7546                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7547                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7548                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7549                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7550                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7551                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7552                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7553                         I40E_INSET_FLEX_PAYLOAD,
7554                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7555                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7556                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7557                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7558                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7559                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7560                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7561                         I40E_INSET_FLEX_PAYLOAD,
7562                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7563                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7564                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7565                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7566                         I40E_INSET_FLEX_PAYLOAD,
7567         };
7568
7569         /**
7570          * Flow director supports only fields defined in
7571          * union rte_eth_fdir_flow.
7572          */
7573         static const uint64_t valid_fdir_inset_table[] = {
7574                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7575                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7576                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7577                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7578                 I40E_INSET_IPV4_TTL,
7579                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7580                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7581                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7582                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7583                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7584 #ifdef X722_SUPPORT
7585                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7586                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7587                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7588                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7589                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7590                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7591                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7592                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7593                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7594                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7595 #endif
7596                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7597                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7598                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7599                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7600                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7601 #ifdef X722_SUPPORT
7602                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7603                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7604                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7605                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7606                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7607 #endif
7608                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7609                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7610                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7611                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7612                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7613                 I40E_INSET_SCTP_VT,
7614                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7615                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7616                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7617                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7618                 I40E_INSET_IPV4_TTL,
7619                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7620                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7621                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7622                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7623                 I40E_INSET_IPV6_HOP_LIMIT,
7624                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7625                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7626                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7627                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7628                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7629 #ifdef X722_SUPPORT
7630                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7631                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7632                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7633                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7634                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7635                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7636                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7637                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7638                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7639                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7640 #endif
7641                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7642                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7643                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7644                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7645                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7646 #ifdef X722_SUPPORT
7647                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7648                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7649                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7650                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7651                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7652 #endif
7653                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7654                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7655                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7656                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7657                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7658                 I40E_INSET_SCTP_VT,
7659                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7660                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7661                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7662                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7663                 I40E_INSET_IPV6_HOP_LIMIT,
7664                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7665                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7666                 I40E_INSET_LAST_ETHER_TYPE,
7667         };
7668
7669         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7670                 return 0;
7671         if (filter == RTE_ETH_FILTER_HASH)
7672                 valid = valid_hash_inset_table[pctype];
7673         else
7674                 valid = valid_fdir_inset_table[pctype];
7675
7676         return valid;
7677 }
7678
7679 /**
7680  * Validate if the input set is allowed for a specific PCTYPE
7681  */
7682 static int
7683 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7684                 enum rte_filter_type filter, uint64_t inset)
7685 {
7686         uint64_t valid;
7687
7688         valid = i40e_get_valid_input_set(pctype, filter);
7689         if (inset & (~valid))
7690                 return -EINVAL;
7691
7692         return 0;
7693 }
7694
7695 /* default input set fields combination per pctype */
7696 static uint64_t
7697 i40e_get_default_input_set(uint16_t pctype)
7698 {
7699         static const uint64_t default_inset_table[] = {
7700                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7701                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7702                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7703                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7704                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7705 #ifdef X722_SUPPORT
7706                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7707                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7708                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7709                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7710                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7711                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7712 #endif
7713                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7714                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7715                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7716 #ifdef X722_SUPPORT
7717                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7718                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7719                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7720 #endif
7721                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7722                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7723                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7724                         I40E_INSET_SCTP_VT,
7725                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7726                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7727                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7728                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7729                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7730                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7731                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7732 #ifdef X722_SUPPORT
7733                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7734                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7735                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7736                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7737                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7738                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7739 #endif
7740                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7741                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7742                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7743 #ifdef X722_SUPPORT
7744                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7745                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7746                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7747 #endif
7748                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7749                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7750                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7751                         I40E_INSET_SCTP_VT,
7752                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7753                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7754                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7755                         I40E_INSET_LAST_ETHER_TYPE,
7756         };
7757
7758         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7759                 return 0;
7760
7761         return default_inset_table[pctype];
7762 }
7763
7764 /**
7765  * Parse the input set from index to logical bit masks
7766  */
7767 static int
7768 i40e_parse_input_set(uint64_t *inset,
7769                      enum i40e_filter_pctype pctype,
7770                      enum rte_eth_input_set_field *field,
7771                      uint16_t size)
7772 {
7773         uint16_t i, j;
7774         int ret = -EINVAL;
7775
7776         static const struct {
7777                 enum rte_eth_input_set_field field;
7778                 uint64_t inset;
7779         } inset_convert_table[] = {
7780                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7781                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7782                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7783                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7784                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7785                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7786                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7787                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7788                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7789                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7790                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7791                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7792                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7793                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7794                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7795                         I40E_INSET_IPV6_NEXT_HDR},
7796                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7797                         I40E_INSET_IPV6_HOP_LIMIT},
7798                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7799                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7800                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7801                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7802                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7803                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7804                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7805                         I40E_INSET_SCTP_VT},
7806                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7807                         I40E_INSET_TUNNEL_DMAC},
7808                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7809                         I40E_INSET_VLAN_TUNNEL},
7810                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7811                         I40E_INSET_TUNNEL_ID},
7812                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7813                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7814                         I40E_INSET_FLEX_PAYLOAD_W1},
7815                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7816                         I40E_INSET_FLEX_PAYLOAD_W2},
7817                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7818                         I40E_INSET_FLEX_PAYLOAD_W3},
7819                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7820                         I40E_INSET_FLEX_PAYLOAD_W4},
7821                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7822                         I40E_INSET_FLEX_PAYLOAD_W5},
7823                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7824                         I40E_INSET_FLEX_PAYLOAD_W6},
7825                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7826                         I40E_INSET_FLEX_PAYLOAD_W7},
7827                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7828                         I40E_INSET_FLEX_PAYLOAD_W8},
7829         };
7830
7831         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7832                 return ret;
7833
7834         /* Only one item allowed for default or all */
7835         if (size == 1) {
7836                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7837                         *inset = i40e_get_default_input_set(pctype);
7838                         return 0;
7839                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7840                         *inset = I40E_INSET_NONE;
7841                         return 0;
7842                 }
7843         }
7844
7845         for (i = 0, *inset = 0; i < size; i++) {
7846                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7847                         if (field[i] == inset_convert_table[j].field) {
7848                                 *inset |= inset_convert_table[j].inset;
7849                                 break;
7850                         }
7851                 }
7852
7853                 /* It contains unsupported input set, return immediately */
7854                 if (j == RTE_DIM(inset_convert_table))
7855                         return ret;
7856         }
7857
7858         return 0;
7859 }
7860
7861 /**
7862  * Translate the input set from bit masks to register aware bit masks
7863  * and vice versa
7864  */
7865 static uint64_t
7866 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7867 {
7868         uint64_t val = 0;
7869         uint16_t i;
7870
7871         struct inset_map {
7872                 uint64_t inset;
7873                 uint64_t inset_reg;
7874         };
7875
7876         static const struct inset_map inset_map_common[] = {
7877                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7878                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7879                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7880                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7881                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7882                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7883                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7884                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7885                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7886                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7887                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7888                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7889                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7890                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7891                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7892                 {I40E_INSET_TUNNEL_DMAC,
7893                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7894                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7895                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7896                 {I40E_INSET_TUNNEL_SRC_PORT,
7897                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7898                 {I40E_INSET_TUNNEL_DST_PORT,
7899                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7900                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7901                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7902                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7903                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7904                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7905                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7906                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7907                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7908                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7909         };
7910
7911     /* some different registers map in x722*/
7912         static const struct inset_map inset_map_diff_x722[] = {
7913                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7914                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7915                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7916                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7917         };
7918
7919         static const struct inset_map inset_map_diff_not_x722[] = {
7920                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7921                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7922                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7923                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7924         };
7925
7926         if (input == 0)
7927                 return val;
7928
7929         /* Translate input set to register aware inset */
7930         if (type == I40E_MAC_X722) {
7931                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7932                         if (input & inset_map_diff_x722[i].inset)
7933                                 val |= inset_map_diff_x722[i].inset_reg;
7934                 }
7935         } else {
7936                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7937                         if (input & inset_map_diff_not_x722[i].inset)
7938                                 val |= inset_map_diff_not_x722[i].inset_reg;
7939                 }
7940         }
7941
7942         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7943                 if (input & inset_map_common[i].inset)
7944                         val |= inset_map_common[i].inset_reg;
7945         }
7946
7947         return val;
7948 }
7949
7950 static int
7951 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7952 {
7953         uint8_t i, idx = 0;
7954         uint64_t inset_need_mask = inset;
7955
7956         static const struct {
7957                 uint64_t inset;
7958                 uint32_t mask;
7959         } inset_mask_map[] = {
7960                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7961                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7962                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7963                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7964                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7965                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7966                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7967                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7968         };
7969
7970         if (!inset || !mask || !nb_elem)
7971                 return 0;
7972
7973         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7974                 /* Clear the inset bit, if no MASK is required,
7975                  * for example proto + ttl
7976                  */
7977                 if ((inset & inset_mask_map[i].inset) ==
7978                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7979                         inset_need_mask &= ~inset_mask_map[i].inset;
7980                 if (!inset_need_mask)
7981                         return 0;
7982         }
7983         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7984                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7985                     inset_mask_map[i].inset) {
7986                         if (idx >= nb_elem) {
7987                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7988                                 return -EINVAL;
7989                         }
7990                         mask[idx] = inset_mask_map[i].mask;
7991                         idx++;
7992                 }
7993         }
7994
7995         return idx;
7996 }
7997
7998 static void
7999 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8000 {
8001         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8002
8003         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
8004         if (reg != val)
8005                 i40e_write_rx_ctl(hw, addr, val);
8006         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
8007                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8008 }
8009
8010 static void
8011 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8012 {
8013         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8014
8015         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8016         if (reg != val)
8017                 i40e_write_global_rx_ctl(hw, addr, val);
8018         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8019                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8020 }
8021
8022 static void
8023 i40e_filter_input_set_init(struct i40e_pf *pf)
8024 {
8025         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8026         enum i40e_filter_pctype pctype;
8027         uint64_t input_set, inset_reg;
8028         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8029         int num, i;
8030
8031         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8032              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8033                 if (hw->mac.type == I40E_MAC_X722) {
8034                         if (!I40E_VALID_PCTYPE_X722(pctype))
8035                                 continue;
8036                 } else {
8037                         if (!I40E_VALID_PCTYPE(pctype))
8038                                 continue;
8039                 }
8040
8041                 input_set = i40e_get_default_input_set(pctype);
8042
8043                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8044                                                    I40E_INSET_MASK_NUM_REG);
8045                 if (num < 0)
8046                         return;
8047
8048                 if (pf->support_multi_driver && num > 0) {
8049                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
8050                         return;
8051                 }
8052
8053                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8054                                         input_set);
8055
8056                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8057                                       (uint32_t)(inset_reg & UINT32_MAX));
8058                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8059                                      (uint32_t)((inset_reg >>
8060                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8061                 if (!pf->support_multi_driver) {
8062                         i40e_check_write_global_reg(hw,
8063                                             I40E_GLQF_HASH_INSET(0, pctype),
8064                                             (uint32_t)(inset_reg & UINT32_MAX));
8065                         i40e_check_write_global_reg(hw,
8066                                             I40E_GLQF_HASH_INSET(1, pctype),
8067                                             (uint32_t)((inset_reg >>
8068                                             I40E_32_BIT_WIDTH) & UINT32_MAX));
8069
8070                         for (i = 0; i < num; i++) {
8071                                 i40e_check_write_global_reg(hw,
8072                                                     I40E_GLQF_FD_MSK(i, pctype),
8073                                                     mask_reg[i]);
8074                                 i40e_check_write_global_reg(hw,
8075                                                   I40E_GLQF_HASH_MSK(i, pctype),
8076                                                   mask_reg[i]);
8077                         }
8078                         /*clear unused mask registers of the pctype */
8079                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8080                                 i40e_check_write_global_reg(hw,
8081                                                     I40E_GLQF_FD_MSK(i, pctype),
8082                                                     0);
8083                                 i40e_check_write_global_reg(hw,
8084                                                   I40E_GLQF_HASH_MSK(i, pctype),
8085                                                     0);
8086                         }
8087                 } else {
8088                         PMD_DRV_LOG(ERR,
8089                                     "Input set setting is not supported.");
8090                 }
8091                 I40E_WRITE_FLUSH(hw);
8092
8093                 /* store the default input set */
8094                 if (!pf->support_multi_driver)
8095                         pf->hash_input_set[pctype] = input_set;
8096                 pf->fdir.input_set[pctype] = input_set;
8097         }
8098
8099         if (!pf->support_multi_driver) {
8100                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
8101                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
8102                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
8103         }
8104 }
8105
8106 int
8107 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8108                          struct rte_eth_input_set_conf *conf)
8109 {
8110         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8111         enum i40e_filter_pctype pctype;
8112         uint64_t input_set, inset_reg = 0;
8113         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8114         int ret, i, num;
8115
8116         if (pf->support_multi_driver) {
8117                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
8118                 return -ENOTSUP;
8119         }
8120
8121         if (!conf) {
8122                 PMD_DRV_LOG(ERR, "Invalid pointer");
8123                 return -EFAULT;
8124         }
8125         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8126             conf->op != RTE_ETH_INPUT_SET_ADD) {
8127                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8128                 return -EINVAL;
8129         }
8130
8131         if (!I40E_VALID_FLOW(conf->flow_type)) {
8132                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8133                 return -EINVAL;
8134         }
8135
8136         if (hw->mac.type == I40E_MAC_X722) {
8137                 /* get translated pctype value in fd pctype register */
8138                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8139                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8140                         conf->flow_type)));
8141         } else
8142                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8143
8144         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8145                                    conf->inset_size);
8146         if (ret) {
8147                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8148                 return -EINVAL;
8149         }
8150         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8151                                     input_set) != 0) {
8152                 PMD_DRV_LOG(ERR, "Invalid input set");
8153                 return -EINVAL;
8154         }
8155         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8156                 /* get inset value in register */
8157                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8158                 inset_reg <<= I40E_32_BIT_WIDTH;
8159                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8160                 input_set |= pf->hash_input_set[pctype];
8161         }
8162         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8163                                            I40E_INSET_MASK_NUM_REG);
8164         if (num < 0)
8165                 return -EINVAL;
8166
8167         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8168
8169         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8170                                     (uint32_t)(inset_reg & UINT32_MAX));
8171         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8172                                     (uint32_t)((inset_reg >>
8173                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
8174         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
8175
8176         for (i = 0; i < num; i++)
8177                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8178                                             mask_reg[i]);
8179         /*clear unused mask registers of the pctype */
8180         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8181                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8182                                             0);
8183         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
8184         I40E_WRITE_FLUSH(hw);
8185
8186         pf->hash_input_set[pctype] = input_set;
8187         return 0;
8188 }
8189
8190 int
8191 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8192                          struct rte_eth_input_set_conf *conf)
8193 {
8194         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8195         enum i40e_filter_pctype pctype;
8196         uint64_t input_set, inset_reg = 0;
8197         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8198         int ret, i, num;
8199
8200         if (!hw || !conf) {
8201                 PMD_DRV_LOG(ERR, "Invalid pointer");
8202                 return -EFAULT;
8203         }
8204         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8205             conf->op != RTE_ETH_INPUT_SET_ADD) {
8206                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8207                 return -EINVAL;
8208         }
8209
8210         if (!I40E_VALID_FLOW(conf->flow_type)) {
8211                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8212                 return -EINVAL;
8213         }
8214
8215         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8216
8217         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8218                                    conf->inset_size);
8219         if (ret) {
8220                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8221                 return -EINVAL;
8222         }
8223         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8224                                     input_set) != 0) {
8225                 PMD_DRV_LOG(ERR, "Invalid input set");
8226                 return -EINVAL;
8227         }
8228
8229         /* get inset value in register */
8230         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8231         inset_reg <<= I40E_32_BIT_WIDTH;
8232         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8233
8234         /* Can not change the inset reg for flex payload for fdir,
8235          * it is done by writing I40E_PRTQF_FD_FLXINSET
8236          * in i40e_set_flex_mask_on_pctype.
8237          */
8238         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8239                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8240         else
8241                 input_set |= pf->fdir.input_set[pctype];
8242         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8243                                            I40E_INSET_MASK_NUM_REG);
8244         if (num < 0)
8245                 return -EINVAL;
8246
8247         if (pf->support_multi_driver && num > 0) {
8248                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
8249                 return -ENOTSUP;
8250         }
8251
8252         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8253
8254         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8255                               (uint32_t)(inset_reg & UINT32_MAX));
8256         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8257                              (uint32_t)((inset_reg >>
8258                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8259
8260         if (!pf->support_multi_driver) {
8261                 for (i = 0; i < num; i++)
8262                         i40e_check_write_global_reg(hw,
8263                                                     I40E_GLQF_FD_MSK(i, pctype),
8264                                                     mask_reg[i]);
8265                 /*clear unused mask registers of the pctype */
8266                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8267                         i40e_check_write_global_reg(hw,
8268                                                     I40E_GLQF_FD_MSK(i, pctype),
8269                                                     0);
8270                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
8271         } else {
8272                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
8273         }
8274         I40E_WRITE_FLUSH(hw);
8275
8276         pf->fdir.input_set[pctype] = input_set;
8277         return 0;
8278 }
8279
8280 static int
8281 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8282 {
8283         int ret = 0;
8284
8285         if (!hw || !info) {
8286                 PMD_DRV_LOG(ERR, "Invalid pointer");
8287                 return -EFAULT;
8288         }
8289
8290         switch (info->info_type) {
8291         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8292                 i40e_get_symmetric_hash_enable_per_port(hw,
8293                                         &(info->info.enable));
8294                 break;
8295         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8296                 ret = i40e_get_hash_filter_global_config(hw,
8297                                 &(info->info.global_conf));
8298                 break;
8299         default:
8300                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8301                                                         info->info_type);
8302                 ret = -EINVAL;
8303                 break;
8304         }
8305
8306         return ret;
8307 }
8308
8309 static int
8310 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8311 {
8312         int ret = 0;
8313
8314         if (!hw || !info) {
8315                 PMD_DRV_LOG(ERR, "Invalid pointer");
8316                 return -EFAULT;
8317         }
8318
8319         switch (info->info_type) {
8320         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8321                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8322                 break;
8323         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8324                 ret = i40e_set_hash_filter_global_config(hw,
8325                                 &(info->info.global_conf));
8326                 break;
8327         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8328                 ret = i40e_hash_filter_inset_select(hw,
8329                                                &(info->info.input_set_conf));
8330                 break;
8331
8332         default:
8333                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8334                                                         info->info_type);
8335                 ret = -EINVAL;
8336                 break;
8337         }
8338
8339         return ret;
8340 }
8341
8342 /* Operations for hash function */
8343 static int
8344 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8345                       enum rte_filter_op filter_op,
8346                       void *arg)
8347 {
8348         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8349         int ret = 0;
8350
8351         switch (filter_op) {
8352         case RTE_ETH_FILTER_NOP:
8353                 break;
8354         case RTE_ETH_FILTER_GET:
8355                 ret = i40e_hash_filter_get(hw,
8356                         (struct rte_eth_hash_filter_info *)arg);
8357                 break;
8358         case RTE_ETH_FILTER_SET:
8359                 ret = i40e_hash_filter_set(hw,
8360                         (struct rte_eth_hash_filter_info *)arg);
8361                 break;
8362         default:
8363                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8364                                                                 filter_op);
8365                 ret = -ENOTSUP;
8366                 break;
8367         }
8368
8369         return ret;
8370 }
8371
8372 /*
8373  * Configure ethertype filter, which can director packet by filtering
8374  * with mac address and ether_type or only ether_type
8375  */
8376 static int
8377 i40e_ethertype_filter_set(struct i40e_pf *pf,
8378                         struct rte_eth_ethertype_filter *filter,
8379                         bool add)
8380 {
8381         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8382         struct i40e_control_filter_stats stats;
8383         uint16_t flags = 0;
8384         int ret;
8385
8386         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8387                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8388                 return -EINVAL;
8389         }
8390         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8391                 filter->ether_type == ETHER_TYPE_IPv6) {
8392                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8393                         " control packet filter.", filter->ether_type);
8394                 return -EINVAL;
8395         }
8396         if (filter->ether_type == ETHER_TYPE_VLAN)
8397                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8398                         " not supported.");
8399
8400         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8401                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8402         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8403                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8404         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8405
8406         memset(&stats, 0, sizeof(stats));
8407         ret = i40e_aq_add_rem_control_packet_filter(hw,
8408                         filter->mac_addr.addr_bytes,
8409                         filter->ether_type, flags,
8410                         pf->main_vsi->seid,
8411                         filter->queue, add, &stats, NULL);
8412
8413         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8414                          " mac_etype_used = %u, etype_used = %u,"
8415                          " mac_etype_free = %u, etype_free = %u\n",
8416                          ret, stats.mac_etype_used, stats.etype_used,
8417                          stats.mac_etype_free, stats.etype_free);
8418         if (ret < 0)
8419                 return -ENOSYS;
8420         return 0;
8421 }
8422
8423 /*
8424  * Handle operations for ethertype filter.
8425  */
8426 static int
8427 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8428                                 enum rte_filter_op filter_op,
8429                                 void *arg)
8430 {
8431         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8432         int ret = 0;
8433
8434         if (filter_op == RTE_ETH_FILTER_NOP)
8435                 return ret;
8436
8437         if (arg == NULL) {
8438                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8439                             filter_op);
8440                 return -EINVAL;
8441         }
8442
8443         switch (filter_op) {
8444         case RTE_ETH_FILTER_ADD:
8445                 ret = i40e_ethertype_filter_set(pf,
8446                         (struct rte_eth_ethertype_filter *)arg,
8447                         TRUE);
8448                 break;
8449         case RTE_ETH_FILTER_DELETE:
8450                 ret = i40e_ethertype_filter_set(pf,
8451                         (struct rte_eth_ethertype_filter *)arg,
8452                         FALSE);
8453                 break;
8454         default:
8455                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8456                 ret = -ENOSYS;
8457                 break;
8458         }
8459         return ret;
8460 }
8461
8462 static int
8463 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8464                      enum rte_filter_type filter_type,
8465                      enum rte_filter_op filter_op,
8466                      void *arg)
8467 {
8468         int ret = 0;
8469
8470         if (dev == NULL)
8471                 return -EINVAL;
8472
8473         switch (filter_type) {
8474         case RTE_ETH_FILTER_NONE:
8475                 /* For global configuration */
8476                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8477                 break;
8478         case RTE_ETH_FILTER_HASH:
8479                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8480                 break;
8481         case RTE_ETH_FILTER_MACVLAN:
8482                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8483                 break;
8484         case RTE_ETH_FILTER_ETHERTYPE:
8485                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8486                 break;
8487         case RTE_ETH_FILTER_TUNNEL:
8488                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8489                 break;
8490         case RTE_ETH_FILTER_FDIR:
8491                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8492                 break;
8493         default:
8494                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8495                                                         filter_type);
8496                 ret = -EINVAL;
8497                 break;
8498         }
8499
8500         return ret;
8501 }
8502
8503 /*
8504  * Check and enable Extended Tag.
8505  * Enabling Extended Tag is important for 40G performance.
8506  */
8507 static void
8508 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8509 {
8510         uint32_t buf = 0;
8511         int ret;
8512
8513         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8514                                       PCI_DEV_CAP_REG);
8515         if (ret < 0) {
8516                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8517                             PCI_DEV_CAP_REG);
8518                 return;
8519         }
8520         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8521                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8522                 return;
8523         }
8524
8525         buf = 0;
8526         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8527                                       PCI_DEV_CTRL_REG);
8528         if (ret < 0) {
8529                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8530                             PCI_DEV_CTRL_REG);
8531                 return;
8532         }
8533         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8534                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8535                 return;
8536         }
8537         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8538         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8539                                        PCI_DEV_CTRL_REG);
8540         if (ret < 0) {
8541                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8542                             PCI_DEV_CTRL_REG);
8543                 return;
8544         }
8545 }
8546
8547 /*
8548  * As some registers wouldn't be reset unless a global hardware reset,
8549  * hardware initialization is needed to put those registers into an
8550  * expected initial state.
8551  */
8552 static void
8553 i40e_hw_init(struct rte_eth_dev *dev)
8554 {
8555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8556
8557         i40e_enable_extended_tag(dev);
8558
8559         /* clear the PF Queue Filter control register */
8560         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8561
8562         /* Disable symmetric hash per port */
8563         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8564 }
8565
8566 enum i40e_filter_pctype
8567 i40e_flowtype_to_pctype(uint16_t flow_type)
8568 {
8569         static const enum i40e_filter_pctype pctype_table[] = {
8570                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8571                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8572                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8573                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8574                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8575                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8576                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8577                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8578                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8579                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8580                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8581                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8582                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8583                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8584                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8585                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8586                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8587                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8588                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8589         };
8590
8591         return pctype_table[flow_type];
8592 }
8593
8594 uint16_t
8595 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8596 {
8597         static const uint16_t flowtype_table[] = {
8598                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8599                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8600                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8601 #ifdef X722_SUPPORT
8602                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8603                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8604                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8605                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8606 #endif
8607                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8608                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8609 #ifdef X722_SUPPORT
8610                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8611                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8612 #endif
8613                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8614                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8615                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8616                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8617                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8618                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8619                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8620 #ifdef X722_SUPPORT
8621                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8622                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8623                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8624                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8625 #endif
8626                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8627                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8628 #ifdef X722_SUPPORT
8629                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8630                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8631 #endif
8632                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8633                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8634                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8635                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8636                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8637         };
8638
8639         return flowtype_table[pctype];
8640 }
8641
8642 /*
8643  * On X710, performance number is far from the expectation on recent firmware
8644  * versions; on XL710, performance number is also far from the expectation on
8645  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8646  * mode is enabled and port MAC address is equal to the packet destination MAC
8647  * address. The fix for this issue may not be integrated in the following
8648  * firmware version. So the workaround in software driver is needed. It needs
8649  * to modify the initial values of 3 internal only registers for both X710 and
8650  * XL710. Note that the values for X710 or XL710 could be different, and the
8651  * workaround can be removed when it is fixed in firmware in the future.
8652  */
8653
8654 /* For both X710 and XL710 */
8655 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
8656 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
8657 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
8658
8659 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8660 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8661
8662 /* For X722 */
8663 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8664 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8665
8666 /* For X710 */
8667 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8668 /* For XL710 */
8669 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8670 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8671
8672 static int
8673 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8674 {
8675         enum i40e_status_code status;
8676         struct i40e_aq_get_phy_abilities_resp phy_ab;
8677         int ret = -ENOTSUP;
8678
8679         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8680                                               NULL);
8681
8682         if (status)
8683                 return ret;
8684
8685         return 0;
8686 }
8687
8688 static void
8689 i40e_configure_registers(struct i40e_hw *hw)
8690 {
8691         static struct {
8692                 uint32_t addr;
8693                 uint64_t val;
8694         } reg_table[] = {
8695                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8696                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8697                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8698         };
8699         uint64_t reg;
8700         uint32_t i;
8701         int ret;
8702
8703         for (i = 0; i < RTE_DIM(reg_table); i++) {
8704                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8705                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8706                                 reg_table[i].val =
8707                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8708                         else /* For X710/XL710/XXV710 */
8709                                 if (hw->aq.fw_maj_ver < 6)
8710                                         reg_table[i].val =
8711                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
8712                                 else
8713                                         reg_table[i].val =
8714                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
8715                 }
8716
8717                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8718                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8719                                 reg_table[i].val =
8720                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8721                         else /* For X710/XL710/XXV710 */
8722                                 reg_table[i].val =
8723                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8724                 }
8725
8726                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8727                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8728                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8729                                 reg_table[i].val =
8730                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8731                         else /* For X710 */
8732                                 reg_table[i].val =
8733                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8734                 }
8735
8736                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8737                                                         &reg, NULL);
8738                 if (ret < 0) {
8739                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8740                                                         reg_table[i].addr);
8741                         break;
8742                 }
8743                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8744                                                 reg_table[i].addr, reg);
8745                 if (reg == reg_table[i].val)
8746                         continue;
8747
8748                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8749                                                 reg_table[i].val, NULL);
8750                 if (ret < 0) {
8751                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8752                                 "address of 0x%"PRIx32, reg_table[i].val,
8753                                                         reg_table[i].addr);
8754                         break;
8755                 }
8756                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8757                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8758         }
8759 }
8760
8761 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8762 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8763 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8764 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8765 static int
8766 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8767 {
8768         uint32_t reg;
8769         int ret;
8770
8771         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8772                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8773                 return -EINVAL;
8774         }
8775
8776         /* Configure for double VLAN RX stripping */
8777         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8778         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8779                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8780                 ret = i40e_aq_debug_write_register(hw,
8781                                                    I40E_VSI_TSR(vsi->vsi_id),
8782                                                    reg, NULL);
8783                 if (ret < 0) {
8784                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8785                                     vsi->vsi_id);
8786                         return I40E_ERR_CONFIG;
8787                 }
8788         }
8789
8790         /* Configure for double VLAN TX insertion */
8791         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8792         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8793                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8794                 ret = i40e_aq_debug_write_register(hw,
8795                                                    I40E_VSI_L2TAGSTXVALID(
8796                                                    vsi->vsi_id), reg, NULL);
8797                 if (ret < 0) {
8798                         PMD_DRV_LOG(ERR, "Failed to update "
8799                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8800                         return I40E_ERR_CONFIG;
8801                 }
8802         }
8803
8804         return 0;
8805 }
8806
8807 /**
8808  * i40e_aq_add_mirror_rule
8809  * @hw: pointer to the hardware structure
8810  * @seid: VEB seid to add mirror rule to
8811  * @dst_id: destination vsi seid
8812  * @entries: Buffer which contains the entities to be mirrored
8813  * @count: number of entities contained in the buffer
8814  * @rule_id:the rule_id of the rule to be added
8815  *
8816  * Add a mirror rule for a given veb.
8817  *
8818  **/
8819 static enum i40e_status_code
8820 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8821                         uint16_t seid, uint16_t dst_id,
8822                         uint16_t rule_type, uint16_t *entries,
8823                         uint16_t count, uint16_t *rule_id)
8824 {
8825         struct i40e_aq_desc desc;
8826         struct i40e_aqc_add_delete_mirror_rule cmd;
8827         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8828                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8829                 &desc.params.raw;
8830         uint16_t buff_len;
8831         enum i40e_status_code status;
8832
8833         i40e_fill_default_direct_cmd_desc(&desc,
8834                                           i40e_aqc_opc_add_mirror_rule);
8835         memset(&cmd, 0, sizeof(cmd));
8836
8837         buff_len = sizeof(uint16_t) * count;
8838         desc.datalen = rte_cpu_to_le_16(buff_len);
8839         if (buff_len > 0)
8840                 desc.flags |= rte_cpu_to_le_16(
8841                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8842         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8843                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8844         cmd.num_entries = rte_cpu_to_le_16(count);
8845         cmd.seid = rte_cpu_to_le_16(seid);
8846         cmd.destination = rte_cpu_to_le_16(dst_id);
8847
8848         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8849         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8850         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8851                          "rule_id = %u"
8852                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8853                          hw->aq.asq_last_status, resp->rule_id,
8854                          resp->mirror_rules_used, resp->mirror_rules_free);
8855         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8856
8857         return status;
8858 }
8859
8860 /**
8861  * i40e_aq_del_mirror_rule
8862  * @hw: pointer to the hardware structure
8863  * @seid: VEB seid to add mirror rule to
8864  * @entries: Buffer which contains the entities to be mirrored
8865  * @count: number of entities contained in the buffer
8866  * @rule_id:the rule_id of the rule to be delete
8867  *
8868  * Delete a mirror rule for a given veb.
8869  *
8870  **/
8871 static enum i40e_status_code
8872 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8873                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8874                 uint16_t count, uint16_t rule_id)
8875 {
8876         struct i40e_aq_desc desc;
8877         struct i40e_aqc_add_delete_mirror_rule cmd;
8878         uint16_t buff_len = 0;
8879         enum i40e_status_code status;
8880         void *buff = NULL;
8881
8882         i40e_fill_default_direct_cmd_desc(&desc,
8883                                           i40e_aqc_opc_delete_mirror_rule);
8884         memset(&cmd, 0, sizeof(cmd));
8885         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8886                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8887                                                           I40E_AQ_FLAG_RD));
8888                 cmd.num_entries = count;
8889                 buff_len = sizeof(uint16_t) * count;
8890                 desc.datalen = rte_cpu_to_le_16(buff_len);
8891                 buff = (void *)entries;
8892         } else
8893                 /* rule id is filled in destination field for deleting mirror rule */
8894                 cmd.destination = rte_cpu_to_le_16(rule_id);
8895
8896         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8897                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8898         cmd.seid = rte_cpu_to_le_16(seid);
8899
8900         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8901         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8902
8903         return status;
8904 }
8905
8906 /**
8907  * i40e_mirror_rule_set
8908  * @dev: pointer to the hardware structure
8909  * @mirror_conf: mirror rule info
8910  * @sw_id: mirror rule's sw_id
8911  * @on: enable/disable
8912  *
8913  * set a mirror rule.
8914  *
8915  **/
8916 static int
8917 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8918                         struct rte_eth_mirror_conf *mirror_conf,
8919                         uint8_t sw_id, uint8_t on)
8920 {
8921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8923         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8924         struct i40e_mirror_rule *parent = NULL;
8925         uint16_t seid, dst_seid, rule_id;
8926         uint16_t i, j = 0;
8927         int ret;
8928
8929         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8930
8931         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8932                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8933                         " without veb or vfs.");
8934                 return -ENOSYS;
8935         }
8936         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8937                 PMD_DRV_LOG(ERR, "mirror table is full.");
8938                 return -ENOSPC;
8939         }
8940         if (mirror_conf->dst_pool > pf->vf_num) {
8941                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8942                                  mirror_conf->dst_pool);
8943                 return -EINVAL;
8944         }
8945
8946         seid = pf->main_vsi->veb->seid;
8947
8948         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8949                 if (sw_id <= it->index) {
8950                         mirr_rule = it;
8951                         break;
8952                 }
8953                 parent = it;
8954         }
8955         if (mirr_rule && sw_id == mirr_rule->index) {
8956                 if (on) {
8957                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8958                         return -EEXIST;
8959                 } else {
8960                         ret = i40e_aq_del_mirror_rule(hw, seid,
8961                                         mirr_rule->rule_type,
8962                                         mirr_rule->entries,
8963                                         mirr_rule->num_entries, mirr_rule->id);
8964                         if (ret < 0) {
8965                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8966                                                    " ret = %d, aq_err = %d.",
8967                                                    ret, hw->aq.asq_last_status);
8968                                 return -ENOSYS;
8969                         }
8970                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8971                         rte_free(mirr_rule);
8972                         pf->nb_mirror_rule--;
8973                         return 0;
8974                 }
8975         } else if (!on) {
8976                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8977                 return -ENOENT;
8978         }
8979
8980         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8981                                 sizeof(struct i40e_mirror_rule) , 0);
8982         if (!mirr_rule) {
8983                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8984                 return I40E_ERR_NO_MEMORY;
8985         }
8986         switch (mirror_conf->rule_type) {
8987         case ETH_MIRROR_VLAN:
8988                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8989                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8990                                 mirr_rule->entries[j] =
8991                                         mirror_conf->vlan.vlan_id[i];
8992                                 j++;
8993                         }
8994                 }
8995                 if (j == 0) {
8996                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8997                         rte_free(mirr_rule);
8998                         return -EINVAL;
8999                 }
9000                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9001                 break;
9002         case ETH_MIRROR_VIRTUAL_POOL_UP:
9003         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9004                 /* check if the specified pool bit is out of range */
9005                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9006                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9007                         rte_free(mirr_rule);
9008                         return -EINVAL;
9009                 }
9010                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9011                         if (mirror_conf->pool_mask & (1ULL << i)) {
9012                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9013                                 j++;
9014                         }
9015                 }
9016                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9017                         /* add pf vsi to entries */
9018                         mirr_rule->entries[j] = pf->main_vsi_seid;
9019                         j++;
9020                 }
9021                 if (j == 0) {
9022                         PMD_DRV_LOG(ERR, "pool is not specified.");
9023                         rte_free(mirr_rule);
9024                         return -EINVAL;
9025                 }
9026                 /* egress and ingress in aq commands means from switch but not port */
9027                 mirr_rule->rule_type =
9028                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9029                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9030                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9031                 break;
9032         case ETH_MIRROR_UPLINK_PORT:
9033                 /* egress and ingress in aq commands means from switch but not port*/
9034                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9035                 break;
9036         case ETH_MIRROR_DOWNLINK_PORT:
9037                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9038                 break;
9039         default:
9040                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9041                         mirror_conf->rule_type);
9042                 rte_free(mirr_rule);
9043                 return -EINVAL;
9044         }
9045
9046         /* If the dst_pool is equal to vf_num, consider it as PF */
9047         if (mirror_conf->dst_pool == pf->vf_num)
9048                 dst_seid = pf->main_vsi_seid;
9049         else
9050                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9051
9052         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9053                                       mirr_rule->rule_type, mirr_rule->entries,
9054                                       j, &rule_id);
9055         if (ret < 0) {
9056                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9057                                    " ret = %d, aq_err = %d.",
9058                                    ret, hw->aq.asq_last_status);
9059                 rte_free(mirr_rule);
9060                 return -ENOSYS;
9061         }
9062
9063         mirr_rule->index = sw_id;
9064         mirr_rule->num_entries = j;
9065         mirr_rule->id = rule_id;
9066         mirr_rule->dst_vsi_seid = dst_seid;
9067
9068         if (parent)
9069                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9070         else
9071                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9072
9073         pf->nb_mirror_rule++;
9074         return 0;
9075 }
9076
9077 /**
9078  * i40e_mirror_rule_reset
9079  * @dev: pointer to the device
9080  * @sw_id: mirror rule's sw_id
9081  *
9082  * reset a mirror rule.
9083  *
9084  **/
9085 static int
9086 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9087 {
9088         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9090         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9091         uint16_t seid;
9092         int ret;
9093
9094         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9095
9096         seid = pf->main_vsi->veb->seid;
9097
9098         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9099                 if (sw_id == it->index) {
9100                         mirr_rule = it;
9101                         break;
9102                 }
9103         }
9104         if (mirr_rule) {
9105                 ret = i40e_aq_del_mirror_rule(hw, seid,
9106                                 mirr_rule->rule_type,
9107                                 mirr_rule->entries,
9108                                 mirr_rule->num_entries, mirr_rule->id);
9109                 if (ret < 0) {
9110                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9111                                            " status = %d, aq_err = %d.",
9112                                            ret, hw->aq.asq_last_status);
9113                         return -ENOSYS;
9114                 }
9115                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9116                 rte_free(mirr_rule);
9117                 pf->nb_mirror_rule--;
9118         } else {
9119                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9120                 return -ENOENT;
9121         }
9122         return 0;
9123 }
9124
9125 static uint64_t
9126 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9127 {
9128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9129         uint64_t systim_cycles;
9130
9131         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9132         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9133                         << 32;
9134
9135         return systim_cycles;
9136 }
9137
9138 static uint64_t
9139 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9140 {
9141         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9142         uint64_t rx_tstamp;
9143
9144         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9145         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9146                         << 32;
9147
9148         return rx_tstamp;
9149 }
9150
9151 static uint64_t
9152 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9153 {
9154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9155         uint64_t tx_tstamp;
9156
9157         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9158         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9159                         << 32;
9160
9161         return tx_tstamp;
9162 }
9163
9164 static void
9165 i40e_start_timecounters(struct rte_eth_dev *dev)
9166 {
9167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9168         struct i40e_adapter *adapter =
9169                         (struct i40e_adapter *)dev->data->dev_private;
9170         struct rte_eth_link link;
9171         uint32_t tsync_inc_l;
9172         uint32_t tsync_inc_h;
9173
9174         /* Get current link speed. */
9175         memset(&link, 0, sizeof(link));
9176         i40e_dev_link_update(dev, 1);
9177         rte_i40e_dev_atomic_read_link_status(dev, &link);
9178
9179         switch (link.link_speed) {
9180         case ETH_SPEED_NUM_40G:
9181                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9182                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9183                 break;
9184         case ETH_SPEED_NUM_10G:
9185                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9186                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9187                 break;
9188         case ETH_SPEED_NUM_1G:
9189                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9190                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9191                 break;
9192         default:
9193                 tsync_inc_l = 0x0;
9194                 tsync_inc_h = 0x0;
9195         }
9196
9197         /* Set the timesync increment value. */
9198         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9199         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9200
9201         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9202         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9203         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9204
9205         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9206         adapter->systime_tc.cc_shift = 0;
9207         adapter->systime_tc.nsec_mask = 0;
9208
9209         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9210         adapter->rx_tstamp_tc.cc_shift = 0;
9211         adapter->rx_tstamp_tc.nsec_mask = 0;
9212
9213         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9214         adapter->tx_tstamp_tc.cc_shift = 0;
9215         adapter->tx_tstamp_tc.nsec_mask = 0;
9216 }
9217
9218 static int
9219 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9220 {
9221         struct i40e_adapter *adapter =
9222                         (struct i40e_adapter *)dev->data->dev_private;
9223
9224         adapter->systime_tc.nsec += delta;
9225         adapter->rx_tstamp_tc.nsec += delta;
9226         adapter->tx_tstamp_tc.nsec += delta;
9227
9228         return 0;
9229 }
9230
9231 static int
9232 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9233 {
9234         uint64_t ns;
9235         struct i40e_adapter *adapter =
9236                         (struct i40e_adapter *)dev->data->dev_private;
9237
9238         ns = rte_timespec_to_ns(ts);
9239
9240         /* Set the timecounters to a new value. */
9241         adapter->systime_tc.nsec = ns;
9242         adapter->rx_tstamp_tc.nsec = ns;
9243         adapter->tx_tstamp_tc.nsec = ns;
9244
9245         return 0;
9246 }
9247
9248 static int
9249 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9250 {
9251         uint64_t ns, systime_cycles;
9252         struct i40e_adapter *adapter =
9253                         (struct i40e_adapter *)dev->data->dev_private;
9254
9255         systime_cycles = i40e_read_systime_cyclecounter(dev);
9256         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9257         *ts = rte_ns_to_timespec(ns);
9258
9259         return 0;
9260 }
9261
9262 static int
9263 i40e_timesync_enable(struct rte_eth_dev *dev)
9264 {
9265         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9266         uint32_t tsync_ctl_l;
9267         uint32_t tsync_ctl_h;
9268
9269         /* Stop the timesync system time. */
9270         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9271         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9272         /* Reset the timesync system time value. */
9273         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9274         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9275
9276         i40e_start_timecounters(dev);
9277
9278         /* Clear timesync registers. */
9279         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9280         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9281         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9282         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9283         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9284         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9285
9286         /* Enable timestamping of PTP packets. */
9287         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9288         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9289
9290         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9291         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9292         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9293
9294         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9295         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9296
9297         return 0;
9298 }
9299
9300 static int
9301 i40e_timesync_disable(struct rte_eth_dev *dev)
9302 {
9303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9304         uint32_t tsync_ctl_l;
9305         uint32_t tsync_ctl_h;
9306
9307         /* Disable timestamping of transmitted PTP packets. */
9308         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9309         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9310
9311         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9312         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9313
9314         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9315         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9316
9317         /* Reset the timesync increment value. */
9318         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9319         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9320
9321         return 0;
9322 }
9323
9324 static int
9325 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9326                                 struct timespec *timestamp, uint32_t flags)
9327 {
9328         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9329         struct i40e_adapter *adapter =
9330                 (struct i40e_adapter *)dev->data->dev_private;
9331
9332         uint32_t sync_status;
9333         uint32_t index = flags & 0x03;
9334         uint64_t rx_tstamp_cycles;
9335         uint64_t ns;
9336
9337         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9338         if ((sync_status & (1 << index)) == 0)
9339                 return -EINVAL;
9340
9341         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9342         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9343         *timestamp = rte_ns_to_timespec(ns);
9344
9345         return 0;
9346 }
9347
9348 static int
9349 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9350                                 struct timespec *timestamp)
9351 {
9352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9353         struct i40e_adapter *adapter =
9354                 (struct i40e_adapter *)dev->data->dev_private;
9355
9356         uint32_t sync_status;
9357         uint64_t tx_tstamp_cycles;
9358         uint64_t ns;
9359
9360         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9361         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9362                 return -EINVAL;
9363
9364         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9365         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9366         *timestamp = rte_ns_to_timespec(ns);
9367
9368         return 0;
9369 }
9370
9371 /*
9372  * i40e_parse_dcb_configure - parse dcb configure from user
9373  * @dev: the device being configured
9374  * @dcb_cfg: pointer of the result of parse
9375  * @*tc_map: bit map of enabled traffic classes
9376  *
9377  * Returns 0 on success, negative value on failure
9378  */
9379 static int
9380 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9381                          struct i40e_dcbx_config *dcb_cfg,
9382                          uint8_t *tc_map)
9383 {
9384         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9385         uint8_t i, tc_bw, bw_lf;
9386
9387         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9388
9389         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9390         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9391                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9392                 return -EINVAL;
9393         }
9394
9395         /* assume each tc has the same bw */
9396         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9397         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9398                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9399         /* to ensure the sum of tcbw is equal to 100 */
9400         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9401         for (i = 0; i < bw_lf; i++)
9402                 dcb_cfg->etscfg.tcbwtable[i]++;
9403
9404         /* assume each tc has the same Transmission Selection Algorithm */
9405         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9406                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9407
9408         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9409                 dcb_cfg->etscfg.prioritytable[i] =
9410                                 dcb_rx_conf->dcb_tc[i];
9411
9412         /* FW needs one App to configure HW */
9413         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9414         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9415         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9416         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9417
9418         if (dcb_rx_conf->nb_tcs == 0)
9419                 *tc_map = 1; /* tc0 only */
9420         else
9421                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9422
9423         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9424                 dcb_cfg->pfc.willing = 0;
9425                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9426                 dcb_cfg->pfc.pfcenable = *tc_map;
9427         }
9428         return 0;
9429 }
9430
9431
9432 static enum i40e_status_code
9433 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9434                               struct i40e_aqc_vsi_properties_data *info,
9435                               uint8_t enabled_tcmap)
9436 {
9437         enum i40e_status_code ret;
9438         int i, total_tc = 0;
9439         uint16_t qpnum_per_tc, bsf, qp_idx;
9440         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9441         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9442         uint16_t used_queues;
9443
9444         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9445         if (ret != I40E_SUCCESS)
9446                 return ret;
9447
9448         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9449                 if (enabled_tcmap & (1 << i))
9450                         total_tc++;
9451         }
9452         if (total_tc == 0)
9453                 total_tc = 1;
9454         vsi->enabled_tc = enabled_tcmap;
9455
9456         /* different VSI has different queues assigned */
9457         if (vsi->type == I40E_VSI_MAIN)
9458                 used_queues = dev_data->nb_rx_queues -
9459                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9460         else if (vsi->type == I40E_VSI_VMDQ2)
9461                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9462         else {
9463                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9464                 return I40E_ERR_NO_AVAILABLE_VSI;
9465         }
9466
9467         qpnum_per_tc = used_queues / total_tc;
9468         /* Number of queues per enabled TC */
9469         if (qpnum_per_tc == 0) {
9470                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9471                 return I40E_ERR_INVALID_QP_ID;
9472         }
9473         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9474                                 I40E_MAX_Q_PER_TC);
9475         bsf = rte_bsf32(qpnum_per_tc);
9476
9477         /**
9478          * Configure TC and queue mapping parameters, for enabled TC,
9479          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9480          * default queue will serve it.
9481          */
9482         qp_idx = 0;
9483         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9484                 if (vsi->enabled_tc & (1 << i)) {
9485                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9486                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9487                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9488                         qp_idx += qpnum_per_tc;
9489                 } else
9490                         info->tc_mapping[i] = 0;
9491         }
9492
9493         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9494         if (vsi->type == I40E_VSI_SRIOV) {
9495                 info->mapping_flags |=
9496                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9497                 for (i = 0; i < vsi->nb_qps; i++)
9498                         info->queue_mapping[i] =
9499                                 rte_cpu_to_le_16(vsi->base_queue + i);
9500         } else {
9501                 info->mapping_flags |=
9502                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9503                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9504         }
9505         info->valid_sections |=
9506                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9507
9508         return I40E_SUCCESS;
9509 }
9510
9511 /*
9512  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9513  * @veb: VEB to be configured
9514  * @tc_map: enabled TC bitmap
9515  *
9516  * Returns 0 on success, negative value on failure
9517  */
9518 static enum i40e_status_code
9519 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9520 {
9521         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9522         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9523         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9524         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9525         enum i40e_status_code ret = I40E_SUCCESS;
9526         int i;
9527         uint32_t bw_max;
9528
9529         /* Check if enabled_tc is same as existing or new TCs */
9530         if (veb->enabled_tc == tc_map)
9531                 return ret;
9532
9533         /* configure tc bandwidth */
9534         memset(&veb_bw, 0, sizeof(veb_bw));
9535         veb_bw.tc_valid_bits = tc_map;
9536         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9537         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9538                 if (tc_map & BIT_ULL(i))
9539                         veb_bw.tc_bw_share_credits[i] = 1;
9540         }
9541         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9542                                                    &veb_bw, NULL);
9543         if (ret) {
9544                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9545                                   " per TC failed = %d",
9546                                   hw->aq.asq_last_status);
9547                 return ret;
9548         }
9549
9550         memset(&ets_query, 0, sizeof(ets_query));
9551         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9552                                                    &ets_query, NULL);
9553         if (ret != I40E_SUCCESS) {
9554                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9555                                  " configuration %u", hw->aq.asq_last_status);
9556                 return ret;
9557         }
9558         memset(&bw_query, 0, sizeof(bw_query));
9559         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9560                                                   &bw_query, NULL);
9561         if (ret != I40E_SUCCESS) {
9562                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9563                                  " configuration %u", hw->aq.asq_last_status);
9564                 return ret;
9565         }
9566
9567         /* store and print out BW info */
9568         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9569         veb->bw_info.bw_max = ets_query.tc_bw_max;
9570         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9571         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9572         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9573                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9574                      I40E_16_BIT_WIDTH);
9575         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9576                 veb->bw_info.bw_ets_share_credits[i] =
9577                                 bw_query.tc_bw_share_credits[i];
9578                 veb->bw_info.bw_ets_credits[i] =
9579                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9580                 /* 4 bits per TC, 4th bit is reserved */
9581                 veb->bw_info.bw_ets_max[i] =
9582                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9583                                   RTE_LEN2MASK(3, uint8_t));
9584                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9585                             veb->bw_info.bw_ets_share_credits[i]);
9586                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9587                             veb->bw_info.bw_ets_credits[i]);
9588                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9589                             veb->bw_info.bw_ets_max[i]);
9590         }
9591
9592         veb->enabled_tc = tc_map;
9593
9594         return ret;
9595 }
9596
9597
9598 /*
9599  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9600  * @vsi: VSI to be configured
9601  * @tc_map: enabled TC bitmap
9602  *
9603  * Returns 0 on success, negative value on failure
9604  */
9605 static enum i40e_status_code
9606 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9607 {
9608         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9609         struct i40e_vsi_context ctxt;
9610         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9611         enum i40e_status_code ret = I40E_SUCCESS;
9612         int i;
9613
9614         /* Check if enabled_tc is same as existing or new TCs */
9615         if (vsi->enabled_tc == tc_map)
9616                 return ret;
9617
9618         /* configure tc bandwidth */
9619         memset(&bw_data, 0, sizeof(bw_data));
9620         bw_data.tc_valid_bits = tc_map;
9621         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9622         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9623                 if (tc_map & BIT_ULL(i))
9624                         bw_data.tc_bw_credits[i] = 1;
9625         }
9626         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9627         if (ret) {
9628                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9629                         " per TC failed = %d",
9630                         hw->aq.asq_last_status);
9631                 goto out;
9632         }
9633         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9634                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9635
9636         /* Update Queue Pairs Mapping for currently enabled UPs */
9637         ctxt.seid = vsi->seid;
9638         ctxt.pf_num = hw->pf_id;
9639         ctxt.vf_num = 0;
9640         ctxt.uplink_seid = vsi->uplink_seid;
9641         ctxt.info = vsi->info;
9642         i40e_get_cap(hw);
9643         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9644         if (ret)
9645                 goto out;
9646
9647         /* Update the VSI after updating the VSI queue-mapping information */
9648         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9649         if (ret) {
9650                 PMD_INIT_LOG(ERR, "Failed to configure "
9651                             "TC queue mapping = %d",
9652                             hw->aq.asq_last_status);
9653                 goto out;
9654         }
9655         /* update the local VSI info with updated queue map */
9656         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9657                                         sizeof(vsi->info.tc_mapping));
9658         (void)rte_memcpy(&vsi->info.queue_mapping,
9659                         &ctxt.info.queue_mapping,
9660                 sizeof(vsi->info.queue_mapping));
9661         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9662         vsi->info.valid_sections = 0;
9663
9664         /* query and update current VSI BW information */
9665         ret = i40e_vsi_get_bw_config(vsi);
9666         if (ret) {
9667                 PMD_INIT_LOG(ERR,
9668                          "Failed updating vsi bw info, err %s aq_err %s",
9669                          i40e_stat_str(hw, ret),
9670                          i40e_aq_str(hw, hw->aq.asq_last_status));
9671                 goto out;
9672         }
9673
9674         vsi->enabled_tc = tc_map;
9675
9676 out:
9677         return ret;
9678 }
9679
9680 /*
9681  * i40e_dcb_hw_configure - program the dcb setting to hw
9682  * @pf: pf the configuration is taken on
9683  * @new_cfg: new configuration
9684  * @tc_map: enabled TC bitmap
9685  *
9686  * Returns 0 on success, negative value on failure
9687  */
9688 static enum i40e_status_code
9689 i40e_dcb_hw_configure(struct i40e_pf *pf,
9690                       struct i40e_dcbx_config *new_cfg,
9691                       uint8_t tc_map)
9692 {
9693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9694         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9695         struct i40e_vsi *main_vsi = pf->main_vsi;
9696         struct i40e_vsi_list *vsi_list;
9697         enum i40e_status_code ret;
9698         int i;
9699         uint32_t val;
9700
9701         /* Use the FW API if FW > v4.4*/
9702         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9703               (hw->aq.fw_maj_ver >= 5))) {
9704                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9705                                   " to configure DCB");
9706                 return I40E_ERR_FIRMWARE_API_VERSION;
9707         }
9708
9709         /* Check if need reconfiguration */
9710         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9711                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9712                 return I40E_SUCCESS;
9713         }
9714
9715         /* Copy the new config to the current config */
9716         *old_cfg = *new_cfg;
9717         old_cfg->etsrec = old_cfg->etscfg;
9718         ret = i40e_set_dcb_config(hw);
9719         if (ret) {
9720                 PMD_INIT_LOG(ERR,
9721                          "Set DCB Config failed, err %s aq_err %s\n",
9722                          i40e_stat_str(hw, ret),
9723                          i40e_aq_str(hw, hw->aq.asq_last_status));
9724                 return ret;
9725         }
9726         /* set receive Arbiter to RR mode and ETS scheme by default */
9727         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9728                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9729                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9730                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9731                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9732                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9733                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9734                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9735                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9736                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9737                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9738                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9739                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9740         }
9741         /* get local mib to check whether it is configured correctly */
9742         /* IEEE mode */
9743         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9744         /* Get Local DCB Config */
9745         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9746                                      &hw->local_dcbx_config);
9747
9748         /* if Veb is created, need to update TC of it at first */
9749         if (main_vsi->veb) {
9750                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9751                 if (ret)
9752                         PMD_INIT_LOG(WARNING,
9753                                  "Failed configuring TC for VEB seid=%d\n",
9754                                  main_vsi->veb->seid);
9755         }
9756         /* Update each VSI */
9757         i40e_vsi_config_tc(main_vsi, tc_map);
9758         if (main_vsi->veb) {
9759                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9760                         /* Beside main VSI and VMDQ VSIs, only enable default
9761                          * TC for other VSIs
9762                          */
9763                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9764                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9765                                                          tc_map);
9766                         else
9767                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9768                                                          I40E_DEFAULT_TCMAP);
9769                         if (ret)
9770                                 PMD_INIT_LOG(WARNING,
9771                                          "Failed configuring TC for VSI seid=%d\n",
9772                                          vsi_list->vsi->seid);
9773                         /* continue */
9774                 }
9775         }
9776         return I40E_SUCCESS;
9777 }
9778
9779 /*
9780  * i40e_dcb_init_configure - initial dcb config
9781  * @dev: device being configured
9782  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9783  *
9784  * Returns 0 on success, negative value on failure
9785  */
9786 static int
9787 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9788 {
9789         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9791         int ret = 0;
9792
9793         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9794                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9795                 return -ENOTSUP;
9796         }
9797
9798         /* DCB initialization:
9799          * Update DCB configuration from the Firmware and configure
9800          * LLDP MIB change event.
9801          */
9802         if (sw_dcb == TRUE) {
9803                 ret = i40e_init_dcb(hw);
9804                 /* If lldp agent is stopped, the return value from
9805                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9806                  * adminq status. Otherwise, it should return success.
9807                  */
9808                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9809                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9810                         memset(&hw->local_dcbx_config, 0,
9811                                 sizeof(struct i40e_dcbx_config));
9812                         /* set dcb default configuration */
9813                         hw->local_dcbx_config.etscfg.willing = 0;
9814                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9815                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9816                         hw->local_dcbx_config.etscfg.tsatable[0] =
9817                                                 I40E_IEEE_TSA_ETS;
9818                         hw->local_dcbx_config.etsrec =
9819                                 hw->local_dcbx_config.etscfg;
9820                         hw->local_dcbx_config.pfc.willing = 0;
9821                         hw->local_dcbx_config.pfc.pfccap =
9822                                                 I40E_MAX_TRAFFIC_CLASS;
9823                         /* FW needs one App to configure HW */
9824                         hw->local_dcbx_config.numapps = 1;
9825                         hw->local_dcbx_config.app[0].selector =
9826                                                 I40E_APP_SEL_ETHTYPE;
9827                         hw->local_dcbx_config.app[0].priority = 3;
9828                         hw->local_dcbx_config.app[0].protocolid =
9829                                                 I40E_APP_PROTOID_FCOE;
9830                         ret = i40e_set_dcb_config(hw);
9831                         if (ret) {
9832                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9833                                         " err = %d, aq_err = %d.", ret,
9834                                           hw->aq.asq_last_status);
9835                                 return -ENOSYS;
9836                         }
9837                 } else {
9838                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9839                                           " err = %d, aq_err = %d.", ret,
9840                                           hw->aq.asq_last_status);
9841                         return -ENOTSUP;
9842                 }
9843         } else {
9844                 ret = i40e_aq_start_lldp(hw, NULL);
9845                 if (ret != I40E_SUCCESS)
9846                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9847
9848                 ret = i40e_init_dcb(hw);
9849                 if (!ret) {
9850                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9851                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9852                                                   " DCBX offload.");
9853                                 return -ENOTSUP;
9854                         }
9855                 } else {
9856                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9857                                           " aq_err = %d.", ret,
9858                                           hw->aq.asq_last_status);
9859                         return -ENOTSUP;
9860                 }
9861         }
9862         return 0;
9863 }
9864
9865 /*
9866  * i40e_dcb_setup - setup dcb related config
9867  * @dev: device being configured
9868  *
9869  * Returns 0 on success, negative value on failure
9870  */
9871 static int
9872 i40e_dcb_setup(struct rte_eth_dev *dev)
9873 {
9874         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9875         struct i40e_dcbx_config dcb_cfg;
9876         uint8_t tc_map = 0;
9877         int ret = 0;
9878
9879         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9880                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9881                 return -ENOTSUP;
9882         }
9883
9884         if (pf->vf_num != 0)
9885                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9886
9887         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9888         if (ret) {
9889                 PMD_INIT_LOG(ERR, "invalid dcb config");
9890                 return -EINVAL;
9891         }
9892         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9893         if (ret) {
9894                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9895                 return -ENOSYS;
9896         }
9897
9898         return 0;
9899 }
9900
9901 static int
9902 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9903                       struct rte_eth_dcb_info *dcb_info)
9904 {
9905         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9906         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9907         struct i40e_vsi *vsi = pf->main_vsi;
9908         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9909         uint16_t bsf, tc_mapping;
9910         int i, j = 0;
9911
9912         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9913                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9914         else
9915                 dcb_info->nb_tcs = 1;
9916         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9917                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9918         for (i = 0; i < dcb_info->nb_tcs; i++)
9919                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9920
9921         /* get queue mapping if vmdq is disabled */
9922         if (!pf->nb_cfg_vmdq_vsi) {
9923                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9924                         if (!(vsi->enabled_tc & (1 << i)))
9925                                 continue;
9926                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9927                         dcb_info->tc_queue.tc_rxq[j][i].base =
9928                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9929                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9930                         dcb_info->tc_queue.tc_txq[j][i].base =
9931                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9932                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9933                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9934                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9935                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9936                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9937                 }
9938                 return 0;
9939         }
9940
9941         /* get queue mapping if vmdq is enabled */
9942         do {
9943                 vsi = pf->vmdq[j].vsi;
9944                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9945                         if (!(vsi->enabled_tc & (1 << i)))
9946                                 continue;
9947                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9948                         dcb_info->tc_queue.tc_rxq[j][i].base =
9949                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9950                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9951                         dcb_info->tc_queue.tc_txq[j][i].base =
9952                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9953                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9954                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9955                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9956                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9957                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9958                 }
9959                 j++;
9960         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9961         return 0;
9962 }
9963
9964 static int
9965 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9966 {
9967         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9968         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9969         uint16_t msix_intr;
9970
9971         msix_intr = intr_handle->intr_vec[queue_id];
9972         if (msix_intr == I40E_MISC_VEC_ID)
9973                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9974                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
9975                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
9976                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
9977         else
9978                 I40E_WRITE_REG(hw,
9979                                I40E_PFINT_DYN_CTLN(msix_intr -
9980                                                    I40E_RX_VEC_START),
9981                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9982                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9983                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
9984
9985         I40E_WRITE_FLUSH(hw);
9986         rte_intr_enable(&dev->pci_dev->intr_handle);
9987
9988         return 0;
9989 }
9990
9991 static int
9992 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9993 {
9994         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9995         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9996         uint16_t msix_intr;
9997
9998         msix_intr = intr_handle->intr_vec[queue_id];
9999         if (msix_intr == I40E_MISC_VEC_ID)
10000                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10001                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
10002         else
10003                 I40E_WRITE_REG(hw,
10004                                I40E_PFINT_DYN_CTLN(msix_intr -
10005                                                    I40E_RX_VEC_START),
10006                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
10007         I40E_WRITE_FLUSH(hw);
10008
10009         return 0;
10010 }
10011
10012 static int i40e_get_regs(struct rte_eth_dev *dev,
10013                          struct rte_dev_reg_info *regs)
10014 {
10015         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10016         uint32_t *ptr_data = regs->data;
10017         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10018         const struct i40e_reg_info *reg_info;
10019
10020         if (ptr_data == NULL) {
10021                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10022                 regs->width = sizeof(uint32_t);
10023                 return 0;
10024         }
10025
10026         /* The first few registers have to be read using AQ operations */
10027         reg_idx = 0;
10028         while (i40e_regs_adminq[reg_idx].name) {
10029                 reg_info = &i40e_regs_adminq[reg_idx++];
10030                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10031                         for (arr_idx2 = 0;
10032                                         arr_idx2 <= reg_info->count2;
10033                                         arr_idx2++) {
10034                                 reg_offset = arr_idx * reg_info->stride1 +
10035                                         arr_idx2 * reg_info->stride2;
10036                                 reg_offset += reg_info->base_addr;
10037                                 ptr_data[reg_offset >> 2] =
10038                                         i40e_read_rx_ctl(hw, reg_offset);
10039                         }
10040         }
10041
10042         /* The remaining registers can be read using primitives */
10043         reg_idx = 0;
10044         while (i40e_regs_others[reg_idx].name) {
10045                 reg_info = &i40e_regs_others[reg_idx++];
10046                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10047                         for (arr_idx2 = 0;
10048                                         arr_idx2 <= reg_info->count2;
10049                                         arr_idx2++) {
10050                                 reg_offset = arr_idx * reg_info->stride1 +
10051                                         arr_idx2 * reg_info->stride2;
10052                                 reg_offset += reg_info->base_addr;
10053                                 ptr_data[reg_offset >> 2] =
10054                                         I40E_READ_REG(hw, reg_offset);
10055                         }
10056         }
10057
10058         return 0;
10059 }
10060
10061 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10062 {
10063         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10064
10065         /* Convert word count to byte count */
10066         return hw->nvm.sr_size << 1;
10067 }
10068
10069 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10070                            struct rte_dev_eeprom_info *eeprom)
10071 {
10072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10073         uint16_t *data = eeprom->data;
10074         uint16_t offset, length, cnt_words;
10075         int ret_code;
10076
10077         offset = eeprom->offset >> 1;
10078         length = eeprom->length >> 1;
10079         cnt_words = length;
10080
10081         if (offset > hw->nvm.sr_size ||
10082                 offset + length > hw->nvm.sr_size) {
10083                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10084                 return -EINVAL;
10085         }
10086
10087         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10088
10089         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10090         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10091                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10092                 return -EIO;
10093         }
10094
10095         return 0;
10096 }
10097
10098 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10099                                       struct ether_addr *mac_addr)
10100 {
10101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10102         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10103         struct i40e_vsi *vsi = pf->main_vsi;
10104         struct i40e_mac_filter_info mac_filter;
10105         struct i40e_mac_filter *f;
10106         int ret;
10107
10108         if (!is_valid_assigned_ether_addr(mac_addr)) {
10109                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10110                 return;
10111         }
10112
10113         TAILQ_FOREACH(f, &vsi->mac_list, next) {
10114                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
10115                         break;
10116         }
10117
10118         if (f == NULL) {
10119                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
10120                 return;
10121         }
10122
10123         mac_filter = f->mac_info;
10124         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
10125         if (ret != I40E_SUCCESS) {
10126                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
10127                 return;
10128         }
10129         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
10130         ret = i40e_vsi_add_mac(vsi, &mac_filter);
10131         if (ret != I40E_SUCCESS) {
10132                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
10133                 return;
10134         }
10135         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
10136
10137         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
10138                                   mac_addr->addr_bytes, NULL);
10139 }
10140
10141 static int
10142 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10143 {
10144         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10145         struct rte_eth_dev_data *dev_data = pf->dev_data;
10146         uint32_t frame_size = mtu + ETHER_HDR_LEN
10147                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10148         int ret = 0;
10149
10150         /* check if mtu is within the allowed range */
10151         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10152                 return -EINVAL;
10153
10154         /* mtu setting is forbidden if port is start */
10155         if (dev_data->dev_started) {
10156                 PMD_DRV_LOG(ERR,
10157                             "port %d must be stopped before configuration\n",
10158                             dev_data->port_id);
10159                 return -EBUSY;
10160         }
10161
10162         if (frame_size > ETHER_MAX_LEN)
10163                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10164         else
10165                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10166
10167         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10168
10169         return ret;
10170 }