drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_bus_pci.h>
  47 #include <rte_ether.h>
  48 #include <rte_ethdev.h>
  49 #include <rte_ethdev_pci.h>
  50 #include <rte_memzone.h>
  51 #include <rte_malloc.h>
  52 #include <rte_memcpy.h>
  53 #include <rte_alarm.h>
  54 #include <rte_dev.h>
  55 #include <rte_eth_ctrl.h>
  56 #include <rte_tailq.h>
  57 #include <rte_hash_crc.h>
  58
  59 #include "i40e_logs.h"
  60 #include "base/i40e_prototype.h"
  61 #include "base/i40e_adminq_cmd.h"
  62 #include "base/i40e_type.h"
  63 #include "base/i40e_register.h"
  64 #include "base/i40e_dcb.h"
  65 #include "i40e_ethdev.h"
  66 #include "i40e_rxtx.h"
  67 #include "i40e_pf.h"
  68 #include "i40e_regs.h"
  69 #include "rte_pmd_i40e.h"
  70
  71 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  72 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  73
  74 #define I40E_CLEAR_PXE_WAIT_MS     200
  75
  76 /* Maximun number of capability elements */
  77 #define I40E_MAX_CAP_ELE_NUM       128
  78
  79 /* Wait count and interval */
  80 #define I40E_CHK_Q_ENA_COUNT       1000
  81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  82
  83 /* Maximun number of VSI */
  84 #define I40E_MAX_NUM_VSIS          (384UL)
  85
  86 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  87
  88 /* Flow control default timer */
  89 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  90
  91 /* Flow control enable fwd bit */
  92 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  93
  94 /* Receive Packet Buffer size */
  95 #define I40E_RXPBSIZE (968 * 1024)
  96
  97 /* Kilobytes shift */
  98 #define I40E_KILOSHIFT 10
  99
 100 /* Flow control default high water */
 101 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 102
 103 /* Flow control default low water */
 104 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 105
 106 /* Receive Average Packet Size in Byte*/
 107 #define I40E_PACKET_AVERAGE_SIZE 128
 108
 109 /* Mask of PF interrupt causes */
 110 #define I40E_PFINT_ICR0_ENA_MASK ( \
 111                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 115                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 116                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 118                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 119                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 120
 121 #define I40E_FLOW_TYPES ( \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 130         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 131         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 132         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 133
 134 /* Additional timesync values. */
 135 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 136 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 137 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 138 #define I40E_PRTTSYN_TSYNENA     0x80000000
 139 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 140 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 141
 142 /**
 143  * Below are values for writing un-exposed registers suggested
 144  * by silicon experts
 145  */
 146 /* Destination MAC address */
 147 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 148 /* Source MAC address */
 149 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 150 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 151 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 152 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 154 /* Single VLAN tag in the inner L2 header */
 155 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 156 /* Source IPv4 address */
 157 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 158 /* Destination IPv4 address */
 159 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 160 /* Source IPv4 address for X722 */
 161 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 162 /* Destination IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 164 /* IPv4 Protocol for X722 */
 165 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 166 /* IPv4 Time to Live for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 168 /* IPv4 Type of Service (TOS) */
 169 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 170 /* IPv4 Protocol */
 171 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 172 /* IPv4 Time to Live */
 173 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 174 /* Source IPv6 address */
 175 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 176 /* Destination IPv6 address */
 177 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 178 /* IPv6 Traffic Class (TC) */
 179 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 180 /* IPv6 Next Header */
 181 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 182 /* IPv6 Hop Limit */
 183 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 184 /* Source L4 port */
 185 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 186 /* Destination L4 port */
 187 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 188 /* SCTP verification tag */
 189 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 190 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 191 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 192 /* Source port of tunneling UDP */
 193 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 194 /* Destination port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 196 /* UDP Tunneling ID, NVGRE/GRE key */
 197 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 198 /* Last ether type */
 199 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 200 /* Tunneling outer destination IPv4 address */
 201 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 202 /* Tunneling outer destination IPv6 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 204 /* 1st word of flex payload */
 205 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 206 /* 2nd word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 208 /* 3rd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 210 /* 4th word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 212 /* 5th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 214 /* 6th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 216 /* 7th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 218 /* 8th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 220 /* all 8 words flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 222 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 223
 224 #define I40E_TRANSLATE_INSET 0
 225 #define I40E_TRANSLATE_REG   1
 226
 227 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 228 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 229 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 230 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 231 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 232 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 233
 234 /* PCI offset for querying capability */
 235 #define PCI_DEV_CAP_REG            0xA4
 236 /* PCI offset for enabling/disabling Extended Tag */
 237 #define PCI_DEV_CTRL_REG           0xA8
 238 /* Bit mask of Extended Tag capability */
 239 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 240 /* Bit shift of Extended Tag enable/disable */
 241 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 242 /* Bit mask of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 244
 245 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int i40e_dev_configure(struct rte_eth_dev *dev);
 248 static int i40e_dev_start(struct rte_eth_dev *dev);
 249 static void i40e_dev_stop(struct rte_eth_dev *dev);
 250 static void i40e_dev_close(struct rte_eth_dev *dev);
 251 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 258 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_stats *stats);
 260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_xstat *xstats, unsigned n);
 262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 263                                      struct rte_eth_xstat_name *xstats_names,
 264                                      unsigned limit);
 265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id,
 268                                             uint8_t stat_idx,
 269                                             uint8_t is_rx);
 270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 271                                 char *fw_version, size_t fw_size);
 272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 273                               struct rte_eth_dev_info *dev_info);
 274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 275                                 uint16_t vlan_id,
 276                                 int on);
 277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 278                               enum rte_vlan_type vlan_type,
 279                               uint16_t tpid);
 280 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 282                                       uint16_t queue,
 283                                       int on);
 284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 288                               struct rte_eth_fc_conf *fc_conf);
 289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 292                                        struct rte_eth_pfc_conf *pfc_conf);
 293 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 294                             struct ether_addr *mac_addr,
 295                             uint32_t index,
 296                             uint32_t pool);
 297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 299                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 300                                     uint16_t reta_size);
 301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 302                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                    uint16_t reta_size);
 304
 305 static int i40e_get_cap(struct i40e_hw *hw);
 306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 307 static int i40e_pf_setup(struct i40e_pf *pf);
 308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 310 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 311 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 312                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 313 static void i40e_stat_update_48(struct i40e_hw *hw,
 314                                uint32_t hireg,
 315                                uint32_t loreg,
 316                                bool offset_loaded,
 317                                uint64_t *offset,
 318                                uint64_t *stat);
 319 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 320 static void i40e_dev_interrupt_handler(void *param);
 321 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 322                                 uint32_t base, uint32_t num);
 323 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 324 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 325                         uint32_t base);
 326 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 327                         uint16_t num);
 328 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 329 static int i40e_veb_release(struct i40e_veb *veb);
 330 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 331                                                 struct i40e_vsi *vsi);
 332 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 333 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 334 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 335                                              struct i40e_macvlan_filter *mv_f,
 336                                              int num,
 337                                              uint16_t vlan);
 338 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 339 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 340                                     struct rte_eth_rss_conf *rss_conf);
 341 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 342                                       struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 344                                         struct rte_eth_udp_tunnel *udp_tunnel);
 345 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 348 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 349                                 enum rte_filter_op filter_op,
 350                                 void *arg);
 351 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 352                                 enum rte_filter_type filter_type,
 353                                 enum rte_filter_op filter_op,
 354                                 void *arg);
 355 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 356                                   struct rte_eth_dcb_info *dcb_info);
 357 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 358 static void i40e_configure_registers(struct i40e_hw *hw);
 359 static void i40e_hw_init(struct rte_eth_dev *dev);
 360 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 361 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 362                                                      uint16_t seid,
 363                                                      uint16_t rule_type,
 364                                                      uint16_t *entries,
 365                                                      uint16_t count,
 366                                                      uint16_t rule_id);
 367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 368                         struct rte_eth_mirror_conf *mirror_conf,
 369                         uint8_t sw_id, uint8_t on);
 370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 371
 372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp,
 376                                            uint32_t flags);
 377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp);
 379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 380
 381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 382
 383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 384                                    struct timespec *timestamp);
 385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 386                                     const struct timespec *timestamp);
 387
 388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 389                                          uint16_t queue_id);
 390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 391                                           uint16_t queue_id);
 392
 393 static int i40e_get_regs(struct rte_eth_dev *dev,
 394                          struct rte_dev_reg_info *regs);
 395
 396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 397
 398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 399                            struct rte_dev_eeprom_info *eeprom);
 400
 401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 402                                       struct ether_addr *mac_addr);
 403
 404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 405
 406 static int i40e_ethertype_filter_convert(
 407         const struct rte_eth_ethertype_filter *input,
 408         struct i40e_ethertype_filter *filter);
 409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 410                                    struct i40e_ethertype_filter *filter);
 411
 412 static int i40e_tunnel_filter_convert(
 413         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 414         struct i40e_tunnel_filter *tunnel_filter);
 415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 416                                 struct i40e_tunnel_filter *tunnel_filter);
 417 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 418
 419 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 420 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 421 static void i40e_filter_restore(struct i40e_pf *pf);
 422 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 423
 424 int i40e_logtype_init;
 425 int i40e_logtype_driver;
 426
 427 static const struct rte_pci_id pci_id_i40e_map[] = {
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 448         { .vendor_id = 0, /* sentinel */ },
 449 };
 450
 451 static const struct eth_dev_ops i40e_eth_dev_ops = {
 452         .dev_configure                = i40e_dev_configure,
 453         .dev_start                    = i40e_dev_start,
 454         .dev_stop                     = i40e_dev_stop,
 455         .dev_close                    = i40e_dev_close,
 456         .dev_reset                    = i40e_dev_reset,
 457         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 458         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 459         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 460         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 461         .dev_set_link_up              = i40e_dev_set_link_up,
 462         .dev_set_link_down            = i40e_dev_set_link_down,
 463         .link_update                  = i40e_dev_link_update,
 464         .stats_get                    = i40e_dev_stats_get,
 465         .xstats_get                   = i40e_dev_xstats_get,
 466         .xstats_get_names             = i40e_dev_xstats_get_names,
 467         .stats_reset                  = i40e_dev_stats_reset,
 468         .xstats_reset                 = i40e_dev_stats_reset,
 469         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 470         .fw_version_get               = i40e_fw_version_get,
 471         .dev_infos_get                = i40e_dev_info_get,
 472         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 473         .vlan_filter_set              = i40e_vlan_filter_set,
 474         .vlan_tpid_set                = i40e_vlan_tpid_set,
 475         .vlan_offload_set             = i40e_vlan_offload_set,
 476         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 477         .vlan_pvid_set                = i40e_vlan_pvid_set,
 478         .rx_queue_start               = i40e_dev_rx_queue_start,
 479         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 480         .tx_queue_start               = i40e_dev_tx_queue_start,
 481         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 482         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 483         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 484         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 485         .rx_queue_release             = i40e_dev_rx_queue_release,
 486         .rx_queue_count               = i40e_dev_rx_queue_count,
 487         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 488         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 489         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 490         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 491         .tx_queue_release             = i40e_dev_tx_queue_release,
 492         .dev_led_on                   = i40e_dev_led_on,
 493         .dev_led_off                  = i40e_dev_led_off,
 494         .flow_ctrl_get                = i40e_flow_ctrl_get,
 495         .flow_ctrl_set                = i40e_flow_ctrl_set,
 496         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 497         .mac_addr_add                 = i40e_macaddr_add,
 498         .mac_addr_remove              = i40e_macaddr_remove,
 499         .reta_update                  = i40e_dev_rss_reta_update,
 500         .reta_query                   = i40e_dev_rss_reta_query,
 501         .rss_hash_update              = i40e_dev_rss_hash_update,
 502         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 503         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 504         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 505         .filter_ctrl                  = i40e_dev_filter_ctrl,
 506         .rxq_info_get                 = i40e_rxq_info_get,
 507         .txq_info_get                 = i40e_txq_info_get,
 508         .mirror_rule_set              = i40e_mirror_rule_set,
 509         .mirror_rule_reset            = i40e_mirror_rule_reset,
 510         .timesync_enable              = i40e_timesync_enable,
 511         .timesync_disable             = i40e_timesync_disable,
 512         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 513         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 514         .get_dcb_info                 = i40e_dev_get_dcb_info,
 515         .timesync_adjust_time         = i40e_timesync_adjust_time,
 516         .timesync_read_time           = i40e_timesync_read_time,
 517         .timesync_write_time          = i40e_timesync_write_time,
 518         .get_reg                      = i40e_get_regs,
 519         .get_eeprom_length            = i40e_get_eeprom_length,
 520         .get_eeprom                   = i40e_get_eeprom,
 521         .mac_addr_set                 = i40e_set_default_mac_addr,
 522         .mtu_set                      = i40e_dev_mtu_set,
 523         .tm_ops_get                   = i40e_tm_ops_get,
 524 };
 525
 526 /* store statistics names and its offset in stats structure */
 527 struct rte_i40e_xstats_name_off {
 528         char name[RTE_ETH_XSTATS_NAME_SIZE];
 529         unsigned offset;
 530 };
 531
 532 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 533         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 534         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 535         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 536         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 537         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 538                 rx_unknown_protocol)},
 539         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 540         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 541         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 542         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 543 };
 544
 545 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 546                 sizeof(rte_i40e_stats_strings[0]))
 547
 548 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 549         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 550                 tx_dropped_link_down)},
 551         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 552         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 553                 illegal_bytes)},
 554         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 555         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 556                 mac_local_faults)},
 557         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 558                 mac_remote_faults)},
 559         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 560                 rx_length_errors)},
 561         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 562         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 563         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 564         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 565         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 566         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_127)},
 568         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_255)},
 570         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_511)},
 572         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_1023)},
 574         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_1522)},
 576         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_big)},
 578         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_undersize)},
 580         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 581                 rx_oversize)},
 582         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 583                 mac_short_packet_dropped)},
 584         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_fragments)},
 586         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 587         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 588         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_127)},
 590         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_255)},
 592         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_511)},
 594         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_1023)},
 596         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_1522)},
 598         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_big)},
 600         {"rx_flow_director_atr_match_packets",
 601                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 602         {"rx_flow_director_sb_match_packets",
 603                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 604         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 605                 tx_lpi_status)},
 606         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 607                 rx_lpi_status)},
 608         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 609                 tx_lpi_count)},
 610         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 611                 rx_lpi_count)},
 612 };
 613
 614 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 615                 sizeof(rte_i40e_hw_port_strings[0]))
 616
 617 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 618         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xon_rx)},
 620         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xoff_rx)},
 622 };
 623
 624 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 625                 sizeof(rte_i40e_rxq_prio_strings[0]))
 626
 627 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 628         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 629                 priority_xon_tx)},
 630         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 631                 priority_xoff_tx)},
 632         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 633                 priority_xon_2_xoff)},
 634 };
 635
 636 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 637                 sizeof(rte_i40e_txq_prio_strings[0]))
 638
 639 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 640         struct rte_pci_device *pci_dev)
 641 {
 642         return rte_eth_dev_pci_generic_probe(pci_dev,
 643                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 644 }
 645
 646 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 647 {
 648         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 649 }
 650
 651 static struct rte_pci_driver rte_i40e_pmd = {
 652         .id_table = pci_id_i40e_map,
 653         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 654                      RTE_PCI_DRV_IOVA_AS_VA,
 655         .probe = eth_i40e_pci_probe,
 656         .remove = eth_i40e_pci_remove,
 657 };
 658
 659 static inline int
 660 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 661                                      struct rte_eth_link *link)
 662 {
 663         struct rte_eth_link *dst = link;
 664         struct rte_eth_link *src = &(dev->data->dev_link);
 665
 666         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 667                                         *(uint64_t *)src) == 0)
 668                 return -1;
 669
 670         return 0;
 671 }
 672
 673 static inline int
 674 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 675                                       struct rte_eth_link *link)
 676 {
 677         struct rte_eth_link *dst = &(dev->data->dev_link);
 678         struct rte_eth_link *src = link;
 679
 680         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 681                                         *(uint64_t *)src) == 0)
 682                 return -1;
 683
 684         return 0;
 685 }
 686
 687 static inline void
 688 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 689 {
 690         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 691         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 692                     "with value 0x%08x",
 693                     reg_addr, reg_val);
 694 }
 695
 696 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 697 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 698 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 699
 700 #ifndef I40E_GLQF_ORT
 701 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 702 #endif
 703 #ifndef I40E_GLQF_PIT
 704 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 705 #endif
 706 #ifndef I40E_GLQF_L3_MAP
 707 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 708 #endif
 709
 710 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 711 {
 712         /*
 713          * Force global configuration for flexible payload
 714          * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
 715          * This should be removed from code once proper
 716          * configuration API is added to avoid configuration conflicts
 717          * between ports of the same device.
 718          */
 719         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 720         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 721         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 722         i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
 723
 724         /*
 725          * Initialize registers for parsing packet type of QinQ
 726          * This should be removed from code once proper
 727          * configuration API is added to avoid configuration conflicts
 728          * between ports of the same device.
 729          */
 730         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 731         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 732         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 733 }
 734
 735 static inline void i40e_config_automask(struct i40e_pf *pf)
 736 {
 737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 738         uint32_t val;
 739
 740         /* INTENA flag is not auto-cleared for interrupt */
 741         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 742         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 743                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 744
 745         /* If support multi-driver, PF will use INT0. */
 746         if (!pf->support_multi_driver)
 747                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 748
 749         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 750 }
 751
 752 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 753
 754 /*
 755  * Add a ethertype filter to drop all flow control frames transmitted
 756  * from VSIs.
 757 */
 758 static void
 759 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 760 {
 761         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 762         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 763                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 764                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 765         int ret;
 766
 767         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 768                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 769                                 pf->main_vsi_seid, 0,
 770                                 TRUE, NULL, NULL);
 771         if (ret)
 772                 PMD_INIT_LOG(ERR,
 773                         "Failed to add filter to drop flow control frames from VSIs.");
 774 }
 775
 776 static int
 777 floating_veb_list_handler(__rte_unused const char *key,
 778                           const char *floating_veb_value,
 779                           void *opaque)
 780 {
 781         int idx = 0;
 782         unsigned int count = 0;
 783         char *end = NULL;
 784         int min, max;
 785         bool *vf_floating_veb = opaque;
 786
 787         while (isblank(*floating_veb_value))
 788                 floating_veb_value++;
 789
 790         /* Reset floating VEB configuration for VFs */
 791         for (idx = 0; idx < I40E_MAX_VF; idx++)
 792                 vf_floating_veb[idx] = false;
 793
 794         min = I40E_MAX_VF;
 795         do {
 796                 while (isblank(*floating_veb_value))
 797                         floating_veb_value++;
 798                 if (*floating_veb_value == '\0')
 799                         return -1;
 800                 errno = 0;
 801                 idx = strtoul(floating_veb_value, &end, 10);
 802                 if (errno || end == NULL)
 803                         return -1;
 804                 while (isblank(*end))
 805                         end++;
 806                 if (*end == '-') {
 807                         min = idx;
 808                 } else if ((*end == ';') || (*end == '\0')) {
 809                         max = idx;
 810                         if (min == I40E_MAX_VF)
 811                                 min = idx;
 812                         if (max >= I40E_MAX_VF)
 813                                 max = I40E_MAX_VF - 1;
 814                         for (idx = min; idx <= max; idx++) {
 815                                 vf_floating_veb[idx] = true;
 816                                 count++;
 817                         }
 818                         min = I40E_MAX_VF;
 819                 } else {
 820                         return -1;
 821                 }
 822                 floating_veb_value = end + 1;
 823         } while (*end != '\0');
 824
 825         if (count == 0)
 826                 return -1;
 827
 828         return 0;
 829 }
 830
 831 static void
 832 config_vf_floating_veb(struct rte_devargs *devargs,
 833                        uint16_t floating_veb,
 834                        bool *vf_floating_veb)
 835 {
 836         struct rte_kvargs *kvlist;
 837         int i;
 838         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 839
 840         if (!floating_veb)
 841                 return;
 842         /* All the VFs attach to the floating VEB by default
 843          * when the floating VEB is enabled.
 844          */
 845         for (i = 0; i < I40E_MAX_VF; i++)
 846                 vf_floating_veb[i] = true;
 847
 848         if (devargs == NULL)
 849                 return;
 850
 851         kvlist = rte_kvargs_parse(devargs->args, NULL);
 852         if (kvlist == NULL)
 853                 return;
 854
 855         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 856                 rte_kvargs_free(kvlist);
 857                 return;
 858         }
 859         /* When the floating_veb_list parameter exists, all the VFs
 860          * will attach to the legacy VEB firstly, then configure VFs
 861          * to the floating VEB according to the floating_veb_list.
 862          */
 863         if (rte_kvargs_process(kvlist, floating_veb_list,
 864                                floating_veb_list_handler,
 865                                vf_floating_veb) < 0) {
 866                 rte_kvargs_free(kvlist);
 867                 return;
 868         }
 869         rte_kvargs_free(kvlist);
 870 }
 871
 872 static int
 873 i40e_check_floating_handler(__rte_unused const char *key,
 874                             const char *value,
 875                             __rte_unused void *opaque)
 876 {
 877         if (strcmp(value, "1"))
 878                 return -1;
 879
 880         return 0;
 881 }
 882
 883 static int
 884 is_floating_veb_supported(struct rte_devargs *devargs)
 885 {
 886         struct rte_kvargs *kvlist;
 887         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 888
 889         if (devargs == NULL)
 890                 return 0;
 891
 892         kvlist = rte_kvargs_parse(devargs->args, NULL);
 893         if (kvlist == NULL)
 894                 return 0;
 895
 896         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 897                 rte_kvargs_free(kvlist);
 898                 return 0;
 899         }
 900         /* Floating VEB is enabled when there's key-value:
 901          * enable_floating_veb=1
 902          */
 903         if (rte_kvargs_process(kvlist, floating_veb_key,
 904                                i40e_check_floating_handler, NULL) < 0) {
 905                 rte_kvargs_free(kvlist);
 906                 return 0;
 907         }
 908         rte_kvargs_free(kvlist);
 909
 910         return 1;
 911 }
 912
 913 static void
 914 config_floating_veb(struct rte_eth_dev *dev)
 915 {
 916         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 919
 920         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 921
 922         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 923                 pf->floating_veb =
 924                         is_floating_veb_supported(pci_dev->device.devargs);
 925                 config_vf_floating_veb(pci_dev->device.devargs,
 926                                        pf->floating_veb,
 927                                        pf->floating_veb_list);
 928         } else {
 929                 pf->floating_veb = false;
 930         }
 931 }
 932
 933 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 934 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 935
 936 static int
 937 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 938 {
 939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 940         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 941         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 942         int ret;
 943
 944         struct rte_hash_parameters ethertype_hash_params = {
 945                 .name = ethertype_hash_name,
 946                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 947                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 948                 .hash_func = rte_hash_crc,
 949                 .hash_func_init_val = 0,
 950                 .socket_id = rte_socket_id(),
 951         };
 952
 953         /* Initialize ethertype filter rule list and hash */
 954         TAILQ_INIT(&ethertype_rule->ethertype_list);
 955         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 956                  "ethertype_%s", dev->device->name);
 957         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 958         if (!ethertype_rule->hash_table) {
 959                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 960                 return -EINVAL;
 961         }
 962         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 963                                        sizeof(struct i40e_ethertype_filter *) *
 964                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 965                                        0);
 966         if (!ethertype_rule->hash_map) {
 967                 PMD_INIT_LOG(ERR,
 968                              "Failed to allocate memory for ethertype hash map!");
 969                 ret = -ENOMEM;
 970                 goto err_ethertype_hash_map_alloc;
 971         }
 972
 973         return 0;
 974
 975 err_ethertype_hash_map_alloc:
 976         rte_hash_free(ethertype_rule->hash_table);
 977
 978         return ret;
 979 }
 980
 981 static int
 982 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 983 {
 984         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 985         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 986         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 987         int ret;
 988
 989         struct rte_hash_parameters tunnel_hash_params = {
 990                 .name = tunnel_hash_name,
 991                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 992                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 993                 .hash_func = rte_hash_crc,
 994                 .hash_func_init_val = 0,
 995                 .socket_id = rte_socket_id(),
 996         };
 997
 998         /* Initialize tunnel filter rule list and hash */
 999         TAILQ_INIT(&tunnel_rule->tunnel_list);
1000         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1001                  "tunnel_%s", dev->device->name);
1002         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1003         if (!tunnel_rule->hash_table) {
1004                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1005                 return -EINVAL;
1006         }
1007         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1008                                     sizeof(struct i40e_tunnel_filter *) *
1009                                     I40E_MAX_TUNNEL_FILTER_NUM,
1010                                     0);
1011         if (!tunnel_rule->hash_map) {
1012                 PMD_INIT_LOG(ERR,
1013                              "Failed to allocate memory for tunnel hash map!");
1014                 ret = -ENOMEM;
1015                 goto err_tunnel_hash_map_alloc;
1016         }
1017
1018         return 0;
1019
1020 err_tunnel_hash_map_alloc:
1021         rte_hash_free(tunnel_rule->hash_table);
1022
1023         return ret;
1024 }
1025
1026 static int
1027 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1028 {
1029         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1030         struct i40e_fdir_info *fdir_info = &pf->fdir;
1031         char fdir_hash_name[RTE_HASH_NAMESIZE];
1032         int ret;
1033
1034         struct rte_hash_parameters fdir_hash_params = {
1035                 .name = fdir_hash_name,
1036                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1037                 .key_len = sizeof(struct i40e_fdir_input),
1038                 .hash_func = rte_hash_crc,
1039                 .hash_func_init_val = 0,
1040                 .socket_id = rte_socket_id(),
1041         };
1042
1043         /* Initialize flow director filter rule list and hash */
1044         TAILQ_INIT(&fdir_info->fdir_list);
1045         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1046                  "fdir_%s", dev->device->name);
1047         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1048         if (!fdir_info->hash_table) {
1049                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1050                 return -EINVAL;
1051         }
1052         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1053                                           sizeof(struct i40e_fdir_filter *) *
1054                                           I40E_MAX_FDIR_FILTER_NUM,
1055                                           0);
1056         if (!fdir_info->hash_map) {
1057                 PMD_INIT_LOG(ERR,
1058                              "Failed to allocate memory for fdir hash map!");
1059                 ret = -ENOMEM;
1060                 goto err_fdir_hash_map_alloc;
1061         }
1062         return 0;
1063
1064 err_fdir_hash_map_alloc:
1065         rte_hash_free(fdir_info->hash_table);
1066
1067         return ret;
1068 }
1069
1070 static void
1071 i40e_init_customized_info(struct i40e_pf *pf)
1072 {
1073         int i;
1074
1075         /* Initialize customized pctype */
1076         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1077                 pf->customized_pctype[i].index = i;
1078                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1079                 pf->customized_pctype[i].valid = false;
1080         }
1081
1082         pf->gtp_support = false;
1083 }
1084
1085 void
1086 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1087 {
1088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1089         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1090         struct i40e_queue_regions *info = &pf->queue_region;
1091         uint16_t i;
1092
1093         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1094                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1095
1096         memset(info, 0, sizeof(struct i40e_queue_regions));
1097 }
1098
1099 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1100
1101 static int
1102 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1103                                const char *value,
1104                                void *opaque)
1105 {
1106         struct i40e_pf *pf;
1107         unsigned long support_multi_driver;
1108         char *end;
1109
1110         pf = (struct i40e_pf *)opaque;
1111
1112         errno = 0;
1113         support_multi_driver = strtoul(value, &end, 10);
1114         if (errno != 0 || end == value || *end != 0) {
1115                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1116                 return -(EINVAL);
1117         }
1118
1119         if (support_multi_driver == 1 || support_multi_driver == 0)
1120                 pf->support_multi_driver = (bool)support_multi_driver;
1121         else
1122                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1123                             "enable global configuration by default."
1124                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1125         return 0;
1126 }
1127
1128 static int
1129 i40e_support_multi_driver(struct rte_eth_dev *dev)
1130 {
1131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1132         static const char *const valid_keys[] = {
1133                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1134         struct rte_kvargs *kvlist;
1135
1136         /* Enable global configuration by default */
1137         pf->support_multi_driver = false;
1138
1139         if (!dev->device->devargs)
1140                 return 0;
1141
1142         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1143         if (!kvlist)
1144                 return -EINVAL;
1145
1146         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1147                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1148                             "the first invalid or last valid one is used !",
1149                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1150
1151         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1152                                i40e_parse_multi_drv_handler, pf) < 0) {
1153                 rte_kvargs_free(kvlist);
1154                 return -EINVAL;
1155         }
1156
1157         rte_kvargs_free(kvlist);
1158         return 0;
1159 }
1160
1161 static int
1162 eth_i40e_dev_init(struct rte_eth_dev *dev)
1163 {
1164         struct rte_pci_device *pci_dev;
1165         struct rte_intr_handle *intr_handle;
1166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168         struct i40e_vsi *vsi;
1169         int ret;
1170         uint32_t len;
1171         uint8_t aq_fail = 0;
1172
1173         PMD_INIT_FUNC_TRACE();
1174
1175         dev->dev_ops = &i40e_eth_dev_ops;
1176         dev->rx_pkt_burst = i40e_recv_pkts;
1177         dev->tx_pkt_burst = i40e_xmit_pkts;
1178         dev->tx_pkt_prepare = i40e_prep_pkts;
1179
1180         /* for secondary processes, we don't initialise any further as primary
1181          * has already done this work. Only check we don't need a different
1182          * RX function */
1183         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1184                 i40e_set_rx_function(dev);
1185                 i40e_set_tx_function(dev);
1186                 return 0;
1187         }
1188         i40e_set_default_ptype_table(dev);
1189         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1190         intr_handle = &pci_dev->intr_handle;
1191
1192         rte_eth_copy_pci_info(dev, pci_dev);
1193
1194         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1195         pf->adapter->eth_dev = dev;
1196         pf->dev_data = dev->data;
1197
1198         hw->back = I40E_PF_TO_ADAPTER(pf);
1199         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1200         if (!hw->hw_addr) {
1201                 PMD_INIT_LOG(ERR,
1202                         "Hardware is not available, as address is NULL");
1203                 return -ENODEV;
1204         }
1205
1206         hw->vendor_id = pci_dev->id.vendor_id;
1207         hw->device_id = pci_dev->id.device_id;
1208         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1209         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1210         hw->bus.device = pci_dev->addr.devid;
1211         hw->bus.func = pci_dev->addr.function;
1212         hw->adapter_stopped = 0;
1213
1214         /* Check if need to support multi-driver */
1215         i40e_support_multi_driver(dev);
1216
1217         /* Make sure all is clean before doing PF reset */
1218         i40e_clear_hw(hw);
1219
1220         /* Initialize the hardware */
1221         i40e_hw_init(dev);
1222
1223         /* Reset here to make sure all is clean for each PF */
1224         ret = i40e_pf_reset(hw);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1227                 return ret;
1228         }
1229
1230         /* Initialize the shared code (base driver) */
1231         ret = i40e_init_shared_code(hw);
1232         if (ret) {
1233                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1234                 return ret;
1235         }
1236
1237         i40e_config_automask(pf);
1238
1239         i40e_set_default_pctype_table(dev);
1240
1241         /*
1242          * To work around the NVM issue, initialize registers
1243          * for flexible payload and packet type of QinQ by
1244          * software. It should be removed once issues are fixed
1245          * in NVM.
1246          */
1247         if (!pf->support_multi_driver)
1248                 i40e_GLQF_reg_init(hw);
1249
1250         /* Initialize the input set for filters (hash and fd) to default value */
1251         i40e_filter_input_set_init(pf);
1252
1253         /* Initialize the parameters for adminq */
1254         i40e_init_adminq_parameter(hw);
1255         ret = i40e_init_adminq(hw);
1256         if (ret != I40E_SUCCESS) {
1257                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1258                 return -EIO;
1259         }
1260         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1261                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1262                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1263                      ((hw->nvm.version >> 12) & 0xf),
1264                      ((hw->nvm.version >> 4) & 0xff),
1265                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1266
1267         /* initialise the L3_MAP register */
1268         if (!pf->support_multi_driver) {
1269                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1270                                                    0x00000028,  NULL);
1271                 if (ret)
1272                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1273                                      ret);
1274                 PMD_INIT_LOG(DEBUG,
1275                              "Global register 0x%08x is changed with 0x28",
1276                              I40E_GLQF_L3_MAP(40));
1277                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1278         }
1279
1280         /* Need the special FW version to support floating VEB */
1281         config_floating_veb(dev);
1282         /* Clear PXE mode */
1283         i40e_clear_pxe_mode(hw);
1284         i40e_dev_sync_phy_type(hw);
1285
1286         /*
1287          * On X710, performance number is far from the expectation on recent
1288          * firmware versions. The fix for this issue may not be integrated in
1289          * the following firmware version. So the workaround in software driver
1290          * is needed. It needs to modify the initial values of 3 internal only
1291          * registers. Note that the workaround can be removed when it is fixed
1292          * in firmware in the future.
1293          */
1294         i40e_configure_registers(hw);
1295
1296         /* Get hw capabilities */
1297         ret = i40e_get_cap(hw);
1298         if (ret != I40E_SUCCESS) {
1299                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1300                 goto err_get_capabilities;
1301         }
1302
1303         /* Initialize parameters for PF */
1304         ret = i40e_pf_parameter_init(dev);
1305         if (ret != 0) {
1306                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1307                 goto err_parameter_init;
1308         }
1309
1310         /* Initialize the queue management */
1311         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1312         if (ret < 0) {
1313                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1314                 goto err_qp_pool_init;
1315         }
1316         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1317                                 hw->func_caps.num_msix_vectors - 1);
1318         if (ret < 0) {
1319                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1320                 goto err_msix_pool_init;
1321         }
1322
1323         /* Initialize lan hmc */
1324         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1325                                 hw->func_caps.num_rx_qp, 0, 0);
1326         if (ret != I40E_SUCCESS) {
1327                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1328                 goto err_init_lan_hmc;
1329         }
1330
1331         /* Configure lan hmc */
1332         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1333         if (ret != I40E_SUCCESS) {
1334                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1335                 goto err_configure_lan_hmc;
1336         }
1337
1338         /* Get and check the mac address */
1339         i40e_get_mac_addr(hw, hw->mac.addr);
1340         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1341                 PMD_INIT_LOG(ERR, "mac address is not valid");
1342                 ret = -EIO;
1343                 goto err_get_mac_addr;
1344         }
1345         /* Copy the permanent MAC address */
1346         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1347                         (struct ether_addr *) hw->mac.perm_addr);
1348
1349         /* Disable flow control */
1350         hw->fc.requested_mode = I40E_FC_NONE;
1351         i40e_set_fc(hw, &aq_fail, TRUE);
1352
1353         /* Set the global registers with default ether type value */
1354         if (!pf->support_multi_driver) {
1355                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1356                                          ETHER_TYPE_VLAN);
1357                 if (ret != I40E_SUCCESS) {
1358                         PMD_INIT_LOG(ERR,
1359                                      "Failed to set the default outer "
1360                                      "VLAN ether type");
1361                         goto err_setup_pf_switch;
1362                 }
1363         }
1364
1365         /* PF setup, which includes VSI setup */
1366         ret = i40e_pf_setup(pf);
1367         if (ret) {
1368                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1369                 goto err_setup_pf_switch;
1370         }
1371
1372         /* reset all stats of the device, including pf and main vsi */
1373         i40e_dev_stats_reset(dev);
1374
1375         vsi = pf->main_vsi;
1376
1377         /* Disable double vlan by default */
1378         i40e_vsi_config_double_vlan(vsi, FALSE);
1379
1380         /* Disable S-TAG identification when floating_veb is disabled */
1381         if (!pf->floating_veb) {
1382                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1383                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1384                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1385                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1386                 }
1387         }
1388
1389         if (!vsi->max_macaddrs)
1390                 len = ETHER_ADDR_LEN;
1391         else
1392                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1393
1394         /* Should be after VSI initialized */
1395         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1396         if (!dev->data->mac_addrs) {
1397                 PMD_INIT_LOG(ERR,
1398                         "Failed to allocated memory for storing mac address");
1399                 goto err_mac_alloc;
1400         }
1401         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1402                                         &dev->data->mac_addrs[0]);
1403
1404         /* Init dcb to sw mode by default */
1405         ret = i40e_dcb_init_configure(dev, TRUE);
1406         if (ret != I40E_SUCCESS) {
1407                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1408                 pf->flags &= ~I40E_FLAG_DCB;
1409         }
1410         /* Update HW struct after DCB configuration */
1411         i40e_get_cap(hw);
1412
1413         /* initialize pf host driver to setup SRIOV resource if applicable */
1414         i40e_pf_host_init(dev);
1415
1416         /* register callback func to eal lib */
1417         rte_intr_callback_register(intr_handle,
1418                                    i40e_dev_interrupt_handler, dev);
1419
1420         /* configure and enable device interrupt */
1421         i40e_pf_config_irq0(hw, TRUE);
1422         i40e_pf_enable_irq0(hw);
1423
1424         /* enable uio intr after callback register */
1425         rte_intr_enable(intr_handle);
1426         /*
1427          * Add an ethertype filter to drop all flow control frames transmitted
1428          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1429          * frames to wire.
1430          */
1431         i40e_add_tx_flow_control_drop_filter(pf);
1432
1433         /* Set the max frame size to 0x2600 by default,
1434          * in case other drivers changed the default value.
1435          */
1436         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1437
1438         /* initialize mirror rule list */
1439         TAILQ_INIT(&pf->mirror_list);
1440
1441         /* initialize Traffic Manager configuration */
1442         i40e_tm_conf_init(dev);
1443
1444         /* Initialize customized information */
1445         i40e_init_customized_info(pf);
1446
1447         ret = i40e_init_ethtype_filter_list(dev);
1448         if (ret < 0)
1449                 goto err_init_ethtype_filter_list;
1450         ret = i40e_init_tunnel_filter_list(dev);
1451         if (ret < 0)
1452                 goto err_init_tunnel_filter_list;
1453         ret = i40e_init_fdir_filter_list(dev);
1454         if (ret < 0)
1455                 goto err_init_fdir_filter_list;
1456
1457         /* initialize queue region configuration */
1458         i40e_init_queue_region_conf(dev);
1459
1460         return 0;
1461
1462 err_init_fdir_filter_list:
1463         rte_free(pf->tunnel.hash_table);
1464         rte_free(pf->tunnel.hash_map);
1465 err_init_tunnel_filter_list:
1466         rte_free(pf->ethertype.hash_table);
1467         rte_free(pf->ethertype.hash_map);
1468 err_init_ethtype_filter_list:
1469         rte_free(dev->data->mac_addrs);
1470 err_mac_alloc:
1471         i40e_vsi_release(pf->main_vsi);
1472 err_setup_pf_switch:
1473 err_get_mac_addr:
1474 err_configure_lan_hmc:
1475         (void)i40e_shutdown_lan_hmc(hw);
1476 err_init_lan_hmc:
1477         i40e_res_pool_destroy(&pf->msix_pool);
1478 err_msix_pool_init:
1479         i40e_res_pool_destroy(&pf->qp_pool);
1480 err_qp_pool_init:
1481 err_parameter_init:
1482 err_get_capabilities:
1483         (void)i40e_shutdown_adminq(hw);
1484
1485         return ret;
1486 }
1487
1488 static void
1489 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1490 {
1491         struct i40e_ethertype_filter *p_ethertype;
1492         struct i40e_ethertype_rule *ethertype_rule;
1493
1494         ethertype_rule = &pf->ethertype;
1495         /* Remove all ethertype filter rules and hash */
1496         if (ethertype_rule->hash_map)
1497                 rte_free(ethertype_rule->hash_map);
1498         if (ethertype_rule->hash_table)
1499                 rte_hash_free(ethertype_rule->hash_table);
1500
1501         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1502                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1503                              p_ethertype, rules);
1504                 rte_free(p_ethertype);
1505         }
1506 }
1507
1508 static void
1509 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1510 {
1511         struct i40e_tunnel_filter *p_tunnel;
1512         struct i40e_tunnel_rule *tunnel_rule;
1513
1514         tunnel_rule = &pf->tunnel;
1515         /* Remove all tunnel director rules and hash */
1516         if (tunnel_rule->hash_map)
1517                 rte_free(tunnel_rule->hash_map);
1518         if (tunnel_rule->hash_table)
1519                 rte_hash_free(tunnel_rule->hash_table);
1520
1521         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1522                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1523                 rte_free(p_tunnel);
1524         }
1525 }
1526
1527 static void
1528 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1529 {
1530         struct i40e_fdir_filter *p_fdir;
1531         struct i40e_fdir_info *fdir_info;
1532
1533         fdir_info = &pf->fdir;
1534         /* Remove all flow director rules and hash */
1535         if (fdir_info->hash_map)
1536                 rte_free(fdir_info->hash_map);
1537         if (fdir_info->hash_table)
1538                 rte_hash_free(fdir_info->hash_table);
1539
1540         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1541                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1542                 rte_free(p_fdir);
1543         }
1544 }
1545
1546 static int
1547 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1548 {
1549         struct i40e_pf *pf;
1550         struct rte_pci_device *pci_dev;
1551         struct rte_intr_handle *intr_handle;
1552         struct i40e_hw *hw;
1553         struct i40e_filter_control_settings settings;
1554         struct rte_flow *p_flow;
1555         int ret;
1556         uint8_t aq_fail = 0;
1557         int retries = 0;
1558
1559         PMD_INIT_FUNC_TRACE();
1560
1561         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1562                 return 0;
1563
1564         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1565         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1567         intr_handle = &pci_dev->intr_handle;
1568
1569         if (hw->adapter_stopped == 0)
1570                 i40e_dev_close(dev);
1571
1572         dev->dev_ops = NULL;
1573         dev->rx_pkt_burst = NULL;
1574         dev->tx_pkt_burst = NULL;
1575
1576         /* Clear PXE mode */
1577         i40e_clear_pxe_mode(hw);
1578
1579         /* Unconfigure filter control */
1580         memset(&settings, 0, sizeof(settings));
1581         ret = i40e_set_filter_control(hw, &settings);
1582         if (ret)
1583                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1584                                         ret);
1585
1586         /* Disable flow control */
1587         hw->fc.requested_mode = I40E_FC_NONE;
1588         i40e_set_fc(hw, &aq_fail, TRUE);
1589
1590         /* uninitialize pf host driver */
1591         i40e_pf_host_uninit(dev);
1592
1593         rte_free(dev->data->mac_addrs);
1594         dev->data->mac_addrs = NULL;
1595
1596         /* disable uio intr before callback unregister */
1597         rte_intr_disable(intr_handle);
1598
1599         /* unregister callback func to eal lib */
1600         do {
1601                 ret = rte_intr_callback_unregister(intr_handle,
1602                                 i40e_dev_interrupt_handler, dev);
1603                 if (ret >= 0) {
1604                         break;
1605                 } else if (ret != -EAGAIN) {
1606                         PMD_INIT_LOG(ERR,
1607                                  "intr callback unregister failed: %d",
1608                                  ret);
1609                         return ret;
1610                 }
1611                 i40e_msec_delay(500);
1612         } while (retries++ < 5);
1613
1614         i40e_rm_ethtype_filter_list(pf);
1615         i40e_rm_tunnel_filter_list(pf);
1616         i40e_rm_fdir_filter_list(pf);
1617
1618         /* Remove all flows */
1619         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1620                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1621                 rte_free(p_flow);
1622         }
1623
1624         /* Remove all Traffic Manager configuration */
1625         i40e_tm_conf_uninit(dev);
1626
1627         return 0;
1628 }
1629
1630 static int
1631 i40e_dev_configure(struct rte_eth_dev *dev)
1632 {
1633         struct i40e_adapter *ad =
1634                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1635         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1638         int i, ret;
1639
1640         ret = i40e_dev_sync_phy_type(hw);
1641         if (ret)
1642                 return ret;
1643
1644         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1645          * bulk allocation or vector Rx preconditions we will reset it.
1646          */
1647         ad->rx_bulk_alloc_allowed = true;
1648         ad->rx_vec_allowed = true;
1649         ad->tx_simple_allowed = true;
1650         ad->tx_vec_allowed = true;
1651
1652         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1653                 ret = i40e_fdir_setup(pf);
1654                 if (ret != I40E_SUCCESS) {
1655                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1656                         return -ENOTSUP;
1657                 }
1658                 ret = i40e_fdir_configure(dev);
1659                 if (ret < 0) {
1660                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1661                         goto err;
1662                 }
1663         } else
1664                 i40e_fdir_teardown(pf);
1665
1666         ret = i40e_dev_init_vlan(dev);
1667         if (ret < 0)
1668                 goto err;
1669
1670         /* VMDQ setup.
1671          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1672          *  RSS setting have different requirements.
1673          *  General PMD driver call sequence are NIC init, configure,
1674          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1675          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1676          *  applicable. So, VMDQ setting has to be done before
1677          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1678          *  For RSS setting, it will try to calculate actual configured RX queue
1679          *  number, which will be available after rx_queue_setup(). dev_start()
1680          *  function is good to place RSS setup.
1681          */
1682         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1683                 ret = i40e_vmdq_setup(dev);
1684                 if (ret)
1685                         goto err;
1686         }
1687
1688         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1689                 ret = i40e_dcb_setup(dev);
1690                 if (ret) {
1691                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1692                         goto err_dcb;
1693                 }
1694         }
1695
1696         TAILQ_INIT(&pf->flow_list);
1697
1698         return 0;
1699
1700 err_dcb:
1701         /* need to release vmdq resource if exists */
1702         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1703                 i40e_vsi_release(pf->vmdq[i].vsi);
1704                 pf->vmdq[i].vsi = NULL;
1705         }
1706         rte_free(pf->vmdq);
1707         pf->vmdq = NULL;
1708 err:
1709         /* need to release fdir resource if exists */
1710         i40e_fdir_teardown(pf);
1711         return ret;
1712 }
1713
1714 void
1715 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1716 {
1717         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1718         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1719         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1720         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1721         uint16_t msix_vect = vsi->msix_intr;
1722         uint16_t i;
1723
1724         for (i = 0; i < vsi->nb_qps; i++) {
1725                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1726                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1727                 rte_wmb();
1728         }
1729
1730         if (vsi->type != I40E_VSI_SRIOV) {
1731                 if (!rte_intr_allow_others(intr_handle)) {
1732                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1733                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1734                         I40E_WRITE_REG(hw,
1735                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1736                                        0);
1737                 } else {
1738                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1739                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1740                         I40E_WRITE_REG(hw,
1741                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1742                                                        msix_vect - 1), 0);
1743                 }
1744         } else {
1745                 uint32_t reg;
1746                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1747                         vsi->user_param + (msix_vect - 1);
1748
1749                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1750                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1751         }
1752         I40E_WRITE_FLUSH(hw);
1753 }
1754
1755 static void
1756 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1757                        int base_queue, int nb_queue,
1758                        uint16_t itr_idx)
1759 {
1760         int i;
1761         uint32_t val;
1762         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1763         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1764
1765         /* Bind all RX queues to allocated MSIX interrupt */
1766         for (i = 0; i < nb_queue; i++) {
1767                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1768                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1769                         ((base_queue + i + 1) <<
1770                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1771                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1772                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1773
1774                 if (i == nb_queue - 1)
1775                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1776                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1777         }
1778
1779         /* Write first RX queue to Link list register as the head element */
1780         if (vsi->type != I40E_VSI_SRIOV) {
1781                 uint16_t interval =
1782                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL,
1783                                                pf->support_multi_driver);
1784
1785                 if (msix_vect == I40E_MISC_VEC_ID) {
1786                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1787                                        (base_queue <<
1788                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1789                                        (0x0 <<
1790                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1791                         I40E_WRITE_REG(hw,
1792                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1793                                        interval);
1794                 } else {
1795                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1796                                        (base_queue <<
1797                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1798                                        (0x0 <<
1799                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1800                         I40E_WRITE_REG(hw,
1801                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1802                                                        msix_vect - 1),
1803                                        interval);
1804                 }
1805         } else {
1806                 uint32_t reg;
1807
1808                 if (msix_vect == I40E_MISC_VEC_ID) {
1809                         I40E_WRITE_REG(hw,
1810                                        I40E_VPINT_LNKLST0(vsi->user_param),
1811                                        (base_queue <<
1812                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1813                                        (0x0 <<
1814                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1815                 } else {
1816                         /* num_msix_vectors_vf needs to minus irq0 */
1817                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1818                                 vsi->user_param + (msix_vect - 1);
1819
1820                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1821                                        (base_queue <<
1822                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1823                                        (0x0 <<
1824                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1825                 }
1826         }
1827
1828         I40E_WRITE_FLUSH(hw);
1829 }
1830
1831 void
1832 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1833 {
1834         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1835         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1836         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1837         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1838         uint16_t msix_vect = vsi->msix_intr;
1839         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1840         uint16_t queue_idx = 0;
1841         int record = 0;
1842         int i;
1843
1844         for (i = 0; i < vsi->nb_qps; i++) {
1845                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1846                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1847         }
1848
1849         /* VF bind interrupt */
1850         if (vsi->type == I40E_VSI_SRIOV) {
1851                 __vsi_queues_bind_intr(vsi, msix_vect,
1852                                        vsi->base_queue, vsi->nb_qps,
1853                                        itr_idx);
1854                 return;
1855         }
1856
1857         /* PF & VMDq bind interrupt */
1858         if (rte_intr_dp_is_en(intr_handle)) {
1859                 if (vsi->type == I40E_VSI_MAIN) {
1860                         queue_idx = 0;
1861                         record = 1;
1862                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1863                         struct i40e_vsi *main_vsi =
1864                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1865                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1866                         record = 1;
1867                 }
1868         }
1869
1870         for (i = 0; i < vsi->nb_used_qps; i++) {
1871                 if (nb_msix <= 1) {
1872                         if (!rte_intr_allow_others(intr_handle))
1873                                 /* allow to share MISC_VEC_ID */
1874                                 msix_vect = I40E_MISC_VEC_ID;
1875
1876                         /* no enough msix_vect, map all to one */
1877                         __vsi_queues_bind_intr(vsi, msix_vect,
1878                                                vsi->base_queue + i,
1879                                                vsi->nb_used_qps - i,
1880                                                itr_idx);
1881                         for (; !!record && i < vsi->nb_used_qps; i++)
1882                                 intr_handle->intr_vec[queue_idx + i] =
1883                                         msix_vect;
1884                         break;
1885                 }
1886                 /* 1:1 queue/msix_vect mapping */
1887                 __vsi_queues_bind_intr(vsi, msix_vect,
1888                                        vsi->base_queue + i, 1,
1889                                        itr_idx);
1890                 if (!!record)
1891                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1892
1893                 msix_vect++;
1894                 nb_msix--;
1895         }
1896 }
1897
1898 static void
1899 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1900 {
1901         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1902         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1903         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1904         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1905         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1906         uint16_t msix_intr, i;
1907
1908         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1909                 for (i = 0; i < vsi->nb_msix; i++) {
1910                         msix_intr = vsi->msix_intr + i;
1911                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1912                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1913                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1914                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1915                 }
1916         else
1917                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1918                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1919                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1920                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1921
1922         I40E_WRITE_FLUSH(hw);
1923 }
1924
1925 static void
1926 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1927 {
1928         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1929         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1930         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1931         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1932         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1933         uint16_t msix_intr, i;
1934
1935         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1936                 for (i = 0; i < vsi->nb_msix; i++) {
1937                         msix_intr = vsi->msix_intr + i;
1938                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1939                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1940                 }
1941         else
1942                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1943                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1944
1945         I40E_WRITE_FLUSH(hw);
1946 }
1947
1948 static inline uint8_t
1949 i40e_parse_link_speeds(uint16_t link_speeds)
1950 {
1951         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1952
1953         if (link_speeds & ETH_LINK_SPEED_40G)
1954                 link_speed |= I40E_LINK_SPEED_40GB;
1955         if (link_speeds & ETH_LINK_SPEED_25G)
1956                 link_speed |= I40E_LINK_SPEED_25GB;
1957         if (link_speeds & ETH_LINK_SPEED_20G)
1958                 link_speed |= I40E_LINK_SPEED_20GB;
1959         if (link_speeds & ETH_LINK_SPEED_10G)
1960                 link_speed |= I40E_LINK_SPEED_10GB;
1961         if (link_speeds & ETH_LINK_SPEED_1G)
1962                 link_speed |= I40E_LINK_SPEED_1GB;
1963         if (link_speeds & ETH_LINK_SPEED_100M)
1964                 link_speed |= I40E_LINK_SPEED_100MB;
1965
1966         return link_speed;
1967 }
1968
1969 static int
1970 i40e_phy_conf_link(struct i40e_hw *hw,
1971                    uint8_t abilities,
1972                    uint8_t force_speed,
1973                    bool is_up)
1974 {
1975         enum i40e_status_code status;
1976         struct i40e_aq_get_phy_abilities_resp phy_ab;
1977         struct i40e_aq_set_phy_config phy_conf;
1978         enum i40e_aq_phy_type cnt;
1979         uint32_t phy_type_mask = 0;
1980
1981         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1982                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1983                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1984                         I40E_AQ_PHY_FLAG_LOW_POWER;
1985         const uint8_t advt = I40E_LINK_SPEED_40GB |
1986                         I40E_LINK_SPEED_25GB |
1987                         I40E_LINK_SPEED_10GB |
1988                         I40E_LINK_SPEED_1GB |
1989                         I40E_LINK_SPEED_100MB;
1990         int ret = -ENOTSUP;
1991
1992
1993         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1994                                               NULL);
1995         if (status)
1996                 return ret;
1997
1998         /* If link already up, no need to set up again */
1999         if (is_up && phy_ab.phy_type != 0)
2000                 return I40E_SUCCESS;
2001
2002         memset(&phy_conf, 0, sizeof(phy_conf));
2003
2004         /* bits 0-2 use the values from get_phy_abilities_resp */
2005         abilities &= ~mask;
2006         abilities |= phy_ab.abilities & mask;
2007
2008         /* update ablities and speed */
2009         if (abilities & I40E_AQ_PHY_AN_ENABLED)
2010                 phy_conf.link_speed = advt;
2011         else
2012                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2013
2014         phy_conf.abilities = abilities;
2015
2016
2017
2018         /* To enable link, phy_type mask needs to include each type */
2019         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
2020                 phy_type_mask |= 1 << cnt;
2021
2022         /* use get_phy_abilities_resp value for the rest */
2023         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2024         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2025                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2026                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2027         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2028         phy_conf.eee_capability = phy_ab.eee_capability;
2029         phy_conf.eeer = phy_ab.eeer_val;
2030         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2031
2032         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2033                     phy_ab.abilities, phy_ab.link_speed);
2034         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2035                     phy_conf.abilities, phy_conf.link_speed);
2036
2037         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2038         if (status)
2039                 return ret;
2040
2041         return I40E_SUCCESS;
2042 }
2043
2044 static int
2045 i40e_apply_link_speed(struct rte_eth_dev *dev)
2046 {
2047         uint8_t speed;
2048         uint8_t abilities = 0;
2049         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2050         struct rte_eth_conf *conf = &dev->data->dev_conf;
2051
2052         speed = i40e_parse_link_speeds(conf->link_speeds);
2053         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2054         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2055                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2056         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2057
2058         return i40e_phy_conf_link(hw, abilities, speed, true);
2059 }
2060
2061 static int
2062 i40e_dev_start(struct rte_eth_dev *dev)
2063 {
2064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2066         struct i40e_vsi *main_vsi = pf->main_vsi;
2067         int ret, i;
2068         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2069         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2070         uint32_t intr_vector = 0;
2071         struct i40e_vsi *vsi;
2072
2073         hw->adapter_stopped = 0;
2074
2075         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2076                 PMD_INIT_LOG(ERR,
2077                 "Invalid link_speeds for port %u, autonegotiation disabled",
2078                               dev->data->port_id);
2079                 return -EINVAL;
2080         }
2081
2082         rte_intr_disable(intr_handle);
2083
2084         if ((rte_intr_cap_multiple(intr_handle) ||
2085              !RTE_ETH_DEV_SRIOV(dev).active) &&
2086             dev->data->dev_conf.intr_conf.rxq != 0) {
2087                 intr_vector = dev->data->nb_rx_queues;
2088                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2089                 if (ret)
2090                         return ret;
2091         }
2092
2093         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2094                 intr_handle->intr_vec =
2095                         rte_zmalloc("intr_vec",
2096                                     dev->data->nb_rx_queues * sizeof(int),
2097                                     0);
2098                 if (!intr_handle->intr_vec) {
2099                         PMD_INIT_LOG(ERR,
2100                                 "Failed to allocate %d rx_queues intr_vec",
2101                                 dev->data->nb_rx_queues);
2102                         return -ENOMEM;
2103                 }
2104         }
2105
2106         /* Initialize VSI */
2107         ret = i40e_dev_rxtx_init(pf);
2108         if (ret != I40E_SUCCESS) {
2109                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2110                 goto err_up;
2111         }
2112
2113         /* Map queues with MSIX interrupt */
2114         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2115                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2116         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2117         i40e_vsi_enable_queues_intr(main_vsi);
2118
2119         /* Map VMDQ VSI queues with MSIX interrupt */
2120         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2121                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2122                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2123                                           I40E_ITR_INDEX_DEFAULT);
2124                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2125         }
2126
2127         /* enable FDIR MSIX interrupt */
2128         if (pf->fdir.fdir_vsi) {
2129                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2130                                           I40E_ITR_INDEX_NONE);
2131                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2132         }
2133
2134         /* Enable all queues which have been configured */
2135         ret = i40e_dev_switch_queues(pf, TRUE);
2136         if (ret != I40E_SUCCESS) {
2137                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2138                 goto err_up;
2139         }
2140
2141         /* Enable receiving broadcast packets */
2142         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2143         if (ret != I40E_SUCCESS)
2144                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2145
2146         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2147                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2148                                                 true, NULL);
2149                 if (ret != I40E_SUCCESS)
2150                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2151         }
2152
2153         /* Enable the VLAN promiscuous mode. */
2154         if (pf->vfs) {
2155                 for (i = 0; i < pf->vf_num; i++) {
2156                         vsi = pf->vfs[i].vsi;
2157                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2158                                                      true, NULL);
2159                 }
2160         }
2161
2162         /* Apply link configure */
2163         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2164                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2165                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2166                                 ETH_LINK_SPEED_40G)) {
2167                 PMD_DRV_LOG(ERR, "Invalid link setting");
2168                 goto err_up;
2169         }
2170         ret = i40e_apply_link_speed(dev);
2171         if (I40E_SUCCESS != ret) {
2172                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2173                 goto err_up;
2174         }
2175
2176         if (!rte_intr_allow_others(intr_handle)) {
2177                 rte_intr_callback_unregister(intr_handle,
2178                                              i40e_dev_interrupt_handler,
2179                                              (void *)dev);
2180                 /* configure and enable device interrupt */
2181                 i40e_pf_config_irq0(hw, FALSE);
2182                 i40e_pf_enable_irq0(hw);
2183
2184                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2185                         PMD_INIT_LOG(INFO,
2186                                 "lsc won't enable because of no intr multiplex");
2187         } else {
2188                 ret = i40e_aq_set_phy_int_mask(hw,
2189                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2190                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2191                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2192                 if (ret != I40E_SUCCESS)
2193                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2194
2195                 /* Call get_link_info aq commond to enable/disable LSE */
2196                 i40e_dev_link_update(dev, 0);
2197         }
2198
2199         /* enable uio intr after callback register */
2200         rte_intr_enable(intr_handle);
2201
2202         i40e_filter_restore(pf);
2203
2204         if (pf->tm_conf.root && !pf->tm_conf.committed)
2205                 PMD_DRV_LOG(WARNING,
2206                             "please call hierarchy_commit() "
2207                             "before starting the port");
2208
2209         return I40E_SUCCESS;
2210
2211 err_up:
2212         i40e_dev_switch_queues(pf, FALSE);
2213         i40e_dev_clear_queues(dev);
2214
2215         return ret;
2216 }
2217
2218 static void
2219 i40e_dev_stop(struct rte_eth_dev *dev)
2220 {
2221         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2222         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2223         struct i40e_vsi *main_vsi = pf->main_vsi;
2224         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2225         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2226         int i;
2227
2228         if (hw->adapter_stopped == 1)
2229                 return;
2230         /* Disable all queues */
2231         i40e_dev_switch_queues(pf, FALSE);
2232
2233         /* un-map queues with interrupt registers */
2234         i40e_vsi_disable_queues_intr(main_vsi);
2235         i40e_vsi_queues_unbind_intr(main_vsi);
2236
2237         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2238                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2239                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2240         }
2241
2242         if (pf->fdir.fdir_vsi) {
2243                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2244                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2245         }
2246         /* Clear all queues and release memory */
2247         i40e_dev_clear_queues(dev);
2248
2249         /* Set link down */
2250         i40e_dev_set_link_down(dev);
2251
2252         if (!rte_intr_allow_others(intr_handle))
2253                 /* resume to the default handler */
2254                 rte_intr_callback_register(intr_handle,
2255                                            i40e_dev_interrupt_handler,
2256                                            (void *)dev);
2257
2258         /* Clean datapath event and queue/vec mapping */
2259         rte_intr_efd_disable(intr_handle);
2260         if (intr_handle->intr_vec) {
2261                 rte_free(intr_handle->intr_vec);
2262                 intr_handle->intr_vec = NULL;
2263         }
2264
2265         /* reset hierarchy commit */
2266         pf->tm_conf.committed = false;
2267
2268         hw->adapter_stopped = 1;
2269 }
2270
2271 static void
2272 i40e_dev_close(struct rte_eth_dev *dev)
2273 {
2274         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2277         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2278         struct i40e_mirror_rule *p_mirror;
2279         uint32_t reg;
2280         int i;
2281         int ret;
2282
2283         PMD_INIT_FUNC_TRACE();
2284
2285         i40e_dev_stop(dev);
2286
2287         /* Remove all mirror rules */
2288         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2289                 ret = i40e_aq_del_mirror_rule(hw,
2290                                               pf->main_vsi->veb->seid,
2291                                               p_mirror->rule_type,
2292                                               p_mirror->entries,
2293                                               p_mirror->num_entries,
2294                                               p_mirror->id);
2295                 if (ret < 0)
2296                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2297                                     "status = %d, aq_err = %d.", ret,
2298                                     hw->aq.asq_last_status);
2299
2300                 /* remove mirror software resource anyway */
2301                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2302                 rte_free(p_mirror);
2303                 pf->nb_mirror_rule--;
2304         }
2305
2306         i40e_dev_free_queues(dev);
2307
2308         /* Disable interrupt */
2309         i40e_pf_disable_irq0(hw);
2310         rte_intr_disable(intr_handle);
2311
2312         i40e_fdir_teardown(pf);
2313
2314         /* shutdown and destroy the HMC */
2315         i40e_shutdown_lan_hmc(hw);
2316
2317         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2318                 i40e_vsi_release(pf->vmdq[i].vsi);
2319                 pf->vmdq[i].vsi = NULL;
2320         }
2321         rte_free(pf->vmdq);
2322         pf->vmdq = NULL;
2323
2324         /* release all the existing VSIs and VEBs */
2325         i40e_vsi_release(pf->main_vsi);
2326
2327         /* shutdown the adminq */
2328         i40e_aq_queue_shutdown(hw, true);
2329         i40e_shutdown_adminq(hw);
2330
2331         i40e_res_pool_destroy(&pf->qp_pool);
2332         i40e_res_pool_destroy(&pf->msix_pool);
2333
2334         /* force a PF reset to clean anything leftover */
2335         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2336         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2337                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2338         I40E_WRITE_FLUSH(hw);
2339 }
2340
2341 /*
2342  * Reset PF device only to re-initialize resources in PMD layer
2343  */
2344 static int
2345 i40e_dev_reset(struct rte_eth_dev *dev)
2346 {
2347         int ret;
2348
2349         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2350          * its VF to make them align with it. The detailed notification
2351          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2352          * To avoid unexpected behavior in VF, currently reset of PF with
2353          * SR-IOV activation is not supported. It might be supported later.
2354          */
2355         if (dev->data->sriov.active)
2356                 return -ENOTSUP;
2357
2358         ret = eth_i40e_dev_uninit(dev);
2359         if (ret)
2360                 return ret;
2361
2362         ret = eth_i40e_dev_init(dev);
2363
2364         return ret;
2365 }
2366
2367 static void
2368 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2369 {
2370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2371         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         struct i40e_vsi *vsi = pf->main_vsi;
2373         int status;
2374
2375         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2376                                                      true, NULL, true);
2377         if (status != I40E_SUCCESS)
2378                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2379
2380         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2381                                                         TRUE, NULL);
2382         if (status != I40E_SUCCESS)
2383                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2384
2385 }
2386
2387 static void
2388 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2389 {
2390         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392         struct i40e_vsi *vsi = pf->main_vsi;
2393         int status;
2394
2395         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2396                                                      false, NULL, true);
2397         if (status != I40E_SUCCESS)
2398                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2399
2400         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2401                                                         false, NULL);
2402         if (status != I40E_SUCCESS)
2403                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2404 }
2405
2406 static void
2407 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2408 {
2409         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411         struct i40e_vsi *vsi = pf->main_vsi;
2412         int ret;
2413
2414         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2415         if (ret != I40E_SUCCESS)
2416                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2417 }
2418
2419 static void
2420 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2421 {
2422         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2423         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424         struct i40e_vsi *vsi = pf->main_vsi;
2425         int ret;
2426
2427         if (dev->data->promiscuous == 1)
2428                 return; /* must remain in all_multicast mode */
2429
2430         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2431                                 vsi->seid, FALSE, NULL);
2432         if (ret != I40E_SUCCESS)
2433                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2434 }
2435
2436 /*
2437  * Set device link up.
2438  */
2439 static int
2440 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2441 {
2442         /* re-apply link speed setting */
2443         return i40e_apply_link_speed(dev);
2444 }
2445
2446 /*
2447  * Set device link down.
2448  */
2449 static int
2450 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2451 {
2452         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2453         uint8_t abilities = 0;
2454         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2455
2456         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2457         return i40e_phy_conf_link(hw, abilities, speed, false);
2458 }
2459
2460 static __rte_always_inline void
2461 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2462 {
2463 /* Link status registers and values*/
2464 #define I40E_PRTMAC_LINKSTA             0x001E2420
2465 #define I40E_REG_LINK_UP                0x40000080
2466 #define I40E_PRTMAC_MACC                0x001E24E0
2467 #define I40E_REG_MACC_25GB              0x00020000
2468 #define I40E_REG_SPEED_MASK             0x38000000
2469 #define I40E_REG_SPEED_100MB            0x00000000
2470 #define I40E_REG_SPEED_1GB              0x08000000
2471 #define I40E_REG_SPEED_10GB             0x10000000
2472 #define I40E_REG_SPEED_20GB             0x20000000
2473 #define I40E_REG_SPEED_25_40GB          0x18000000
2474         uint32_t link_speed;
2475         uint32_t reg_val;
2476
2477         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2478         link_speed = reg_val & I40E_REG_SPEED_MASK;
2479         reg_val &= I40E_REG_LINK_UP;
2480         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2481
2482         if (unlikely(link->link_status == 0))
2483                 return;
2484
2485         /* Parse the link status */
2486         switch (link_speed) {
2487         case I40E_REG_SPEED_100MB:
2488                 link->link_speed = ETH_SPEED_NUM_100M;
2489                 break;
2490         case I40E_REG_SPEED_1GB:
2491                 link->link_speed = ETH_SPEED_NUM_1G;
2492                 break;
2493         case I40E_REG_SPEED_10GB:
2494                 link->link_speed = ETH_SPEED_NUM_10G;
2495                 break;
2496         case I40E_REG_SPEED_20GB:
2497                 link->link_speed = ETH_SPEED_NUM_20G;
2498                 break;
2499         case I40E_REG_SPEED_25_40GB:
2500                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2501
2502                 if (reg_val & I40E_REG_MACC_25GB)
2503                         link->link_speed = ETH_SPEED_NUM_25G;
2504                 else
2505                         link->link_speed = ETH_SPEED_NUM_40G;
2506
2507                 break;
2508         default:
2509                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2510                 break;
2511         }
2512 }
2513
2514 static __rte_always_inline void
2515 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2516         bool enable_lse)
2517 {
2518 #define CHECK_INTERVAL             100  /* 100ms */
2519 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2520         uint32_t rep_cnt = MAX_REPEAT_TIME;
2521         struct i40e_link_status link_status;
2522         int status;
2523
2524         memset(&link_status, 0, sizeof(link_status));
2525
2526         do {
2527                 /* Get link status information from hardware */
2528                 status = i40e_aq_get_link_info(hw, enable_lse,
2529                                                 &link_status, NULL);
2530                 if (unlikely(status != I40E_SUCCESS)) {
2531                         link->link_speed = ETH_SPEED_NUM_100M;
2532                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2533                         PMD_DRV_LOG(ERR, "Failed to get link info");
2534                         return;
2535                 }
2536
2537                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2538                 if (unlikely(link->link_status != 0))
2539                         break;
2540
2541                 rte_delay_ms(CHECK_INTERVAL);
2542         } while (--rep_cnt);
2543
2544         /* Parse the link status */
2545         switch (link_status.link_speed) {
2546         case I40E_LINK_SPEED_100MB:
2547                 link->link_speed = ETH_SPEED_NUM_100M;
2548                 break;
2549         case I40E_LINK_SPEED_1GB:
2550                 link->link_speed = ETH_SPEED_NUM_1G;
2551                 break;
2552         case I40E_LINK_SPEED_10GB:
2553                 link->link_speed = ETH_SPEED_NUM_10G;
2554                 break;
2555         case I40E_LINK_SPEED_20GB:
2556                 link->link_speed = ETH_SPEED_NUM_20G;
2557                 break;
2558         case I40E_LINK_SPEED_25GB:
2559                 link->link_speed = ETH_SPEED_NUM_25G;
2560                 break;
2561         case I40E_LINK_SPEED_40GB:
2562                 link->link_speed = ETH_SPEED_NUM_40G;
2563                 break;
2564         default:
2565                 link->link_speed = ETH_SPEED_NUM_100M;
2566                 break;
2567         }
2568 }
2569
2570 int
2571 i40e_dev_link_update(struct rte_eth_dev *dev,
2572                      int wait_to_complete)
2573 {
2574         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575         struct rte_eth_link link, old;
2576         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2577
2578         memset(&link, 0, sizeof(link));
2579         memset(&old, 0, sizeof(old));
2580
2581         rte_i40e_dev_atomic_read_link_status(dev, &old);
2582
2583         /* i40e uses full duplex only */
2584         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2585         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2586                         ETH_LINK_SPEED_FIXED);
2587
2588         if (!wait_to_complete)
2589                 update_link_no_wait(hw, &link);
2590         else
2591                 update_link_wait(hw, &link, enable_lse);
2592
2593         rte_i40e_dev_atomic_write_link_status(dev, &link);
2594         if (link.link_status == old.link_status)
2595                 return -1;
2596
2597         i40e_notify_all_vfs_link_status(dev);
2598
2599         return 0;
2600 }
2601
2602 /* Get all the statistics of a VSI */
2603 void
2604 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2605 {
2606         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2607         struct i40e_eth_stats *nes = &vsi->eth_stats;
2608         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2609         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2610
2611         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2612                             vsi->offset_loaded, &oes->rx_bytes,
2613                             &nes->rx_bytes);
2614         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2615                             vsi->offset_loaded, &oes->rx_unicast,
2616                             &nes->rx_unicast);
2617         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2618                             vsi->offset_loaded, &oes->rx_multicast,
2619                             &nes->rx_multicast);
2620         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2621                             vsi->offset_loaded, &oes->rx_broadcast,
2622                             &nes->rx_broadcast);
2623         /* exclude CRC bytes */
2624         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2625                 nes->rx_broadcast) * ETHER_CRC_LEN;
2626
2627         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2628                             &oes->rx_discards, &nes->rx_discards);
2629         /* GLV_REPC not supported */
2630         /* GLV_RMPC not supported */
2631         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2632                             &oes->rx_unknown_protocol,
2633                             &nes->rx_unknown_protocol);
2634         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2635                             vsi->offset_loaded, &oes->tx_bytes,
2636                             &nes->tx_bytes);
2637         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2638                             vsi->offset_loaded, &oes->tx_unicast,
2639                             &nes->tx_unicast);
2640         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2641                             vsi->offset_loaded, &oes->tx_multicast,
2642                             &nes->tx_multicast);
2643         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2644                             vsi->offset_loaded,  &oes->tx_broadcast,
2645                             &nes->tx_broadcast);
2646         /* GLV_TDPC not supported */
2647         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2648                             &oes->tx_errors, &nes->tx_errors);
2649         vsi->offset_loaded = true;
2650
2651         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2652                     vsi->vsi_id);
2653         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2654         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2655         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2656         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2657         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2658         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2659                     nes->rx_unknown_protocol);
2660         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2661         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2662         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2663         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2664         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2665         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2666         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2667                     vsi->vsi_id);
2668 }
2669
2670 static void
2671 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2672 {
2673         unsigned int i;
2674         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2675         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2676
2677         /* Get rx/tx bytes of internal transfer packets */
2678         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2679                         I40E_GLV_GORCL(hw->port),
2680                         pf->offset_loaded,
2681                         &pf->internal_stats_offset.rx_bytes,
2682                         &pf->internal_stats.rx_bytes);
2683
2684         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2685                         I40E_GLV_GOTCL(hw->port),
2686                         pf->offset_loaded,
2687                         &pf->internal_stats_offset.tx_bytes,
2688                         &pf->internal_stats.tx_bytes);
2689         /* Get total internal rx packet count */
2690         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2691                             I40E_GLV_UPRCL(hw->port),
2692                             pf->offset_loaded,
2693                             &pf->internal_stats_offset.rx_unicast,
2694                             &pf->internal_stats.rx_unicast);
2695         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2696                             I40E_GLV_MPRCL(hw->port),
2697                             pf->offset_loaded,
2698                             &pf->internal_stats_offset.rx_multicast,
2699                             &pf->internal_stats.rx_multicast);
2700         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2701                             I40E_GLV_BPRCL(hw->port),
2702                             pf->offset_loaded,
2703                             &pf->internal_stats_offset.rx_broadcast,
2704                             &pf->internal_stats.rx_broadcast);
2705         /* Get total internal tx packet count */
2706         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2707                             I40E_GLV_UPTCL(hw->port),
2708                             pf->offset_loaded,
2709                             &pf->internal_stats_offset.tx_unicast,
2710                             &pf->internal_stats.tx_unicast);
2711         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2712                             I40E_GLV_MPTCL(hw->port),
2713                             pf->offset_loaded,
2714                             &pf->internal_stats_offset.tx_multicast,
2715                             &pf->internal_stats.tx_multicast);
2716         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2717                             I40E_GLV_BPTCL(hw->port),
2718                             pf->offset_loaded,
2719                             &pf->internal_stats_offset.tx_broadcast,
2720                             &pf->internal_stats.tx_broadcast);
2721
2722         /* exclude CRC size */
2723         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2724                 pf->internal_stats.rx_multicast +
2725                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2726
2727         /* Get statistics of struct i40e_eth_stats */
2728         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2729                             I40E_GLPRT_GORCL(hw->port),
2730                             pf->offset_loaded, &os->eth.rx_bytes,
2731                             &ns->eth.rx_bytes);
2732         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2733                             I40E_GLPRT_UPRCL(hw->port),
2734                             pf->offset_loaded, &os->eth.rx_unicast,
2735                             &ns->eth.rx_unicast);
2736         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2737                             I40E_GLPRT_MPRCL(hw->port),
2738                             pf->offset_loaded, &os->eth.rx_multicast,
2739                             &ns->eth.rx_multicast);
2740         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2741                             I40E_GLPRT_BPRCL(hw->port),
2742                             pf->offset_loaded, &os->eth.rx_broadcast,
2743                             &ns->eth.rx_broadcast);
2744         /* Workaround: CRC size should not be included in byte statistics,
2745          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2746          */
2747         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2748                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2749
2750         /* exclude internal rx bytes
2751          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2752          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2753          * value.
2754          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2755          */
2756         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2757                 ns->eth.rx_bytes = 0;
2758         else
2759                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2760
2761         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2762                 ns->eth.rx_unicast = 0;
2763         else
2764                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2765
2766         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2767                 ns->eth.rx_multicast = 0;
2768         else
2769                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2770
2771         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2772                 ns->eth.rx_broadcast = 0;
2773         else
2774                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2775
2776         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2777                             pf->offset_loaded, &os->eth.rx_discards,
2778                             &ns->eth.rx_discards);
2779         /* GLPRT_REPC not supported */
2780         /* GLPRT_RMPC not supported */
2781         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2782                             pf->offset_loaded,
2783                             &os->eth.rx_unknown_protocol,
2784                             &ns->eth.rx_unknown_protocol);
2785         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2786                             I40E_GLPRT_GOTCL(hw->port),
2787                             pf->offset_loaded, &os->eth.tx_bytes,
2788                             &ns->eth.tx_bytes);
2789         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2790                             I40E_GLPRT_UPTCL(hw->port),
2791                             pf->offset_loaded, &os->eth.tx_unicast,
2792                             &ns->eth.tx_unicast);
2793         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2794                             I40E_GLPRT_MPTCL(hw->port),
2795                             pf->offset_loaded, &os->eth.tx_multicast,
2796                             &ns->eth.tx_multicast);
2797         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2798                             I40E_GLPRT_BPTCL(hw->port),
2799                             pf->offset_loaded, &os->eth.tx_broadcast,
2800                             &ns->eth.tx_broadcast);
2801         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2802                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2803
2804         /* exclude internal tx bytes
2805          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2806          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2807          * value.
2808          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2809          */
2810         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2811                 ns->eth.tx_bytes = 0;
2812         else
2813                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2814
2815         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2816                 ns->eth.tx_unicast = 0;
2817         else
2818                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2819
2820         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2821                 ns->eth.tx_multicast = 0;
2822         else
2823                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2824
2825         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2826                 ns->eth.tx_broadcast = 0;
2827         else
2828                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2829
2830         /* GLPRT_TEPC not supported */
2831
2832         /* additional port specific stats */
2833         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2834                             pf->offset_loaded, &os->tx_dropped_link_down,
2835                             &ns->tx_dropped_link_down);
2836         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2837                             pf->offset_loaded, &os->crc_errors,
2838                             &ns->crc_errors);
2839         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2840                             pf->offset_loaded, &os->illegal_bytes,
2841                             &ns->illegal_bytes);
2842         /* GLPRT_ERRBC not supported */
2843         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2844                             pf->offset_loaded, &os->mac_local_faults,
2845                             &ns->mac_local_faults);
2846         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2847                             pf->offset_loaded, &os->mac_remote_faults,
2848                             &ns->mac_remote_faults);
2849         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2850                             pf->offset_loaded, &os->rx_length_errors,
2851                             &ns->rx_length_errors);
2852         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2853                             pf->offset_loaded, &os->link_xon_rx,
2854                             &ns->link_xon_rx);
2855         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2856                             pf->offset_loaded, &os->link_xoff_rx,
2857                             &ns->link_xoff_rx);
2858         for (i = 0; i < 8; i++) {
2859                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2860                                     pf->offset_loaded,
2861                                     &os->priority_xon_rx[i],
2862                                     &ns->priority_xon_rx[i]);
2863                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2864                                     pf->offset_loaded,
2865                                     &os->priority_xoff_rx[i],
2866                                     &ns->priority_xoff_rx[i]);
2867         }
2868         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2869                             pf->offset_loaded, &os->link_xon_tx,
2870                             &ns->link_xon_tx);
2871         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2872                             pf->offset_loaded, &os->link_xoff_tx,
2873                             &ns->link_xoff_tx);
2874         for (i = 0; i < 8; i++) {
2875                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2876                                     pf->offset_loaded,
2877                                     &os->priority_xon_tx[i],
2878                                     &ns->priority_xon_tx[i]);
2879                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2880                                     pf->offset_loaded,
2881                                     &os->priority_xoff_tx[i],
2882                                     &ns->priority_xoff_tx[i]);
2883                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2884                                     pf->offset_loaded,
2885                                     &os->priority_xon_2_xoff[i],
2886                                     &ns->priority_xon_2_xoff[i]);
2887         }
2888         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2889                             I40E_GLPRT_PRC64L(hw->port),
2890                             pf->offset_loaded, &os->rx_size_64,
2891                             &ns->rx_size_64);
2892         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2893                             I40E_GLPRT_PRC127L(hw->port),
2894                             pf->offset_loaded, &os->rx_size_127,
2895                             &ns->rx_size_127);
2896         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2897                             I40E_GLPRT_PRC255L(hw->port),
2898                             pf->offset_loaded, &os->rx_size_255,
2899                             &ns->rx_size_255);
2900         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2901                             I40E_GLPRT_PRC511L(hw->port),
2902                             pf->offset_loaded, &os->rx_size_511,
2903                             &ns->rx_size_511);
2904         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2905                             I40E_GLPRT_PRC1023L(hw->port),
2906                             pf->offset_loaded, &os->rx_size_1023,
2907                             &ns->rx_size_1023);
2908         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2909                             I40E_GLPRT_PRC1522L(hw->port),
2910                             pf->offset_loaded, &os->rx_size_1522,
2911                             &ns->rx_size_1522);
2912         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2913                             I40E_GLPRT_PRC9522L(hw->port),
2914                             pf->offset_loaded, &os->rx_size_big,
2915                             &ns->rx_size_big);
2916         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2917                             pf->offset_loaded, &os->rx_undersize,
2918                             &ns->rx_undersize);
2919         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2920                             pf->offset_loaded, &os->rx_fragments,
2921                             &ns->rx_fragments);
2922         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2923                             pf->offset_loaded, &os->rx_oversize,
2924                             &ns->rx_oversize);
2925         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2926                             pf->offset_loaded, &os->rx_jabber,
2927                             &ns->rx_jabber);
2928         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2929                             I40E_GLPRT_PTC64L(hw->port),
2930                             pf->offset_loaded, &os->tx_size_64,
2931                             &ns->tx_size_64);
2932         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2933                             I40E_GLPRT_PTC127L(hw->port),
2934                             pf->offset_loaded, &os->tx_size_127,
2935                             &ns->tx_size_127);
2936         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2937                             I40E_GLPRT_PTC255L(hw->port),
2938                             pf->offset_loaded, &os->tx_size_255,
2939                             &ns->tx_size_255);
2940         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2941                             I40E_GLPRT_PTC511L(hw->port),
2942                             pf->offset_loaded, &os->tx_size_511,
2943                             &ns->tx_size_511);
2944         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2945                             I40E_GLPRT_PTC1023L(hw->port),
2946                             pf->offset_loaded, &os->tx_size_1023,
2947                             &ns->tx_size_1023);
2948         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2949                             I40E_GLPRT_PTC1522L(hw->port),
2950                             pf->offset_loaded, &os->tx_size_1522,
2951                             &ns->tx_size_1522);
2952         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2953                             I40E_GLPRT_PTC9522L(hw->port),
2954                             pf->offset_loaded, &os->tx_size_big,
2955                             &ns->tx_size_big);
2956         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2957                            pf->offset_loaded,
2958                            &os->fd_sb_match, &ns->fd_sb_match);
2959         /* GLPRT_MSPDC not supported */
2960         /* GLPRT_XEC not supported */
2961
2962         pf->offset_loaded = true;
2963
2964         if (pf->main_vsi)
2965                 i40e_update_vsi_stats(pf->main_vsi);
2966 }
2967
2968 /* Get all statistics of a port */
2969 static int
2970 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2971 {
2972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2975         unsigned i;
2976
2977         /* call read registers - updates values, now write them to struct */
2978         i40e_read_stats_registers(pf, hw);
2979
2980         stats->ipackets = ns->eth.rx_unicast +
2981                         ns->eth.rx_multicast +
2982                         ns->eth.rx_broadcast -
2983                         ns->eth.rx_discards -
2984                         pf->main_vsi->eth_stats.rx_discards;
2985         stats->opackets = ns->eth.tx_unicast +
2986                         ns->eth.tx_multicast +
2987                         ns->eth.tx_broadcast;
2988         stats->ibytes   = ns->eth.rx_bytes;
2989         stats->obytes   = ns->eth.tx_bytes;
2990         stats->oerrors  = ns->eth.tx_errors +
2991                         pf->main_vsi->eth_stats.tx_errors;
2992
2993         /* Rx Errors */
2994         stats->imissed  = ns->eth.rx_discards +
2995                         pf->main_vsi->eth_stats.rx_discards;
2996         stats->ierrors  = ns->crc_errors +
2997                         ns->rx_length_errors + ns->rx_undersize +
2998                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2999
3000         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3001         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3002         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3003         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3004         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3005         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3006         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3007                     ns->eth.rx_unknown_protocol);
3008         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3009         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3010         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3011         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3012         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3013         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3014
3015         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3016                     ns->tx_dropped_link_down);
3017         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3018         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3019                     ns->illegal_bytes);
3020         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3021         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3022                     ns->mac_local_faults);
3023         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3024                     ns->mac_remote_faults);
3025         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3026                     ns->rx_length_errors);
3027         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3028         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3029         for (i = 0; i < 8; i++) {
3030                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3031                                 i, ns->priority_xon_rx[i]);
3032                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3033                                 i, ns->priority_xoff_rx[i]);
3034         }
3035         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3036         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3037         for (i = 0; i < 8; i++) {
3038                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3039                                 i, ns->priority_xon_tx[i]);
3040                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3041                                 i, ns->priority_xoff_tx[i]);
3042                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3043                                 i, ns->priority_xon_2_xoff[i]);
3044         }
3045         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3046         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3047         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3048         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3049         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3050         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3051         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3052         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3053         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3054         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3055         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3056         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3057         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3058         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3059         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3060         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3061         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3062         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3063         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3064                         ns->mac_short_packet_dropped);
3065         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3066                     ns->checksum_error);
3067         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3068         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3069         return 0;
3070 }
3071
3072 /* Reset the statistics */
3073 static void
3074 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3075 {
3076         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078
3079         /* Mark PF and VSI stats to update the offset, aka "reset" */
3080         pf->offset_loaded = false;
3081         if (pf->main_vsi)
3082                 pf->main_vsi->offset_loaded = false;
3083
3084         /* read the stats, reading current register values into offset */
3085         i40e_read_stats_registers(pf, hw);
3086 }
3087
3088 static uint32_t
3089 i40e_xstats_calc_num(void)
3090 {
3091         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3092                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3093                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3094 }
3095
3096 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3097                                      struct rte_eth_xstat_name *xstats_names,
3098                                      __rte_unused unsigned limit)
3099 {
3100         unsigned count = 0;
3101         unsigned i, prio;
3102
3103         if (xstats_names == NULL)
3104                 return i40e_xstats_calc_num();
3105
3106         /* Note: limit checked in rte_eth_xstats_names() */
3107
3108         /* Get stats from i40e_eth_stats struct */
3109         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3110                 snprintf(xstats_names[count].name,
3111                          sizeof(xstats_names[count].name),
3112                          "%s", rte_i40e_stats_strings[i].name);
3113                 count++;
3114         }
3115
3116         /* Get individiual stats from i40e_hw_port struct */
3117         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3118                 snprintf(xstats_names[count].name,
3119                         sizeof(xstats_names[count].name),
3120                          "%s", rte_i40e_hw_port_strings[i].name);
3121                 count++;
3122         }
3123
3124         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3125                 for (prio = 0; prio < 8; prio++) {
3126                         snprintf(xstats_names[count].name,
3127                                  sizeof(xstats_names[count].name),
3128                                  "rx_priority%u_%s", prio,
3129                                  rte_i40e_rxq_prio_strings[i].name);
3130                         count++;
3131                 }
3132         }
3133
3134         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3135                 for (prio = 0; prio < 8; prio++) {
3136                         snprintf(xstats_names[count].name,
3137                                  sizeof(xstats_names[count].name),
3138                                  "tx_priority%u_%s", prio,
3139                                  rte_i40e_txq_prio_strings[i].name);
3140                         count++;
3141                 }
3142         }
3143         return count;
3144 }
3145
3146 static int
3147 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3148                     unsigned n)
3149 {
3150         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3152         unsigned i, count, prio;
3153         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3154
3155         count = i40e_xstats_calc_num();
3156         if (n < count)
3157                 return count;
3158
3159         i40e_read_stats_registers(pf, hw);
3160
3161         if (xstats == NULL)
3162                 return 0;
3163
3164         count = 0;
3165
3166         /* Get stats from i40e_eth_stats struct */
3167         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3168                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3169                         rte_i40e_stats_strings[i].offset);
3170                 xstats[count].id = count;
3171                 count++;
3172         }
3173
3174         /* Get individiual stats from i40e_hw_port struct */
3175         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3176                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3177                         rte_i40e_hw_port_strings[i].offset);
3178                 xstats[count].id = count;
3179                 count++;
3180         }
3181
3182         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3183                 for (prio = 0; prio < 8; prio++) {
3184                         xstats[count].value =
3185                                 *(uint64_t *)(((char *)hw_stats) +
3186                                 rte_i40e_rxq_prio_strings[i].offset +
3187                                 (sizeof(uint64_t) * prio));
3188                         xstats[count].id = count;
3189                         count++;
3190                 }
3191         }
3192
3193         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3194                 for (prio = 0; prio < 8; prio++) {
3195                         xstats[count].value =
3196                                 *(uint64_t *)(((char *)hw_stats) +
3197                                 rte_i40e_txq_prio_strings[i].offset +
3198                                 (sizeof(uint64_t) * prio));
3199                         xstats[count].id = count;
3200                         count++;
3201                 }
3202         }
3203
3204         return count;
3205 }
3206
3207 static int
3208 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3209                                  __rte_unused uint16_t queue_id,
3210                                  __rte_unused uint8_t stat_idx,
3211                                  __rte_unused uint8_t is_rx)
3212 {
3213         PMD_INIT_FUNC_TRACE();
3214
3215         return -ENOSYS;
3216 }
3217
3218 static int
3219 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3220 {
3221         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3222         u32 full_ver;
3223         u8 ver, patch;
3224         u16 build;
3225         int ret;
3226
3227         full_ver = hw->nvm.oem_ver;
3228         ver = (u8)(full_ver >> 24);
3229         build = (u16)((full_ver >> 8) & 0xffff);
3230         patch = (u8)(full_ver & 0xff);
3231
3232         ret = snprintf(fw_version, fw_size,
3233                  "%d.%d%d 0x%08x %d.%d.%d",
3234                  ((hw->nvm.version >> 12) & 0xf),
3235                  ((hw->nvm.version >> 4) & 0xff),
3236                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3237                  ver, build, patch);
3238
3239         ret += 1; /* add the size of '\0' */
3240         if (fw_size < (u32)ret)
3241                 return ret;
3242         else
3243                 return 0;
3244 }
3245
3246 static void
3247 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3248 {
3249         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3250         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251         struct i40e_vsi *vsi = pf->main_vsi;
3252         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3253
3254         dev_info->pci_dev = pci_dev;
3255         dev_info->max_rx_queues = vsi->nb_qps;
3256         dev_info->max_tx_queues = vsi->nb_qps;
3257         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3258         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3259         dev_info->max_mac_addrs = vsi->max_macaddrs;
3260         dev_info->max_vfs = pci_dev->max_vfs;
3261         dev_info->rx_offload_capa =
3262                 DEV_RX_OFFLOAD_VLAN_STRIP |
3263                 DEV_RX_OFFLOAD_QINQ_STRIP |
3264                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3265                 DEV_RX_OFFLOAD_UDP_CKSUM |
3266                 DEV_RX_OFFLOAD_TCP_CKSUM;
3267         dev_info->tx_offload_capa =
3268                 DEV_TX_OFFLOAD_VLAN_INSERT |
3269                 DEV_TX_OFFLOAD_QINQ_INSERT |
3270                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3271                 DEV_TX_OFFLOAD_UDP_CKSUM |
3272                 DEV_TX_OFFLOAD_TCP_CKSUM |
3273                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3274                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3275                 DEV_TX_OFFLOAD_TCP_TSO |
3276                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3277                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3278                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3279                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3280         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3281                                                 sizeof(uint32_t);
3282         dev_info->reta_size = pf->hash_lut_size;
3283         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3284
3285         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3286                 .rx_thresh = {
3287                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3288                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3289                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3290                 },
3291                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3292                 .rx_drop_en = 0,
3293         };
3294
3295         dev_info->default_txconf = (struct rte_eth_txconf) {
3296                 .tx_thresh = {
3297                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3298                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3299                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3300                 },
3301                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3302                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3303                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3304                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3305         };
3306
3307         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3308                 .nb_max = I40E_MAX_RING_DESC,
3309                 .nb_min = I40E_MIN_RING_DESC,
3310                 .nb_align = I40E_ALIGN_RING_DESC,
3311         };
3312
3313         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3314                 .nb_max = I40E_MAX_RING_DESC,
3315                 .nb_min = I40E_MIN_RING_DESC,
3316                 .nb_align = I40E_ALIGN_RING_DESC,
3317                 .nb_seg_max = I40E_TX_MAX_SEG,
3318                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3319         };
3320
3321         if (pf->flags & I40E_FLAG_VMDQ) {
3322                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3323                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3324                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3325                                                 pf->max_nb_vmdq_vsi;
3326                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3327                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3328                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3329         }
3330
3331         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3332                 /* For XL710 */
3333                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3334         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3335                 /* For XXV710 */
3336                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3337         else
3338                 /* For X710 */
3339                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3340 }
3341
3342 static int
3343 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3344 {
3345         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3346         struct i40e_vsi *vsi = pf->main_vsi;
3347         PMD_INIT_FUNC_TRACE();
3348
3349         if (on)
3350                 return i40e_vsi_add_vlan(vsi, vlan_id);
3351         else
3352                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3353 }
3354
3355 static int
3356 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3357                                 enum rte_vlan_type vlan_type,
3358                                 uint16_t tpid, int qinq)
3359 {
3360         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361         uint64_t reg_r = 0;
3362         uint64_t reg_w = 0;
3363         uint16_t reg_id = 3;
3364         int ret;
3365
3366         if (qinq) {
3367                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3368                         reg_id = 2;
3369         }
3370
3371         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3372                                           &reg_r, NULL);
3373         if (ret != I40E_SUCCESS) {
3374                 PMD_DRV_LOG(ERR,
3375                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3376                            reg_id);
3377                 return -EIO;
3378         }
3379         PMD_DRV_LOG(DEBUG,
3380                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3381                     reg_id, reg_r);
3382
3383         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3384         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3385         if (reg_r == reg_w) {
3386                 PMD_DRV_LOG(DEBUG, "No need to write");
3387                 return 0;
3388         }
3389
3390         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3391                                            reg_w, NULL);
3392         if (ret != I40E_SUCCESS) {
3393                 PMD_DRV_LOG(ERR,
3394                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3395                             reg_id);
3396                 return -EIO;
3397         }
3398         PMD_DRV_LOG(DEBUG,
3399                     "Global register 0x%08x is changed with value 0x%08x",
3400                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3401
3402         return 0;
3403 }
3404
3405 static int
3406 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3407                    enum rte_vlan_type vlan_type,
3408                    uint16_t tpid)
3409 {
3410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3411         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3412         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3413         int ret = 0;
3414
3415         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3416              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3417             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3418                 PMD_DRV_LOG(ERR,
3419                             "Unsupported vlan type.");
3420                 return -EINVAL;
3421         }
3422
3423         if (pf->support_multi_driver) {
3424                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3425                 return -ENOTSUP;
3426         }
3427
3428         /* 802.1ad frames ability is added in NVM API 1.7*/
3429         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3430                 if (qinq) {
3431                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3432                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3433                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3434                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3435                 } else {
3436                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3437                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3438                 }
3439                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3440                 if (ret != I40E_SUCCESS) {
3441                         PMD_DRV_LOG(ERR,
3442                                     "Set switch config failed aq_err: %d",
3443                                     hw->aq.asq_last_status);
3444                         ret = -EIO;
3445                 }
3446         } else
3447                 /* If NVM API < 1.7, keep the register setting */
3448                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3449                                                       tpid, qinq);
3450         i40e_global_cfg_warning(I40E_WARNING_TPID);
3451
3452         return ret;
3453 }
3454
3455 static int
3456 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3457 {
3458         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3459         struct i40e_vsi *vsi = pf->main_vsi;
3460
3461         if (mask & ETH_VLAN_FILTER_MASK) {
3462                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3463                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3464                 else
3465                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3466         }
3467
3468         if (mask & ETH_VLAN_STRIP_MASK) {
3469                 /* Enable or disable VLAN stripping */
3470                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3471                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3472                 else
3473                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3474         }
3475
3476         if (mask & ETH_VLAN_EXTEND_MASK) {
3477                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3478                         i40e_vsi_config_double_vlan(vsi, TRUE);
3479                         /* Set global registers with default ethertype. */
3480                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3481                                            ETHER_TYPE_VLAN);
3482                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3483                                            ETHER_TYPE_VLAN);
3484                 }
3485                 else
3486                         i40e_vsi_config_double_vlan(vsi, FALSE);
3487         }
3488
3489         return 0;
3490 }
3491
3492 static void
3493 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3494                           __rte_unused uint16_t queue,
3495                           __rte_unused int on)
3496 {
3497         PMD_INIT_FUNC_TRACE();
3498 }
3499
3500 static int
3501 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3502 {
3503         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3504         struct i40e_vsi *vsi = pf->main_vsi;
3505         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3506         struct i40e_vsi_vlan_pvid_info info;
3507
3508         memset(&info, 0, sizeof(info));
3509         info.on = on;
3510         if (info.on)
3511                 info.config.pvid = pvid;
3512         else {
3513                 info.config.reject.tagged =
3514                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3515                 info.config.reject.untagged =
3516                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3517         }
3518
3519         return i40e_vsi_vlan_pvid_set(vsi, &info);
3520 }
3521
3522 static int
3523 i40e_dev_led_on(struct rte_eth_dev *dev)
3524 {
3525         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3526         uint32_t mode = i40e_led_get(hw);
3527
3528         if (mode == 0)
3529                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3530
3531         return 0;
3532 }
3533
3534 static int
3535 i40e_dev_led_off(struct rte_eth_dev *dev)
3536 {
3537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538         uint32_t mode = i40e_led_get(hw);
3539
3540         if (mode != 0)
3541                 i40e_led_set(hw, 0, false);
3542
3543         return 0;
3544 }
3545
3546 static int
3547 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3548 {
3549         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3551
3552         fc_conf->pause_time = pf->fc_conf.pause_time;
3553
3554         /* read out from register, in case they are modified by other port */
3555         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3556                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3557         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3558                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3559
3560         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3561         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3562
3563          /* Return current mode according to actual setting*/
3564         switch (hw->fc.current_mode) {
3565         case I40E_FC_FULL:
3566                 fc_conf->mode = RTE_FC_FULL;
3567                 break;
3568         case I40E_FC_TX_PAUSE:
3569                 fc_conf->mode = RTE_FC_TX_PAUSE;
3570                 break;
3571         case I40E_FC_RX_PAUSE:
3572                 fc_conf->mode = RTE_FC_RX_PAUSE;
3573                 break;
3574         case I40E_FC_NONE:
3575         default:
3576                 fc_conf->mode = RTE_FC_NONE;
3577         };
3578
3579         return 0;
3580 }
3581
3582 static int
3583 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3584 {
3585         uint32_t mflcn_reg, fctrl_reg, reg;
3586         uint32_t max_high_water;
3587         uint8_t i, aq_failure;
3588         int err;
3589         struct i40e_hw *hw;
3590         struct i40e_pf *pf;
3591         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3592                 [RTE_FC_NONE] = I40E_FC_NONE,
3593                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3594                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3595                 [RTE_FC_FULL] = I40E_FC_FULL
3596         };
3597
3598         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3599
3600         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3601         if ((fc_conf->high_water > max_high_water) ||
3602                         (fc_conf->high_water < fc_conf->low_water)) {
3603                 PMD_INIT_LOG(ERR,
3604                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3605                         max_high_water);
3606                 return -EINVAL;
3607         }
3608
3609         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3610         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3611         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3612
3613         pf->fc_conf.pause_time = fc_conf->pause_time;
3614         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3615         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3616
3617         PMD_INIT_FUNC_TRACE();
3618
3619         /* All the link flow control related enable/disable register
3620          * configuration is handle by the F/W
3621          */
3622         err = i40e_set_fc(hw, &aq_failure, true);
3623         if (err < 0)
3624                 return -ENOSYS;
3625
3626         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3627                 /* Configure flow control refresh threshold,
3628                  * the value for stat_tx_pause_refresh_timer[8]
3629                  * is used for global pause operation.
3630                  */
3631
3632                 I40E_WRITE_REG(hw,
3633                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3634                                pf->fc_conf.pause_time);
3635
3636                 /* configure the timer value included in transmitted pause
3637                  * frame,
3638                  * the value for stat_tx_pause_quanta[8] is used for global
3639                  * pause operation
3640                  */
3641                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3642                                pf->fc_conf.pause_time);
3643
3644                 fctrl_reg = I40E_READ_REG(hw,
3645                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3646
3647                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3648                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3649                 else
3650                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3651
3652                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3653                                fctrl_reg);
3654         } else {
3655                 /* Configure pause time (2 TCs per register) */
3656                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3657                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3658                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3659
3660                 /* Configure flow control refresh threshold value */
3661                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3662                                pf->fc_conf.pause_time / 2);
3663
3664                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3665
3666                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3667                  *depending on configuration
3668                  */
3669                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3670                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3671                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3672                 } else {
3673                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3674                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3675                 }
3676
3677                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3678         }
3679
3680         if (!pf->support_multi_driver) {
3681                 /* config water marker both based on the packets and bytes */
3682                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3683                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3684                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3685                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3686                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3687                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3688                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3689                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3690                                   << I40E_KILOSHIFT);
3691                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3692                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3693                                    << I40E_KILOSHIFT);
3694                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3695         } else {
3696                 PMD_DRV_LOG(ERR,
3697                             "Water marker configuration is not supported.");
3698         }
3699
3700         I40E_WRITE_FLUSH(hw);
3701
3702         return 0;
3703 }
3704
3705 static int
3706 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3707                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3708 {
3709         PMD_INIT_FUNC_TRACE();
3710
3711         return -ENOSYS;
3712 }
3713
3714 /* Add a MAC address, and update filters */
3715 static int
3716 i40e_macaddr_add(struct rte_eth_dev *dev,
3717                  struct ether_addr *mac_addr,
3718                  __rte_unused uint32_t index,
3719                  uint32_t pool)
3720 {
3721         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3722         struct i40e_mac_filter_info mac_filter;
3723         struct i40e_vsi *vsi;
3724         int ret;
3725
3726         /* If VMDQ not enabled or configured, return */
3727         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3728                           !pf->nb_cfg_vmdq_vsi)) {
3729                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3730                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3731                         pool);
3732                 return -ENOTSUP;
3733         }
3734
3735         if (pool > pf->nb_cfg_vmdq_vsi) {
3736                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3737                                 pool, pf->nb_cfg_vmdq_vsi);
3738                 return -EINVAL;
3739         }
3740
3741         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3742         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3743                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3744         else
3745                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3746
3747         if (pool == 0)
3748                 vsi = pf->main_vsi;
3749         else
3750                 vsi = pf->vmdq[pool - 1].vsi;
3751
3752         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3753         if (ret != I40E_SUCCESS) {
3754                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3755                 return -ENODEV;
3756         }
3757         return 0;
3758 }
3759
3760 /* Remove a MAC address, and update filters */
3761 static void
3762 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3763 {
3764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3765         struct i40e_vsi *vsi;
3766         struct rte_eth_dev_data *data = dev->data;
3767         struct ether_addr *macaddr;
3768         int ret;
3769         uint32_t i;
3770         uint64_t pool_sel;
3771
3772         macaddr = &(data->mac_addrs[index]);
3773
3774         pool_sel = dev->data->mac_pool_sel[index];
3775
3776         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3777                 if (pool_sel & (1ULL << i)) {
3778                         if (i == 0)
3779                                 vsi = pf->main_vsi;
3780                         else {
3781                                 /* No VMDQ pool enabled or configured */
3782                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3783                                         (i > pf->nb_cfg_vmdq_vsi)) {
3784                                         PMD_DRV_LOG(ERR,
3785                                                 "No VMDQ pool enabled/configured");
3786                                         return;
3787                                 }
3788                                 vsi = pf->vmdq[i - 1].vsi;
3789                         }
3790                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3791
3792                         if (ret) {
3793                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3794                                 return;
3795                         }
3796                 }
3797         }
3798 }
3799
3800 /* Set perfect match or hash match of MAC and VLAN for a VF */
3801 static int
3802 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3803                  struct rte_eth_mac_filter *filter,
3804                  bool add)
3805 {
3806         struct i40e_hw *hw;
3807         struct i40e_mac_filter_info mac_filter;
3808         struct ether_addr old_mac;
3809         struct ether_addr *new_mac;
3810         struct i40e_pf_vf *vf = NULL;
3811         uint16_t vf_id;
3812         int ret;
3813
3814         if (pf == NULL) {
3815                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3816                 return -EINVAL;
3817         }
3818         hw = I40E_PF_TO_HW(pf);
3819
3820         if (filter == NULL) {
3821                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3822                 return -EINVAL;
3823         }
3824
3825         new_mac = &filter->mac_addr;
3826
3827         if (is_zero_ether_addr(new_mac)) {
3828                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3829                 return -EINVAL;
3830         }
3831
3832         vf_id = filter->dst_id;
3833
3834         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3835                 PMD_DRV_LOG(ERR, "Invalid argument.");
3836                 return -EINVAL;
3837         }
3838         vf = &pf->vfs[vf_id];
3839
3840         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3841                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3842                 return -EINVAL;
3843         }
3844
3845         if (add) {
3846                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3847                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3848                                 ETHER_ADDR_LEN);
3849                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3850                                  ETHER_ADDR_LEN);
3851
3852                 mac_filter.filter_type = filter->filter_type;
3853                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3854                 if (ret != I40E_SUCCESS) {
3855                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3856                         return -1;
3857                 }
3858                 ether_addr_copy(new_mac, &pf->dev_addr);
3859         } else {
3860                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3861                                 ETHER_ADDR_LEN);
3862                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3863                 if (ret != I40E_SUCCESS) {
3864                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3865                         return -1;
3866                 }
3867
3868                 /* Clear device address as it has been removed */
3869                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3870                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3871         }
3872
3873         return 0;
3874 }
3875
3876 /* MAC filter handle */
3877 static int
3878 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3879                 void *arg)
3880 {
3881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3882         struct rte_eth_mac_filter *filter;
3883         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3884         int ret = I40E_NOT_SUPPORTED;
3885
3886         filter = (struct rte_eth_mac_filter *)(arg);
3887
3888         switch (filter_op) {
3889         case RTE_ETH_FILTER_NOP:
3890                 ret = I40E_SUCCESS;
3891                 break;
3892         case RTE_ETH_FILTER_ADD:
3893                 i40e_pf_disable_irq0(hw);
3894                 if (filter->is_vf)
3895                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3896                 i40e_pf_enable_irq0(hw);
3897                 break;
3898         case RTE_ETH_FILTER_DELETE:
3899                 i40e_pf_disable_irq0(hw);
3900                 if (filter->is_vf)
3901                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3902                 i40e_pf_enable_irq0(hw);
3903                 break;
3904         default:
3905                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3906                 ret = I40E_ERR_PARAM;
3907                 break;
3908         }
3909
3910         return ret;
3911 }
3912
3913 static int
3914 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3915 {
3916         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3917         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3918         int ret;
3919
3920         if (!lut)
3921                 return -EINVAL;
3922
3923         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3924                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3925                                           lut, lut_size);
3926                 if (ret) {
3927                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3928                         return ret;
3929                 }
3930         } else {
3931                 uint32_t *lut_dw = (uint32_t *)lut;
3932                 uint16_t i, lut_size_dw = lut_size / 4;
3933
3934                 for (i = 0; i < lut_size_dw; i++)
3935                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3936         }
3937
3938         return 0;
3939 }
3940
3941 static int
3942 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3943 {
3944         struct i40e_pf *pf;
3945         struct i40e_hw *hw;
3946         int ret;
3947
3948         if (!vsi || !lut)
3949                 return -EINVAL;
3950
3951         pf = I40E_VSI_TO_PF(vsi);
3952         hw = I40E_VSI_TO_HW(vsi);
3953
3954         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3955                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3956                                           lut, lut_size);
3957                 if (ret) {
3958                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3959                         return ret;
3960                 }
3961         } else {
3962                 uint32_t *lut_dw = (uint32_t *)lut;
3963                 uint16_t i, lut_size_dw = lut_size / 4;
3964
3965                 for (i = 0; i < lut_size_dw; i++)
3966                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3967                 I40E_WRITE_FLUSH(hw);
3968         }
3969
3970         return 0;
3971 }
3972
3973 static int
3974 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3975                          struct rte_eth_rss_reta_entry64 *reta_conf,
3976                          uint16_t reta_size)
3977 {
3978         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3979         uint16_t i, lut_size = pf->hash_lut_size;
3980         uint16_t idx, shift;
3981         uint8_t *lut;
3982         int ret;
3983
3984         if (reta_size != lut_size ||
3985                 reta_size > ETH_RSS_RETA_SIZE_512) {
3986                 PMD_DRV_LOG(ERR,
3987                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3988                         reta_size, lut_size);
3989                 return -EINVAL;
3990         }
3991
3992         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3993         if (!lut) {
3994                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3995                 return -ENOMEM;
3996         }
3997         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3998         if (ret)
3999                 goto out;
4000         for (i = 0; i < reta_size; i++) {
4001                 idx = i / RTE_RETA_GROUP_SIZE;
4002                 shift = i % RTE_RETA_GROUP_SIZE;
4003                 if (reta_conf[idx].mask & (1ULL << shift))
4004                         lut[i] = reta_conf[idx].reta[shift];
4005         }
4006         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4007
4008 out:
4009         rte_free(lut);
4010
4011         return ret;
4012 }
4013
4014 static int
4015 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4016                         struct rte_eth_rss_reta_entry64 *reta_conf,
4017                         uint16_t reta_size)
4018 {
4019         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4020         uint16_t i, lut_size = pf->hash_lut_size;
4021         uint16_t idx, shift;
4022         uint8_t *lut;
4023         int ret;
4024
4025         if (reta_size != lut_size ||
4026                 reta_size > ETH_RSS_RETA_SIZE_512) {
4027                 PMD_DRV_LOG(ERR,
4028                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4029                         reta_size, lut_size);
4030                 return -EINVAL;
4031         }
4032
4033         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4034         if (!lut) {
4035                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4036                 return -ENOMEM;
4037         }
4038
4039         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4040         if (ret)
4041                 goto out;
4042         for (i = 0; i < reta_size; i++) {
4043                 idx = i / RTE_RETA_GROUP_SIZE;
4044                 shift = i % RTE_RETA_GROUP_SIZE;
4045                 if (reta_conf[idx].mask & (1ULL << shift))
4046                         reta_conf[idx].reta[shift] = lut[i];
4047         }
4048
4049 out:
4050         rte_free(lut);
4051
4052         return ret;
4053 }
4054
4055 /**
4056  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4057  * @hw:   pointer to the HW structure
4058  * @mem:  pointer to mem struct to fill out
4059  * @size: size of memory requested
4060  * @alignment: what to align the allocation to
4061  **/
4062 enum i40e_status_code
4063 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4064                         struct i40e_dma_mem *mem,
4065                         u64 size,
4066                         u32 alignment)
4067 {
4068         const struct rte_memzone *mz = NULL;
4069         char z_name[RTE_MEMZONE_NAMESIZE];
4070
4071         if (!mem)
4072                 return I40E_ERR_PARAM;
4073
4074         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4075         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
4076                                          alignment, RTE_PGSIZE_2M);
4077         if (!mz)
4078                 return I40E_ERR_NO_MEMORY;
4079
4080         mem->size = size;
4081         mem->va = mz->addr;
4082         mem->pa = mz->iova;
4083         mem->zone = (const void *)mz;
4084         PMD_DRV_LOG(DEBUG,
4085                 "memzone %s allocated with physical address: %"PRIu64,
4086                 mz->name, mem->pa);
4087
4088         return I40E_SUCCESS;
4089 }
4090
4091 /**
4092  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4093  * @hw:   pointer to the HW structure
4094  * @mem:  ptr to mem struct to free
4095  **/
4096 enum i40e_status_code
4097 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4098                     struct i40e_dma_mem *mem)
4099 {
4100         if (!mem)
4101                 return I40E_ERR_PARAM;
4102
4103         PMD_DRV_LOG(DEBUG,
4104                 "memzone %s to be freed with physical address: %"PRIu64,
4105                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4106         rte_memzone_free((const struct rte_memzone *)mem->zone);
4107         mem->zone = NULL;
4108         mem->va = NULL;
4109         mem->pa = (u64)0;
4110
4111         return I40E_SUCCESS;
4112 }
4113
4114 /**
4115  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4116  * @hw:   pointer to the HW structure
4117  * @mem:  pointer to mem struct to fill out
4118  * @size: size of memory requested
4119  **/
4120 enum i40e_status_code
4121 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4122                          struct i40e_virt_mem *mem,
4123                          u32 size)
4124 {
4125         if (!mem)
4126                 return I40E_ERR_PARAM;
4127
4128         mem->size = size;
4129         mem->va = rte_zmalloc("i40e", size, 0);
4130
4131         if (mem->va)
4132                 return I40E_SUCCESS;
4133         else
4134                 return I40E_ERR_NO_MEMORY;
4135 }
4136
4137 /**
4138  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4139  * @hw:   pointer to the HW structure
4140  * @mem:  pointer to mem struct to free
4141  **/
4142 enum i40e_status_code
4143 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4144                      struct i40e_virt_mem *mem)
4145 {
4146         if (!mem)
4147                 return I40E_ERR_PARAM;
4148
4149         rte_free(mem->va);
4150         mem->va = NULL;
4151
4152         return I40E_SUCCESS;
4153 }
4154
4155 void
4156 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4157 {
4158         rte_spinlock_init(&sp->spinlock);
4159 }
4160
4161 void
4162 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4163 {
4164         rte_spinlock_lock(&sp->spinlock);
4165 }
4166
4167 void
4168 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4169 {
4170         rte_spinlock_unlock(&sp->spinlock);
4171 }
4172
4173 void
4174 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4175 {
4176         return;
4177 }
4178
4179 /**
4180  * Get the hardware capabilities, which will be parsed
4181  * and saved into struct i40e_hw.
4182  */
4183 static int
4184 i40e_get_cap(struct i40e_hw *hw)
4185 {
4186         struct i40e_aqc_list_capabilities_element_resp *buf;
4187         uint16_t len, size = 0;
4188         int ret;
4189
4190         /* Calculate a huge enough buff for saving response data temporarily */
4191         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4192                                                 I40E_MAX_CAP_ELE_NUM;
4193         buf = rte_zmalloc("i40e", len, 0);
4194         if (!buf) {
4195                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4196                 return I40E_ERR_NO_MEMORY;
4197         }
4198
4199         /* Get, parse the capabilities and save it to hw */
4200         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4201                         i40e_aqc_opc_list_func_capabilities, NULL);
4202         if (ret != I40E_SUCCESS)
4203                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4204
4205         /* Free the temporary buffer after being used */
4206         rte_free(buf);
4207
4208         return ret;
4209 }
4210
4211 static int
4212 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4213 {
4214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4215         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4216         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4217         uint16_t qp_count = 0, vsi_count = 0;
4218
4219         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4220                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4221                 return -EINVAL;
4222         }
4223         /* Add the parameter init for LFC */
4224         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4225         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4226         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4227
4228         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4229         pf->max_num_vsi = hw->func_caps.num_vsis;
4230         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4231         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4232         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4233
4234         /* FDir queue/VSI allocation */
4235         pf->fdir_qp_offset = 0;
4236         if (hw->func_caps.fd) {
4237                 pf->flags |= I40E_FLAG_FDIR;
4238                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4239         } else {
4240                 pf->fdir_nb_qps = 0;
4241         }
4242         qp_count += pf->fdir_nb_qps;
4243         vsi_count += 1;
4244
4245         /* LAN queue/VSI allocation */
4246         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4247         if (!hw->func_caps.rss) {
4248                 pf->lan_nb_qps = 1;
4249         } else {
4250                 pf->flags |= I40E_FLAG_RSS;
4251                 if (hw->mac.type == I40E_MAC_X722)
4252                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4253                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4254         }
4255         qp_count += pf->lan_nb_qps;
4256         vsi_count += 1;
4257
4258         /* VF queue/VSI allocation */
4259         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4260         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4261                 pf->flags |= I40E_FLAG_SRIOV;
4262                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4263                 pf->vf_num = pci_dev->max_vfs;
4264                 PMD_DRV_LOG(DEBUG,
4265                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4266                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4267         } else {
4268                 pf->vf_nb_qps = 0;
4269                 pf->vf_num = 0;
4270         }
4271         qp_count += pf->vf_nb_qps * pf->vf_num;
4272         vsi_count += pf->vf_num;
4273
4274         /* VMDq queue/VSI allocation */
4275         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4276         pf->vmdq_nb_qps = 0;
4277         pf->max_nb_vmdq_vsi = 0;
4278         if (hw->func_caps.vmdq) {
4279                 if (qp_count < hw->func_caps.num_tx_qp &&
4280                         vsi_count < hw->func_caps.num_vsis) {
4281                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4282                                 qp_count) / pf->vmdq_nb_qp_max;
4283
4284                         /* Limit the maximum number of VMDq vsi to the maximum
4285                          * ethdev can support
4286                          */
4287                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4288                                 hw->func_caps.num_vsis - vsi_count);
4289                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4290                                 ETH_64_POOLS);
4291                         if (pf->max_nb_vmdq_vsi) {
4292                                 pf->flags |= I40E_FLAG_VMDQ;
4293                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4294                                 PMD_DRV_LOG(DEBUG,
4295                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4296                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4297                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4298                         } else {
4299                                 PMD_DRV_LOG(INFO,
4300                                         "No enough queues left for VMDq");
4301                         }
4302                 } else {
4303                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4304                 }
4305         }
4306         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4307         vsi_count += pf->max_nb_vmdq_vsi;
4308
4309         if (hw->func_caps.dcb)
4310                 pf->flags |= I40E_FLAG_DCB;
4311
4312         if (qp_count > hw->func_caps.num_tx_qp) {
4313                 PMD_DRV_LOG(ERR,
4314                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4315                         qp_count, hw->func_caps.num_tx_qp);
4316                 return -EINVAL;
4317         }
4318         if (vsi_count > hw->func_caps.num_vsis) {
4319                 PMD_DRV_LOG(ERR,
4320                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4321                         vsi_count, hw->func_caps.num_vsis);
4322                 return -EINVAL;
4323         }
4324
4325         return 0;
4326 }
4327
4328 static int
4329 i40e_pf_get_switch_config(struct i40e_pf *pf)
4330 {
4331         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4332         struct i40e_aqc_get_switch_config_resp *switch_config;
4333         struct i40e_aqc_switch_config_element_resp *element;
4334         uint16_t start_seid = 0, num_reported;
4335         int ret;
4336
4337         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4338                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4339         if (!switch_config) {
4340                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4341                 return -ENOMEM;
4342         }
4343
4344         /* Get the switch configurations */
4345         ret = i40e_aq_get_switch_config(hw, switch_config,
4346                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4347         if (ret != I40E_SUCCESS) {
4348                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4349                 goto fail;
4350         }
4351         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4352         if (num_reported != 1) { /* The number should be 1 */
4353                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4354                 goto fail;
4355         }
4356
4357         /* Parse the switch configuration elements */
4358         element = &(switch_config->element[0]);
4359         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4360                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4361                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4362         } else
4363                 PMD_DRV_LOG(INFO, "Unknown element type");
4364
4365 fail:
4366         rte_free(switch_config);
4367
4368         return ret;
4369 }
4370
4371 static int
4372 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4373                         uint32_t num)
4374 {
4375         struct pool_entry *entry;
4376
4377         if (pool == NULL || num == 0)
4378                 return -EINVAL;
4379
4380         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4381         if (entry == NULL) {
4382                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4383                 return -ENOMEM;
4384         }
4385
4386         /* queue heap initialize */
4387         pool->num_free = num;
4388         pool->num_alloc = 0;
4389         pool->base = base;
4390         LIST_INIT(&pool->alloc_list);
4391         LIST_INIT(&pool->free_list);
4392
4393         /* Initialize element  */
4394         entry->base = 0;
4395         entry->len = num;
4396
4397         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4398         return 0;
4399 }
4400
4401 static void
4402 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4403 {
4404         struct pool_entry *entry, *next_entry;
4405
4406         if (pool == NULL)
4407                 return;
4408
4409         for (entry = LIST_FIRST(&pool->alloc_list);
4410                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4411                         entry = next_entry) {
4412                 LIST_REMOVE(entry, next);
4413                 rte_free(entry);
4414         }
4415
4416         for (entry = LIST_FIRST(&pool->free_list);
4417                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4418                         entry = next_entry) {
4419                 LIST_REMOVE(entry, next);
4420                 rte_free(entry);
4421         }
4422
4423         pool->num_free = 0;
4424         pool->num_alloc = 0;
4425         pool->base = 0;
4426         LIST_INIT(&pool->alloc_list);
4427         LIST_INIT(&pool->free_list);
4428 }
4429
4430 static int
4431 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4432                        uint32_t base)
4433 {
4434         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4435         uint32_t pool_offset;
4436         int insert;
4437
4438         if (pool == NULL) {
4439                 PMD_DRV_LOG(ERR, "Invalid parameter");
4440                 return -EINVAL;
4441         }
4442
4443         pool_offset = base - pool->base;
4444         /* Lookup in alloc list */
4445         LIST_FOREACH(entry, &pool->alloc_list, next) {
4446                 if (entry->base == pool_offset) {
4447                         valid_entry = entry;
4448                         LIST_REMOVE(entry, next);
4449                         break;
4450                 }
4451         }
4452
4453         /* Not find, return */
4454         if (valid_entry == NULL) {
4455                 PMD_DRV_LOG(ERR, "Failed to find entry");
4456                 return -EINVAL;
4457         }
4458
4459         /**
4460          * Found it, move it to free list  and try to merge.
4461          * In order to make merge easier, always sort it by qbase.
4462          * Find adjacent prev and last entries.
4463          */
4464         prev = next = NULL;
4465         LIST_FOREACH(entry, &pool->free_list, next) {
4466                 if (entry->base > valid_entry->base) {
4467                         next = entry;
4468                         break;
4469                 }
4470                 prev = entry;
4471         }
4472
4473         insert = 0;
4474         /* Try to merge with next one*/
4475         if (next != NULL) {
4476                 /* Merge with next one */
4477                 if (valid_entry->base + valid_entry->len == next->base) {
4478                         next->base = valid_entry->base;
4479                         next->len += valid_entry->len;
4480                         rte_free(valid_entry);
4481                         valid_entry = next;
4482                         insert = 1;
4483                 }
4484         }
4485
4486         if (prev != NULL) {
4487                 /* Merge with previous one */
4488                 if (prev->base + prev->len == valid_entry->base) {
4489                         prev->len += valid_entry->len;
4490                         /* If it merge with next one, remove next node */
4491                         if (insert == 1) {
4492                                 LIST_REMOVE(valid_entry, next);
4493                                 rte_free(valid_entry);
4494                         } else {
4495                                 rte_free(valid_entry);
4496                                 insert = 1;
4497                         }
4498                 }
4499         }
4500
4501         /* Not find any entry to merge, insert */
4502         if (insert == 0) {
4503                 if (prev != NULL)
4504                         LIST_INSERT_AFTER(prev, valid_entry, next);
4505                 else if (next != NULL)
4506                         LIST_INSERT_BEFORE(next, valid_entry, next);
4507                 else /* It's empty list, insert to head */
4508                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4509         }
4510
4511         pool->num_free += valid_entry->len;
4512         pool->num_alloc -= valid_entry->len;
4513
4514         return 0;
4515 }
4516
4517 static int
4518 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4519                        uint16_t num)
4520 {
4521         struct pool_entry *entry, *valid_entry;
4522
4523         if (pool == NULL || num == 0) {
4524                 PMD_DRV_LOG(ERR, "Invalid parameter");
4525                 return -EINVAL;
4526         }
4527
4528         if (pool->num_free < num) {
4529                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4530                             num, pool->num_free);
4531                 return -ENOMEM;
4532         }
4533
4534         valid_entry = NULL;
4535         /* Lookup  in free list and find most fit one */
4536         LIST_FOREACH(entry, &pool->free_list, next) {
4537                 if (entry->len >= num) {
4538                         /* Find best one */
4539                         if (entry->len == num) {
4540                                 valid_entry = entry;
4541                                 break;
4542                         }
4543                         if (valid_entry == NULL || valid_entry->len > entry->len)
4544                                 valid_entry = entry;
4545                 }
4546         }
4547
4548         /* Not find one to satisfy the request, return */
4549         if (valid_entry == NULL) {
4550                 PMD_DRV_LOG(ERR, "No valid entry found");
4551                 return -ENOMEM;
4552         }
4553         /**
4554          * The entry have equal queue number as requested,
4555          * remove it from alloc_list.
4556          */
4557         if (valid_entry->len == num) {
4558                 LIST_REMOVE(valid_entry, next);
4559         } else {
4560                 /**
4561                  * The entry have more numbers than requested,
4562                  * create a new entry for alloc_list and minus its
4563                  * queue base and number in free_list.
4564                  */
4565                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4566                 if (entry == NULL) {
4567                         PMD_DRV_LOG(ERR,
4568                                 "Failed to allocate memory for resource pool");
4569                         return -ENOMEM;
4570                 }
4571                 entry->base = valid_entry->base;
4572                 entry->len = num;
4573                 valid_entry->base += num;
4574                 valid_entry->len -= num;
4575                 valid_entry = entry;
4576         }
4577
4578         /* Insert it into alloc list, not sorted */
4579         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4580
4581         pool->num_free -= valid_entry->len;
4582         pool->num_alloc += valid_entry->len;
4583
4584         return valid_entry->base + pool->base;
4585 }
4586
4587 /**
4588  * bitmap_is_subset - Check whether src2 is subset of src1
4589  **/
4590 static inline int
4591 bitmap_is_subset(uint8_t src1, uint8_t src2)
4592 {
4593         return !((src1 ^ src2) & src2);
4594 }
4595
4596 static enum i40e_status_code
4597 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4598 {
4599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4600
4601         /* If DCB is not supported, only default TC is supported */
4602         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4603                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4604                 return I40E_NOT_SUPPORTED;
4605         }
4606
4607         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4608                 PMD_DRV_LOG(ERR,
4609                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4610                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4611                 return I40E_NOT_SUPPORTED;
4612         }
4613         return I40E_SUCCESS;
4614 }
4615
4616 int
4617 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4618                                 struct i40e_vsi_vlan_pvid_info *info)
4619 {
4620         struct i40e_hw *hw;
4621         struct i40e_vsi_context ctxt;
4622         uint8_t vlan_flags = 0;
4623         int ret;
4624
4625         if (vsi == NULL || info == NULL) {
4626                 PMD_DRV_LOG(ERR, "invalid parameters");
4627                 return I40E_ERR_PARAM;
4628         }
4629
4630         if (info->on) {
4631                 vsi->info.pvid = info->config.pvid;
4632                 /**
4633                  * If insert pvid is enabled, only tagged pkts are
4634                  * allowed to be sent out.
4635                  */
4636                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4637                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4638         } else {
4639                 vsi->info.pvid = 0;
4640                 if (info->config.reject.tagged == 0)
4641                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4642
4643                 if (info->config.reject.untagged == 0)
4644                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4645         }
4646         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4647                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4648         vsi->info.port_vlan_flags |= vlan_flags;
4649         vsi->info.valid_sections =
4650                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4651         memset(&ctxt, 0, sizeof(ctxt));
4652         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4653         ctxt.seid = vsi->seid;
4654
4655         hw = I40E_VSI_TO_HW(vsi);
4656         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4657         if (ret != I40E_SUCCESS)
4658                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4659
4660         return ret;
4661 }
4662
4663 static int
4664 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4665 {
4666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4667         int i, ret;
4668         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4669
4670         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4671         if (ret != I40E_SUCCESS)
4672                 return ret;
4673
4674         if (!vsi->seid) {
4675                 PMD_DRV_LOG(ERR, "seid not valid");
4676                 return -EINVAL;
4677         }
4678
4679         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4680         tc_bw_data.tc_valid_bits = enabled_tcmap;
4681         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4682                 tc_bw_data.tc_bw_credits[i] =
4683                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4684
4685         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4686         if (ret != I40E_SUCCESS) {
4687                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4688                 return ret;
4689         }
4690
4691         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4692                                         sizeof(vsi->info.qs_handle));
4693         return I40E_SUCCESS;
4694 }
4695
4696 static enum i40e_status_code
4697 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4698                                  struct i40e_aqc_vsi_properties_data *info,
4699                                  uint8_t enabled_tcmap)
4700 {
4701         enum i40e_status_code ret;
4702         int i, total_tc = 0;
4703         uint16_t qpnum_per_tc, bsf, qp_idx;
4704
4705         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4706         if (ret != I40E_SUCCESS)
4707                 return ret;
4708
4709         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4710                 if (enabled_tcmap & (1 << i))
4711                         total_tc++;
4712         if (total_tc == 0)
4713                 total_tc = 1;
4714         vsi->enabled_tc = enabled_tcmap;
4715
4716         /* Number of queues per enabled TC */
4717         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4718         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4719         bsf = rte_bsf32(qpnum_per_tc);
4720
4721         /* Adjust the queue number to actual queues that can be applied */
4722         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4723                 vsi->nb_qps = qpnum_per_tc * total_tc;
4724
4725         /**
4726          * Configure TC and queue mapping parameters, for enabled TC,
4727          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4728          * default queue will serve it.
4729          */
4730         qp_idx = 0;
4731         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4732                 if (vsi->enabled_tc & (1 << i)) {
4733                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4734                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4735                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4736                         qp_idx += qpnum_per_tc;
4737                 } else
4738                         info->tc_mapping[i] = 0;
4739         }
4740
4741         /* Associate queue number with VSI */
4742         if (vsi->type == I40E_VSI_SRIOV) {
4743                 info->mapping_flags |=
4744                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4745                 for (i = 0; i < vsi->nb_qps; i++)
4746                         info->queue_mapping[i] =
4747                                 rte_cpu_to_le_16(vsi->base_queue + i);
4748         } else {
4749                 info->mapping_flags |=
4750                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4751                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4752         }
4753         info->valid_sections |=
4754                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4755
4756         return I40E_SUCCESS;
4757 }
4758
4759 static int
4760 i40e_veb_release(struct i40e_veb *veb)
4761 {
4762         struct i40e_vsi *vsi;
4763         struct i40e_hw *hw;
4764
4765         if (veb == NULL)
4766                 return -EINVAL;
4767
4768         if (!TAILQ_EMPTY(&veb->head)) {
4769                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4770                 return -EACCES;
4771         }
4772         /* associate_vsi field is NULL for floating VEB */
4773         if (veb->associate_vsi != NULL) {
4774                 vsi = veb->associate_vsi;
4775                 hw = I40E_VSI_TO_HW(vsi);
4776
4777                 vsi->uplink_seid = veb->uplink_seid;
4778                 vsi->veb = NULL;
4779         } else {
4780                 veb->associate_pf->main_vsi->floating_veb = NULL;
4781                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4782         }
4783
4784         i40e_aq_delete_element(hw, veb->seid, NULL);
4785         rte_free(veb);
4786         return I40E_SUCCESS;
4787 }
4788
4789 /* Setup a veb */
4790 static struct i40e_veb *
4791 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4792 {
4793         struct i40e_veb *veb;
4794         int ret;
4795         struct i40e_hw *hw;
4796
4797         if (pf == NULL) {
4798                 PMD_DRV_LOG(ERR,
4799                             "veb setup failed, associated PF shouldn't null");
4800                 return NULL;
4801         }
4802         hw = I40E_PF_TO_HW(pf);
4803
4804         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4805         if (!veb) {
4806                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4807                 goto fail;
4808         }
4809
4810         veb->associate_vsi = vsi;
4811         veb->associate_pf = pf;
4812         TAILQ_INIT(&veb->head);
4813         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4814
4815         /* create floating veb if vsi is NULL */
4816         if (vsi != NULL) {
4817                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4818                                       I40E_DEFAULT_TCMAP, false,
4819                                       &veb->seid, false, NULL);
4820         } else {
4821                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4822                                       true, &veb->seid, false, NULL);
4823         }
4824
4825         if (ret != I40E_SUCCESS) {
4826                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4827                             hw->aq.asq_last_status);
4828                 goto fail;
4829         }
4830         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4831
4832         /* get statistics index */
4833         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4834                                 &veb->stats_idx, NULL, NULL, NULL);
4835         if (ret != I40E_SUCCESS) {
4836                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4837                             hw->aq.asq_last_status);
4838                 goto fail;
4839         }
4840         /* Get VEB bandwidth, to be implemented */
4841         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4842         if (vsi)
4843                 vsi->uplink_seid = veb->seid;
4844
4845         return veb;
4846 fail:
4847         rte_free(veb);
4848         return NULL;
4849 }
4850
4851 int
4852 i40e_vsi_release(struct i40e_vsi *vsi)
4853 {
4854         struct i40e_pf *pf;
4855         struct i40e_hw *hw;
4856         struct i40e_vsi_list *vsi_list;
4857         void *temp;
4858         int ret;
4859         struct i40e_mac_filter *f;
4860         uint16_t user_param;
4861
4862         if (!vsi)
4863                 return I40E_SUCCESS;
4864
4865         if (!vsi->adapter)
4866                 return -EFAULT;
4867
4868         user_param = vsi->user_param;
4869
4870         pf = I40E_VSI_TO_PF(vsi);
4871         hw = I40E_VSI_TO_HW(vsi);
4872
4873         /* VSI has child to attach, release child first */
4874         if (vsi->veb) {
4875                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4876                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4877                                 return -1;
4878                 }
4879                 i40e_veb_release(vsi->veb);
4880         }
4881
4882         if (vsi->floating_veb) {
4883                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4884                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4885                                 return -1;
4886                 }
4887         }
4888
4889         /* Remove all macvlan filters of the VSI */
4890         i40e_vsi_remove_all_macvlan_filter(vsi);
4891         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4892                 rte_free(f);
4893
4894         if (vsi->type != I40E_VSI_MAIN &&
4895             ((vsi->type != I40E_VSI_SRIOV) ||
4896             !pf->floating_veb_list[user_param])) {
4897                 /* Remove vsi from parent's sibling list */
4898                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4899                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4900                         return I40E_ERR_PARAM;
4901                 }
4902                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4903                                 &vsi->sib_vsi_list, list);
4904
4905                 /* Remove all switch element of the VSI */
4906                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4907                 if (ret != I40E_SUCCESS)
4908                         PMD_DRV_LOG(ERR, "Failed to delete element");
4909         }
4910
4911         if ((vsi->type == I40E_VSI_SRIOV) &&
4912             pf->floating_veb_list[user_param]) {
4913                 /* Remove vsi from parent's sibling list */
4914                 if (vsi->parent_vsi == NULL ||
4915                     vsi->parent_vsi->floating_veb == NULL) {
4916                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4917                         return I40E_ERR_PARAM;
4918                 }
4919                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4920                              &vsi->sib_vsi_list, list);
4921
4922                 /* Remove all switch element of the VSI */
4923                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4924                 if (ret != I40E_SUCCESS)
4925                         PMD_DRV_LOG(ERR, "Failed to delete element");
4926         }
4927
4928         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4929
4930         if (vsi->type != I40E_VSI_SRIOV)
4931                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4932         rte_free(vsi);
4933
4934         return I40E_SUCCESS;
4935 }
4936
4937 static int
4938 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4939 {
4940         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4941         struct i40e_aqc_remove_macvlan_element_data def_filter;
4942         struct i40e_mac_filter_info filter;
4943         int ret;
4944
4945         if (vsi->type != I40E_VSI_MAIN)
4946                 return I40E_ERR_CONFIG;
4947         memset(&def_filter, 0, sizeof(def_filter));
4948         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4949                                         ETH_ADDR_LEN);
4950         def_filter.vlan_tag = 0;
4951         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4952                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4953         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4954         if (ret != I40E_SUCCESS) {
4955                 struct i40e_mac_filter *f;
4956                 struct ether_addr *mac;
4957
4958                 PMD_DRV_LOG(DEBUG,
4959                             "Cannot remove the default macvlan filter");
4960                 /* It needs to add the permanent mac into mac list */
4961                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4962                 if (f == NULL) {
4963                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4964                         return I40E_ERR_NO_MEMORY;
4965                 }
4966                 mac = &f->mac_info.mac_addr;
4967                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4968                                 ETH_ADDR_LEN);
4969                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4970                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4971                 vsi->mac_num++;
4972
4973                 return ret;
4974         }
4975         rte_memcpy(&filter.mac_addr,
4976                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4977         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4978         return i40e_vsi_add_mac(vsi, &filter);
4979 }
4980
4981 /*
4982  * i40e_vsi_get_bw_config - Query VSI BW Information
4983  * @vsi: the VSI to be queried
4984  *
4985  * Returns 0 on success, negative value on failure
4986  */
4987 static enum i40e_status_code
4988 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4989 {
4990         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4991         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4992         struct i40e_hw *hw = &vsi->adapter->hw;
4993         i40e_status ret;
4994         int i;
4995         uint32_t bw_max;
4996
4997         memset(&bw_config, 0, sizeof(bw_config));
4998         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4999         if (ret != I40E_SUCCESS) {
5000                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5001                             hw->aq.asq_last_status);
5002                 return ret;
5003         }
5004
5005         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5006         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5007                                         &ets_sla_config, NULL);
5008         if (ret != I40E_SUCCESS) {
5009                 PMD_DRV_LOG(ERR,
5010                         "VSI failed to get TC bandwdith configuration %u",
5011                         hw->aq.asq_last_status);
5012                 return ret;
5013         }
5014
5015         /* store and print out BW info */
5016         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5017         vsi->bw_info.bw_max = bw_config.max_bw;
5018         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5019         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5020         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5021                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5022                      I40E_16_BIT_WIDTH);
5023         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5024                 vsi->bw_info.bw_ets_share_credits[i] =
5025                                 ets_sla_config.share_credits[i];
5026                 vsi->bw_info.bw_ets_credits[i] =
5027                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5028                 /* 4 bits per TC, 4th bit is reserved */
5029                 vsi->bw_info.bw_ets_max[i] =
5030                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5031                                   RTE_LEN2MASK(3, uint8_t));
5032                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5033                             vsi->bw_info.bw_ets_share_credits[i]);
5034                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5035                             vsi->bw_info.bw_ets_credits[i]);
5036                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5037                             vsi->bw_info.bw_ets_max[i]);
5038         }
5039
5040         return I40E_SUCCESS;
5041 }
5042
5043 /* i40e_enable_pf_lb
5044  * @pf: pointer to the pf structure
5045  *
5046  * allow loopback on pf
5047  */
5048 static inline void
5049 i40e_enable_pf_lb(struct i40e_pf *pf)
5050 {
5051         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5052         struct i40e_vsi_context ctxt;
5053         int ret;
5054
5055         /* Use the FW API if FW >= v5.0 */
5056         if (hw->aq.fw_maj_ver < 5) {
5057                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5058                 return;
5059         }
5060
5061         memset(&ctxt, 0, sizeof(ctxt));
5062         ctxt.seid = pf->main_vsi_seid;
5063         ctxt.pf_num = hw->pf_id;
5064         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5065         if (ret) {
5066                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5067                             ret, hw->aq.asq_last_status);
5068                 return;
5069         }
5070         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5071         ctxt.info.valid_sections =
5072                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5073         ctxt.info.switch_id |=
5074                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5075
5076         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5077         if (ret)
5078                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5079                             hw->aq.asq_last_status);
5080 }
5081
5082 /* Setup a VSI */
5083 struct i40e_vsi *
5084 i40e_vsi_setup(struct i40e_pf *pf,
5085                enum i40e_vsi_type type,
5086                struct i40e_vsi *uplink_vsi,
5087                uint16_t user_param)
5088 {
5089         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5090         struct i40e_vsi *vsi;
5091         struct i40e_mac_filter_info filter;
5092         int ret;
5093         struct i40e_vsi_context ctxt;
5094         struct ether_addr broadcast =
5095                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5096
5097         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5098             uplink_vsi == NULL) {
5099                 PMD_DRV_LOG(ERR,
5100                         "VSI setup failed, VSI link shouldn't be NULL");
5101                 return NULL;
5102         }
5103
5104         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5105                 PMD_DRV_LOG(ERR,
5106                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5107                 return NULL;
5108         }
5109
5110         /* two situations
5111          * 1.type is not MAIN and uplink vsi is not NULL
5112          * If uplink vsi didn't setup VEB, create one first under veb field
5113          * 2.type is SRIOV and the uplink is NULL
5114          * If floating VEB is NULL, create one veb under floating veb field
5115          */
5116
5117         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5118             uplink_vsi->veb == NULL) {
5119                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5120
5121                 if (uplink_vsi->veb == NULL) {
5122                         PMD_DRV_LOG(ERR, "VEB setup failed");
5123                         return NULL;
5124                 }
5125                 /* set ALLOWLOOPBACk on pf, when veb is created */
5126                 i40e_enable_pf_lb(pf);
5127         }
5128
5129         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5130             pf->main_vsi->floating_veb == NULL) {
5131                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5132
5133                 if (pf->main_vsi->floating_veb == NULL) {
5134                         PMD_DRV_LOG(ERR, "VEB setup failed");
5135                         return NULL;
5136                 }
5137         }
5138
5139         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5140         if (!vsi) {
5141                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5142                 return NULL;
5143         }
5144         TAILQ_INIT(&vsi->mac_list);
5145         vsi->type = type;
5146         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5147         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5148         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5149         vsi->user_param = user_param;
5150         vsi->vlan_anti_spoof_on = 0;
5151         vsi->vlan_filter_on = 0;
5152         /* Allocate queues */
5153         switch (vsi->type) {
5154         case I40E_VSI_MAIN  :
5155                 vsi->nb_qps = pf->lan_nb_qps;
5156                 break;
5157         case I40E_VSI_SRIOV :
5158                 vsi->nb_qps = pf->vf_nb_qps;
5159                 break;
5160         case I40E_VSI_VMDQ2:
5161                 vsi->nb_qps = pf->vmdq_nb_qps;
5162                 break;
5163         case I40E_VSI_FDIR:
5164                 vsi->nb_qps = pf->fdir_nb_qps;
5165                 break;
5166         default:
5167                 goto fail_mem;
5168         }
5169         /*
5170          * The filter status descriptor is reported in rx queue 0,
5171          * while the tx queue for fdir filter programming has no
5172          * such constraints, can be non-zero queues.
5173          * To simplify it, choose FDIR vsi use queue 0 pair.
5174          * To make sure it will use queue 0 pair, queue allocation
5175          * need be done before this function is called
5176          */
5177         if (type != I40E_VSI_FDIR) {
5178                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5179                         if (ret < 0) {
5180                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5181                                                 vsi->seid, ret);
5182                                 goto fail_mem;
5183                         }
5184                         vsi->base_queue = ret;
5185         } else
5186                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5187
5188         /* VF has MSIX interrupt in VF range, don't allocate here */
5189         if (type == I40E_VSI_MAIN) {
5190                 if (pf->support_multi_driver) {
5191                         /* If support multi-driver, need to use INT0 instead of
5192                          * allocating from msix pool. The Msix pool is init from
5193                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5194                          * to 1 without calling i40e_res_pool_alloc.
5195                          */
5196                         vsi->msix_intr = 0;
5197                         vsi->nb_msix = 1;
5198                 } else {
5199                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5200                                                   RTE_MIN(vsi->nb_qps,
5201                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5202                         if (ret < 0) {
5203                                 PMD_DRV_LOG(ERR,
5204                                             "VSI MAIN %d get heap failed %d",
5205                                             vsi->seid, ret);
5206                                 goto fail_queue_alloc;
5207                         }
5208                         vsi->msix_intr = ret;
5209                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5210                                                RTE_MAX_RXTX_INTR_VEC_ID);
5211                 }
5212         } else if (type != I40E_VSI_SRIOV) {
5213                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5214                 if (ret < 0) {
5215                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5216                         goto fail_queue_alloc;
5217                 }
5218                 vsi->msix_intr = ret;
5219                 vsi->nb_msix = 1;
5220         } else {
5221                 vsi->msix_intr = 0;
5222                 vsi->nb_msix = 0;
5223         }
5224
5225         /* Add VSI */
5226         if (type == I40E_VSI_MAIN) {
5227                 /* For main VSI, no need to add since it's default one */
5228                 vsi->uplink_seid = pf->mac_seid;
5229                 vsi->seid = pf->main_vsi_seid;
5230                 /* Bind queues with specific MSIX interrupt */
5231                 /**
5232                  * Needs 2 interrupt at least, one for misc cause which will
5233                  * enabled from OS side, Another for queues binding the
5234                  * interrupt from device side only.
5235                  */
5236
5237                 /* Get default VSI parameters from hardware */
5238                 memset(&ctxt, 0, sizeof(ctxt));
5239                 ctxt.seid = vsi->seid;
5240                 ctxt.pf_num = hw->pf_id;
5241                 ctxt.uplink_seid = vsi->uplink_seid;
5242                 ctxt.vf_num = 0;
5243                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5244                 if (ret != I40E_SUCCESS) {
5245                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5246                         goto fail_msix_alloc;
5247                 }
5248                 rte_memcpy(&vsi->info, &ctxt.info,
5249                         sizeof(struct i40e_aqc_vsi_properties_data));
5250                 vsi->vsi_id = ctxt.vsi_number;
5251                 vsi->info.valid_sections = 0;
5252
5253                 /* Configure tc, enabled TC0 only */
5254                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5255                         I40E_SUCCESS) {
5256                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5257                         goto fail_msix_alloc;
5258                 }
5259
5260                 /* TC, queue mapping */
5261                 memset(&ctxt, 0, sizeof(ctxt));
5262                 vsi->info.valid_sections |=
5263                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5264                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5265                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5266                 rte_memcpy(&ctxt.info, &vsi->info,
5267                         sizeof(struct i40e_aqc_vsi_properties_data));
5268                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5269                                                 I40E_DEFAULT_TCMAP);
5270                 if (ret != I40E_SUCCESS) {
5271                         PMD_DRV_LOG(ERR,
5272                                 "Failed to configure TC queue mapping");
5273                         goto fail_msix_alloc;
5274                 }
5275                 ctxt.seid = vsi->seid;
5276                 ctxt.pf_num = hw->pf_id;
5277                 ctxt.uplink_seid = vsi->uplink_seid;
5278                 ctxt.vf_num = 0;
5279
5280                 /* Update VSI parameters */
5281                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5282                 if (ret != I40E_SUCCESS) {
5283                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5284                         goto fail_msix_alloc;
5285                 }
5286
5287                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5288                                                 sizeof(vsi->info.tc_mapping));
5289                 rte_memcpy(&vsi->info.queue_mapping,
5290                                 &ctxt.info.queue_mapping,
5291                         sizeof(vsi->info.queue_mapping));
5292                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5293                 vsi->info.valid_sections = 0;
5294
5295                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5296                                 ETH_ADDR_LEN);
5297
5298                 /**
5299                  * Updating default filter settings are necessary to prevent
5300                  * reception of tagged packets.
5301                  * Some old firmware configurations load a default macvlan
5302                  * filter which accepts both tagged and untagged packets.
5303                  * The updating is to use a normal filter instead if needed.
5304                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5305                  * The firmware with correct configurations load the default
5306                  * macvlan filter which is expected and cannot be removed.
5307                  */
5308                 i40e_update_default_filter_setting(vsi);
5309                 i40e_config_qinq(hw, vsi);
5310         } else if (type == I40E_VSI_SRIOV) {
5311                 memset(&ctxt, 0, sizeof(ctxt));
5312                 /**
5313                  * For other VSI, the uplink_seid equals to uplink VSI's
5314                  * uplink_seid since they share same VEB
5315                  */
5316                 if (uplink_vsi == NULL)
5317                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5318                 else
5319                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5320                 ctxt.pf_num = hw->pf_id;
5321                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5322                 ctxt.uplink_seid = vsi->uplink_seid;
5323                 ctxt.connection_type = 0x1;
5324                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5325
5326                 /* Use the VEB configuration if FW >= v5.0 */
5327                 if (hw->aq.fw_maj_ver >= 5) {
5328                         /* Configure switch ID */
5329                         ctxt.info.valid_sections |=
5330                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5331                         ctxt.info.switch_id =
5332                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5333                 }
5334
5335                 /* Configure port/vlan */
5336                 ctxt.info.valid_sections |=
5337                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5338                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5339                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5340                                                 hw->func_caps.enabled_tcmap);
5341                 if (ret != I40E_SUCCESS) {
5342                         PMD_DRV_LOG(ERR,
5343                                 "Failed to configure TC queue mapping");
5344                         goto fail_msix_alloc;
5345                 }
5346
5347                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5348                 ctxt.info.valid_sections |=
5349                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5350                 /**
5351                  * Since VSI is not created yet, only configure parameter,
5352                  * will add vsi below.
5353                  */
5354
5355                 i40e_config_qinq(hw, vsi);
5356         } else if (type == I40E_VSI_VMDQ2) {
5357                 memset(&ctxt, 0, sizeof(ctxt));
5358                 /*
5359                  * For other VSI, the uplink_seid equals to uplink VSI's
5360                  * uplink_seid since they share same VEB
5361                  */
5362                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5363                 ctxt.pf_num = hw->pf_id;
5364                 ctxt.vf_num = 0;
5365                 ctxt.uplink_seid = vsi->uplink_seid;
5366                 ctxt.connection_type = 0x1;
5367                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5368
5369                 ctxt.info.valid_sections |=
5370                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5371                 /* user_param carries flag to enable loop back */
5372                 if (user_param) {
5373                         ctxt.info.switch_id =
5374                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5375                         ctxt.info.switch_id |=
5376                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5377                 }
5378
5379                 /* Configure port/vlan */
5380                 ctxt.info.valid_sections |=
5381                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5382                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5383                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5384                                                 I40E_DEFAULT_TCMAP);
5385                 if (ret != I40E_SUCCESS) {
5386                         PMD_DRV_LOG(ERR,
5387                                 "Failed to configure TC queue mapping");
5388                         goto fail_msix_alloc;
5389                 }
5390                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5391                 ctxt.info.valid_sections |=
5392                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5393         } else if (type == I40E_VSI_FDIR) {
5394                 memset(&ctxt, 0, sizeof(ctxt));
5395                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5396                 ctxt.pf_num = hw->pf_id;
5397                 ctxt.vf_num = 0;
5398                 ctxt.uplink_seid = vsi->uplink_seid;
5399                 ctxt.connection_type = 0x1;     /* regular data port */
5400                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5401                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5402                                                 I40E_DEFAULT_TCMAP);
5403                 if (ret != I40E_SUCCESS) {
5404                         PMD_DRV_LOG(ERR,
5405                                 "Failed to configure TC queue mapping.");
5406                         goto fail_msix_alloc;
5407                 }
5408                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5409                 ctxt.info.valid_sections |=
5410                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5411         } else {
5412                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5413                 goto fail_msix_alloc;
5414         }
5415
5416         if (vsi->type != I40E_VSI_MAIN) {
5417                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5418                 if (ret != I40E_SUCCESS) {
5419                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5420                                     hw->aq.asq_last_status);
5421                         goto fail_msix_alloc;
5422                 }
5423                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5424                 vsi->info.valid_sections = 0;
5425                 vsi->seid = ctxt.seid;
5426                 vsi->vsi_id = ctxt.vsi_number;
5427                 vsi->sib_vsi_list.vsi = vsi;
5428                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5429                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5430                                           &vsi->sib_vsi_list, list);
5431                 } else {
5432                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5433                                           &vsi->sib_vsi_list, list);
5434                 }
5435         }
5436
5437         /* MAC/VLAN configuration */
5438         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5439         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5440
5441         ret = i40e_vsi_add_mac(vsi, &filter);
5442         if (ret != I40E_SUCCESS) {
5443                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5444                 goto fail_msix_alloc;
5445         }
5446
5447         /* Get VSI BW information */
5448         i40e_vsi_get_bw_config(vsi);
5449         return vsi;
5450 fail_msix_alloc:
5451         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5452 fail_queue_alloc:
5453         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5454 fail_mem:
5455         rte_free(vsi);
5456         return NULL;
5457 }
5458
5459 /* Configure vlan filter on or off */
5460 int
5461 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5462 {
5463         int i, num;
5464         struct i40e_mac_filter *f;
5465         void *temp;
5466         struct i40e_mac_filter_info *mac_filter;
5467         enum rte_mac_filter_type desired_filter;
5468         int ret = I40E_SUCCESS;
5469
5470         if (on) {
5471                 /* Filter to match MAC and VLAN */
5472                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5473         } else {
5474                 /* Filter to match only MAC */
5475                 desired_filter = RTE_MAC_PERFECT_MATCH;
5476         }
5477
5478         num = vsi->mac_num;
5479
5480         mac_filter = rte_zmalloc("mac_filter_info_data",
5481                                  num * sizeof(*mac_filter), 0);
5482         if (mac_filter == NULL) {
5483                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5484                 return I40E_ERR_NO_MEMORY;
5485         }
5486
5487         i = 0;
5488
5489         /* Remove all existing mac */
5490         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5491                 mac_filter[i] = f->mac_info;
5492                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5493                 if (ret) {
5494                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5495                                     on ? "enable" : "disable");
5496                         goto DONE;
5497                 }
5498                 i++;
5499         }
5500
5501         /* Override with new filter */
5502         for (i = 0; i < num; i++) {
5503                 mac_filter[i].filter_type = desired_filter;
5504                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5505                 if (ret) {
5506                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5507                                     on ? "enable" : "disable");
5508                         goto DONE;
5509                 }
5510         }
5511
5512 DONE:
5513         rte_free(mac_filter);
5514         return ret;
5515 }
5516
5517 /* Configure vlan stripping on or off */
5518 int
5519 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5520 {
5521         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5522         struct i40e_vsi_context ctxt;
5523         uint8_t vlan_flags;
5524         int ret = I40E_SUCCESS;
5525
5526         /* Check if it has been already on or off */
5527         if (vsi->info.valid_sections &
5528                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5529                 if (on) {
5530                         if ((vsi->info.port_vlan_flags &
5531                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5532                                 return 0; /* already on */
5533                 } else {
5534                         if ((vsi->info.port_vlan_flags &
5535                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5536                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5537                                 return 0; /* already off */
5538                 }
5539         }
5540
5541         if (on)
5542                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5543         else
5544                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5545         vsi->info.valid_sections =
5546                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5547         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5548         vsi->info.port_vlan_flags |= vlan_flags;
5549         ctxt.seid = vsi->seid;
5550         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5551         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5552         if (ret)
5553                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5554                             on ? "enable" : "disable");
5555
5556         return ret;
5557 }
5558
5559 static int
5560 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5561 {
5562         struct rte_eth_dev_data *data = dev->data;
5563         int ret;
5564         int mask = 0;
5565
5566         /* Apply vlan offload setting */
5567         mask = ETH_VLAN_STRIP_MASK |
5568                ETH_VLAN_FILTER_MASK |
5569                ETH_VLAN_EXTEND_MASK;
5570         ret = i40e_vlan_offload_set(dev, mask);
5571         if (ret) {
5572                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5573                 return ret;
5574         }
5575
5576         /* Apply pvid setting */
5577         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5578                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5579         if (ret)
5580                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5581
5582         return ret;
5583 }
5584
5585 static int
5586 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5587 {
5588         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5589
5590         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5591 }
5592
5593 static int
5594 i40e_update_flow_control(struct i40e_hw *hw)
5595 {
5596 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5597         struct i40e_link_status link_status;
5598         uint32_t rxfc = 0, txfc = 0, reg;
5599         uint8_t an_info;
5600         int ret;
5601
5602         memset(&link_status, 0, sizeof(link_status));
5603         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5604         if (ret != I40E_SUCCESS) {
5605                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5606                 goto write_reg; /* Disable flow control */
5607         }
5608
5609         an_info = hw->phy.link_info.an_info;
5610         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5611                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5612                 ret = I40E_ERR_NOT_READY;
5613                 goto write_reg; /* Disable flow control */
5614         }
5615         /**
5616          * If link auto negotiation is enabled, flow control needs to
5617          * be configured according to it
5618          */
5619         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5620         case I40E_LINK_PAUSE_RXTX:
5621                 rxfc = 1;
5622                 txfc = 1;
5623                 hw->fc.current_mode = I40E_FC_FULL;
5624                 break;
5625         case I40E_AQ_LINK_PAUSE_RX:
5626                 rxfc = 1;
5627                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5628                 break;
5629         case I40E_AQ_LINK_PAUSE_TX:
5630                 txfc = 1;
5631                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5632                 break;
5633         default:
5634                 hw->fc.current_mode = I40E_FC_NONE;
5635                 break;
5636         }
5637
5638 write_reg:
5639         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5640                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5641         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5642         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5643         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5644         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5645
5646         return ret;
5647 }
5648
5649 /* PF setup */
5650 static int
5651 i40e_pf_setup(struct i40e_pf *pf)
5652 {
5653         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5654         struct i40e_filter_control_settings settings;
5655         struct i40e_vsi *vsi;
5656         int ret;
5657
5658         /* Clear all stats counters */
5659         pf->offset_loaded = FALSE;
5660         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5661         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5662         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5663         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5664
5665         ret = i40e_pf_get_switch_config(pf);
5666         if (ret != I40E_SUCCESS) {
5667                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5668                 return ret;
5669         }
5670         if (pf->flags & I40E_FLAG_FDIR) {
5671                 /* make queue allocated first, let FDIR use queue pair 0*/
5672                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5673                 if (ret != I40E_FDIR_QUEUE_ID) {
5674                         PMD_DRV_LOG(ERR,
5675                                 "queue allocation fails for FDIR: ret =%d",
5676                                 ret);
5677                         pf->flags &= ~I40E_FLAG_FDIR;
5678                 }
5679         }
5680         /*  main VSI setup */
5681         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5682         if (!vsi) {
5683                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5684                 return I40E_ERR_NOT_READY;
5685         }
5686         pf->main_vsi = vsi;
5687
5688         /* Configure filter control */
5689         memset(&settings, 0, sizeof(settings));
5690         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5691                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5692         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5693                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5694         else {
5695                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5696                         hw->func_caps.rss_table_size);
5697                 return I40E_ERR_PARAM;
5698         }
5699         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5700                 hw->func_caps.rss_table_size);
5701         pf->hash_lut_size = hw->func_caps.rss_table_size;
5702
5703         /* Enable ethtype and macvlan filters */
5704         settings.enable_ethtype = TRUE;
5705         settings.enable_macvlan = TRUE;
5706         ret = i40e_set_filter_control(hw, &settings);
5707         if (ret)
5708                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5709                                                                 ret);
5710
5711         /* Update flow control according to the auto negotiation */
5712         i40e_update_flow_control(hw);
5713
5714         return I40E_SUCCESS;
5715 }
5716
5717 int
5718 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5719 {
5720         uint32_t reg;
5721         uint16_t j;
5722
5723         /**
5724          * Set or clear TX Queue Disable flags,
5725          * which is required by hardware.
5726          */
5727         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5728         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5729
5730         /* Wait until the request is finished */
5731         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5732                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5733                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5734                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5735                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5736                                                         & 0x1))) {
5737                         break;
5738                 }
5739         }
5740         if (on) {
5741                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5742                         return I40E_SUCCESS; /* already on, skip next steps */
5743
5744                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5745                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5746         } else {
5747                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5748                         return I40E_SUCCESS; /* already off, skip next steps */
5749                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5750         }
5751         /* Write the register */
5752         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5753         /* Check the result */
5754         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5755                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5756                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5757                 if (on) {
5758                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5759                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5760                                 break;
5761                 } else {
5762                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5763                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5764                                 break;
5765                 }
5766         }
5767         /* Check if it is timeout */
5768         if (j >= I40E_CHK_Q_ENA_COUNT) {
5769                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5770                             (on ? "enable" : "disable"), q_idx);
5771                 return I40E_ERR_TIMEOUT;
5772         }
5773
5774         return I40E_SUCCESS;
5775 }
5776
5777 /* Swith on or off the tx queues */
5778 static int
5779 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5780 {
5781         struct rte_eth_dev_data *dev_data = pf->dev_data;
5782         struct i40e_tx_queue *txq;
5783         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5784         uint16_t i;
5785         int ret;
5786
5787         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5788                 txq = dev_data->tx_queues[i];
5789                 /* Don't operate the queue if not configured or
5790                  * if starting only per queue */
5791                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5792                         continue;
5793                 if (on)
5794                         ret = i40e_dev_tx_queue_start(dev, i);
5795                 else
5796                         ret = i40e_dev_tx_queue_stop(dev, i);
5797                 if ( ret != I40E_SUCCESS)
5798                         return ret;
5799         }
5800
5801         return I40E_SUCCESS;
5802 }
5803
5804 int
5805 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5806 {
5807         uint32_t reg;
5808         uint16_t j;
5809
5810         /* Wait until the request is finished */
5811         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5812                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5813                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5814                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5815                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5816                         break;
5817         }
5818
5819         if (on) {
5820                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5821                         return I40E_SUCCESS; /* Already on, skip next steps */
5822                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5823         } else {
5824                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5825                         return I40E_SUCCESS; /* Already off, skip next steps */
5826                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5827         }
5828
5829         /* Write the register */
5830         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5831         /* Check the result */
5832         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5833                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5834                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5835                 if (on) {
5836                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5837                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5838                                 break;
5839                 } else {
5840                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5841                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5842                                 break;
5843                 }
5844         }
5845
5846         /* Check if it is timeout */
5847         if (j >= I40E_CHK_Q_ENA_COUNT) {
5848                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5849                             (on ? "enable" : "disable"), q_idx);
5850                 return I40E_ERR_TIMEOUT;
5851         }
5852
5853         return I40E_SUCCESS;
5854 }
5855 /* Switch on or off the rx queues */
5856 static int
5857 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5858 {
5859         struct rte_eth_dev_data *dev_data = pf->dev_data;
5860         struct i40e_rx_queue *rxq;
5861         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5862         uint16_t i;
5863         int ret;
5864
5865         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5866                 rxq = dev_data->rx_queues[i];
5867                 /* Don't operate the queue if not configured or
5868                  * if starting only per queue */
5869                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5870                         continue;
5871                 if (on)
5872                         ret = i40e_dev_rx_queue_start(dev, i);
5873                 else
5874                         ret = i40e_dev_rx_queue_stop(dev, i);
5875                 if (ret != I40E_SUCCESS)
5876                         return ret;
5877         }
5878
5879         return I40E_SUCCESS;
5880 }
5881
5882 /* Switch on or off all the rx/tx queues */
5883 int
5884 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5885 {
5886         int ret;
5887
5888         if (on) {
5889                 /* enable rx queues before enabling tx queues */
5890                 ret = i40e_dev_switch_rx_queues(pf, on);
5891                 if (ret) {
5892                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5893                         return ret;
5894                 }
5895                 ret = i40e_dev_switch_tx_queues(pf, on);
5896         } else {
5897                 /* Stop tx queues before stopping rx queues */
5898                 ret = i40e_dev_switch_tx_queues(pf, on);
5899                 if (ret) {
5900                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5901                         return ret;
5902                 }
5903                 ret = i40e_dev_switch_rx_queues(pf, on);
5904         }
5905
5906         return ret;
5907 }
5908
5909 /* Initialize VSI for TX */
5910 static int
5911 i40e_dev_tx_init(struct i40e_pf *pf)
5912 {
5913         struct rte_eth_dev_data *data = pf->dev_data;
5914         uint16_t i;
5915         uint32_t ret = I40E_SUCCESS;
5916         struct i40e_tx_queue *txq;
5917
5918         for (i = 0; i < data->nb_tx_queues; i++) {
5919                 txq = data->tx_queues[i];
5920                 if (!txq || !txq->q_set)
5921                         continue;
5922                 ret = i40e_tx_queue_init(txq);
5923                 if (ret != I40E_SUCCESS)
5924                         break;
5925         }
5926         if (ret == I40E_SUCCESS)
5927                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5928                                      ->eth_dev);
5929
5930         return ret;
5931 }
5932
5933 /* Initialize VSI for RX */
5934 static int
5935 i40e_dev_rx_init(struct i40e_pf *pf)
5936 {
5937         struct rte_eth_dev_data *data = pf->dev_data;
5938         int ret = I40E_SUCCESS;
5939         uint16_t i;
5940         struct i40e_rx_queue *rxq;
5941
5942         i40e_pf_config_mq_rx(pf);
5943         for (i = 0; i < data->nb_rx_queues; i++) {
5944                 rxq = data->rx_queues[i];
5945                 if (!rxq || !rxq->q_set)
5946                         continue;
5947
5948                 ret = i40e_rx_queue_init(rxq);
5949                 if (ret != I40E_SUCCESS) {
5950                         PMD_DRV_LOG(ERR,
5951                                 "Failed to do RX queue initialization");
5952                         break;
5953                 }
5954         }
5955         if (ret == I40E_SUCCESS)
5956                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5957                                      ->eth_dev);
5958
5959         return ret;
5960 }
5961
5962 static int
5963 i40e_dev_rxtx_init(struct i40e_pf *pf)
5964 {
5965         int err;
5966
5967         err = i40e_dev_tx_init(pf);
5968         if (err) {
5969                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5970                 return err;
5971         }
5972         err = i40e_dev_rx_init(pf);
5973         if (err) {
5974                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5975                 return err;
5976         }
5977
5978         return err;
5979 }
5980
5981 static int
5982 i40e_vmdq_setup(struct rte_eth_dev *dev)
5983 {
5984         struct rte_eth_conf *conf = &dev->data->dev_conf;
5985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5986         int i, err, conf_vsis, j, loop;
5987         struct i40e_vsi *vsi;
5988         struct i40e_vmdq_info *vmdq_info;
5989         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5990         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5991
5992         /*
5993          * Disable interrupt to avoid message from VF. Furthermore, it will
5994          * avoid race condition in VSI creation/destroy.
5995          */
5996         i40e_pf_disable_irq0(hw);
5997
5998         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5999                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6000                 return -ENOTSUP;
6001         }
6002
6003         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6004         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6005                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6006                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6007                         pf->max_nb_vmdq_vsi);
6008                 return -ENOTSUP;
6009         }
6010
6011         if (pf->vmdq != NULL) {
6012                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6013                 return 0;
6014         }
6015
6016         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6017                                 sizeof(*vmdq_info) * conf_vsis, 0);
6018
6019         if (pf->vmdq == NULL) {
6020                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6021                 return -ENOMEM;
6022         }
6023
6024         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6025
6026         /* Create VMDQ VSI */
6027         for (i = 0; i < conf_vsis; i++) {
6028                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6029                                 vmdq_conf->enable_loop_back);
6030                 if (vsi == NULL) {
6031                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6032                         err = -1;
6033                         goto err_vsi_setup;
6034                 }
6035                 vmdq_info = &pf->vmdq[i];
6036                 vmdq_info->pf = pf;
6037                 vmdq_info->vsi = vsi;
6038         }
6039         pf->nb_cfg_vmdq_vsi = conf_vsis;
6040
6041         /* Configure Vlan */
6042         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6043         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6044                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6045                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6046                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6047                                         vmdq_conf->pool_map[i].vlan_id, j);
6048
6049                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6050                                                 vmdq_conf->pool_map[i].vlan_id);
6051                                 if (err) {
6052                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6053                                         err = -1;
6054                                         goto err_vsi_setup;
6055                                 }
6056                         }
6057                 }
6058         }
6059
6060         i40e_pf_enable_irq0(hw);
6061
6062         return 0;
6063
6064 err_vsi_setup:
6065         for (i = 0; i < conf_vsis; i++)
6066                 if (pf->vmdq[i].vsi == NULL)
6067                         break;
6068                 else
6069                         i40e_vsi_release(pf->vmdq[i].vsi);
6070
6071         rte_free(pf->vmdq);
6072         pf->vmdq = NULL;
6073         i40e_pf_enable_irq0(hw);
6074         return err;
6075 }
6076
6077 static void
6078 i40e_stat_update_32(struct i40e_hw *hw,
6079                    uint32_t reg,
6080                    bool offset_loaded,
6081                    uint64_t *offset,
6082                    uint64_t *stat)
6083 {
6084         uint64_t new_data;
6085
6086         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6087         if (!offset_loaded)
6088                 *offset = new_data;
6089
6090         if (new_data >= *offset)
6091                 *stat = (uint64_t)(new_data - *offset);
6092         else
6093                 *stat = (uint64_t)((new_data +
6094                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6095 }
6096
6097 static void
6098 i40e_stat_update_48(struct i40e_hw *hw,
6099                    uint32_t hireg,
6100                    uint32_t loreg,
6101                    bool offset_loaded,
6102                    uint64_t *offset,
6103                    uint64_t *stat)
6104 {
6105         uint64_t new_data;
6106
6107         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6108         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6109                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6110
6111         if (!offset_loaded)
6112                 *offset = new_data;
6113
6114         if (new_data >= *offset)
6115                 *stat = new_data - *offset;
6116         else
6117                 *stat = (uint64_t)((new_data +
6118                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6119
6120         *stat &= I40E_48_BIT_MASK;
6121 }
6122
6123 /* Disable IRQ0 */
6124 void
6125 i40e_pf_disable_irq0(struct i40e_hw *hw)
6126 {
6127         /* Disable all interrupt types */
6128         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6129                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6130         I40E_WRITE_FLUSH(hw);
6131 }
6132
6133 /* Enable IRQ0 */
6134 void
6135 i40e_pf_enable_irq0(struct i40e_hw *hw)
6136 {
6137         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6138                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6139                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6140                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6141         I40E_WRITE_FLUSH(hw);
6142 }
6143
6144 static void
6145 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6146 {
6147         /* read pending request and disable first */
6148         i40e_pf_disable_irq0(hw);
6149         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6150         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6151                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6152
6153         if (no_queue)
6154                 /* Link no queues with irq0 */
6155                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6156                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6157 }
6158
6159 static void
6160 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6161 {
6162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6163         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6164         int i;
6165         uint16_t abs_vf_id;
6166         uint32_t index, offset, val;
6167
6168         if (!pf->vfs)
6169                 return;
6170         /**
6171          * Try to find which VF trigger a reset, use absolute VF id to access
6172          * since the reg is global register.
6173          */
6174         for (i = 0; i < pf->vf_num; i++) {
6175                 abs_vf_id = hw->func_caps.vf_base_id + i;
6176                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6177                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6178                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6179                 /* VFR event occurred */
6180                 if (val & (0x1 << offset)) {
6181                         int ret;
6182
6183                         /* Clear the event first */
6184                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6185                                                         (0x1 << offset));
6186                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6187                         /**
6188                          * Only notify a VF reset event occurred,
6189                          * don't trigger another SW reset
6190                          */
6191                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6192                         if (ret != I40E_SUCCESS)
6193                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6194                 }
6195         }
6196 }
6197
6198 static void
6199 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6200 {
6201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6202         int i;
6203
6204         for (i = 0; i < pf->vf_num; i++)
6205                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6206 }
6207
6208 static void
6209 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6210 {
6211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6212         struct i40e_arq_event_info info;
6213         uint16_t pending, opcode;
6214         int ret;
6215
6216         info.buf_len = I40E_AQ_BUF_SZ;
6217         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6218         if (!info.msg_buf) {
6219                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6220                 return;
6221         }
6222
6223         pending = 1;
6224         while (pending) {
6225                 ret = i40e_clean_arq_element(hw, &info, &pending);
6226
6227                 if (ret != I40E_SUCCESS) {
6228                         PMD_DRV_LOG(INFO,
6229                                 "Failed to read msg from AdminQ, aq_err: %u",
6230                                 hw->aq.asq_last_status);
6231                         break;
6232                 }
6233                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6234
6235                 switch (opcode) {
6236                 case i40e_aqc_opc_send_msg_to_pf:
6237                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6238                         i40e_pf_host_handle_vf_msg(dev,
6239                                         rte_le_to_cpu_16(info.desc.retval),
6240                                         rte_le_to_cpu_32(info.desc.cookie_high),
6241                                         rte_le_to_cpu_32(info.desc.cookie_low),
6242                                         info.msg_buf,
6243                                         info.msg_len);
6244                         break;
6245                 case i40e_aqc_opc_get_link_status:
6246                         ret = i40e_dev_link_update(dev, 0);
6247                         if (!ret)
6248                                 _rte_eth_dev_callback_process(dev,
6249                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
6250                         break;
6251                 default:
6252                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6253                                     opcode);
6254                         break;
6255                 }
6256         }
6257         rte_free(info.msg_buf);
6258 }
6259
6260 /**
6261  * Interrupt handler triggered by NIC  for handling
6262  * specific interrupt.
6263  *
6264  * @param handle
6265  *  Pointer to interrupt handle.
6266  * @param param
6267  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6268  *
6269  * @return
6270  *  void
6271  */
6272 static void
6273 i40e_dev_interrupt_handler(void *param)
6274 {
6275         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6277         uint32_t icr0;
6278
6279         /* Disable interrupt */
6280         i40e_pf_disable_irq0(hw);
6281
6282         /* read out interrupt causes */
6283         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6284
6285         /* No interrupt event indicated */
6286         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6287                 PMD_DRV_LOG(INFO, "No interrupt event");
6288                 goto done;
6289         }
6290         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6291                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6292         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6293                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6294         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6295                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6296         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6297                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6298         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6299                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6300         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6301                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6302         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6303                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6304
6305         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6306                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6307                 i40e_dev_handle_vfr_event(dev);
6308         }
6309         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6310                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6311                 i40e_dev_handle_aq_msg(dev);
6312         }
6313
6314 done:
6315         /* Enable interrupt */
6316         i40e_pf_enable_irq0(hw);
6317         rte_intr_enable(dev->intr_handle);
6318 }
6319
6320 int
6321 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6322                          struct i40e_macvlan_filter *filter,
6323                          int total)
6324 {
6325         int ele_num, ele_buff_size;
6326         int num, actual_num, i;
6327         uint16_t flags;
6328         int ret = I40E_SUCCESS;
6329         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6330         struct i40e_aqc_add_macvlan_element_data *req_list;
6331
6332         if (filter == NULL  || total == 0)
6333                 return I40E_ERR_PARAM;
6334         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6335         ele_buff_size = hw->aq.asq_buf_size;
6336
6337         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6338         if (req_list == NULL) {
6339                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6340                 return I40E_ERR_NO_MEMORY;
6341         }
6342
6343         num = 0;
6344         do {
6345                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6346                 memset(req_list, 0, ele_buff_size);
6347
6348                 for (i = 0; i < actual_num; i++) {
6349                         rte_memcpy(req_list[i].mac_addr,
6350                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6351                         req_list[i].vlan_tag =
6352                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6353
6354                         switch (filter[num + i].filter_type) {
6355                         case RTE_MAC_PERFECT_MATCH:
6356                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6357                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6358                                 break;
6359                         case RTE_MACVLAN_PERFECT_MATCH:
6360                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6361                                 break;
6362                         case RTE_MAC_HASH_MATCH:
6363                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6364                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6365                                 break;
6366                         case RTE_MACVLAN_HASH_MATCH:
6367                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6368                                 break;
6369                         default:
6370                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6371                                 ret = I40E_ERR_PARAM;
6372                                 goto DONE;
6373                         }
6374
6375                         req_list[i].queue_number = 0;
6376
6377                         req_list[i].flags = rte_cpu_to_le_16(flags);
6378                 }
6379
6380                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6381                                                 actual_num, NULL);
6382                 if (ret != I40E_SUCCESS) {
6383                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6384                         goto DONE;
6385                 }
6386                 num += actual_num;
6387         } while (num < total);
6388
6389 DONE:
6390         rte_free(req_list);
6391         return ret;
6392 }
6393
6394 int
6395 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6396                             struct i40e_macvlan_filter *filter,
6397                             int total)
6398 {
6399         int ele_num, ele_buff_size;
6400         int num, actual_num, i;
6401         uint16_t flags;
6402         int ret = I40E_SUCCESS;
6403         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6404         struct i40e_aqc_remove_macvlan_element_data *req_list;
6405
6406         if (filter == NULL  || total == 0)
6407                 return I40E_ERR_PARAM;
6408
6409         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6410         ele_buff_size = hw->aq.asq_buf_size;
6411
6412         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6413         if (req_list == NULL) {
6414                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6415                 return I40E_ERR_NO_MEMORY;
6416         }
6417
6418         num = 0;
6419         do {
6420                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6421                 memset(req_list, 0, ele_buff_size);
6422
6423                 for (i = 0; i < actual_num; i++) {
6424                         rte_memcpy(req_list[i].mac_addr,
6425                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6426                         req_list[i].vlan_tag =
6427                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6428
6429                         switch (filter[num + i].filter_type) {
6430                         case RTE_MAC_PERFECT_MATCH:
6431                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6432                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6433                                 break;
6434                         case RTE_MACVLAN_PERFECT_MATCH:
6435                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6436                                 break;
6437                         case RTE_MAC_HASH_MATCH:
6438                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6439                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6440                                 break;
6441                         case RTE_MACVLAN_HASH_MATCH:
6442                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6443                                 break;
6444                         default:
6445                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6446                                 ret = I40E_ERR_PARAM;
6447                                 goto DONE;
6448                         }
6449                         req_list[i].flags = rte_cpu_to_le_16(flags);
6450                 }
6451
6452                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6453                                                 actual_num, NULL);
6454                 if (ret != I40E_SUCCESS) {
6455                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6456                         goto DONE;
6457                 }
6458                 num += actual_num;
6459         } while (num < total);
6460
6461 DONE:
6462         rte_free(req_list);
6463         return ret;
6464 }
6465
6466 /* Find out specific MAC filter */
6467 static struct i40e_mac_filter *
6468 i40e_find_mac_filter(struct i40e_vsi *vsi,
6469                          struct ether_addr *macaddr)
6470 {
6471         struct i40e_mac_filter *f;
6472
6473         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6474                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6475                         return f;
6476         }
6477
6478         return NULL;
6479 }
6480
6481 static bool
6482 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6483                          uint16_t vlan_id)
6484 {
6485         uint32_t vid_idx, vid_bit;
6486
6487         if (vlan_id > ETH_VLAN_ID_MAX)
6488                 return 0;
6489
6490         vid_idx = I40E_VFTA_IDX(vlan_id);
6491         vid_bit = I40E_VFTA_BIT(vlan_id);
6492
6493         if (vsi->vfta[vid_idx] & vid_bit)
6494                 return 1;
6495         else
6496                 return 0;
6497 }
6498
6499 static void
6500 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6501                        uint16_t vlan_id, bool on)
6502 {
6503         uint32_t vid_idx, vid_bit;
6504
6505         vid_idx = I40E_VFTA_IDX(vlan_id);
6506         vid_bit = I40E_VFTA_BIT(vlan_id);
6507
6508         if (on)
6509                 vsi->vfta[vid_idx] |= vid_bit;
6510         else
6511                 vsi->vfta[vid_idx] &= ~vid_bit;
6512 }
6513
6514 void
6515 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6516                      uint16_t vlan_id, bool on)
6517 {
6518         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6519         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6520         int ret;
6521
6522         if (vlan_id > ETH_VLAN_ID_MAX)
6523                 return;
6524
6525         i40e_store_vlan_filter(vsi, vlan_id, on);
6526
6527         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6528                 return;
6529
6530         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6531
6532         if (on) {
6533                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6534                                        &vlan_data, 1, NULL);
6535                 if (ret != I40E_SUCCESS)
6536                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6537         } else {
6538                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6539                                           &vlan_data, 1, NULL);
6540                 if (ret != I40E_SUCCESS)
6541                         PMD_DRV_LOG(ERR,
6542                                     "Failed to remove vlan filter");
6543         }
6544 }
6545
6546 /**
6547  * Find all vlan options for specific mac addr,
6548  * return with actual vlan found.
6549  */
6550 int
6551 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6552                            struct i40e_macvlan_filter *mv_f,
6553                            int num, struct ether_addr *addr)
6554 {
6555         int i;
6556         uint32_t j, k;
6557
6558         /**
6559          * Not to use i40e_find_vlan_filter to decrease the loop time,
6560          * although the code looks complex.
6561           */
6562         if (num < vsi->vlan_num)
6563                 return I40E_ERR_PARAM;
6564
6565         i = 0;
6566         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6567                 if (vsi->vfta[j]) {
6568                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6569                                 if (vsi->vfta[j] & (1 << k)) {
6570                                         if (i > num - 1) {
6571                                                 PMD_DRV_LOG(ERR,
6572                                                         "vlan number doesn't match");
6573                                                 return I40E_ERR_PARAM;
6574                                         }
6575                                         rte_memcpy(&mv_f[i].macaddr,
6576                                                         addr, ETH_ADDR_LEN);
6577                                         mv_f[i].vlan_id =
6578                                                 j * I40E_UINT32_BIT_SIZE + k;
6579                                         i++;
6580                                 }
6581                         }
6582                 }
6583         }
6584         return I40E_SUCCESS;
6585 }
6586
6587 static inline int
6588 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6589                            struct i40e_macvlan_filter *mv_f,
6590                            int num,
6591                            uint16_t vlan)
6592 {
6593         int i = 0;
6594         struct i40e_mac_filter *f;
6595
6596         if (num < vsi->mac_num)
6597                 return I40E_ERR_PARAM;
6598
6599         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6600                 if (i > num - 1) {
6601                         PMD_DRV_LOG(ERR, "buffer number not match");
6602                         return I40E_ERR_PARAM;
6603                 }
6604                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6605                                 ETH_ADDR_LEN);
6606                 mv_f[i].vlan_id = vlan;
6607                 mv_f[i].filter_type = f->mac_info.filter_type;
6608                 i++;
6609         }
6610
6611         return I40E_SUCCESS;
6612 }
6613
6614 static int
6615 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6616 {
6617         int i, j, num;
6618         struct i40e_mac_filter *f;
6619         struct i40e_macvlan_filter *mv_f;
6620         int ret = I40E_SUCCESS;
6621
6622         if (vsi == NULL || vsi->mac_num == 0)
6623                 return I40E_ERR_PARAM;
6624
6625         /* Case that no vlan is set */
6626         if (vsi->vlan_num == 0)
6627                 num = vsi->mac_num;
6628         else
6629                 num = vsi->mac_num * vsi->vlan_num;
6630
6631         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6632         if (mv_f == NULL) {
6633                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6634                 return I40E_ERR_NO_MEMORY;
6635         }
6636
6637         i = 0;
6638         if (vsi->vlan_num == 0) {
6639                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6640                         rte_memcpy(&mv_f[i].macaddr,
6641                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6642                         mv_f[i].filter_type = f->mac_info.filter_type;
6643                         mv_f[i].vlan_id = 0;
6644                         i++;
6645                 }
6646         } else {
6647                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6648                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6649                                         vsi->vlan_num, &f->mac_info.mac_addr);
6650                         if (ret != I40E_SUCCESS)
6651                                 goto DONE;
6652                         for (j = i; j < i + vsi->vlan_num; j++)
6653                                 mv_f[j].filter_type = f->mac_info.filter_type;
6654                         i += vsi->vlan_num;
6655                 }
6656         }
6657
6658         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6659 DONE:
6660         rte_free(mv_f);
6661
6662         return ret;
6663 }
6664
6665 int
6666 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6667 {
6668         struct i40e_macvlan_filter *mv_f;
6669         int mac_num;
6670         int ret = I40E_SUCCESS;
6671
6672         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6673                 return I40E_ERR_PARAM;
6674
6675         /* If it's already set, just return */
6676         if (i40e_find_vlan_filter(vsi,vlan))
6677                 return I40E_SUCCESS;
6678
6679         mac_num = vsi->mac_num;
6680
6681         if (mac_num == 0) {
6682                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6683                 return I40E_ERR_PARAM;
6684         }
6685
6686         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6687
6688         if (mv_f == NULL) {
6689                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6690                 return I40E_ERR_NO_MEMORY;
6691         }
6692
6693         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6694
6695         if (ret != I40E_SUCCESS)
6696                 goto DONE;
6697
6698         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6699
6700         if (ret != I40E_SUCCESS)
6701                 goto DONE;
6702
6703         i40e_set_vlan_filter(vsi, vlan, 1);
6704
6705         vsi->vlan_num++;
6706         ret = I40E_SUCCESS;
6707 DONE:
6708         rte_free(mv_f);
6709         return ret;
6710 }
6711
6712 int
6713 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6714 {
6715         struct i40e_macvlan_filter *mv_f;
6716         int mac_num;
6717         int ret = I40E_SUCCESS;
6718
6719         /**
6720          * Vlan 0 is the generic filter for untagged packets
6721          * and can't be removed.
6722          */
6723         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6724                 return I40E_ERR_PARAM;
6725
6726         /* If can't find it, just return */
6727         if (!i40e_find_vlan_filter(vsi, vlan))
6728                 return I40E_ERR_PARAM;
6729
6730         mac_num = vsi->mac_num;
6731
6732         if (mac_num == 0) {
6733                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6734                 return I40E_ERR_PARAM;
6735         }
6736
6737         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6738
6739         if (mv_f == NULL) {
6740                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6741                 return I40E_ERR_NO_MEMORY;
6742         }
6743
6744         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6745
6746         if (ret != I40E_SUCCESS)
6747                 goto DONE;
6748
6749         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6750
6751         if (ret != I40E_SUCCESS)
6752                 goto DONE;
6753
6754         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6755         if (vsi->vlan_num == 1) {
6756                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6757                 if (ret != I40E_SUCCESS)
6758                         goto DONE;
6759
6760                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6761                 if (ret != I40E_SUCCESS)
6762                         goto DONE;
6763         }
6764
6765         i40e_set_vlan_filter(vsi, vlan, 0);
6766
6767         vsi->vlan_num--;
6768         ret = I40E_SUCCESS;
6769 DONE:
6770         rte_free(mv_f);
6771         return ret;
6772 }
6773
6774 int
6775 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6776 {
6777         struct i40e_mac_filter *f;
6778         struct i40e_macvlan_filter *mv_f;
6779         int i, vlan_num = 0;
6780         int ret = I40E_SUCCESS;
6781
6782         /* If it's add and we've config it, return */
6783         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6784         if (f != NULL)
6785                 return I40E_SUCCESS;
6786         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6787                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6788
6789                 /**
6790                  * If vlan_num is 0, that's the first time to add mac,
6791                  * set mask for vlan_id 0.
6792                  */
6793                 if (vsi->vlan_num == 0) {
6794                         i40e_set_vlan_filter(vsi, 0, 1);
6795                         vsi->vlan_num = 1;
6796                 }
6797                 vlan_num = vsi->vlan_num;
6798         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6799                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6800                 vlan_num = 1;
6801
6802         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6803         if (mv_f == NULL) {
6804                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6805                 return I40E_ERR_NO_MEMORY;
6806         }
6807
6808         for (i = 0; i < vlan_num; i++) {
6809                 mv_f[i].filter_type = mac_filter->filter_type;
6810                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6811                                 ETH_ADDR_LEN);
6812         }
6813
6814         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6815                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6816                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6817                                         &mac_filter->mac_addr);
6818                 if (ret != I40E_SUCCESS)
6819                         goto DONE;
6820         }
6821
6822         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6823         if (ret != I40E_SUCCESS)
6824                 goto DONE;
6825
6826         /* Add the mac addr into mac list */
6827         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6828         if (f == NULL) {
6829                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6830                 ret = I40E_ERR_NO_MEMORY;
6831                 goto DONE;
6832         }
6833         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6834                         ETH_ADDR_LEN);
6835         f->mac_info.filter_type = mac_filter->filter_type;
6836         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6837         vsi->mac_num++;
6838
6839         ret = I40E_SUCCESS;
6840 DONE:
6841         rte_free(mv_f);
6842
6843         return ret;
6844 }
6845
6846 int
6847 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6848 {
6849         struct i40e_mac_filter *f;
6850         struct i40e_macvlan_filter *mv_f;
6851         int i, vlan_num;
6852         enum rte_mac_filter_type filter_type;
6853         int ret = I40E_SUCCESS;
6854
6855         /* Can't find it, return an error */
6856         f = i40e_find_mac_filter(vsi, addr);
6857         if (f == NULL)
6858                 return I40E_ERR_PARAM;
6859
6860         vlan_num = vsi->vlan_num;
6861         filter_type = f->mac_info.filter_type;
6862         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6863                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6864                 if (vlan_num == 0) {
6865                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6866                         return I40E_ERR_PARAM;
6867                 }
6868         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6869                         filter_type == RTE_MAC_HASH_MATCH)
6870                 vlan_num = 1;
6871
6872         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6873         if (mv_f == NULL) {
6874                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6875                 return I40E_ERR_NO_MEMORY;
6876         }
6877
6878         for (i = 0; i < vlan_num; i++) {
6879                 mv_f[i].filter_type = filter_type;
6880                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6881                                 ETH_ADDR_LEN);
6882         }
6883         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6884                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6885                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6886                 if (ret != I40E_SUCCESS)
6887                         goto DONE;
6888         }
6889
6890         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6891         if (ret != I40E_SUCCESS)
6892                 goto DONE;
6893
6894         /* Remove the mac addr into mac list */
6895         TAILQ_REMOVE(&vsi->mac_list, f, next);
6896         rte_free(f);
6897         vsi->mac_num--;
6898
6899         ret = I40E_SUCCESS;
6900 DONE:
6901         rte_free(mv_f);
6902         return ret;
6903 }
6904
6905 /* Configure hash enable flags for RSS */
6906 uint64_t
6907 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6908 {
6909         uint64_t hena = 0;
6910         int i;
6911
6912         if (!flags)
6913                 return hena;
6914
6915         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6916                 if (flags & (1ULL << i))
6917                         hena |= adapter->pctypes_tbl[i];
6918         }
6919
6920         return hena;
6921 }
6922
6923 /* Parse the hash enable flags */
6924 uint64_t
6925 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6926 {
6927         uint64_t rss_hf = 0;
6928
6929         if (!flags)
6930                 return rss_hf;
6931         int i;
6932
6933         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6934                 if (flags & adapter->pctypes_tbl[i])
6935                         rss_hf |= (1ULL << i);
6936         }
6937         return rss_hf;
6938 }
6939
6940 /* Disable RSS */
6941 static void
6942 i40e_pf_disable_rss(struct i40e_pf *pf)
6943 {
6944         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6945
6946         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6947         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6948         I40E_WRITE_FLUSH(hw);
6949 }
6950
6951 static int
6952 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6953 {
6954         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6955         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6956         int ret = 0;
6957
6958         if (!key || key_len == 0) {
6959                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6960                 return 0;
6961         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6962                 sizeof(uint32_t)) {
6963                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6964                 return -EINVAL;
6965         }
6966
6967         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6968                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6969                         (struct i40e_aqc_get_set_rss_key_data *)key;
6970
6971                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6972                 if (ret)
6973                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6974         } else {
6975                 uint32_t *hash_key = (uint32_t *)key;
6976                 uint16_t i;
6977
6978                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6979                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6980                 I40E_WRITE_FLUSH(hw);
6981         }
6982
6983         return ret;
6984 }
6985
6986 static int
6987 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6988 {
6989         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6990         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6991         int ret;
6992
6993         if (!key || !key_len)
6994                 return -EINVAL;
6995
6996         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6997                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6998                         (struct i40e_aqc_get_set_rss_key_data *)key);
6999                 if (ret) {
7000                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7001                         return ret;
7002                 }
7003         } else {
7004                 uint32_t *key_dw = (uint32_t *)key;
7005                 uint16_t i;
7006
7007                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7008                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
7009         }
7010         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
7011
7012         return 0;
7013 }
7014
7015 static int
7016 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7017 {
7018         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7019         uint64_t hena;
7020         int ret;
7021
7022         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7023                                rss_conf->rss_key_len);
7024         if (ret)
7025                 return ret;
7026
7027         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7028         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7029         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7030         I40E_WRITE_FLUSH(hw);
7031
7032         return 0;
7033 }
7034
7035 static int
7036 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7037                          struct rte_eth_rss_conf *rss_conf)
7038 {
7039         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7040         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7041         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7042         uint64_t hena;
7043
7044         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7045         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7046
7047         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7048                 if (rss_hf != 0) /* Enable RSS */
7049                         return -EINVAL;
7050                 return 0; /* Nothing to do */
7051         }
7052         /* RSS enabled */
7053         if (rss_hf == 0) /* Disable RSS */
7054                 return -EINVAL;
7055
7056         return i40e_hw_rss_hash_set(pf, rss_conf);
7057 }
7058
7059 static int
7060 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7061                            struct rte_eth_rss_conf *rss_conf)
7062 {
7063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7064         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7065         uint64_t hena;
7066
7067         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7068                          &rss_conf->rss_key_len);
7069
7070         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7071         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7072         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7073
7074         return 0;
7075 }
7076
7077 static int
7078 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7079 {
7080         switch (filter_type) {
7081         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7082                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7083                 break;
7084         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7085                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7086                 break;
7087         case RTE_TUNNEL_FILTER_IMAC_TENID:
7088                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7089                 break;
7090         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7091                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7092                 break;
7093         case ETH_TUNNEL_FILTER_IMAC:
7094                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7095                 break;
7096         case ETH_TUNNEL_FILTER_OIP:
7097                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7098                 break;
7099         case ETH_TUNNEL_FILTER_IIP:
7100                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7101                 break;
7102         default:
7103                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7104                 return -EINVAL;
7105         }
7106
7107         return 0;
7108 }
7109
7110 /* Convert tunnel filter structure */
7111 static int
7112 i40e_tunnel_filter_convert(
7113         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7114         struct i40e_tunnel_filter *tunnel_filter)
7115 {
7116         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7117                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7118         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7119                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7120         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7121         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7122              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7123             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7124                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7125         else
7126                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7127         tunnel_filter->input.flags = cld_filter->element.flags;
7128         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7129         tunnel_filter->queue = cld_filter->element.queue_number;
7130         rte_memcpy(tunnel_filter->input.general_fields,
7131                    cld_filter->general_fields,
7132                    sizeof(cld_filter->general_fields));
7133
7134         return 0;
7135 }
7136
7137 /* Check if there exists the tunnel filter */
7138 struct i40e_tunnel_filter *
7139 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7140                              const struct i40e_tunnel_filter_input *input)
7141 {
7142         int ret;
7143
7144         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7145         if (ret < 0)
7146                 return NULL;
7147
7148         return tunnel_rule->hash_map[ret];
7149 }
7150
7151 /* Add a tunnel filter into the SW list */
7152 static int
7153 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7154                              struct i40e_tunnel_filter *tunnel_filter)
7155 {
7156         struct i40e_tunnel_rule *rule = &pf->tunnel;
7157         int ret;
7158
7159         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7160         if (ret < 0) {
7161                 PMD_DRV_LOG(ERR,
7162                             "Failed to insert tunnel filter to hash table %d!",
7163                             ret);
7164                 return ret;
7165         }
7166         rule->hash_map[ret] = tunnel_filter;
7167
7168         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7169
7170         return 0;
7171 }
7172
7173 /* Delete a tunnel filter from the SW list */
7174 int
7175 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7176                           struct i40e_tunnel_filter_input *input)
7177 {
7178         struct i40e_tunnel_rule *rule = &pf->tunnel;
7179         struct i40e_tunnel_filter *tunnel_filter;
7180         int ret;
7181
7182         ret = rte_hash_del_key(rule->hash_table, input);
7183         if (ret < 0) {
7184                 PMD_DRV_LOG(ERR,
7185                             "Failed to delete tunnel filter to hash table %d!",
7186                             ret);
7187                 return ret;
7188         }
7189         tunnel_filter = rule->hash_map[ret];
7190         rule->hash_map[ret] = NULL;
7191
7192         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7193         rte_free(tunnel_filter);
7194
7195         return 0;
7196 }
7197
7198 int
7199 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7200                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7201                         uint8_t add)
7202 {
7203         uint16_t ip_type;
7204         uint32_t ipv4_addr, ipv4_addr_le;
7205         uint8_t i, tun_type = 0;
7206         /* internal varialbe to convert ipv6 byte order */
7207         uint32_t convert_ipv6[4];
7208         int val, ret = 0;
7209         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7210         struct i40e_vsi *vsi = pf->main_vsi;
7211         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7212         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7213         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7214         struct i40e_tunnel_filter *tunnel, *node;
7215         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7216
7217         cld_filter = rte_zmalloc("tunnel_filter",
7218                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7219         0);
7220
7221         if (NULL == cld_filter) {
7222                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7223                 return -ENOMEM;
7224         }
7225         pfilter = cld_filter;
7226
7227         ether_addr_copy(&tunnel_filter->outer_mac,
7228                         (struct ether_addr *)&pfilter->element.outer_mac);
7229         ether_addr_copy(&tunnel_filter->inner_mac,
7230                         (struct ether_addr *)&pfilter->element.inner_mac);
7231
7232         pfilter->element.inner_vlan =
7233                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7234         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7235                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7236                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7237                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7238                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7239                                 &ipv4_addr_le,
7240                                 sizeof(pfilter->element.ipaddr.v4.data));
7241         } else {
7242                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7243                 for (i = 0; i < 4; i++) {
7244                         convert_ipv6[i] =
7245                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7246                 }
7247                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7248                            &convert_ipv6,
7249                            sizeof(pfilter->element.ipaddr.v6.data));
7250         }
7251
7252         /* check tunneled type */
7253         switch (tunnel_filter->tunnel_type) {
7254         case RTE_TUNNEL_TYPE_VXLAN:
7255                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7256                 break;
7257         case RTE_TUNNEL_TYPE_NVGRE:
7258                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7259                 break;
7260         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7261                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7262                 break;
7263         default:
7264                 /* Other tunnel types is not supported. */
7265                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7266                 rte_free(cld_filter);
7267                 return -EINVAL;
7268         }
7269
7270         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7271                                        &pfilter->element.flags);
7272         if (val < 0) {
7273                 rte_free(cld_filter);
7274                 return -EINVAL;
7275         }
7276
7277         pfilter->element.flags |= rte_cpu_to_le_16(
7278                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7279                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7280         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7281         pfilter->element.queue_number =
7282                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7283
7284         /* Check if there is the filter in SW list */
7285         memset(&check_filter, 0, sizeof(check_filter));
7286         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7287         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7288         if (add && node) {
7289                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7290                 rte_free(cld_filter);
7291                 return -EINVAL;
7292         }
7293
7294         if (!add && !node) {
7295                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7296                 rte_free(cld_filter);
7297                 return -EINVAL;
7298         }
7299
7300         if (add) {
7301                 ret = i40e_aq_add_cloud_filters(hw,
7302                                         vsi->seid, &cld_filter->element, 1);
7303                 if (ret < 0) {
7304                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7305                         rte_free(cld_filter);
7306                         return -ENOTSUP;
7307                 }
7308                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7309                 if (tunnel == NULL) {
7310                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7311                         rte_free(cld_filter);
7312                         return -ENOMEM;
7313                 }
7314
7315                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7316                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7317                 if (ret < 0)
7318                         rte_free(tunnel);
7319         } else {
7320                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7321                                                    &cld_filter->element, 1);
7322                 if (ret < 0) {
7323                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7324                         rte_free(cld_filter);
7325                         return -ENOTSUP;
7326                 }
7327                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7328         }
7329
7330         rte_free(cld_filter);
7331         return ret;
7332 }
7333
7334 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7335 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7336 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7337 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7338 #define I40E_TR_GRE_KEY_MASK                    0x400
7339 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7340 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7341
7342 static enum
7343 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7344 {
7345         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7346         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7347         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7348         enum i40e_status_code status = I40E_SUCCESS;
7349
7350         if (pf->support_multi_driver) {
7351                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7352                 return I40E_NOT_SUPPORTED;
7353         }
7354
7355         memset(&filter_replace, 0,
7356                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7357         memset(&filter_replace_buf, 0,
7358                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7359
7360         /* create L1 filter */
7361         filter_replace.old_filter_type =
7362                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7363         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7364         filter_replace.tr_bit = 0;
7365
7366         /* Prepare the buffer, 3 entries */
7367         filter_replace_buf.data[0] =
7368                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7369         filter_replace_buf.data[0] |=
7370                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7371         filter_replace_buf.data[2] = 0xFF;
7372         filter_replace_buf.data[3] = 0xFF;
7373         filter_replace_buf.data[4] =
7374                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7375         filter_replace_buf.data[4] |=
7376                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7377         filter_replace_buf.data[7] = 0xF0;
7378         filter_replace_buf.data[8]
7379                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7380         filter_replace_buf.data[8] |=
7381                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7382         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7383                 I40E_TR_GENEVE_KEY_MASK |
7384                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7385         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7386                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7387                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7388
7389         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7390                                                &filter_replace_buf);
7391         if (!status)
7392                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7393         return status;
7394 }
7395
7396 static enum
7397 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7398 {
7399         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7400         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7401         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7402         enum i40e_status_code status = I40E_SUCCESS;
7403
7404         if (pf->support_multi_driver) {
7405                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7406                 return I40E_NOT_SUPPORTED;
7407         }
7408
7409         /* For MPLSoUDP */
7410         memset(&filter_replace, 0,
7411                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7412         memset(&filter_replace_buf, 0,
7413                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7414         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7415                 I40E_AQC_MIRROR_CLOUD_FILTER;
7416         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7417         filter_replace.new_filter_type =
7418                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7419         /* Prepare the buffer, 2 entries */
7420         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7421         filter_replace_buf.data[0] |=
7422                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7423         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7424         filter_replace_buf.data[4] |=
7425                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7426         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7427                                                &filter_replace_buf);
7428         if (status < 0)
7429                 return status;
7430
7431         /* For MPLSoGRE */
7432         memset(&filter_replace, 0,
7433                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7434         memset(&filter_replace_buf, 0,
7435                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7436
7437         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7438                 I40E_AQC_MIRROR_CLOUD_FILTER;
7439         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7440         filter_replace.new_filter_type =
7441                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7442         /* Prepare the buffer, 2 entries */
7443         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7444         filter_replace_buf.data[0] |=
7445                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7446         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7447         filter_replace_buf.data[4] |=
7448                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7449
7450         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7451                                                &filter_replace_buf);
7452         if (!status)
7453                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7454         return status;
7455 }
7456
7457 static enum i40e_status_code
7458 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7459 {
7460         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7461         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7462         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7463         enum i40e_status_code status = I40E_SUCCESS;
7464
7465         if (pf->support_multi_driver) {
7466                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7467                 return I40E_NOT_SUPPORTED;
7468         }
7469
7470         /* For GTP-C */
7471         memset(&filter_replace, 0,
7472                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7473         memset(&filter_replace_buf, 0,
7474                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7475         /* create L1 filter */
7476         filter_replace.old_filter_type =
7477                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7478         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7479         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7480                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7481         /* Prepare the buffer, 2 entries */
7482         filter_replace_buf.data[0] =
7483                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7484         filter_replace_buf.data[0] |=
7485                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7486         filter_replace_buf.data[2] = 0xFF;
7487         filter_replace_buf.data[3] = 0xFF;
7488         filter_replace_buf.data[4] =
7489                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7490         filter_replace_buf.data[4] |=
7491                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7492         filter_replace_buf.data[6] = 0xFF;
7493         filter_replace_buf.data[7] = 0xFF;
7494         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7495                                                &filter_replace_buf);
7496         if (status < 0)
7497                 return status;
7498         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7499                     "cloud l1 type is changed from 0x%x to 0x%x",
7500                     filter_replace.old_filter_type,
7501                     filter_replace.new_filter_type);
7502
7503         /* for GTP-U */
7504         memset(&filter_replace, 0,
7505                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7506         memset(&filter_replace_buf, 0,
7507                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7508         /* create L1 filter */
7509         filter_replace.old_filter_type =
7510                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7511         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7512         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7513                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7514         /* Prepare the buffer, 2 entries */
7515         filter_replace_buf.data[0] =
7516                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7517         filter_replace_buf.data[0] |=
7518                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7519         filter_replace_buf.data[2] = 0xFF;
7520         filter_replace_buf.data[3] = 0xFF;
7521         filter_replace_buf.data[4] =
7522                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7523         filter_replace_buf.data[4] |=
7524                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7525         filter_replace_buf.data[6] = 0xFF;
7526         filter_replace_buf.data[7] = 0xFF;
7527
7528         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7529                                                &filter_replace_buf);
7530         if (!status) {
7531                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7532                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7533                             "cloud l1 type is changed from 0x%x to 0x%x",
7534                             filter_replace.old_filter_type,
7535                             filter_replace.new_filter_type);
7536         }
7537         return status;
7538 }
7539
7540 static enum
7541 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7542 {
7543         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7544         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7545         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7546         enum i40e_status_code status = I40E_SUCCESS;
7547
7548         if (pf->support_multi_driver) {
7549                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7550                 return I40E_NOT_SUPPORTED;
7551         }
7552
7553         /* for GTP-C */
7554         memset(&filter_replace, 0,
7555                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7556         memset(&filter_replace_buf, 0,
7557                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7558         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7559         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7560         filter_replace.new_filter_type =
7561                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7562         /* Prepare the buffer, 2 entries */
7563         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7564         filter_replace_buf.data[0] |=
7565                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7566         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7567         filter_replace_buf.data[4] |=
7568                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7569         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7570                                                &filter_replace_buf);
7571         if (status < 0)
7572                 return status;
7573         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7574                     "cloud filter type is changed from 0x%x to 0x%x",
7575                     filter_replace.old_filter_type,
7576                     filter_replace.new_filter_type);
7577
7578         /* for GTP-U */
7579         memset(&filter_replace, 0,
7580                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7581         memset(&filter_replace_buf, 0,
7582                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7583         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7584         filter_replace.old_filter_type =
7585                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7586         filter_replace.new_filter_type =
7587                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7588         /* Prepare the buffer, 2 entries */
7589         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7590         filter_replace_buf.data[0] |=
7591                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7592         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7593         filter_replace_buf.data[4] |=
7594                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7595
7596         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7597                                                &filter_replace_buf);
7598         if (!status) {
7599                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7600                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7601                             "cloud filter type is changed from 0x%x to 0x%x",
7602                             filter_replace.old_filter_type,
7603                             filter_replace.new_filter_type);
7604         }
7605         return status;
7606 }
7607
7608 int
7609 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7610                       struct i40e_tunnel_filter_conf *tunnel_filter,
7611                       uint8_t add)
7612 {
7613         uint16_t ip_type;
7614         uint32_t ipv4_addr, ipv4_addr_le;
7615         uint8_t i, tun_type = 0;
7616         /* internal variable to convert ipv6 byte order */
7617         uint32_t convert_ipv6[4];
7618         int val, ret = 0;
7619         struct i40e_pf_vf *vf = NULL;
7620         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7621         struct i40e_vsi *vsi;
7622         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7623         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7624         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7625         struct i40e_tunnel_filter *tunnel, *node;
7626         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7627         uint32_t teid_le;
7628         bool big_buffer = 0;
7629
7630         cld_filter = rte_zmalloc("tunnel_filter",
7631                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7632                          0);
7633
7634         if (cld_filter == NULL) {
7635                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7636                 return -ENOMEM;
7637         }
7638         pfilter = cld_filter;
7639
7640         ether_addr_copy(&tunnel_filter->outer_mac,
7641                         (struct ether_addr *)&pfilter->element.outer_mac);
7642         ether_addr_copy(&tunnel_filter->inner_mac,
7643                         (struct ether_addr *)&pfilter->element.inner_mac);
7644
7645         pfilter->element.inner_vlan =
7646                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7647         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7648                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7649                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7650                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7651                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7652                                 &ipv4_addr_le,
7653                                 sizeof(pfilter->element.ipaddr.v4.data));
7654         } else {
7655                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7656                 for (i = 0; i < 4; i++) {
7657                         convert_ipv6[i] =
7658                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7659                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7660                 }
7661                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7662                            &convert_ipv6,
7663                            sizeof(pfilter->element.ipaddr.v6.data));
7664         }
7665
7666         /* check tunneled type */
7667         switch (tunnel_filter->tunnel_type) {
7668         case I40E_TUNNEL_TYPE_VXLAN:
7669                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7670                 break;
7671         case I40E_TUNNEL_TYPE_NVGRE:
7672                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7673                 break;
7674         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7675                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7676                 break;
7677         case I40E_TUNNEL_TYPE_MPLSoUDP:
7678                 if (!pf->mpls_replace_flag) {
7679                         i40e_replace_mpls_l1_filter(pf);
7680                         i40e_replace_mpls_cloud_filter(pf);
7681                         pf->mpls_replace_flag = 1;
7682                 }
7683                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7684                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7685                         teid_le >> 4;
7686                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7687                         (teid_le & 0xF) << 12;
7688                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7689                         0x40;
7690                 big_buffer = 1;
7691                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7692                 break;
7693         case I40E_TUNNEL_TYPE_MPLSoGRE:
7694                 if (!pf->mpls_replace_flag) {
7695                         i40e_replace_mpls_l1_filter(pf);
7696                         i40e_replace_mpls_cloud_filter(pf);
7697                         pf->mpls_replace_flag = 1;
7698                 }
7699                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7700                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7701                         teid_le >> 4;
7702                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7703                         (teid_le & 0xF) << 12;
7704                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7705                         0x0;
7706                 big_buffer = 1;
7707                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7708                 break;
7709         case I40E_TUNNEL_TYPE_GTPC:
7710                 if (!pf->gtp_replace_flag) {
7711                         i40e_replace_gtp_l1_filter(pf);
7712                         i40e_replace_gtp_cloud_filter(pf);
7713                         pf->gtp_replace_flag = 1;
7714                 }
7715                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7716                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7717                         (teid_le >> 16) & 0xFFFF;
7718                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7719                         teid_le & 0xFFFF;
7720                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7721                         0x0;
7722                 big_buffer = 1;
7723                 break;
7724         case I40E_TUNNEL_TYPE_GTPU:
7725                 if (!pf->gtp_replace_flag) {
7726                         i40e_replace_gtp_l1_filter(pf);
7727                         i40e_replace_gtp_cloud_filter(pf);
7728                         pf->gtp_replace_flag = 1;
7729                 }
7730                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7731                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7732                         (teid_le >> 16) & 0xFFFF;
7733                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7734                         teid_le & 0xFFFF;
7735                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7736                         0x0;
7737                 big_buffer = 1;
7738                 break;
7739         case I40E_TUNNEL_TYPE_QINQ:
7740                 if (!pf->qinq_replace_flag) {
7741                         ret = i40e_cloud_filter_qinq_create(pf);
7742                         if (ret < 0)
7743                                 PMD_DRV_LOG(DEBUG,
7744                                             "QinQ tunnel filter already created.");
7745                         pf->qinq_replace_flag = 1;
7746                 }
7747                 /*      Add in the General fields the values of
7748                  *      the Outer and Inner VLAN
7749                  *      Big Buffer should be set, see changes in
7750                  *      i40e_aq_add_cloud_filters
7751                  */
7752                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7753                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7754                 big_buffer = 1;
7755                 break;
7756         default:
7757                 /* Other tunnel types is not supported. */
7758                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7759                 rte_free(cld_filter);
7760                 return -EINVAL;
7761         }
7762
7763         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7764                 pfilter->element.flags =
7765                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7766         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7767                 pfilter->element.flags =
7768                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7769         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7770                 pfilter->element.flags =
7771                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7772         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7773                 pfilter->element.flags =
7774                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7775         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7776                 pfilter->element.flags |=
7777                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7778         else {
7779                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7780                                                 &pfilter->element.flags);
7781                 if (val < 0) {
7782                         rte_free(cld_filter);
7783                         return -EINVAL;
7784                 }
7785         }
7786
7787         pfilter->element.flags |= rte_cpu_to_le_16(
7788                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7789                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7790         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7791         pfilter->element.queue_number =
7792                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7793
7794         if (!tunnel_filter->is_to_vf)
7795                 vsi = pf->main_vsi;
7796         else {
7797                 if (tunnel_filter->vf_id >= pf->vf_num) {
7798                         PMD_DRV_LOG(ERR, "Invalid argument.");
7799                         rte_free(cld_filter);
7800                         return -EINVAL;
7801                 }
7802                 vf = &pf->vfs[tunnel_filter->vf_id];
7803                 vsi = vf->vsi;
7804         }
7805
7806         /* Check if there is the filter in SW list */
7807         memset(&check_filter, 0, sizeof(check_filter));
7808         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7809         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7810         check_filter.vf_id = tunnel_filter->vf_id;
7811         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7812         if (add && node) {
7813                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7814                 rte_free(cld_filter);
7815                 return -EINVAL;
7816         }
7817
7818         if (!add && !node) {
7819                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7820                 rte_free(cld_filter);
7821                 return -EINVAL;
7822         }
7823
7824         if (add) {
7825                 if (big_buffer)
7826                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7827                                                    vsi->seid, cld_filter, 1);
7828                 else
7829                         ret = i40e_aq_add_cloud_filters(hw,
7830                                         vsi->seid, &cld_filter->element, 1);
7831                 if (ret < 0) {
7832                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7833                         rte_free(cld_filter);
7834                         return -ENOTSUP;
7835                 }
7836                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7837                 if (tunnel == NULL) {
7838                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7839                         rte_free(cld_filter);
7840                         return -ENOMEM;
7841                 }
7842
7843                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7844                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7845                 if (ret < 0)
7846                         rte_free(tunnel);
7847         } else {
7848                 if (big_buffer)
7849                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7850                                 hw, vsi->seid, cld_filter, 1);
7851                 else
7852                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7853                                                    &cld_filter->element, 1);
7854                 if (ret < 0) {
7855                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7856                         rte_free(cld_filter);
7857                         return -ENOTSUP;
7858                 }
7859                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7860         }
7861
7862         rte_free(cld_filter);
7863         return ret;
7864 }
7865
7866 static int
7867 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7868 {
7869         uint8_t i;
7870
7871         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7872                 if (pf->vxlan_ports[i] == port)
7873                         return i;
7874         }
7875
7876         return -1;
7877 }
7878
7879 static int
7880 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7881 {
7882         int  idx, ret;
7883         uint8_t filter_idx;
7884         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7885
7886         idx = i40e_get_vxlan_port_idx(pf, port);
7887
7888         /* Check if port already exists */
7889         if (idx >= 0) {
7890                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7891                 return -EINVAL;
7892         }
7893
7894         /* Now check if there is space to add the new port */
7895         idx = i40e_get_vxlan_port_idx(pf, 0);
7896         if (idx < 0) {
7897                 PMD_DRV_LOG(ERR,
7898                         "Maximum number of UDP ports reached, not adding port %d",
7899                         port);
7900                 return -ENOSPC;
7901         }
7902
7903         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7904                                         &filter_idx, NULL);
7905         if (ret < 0) {
7906                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7907                 return -1;
7908         }
7909
7910         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7911                          port,  filter_idx);
7912
7913         /* New port: add it and mark its index in the bitmap */
7914         pf->vxlan_ports[idx] = port;
7915         pf->vxlan_bitmap |= (1 << idx);
7916
7917         if (!(pf->flags & I40E_FLAG_VXLAN))
7918                 pf->flags |= I40E_FLAG_VXLAN;
7919
7920         return 0;
7921 }
7922
7923 static int
7924 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7925 {
7926         int idx;
7927         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7928
7929         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7930                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7931                 return -EINVAL;
7932         }
7933
7934         idx = i40e_get_vxlan_port_idx(pf, port);
7935
7936         if (idx < 0) {
7937                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7938                 return -EINVAL;
7939         }
7940
7941         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7942                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7943                 return -1;
7944         }
7945
7946         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7947                         port, idx);
7948
7949         pf->vxlan_ports[idx] = 0;
7950         pf->vxlan_bitmap &= ~(1 << idx);
7951
7952         if (!pf->vxlan_bitmap)
7953                 pf->flags &= ~I40E_FLAG_VXLAN;
7954
7955         return 0;
7956 }
7957
7958 /* Add UDP tunneling port */
7959 static int
7960 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7961                              struct rte_eth_udp_tunnel *udp_tunnel)
7962 {
7963         int ret = 0;
7964         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7965
7966         if (udp_tunnel == NULL)
7967                 return -EINVAL;
7968
7969         switch (udp_tunnel->prot_type) {
7970         case RTE_TUNNEL_TYPE_VXLAN:
7971                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7972                 break;
7973
7974         case RTE_TUNNEL_TYPE_GENEVE:
7975         case RTE_TUNNEL_TYPE_TEREDO:
7976                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7977                 ret = -1;
7978                 break;
7979
7980         default:
7981                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7982                 ret = -1;
7983                 break;
7984         }
7985
7986         return ret;
7987 }
7988
7989 /* Remove UDP tunneling port */
7990 static int
7991 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7992                              struct rte_eth_udp_tunnel *udp_tunnel)
7993 {
7994         int ret = 0;
7995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7996
7997         if (udp_tunnel == NULL)
7998                 return -EINVAL;
7999
8000         switch (udp_tunnel->prot_type) {
8001         case RTE_TUNNEL_TYPE_VXLAN:
8002                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8003                 break;
8004         case RTE_TUNNEL_TYPE_GENEVE:
8005         case RTE_TUNNEL_TYPE_TEREDO:
8006                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8007                 ret = -1;
8008                 break;
8009         default:
8010                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8011                 ret = -1;
8012                 break;
8013         }
8014
8015         return ret;
8016 }
8017
8018 /* Calculate the maximum number of contiguous PF queues that are configured */
8019 static int
8020 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8021 {
8022         struct rte_eth_dev_data *data = pf->dev_data;
8023         int i, num;
8024         struct i40e_rx_queue *rxq;
8025
8026         num = 0;
8027         for (i = 0; i < pf->lan_nb_qps; i++) {
8028                 rxq = data->rx_queues[i];
8029                 if (rxq && rxq->q_set)
8030                         num++;
8031                 else
8032                         break;
8033         }
8034
8035         return num;
8036 }
8037
8038 /* Configure RSS */
8039 static int
8040 i40e_pf_config_rss(struct i40e_pf *pf)
8041 {
8042         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8043         struct rte_eth_rss_conf rss_conf;
8044         uint32_t i, lut = 0;
8045         uint16_t j, num;
8046
8047         /*
8048          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8049          * It's necessary to calculate the actual PF queues that are configured.
8050          */
8051         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8052                 num = i40e_pf_calc_configured_queues_num(pf);
8053         else
8054                 num = pf->dev_data->nb_rx_queues;
8055
8056         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8057         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8058                         num);
8059
8060         if (num == 0) {
8061                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8062                 return -ENOTSUP;
8063         }
8064
8065         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8066                 if (j == num)
8067                         j = 0;
8068                 lut = (lut << 8) | (j & ((0x1 <<
8069                         hw->func_caps.rss_table_entry_width) - 1));
8070                 if ((i & 3) == 3)
8071                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8072         }
8073
8074         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8075         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8076                 i40e_pf_disable_rss(pf);
8077                 return 0;
8078         }
8079         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8080                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8081                 /* Random default keys */
8082                 static uint32_t rss_key_default[] = {0x6b793944,
8083                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8084                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8085                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8086
8087                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8088                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8089                                                         sizeof(uint32_t);
8090         }
8091
8092         return i40e_hw_rss_hash_set(pf, &rss_conf);
8093 }
8094
8095 static int
8096 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8097                                struct rte_eth_tunnel_filter_conf *filter)
8098 {
8099         if (pf == NULL || filter == NULL) {
8100                 PMD_DRV_LOG(ERR, "Invalid parameter");
8101                 return -EINVAL;
8102         }
8103
8104         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8105                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8106                 return -EINVAL;
8107         }
8108
8109         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8110                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8111                 return -EINVAL;
8112         }
8113
8114         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8115                 (is_zero_ether_addr(&filter->outer_mac))) {
8116                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8117                 return -EINVAL;
8118         }
8119
8120         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8121                 (is_zero_ether_addr(&filter->inner_mac))) {
8122                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8123                 return -EINVAL;
8124         }
8125
8126         return 0;
8127 }
8128
8129 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8130 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8131 static int
8132 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8133 {
8134         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8135         uint32_t val, reg;
8136         int ret = -EINVAL;
8137
8138         if (pf->support_multi_driver) {
8139                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8140                 return -ENOTSUP;
8141         }
8142
8143         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8144         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8145
8146         if (len == 3) {
8147                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8148         } else if (len == 4) {
8149                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8150         } else {
8151                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8152                 return ret;
8153         }
8154
8155         if (reg != val) {
8156                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8157                                                    reg, NULL);
8158                 if (ret != 0)
8159                         return ret;
8160                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8161                             "with value 0x%08x",
8162                             I40E_GL_PRS_FVBM(2), reg);
8163                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8164         } else {
8165                 ret = 0;
8166         }
8167         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8168                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8169
8170         return ret;
8171 }
8172
8173 static int
8174 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8175 {
8176         int ret = -EINVAL;
8177
8178         if (!hw || !cfg)
8179                 return -EINVAL;
8180
8181         switch (cfg->cfg_type) {
8182         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8183                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8184                 break;
8185         default:
8186                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8187                 break;
8188         }
8189
8190         return ret;
8191 }
8192
8193 static int
8194 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8195                                enum rte_filter_op filter_op,
8196                                void *arg)
8197 {
8198         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8199         int ret = I40E_ERR_PARAM;
8200
8201         switch (filter_op) {
8202         case RTE_ETH_FILTER_SET:
8203                 ret = i40e_dev_global_config_set(hw,
8204                         (struct rte_eth_global_cfg *)arg);
8205                 break;
8206         default:
8207                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8208                 break;
8209         }
8210
8211         return ret;
8212 }
8213
8214 static int
8215 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8216                           enum rte_filter_op filter_op,
8217                           void *arg)
8218 {
8219         struct rte_eth_tunnel_filter_conf *filter;
8220         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8221         int ret = I40E_SUCCESS;
8222
8223         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8224
8225         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8226                 return I40E_ERR_PARAM;
8227
8228         switch (filter_op) {
8229         case RTE_ETH_FILTER_NOP:
8230                 if (!(pf->flags & I40E_FLAG_VXLAN))
8231                         ret = I40E_NOT_SUPPORTED;
8232                 break;
8233         case RTE_ETH_FILTER_ADD:
8234                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8235                 break;
8236         case RTE_ETH_FILTER_DELETE:
8237                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8238                 break;
8239         default:
8240                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8241                 ret = I40E_ERR_PARAM;
8242                 break;
8243         }
8244
8245         return ret;
8246 }
8247
8248 static int
8249 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8250 {
8251         int ret = 0;
8252         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8253
8254         /* RSS setup */
8255         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8256                 ret = i40e_pf_config_rss(pf);
8257         else
8258                 i40e_pf_disable_rss(pf);
8259
8260         return ret;
8261 }
8262
8263 /* Get the symmetric hash enable configurations per port */
8264 static void
8265 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8266 {
8267         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8268
8269         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8270 }
8271
8272 /* Set the symmetric hash enable configurations per port */
8273 static void
8274 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8275 {
8276         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8277
8278         if (enable > 0) {
8279                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8280                         PMD_DRV_LOG(INFO,
8281                                 "Symmetric hash has already been enabled");
8282                         return;
8283                 }
8284                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8285         } else {
8286                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8287                         PMD_DRV_LOG(INFO,
8288                                 "Symmetric hash has already been disabled");
8289                         return;
8290                 }
8291                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8292         }
8293         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8294         I40E_WRITE_FLUSH(hw);
8295 }
8296
8297 /*
8298  * Get global configurations of hash function type and symmetric hash enable
8299  * per flow type (pctype). Note that global configuration means it affects all
8300  * the ports on the same NIC.
8301  */
8302 static int
8303 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8304                                    struct rte_eth_hash_global_conf *g_cfg)
8305 {
8306         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8307         uint32_t reg;
8308         uint16_t i, j;
8309
8310         memset(g_cfg, 0, sizeof(*g_cfg));
8311         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8312         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8313                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8314         else
8315                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8316         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8317                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8318
8319         /*
8320          * We work only with lowest 32 bits which is not correct, but to work
8321          * properly the valid_bit_mask size should be increased up to 64 bits
8322          * and this will brake ABI. This modification will be done in next
8323          * release
8324          */
8325         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8326
8327         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8328                 if (!adapter->pctypes_tbl[i])
8329                         continue;
8330                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8331                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8332                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8333                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8334                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8335                                         g_cfg->sym_hash_enable_mask[0] |=
8336                                                                 (1UL << i);
8337                                 }
8338                         }
8339                 }
8340         }
8341
8342         return 0;
8343 }
8344
8345 static int
8346 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8347                               const struct rte_eth_hash_global_conf *g_cfg)
8348 {
8349         uint32_t i;
8350         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8351
8352         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8353                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8354                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8355                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8356                                                 g_cfg->hash_func);
8357                 return -EINVAL;
8358         }
8359
8360         /*
8361          * As i40e supports less than 32 flow types, only first 32 bits need to
8362          * be checked.
8363          */
8364         mask0 = g_cfg->valid_bit_mask[0];
8365         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8366                 if (i == 0) {
8367                         /* Check if any unsupported flow type configured */
8368                         if ((mask0 | i40e_mask) ^ i40e_mask)
8369                                 goto mask_err;
8370                 } else {
8371                         if (g_cfg->valid_bit_mask[i])
8372                                 goto mask_err;
8373                 }
8374         }
8375
8376         return 0;
8377
8378 mask_err:
8379         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8380
8381         return -EINVAL;
8382 }
8383
8384 /*
8385  * Set global configurations of hash function type and symmetric hash enable
8386  * per flow type (pctype). Note any modifying global configuration will affect
8387  * all the ports on the same NIC.
8388  */
8389 static int
8390 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8391                                    struct rte_eth_hash_global_conf *g_cfg)
8392 {
8393         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8394         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8395         int ret;
8396         uint16_t i, j;
8397         uint32_t reg;
8398         /*
8399          * We work only with lowest 32 bits which is not correct, but to work
8400          * properly the valid_bit_mask size should be increased up to 64 bits
8401          * and this will brake ABI. This modification will be done in next
8402          * release
8403          */
8404         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8405                                         (uint32_t)adapter->flow_types_mask;
8406
8407         if (pf->support_multi_driver) {
8408                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8409                 return -ENOTSUP;
8410         }
8411
8412         /* Check the input parameters */
8413         ret = i40e_hash_global_config_check(adapter, g_cfg);
8414         if (ret < 0)
8415                 return ret;
8416
8417         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8418                 if (mask0 & (1UL << i)) {
8419                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8420                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8421
8422                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8423                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8424                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8425                                         i40e_write_global_rx_ctl(hw,
8426                                                           I40E_GLQF_HSYM(j),
8427                                                           reg);
8428                         }
8429                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8430                 }
8431         }
8432
8433         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8434         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8435                 /* Toeplitz */
8436                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8437                         PMD_DRV_LOG(DEBUG,
8438                                 "Hash function already set to Toeplitz");
8439                         goto out;
8440                 }
8441                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8442         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8443                 /* Simple XOR */
8444                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8445                         PMD_DRV_LOG(DEBUG,
8446                                 "Hash function already set to Simple XOR");
8447                         goto out;
8448                 }
8449                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8450         } else
8451                 /* Use the default, and keep it as it is */
8452                 goto out;
8453
8454         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8455         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8456
8457 out:
8458         I40E_WRITE_FLUSH(hw);
8459
8460         return 0;
8461 }
8462
8463 /**
8464  * Valid input sets for hash and flow director filters per PCTYPE
8465  */
8466 static uint64_t
8467 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8468                 enum rte_filter_type filter)
8469 {
8470         uint64_t valid;
8471
8472         static const uint64_t valid_hash_inset_table[] = {
8473                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8474                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8475                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8476                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8477                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8478                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8479                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8480                         I40E_INSET_FLEX_PAYLOAD,
8481                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8482                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8483                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8484                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8485                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8486                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8487                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8488                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8489                         I40E_INSET_FLEX_PAYLOAD,
8490                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8491                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8492                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8493                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8494                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8495                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8496                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8497                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8498                         I40E_INSET_FLEX_PAYLOAD,
8499                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8500                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8501                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8502                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8503                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8504                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8505                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8506                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8507                         I40E_INSET_FLEX_PAYLOAD,
8508                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8509                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8510                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8511                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8512                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8513                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8514                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8515                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8516                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8517                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8518                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8519                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8520                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8521                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8522                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8523                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8524                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8525                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8526                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8527                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8528                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8529                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8530                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8531                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8532                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8533                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8534                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8535                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8536                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8537                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8538                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8539                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8540                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8541                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8542                         I40E_INSET_FLEX_PAYLOAD,
8543                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8544                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8545                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8546                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8547                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8548                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8549                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8550                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8551                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8552                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8553                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8554                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8555                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8556                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8557                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8558                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8559                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8560                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8561                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8562                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8563                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8564                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8565                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8566                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8567                         I40E_INSET_FLEX_PAYLOAD,
8568                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8569                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8570                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8571                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8572                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8573                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8574                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8575                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8576                         I40E_INSET_FLEX_PAYLOAD,
8577                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8578                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8579                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8580                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8581                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8582                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8583                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8584                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8585                         I40E_INSET_FLEX_PAYLOAD,
8586                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8587                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8588                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8589                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8590                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8591                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8592                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8593                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8594                         I40E_INSET_FLEX_PAYLOAD,
8595                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8596                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8597                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8598                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8599                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8600                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8601                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8602                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8603                         I40E_INSET_FLEX_PAYLOAD,
8604                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8605                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8606                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8607                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8608                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8609                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8610                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8611                         I40E_INSET_FLEX_PAYLOAD,
8612                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8613                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8614                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8615                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8616                         I40E_INSET_FLEX_PAYLOAD,
8617         };
8618
8619         /**
8620          * Flow director supports only fields defined in
8621          * union rte_eth_fdir_flow.
8622          */
8623         static const uint64_t valid_fdir_inset_table[] = {
8624                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8625                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8626                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8627                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8628                 I40E_INSET_IPV4_TTL,
8629                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8630                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8631                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8632                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8633                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8634                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8635                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8636                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8637                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8638                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8639                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8640                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8641                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8642                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8643                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8644                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8645                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8646                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8647                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8648                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8649                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8650                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8651                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8652                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8653                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8654                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8655                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8656                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8657                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8658                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8659                 I40E_INSET_SCTP_VT,
8660                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8661                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8662                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8663                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8664                 I40E_INSET_IPV4_TTL,
8665                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8666                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8667                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8668                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8669                 I40E_INSET_IPV6_HOP_LIMIT,
8670                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8671                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8672                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8673                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8674                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8675                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8676                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8677                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8678                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8679                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8680                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8681                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8682                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8683                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8684                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8685                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8686                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8687                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8688                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8689                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8690                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8691                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8692                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8693                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8694                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8695                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8696                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8697                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8698                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8699                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8700                 I40E_INSET_SCTP_VT,
8701                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8702                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8703                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8704                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8705                 I40E_INSET_IPV6_HOP_LIMIT,
8706                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8707                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8708                 I40E_INSET_LAST_ETHER_TYPE,
8709         };
8710
8711         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8712                 return 0;
8713         if (filter == RTE_ETH_FILTER_HASH)
8714                 valid = valid_hash_inset_table[pctype];
8715         else
8716                 valid = valid_fdir_inset_table[pctype];
8717
8718         return valid;
8719 }
8720
8721 /**
8722  * Validate if the input set is allowed for a specific PCTYPE
8723  */
8724 int
8725 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8726                 enum rte_filter_type filter, uint64_t inset)
8727 {
8728         uint64_t valid;
8729
8730         valid = i40e_get_valid_input_set(pctype, filter);
8731         if (inset & (~valid))
8732                 return -EINVAL;
8733
8734         return 0;
8735 }
8736
8737 /* default input set fields combination per pctype */
8738 uint64_t
8739 i40e_get_default_input_set(uint16_t pctype)
8740 {
8741         static const uint64_t default_inset_table[] = {
8742                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8743                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8744                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8745                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8746                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8747                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8748                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8749                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8750                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8751                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8752                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8753                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8754                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8756                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8757                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8759                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8760                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8761                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8762                         I40E_INSET_SCTP_VT,
8763                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8764                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8765                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8766                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8767                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8768                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8769                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8770                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8771                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8772                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8773                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8774                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8775                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8776                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8777                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8779                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8780                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8782                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8783                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8784                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8785                         I40E_INSET_SCTP_VT,
8786                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8787                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8788                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8789                         I40E_INSET_LAST_ETHER_TYPE,
8790         };
8791
8792         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8793                 return 0;
8794
8795         return default_inset_table[pctype];
8796 }
8797
8798 /**
8799  * Parse the input set from index to logical bit masks
8800  */
8801 static int
8802 i40e_parse_input_set(uint64_t *inset,
8803                      enum i40e_filter_pctype pctype,
8804                      enum rte_eth_input_set_field *field,
8805                      uint16_t size)
8806 {
8807         uint16_t i, j;
8808         int ret = -EINVAL;
8809
8810         static const struct {
8811                 enum rte_eth_input_set_field field;
8812                 uint64_t inset;
8813         } inset_convert_table[] = {
8814                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8815                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8816                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8817                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8818                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8819                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8820                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8821                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8822                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8823                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8824                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8825                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8826                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8827                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8828                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8829                         I40E_INSET_IPV6_NEXT_HDR},
8830                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8831                         I40E_INSET_IPV6_HOP_LIMIT},
8832                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8833                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8834                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8835                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8836                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8837                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8838                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8839                         I40E_INSET_SCTP_VT},
8840                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8841                         I40E_INSET_TUNNEL_DMAC},
8842                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8843                         I40E_INSET_VLAN_TUNNEL},
8844                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8845                         I40E_INSET_TUNNEL_ID},
8846                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8847                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8848                         I40E_INSET_FLEX_PAYLOAD_W1},
8849                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8850                         I40E_INSET_FLEX_PAYLOAD_W2},
8851                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8852                         I40E_INSET_FLEX_PAYLOAD_W3},
8853                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8854                         I40E_INSET_FLEX_PAYLOAD_W4},
8855                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8856                         I40E_INSET_FLEX_PAYLOAD_W5},
8857                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8858                         I40E_INSET_FLEX_PAYLOAD_W6},
8859                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8860                         I40E_INSET_FLEX_PAYLOAD_W7},
8861                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8862                         I40E_INSET_FLEX_PAYLOAD_W8},
8863         };
8864
8865         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8866                 return ret;
8867
8868         /* Only one item allowed for default or all */
8869         if (size == 1) {
8870                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8871                         *inset = i40e_get_default_input_set(pctype);
8872                         return 0;
8873                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8874                         *inset = I40E_INSET_NONE;
8875                         return 0;
8876                 }
8877         }
8878
8879         for (i = 0, *inset = 0; i < size; i++) {
8880                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8881                         if (field[i] == inset_convert_table[j].field) {
8882                                 *inset |= inset_convert_table[j].inset;
8883                                 break;
8884                         }
8885                 }
8886
8887                 /* It contains unsupported input set, return immediately */
8888                 if (j == RTE_DIM(inset_convert_table))
8889                         return ret;
8890         }
8891
8892         return 0;
8893 }
8894
8895 /**
8896  * Translate the input set from bit masks to register aware bit masks
8897  * and vice versa
8898  */
8899 uint64_t
8900 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8901 {
8902         uint64_t val = 0;
8903         uint16_t i;
8904
8905         struct inset_map {
8906                 uint64_t inset;
8907                 uint64_t inset_reg;
8908         };
8909
8910         static const struct inset_map inset_map_common[] = {
8911                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8912                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8913                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8914                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8915                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8916                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8917                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8918                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8919                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8920                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8921                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8922                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8923                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8924                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8925                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8926                 {I40E_INSET_TUNNEL_DMAC,
8927                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8928                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8929                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8930                 {I40E_INSET_TUNNEL_SRC_PORT,
8931                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8932                 {I40E_INSET_TUNNEL_DST_PORT,
8933                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8934                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8935                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8936                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8937                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8938                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8939                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8940                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8941                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8942                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8943         };
8944
8945     /* some different registers map in x722*/
8946         static const struct inset_map inset_map_diff_x722[] = {
8947                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8948                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8949                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8950                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8951         };
8952
8953         static const struct inset_map inset_map_diff_not_x722[] = {
8954                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8955                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8956                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8957                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8958         };
8959
8960         if (input == 0)
8961                 return val;
8962
8963         /* Translate input set to register aware inset */
8964         if (type == I40E_MAC_X722) {
8965                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8966                         if (input & inset_map_diff_x722[i].inset)
8967                                 val |= inset_map_diff_x722[i].inset_reg;
8968                 }
8969         } else {
8970                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8971                         if (input & inset_map_diff_not_x722[i].inset)
8972                                 val |= inset_map_diff_not_x722[i].inset_reg;
8973                 }
8974         }
8975
8976         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8977                 if (input & inset_map_common[i].inset)
8978                         val |= inset_map_common[i].inset_reg;
8979         }
8980
8981         return val;
8982 }
8983
8984 int
8985 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8986 {
8987         uint8_t i, idx = 0;
8988         uint64_t inset_need_mask = inset;
8989
8990         static const struct {
8991                 uint64_t inset;
8992                 uint32_t mask;
8993         } inset_mask_map[] = {
8994                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8995                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8996                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8997                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8998                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8999                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9000                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9001                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9002         };
9003
9004         if (!inset || !mask || !nb_elem)
9005                 return 0;
9006
9007         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9008                 /* Clear the inset bit, if no MASK is required,
9009                  * for example proto + ttl
9010                  */
9011                 if ((inset & inset_mask_map[i].inset) ==
9012                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9013                         inset_need_mask &= ~inset_mask_map[i].inset;
9014                 if (!inset_need_mask)
9015                         return 0;
9016         }
9017         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9018                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9019                     inset_mask_map[i].inset) {
9020                         if (idx >= nb_elem) {
9021                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9022                                 return -EINVAL;
9023                         }
9024                         mask[idx] = inset_mask_map[i].mask;
9025                         idx++;
9026                 }
9027         }
9028
9029         return idx;
9030 }
9031
9032 void
9033 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9034 {
9035         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9036
9037         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9038         if (reg != val)
9039                 i40e_write_rx_ctl(hw, addr, val);
9040         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9041                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9042 }
9043
9044 void
9045 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9046 {
9047         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9048
9049         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9050         if (reg != val)
9051                 i40e_write_global_rx_ctl(hw, addr, val);
9052         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9053                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9054 }
9055
9056 static void
9057 i40e_filter_input_set_init(struct i40e_pf *pf)
9058 {
9059         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9060         enum i40e_filter_pctype pctype;
9061         uint64_t input_set, inset_reg;
9062         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9063         int num, i;
9064         uint16_t flow_type;
9065
9066         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9067              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9068                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9069
9070                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9071                         continue;
9072
9073                 input_set = i40e_get_default_input_set(pctype);
9074
9075                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9076                                                    I40E_INSET_MASK_NUM_REG);
9077                 if (num < 0)
9078                         return;
9079                 if (pf->support_multi_driver && num > 0) {
9080                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9081                         return;
9082                 }
9083                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9084                                         input_set);
9085
9086                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9087                                       (uint32_t)(inset_reg & UINT32_MAX));
9088                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9089                                      (uint32_t)((inset_reg >>
9090                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9091                 if (!pf->support_multi_driver) {
9092                         i40e_check_write_global_reg(hw,
9093                                             I40E_GLQF_HASH_INSET(0, pctype),
9094                                             (uint32_t)(inset_reg & UINT32_MAX));
9095                         i40e_check_write_global_reg(hw,
9096                                              I40E_GLQF_HASH_INSET(1, pctype),
9097                                              (uint32_t)((inset_reg >>
9098                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9099
9100                         for (i = 0; i < num; i++) {
9101                                 i40e_check_write_global_reg(hw,
9102                                                     I40E_GLQF_FD_MSK(i, pctype),
9103                                                     mask_reg[i]);
9104                                 i40e_check_write_global_reg(hw,
9105                                                   I40E_GLQF_HASH_MSK(i, pctype),
9106                                                   mask_reg[i]);
9107                         }
9108                         /*clear unused mask registers of the pctype */
9109                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9110                                 i40e_check_write_global_reg(hw,
9111                                                     I40E_GLQF_FD_MSK(i, pctype),
9112                                                     0);
9113                                 i40e_check_write_global_reg(hw,
9114                                                   I40E_GLQF_HASH_MSK(i, pctype),
9115                                                   0);
9116                         }
9117                 } else {
9118                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9119                 }
9120                 I40E_WRITE_FLUSH(hw);
9121
9122                 /* store the default input set */
9123                 if (!pf->support_multi_driver)
9124                         pf->hash_input_set[pctype] = input_set;
9125                 pf->fdir.input_set[pctype] = input_set;
9126         }
9127
9128         if (!pf->support_multi_driver) {
9129                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9130                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9131                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9132         }
9133 }
9134
9135 int
9136 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9137                          struct rte_eth_input_set_conf *conf)
9138 {
9139         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9140         enum i40e_filter_pctype pctype;
9141         uint64_t input_set, inset_reg = 0;
9142         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9143         int ret, i, num;
9144
9145         if (!conf) {
9146                 PMD_DRV_LOG(ERR, "Invalid pointer");
9147                 return -EFAULT;
9148         }
9149         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9150             conf->op != RTE_ETH_INPUT_SET_ADD) {
9151                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9152                 return -EINVAL;
9153         }
9154
9155         if (pf->support_multi_driver) {
9156                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9157                 return -ENOTSUP;
9158         }
9159
9160         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9161         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9162                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9163                 return -EINVAL;
9164         }
9165
9166         if (hw->mac.type == I40E_MAC_X722) {
9167                 /* get translated pctype value in fd pctype register */
9168                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9169                         I40E_GLQF_FD_PCTYPES((int)pctype));
9170         }
9171
9172         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9173                                    conf->inset_size);
9174         if (ret) {
9175                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9176                 return -EINVAL;
9177         }
9178
9179         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9180                 /* get inset value in register */
9181                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9182                 inset_reg <<= I40E_32_BIT_WIDTH;
9183                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9184                 input_set |= pf->hash_input_set[pctype];
9185         }
9186         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9187                                            I40E_INSET_MASK_NUM_REG);
9188         if (num < 0)
9189                 return -EINVAL;
9190
9191         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9192
9193         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9194                                     (uint32_t)(inset_reg & UINT32_MAX));
9195         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9196                                     (uint32_t)((inset_reg >>
9197                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9198         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9199
9200         for (i = 0; i < num; i++)
9201                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9202                                             mask_reg[i]);
9203         /*clear unused mask registers of the pctype */
9204         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9205                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9206                                             0);
9207         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9208         I40E_WRITE_FLUSH(hw);
9209
9210         pf->hash_input_set[pctype] = input_set;
9211         return 0;
9212 }
9213
9214 int
9215 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9216                          struct rte_eth_input_set_conf *conf)
9217 {
9218         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9219         enum i40e_filter_pctype pctype;
9220         uint64_t input_set, inset_reg = 0;
9221         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9222         int ret, i, num;
9223
9224         if (!hw || !conf) {
9225                 PMD_DRV_LOG(ERR, "Invalid pointer");
9226                 return -EFAULT;
9227         }
9228         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9229             conf->op != RTE_ETH_INPUT_SET_ADD) {
9230                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9231                 return -EINVAL;
9232         }
9233
9234         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9235
9236         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9237                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9238                 return -EINVAL;
9239         }
9240
9241         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9242                                    conf->inset_size);
9243         if (ret) {
9244                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9245                 return -EINVAL;
9246         }
9247
9248         /* get inset value in register */
9249         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9250         inset_reg <<= I40E_32_BIT_WIDTH;
9251         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9252
9253         /* Can not change the inset reg for flex payload for fdir,
9254          * it is done by writing I40E_PRTQF_FD_FLXINSET
9255          * in i40e_set_flex_mask_on_pctype.
9256          */
9257         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9258                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9259         else
9260                 input_set |= pf->fdir.input_set[pctype];
9261         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9262                                            I40E_INSET_MASK_NUM_REG);
9263         if (num < 0)
9264                 return -EINVAL;
9265         if (pf->support_multi_driver && num > 0) {
9266                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9267                 return -ENOTSUP;
9268         }
9269
9270         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9271
9272         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9273                               (uint32_t)(inset_reg & UINT32_MAX));
9274         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9275                              (uint32_t)((inset_reg >>
9276                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9277
9278         if (!pf->support_multi_driver) {
9279                 for (i = 0; i < num; i++)
9280                         i40e_check_write_global_reg(hw,
9281                                                     I40E_GLQF_FD_MSK(i, pctype),
9282                                                     mask_reg[i]);
9283                 /*clear unused mask registers of the pctype */
9284                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9285                         i40e_check_write_global_reg(hw,
9286                                                     I40E_GLQF_FD_MSK(i, pctype),
9287                                                     0);
9288                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9289         } else {
9290                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9291         }
9292         I40E_WRITE_FLUSH(hw);
9293
9294         pf->fdir.input_set[pctype] = input_set;
9295         return 0;
9296 }
9297
9298 static int
9299 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9300 {
9301         int ret = 0;
9302
9303         if (!hw || !info) {
9304                 PMD_DRV_LOG(ERR, "Invalid pointer");
9305                 return -EFAULT;
9306         }
9307
9308         switch (info->info_type) {
9309         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9310                 i40e_get_symmetric_hash_enable_per_port(hw,
9311                                         &(info->info.enable));
9312                 break;
9313         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9314                 ret = i40e_get_hash_filter_global_config(hw,
9315                                 &(info->info.global_conf));
9316                 break;
9317         default:
9318                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9319                                                         info->info_type);
9320                 ret = -EINVAL;
9321                 break;
9322         }
9323
9324         return ret;
9325 }
9326
9327 static int
9328 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9329 {
9330         int ret = 0;
9331
9332         if (!hw || !info) {
9333                 PMD_DRV_LOG(ERR, "Invalid pointer");
9334                 return -EFAULT;
9335         }
9336
9337         switch (info->info_type) {
9338         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9339                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9340                 break;
9341         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9342                 ret = i40e_set_hash_filter_global_config(hw,
9343                                 &(info->info.global_conf));
9344                 break;
9345         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9346                 ret = i40e_hash_filter_inset_select(hw,
9347                                                &(info->info.input_set_conf));
9348                 break;
9349
9350         default:
9351                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9352                                                         info->info_type);
9353                 ret = -EINVAL;
9354                 break;
9355         }
9356
9357         return ret;
9358 }
9359
9360 /* Operations for hash function */
9361 static int
9362 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9363                       enum rte_filter_op filter_op,
9364                       void *arg)
9365 {
9366         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9367         int ret = 0;
9368
9369         switch (filter_op) {
9370         case RTE_ETH_FILTER_NOP:
9371                 break;
9372         case RTE_ETH_FILTER_GET:
9373                 ret = i40e_hash_filter_get(hw,
9374                         (struct rte_eth_hash_filter_info *)arg);
9375                 break;
9376         case RTE_ETH_FILTER_SET:
9377                 ret = i40e_hash_filter_set(hw,
9378                         (struct rte_eth_hash_filter_info *)arg);
9379                 break;
9380         default:
9381                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9382                                                                 filter_op);
9383                 ret = -ENOTSUP;
9384                 break;
9385         }
9386
9387         return ret;
9388 }
9389
9390 /* Convert ethertype filter structure */
9391 static int
9392 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9393                               struct i40e_ethertype_filter *filter)
9394 {
9395         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9396         filter->input.ether_type = input->ether_type;
9397         filter->flags = input->flags;
9398         filter->queue = input->queue;
9399
9400         return 0;
9401 }
9402
9403 /* Check if there exists the ehtertype filter */
9404 struct i40e_ethertype_filter *
9405 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9406                                 const struct i40e_ethertype_filter_input *input)
9407 {
9408         int ret;
9409
9410         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9411         if (ret < 0)
9412                 return NULL;
9413
9414         return ethertype_rule->hash_map[ret];
9415 }
9416
9417 /* Add ethertype filter in SW list */
9418 static int
9419 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9420                                 struct i40e_ethertype_filter *filter)
9421 {
9422         struct i40e_ethertype_rule *rule = &pf->ethertype;
9423         int ret;
9424
9425         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9426         if (ret < 0) {
9427                 PMD_DRV_LOG(ERR,
9428                             "Failed to insert ethertype filter"
9429                             " to hash table %d!",
9430                             ret);
9431                 return ret;
9432         }
9433         rule->hash_map[ret] = filter;
9434
9435         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9436
9437         return 0;
9438 }
9439
9440 /* Delete ethertype filter in SW list */
9441 int
9442 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9443                              struct i40e_ethertype_filter_input *input)
9444 {
9445         struct i40e_ethertype_rule *rule = &pf->ethertype;
9446         struct i40e_ethertype_filter *filter;
9447         int ret;
9448
9449         ret = rte_hash_del_key(rule->hash_table, input);
9450         if (ret < 0) {
9451                 PMD_DRV_LOG(ERR,
9452                             "Failed to delete ethertype filter"
9453                             " to hash table %d!",
9454                             ret);
9455                 return ret;
9456         }
9457         filter = rule->hash_map[ret];
9458         rule->hash_map[ret] = NULL;
9459
9460         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9461         rte_free(filter);
9462
9463         return 0;
9464 }
9465
9466 /*
9467  * Configure ethertype filter, which can director packet by filtering
9468  * with mac address and ether_type or only ether_type
9469  */
9470 int
9471 i40e_ethertype_filter_set(struct i40e_pf *pf,
9472                         struct rte_eth_ethertype_filter *filter,
9473                         bool add)
9474 {
9475         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9476         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9477         struct i40e_ethertype_filter *ethertype_filter, *node;
9478         struct i40e_ethertype_filter check_filter;
9479         struct i40e_control_filter_stats stats;
9480         uint16_t flags = 0;
9481         int ret;
9482
9483         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9484                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9485                 return -EINVAL;
9486         }
9487         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9488                 filter->ether_type == ETHER_TYPE_IPv6) {
9489                 PMD_DRV_LOG(ERR,
9490                         "unsupported ether_type(0x%04x) in control packet filter.",
9491                         filter->ether_type);
9492                 return -EINVAL;
9493         }
9494         if (filter->ether_type == ETHER_TYPE_VLAN)
9495                 PMD_DRV_LOG(WARNING,
9496                         "filter vlan ether_type in first tag is not supported.");
9497
9498         /* Check if there is the filter in SW list */
9499         memset(&check_filter, 0, sizeof(check_filter));
9500         i40e_ethertype_filter_convert(filter, &check_filter);
9501         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9502                                                &check_filter.input);
9503         if (add && node) {
9504                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9505                 return -EINVAL;
9506         }
9507
9508         if (!add && !node) {
9509                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9510                 return -EINVAL;
9511         }
9512
9513         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9514                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9515         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9516                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9517         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9518
9519         memset(&stats, 0, sizeof(stats));
9520         ret = i40e_aq_add_rem_control_packet_filter(hw,
9521                         filter->mac_addr.addr_bytes,
9522                         filter->ether_type, flags,
9523                         pf->main_vsi->seid,
9524                         filter->queue, add, &stats, NULL);
9525
9526         PMD_DRV_LOG(INFO,
9527                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9528                 ret, stats.mac_etype_used, stats.etype_used,
9529                 stats.mac_etype_free, stats.etype_free);
9530         if (ret < 0)
9531                 return -ENOSYS;
9532
9533         /* Add or delete a filter in SW list */
9534         if (add) {
9535                 ethertype_filter = rte_zmalloc("ethertype_filter",
9536                                        sizeof(*ethertype_filter), 0);
9537                 if (ethertype_filter == NULL) {
9538                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9539                         return -ENOMEM;
9540                 }
9541
9542                 rte_memcpy(ethertype_filter, &check_filter,
9543                            sizeof(check_filter));
9544                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9545                 if (ret < 0)
9546                         rte_free(ethertype_filter);
9547         } else {
9548                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9549         }
9550
9551         return ret;
9552 }
9553
9554 /*
9555  * Handle operations for ethertype filter.
9556  */
9557 static int
9558 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9559                                 enum rte_filter_op filter_op,
9560                                 void *arg)
9561 {
9562         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9563         int ret = 0;
9564
9565         if (filter_op == RTE_ETH_FILTER_NOP)
9566                 return ret;
9567
9568         if (arg == NULL) {
9569                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9570                             filter_op);
9571                 return -EINVAL;
9572         }
9573
9574         switch (filter_op) {
9575         case RTE_ETH_FILTER_ADD:
9576                 ret = i40e_ethertype_filter_set(pf,
9577                         (struct rte_eth_ethertype_filter *)arg,
9578                         TRUE);
9579                 break;
9580         case RTE_ETH_FILTER_DELETE:
9581                 ret = i40e_ethertype_filter_set(pf,
9582                         (struct rte_eth_ethertype_filter *)arg,
9583                         FALSE);
9584                 break;
9585         default:
9586                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9587                 ret = -ENOSYS;
9588                 break;
9589         }
9590         return ret;
9591 }
9592
9593 static int
9594 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9595                      enum rte_filter_type filter_type,
9596                      enum rte_filter_op filter_op,
9597                      void *arg)
9598 {
9599         int ret = 0;
9600
9601         if (dev == NULL)
9602                 return -EINVAL;
9603
9604         switch (filter_type) {
9605         case RTE_ETH_FILTER_NONE:
9606                 /* For global configuration */
9607                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9608                 break;
9609         case RTE_ETH_FILTER_HASH:
9610                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9611                 break;
9612         case RTE_ETH_FILTER_MACVLAN:
9613                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9614                 break;
9615         case RTE_ETH_FILTER_ETHERTYPE:
9616                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9617                 break;
9618         case RTE_ETH_FILTER_TUNNEL:
9619                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9620                 break;
9621         case RTE_ETH_FILTER_FDIR:
9622                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9623                 break;
9624         case RTE_ETH_FILTER_GENERIC:
9625                 if (filter_op != RTE_ETH_FILTER_GET)
9626                         return -EINVAL;
9627                 *(const void **)arg = &i40e_flow_ops;
9628                 break;
9629         default:
9630                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9631                                                         filter_type);
9632                 ret = -EINVAL;
9633                 break;
9634         }
9635
9636         return ret;
9637 }
9638
9639 /*
9640  * Check and enable Extended Tag.
9641  * Enabling Extended Tag is important for 40G performance.
9642  */
9643 static void
9644 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9645 {
9646         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9647         uint32_t buf = 0;
9648         int ret;
9649
9650         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9651                                       PCI_DEV_CAP_REG);
9652         if (ret < 0) {
9653                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9654                             PCI_DEV_CAP_REG);
9655                 return;
9656         }
9657         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9658                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9659                 return;
9660         }
9661
9662         buf = 0;
9663         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9664                                       PCI_DEV_CTRL_REG);
9665         if (ret < 0) {
9666                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9667                             PCI_DEV_CTRL_REG);
9668                 return;
9669         }
9670         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9671                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9672                 return;
9673         }
9674         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9675         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9676                                        PCI_DEV_CTRL_REG);
9677         if (ret < 0) {
9678                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9679                             PCI_DEV_CTRL_REG);
9680                 return;
9681         }
9682 }
9683
9684 /*
9685  * As some registers wouldn't be reset unless a global hardware reset,
9686  * hardware initialization is needed to put those registers into an
9687  * expected initial state.
9688  */
9689 static void
9690 i40e_hw_init(struct rte_eth_dev *dev)
9691 {
9692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9693
9694         i40e_enable_extended_tag(dev);
9695
9696         /* clear the PF Queue Filter control register */
9697         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9698
9699         /* Disable symmetric hash per port */
9700         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9701 }
9702
9703 /*
9704  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9705  * however this function will return only one highest pctype index,
9706  * which is not quite correct. This is known problem of i40e driver
9707  * and needs to be fixed later.
9708  */
9709 enum i40e_filter_pctype
9710 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9711 {
9712         int i;
9713         uint64_t pctype_mask;
9714
9715         if (flow_type < I40E_FLOW_TYPE_MAX) {
9716                 pctype_mask = adapter->pctypes_tbl[flow_type];
9717                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9718                         if (pctype_mask & (1ULL << i))
9719                                 return (enum i40e_filter_pctype)i;
9720                 }
9721         }
9722         return I40E_FILTER_PCTYPE_INVALID;
9723 }
9724
9725 uint16_t
9726 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9727                         enum i40e_filter_pctype pctype)
9728 {
9729         uint16_t flowtype;
9730         uint64_t pctype_mask = 1ULL << pctype;
9731
9732         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9733              flowtype++) {
9734                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9735                         return flowtype;
9736         }
9737
9738         return RTE_ETH_FLOW_UNKNOWN;
9739 }
9740
9741 /*
9742  * On X710, performance number is far from the expectation on recent firmware
9743  * versions; on XL710, performance number is also far from the expectation on
9744  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9745  * mode is enabled and port MAC address is equal to the packet destination MAC
9746  * address. The fix for this issue may not be integrated in the following
9747  * firmware version. So the workaround in software driver is needed. It needs
9748  * to modify the initial values of 3 internal only registers for both X710 and
9749  * XL710. Note that the values for X710 or XL710 could be different, and the
9750  * workaround can be removed when it is fixed in firmware in the future.
9751  */
9752
9753 /* For both X710 and XL710 */
9754 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9755 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9756 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9757
9758 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9759 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9760
9761 /* For X722 */
9762 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9763 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9764
9765 /* For X710 */
9766 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9767 /* For XL710 */
9768 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9769 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9770
9771 static int
9772 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9773 {
9774         enum i40e_status_code status;
9775         struct i40e_aq_get_phy_abilities_resp phy_ab;
9776         int ret = -ENOTSUP;
9777         int retries = 0;
9778
9779         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9780                                               NULL);
9781
9782         while (status) {
9783                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9784                         status);
9785                 retries++;
9786                 rte_delay_us(100000);
9787                 if  (retries < 5)
9788                         status = i40e_aq_get_phy_capabilities(hw, false,
9789                                         true, &phy_ab, NULL);
9790                 else
9791                         return ret;
9792         }
9793         return 0;
9794 }
9795
9796 static void
9797 i40e_configure_registers(struct i40e_hw *hw)
9798 {
9799         static struct {
9800                 uint32_t addr;
9801                 uint64_t val;
9802         } reg_table[] = {
9803                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9804                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9805                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9806         };
9807         uint64_t reg;
9808         uint32_t i;
9809         int ret;
9810
9811         for (i = 0; i < RTE_DIM(reg_table); i++) {
9812                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9813                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9814                                 reg_table[i].val =
9815                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9816                         else /* For X710/XL710/XXV710 */
9817                                 if (hw->aq.fw_maj_ver < 6)
9818                                         reg_table[i].val =
9819                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9820                                 else
9821                                         reg_table[i].val =
9822                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9823                 }
9824
9825                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9826                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9827                                 reg_table[i].val =
9828                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9829                         else /* For X710/XL710/XXV710 */
9830                                 reg_table[i].val =
9831                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9832                 }
9833
9834                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9835                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9836                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9837                                 reg_table[i].val =
9838                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9839                         else /* For X710 */
9840                                 reg_table[i].val =
9841                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9842                 }
9843
9844                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9845                                                         &reg, NULL);
9846                 if (ret < 0) {
9847                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9848                                                         reg_table[i].addr);
9849                         break;
9850                 }
9851                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9852                                                 reg_table[i].addr, reg);
9853                 if (reg == reg_table[i].val)
9854                         continue;
9855
9856                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9857                                                 reg_table[i].val, NULL);
9858                 if (ret < 0) {
9859                         PMD_DRV_LOG(ERR,
9860                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9861                                 reg_table[i].val, reg_table[i].addr);
9862                         break;
9863                 }
9864                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9865                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9866         }
9867 }
9868
9869 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9870 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9871 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9872 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9873 static int
9874 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9875 {
9876         uint32_t reg;
9877         int ret;
9878
9879         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9880                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9881                 return -EINVAL;
9882         }
9883
9884         /* Configure for double VLAN RX stripping */
9885         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9886         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9887                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9888                 ret = i40e_aq_debug_write_register(hw,
9889                                                    I40E_VSI_TSR(vsi->vsi_id),
9890                                                    reg, NULL);
9891                 if (ret < 0) {
9892                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9893                                     vsi->vsi_id);
9894                         return I40E_ERR_CONFIG;
9895                 }
9896         }
9897
9898         /* Configure for double VLAN TX insertion */
9899         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9900         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9901                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9902                 ret = i40e_aq_debug_write_register(hw,
9903                                                    I40E_VSI_L2TAGSTXVALID(
9904                                                    vsi->vsi_id), reg, NULL);
9905                 if (ret < 0) {
9906                         PMD_DRV_LOG(ERR,
9907                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9908                                 vsi->vsi_id);
9909                         return I40E_ERR_CONFIG;
9910                 }
9911         }
9912
9913         return 0;
9914 }
9915
9916 /**
9917  * i40e_aq_add_mirror_rule
9918  * @hw: pointer to the hardware structure
9919  * @seid: VEB seid to add mirror rule to
9920  * @dst_id: destination vsi seid
9921  * @entries: Buffer which contains the entities to be mirrored
9922  * @count: number of entities contained in the buffer
9923  * @rule_id:the rule_id of the rule to be added
9924  *
9925  * Add a mirror rule for a given veb.
9926  *
9927  **/
9928 static enum i40e_status_code
9929 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9930                         uint16_t seid, uint16_t dst_id,
9931                         uint16_t rule_type, uint16_t *entries,
9932                         uint16_t count, uint16_t *rule_id)
9933 {
9934         struct i40e_aq_desc desc;
9935         struct i40e_aqc_add_delete_mirror_rule cmd;
9936         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9937                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9938                 &desc.params.raw;
9939         uint16_t buff_len;
9940         enum i40e_status_code status;
9941
9942         i40e_fill_default_direct_cmd_desc(&desc,
9943                                           i40e_aqc_opc_add_mirror_rule);
9944         memset(&cmd, 0, sizeof(cmd));
9945
9946         buff_len = sizeof(uint16_t) * count;
9947         desc.datalen = rte_cpu_to_le_16(buff_len);
9948         if (buff_len > 0)
9949                 desc.flags |= rte_cpu_to_le_16(
9950                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9951         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9952                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9953         cmd.num_entries = rte_cpu_to_le_16(count);
9954         cmd.seid = rte_cpu_to_le_16(seid);
9955         cmd.destination = rte_cpu_to_le_16(dst_id);
9956
9957         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9958         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9959         PMD_DRV_LOG(INFO,
9960                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9961                 hw->aq.asq_last_status, resp->rule_id,
9962                 resp->mirror_rules_used, resp->mirror_rules_free);
9963         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9964
9965         return status;
9966 }
9967
9968 /**
9969  * i40e_aq_del_mirror_rule
9970  * @hw: pointer to the hardware structure
9971  * @seid: VEB seid to add mirror rule to
9972  * @entries: Buffer which contains the entities to be mirrored
9973  * @count: number of entities contained in the buffer
9974  * @rule_id:the rule_id of the rule to be delete
9975  *
9976  * Delete a mirror rule for a given veb.
9977  *
9978  **/
9979 static enum i40e_status_code
9980 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9981                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9982                 uint16_t count, uint16_t rule_id)
9983 {
9984         struct i40e_aq_desc desc;
9985         struct i40e_aqc_add_delete_mirror_rule cmd;
9986         uint16_t buff_len = 0;
9987         enum i40e_status_code status;
9988         void *buff = NULL;
9989
9990         i40e_fill_default_direct_cmd_desc(&desc,
9991                                           i40e_aqc_opc_delete_mirror_rule);
9992         memset(&cmd, 0, sizeof(cmd));
9993         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9994                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9995                                                           I40E_AQ_FLAG_RD));
9996                 cmd.num_entries = count;
9997                 buff_len = sizeof(uint16_t) * count;
9998                 desc.datalen = rte_cpu_to_le_16(buff_len);
9999                 buff = (void *)entries;
10000         } else
10001                 /* rule id is filled in destination field for deleting mirror rule */
10002                 cmd.destination = rte_cpu_to_le_16(rule_id);
10003
10004         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10005                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10006         cmd.seid = rte_cpu_to_le_16(seid);
10007
10008         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10009         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10010
10011         return status;
10012 }
10013
10014 /**
10015  * i40e_mirror_rule_set
10016  * @dev: pointer to the hardware structure
10017  * @mirror_conf: mirror rule info
10018  * @sw_id: mirror rule's sw_id
10019  * @on: enable/disable
10020  *
10021  * set a mirror rule.
10022  *
10023  **/
10024 static int
10025 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10026                         struct rte_eth_mirror_conf *mirror_conf,
10027                         uint8_t sw_id, uint8_t on)
10028 {
10029         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10030         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10031         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10032         struct i40e_mirror_rule *parent = NULL;
10033         uint16_t seid, dst_seid, rule_id;
10034         uint16_t i, j = 0;
10035         int ret;
10036
10037         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10038
10039         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10040                 PMD_DRV_LOG(ERR,
10041                         "mirror rule can not be configured without veb or vfs.");
10042                 return -ENOSYS;
10043         }
10044         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10045                 PMD_DRV_LOG(ERR, "mirror table is full.");
10046                 return -ENOSPC;
10047         }
10048         if (mirror_conf->dst_pool > pf->vf_num) {
10049                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10050                                  mirror_conf->dst_pool);
10051                 return -EINVAL;
10052         }
10053
10054         seid = pf->main_vsi->veb->seid;
10055
10056         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10057                 if (sw_id <= it->index) {
10058                         mirr_rule = it;
10059                         break;
10060                 }
10061                 parent = it;
10062         }
10063         if (mirr_rule && sw_id == mirr_rule->index) {
10064                 if (on) {
10065                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10066                         return -EEXIST;
10067                 } else {
10068                         ret = i40e_aq_del_mirror_rule(hw, seid,
10069                                         mirr_rule->rule_type,
10070                                         mirr_rule->entries,
10071                                         mirr_rule->num_entries, mirr_rule->id);
10072                         if (ret < 0) {
10073                                 PMD_DRV_LOG(ERR,
10074                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10075                                         ret, hw->aq.asq_last_status);
10076                                 return -ENOSYS;
10077                         }
10078                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10079                         rte_free(mirr_rule);
10080                         pf->nb_mirror_rule--;
10081                         return 0;
10082                 }
10083         } else if (!on) {
10084                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10085                 return -ENOENT;
10086         }
10087
10088         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10089                                 sizeof(struct i40e_mirror_rule) , 0);
10090         if (!mirr_rule) {
10091                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10092                 return I40E_ERR_NO_MEMORY;
10093         }
10094         switch (mirror_conf->rule_type) {
10095         case ETH_MIRROR_VLAN:
10096                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10097                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10098                                 mirr_rule->entries[j] =
10099                                         mirror_conf->vlan.vlan_id[i];
10100                                 j++;
10101                         }
10102                 }
10103                 if (j == 0) {
10104                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10105                         rte_free(mirr_rule);
10106                         return -EINVAL;
10107                 }
10108                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10109                 break;
10110         case ETH_MIRROR_VIRTUAL_POOL_UP:
10111         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10112                 /* check if the specified pool bit is out of range */
10113                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10114                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10115                         rte_free(mirr_rule);
10116                         return -EINVAL;
10117                 }
10118                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10119                         if (mirror_conf->pool_mask & (1ULL << i)) {
10120                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10121                                 j++;
10122                         }
10123                 }
10124                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10125                         /* add pf vsi to entries */
10126                         mirr_rule->entries[j] = pf->main_vsi_seid;
10127                         j++;
10128                 }
10129                 if (j == 0) {
10130                         PMD_DRV_LOG(ERR, "pool is not specified.");
10131                         rte_free(mirr_rule);
10132                         return -EINVAL;
10133                 }
10134                 /* egress and ingress in aq commands means from switch but not port */
10135                 mirr_rule->rule_type =
10136                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10137                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10138                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10139                 break;
10140         case ETH_MIRROR_UPLINK_PORT:
10141                 /* egress and ingress in aq commands means from switch but not port*/
10142                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10143                 break;
10144         case ETH_MIRROR_DOWNLINK_PORT:
10145                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10146                 break;
10147         default:
10148                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10149                         mirror_conf->rule_type);
10150                 rte_free(mirr_rule);
10151                 return -EINVAL;
10152         }
10153
10154         /* If the dst_pool is equal to vf_num, consider it as PF */
10155         if (mirror_conf->dst_pool == pf->vf_num)
10156                 dst_seid = pf->main_vsi_seid;
10157         else
10158                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10159
10160         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10161                                       mirr_rule->rule_type, mirr_rule->entries,
10162                                       j, &rule_id);
10163         if (ret < 0) {
10164                 PMD_DRV_LOG(ERR,
10165                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10166                         ret, hw->aq.asq_last_status);
10167                 rte_free(mirr_rule);
10168                 return -ENOSYS;
10169         }
10170
10171         mirr_rule->index = sw_id;
10172         mirr_rule->num_entries = j;
10173         mirr_rule->id = rule_id;
10174         mirr_rule->dst_vsi_seid = dst_seid;
10175
10176         if (parent)
10177                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10178         else
10179                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10180
10181         pf->nb_mirror_rule++;
10182         return 0;
10183 }
10184
10185 /**
10186  * i40e_mirror_rule_reset
10187  * @dev: pointer to the device
10188  * @sw_id: mirror rule's sw_id
10189  *
10190  * reset a mirror rule.
10191  *
10192  **/
10193 static int
10194 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10195 {
10196         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10198         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10199         uint16_t seid;
10200         int ret;
10201
10202         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10203
10204         seid = pf->main_vsi->veb->seid;
10205
10206         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10207                 if (sw_id == it->index) {
10208                         mirr_rule = it;
10209                         break;
10210                 }
10211         }
10212         if (mirr_rule) {
10213                 ret = i40e_aq_del_mirror_rule(hw, seid,
10214                                 mirr_rule->rule_type,
10215                                 mirr_rule->entries,
10216                                 mirr_rule->num_entries, mirr_rule->id);
10217                 if (ret < 0) {
10218                         PMD_DRV_LOG(ERR,
10219                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10220                                 ret, hw->aq.asq_last_status);
10221                         return -ENOSYS;
10222                 }
10223                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10224                 rte_free(mirr_rule);
10225                 pf->nb_mirror_rule--;
10226         } else {
10227                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10228                 return -ENOENT;
10229         }
10230         return 0;
10231 }
10232
10233 static uint64_t
10234 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10235 {
10236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10237         uint64_t systim_cycles;
10238
10239         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10240         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10241                         << 32;
10242
10243         return systim_cycles;
10244 }
10245
10246 static uint64_t
10247 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10248 {
10249         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10250         uint64_t rx_tstamp;
10251
10252         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10253         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10254                         << 32;
10255
10256         return rx_tstamp;
10257 }
10258
10259 static uint64_t
10260 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10261 {
10262         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10263         uint64_t tx_tstamp;
10264
10265         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10266         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10267                         << 32;
10268
10269         return tx_tstamp;
10270 }
10271
10272 static void
10273 i40e_start_timecounters(struct rte_eth_dev *dev)
10274 {
10275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10276         struct i40e_adapter *adapter =
10277                         (struct i40e_adapter *)dev->data->dev_private;
10278         struct rte_eth_link link;
10279         uint32_t tsync_inc_l;
10280         uint32_t tsync_inc_h;
10281
10282         /* Get current link speed. */
10283         memset(&link, 0, sizeof(link));
10284         i40e_dev_link_update(dev, 1);
10285         rte_i40e_dev_atomic_read_link_status(dev, &link);
10286
10287         switch (link.link_speed) {
10288         case ETH_SPEED_NUM_40G:
10289                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10290                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10291                 break;
10292         case ETH_SPEED_NUM_10G:
10293                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10294                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10295                 break;
10296         case ETH_SPEED_NUM_1G:
10297                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10298                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10299                 break;
10300         default:
10301                 tsync_inc_l = 0x0;
10302                 tsync_inc_h = 0x0;
10303         }
10304
10305         /* Set the timesync increment value. */
10306         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10307         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10308
10309         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10310         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10311         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10312
10313         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10314         adapter->systime_tc.cc_shift = 0;
10315         adapter->systime_tc.nsec_mask = 0;
10316
10317         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10318         adapter->rx_tstamp_tc.cc_shift = 0;
10319         adapter->rx_tstamp_tc.nsec_mask = 0;
10320
10321         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10322         adapter->tx_tstamp_tc.cc_shift = 0;
10323         adapter->tx_tstamp_tc.nsec_mask = 0;
10324 }
10325
10326 static int
10327 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10328 {
10329         struct i40e_adapter *adapter =
10330                         (struct i40e_adapter *)dev->data->dev_private;
10331
10332         adapter->systime_tc.nsec += delta;
10333         adapter->rx_tstamp_tc.nsec += delta;
10334         adapter->tx_tstamp_tc.nsec += delta;
10335
10336         return 0;
10337 }
10338
10339 static int
10340 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10341 {
10342         uint64_t ns;
10343         struct i40e_adapter *adapter =
10344                         (struct i40e_adapter *)dev->data->dev_private;
10345
10346         ns = rte_timespec_to_ns(ts);
10347
10348         /* Set the timecounters to a new value. */
10349         adapter->systime_tc.nsec = ns;
10350         adapter->rx_tstamp_tc.nsec = ns;
10351         adapter->tx_tstamp_tc.nsec = ns;
10352
10353         return 0;
10354 }
10355
10356 static int
10357 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10358 {
10359         uint64_t ns, systime_cycles;
10360         struct i40e_adapter *adapter =
10361                         (struct i40e_adapter *)dev->data->dev_private;
10362
10363         systime_cycles = i40e_read_systime_cyclecounter(dev);
10364         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10365         *ts = rte_ns_to_timespec(ns);
10366
10367         return 0;
10368 }
10369
10370 static int
10371 i40e_timesync_enable(struct rte_eth_dev *dev)
10372 {
10373         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10374         uint32_t tsync_ctl_l;
10375         uint32_t tsync_ctl_h;
10376
10377         /* Stop the timesync system time. */
10378         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10379         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10380         /* Reset the timesync system time value. */
10381         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10382         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10383
10384         i40e_start_timecounters(dev);
10385
10386         /* Clear timesync registers. */
10387         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10388         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10389         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10390         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10391         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10392         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10393
10394         /* Enable timestamping of PTP packets. */
10395         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10396         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10397
10398         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10399         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10400         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10401
10402         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10403         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10404
10405         return 0;
10406 }
10407
10408 static int
10409 i40e_timesync_disable(struct rte_eth_dev *dev)
10410 {
10411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10412         uint32_t tsync_ctl_l;
10413         uint32_t tsync_ctl_h;
10414
10415         /* Disable timestamping of transmitted PTP packets. */
10416         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10417         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10418
10419         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10420         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10421
10422         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10423         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10424
10425         /* Reset the timesync increment value. */
10426         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10427         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10428
10429         return 0;
10430 }
10431
10432 static int
10433 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10434                                 struct timespec *timestamp, uint32_t flags)
10435 {
10436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10437         struct i40e_adapter *adapter =
10438                 (struct i40e_adapter *)dev->data->dev_private;
10439
10440         uint32_t sync_status;
10441         uint32_t index = flags & 0x03;
10442         uint64_t rx_tstamp_cycles;
10443         uint64_t ns;
10444
10445         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10446         if ((sync_status & (1 << index)) == 0)
10447                 return -EINVAL;
10448
10449         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10450         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10451         *timestamp = rte_ns_to_timespec(ns);
10452
10453         return 0;
10454 }
10455
10456 static int
10457 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10458                                 struct timespec *timestamp)
10459 {
10460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10461         struct i40e_adapter *adapter =
10462                 (struct i40e_adapter *)dev->data->dev_private;
10463
10464         uint32_t sync_status;
10465         uint64_t tx_tstamp_cycles;
10466         uint64_t ns;
10467
10468         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10469         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10470                 return -EINVAL;
10471
10472         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10473         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10474         *timestamp = rte_ns_to_timespec(ns);
10475
10476         return 0;
10477 }
10478
10479 /*
10480  * i40e_parse_dcb_configure - parse dcb configure from user
10481  * @dev: the device being configured
10482  * @dcb_cfg: pointer of the result of parse
10483  * @*tc_map: bit map of enabled traffic classes
10484  *
10485  * Returns 0 on success, negative value on failure
10486  */
10487 static int
10488 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10489                          struct i40e_dcbx_config *dcb_cfg,
10490                          uint8_t *tc_map)
10491 {
10492         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10493         uint8_t i, tc_bw, bw_lf;
10494
10495         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10496
10497         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10498         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10499                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10500                 return -EINVAL;
10501         }
10502
10503         /* assume each tc has the same bw */
10504         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10505         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10506                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10507         /* to ensure the sum of tcbw is equal to 100 */
10508         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10509         for (i = 0; i < bw_lf; i++)
10510                 dcb_cfg->etscfg.tcbwtable[i]++;
10511
10512         /* assume each tc has the same Transmission Selection Algorithm */
10513         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10514                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10515
10516         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10517                 dcb_cfg->etscfg.prioritytable[i] =
10518                                 dcb_rx_conf->dcb_tc[i];
10519
10520         /* FW needs one App to configure HW */
10521         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10522         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10523         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10524         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10525
10526         if (dcb_rx_conf->nb_tcs == 0)
10527                 *tc_map = 1; /* tc0 only */
10528         else
10529                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10530
10531         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10532                 dcb_cfg->pfc.willing = 0;
10533                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10534                 dcb_cfg->pfc.pfcenable = *tc_map;
10535         }
10536         return 0;
10537 }
10538
10539
10540 static enum i40e_status_code
10541 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10542                               struct i40e_aqc_vsi_properties_data *info,
10543                               uint8_t enabled_tcmap)
10544 {
10545         enum i40e_status_code ret;
10546         int i, total_tc = 0;
10547         uint16_t qpnum_per_tc, bsf, qp_idx;
10548         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10549         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10550         uint16_t used_queues;
10551
10552         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10553         if (ret != I40E_SUCCESS)
10554                 return ret;
10555
10556         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10557                 if (enabled_tcmap & (1 << i))
10558                         total_tc++;
10559         }
10560         if (total_tc == 0)
10561                 total_tc = 1;
10562         vsi->enabled_tc = enabled_tcmap;
10563
10564         /* different VSI has different queues assigned */
10565         if (vsi->type == I40E_VSI_MAIN)
10566                 used_queues = dev_data->nb_rx_queues -
10567                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10568         else if (vsi->type == I40E_VSI_VMDQ2)
10569                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10570         else {
10571                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10572                 return I40E_ERR_NO_AVAILABLE_VSI;
10573         }
10574
10575         qpnum_per_tc = used_queues / total_tc;
10576         /* Number of queues per enabled TC */
10577         if (qpnum_per_tc == 0) {
10578                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10579                 return I40E_ERR_INVALID_QP_ID;
10580         }
10581         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10582                                 I40E_MAX_Q_PER_TC);
10583         bsf = rte_bsf32(qpnum_per_tc);
10584
10585         /**
10586          * Configure TC and queue mapping parameters, for enabled TC,
10587          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10588          * default queue will serve it.
10589          */
10590         qp_idx = 0;
10591         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10592                 if (vsi->enabled_tc & (1 << i)) {
10593                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10594                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10595                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10596                         qp_idx += qpnum_per_tc;
10597                 } else
10598                         info->tc_mapping[i] = 0;
10599         }
10600
10601         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10602         if (vsi->type == I40E_VSI_SRIOV) {
10603                 info->mapping_flags |=
10604                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10605                 for (i = 0; i < vsi->nb_qps; i++)
10606                         info->queue_mapping[i] =
10607                                 rte_cpu_to_le_16(vsi->base_queue + i);
10608         } else {
10609                 info->mapping_flags |=
10610                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10611                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10612         }
10613         info->valid_sections |=
10614                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10615
10616         return I40E_SUCCESS;
10617 }
10618
10619 /*
10620  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10621  * @veb: VEB to be configured
10622  * @tc_map: enabled TC bitmap
10623  *
10624  * Returns 0 on success, negative value on failure
10625  */
10626 static enum i40e_status_code
10627 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10628 {
10629         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10630         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10631         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10632         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10633         enum i40e_status_code ret = I40E_SUCCESS;
10634         int i;
10635         uint32_t bw_max;
10636
10637         /* Check if enabled_tc is same as existing or new TCs */
10638         if (veb->enabled_tc == tc_map)
10639                 return ret;
10640
10641         /* configure tc bandwidth */
10642         memset(&veb_bw, 0, sizeof(veb_bw));
10643         veb_bw.tc_valid_bits = tc_map;
10644         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10645         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10646                 if (tc_map & BIT_ULL(i))
10647                         veb_bw.tc_bw_share_credits[i] = 1;
10648         }
10649         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10650                                                    &veb_bw, NULL);
10651         if (ret) {
10652                 PMD_INIT_LOG(ERR,
10653                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10654                         hw->aq.asq_last_status);
10655                 return ret;
10656         }
10657
10658         memset(&ets_query, 0, sizeof(ets_query));
10659         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10660                                                    &ets_query, NULL);
10661         if (ret != I40E_SUCCESS) {
10662                 PMD_DRV_LOG(ERR,
10663                         "Failed to get switch_comp ETS configuration %u",
10664                         hw->aq.asq_last_status);
10665                 return ret;
10666         }
10667         memset(&bw_query, 0, sizeof(bw_query));
10668         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10669                                                   &bw_query, NULL);
10670         if (ret != I40E_SUCCESS) {
10671                 PMD_DRV_LOG(ERR,
10672                         "Failed to get switch_comp bandwidth configuration %u",
10673                         hw->aq.asq_last_status);
10674                 return ret;
10675         }
10676
10677         /* store and print out BW info */
10678         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10679         veb->bw_info.bw_max = ets_query.tc_bw_max;
10680         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10681         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10682         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10683                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10684                      I40E_16_BIT_WIDTH);
10685         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10686                 veb->bw_info.bw_ets_share_credits[i] =
10687                                 bw_query.tc_bw_share_credits[i];
10688                 veb->bw_info.bw_ets_credits[i] =
10689                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10690                 /* 4 bits per TC, 4th bit is reserved */
10691                 veb->bw_info.bw_ets_max[i] =
10692                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10693                                   RTE_LEN2MASK(3, uint8_t));
10694                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10695                             veb->bw_info.bw_ets_share_credits[i]);
10696                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10697                             veb->bw_info.bw_ets_credits[i]);
10698                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10699                             veb->bw_info.bw_ets_max[i]);
10700         }
10701
10702         veb->enabled_tc = tc_map;
10703
10704         return ret;
10705 }
10706
10707
10708 /*
10709  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10710  * @vsi: VSI to be configured
10711  * @tc_map: enabled TC bitmap
10712  *
10713  * Returns 0 on success, negative value on failure
10714  */
10715 static enum i40e_status_code
10716 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10717 {
10718         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10719         struct i40e_vsi_context ctxt;
10720         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10721         enum i40e_status_code ret = I40E_SUCCESS;
10722         int i;
10723
10724         /* Check if enabled_tc is same as existing or new TCs */
10725         if (vsi->enabled_tc == tc_map)
10726                 return ret;
10727
10728         /* configure tc bandwidth */
10729         memset(&bw_data, 0, sizeof(bw_data));
10730         bw_data.tc_valid_bits = tc_map;
10731         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10732         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10733                 if (tc_map & BIT_ULL(i))
10734                         bw_data.tc_bw_credits[i] = 1;
10735         }
10736         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10737         if (ret) {
10738                 PMD_INIT_LOG(ERR,
10739                         "AQ command Config VSI BW allocation per TC failed = %d",
10740                         hw->aq.asq_last_status);
10741                 goto out;
10742         }
10743         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10744                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10745
10746         /* Update Queue Pairs Mapping for currently enabled UPs */
10747         ctxt.seid = vsi->seid;
10748         ctxt.pf_num = hw->pf_id;
10749         ctxt.vf_num = 0;
10750         ctxt.uplink_seid = vsi->uplink_seid;
10751         ctxt.info = vsi->info;
10752         i40e_get_cap(hw);
10753         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10754         if (ret)
10755                 goto out;
10756
10757         /* Update the VSI after updating the VSI queue-mapping information */
10758         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10759         if (ret) {
10760                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10761                         hw->aq.asq_last_status);
10762                 goto out;
10763         }
10764         /* update the local VSI info with updated queue map */
10765         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10766                                         sizeof(vsi->info.tc_mapping));
10767         rte_memcpy(&vsi->info.queue_mapping,
10768                         &ctxt.info.queue_mapping,
10769                 sizeof(vsi->info.queue_mapping));
10770         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10771         vsi->info.valid_sections = 0;
10772
10773         /* query and update current VSI BW information */
10774         ret = i40e_vsi_get_bw_config(vsi);
10775         if (ret) {
10776                 PMD_INIT_LOG(ERR,
10777                          "Failed updating vsi bw info, err %s aq_err %s",
10778                          i40e_stat_str(hw, ret),
10779                          i40e_aq_str(hw, hw->aq.asq_last_status));
10780                 goto out;
10781         }
10782
10783         vsi->enabled_tc = tc_map;
10784
10785 out:
10786         return ret;
10787 }
10788
10789 /*
10790  * i40e_dcb_hw_configure - program the dcb setting to hw
10791  * @pf: pf the configuration is taken on
10792  * @new_cfg: new configuration
10793  * @tc_map: enabled TC bitmap
10794  *
10795  * Returns 0 on success, negative value on failure
10796  */
10797 static enum i40e_status_code
10798 i40e_dcb_hw_configure(struct i40e_pf *pf,
10799                       struct i40e_dcbx_config *new_cfg,
10800                       uint8_t tc_map)
10801 {
10802         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10803         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10804         struct i40e_vsi *main_vsi = pf->main_vsi;
10805         struct i40e_vsi_list *vsi_list;
10806         enum i40e_status_code ret;
10807         int i;
10808         uint32_t val;
10809
10810         /* Use the FW API if FW > v4.4*/
10811         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10812               (hw->aq.fw_maj_ver >= 5))) {
10813                 PMD_INIT_LOG(ERR,
10814                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10815                 return I40E_ERR_FIRMWARE_API_VERSION;
10816         }
10817
10818         /* Check if need reconfiguration */
10819         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10820                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10821                 return I40E_SUCCESS;
10822         }
10823
10824         /* Copy the new config to the current config */
10825         *old_cfg = *new_cfg;
10826         old_cfg->etsrec = old_cfg->etscfg;
10827         ret = i40e_set_dcb_config(hw);
10828         if (ret) {
10829                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10830                          i40e_stat_str(hw, ret),
10831                          i40e_aq_str(hw, hw->aq.asq_last_status));
10832                 return ret;
10833         }
10834         /* set receive Arbiter to RR mode and ETS scheme by default */
10835         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10836                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10837                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10838                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10839                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10840                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10841                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10842                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10843                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10844                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10845                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10846                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10847                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10848         }
10849         /* get local mib to check whether it is configured correctly */
10850         /* IEEE mode */
10851         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10852         /* Get Local DCB Config */
10853         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10854                                      &hw->local_dcbx_config);
10855
10856         /* if Veb is created, need to update TC of it at first */
10857         if (main_vsi->veb) {
10858                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10859                 if (ret)
10860                         PMD_INIT_LOG(WARNING,
10861                                  "Failed configuring TC for VEB seid=%d",
10862                                  main_vsi->veb->seid);
10863         }
10864         /* Update each VSI */
10865         i40e_vsi_config_tc(main_vsi, tc_map);
10866         if (main_vsi->veb) {
10867                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10868                         /* Beside main VSI and VMDQ VSIs, only enable default
10869                          * TC for other VSIs
10870                          */
10871                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10872                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10873                                                          tc_map);
10874                         else
10875                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10876                                                          I40E_DEFAULT_TCMAP);
10877                         if (ret)
10878                                 PMD_INIT_LOG(WARNING,
10879                                         "Failed configuring TC for VSI seid=%d",
10880                                         vsi_list->vsi->seid);
10881                         /* continue */
10882                 }
10883         }
10884         return I40E_SUCCESS;
10885 }
10886
10887 /*
10888  * i40e_dcb_init_configure - initial dcb config
10889  * @dev: device being configured
10890  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10891  *
10892  * Returns 0 on success, negative value on failure
10893  */
10894 int
10895 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10896 {
10897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10899         int i, ret = 0;
10900
10901         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10902                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10903                 return -ENOTSUP;
10904         }
10905
10906         /* DCB initialization:
10907          * Update DCB configuration from the Firmware and configure
10908          * LLDP MIB change event.
10909          */
10910         if (sw_dcb == TRUE) {
10911                 ret = i40e_init_dcb(hw);
10912                 /* If lldp agent is stopped, the return value from
10913                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10914                  * adminq status. Otherwise, it should return success.
10915                  */
10916                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10917                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10918                         memset(&hw->local_dcbx_config, 0,
10919                                 sizeof(struct i40e_dcbx_config));
10920                         /* set dcb default configuration */
10921                         hw->local_dcbx_config.etscfg.willing = 0;
10922                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10923                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10924                         hw->local_dcbx_config.etscfg.tsatable[0] =
10925                                                 I40E_IEEE_TSA_ETS;
10926                         /* all UPs mapping to TC0 */
10927                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10928                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10929                         hw->local_dcbx_config.etsrec =
10930                                 hw->local_dcbx_config.etscfg;
10931                         hw->local_dcbx_config.pfc.willing = 0;
10932                         hw->local_dcbx_config.pfc.pfccap =
10933                                                 I40E_MAX_TRAFFIC_CLASS;
10934                         /* FW needs one App to configure HW */
10935                         hw->local_dcbx_config.numapps = 1;
10936                         hw->local_dcbx_config.app[0].selector =
10937                                                 I40E_APP_SEL_ETHTYPE;
10938                         hw->local_dcbx_config.app[0].priority = 3;
10939                         hw->local_dcbx_config.app[0].protocolid =
10940                                                 I40E_APP_PROTOID_FCOE;
10941                         ret = i40e_set_dcb_config(hw);
10942                         if (ret) {
10943                                 PMD_INIT_LOG(ERR,
10944                                         "default dcb config fails. err = %d, aq_err = %d.",
10945                                         ret, hw->aq.asq_last_status);
10946                                 return -ENOSYS;
10947                         }
10948                 } else {
10949                         PMD_INIT_LOG(ERR,
10950                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10951                                 ret, hw->aq.asq_last_status);
10952                         return -ENOTSUP;
10953                 }
10954         } else {
10955                 ret = i40e_aq_start_lldp(hw, NULL);
10956                 if (ret != I40E_SUCCESS)
10957                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10958
10959                 ret = i40e_init_dcb(hw);
10960                 if (!ret) {
10961                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10962                                 PMD_INIT_LOG(ERR,
10963                                         "HW doesn't support DCBX offload.");
10964                                 return -ENOTSUP;
10965                         }
10966                 } else {
10967                         PMD_INIT_LOG(ERR,
10968                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10969                                 ret, hw->aq.asq_last_status);
10970                         return -ENOTSUP;
10971                 }
10972         }
10973         return 0;
10974 }
10975
10976 /*
10977  * i40e_dcb_setup - setup dcb related config
10978  * @dev: device being configured
10979  *
10980  * Returns 0 on success, negative value on failure
10981  */
10982 static int
10983 i40e_dcb_setup(struct rte_eth_dev *dev)
10984 {
10985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10986         struct i40e_dcbx_config dcb_cfg;
10987         uint8_t tc_map = 0;
10988         int ret = 0;
10989
10990         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10991                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10992                 return -ENOTSUP;
10993         }
10994
10995         if (pf->vf_num != 0)
10996                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10997
10998         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10999         if (ret) {
11000                 PMD_INIT_LOG(ERR, "invalid dcb config");
11001                 return -EINVAL;
11002         }
11003         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11004         if (ret) {
11005                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11006                 return -ENOSYS;
11007         }
11008
11009         return 0;
11010 }
11011
11012 static int
11013 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11014                       struct rte_eth_dcb_info *dcb_info)
11015 {
11016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11018         struct i40e_vsi *vsi = pf->main_vsi;
11019         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11020         uint16_t bsf, tc_mapping;
11021         int i, j = 0;
11022
11023         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11024                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11025         else
11026                 dcb_info->nb_tcs = 1;
11027         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11028                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11029         for (i = 0; i < dcb_info->nb_tcs; i++)
11030                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11031
11032         /* get queue mapping if vmdq is disabled */
11033         if (!pf->nb_cfg_vmdq_vsi) {
11034                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11035                         if (!(vsi->enabled_tc & (1 << i)))
11036                                 continue;
11037                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11038                         dcb_info->tc_queue.tc_rxq[j][i].base =
11039                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11040                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11041                         dcb_info->tc_queue.tc_txq[j][i].base =
11042                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11043                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11044                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11045                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11046                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11047                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11048                 }
11049                 return 0;
11050         }
11051
11052         /* get queue mapping if vmdq is enabled */
11053         do {
11054                 vsi = pf->vmdq[j].vsi;
11055                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11056                         if (!(vsi->enabled_tc & (1 << i)))
11057                                 continue;
11058                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11059                         dcb_info->tc_queue.tc_rxq[j][i].base =
11060                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11061                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11062                         dcb_info->tc_queue.tc_txq[j][i].base =
11063                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11064                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11065                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11066                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11067                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11068                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11069                 }
11070                 j++;
11071         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11072         return 0;
11073 }
11074
11075 static int
11076 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11077 {
11078         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11079         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11081         uint16_t msix_intr;
11082
11083         msix_intr = intr_handle->intr_vec[queue_id];
11084         if (msix_intr == I40E_MISC_VEC_ID)
11085                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11086                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11087                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11088                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11089         else
11090                 I40E_WRITE_REG(hw,
11091                                I40E_PFINT_DYN_CTLN(msix_intr -
11092                                                    I40E_RX_VEC_START),
11093                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11094                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11095                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11096
11097         I40E_WRITE_FLUSH(hw);
11098         rte_intr_enable(&pci_dev->intr_handle);
11099
11100         return 0;
11101 }
11102
11103 static int
11104 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11105 {
11106         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11107         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11109         uint16_t msix_intr;
11110
11111         msix_intr = intr_handle->intr_vec[queue_id];
11112         if (msix_intr == I40E_MISC_VEC_ID)
11113                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11114                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11115         else
11116                 I40E_WRITE_REG(hw,
11117                                I40E_PFINT_DYN_CTLN(msix_intr -
11118                                                    I40E_RX_VEC_START),
11119                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11120         I40E_WRITE_FLUSH(hw);
11121
11122         return 0;
11123 }
11124
11125 static int i40e_get_regs(struct rte_eth_dev *dev,
11126                          struct rte_dev_reg_info *regs)
11127 {
11128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11129         uint32_t *ptr_data = regs->data;
11130         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11131         const struct i40e_reg_info *reg_info;
11132
11133         if (ptr_data == NULL) {
11134                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11135                 regs->width = sizeof(uint32_t);
11136                 return 0;
11137         }
11138
11139         /* The first few registers have to be read using AQ operations */
11140         reg_idx = 0;
11141         while (i40e_regs_adminq[reg_idx].name) {
11142                 reg_info = &i40e_regs_adminq[reg_idx++];
11143                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11144                         for (arr_idx2 = 0;
11145                                         arr_idx2 <= reg_info->count2;
11146                                         arr_idx2++) {
11147                                 reg_offset = arr_idx * reg_info->stride1 +
11148                                         arr_idx2 * reg_info->stride2;
11149                                 reg_offset += reg_info->base_addr;
11150                                 ptr_data[reg_offset >> 2] =
11151                                         i40e_read_rx_ctl(hw, reg_offset);
11152                         }
11153         }
11154
11155         /* The remaining registers can be read using primitives */
11156         reg_idx = 0;
11157         while (i40e_regs_others[reg_idx].name) {
11158                 reg_info = &i40e_regs_others[reg_idx++];
11159                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11160                         for (arr_idx2 = 0;
11161                                         arr_idx2 <= reg_info->count2;
11162                                         arr_idx2++) {
11163                                 reg_offset = arr_idx * reg_info->stride1 +
11164                                         arr_idx2 * reg_info->stride2;
11165                                 reg_offset += reg_info->base_addr;
11166                                 ptr_data[reg_offset >> 2] =
11167                                         I40E_READ_REG(hw, reg_offset);
11168                         }
11169         }
11170
11171         return 0;
11172 }
11173
11174 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11175 {
11176         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11177
11178         /* Convert word count to byte count */
11179         return hw->nvm.sr_size << 1;
11180 }
11181
11182 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11183                            struct rte_dev_eeprom_info *eeprom)
11184 {
11185         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11186         uint16_t *data = eeprom->data;
11187         uint16_t offset, length, cnt_words;
11188         int ret_code;
11189
11190         offset = eeprom->offset >> 1;
11191         length = eeprom->length >> 1;
11192         cnt_words = length;
11193
11194         if (offset > hw->nvm.sr_size ||
11195                 offset + length > hw->nvm.sr_size) {
11196                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11197                 return -EINVAL;
11198         }
11199
11200         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11201
11202         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11203         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11204                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11205                 return -EIO;
11206         }
11207
11208         return 0;
11209 }
11210
11211 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11212                                       struct ether_addr *mac_addr)
11213 {
11214         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11215         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11216         struct i40e_vsi *vsi = pf->main_vsi;
11217         struct i40e_mac_filter_info mac_filter;
11218         struct i40e_mac_filter *f;
11219         int ret;
11220
11221         if (!is_valid_assigned_ether_addr(mac_addr)) {
11222                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11223                 return;
11224         }
11225
11226         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11227                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11228                         break;
11229         }
11230
11231         if (f == NULL) {
11232                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11233                 return;
11234         }
11235
11236         mac_filter = f->mac_info;
11237         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11238         if (ret != I40E_SUCCESS) {
11239                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11240                 return;
11241         }
11242         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11243         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11244         if (ret != I40E_SUCCESS) {
11245                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11246                 return;
11247         }
11248         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11249
11250         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11251                                   mac_addr->addr_bytes, NULL);
11252 }
11253
11254 static int
11255 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11256 {
11257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11258         struct rte_eth_dev_data *dev_data = pf->dev_data;
11259         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11260         int ret = 0;
11261
11262         /* check if mtu is within the allowed range */
11263         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11264                 return -EINVAL;
11265
11266         /* mtu setting is forbidden if port is start */
11267         if (dev_data->dev_started) {
11268                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11269                             dev_data->port_id);
11270                 return -EBUSY;
11271         }
11272
11273         if (frame_size > ETHER_MAX_LEN)
11274                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11275         else
11276                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11277
11278         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11279
11280         return ret;
11281 }
11282
11283 /* Restore ethertype filter */
11284 static void
11285 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11286 {
11287         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11288         struct i40e_ethertype_filter_list
11289                 *ethertype_list = &pf->ethertype.ethertype_list;
11290         struct i40e_ethertype_filter *f;
11291         struct i40e_control_filter_stats stats;
11292         uint16_t flags;
11293
11294         TAILQ_FOREACH(f, ethertype_list, rules) {
11295                 flags = 0;
11296                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11297                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11298                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11299                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11300                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11301
11302                 memset(&stats, 0, sizeof(stats));
11303                 i40e_aq_add_rem_control_packet_filter(hw,
11304                                             f->input.mac_addr.addr_bytes,
11305                                             f->input.ether_type,
11306                                             flags, pf->main_vsi->seid,
11307                                             f->queue, 1, &stats, NULL);
11308         }
11309         PMD_DRV_LOG(INFO, "Ethertype filter:"
11310                     " mac_etype_used = %u, etype_used = %u,"
11311                     " mac_etype_free = %u, etype_free = %u",
11312                     stats.mac_etype_used, stats.etype_used,
11313                     stats.mac_etype_free, stats.etype_free);
11314 }
11315
11316 /* Restore tunnel filter */
11317 static void
11318 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11319 {
11320         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11321         struct i40e_vsi *vsi;
11322         struct i40e_pf_vf *vf;
11323         struct i40e_tunnel_filter_list
11324                 *tunnel_list = &pf->tunnel.tunnel_list;
11325         struct i40e_tunnel_filter *f;
11326         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11327         bool big_buffer = 0;
11328
11329         TAILQ_FOREACH(f, tunnel_list, rules) {
11330                 if (!f->is_to_vf)
11331                         vsi = pf->main_vsi;
11332                 else {
11333                         vf = &pf->vfs[f->vf_id];
11334                         vsi = vf->vsi;
11335                 }
11336                 memset(&cld_filter, 0, sizeof(cld_filter));
11337                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11338                         (struct ether_addr *)&cld_filter.element.outer_mac);
11339                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11340                         (struct ether_addr *)&cld_filter.element.inner_mac);
11341                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11342                 cld_filter.element.flags = f->input.flags;
11343                 cld_filter.element.tenant_id = f->input.tenant_id;
11344                 cld_filter.element.queue_number = f->queue;
11345                 rte_memcpy(cld_filter.general_fields,
11346                            f->input.general_fields,
11347                            sizeof(f->input.general_fields));
11348
11349                 if (((f->input.flags &
11350                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11351                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11352                     ((f->input.flags &
11353                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11354                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11355                     ((f->input.flags &
11356                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11357                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11358                         big_buffer = 1;
11359
11360                 if (big_buffer)
11361                         i40e_aq_add_cloud_filters_big_buffer(hw,
11362                                              vsi->seid, &cld_filter, 1);
11363                 else
11364                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11365                                                   &cld_filter.element, 1);
11366         }
11367 }
11368
11369 static void
11370 i40e_filter_restore(struct i40e_pf *pf)
11371 {
11372         i40e_ethertype_filter_restore(pf);
11373         i40e_tunnel_filter_restore(pf);
11374         i40e_fdir_filter_restore(pf);
11375 }
11376
11377 static bool
11378 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11379 {
11380         if (strcmp(dev->device->driver->name, drv->driver.name))
11381                 return false;
11382
11383         return true;
11384 }
11385
11386 bool
11387 is_i40e_supported(struct rte_eth_dev *dev)
11388 {
11389         return is_device_supported(dev, &rte_i40e_pmd);
11390 }
11391
11392 struct i40e_customized_pctype*
11393 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11394 {
11395         int i;
11396
11397         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11398                 if (pf->customized_pctype[i].index == index)
11399                         return &pf->customized_pctype[i];
11400         }
11401         return NULL;
11402 }
11403
11404 static int
11405 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11406                               uint32_t pkg_size, uint32_t proto_num,
11407                               struct rte_pmd_i40e_proto_info *proto,
11408                               enum rte_pmd_i40e_package_op op)
11409 {
11410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11411         uint32_t pctype_num;
11412         struct rte_pmd_i40e_ptype_info *pctype;
11413         uint32_t buff_size;
11414         struct i40e_customized_pctype *new_pctype = NULL;
11415         uint8_t proto_id;
11416         uint8_t pctype_value;
11417         char name[64];
11418         uint32_t i, j, n;
11419         int ret;
11420
11421         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11422             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11423                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11424                 return -1;
11425         }
11426
11427         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11428                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11429                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11430         if (ret) {
11431                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11432                 return -1;
11433         }
11434         if (!pctype_num) {
11435                 PMD_DRV_LOG(INFO, "No new pctype added");
11436                 return -1;
11437         }
11438
11439         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11440         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11441         if (!pctype) {
11442                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11443                 return -1;
11444         }
11445         /* get information about new pctype list */
11446         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11447                                         (uint8_t *)pctype, buff_size,
11448                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11449         if (ret) {
11450                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11451                 rte_free(pctype);
11452                 return -1;
11453         }
11454
11455         /* Update customized pctype. */
11456         for (i = 0; i < pctype_num; i++) {
11457                 pctype_value = pctype[i].ptype_id;
11458                 memset(name, 0, sizeof(name));
11459                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11460                         proto_id = pctype[i].protocols[j];
11461                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11462                                 continue;
11463                         for (n = 0; n < proto_num; n++) {
11464                                 if (proto[n].proto_id != proto_id)
11465                                         continue;
11466                                 strcat(name, proto[n].name);
11467                                 strcat(name, "_");
11468                                 break;
11469                         }
11470                 }
11471                 name[strlen(name) - 1] = '\0';
11472                 if (!strcmp(name, "GTPC"))
11473                         new_pctype =
11474                                 i40e_find_customized_pctype(pf,
11475                                                       I40E_CUSTOMIZED_GTPC);
11476                 else if (!strcmp(name, "GTPU_IPV4"))
11477                         new_pctype =
11478                                 i40e_find_customized_pctype(pf,
11479                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11480                 else if (!strcmp(name, "GTPU_IPV6"))
11481                         new_pctype =
11482                                 i40e_find_customized_pctype(pf,
11483                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11484                 else if (!strcmp(name, "GTPU"))
11485                         new_pctype =
11486                                 i40e_find_customized_pctype(pf,
11487                                                       I40E_CUSTOMIZED_GTPU);
11488                 if (new_pctype) {
11489                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11490                                 new_pctype->pctype = pctype_value;
11491                                 new_pctype->valid = true;
11492                         } else {
11493                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11494                                 new_pctype->valid = false;
11495                         }
11496                 }
11497         }
11498
11499         rte_free(pctype);
11500         return 0;
11501 }
11502
11503 static int
11504 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11505                              uint32_t pkg_size, uint32_t proto_num,
11506                              struct rte_pmd_i40e_proto_info *proto,
11507                              enum rte_pmd_i40e_package_op op)
11508 {
11509         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11510         uint16_t port_id = dev->data->port_id;
11511         uint32_t ptype_num;
11512         struct rte_pmd_i40e_ptype_info *ptype;
11513         uint32_t buff_size;
11514         uint8_t proto_id;
11515         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11516         uint32_t i, j, n;
11517         bool inner_ip;
11518         int ret;
11519
11520         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11521             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11522                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11523                 return -1;
11524         }
11525
11526         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11527                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11528                 return 0;
11529         }
11530
11531         /* get information about new ptype num */
11532         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11533                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11534                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11535         if (ret) {
11536                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11537                 return ret;
11538         }
11539         if (!ptype_num) {
11540                 PMD_DRV_LOG(INFO, "No new ptype added");
11541                 return -1;
11542         }
11543
11544         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11545         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11546         if (!ptype) {
11547                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11548                 return -1;
11549         }
11550
11551         /* get information about new ptype list */
11552         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11553                                         (uint8_t *)ptype, buff_size,
11554                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11555         if (ret) {
11556                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11557                 rte_free(ptype);
11558                 return ret;
11559         }
11560
11561         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11562         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11563         if (!ptype_mapping) {
11564                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11565                 rte_free(ptype);
11566                 return -1;
11567         }
11568
11569         /* Update ptype mapping table. */
11570         for (i = 0; i < ptype_num; i++) {
11571                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11572                 ptype_mapping[i].sw_ptype = 0;
11573                 inner_ip = false;
11574                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11575                         proto_id = ptype[i].protocols[j];
11576                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11577                                 continue;
11578                         for (n = 0; n < proto_num; n++) {
11579                                 if (proto[n].proto_id != proto_id)
11580                                         continue;
11581                                 memset(name, 0, sizeof(name));
11582                                 strcpy(name, proto[n].name);
11583                                 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11584                                         ptype_mapping[i].sw_ptype |=
11585                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11586                                         inner_ip = true;
11587                                 } else if (!strncmp(name, "IPV4FRAG", 8) &&
11588                                            inner_ip) {
11589                                         ptype_mapping[i].sw_ptype |=
11590                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11591                                         ptype_mapping[i].sw_ptype |=
11592                                                 RTE_PTYPE_INNER_L4_FRAG;
11593                                 } else if (!strncmp(name, "IPV4", 4) &&
11594                                            inner_ip)
11595                                         ptype_mapping[i].sw_ptype |=
11596                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11597                                 else if (!strncmp(name, "IPV6", 4) &&
11598                                          !inner_ip) {
11599                                         ptype_mapping[i].sw_ptype |=
11600                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11601                                         inner_ip = true;
11602                                 } else if (!strncmp(name, "IPV6FRAG", 8) &&
11603                                            inner_ip) {
11604                                         ptype_mapping[i].sw_ptype |=
11605                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11606                                         ptype_mapping[i].sw_ptype |=
11607                                                 RTE_PTYPE_INNER_L4_FRAG;
11608                                 } else if (!strncmp(name, "IPV6", 4) &&
11609                                            inner_ip)
11610                                         ptype_mapping[i].sw_ptype |=
11611                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11612                                 else if (!strncmp(name, "GTPC", 4))
11613                                         ptype_mapping[i].sw_ptype |=
11614                                                 RTE_PTYPE_TUNNEL_GTPC;
11615                                 else if (!strncmp(name, "GTPU", 4))
11616                                         ptype_mapping[i].sw_ptype |=
11617                                                 RTE_PTYPE_TUNNEL_GTPU;
11618                                 else if (!strncmp(name, "UDP", 3))
11619                                         ptype_mapping[i].sw_ptype |=
11620                                                 RTE_PTYPE_INNER_L4_UDP;
11621                                 else if (!strncmp(name, "TCP", 3))
11622                                         ptype_mapping[i].sw_ptype |=
11623                                                 RTE_PTYPE_INNER_L4_TCP;
11624                                 else if (!strncmp(name, "SCTP", 4))
11625                                         ptype_mapping[i].sw_ptype |=
11626                                                 RTE_PTYPE_INNER_L4_SCTP;
11627                                 else if (!strncmp(name, "ICMP", 4) ||
11628                                          !strncmp(name, "ICMPV6", 6))
11629                                         ptype_mapping[i].sw_ptype |=
11630                                                 RTE_PTYPE_INNER_L4_ICMP;
11631
11632                                 break;
11633                         }
11634                 }
11635         }
11636
11637         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11638                                                 ptype_num, 0);
11639         if (ret)
11640                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11641
11642         rte_free(ptype_mapping);
11643         rte_free(ptype);
11644         return ret;
11645 }
11646
11647 void
11648 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11649                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11650 {
11651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11652         uint32_t proto_num;
11653         struct rte_pmd_i40e_proto_info *proto;
11654         uint32_t buff_size;
11655         uint32_t i;
11656         int ret;
11657
11658         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11659             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11660                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11661                 return;
11662         }
11663
11664         /* get information about protocol number */
11665         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11666                                        (uint8_t *)&proto_num, sizeof(proto_num),
11667                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11668         if (ret) {
11669                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11670                 return;
11671         }
11672         if (!proto_num) {
11673                 PMD_DRV_LOG(INFO, "No new protocol added");
11674                 return;
11675         }
11676
11677         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11678         proto = rte_zmalloc("new_proto", buff_size, 0);
11679         if (!proto) {
11680                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11681                 return;
11682         }
11683
11684         /* get information about protocol list */
11685         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11686                                         (uint8_t *)proto, buff_size,
11687                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11688         if (ret) {
11689                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11690                 rte_free(proto);
11691                 return;
11692         }
11693
11694         /* Check if GTP is supported. */
11695         for (i = 0; i < proto_num; i++) {
11696                 if (!strncmp(proto[i].name, "GTP", 3)) {
11697                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11698                                 pf->gtp_support = true;
11699                         else
11700                                 pf->gtp_support = false;
11701                         break;
11702                 }
11703         }
11704
11705         /* Update customized pctype info */
11706         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11707                                             proto_num, proto, op);
11708         if (ret)
11709                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11710
11711         /* Update customized ptype info */
11712         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11713                                            proto_num, proto, op);
11714         if (ret)
11715                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11716
11717         rte_free(proto);
11718 }
11719
11720 /* Create a QinQ cloud filter
11721  *
11722  * The Fortville NIC has limited resources for tunnel filters,
11723  * so we can only reuse existing filters.
11724  *
11725  * In step 1 we define which Field Vector fields can be used for
11726  * filter types.
11727  * As we do not have the inner tag defined as a field,
11728  * we have to define it first, by reusing one of L1 entries.
11729  *
11730  * In step 2 we are replacing one of existing filter types with
11731  * a new one for QinQ.
11732  * As we reusing L1 and replacing L2, some of the default filter
11733  * types will disappear,which depends on L1 and L2 entries we reuse.
11734  *
11735  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11736  *
11737  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11738  *              later when we define the cloud filter.
11739  *      a.      Valid_flags.replace_cloud = 0
11740  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11741  *      c.      New_filter = 0x10
11742  *      d.      TR bit = 0xff (optional, not used here)
11743  *      e.      Buffer – 2 entries:
11744  *              i.      Byte 0 = 8 (outer vlan FV index).
11745  *                      Byte 1 = 0 (rsv)
11746  *                      Byte 2-3 = 0x0fff
11747  *              ii.     Byte 0 = 37 (inner vlan FV index).
11748  *                      Byte 1 =0 (rsv)
11749  *                      Byte 2-3 = 0x0fff
11750  *
11751  * Step 2:
11752  * 2.   Create cloud filter using two L1 filters entries: stag and
11753  *              new filter(outer vlan+ inner vlan)
11754  *      a.      Valid_flags.replace_cloud = 1
11755  *      b.      Old_filter = 1 (instead of outer IP)
11756  *      c.      New_filter = 0x10
11757  *      d.      Buffer – 2 entries:
11758  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11759  *                      Byte 1-3 = 0 (rsv)
11760  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11761  *                      Byte 9-11 = 0 (rsv)
11762  */
11763 static int
11764 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11765 {
11766         int ret = -ENOTSUP;
11767         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11768         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11769         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11770
11771         if (pf->support_multi_driver) {
11772                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11773                 return ret;
11774         }
11775
11776         /* Init */
11777         memset(&filter_replace, 0,
11778                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11779         memset(&filter_replace_buf, 0,
11780                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11781
11782         /* create L1 filter */
11783         filter_replace.old_filter_type =
11784                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11785         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11786         filter_replace.tr_bit = 0;
11787
11788         /* Prepare the buffer, 2 entries */
11789         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11790         filter_replace_buf.data[0] |=
11791                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11792         /* Field Vector 12b mask */
11793         filter_replace_buf.data[2] = 0xff;
11794         filter_replace_buf.data[3] = 0x0f;
11795         filter_replace_buf.data[4] =
11796                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11797         filter_replace_buf.data[4] |=
11798                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11799         /* Field Vector 12b mask */
11800         filter_replace_buf.data[6] = 0xff;
11801         filter_replace_buf.data[7] = 0x0f;
11802         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11803                         &filter_replace_buf);
11804         if (ret != I40E_SUCCESS)
11805                 return ret;
11806         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11807                     "cloud l1 type is changed from 0x%x to 0x%x",
11808                     filter_replace.old_filter_type,
11809                     filter_replace.new_filter_type);
11810
11811         /* Apply the second L2 cloud filter */
11812         memset(&filter_replace, 0,
11813                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11814         memset(&filter_replace_buf, 0,
11815                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11816
11817         /* create L2 filter, input for L2 filter will be L1 filter  */
11818         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11819         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11820         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11821
11822         /* Prepare the buffer, 2 entries */
11823         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11824         filter_replace_buf.data[0] |=
11825                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11826         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11827         filter_replace_buf.data[4] |=
11828                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11829         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11830                         &filter_replace_buf);
11831         if (!ret) {
11832                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11833                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11834                             "cloud filter type is changed from 0x%x to 0x%x",
11835                             filter_replace.old_filter_type,
11836                             filter_replace.new_filter_type);
11837         }
11838         return ret;
11839 }
11840
11841 RTE_INIT(i40e_init_log);
11842 static void
11843 i40e_init_log(void)
11844 {
11845         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11846         if (i40e_logtype_init >= 0)
11847                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11848         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11849         if (i40e_logtype_driver >= 0)
11850                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11851 }
11852
11853 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
11854                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");