drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  79
  80 /* Flow control default timer */
  81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  82
  83 /* Flow control default high water */
  84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  85
  86 /* Flow control default low water */
  87 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Receive Average Packet Size in Byte*/
  99 #define I40E_PACKET_AVERAGE_SIZE 128
 100
 101 /* Mask of PF interrupt causes */
 102 #define I40E_PFINT_ICR0_ENA_MASK ( \
 103                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 104                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 105                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 106                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 107                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 109                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 113
 114 #define I40E_FLOW_TYPES ( \
 115         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 116         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 126
 127 /* Additional timesync values. */
 128 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA     0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 133 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 134
 135 #define I40E_MAX_PERCENT            100
 136 #define I40E_DEFAULT_DCB_APP_NUM    1
 137 #define I40E_DEFAULT_DCB_APP_PRIO   3
 138
 139 #define I40E_INSET_NONE            0x00000000000000000ULL
 140
 141 /* bit0 ~ bit 7 */
 142 #define I40E_INSET_DMAC            0x0000000000000001ULL
 143 #define I40E_INSET_SMAC            0x0000000000000002ULL
 144 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 145 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 146 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 147
 148 /* bit 8 ~ bit 15 */
 149 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 150 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 151 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 152 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 153 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 154 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 155 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 156
 157 /* bit 16 ~ bit 31 */
 158 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 159 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 160 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 161 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 162 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 163 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 164 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 165 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 166
 167 /* bit 32 ~ bit 47, tunnel fields */
 168 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 169 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 170 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 171 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 172 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 173 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 174
 175 /* bit 48 ~ bit 55 */
 176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 177
 178 /* bit 56 ~ bit 63, Flex Payload */
 179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD \
 188         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 189         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 190         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 191         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 192
 193 /**
 194  * Below are values for writing un-exposed registers suggested
 195  * by silicon experts
 196  */
 197 /* Destination MAC address */
 198 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 199 /* Source MAC address */
 200 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 202 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 205 /* Single VLAN tag in the inner L2 header */
 206 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 207 /* Source IPv4 address */
 208 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 209 /* Destination IPv4 address */
 210 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 211 /* IPv4 Type of Service (TOS) */
 212 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 213 /* IPv4 Protocol */
 214 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 215 /* IPv4 Time to Live */
 216 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 217 /* Source IPv6 address */
 218 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 219 /* Destination IPv6 address */
 220 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 221 /* IPv6 Traffic Class (TC) */
 222 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 223 /* IPv6 Next Header */
 224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 225 /* IPv6 Hop Limit */
 226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263 /* all 8 words flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 265 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 266
 267 #define I40E_TRANSLATE_INSET 0
 268 #define I40E_TRANSLATE_REG   1
 269
 270 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 271 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 272 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 275 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 276
 277 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 280         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 281
 282 /* PCI offset for querying capability */
 283 #define PCI_DEV_CAP_REG            0xA4
 284 /* PCI offset for enabling/disabling Extended Tag */
 285 #define PCI_DEV_CTRL_REG           0xA8
 286 /* Bit mask of Extended Tag capability */
 287 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 288 /* Bit shift of Extended Tag enable/disable */
 289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 290 /* Bit mask of Extended Tag enable/disable */
 291 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 292
 293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 295 static int i40e_dev_configure(struct rte_eth_dev *dev);
 296 static int i40e_dev_start(struct rte_eth_dev *dev);
 297 static void i40e_dev_stop(struct rte_eth_dev *dev);
 298 static void i40e_dev_close(struct rte_eth_dev *dev);
 299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 306                                struct rte_eth_stats *stats);
 307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 308                                struct rte_eth_xstats *xstats, unsigned n);
 309 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 310 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 311                                             uint16_t queue_id,
 312                                             uint8_t stat_idx,
 313                                             uint8_t is_rx);
 314 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 315                               struct rte_eth_dev_info *dev_info);
 316 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 317                                 uint16_t vlan_id,
 318                                 int on);
 319 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 320                               enum rte_vlan_type vlan_type,
 321                               uint16_t tpid);
 322 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 323 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 324                                       uint16_t queue,
 325                                       int on);
 326 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 327 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 328 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 329 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 330                               struct rte_eth_fc_conf *fc_conf);
 331 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 332                               struct rte_eth_fc_conf *fc_conf);
 333 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 334                                        struct rte_eth_pfc_conf *pfc_conf);
 335 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 336                           struct ether_addr *mac_addr,
 337                           uint32_t index,
 338                           uint32_t pool);
 339 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 340 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 341                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 342                                     uint16_t reta_size);
 343 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 344                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 345                                    uint16_t reta_size);
 346
 347 static int i40e_get_cap(struct i40e_hw *hw);
 348 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 349 static int i40e_pf_setup(struct i40e_pf *pf);
 350 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 351 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 352 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 353 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 354 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 355                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 356 static void i40e_stat_update_48(struct i40e_hw *hw,
 357                                uint32_t hireg,
 358                                uint32_t loreg,
 359                                bool offset_loaded,
 360                                uint64_t *offset,
 361                                uint64_t *stat);
 362 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 363 static void i40e_dev_interrupt_handler(
 364                 __rte_unused struct rte_intr_handle *handle, void *param);
 365 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 366                                 uint32_t base, uint32_t num);
 367 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 368 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 369                         uint32_t base);
 370 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 371                         uint16_t num);
 372 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 373 static int i40e_veb_release(struct i40e_veb *veb);
 374 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 375                                                 struct i40e_vsi *vsi);
 376 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 377 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 378 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 379                                              struct i40e_macvlan_filter *mv_f,
 380                                              int num,
 381                                              struct ether_addr *addr);
 382 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 383                                              struct i40e_macvlan_filter *mv_f,
 384                                              int num,
 385                                              uint16_t vlan);
 386 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 387 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 388                                     struct rte_eth_rss_conf *rss_conf);
 389 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 390                                       struct rte_eth_rss_conf *rss_conf);
 391 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 392                                         struct rte_eth_udp_tunnel *udp_tunnel);
 393 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 394                                         struct rte_eth_udp_tunnel *udp_tunnel);
 395 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 396 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 397                         struct rte_eth_ethertype_filter *filter,
 398                         bool add);
 399 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 400                                 enum rte_filter_op filter_op,
 401                                 void *arg);
 402 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 403                                 enum rte_filter_type filter_type,
 404                                 enum rte_filter_op filter_op,
 405                                 void *arg);
 406 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 407                                   struct rte_eth_dcb_info *dcb_info);
 408 static void i40e_configure_registers(struct i40e_hw *hw);
 409 static void i40e_hw_init(struct rte_eth_dev *dev);
 410 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 411 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 412                         struct rte_eth_mirror_conf *mirror_conf,
 413                         uint8_t sw_id, uint8_t on);
 414 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 415
 416 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 417 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 418 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 419                                            struct timespec *timestamp,
 420                                            uint32_t flags);
 421 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 422                                            struct timespec *timestamp);
 423 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 424
 425 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 426
 427 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 428                                    struct timespec *timestamp);
 429 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 430                                     const struct timespec *timestamp);
 431
 432 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 433                                          uint16_t queue_id);
 434 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 435                                           uint16_t queue_id);
 436
 437 static int i40e_get_reg_length(struct rte_eth_dev *dev);
 438
 439 static int i40e_get_regs(struct rte_eth_dev *dev,
 440                          struct rte_dev_reg_info *regs);
 441
 442 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 443
 444 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 445                            struct rte_dev_eeprom_info *eeprom);
 446
 447 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 448                                       struct ether_addr *mac_addr);
 449
 450 static const struct rte_pci_id pci_id_i40e_map[] = {
 451 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 452 #include "rte_pci_dev_ids.h"
 453 { .vendor_id = 0, /* sentinel */ },
 454 };
 455
 456 static const struct eth_dev_ops i40e_eth_dev_ops = {
 457         .dev_configure                = i40e_dev_configure,
 458         .dev_start                    = i40e_dev_start,
 459         .dev_stop                     = i40e_dev_stop,
 460         .dev_close                    = i40e_dev_close,
 461         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 462         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 463         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 464         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 465         .dev_set_link_up              = i40e_dev_set_link_up,
 466         .dev_set_link_down            = i40e_dev_set_link_down,
 467         .link_update                  = i40e_dev_link_update,
 468         .stats_get                    = i40e_dev_stats_get,
 469         .xstats_get                   = i40e_dev_xstats_get,
 470         .stats_reset                  = i40e_dev_stats_reset,
 471         .xstats_reset                 = i40e_dev_stats_reset,
 472         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 473         .dev_infos_get                = i40e_dev_info_get,
 474         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 475         .vlan_filter_set              = i40e_vlan_filter_set,
 476         .vlan_tpid_set                = i40e_vlan_tpid_set,
 477         .vlan_offload_set             = i40e_vlan_offload_set,
 478         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 479         .vlan_pvid_set                = i40e_vlan_pvid_set,
 480         .rx_queue_start               = i40e_dev_rx_queue_start,
 481         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 482         .tx_queue_start               = i40e_dev_tx_queue_start,
 483         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 484         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 485         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 486         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 487         .rx_queue_release             = i40e_dev_rx_queue_release,
 488         .rx_queue_count               = i40e_dev_rx_queue_count,
 489         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 490         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 491         .tx_queue_release             = i40e_dev_tx_queue_release,
 492         .dev_led_on                   = i40e_dev_led_on,
 493         .dev_led_off                  = i40e_dev_led_off,
 494         .flow_ctrl_get                = i40e_flow_ctrl_get,
 495         .flow_ctrl_set                = i40e_flow_ctrl_set,
 496         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 497         .mac_addr_add                 = i40e_macaddr_add,
 498         .mac_addr_remove              = i40e_macaddr_remove,
 499         .reta_update                  = i40e_dev_rss_reta_update,
 500         .reta_query                   = i40e_dev_rss_reta_query,
 501         .rss_hash_update              = i40e_dev_rss_hash_update,
 502         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 503         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 504         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 505         .filter_ctrl                  = i40e_dev_filter_ctrl,
 506         .rxq_info_get                 = i40e_rxq_info_get,
 507         .txq_info_get                 = i40e_txq_info_get,
 508         .mirror_rule_set              = i40e_mirror_rule_set,
 509         .mirror_rule_reset            = i40e_mirror_rule_reset,
 510         .timesync_enable              = i40e_timesync_enable,
 511         .timesync_disable             = i40e_timesync_disable,
 512         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 513         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 514         .get_dcb_info                 = i40e_dev_get_dcb_info,
 515         .timesync_adjust_time         = i40e_timesync_adjust_time,
 516         .timesync_read_time           = i40e_timesync_read_time,
 517         .timesync_write_time          = i40e_timesync_write_time,
 518         .get_reg_length               = i40e_get_reg_length,
 519         .get_reg                      = i40e_get_regs,
 520         .get_eeprom_length            = i40e_get_eeprom_length,
 521         .get_eeprom                   = i40e_get_eeprom,
 522         .mac_addr_set                 = i40e_set_default_mac_addr,
 523 };
 524
 525 /* store statistics names and its offset in stats structure */
 526 struct rte_i40e_xstats_name_off {
 527         char name[RTE_ETH_XSTATS_NAME_SIZE];
 528         unsigned offset;
 529 };
 530
 531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 532         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 533         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 534         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 535         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 536         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 537                 rx_unknown_protocol)},
 538         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 539         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 540         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 541         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 542 };
 543
 544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 545                 sizeof(rte_i40e_stats_strings[0]))
 546
 547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 548         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 549                 tx_dropped_link_down)},
 550         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 551         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 552                 illegal_bytes)},
 553         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 554         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_local_faults)},
 556         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 557                 mac_remote_faults)},
 558         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 559                 rx_length_errors)},
 560         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 561         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 562         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 563         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 564         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 565         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_127)},
 567         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_255)},
 569         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_511)},
 571         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1023)},
 573         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_1522)},
 575         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_big)},
 577         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_undersize)},
 579         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_oversize)},
 581         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 582                 mac_short_packet_dropped)},
 583         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_fragments)},
 585         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 586         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 587         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_127)},
 589         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_255)},
 591         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_511)},
 593         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1023)},
 595         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_1522)},
 597         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_big)},
 599         {"rx_flow_director_atr_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 601         {"rx_flow_director_sb_match_packets",
 602                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 603         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_status)},
 605         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_status)},
 607         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 tx_lpi_count)},
 609         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 610                 rx_lpi_count)},
 611 };
 612
 613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 614                 sizeof(rte_i40e_hw_port_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_rx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_rx)},
 621 };
 622
 623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 624                 sizeof(rte_i40e_rxq_prio_strings[0]))
 625
 626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 627         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_tx)},
 629         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xoff_tx)},
 631         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xon_2_xoff)},
 633 };
 634
 635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 636                 sizeof(rte_i40e_txq_prio_strings[0]))
 637
 638 static struct eth_driver rte_i40e_pmd = {
 639         .pci_drv = {
 640                 .name = "rte_i40e_pmd",
 641                 .id_table = pci_id_i40e_map,
 642                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 643                         RTE_PCI_DRV_DETACHABLE,
 644         },
 645         .eth_dev_init = eth_i40e_dev_init,
 646         .eth_dev_uninit = eth_i40e_dev_uninit,
 647         .dev_private_size = sizeof(struct i40e_adapter),
 648 };
 649
 650 static inline int
 651 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 652                                      struct rte_eth_link *link)
 653 {
 654         struct rte_eth_link *dst = link;
 655         struct rte_eth_link *src = &(dev->data->dev_link);
 656
 657         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 658                                         *(uint64_t *)src) == 0)
 659                 return -1;
 660
 661         return 0;
 662 }
 663
 664 static inline int
 665 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 666                                       struct rte_eth_link *link)
 667 {
 668         struct rte_eth_link *dst = &(dev->data->dev_link);
 669         struct rte_eth_link *src = link;
 670
 671         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 672                                         *(uint64_t *)src) == 0)
 673                 return -1;
 674
 675         return 0;
 676 }
 677
 678 /*
 679  * Driver initialization routine.
 680  * Invoked once at EAL init time.
 681  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 682  */
 683 static int
 684 rte_i40e_pmd_init(const char *name __rte_unused,
 685                   const char *params __rte_unused)
 686 {
 687         PMD_INIT_FUNC_TRACE();
 688         rte_eth_driver_register(&rte_i40e_pmd);
 689
 690         return 0;
 691 }
 692
 693 static struct rte_driver rte_i40e_driver = {
 694         .type = PMD_PDEV,
 695         .init = rte_i40e_pmd_init,
 696 };
 697
 698 PMD_REGISTER_DRIVER(rte_i40e_driver);
 699
 700 /*
 701  * Initialize registers for flexible payload, which should be set by NVM.
 702  * This should be removed from code once it is fixed in NVM.
 703  */
 704 #ifndef I40E_GLQF_ORT
 705 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 706 #endif
 707 #ifndef I40E_GLQF_PIT
 708 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 709 #endif
 710
 711 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 712 {
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 716         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 720         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 723
 724         /* GLQF_PIT Registers */
 725         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 726         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 727 }
 728
 729 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 730
 731 /*
 732  * Add a ethertype filter to drop all flow control frames transmitted
 733  * from VSIs.
 734 */
 735 static void
 736 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 737 {
 738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 739         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 740                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 741                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 742         int ret;
 743
 744         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 745                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 746                                 pf->main_vsi_seid, 0,
 747                                 TRUE, NULL, NULL);
 748         if (ret)
 749                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 750                                   " frames from VSIs.");
 751 }
 752
 753 static int
 754 eth_i40e_dev_init(struct rte_eth_dev *dev)
 755 {
 756         struct rte_pci_device *pci_dev;
 757         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 759         struct i40e_vsi *vsi;
 760         int ret;
 761         uint32_t len;
 762         uint8_t aq_fail = 0;
 763
 764         PMD_INIT_FUNC_TRACE();
 765
 766         dev->dev_ops = &i40e_eth_dev_ops;
 767         dev->rx_pkt_burst = i40e_recv_pkts;
 768         dev->tx_pkt_burst = i40e_xmit_pkts;
 769
 770         /* for secondary processes, we don't initialise any further as primary
 771          * has already done this work. Only check we don't need a different
 772          * RX function */
 773         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 774                 i40e_set_rx_function(dev);
 775                 i40e_set_tx_function(dev);
 776                 return 0;
 777         }
 778         pci_dev = dev->pci_dev;
 779
 780         rte_eth_copy_pci_info(dev, pci_dev);
 781
 782         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 783         pf->adapter->eth_dev = dev;
 784         pf->dev_data = dev->data;
 785
 786         hw->back = I40E_PF_TO_ADAPTER(pf);
 787         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 788         if (!hw->hw_addr) {
 789                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 790                              "as address is NULL");
 791                 return -ENODEV;
 792         }
 793
 794         hw->vendor_id = pci_dev->id.vendor_id;
 795         hw->device_id = pci_dev->id.device_id;
 796         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 797         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 798         hw->bus.device = pci_dev->addr.devid;
 799         hw->bus.func = pci_dev->addr.function;
 800         hw->adapter_stopped = 0;
 801
 802         /* Make sure all is clean before doing PF reset */
 803         i40e_clear_hw(hw);
 804
 805         /* Initialize the hardware */
 806         i40e_hw_init(dev);
 807
 808         /* Reset here to make sure all is clean for each PF */
 809         ret = i40e_pf_reset(hw);
 810         if (ret) {
 811                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 812                 return ret;
 813         }
 814
 815         /* Initialize the shared code (base driver) */
 816         ret = i40e_init_shared_code(hw);
 817         if (ret) {
 818                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 819                 return ret;
 820         }
 821
 822         /*
 823          * To work around the NVM issue,initialize registers
 824          * for flexible payload by software.
 825          * It should be removed once issues are fixed in NVM.
 826          */
 827         i40e_flex_payload_reg_init(hw);
 828
 829         /* Initialize the input set for filters (hash and fd) to default value */
 830         i40e_filter_input_set_init(pf);
 831
 832         /* Initialize the parameters for adminq */
 833         i40e_init_adminq_parameter(hw);
 834         ret = i40e_init_adminq(hw);
 835         if (ret != I40E_SUCCESS) {
 836                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 837                 return -EIO;
 838         }
 839         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 840                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 841                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 842                      ((hw->nvm.version >> 12) & 0xf),
 843                      ((hw->nvm.version >> 4) & 0xff),
 844                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 845
 846         /* Clear PXE mode */
 847         i40e_clear_pxe_mode(hw);
 848
 849         /*
 850          * On X710, performance number is far from the expectation on recent
 851          * firmware versions. The fix for this issue may not be integrated in
 852          * the following firmware version. So the workaround in software driver
 853          * is needed. It needs to modify the initial values of 3 internal only
 854          * registers. Note that the workaround can be removed when it is fixed
 855          * in firmware in the future.
 856          */
 857         i40e_configure_registers(hw);
 858
 859         /* Get hw capabilities */
 860         ret = i40e_get_cap(hw);
 861         if (ret != I40E_SUCCESS) {
 862                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 863                 goto err_get_capabilities;
 864         }
 865
 866         /* Initialize parameters for PF */
 867         ret = i40e_pf_parameter_init(dev);
 868         if (ret != 0) {
 869                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 870                 goto err_parameter_init;
 871         }
 872
 873         /* Initialize the queue management */
 874         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 875         if (ret < 0) {
 876                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 877                 goto err_qp_pool_init;
 878         }
 879         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 880                                 hw->func_caps.num_msix_vectors - 1);
 881         if (ret < 0) {
 882                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 883                 goto err_msix_pool_init;
 884         }
 885
 886         /* Initialize lan hmc */
 887         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 888                                 hw->func_caps.num_rx_qp, 0, 0);
 889         if (ret != I40E_SUCCESS) {
 890                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 891                 goto err_init_lan_hmc;
 892         }
 893
 894         /* Configure lan hmc */
 895         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 896         if (ret != I40E_SUCCESS) {
 897                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 898                 goto err_configure_lan_hmc;
 899         }
 900
 901         /* Get and check the mac address */
 902         i40e_get_mac_addr(hw, hw->mac.addr);
 903         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 904                 PMD_INIT_LOG(ERR, "mac address is not valid");
 905                 ret = -EIO;
 906                 goto err_get_mac_addr;
 907         }
 908         /* Copy the permanent MAC address */
 909         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 910                         (struct ether_addr *) hw->mac.perm_addr);
 911
 912         /* Disable flow control */
 913         hw->fc.requested_mode = I40E_FC_NONE;
 914         i40e_set_fc(hw, &aq_fail, TRUE);
 915
 916         /* Set the global registers with default ether type value */
 917         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 918         if (ret != I40E_SUCCESS) {
 919                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 920                              "VLAN ether type");
 921                 goto err_setup_pf_switch;
 922         }
 923         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 924         if (ret != I40E_SUCCESS) {
 925                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 926                              "VLAN ether type");
 927                 goto err_setup_pf_switch;
 928         }
 929
 930         /* PF setup, which includes VSI setup */
 931         ret = i40e_pf_setup(pf);
 932         if (ret) {
 933                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 934                 goto err_setup_pf_switch;
 935         }
 936
 937         vsi = pf->main_vsi;
 938
 939         /* Disable double vlan by default */
 940         i40e_vsi_config_double_vlan(vsi, FALSE);
 941
 942         if (!vsi->max_macaddrs)
 943                 len = ETHER_ADDR_LEN;
 944         else
 945                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 946
 947         /* Should be after VSI initialized */
 948         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 949         if (!dev->data->mac_addrs) {
 950                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 951                                         "for storing mac address");
 952                 goto err_mac_alloc;
 953         }
 954         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 955                                         &dev->data->mac_addrs[0]);
 956
 957         /* initialize pf host driver to setup SRIOV resource if applicable */
 958         i40e_pf_host_init(dev);
 959
 960         /* register callback func to eal lib */
 961         rte_intr_callback_register(&(pci_dev->intr_handle),
 962                 i40e_dev_interrupt_handler, (void *)dev);
 963
 964         /* configure and enable device interrupt */
 965         i40e_pf_config_irq0(hw, TRUE);
 966         i40e_pf_enable_irq0(hw);
 967
 968         /* enable uio intr after callback register */
 969         rte_intr_enable(&(pci_dev->intr_handle));
 970         /*
 971          * Add an ethertype filter to drop all flow control frames transmitted
 972          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 973          * frames to wire.
 974          */
 975         i40e_add_tx_flow_control_drop_filter(pf);
 976
 977         /* Set the max frame size to 0x2600 by default,
 978          * in case other drivers changed the default value.
 979          */
 980         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 981
 982         /* initialize mirror rule list */
 983         TAILQ_INIT(&pf->mirror_list);
 984
 985         /* Init dcb to sw mode by default */
 986         ret = i40e_dcb_init_configure(dev, TRUE);
 987         if (ret != I40E_SUCCESS) {
 988                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 989                 pf->flags &= ~I40E_FLAG_DCB;
 990         }
 991
 992         return 0;
 993
 994 err_mac_alloc:
 995         i40e_vsi_release(pf->main_vsi);
 996 err_setup_pf_switch:
 997 err_get_mac_addr:
 998 err_configure_lan_hmc:
 999         (void)i40e_shutdown_lan_hmc(hw);
1000 err_init_lan_hmc:
1001         i40e_res_pool_destroy(&pf->msix_pool);
1002 err_msix_pool_init:
1003         i40e_res_pool_destroy(&pf->qp_pool);
1004 err_qp_pool_init:
1005 err_parameter_init:
1006 err_get_capabilities:
1007         (void)i40e_shutdown_adminq(hw);
1008
1009         return ret;
1010 }
1011
1012 static int
1013 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1014 {
1015         struct rte_pci_device *pci_dev;
1016         struct i40e_hw *hw;
1017         struct i40e_filter_control_settings settings;
1018         int ret;
1019         uint8_t aq_fail = 0;
1020
1021         PMD_INIT_FUNC_TRACE();
1022
1023         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1024                 return 0;
1025
1026         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027         pci_dev = dev->pci_dev;
1028
1029         if (hw->adapter_stopped == 0)
1030                 i40e_dev_close(dev);
1031
1032         dev->dev_ops = NULL;
1033         dev->rx_pkt_burst = NULL;
1034         dev->tx_pkt_burst = NULL;
1035
1036         /* Disable LLDP */
1037         ret = i40e_aq_stop_lldp(hw, true, NULL);
1038         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1039                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1040
1041         /* Clear PXE mode */
1042         i40e_clear_pxe_mode(hw);
1043
1044         /* Unconfigure filter control */
1045         memset(&settings, 0, sizeof(settings));
1046         ret = i40e_set_filter_control(hw, &settings);
1047         if (ret)
1048                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1049                                         ret);
1050
1051         /* Disable flow control */
1052         hw->fc.requested_mode = I40E_FC_NONE;
1053         i40e_set_fc(hw, &aq_fail, TRUE);
1054
1055         /* uninitialize pf host driver */
1056         i40e_pf_host_uninit(dev);
1057
1058         rte_free(dev->data->mac_addrs);
1059         dev->data->mac_addrs = NULL;
1060
1061         /* disable uio intr before callback unregister */
1062         rte_intr_disable(&(pci_dev->intr_handle));
1063
1064         /* register callback func to eal lib */
1065         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1066                 i40e_dev_interrupt_handler, (void *)dev);
1067
1068         return 0;
1069 }
1070
1071 static int
1072 i40e_dev_configure(struct rte_eth_dev *dev)
1073 {
1074         struct i40e_adapter *ad =
1075                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1076         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1077         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1078         int i, ret;
1079
1080         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1081          * bulk allocation or vector Rx preconditions we will reset it.
1082          */
1083         ad->rx_bulk_alloc_allowed = true;
1084         ad->rx_vec_allowed = true;
1085         ad->tx_simple_allowed = true;
1086         ad->tx_vec_allowed = true;
1087
1088         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1089                 ret = i40e_fdir_setup(pf);
1090                 if (ret != I40E_SUCCESS) {
1091                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1092                         return -ENOTSUP;
1093                 }
1094                 ret = i40e_fdir_configure(dev);
1095                 if (ret < 0) {
1096                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1097                         goto err;
1098                 }
1099         } else
1100                 i40e_fdir_teardown(pf);
1101
1102         ret = i40e_dev_init_vlan(dev);
1103         if (ret < 0)
1104                 goto err;
1105
1106         /* VMDQ setup.
1107          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1108          *  RSS setting have different requirements.
1109          *  General PMD driver call sequence are NIC init, configure,
1110          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1111          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1112          *  applicable. So, VMDQ setting has to be done before
1113          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1114          *  For RSS setting, it will try to calculate actual configured RX queue
1115          *  number, which will be available after rx_queue_setup(). dev_start()
1116          *  function is good to place RSS setup.
1117          */
1118         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1119                 ret = i40e_vmdq_setup(dev);
1120                 if (ret)
1121                         goto err;
1122         }
1123
1124         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1125                 ret = i40e_dcb_setup(dev);
1126                 if (ret) {
1127                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1128                         goto err_dcb;
1129                 }
1130         }
1131
1132         return 0;
1133
1134 err_dcb:
1135         /* need to release vmdq resource if exists */
1136         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1137                 i40e_vsi_release(pf->vmdq[i].vsi);
1138                 pf->vmdq[i].vsi = NULL;
1139         }
1140         rte_free(pf->vmdq);
1141         pf->vmdq = NULL;
1142 err:
1143         /* need to release fdir resource if exists */
1144         i40e_fdir_teardown(pf);
1145         return ret;
1146 }
1147
1148 void
1149 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1150 {
1151         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1152         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1153         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1154         uint16_t msix_vect = vsi->msix_intr;
1155         uint16_t i;
1156
1157         for (i = 0; i < vsi->nb_qps; i++) {
1158                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1159                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1160                 rte_wmb();
1161         }
1162
1163         if (vsi->type != I40E_VSI_SRIOV) {
1164                 if (!rte_intr_allow_others(intr_handle)) {
1165                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1166                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1167                         I40E_WRITE_REG(hw,
1168                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1169                                        0);
1170                 } else {
1171                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1172                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1173                         I40E_WRITE_REG(hw,
1174                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1175                                                        msix_vect - 1), 0);
1176                 }
1177         } else {
1178                 uint32_t reg;
1179                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1180                         vsi->user_param + (msix_vect - 1);
1181
1182                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1183                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1184         }
1185         I40E_WRITE_FLUSH(hw);
1186 }
1187
1188 static void
1189 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1190                        int base_queue, int nb_queue)
1191 {
1192         int i;
1193         uint32_t val;
1194         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1195
1196         /* Bind all RX queues to allocated MSIX interrupt */
1197         for (i = 0; i < nb_queue; i++) {
1198                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1199                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1200                         ((base_queue + i + 1) <<
1201                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1202                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1203                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1204
1205                 if (i == nb_queue - 1)
1206                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1207                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1208         }
1209
1210         /* Write first RX queue to Link list register as the head element */
1211         if (vsi->type != I40E_VSI_SRIOV) {
1212                 uint16_t interval =
1213                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1214
1215                 if (msix_vect == I40E_MISC_VEC_ID) {
1216                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1217                                        (base_queue <<
1218                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1219                                        (0x0 <<
1220                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1221                         I40E_WRITE_REG(hw,
1222                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1223                                        interval);
1224                 } else {
1225                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1226                                        (base_queue <<
1227                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1228                                        (0x0 <<
1229                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1230                         I40E_WRITE_REG(hw,
1231                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1232                                                        msix_vect - 1),
1233                                        interval);
1234                 }
1235         } else {
1236                 uint32_t reg;
1237
1238                 if (msix_vect == I40E_MISC_VEC_ID) {
1239                         I40E_WRITE_REG(hw,
1240                                        I40E_VPINT_LNKLST0(vsi->user_param),
1241                                        (base_queue <<
1242                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1243                                        (0x0 <<
1244                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1245                 } else {
1246                         /* num_msix_vectors_vf needs to minus irq0 */
1247                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1248                                 vsi->user_param + (msix_vect - 1);
1249
1250                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1251                                        (base_queue <<
1252                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1253                                        (0x0 <<
1254                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1255                 }
1256         }
1257
1258         I40E_WRITE_FLUSH(hw);
1259 }
1260
1261 void
1262 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1263 {
1264         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1265         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1266         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1267         uint16_t msix_vect = vsi->msix_intr;
1268         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1269         uint16_t queue_idx = 0;
1270         int record = 0;
1271         uint32_t val;
1272         int i;
1273
1274         for (i = 0; i < vsi->nb_qps; i++) {
1275                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1276                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1277         }
1278
1279         /* INTENA flag is not auto-cleared for interrupt */
1280         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1281         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1282                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1283                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1284         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1285
1286         /* VF bind interrupt */
1287         if (vsi->type == I40E_VSI_SRIOV) {
1288                 __vsi_queues_bind_intr(vsi, msix_vect,
1289                                        vsi->base_queue, vsi->nb_qps);
1290                 return;
1291         }
1292
1293         /* PF & VMDq bind interrupt */
1294         if (rte_intr_dp_is_en(intr_handle)) {
1295                 if (vsi->type == I40E_VSI_MAIN) {
1296                         queue_idx = 0;
1297                         record = 1;
1298                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1299                         struct i40e_vsi *main_vsi =
1300                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1301                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1302                         record = 1;
1303                 }
1304         }
1305
1306         for (i = 0; i < vsi->nb_used_qps; i++) {
1307                 if (nb_msix <= 1) {
1308                         if (!rte_intr_allow_others(intr_handle))
1309                                 /* allow to share MISC_VEC_ID */
1310                                 msix_vect = I40E_MISC_VEC_ID;
1311
1312                         /* no enough msix_vect, map all to one */
1313                         __vsi_queues_bind_intr(vsi, msix_vect,
1314                                                vsi->base_queue + i,
1315                                                vsi->nb_used_qps - i);
1316                         for (; !!record && i < vsi->nb_used_qps; i++)
1317                                 intr_handle->intr_vec[queue_idx + i] =
1318                                         msix_vect;
1319                         break;
1320                 }
1321                 /* 1:1 queue/msix_vect mapping */
1322                 __vsi_queues_bind_intr(vsi, msix_vect,
1323                                        vsi->base_queue + i, 1);
1324                 if (!!record)
1325                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1326
1327                 msix_vect++;
1328                 nb_msix--;
1329         }
1330 }
1331
1332 static void
1333 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1334 {
1335         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1336         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1337         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1338         uint16_t interval = i40e_calc_itr_interval(\
1339                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1340         uint16_t msix_intr, i;
1341
1342         if (rte_intr_allow_others(intr_handle))
1343                 for (i = 0; i < vsi->nb_msix; i++) {
1344                         msix_intr = vsi->msix_intr + i;
1345                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1346                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1347                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1348                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1349                                 (interval <<
1350                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1351                 }
1352         else
1353                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1354                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1355                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1356                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1357                                (interval <<
1358                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1359
1360         I40E_WRITE_FLUSH(hw);
1361 }
1362
1363 static void
1364 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1365 {
1366         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1367         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1368         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1369         uint16_t msix_intr, i;
1370
1371         if (rte_intr_allow_others(intr_handle))
1372                 for (i = 0; i < vsi->nb_msix; i++) {
1373                         msix_intr = vsi->msix_intr + i;
1374                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1375                                        0);
1376                 }
1377         else
1378                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1379
1380         I40E_WRITE_FLUSH(hw);
1381 }
1382
1383 static inline uint8_t
1384 i40e_parse_link_speeds(uint16_t link_speeds)
1385 {
1386         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1387
1388         if (link_speeds & ETH_LINK_SPEED_40G)
1389                 link_speed |= I40E_LINK_SPEED_40GB;
1390         if (link_speeds & ETH_LINK_SPEED_20G)
1391                 link_speed |= I40E_LINK_SPEED_20GB;
1392         if (link_speeds & ETH_LINK_SPEED_10G)
1393                 link_speed |= I40E_LINK_SPEED_10GB;
1394         if (link_speeds & ETH_LINK_SPEED_1G)
1395                 link_speed |= I40E_LINK_SPEED_1GB;
1396         if (link_speeds & ETH_LINK_SPEED_100M)
1397                 link_speed |= I40E_LINK_SPEED_100MB;
1398
1399         return link_speed;
1400 }
1401
1402 static int
1403 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1404                    __rte_unused uint8_t abilities,
1405                    __rte_unused uint8_t force_speed)
1406 {
1407         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1408          * for the link control limitation of that all link control should be
1409          * handled by firmware. It should follow up if link control will be
1410          * opened to software driver in future firmware versions.
1411          */
1412         return I40E_SUCCESS;
1413 }
1414
1415 static int
1416 i40e_apply_link_speed(struct rte_eth_dev *dev)
1417 {
1418         uint8_t speed;
1419         uint8_t abilities = 0;
1420         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421         struct rte_eth_conf *conf = &dev->data->dev_conf;
1422
1423         speed = i40e_parse_link_speeds(conf->link_speeds);
1424         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1425         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1426                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1427         else
1428                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1429
1430         return i40e_phy_conf_link(hw, abilities, speed);
1431 }
1432
1433 static int
1434 i40e_dev_start(struct rte_eth_dev *dev)
1435 {
1436         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1437         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1438         struct i40e_vsi *main_vsi = pf->main_vsi;
1439         int ret, i;
1440         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1441         uint32_t intr_vector = 0;
1442
1443         hw->adapter_stopped = 0;
1444
1445         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1446                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1447                              dev->data->port_id);
1448                 return -EINVAL;
1449         }
1450
1451         rte_intr_disable(intr_handle);
1452
1453         if ((rte_intr_cap_multiple(intr_handle) ||
1454              !RTE_ETH_DEV_SRIOV(dev).active) &&
1455             dev->data->dev_conf.intr_conf.rxq != 0) {
1456                 intr_vector = dev->data->nb_rx_queues;
1457                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1458                         return -1;
1459         }
1460
1461         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1462                 intr_handle->intr_vec =
1463                         rte_zmalloc("intr_vec",
1464                                     dev->data->nb_rx_queues * sizeof(int),
1465                                     0);
1466                 if (!intr_handle->intr_vec) {
1467                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1468                                      " intr_vec\n", dev->data->nb_rx_queues);
1469                         return -ENOMEM;
1470                 }
1471         }
1472
1473         /* Initialize VSI */
1474         ret = i40e_dev_rxtx_init(pf);
1475         if (ret != I40E_SUCCESS) {
1476                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1477                 goto err_up;
1478         }
1479
1480         /* Map queues with MSIX interrupt */
1481         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1482                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1483         i40e_vsi_queues_bind_intr(main_vsi);
1484         i40e_vsi_enable_queues_intr(main_vsi);
1485
1486         /* Map VMDQ VSI queues with MSIX interrupt */
1487         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1488                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1489                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1490                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1491         }
1492
1493         /* enable FDIR MSIX interrupt */
1494         if (pf->fdir.fdir_vsi) {
1495                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1496                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1497         }
1498
1499         /* Enable all queues which have been configured */
1500         ret = i40e_dev_switch_queues(pf, TRUE);
1501         if (ret != I40E_SUCCESS) {
1502                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1503                 goto err_up;
1504         }
1505
1506         /* Enable receiving broadcast packets */
1507         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1508         if (ret != I40E_SUCCESS)
1509                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1510
1511         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1512                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1513                                                 true, NULL);
1514                 if (ret != I40E_SUCCESS)
1515                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1516         }
1517
1518         /* Apply link configure */
1519         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1520                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1521                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1522                 PMD_DRV_LOG(ERR, "Invalid link setting");
1523                 goto err_up;
1524         }
1525         ret = i40e_apply_link_speed(dev);
1526         if (I40E_SUCCESS != ret) {
1527                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1528                 goto err_up;
1529         }
1530
1531         if (!rte_intr_allow_others(intr_handle)) {
1532                 rte_intr_callback_unregister(intr_handle,
1533                                              i40e_dev_interrupt_handler,
1534                                              (void *)dev);
1535                 /* configure and enable device interrupt */
1536                 i40e_pf_config_irq0(hw, FALSE);
1537                 i40e_pf_enable_irq0(hw);
1538
1539                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1540                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1541                                      " no intr multiplex\n");
1542         }
1543
1544         /* enable uio intr after callback register */
1545         rte_intr_enable(intr_handle);
1546
1547         return I40E_SUCCESS;
1548
1549 err_up:
1550         i40e_dev_switch_queues(pf, FALSE);
1551         i40e_dev_clear_queues(dev);
1552
1553         return ret;
1554 }
1555
1556 static void
1557 i40e_dev_stop(struct rte_eth_dev *dev)
1558 {
1559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1560         struct i40e_vsi *main_vsi = pf->main_vsi;
1561         struct i40e_mirror_rule *p_mirror;
1562         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1563         int i;
1564
1565         /* Disable all queues */
1566         i40e_dev_switch_queues(pf, FALSE);
1567
1568         /* un-map queues with interrupt registers */
1569         i40e_vsi_disable_queues_intr(main_vsi);
1570         i40e_vsi_queues_unbind_intr(main_vsi);
1571
1572         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1573                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1574                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1575         }
1576
1577         if (pf->fdir.fdir_vsi) {
1578                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1579                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1580         }
1581         /* Clear all queues and release memory */
1582         i40e_dev_clear_queues(dev);
1583
1584         /* Set link down */
1585         i40e_dev_set_link_down(dev);
1586
1587         /* Remove all mirror rules */
1588         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1589                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1590                 rte_free(p_mirror);
1591         }
1592         pf->nb_mirror_rule = 0;
1593
1594         if (!rte_intr_allow_others(intr_handle))
1595                 /* resume to the default handler */
1596                 rte_intr_callback_register(intr_handle,
1597                                            i40e_dev_interrupt_handler,
1598                                            (void *)dev);
1599
1600         /* Clean datapath event and queue/vec mapping */
1601         rte_intr_efd_disable(intr_handle);
1602         if (intr_handle->intr_vec) {
1603                 rte_free(intr_handle->intr_vec);
1604                 intr_handle->intr_vec = NULL;
1605         }
1606 }
1607
1608 static void
1609 i40e_dev_close(struct rte_eth_dev *dev)
1610 {
1611         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1612         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         uint32_t reg;
1614         int i;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         i40e_dev_stop(dev);
1619         hw->adapter_stopped = 1;
1620         i40e_dev_free_queues(dev);
1621
1622         /* Disable interrupt */
1623         i40e_pf_disable_irq0(hw);
1624         rte_intr_disable(&(dev->pci_dev->intr_handle));
1625
1626         /* shutdown and destroy the HMC */
1627         i40e_shutdown_lan_hmc(hw);
1628
1629         /* release all the existing VSIs and VEBs */
1630         i40e_fdir_teardown(pf);
1631         i40e_vsi_release(pf->main_vsi);
1632
1633         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1634                 i40e_vsi_release(pf->vmdq[i].vsi);
1635                 pf->vmdq[i].vsi = NULL;
1636         }
1637
1638         rte_free(pf->vmdq);
1639         pf->vmdq = NULL;
1640
1641         /* shutdown the adminq */
1642         i40e_aq_queue_shutdown(hw, true);
1643         i40e_shutdown_adminq(hw);
1644
1645         i40e_res_pool_destroy(&pf->qp_pool);
1646         i40e_res_pool_destroy(&pf->msix_pool);
1647
1648         /* force a PF reset to clean anything leftover */
1649         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1650         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1651                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1652         I40E_WRITE_FLUSH(hw);
1653 }
1654
1655 static void
1656 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1657 {
1658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         struct i40e_vsi *vsi = pf->main_vsi;
1661         int status;
1662
1663         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1664                                                         true, NULL);
1665         if (status != I40E_SUCCESS)
1666                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1667
1668         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1669                                                         TRUE, NULL);
1670         if (status != I40E_SUCCESS)
1671                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1672
1673 }
1674
1675 static void
1676 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1677 {
1678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680         struct i40e_vsi *vsi = pf->main_vsi;
1681         int status;
1682
1683         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1684                                                         false, NULL);
1685         if (status != I40E_SUCCESS)
1686                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1687
1688         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1689                                                         false, NULL);
1690         if (status != I40E_SUCCESS)
1691                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1692 }
1693
1694 static void
1695 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1696 {
1697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1698         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699         struct i40e_vsi *vsi = pf->main_vsi;
1700         int ret;
1701
1702         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1703         if (ret != I40E_SUCCESS)
1704                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1705 }
1706
1707 static void
1708 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1709 {
1710         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712         struct i40e_vsi *vsi = pf->main_vsi;
1713         int ret;
1714
1715         if (dev->data->promiscuous == 1)
1716                 return; /* must remain in all_multicast mode */
1717
1718         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1719                                 vsi->seid, FALSE, NULL);
1720         if (ret != I40E_SUCCESS)
1721                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1722 }
1723
1724 /*
1725  * Set device link up.
1726  */
1727 static int
1728 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1729 {
1730         /* re-apply link speed setting */
1731         return i40e_apply_link_speed(dev);
1732 }
1733
1734 /*
1735  * Set device link down.
1736  */
1737 static int
1738 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1739 {
1740         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1741         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1742         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743
1744         return i40e_phy_conf_link(hw, abilities, speed);
1745 }
1746
1747 int
1748 i40e_dev_link_update(struct rte_eth_dev *dev,
1749                      int wait_to_complete)
1750 {
1751 #define CHECK_INTERVAL 100  /* 100ms */
1752 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1753         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754         struct i40e_link_status link_status;
1755         struct rte_eth_link link, old;
1756         int status;
1757         unsigned rep_cnt = MAX_REPEAT_TIME;
1758
1759         memset(&link, 0, sizeof(link));
1760         memset(&old, 0, sizeof(old));
1761         memset(&link_status, 0, sizeof(link_status));
1762         rte_i40e_dev_atomic_read_link_status(dev, &old);
1763
1764         do {
1765                 /* Get link status information from hardware */
1766                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1767                 if (status != I40E_SUCCESS) {
1768                         link.link_speed = ETH_SPEED_NUM_100M;
1769                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1770                         PMD_DRV_LOG(ERR, "Failed to get link info");
1771                         goto out;
1772                 }
1773
1774                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1775                 if (!wait_to_complete)
1776                         break;
1777
1778                 rte_delay_ms(CHECK_INTERVAL);
1779         } while (!link.link_status && rep_cnt--);
1780
1781         if (!link.link_status)
1782                 goto out;
1783
1784         /* i40e uses full duplex only */
1785         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1786
1787         /* Parse the link status */
1788         switch (link_status.link_speed) {
1789         case I40E_LINK_SPEED_100MB:
1790                 link.link_speed = ETH_SPEED_NUM_100M;
1791                 break;
1792         case I40E_LINK_SPEED_1GB:
1793                 link.link_speed = ETH_SPEED_NUM_1G;
1794                 break;
1795         case I40E_LINK_SPEED_10GB:
1796                 link.link_speed = ETH_SPEED_NUM_10G;
1797                 break;
1798         case I40E_LINK_SPEED_20GB:
1799                 link.link_speed = ETH_SPEED_NUM_20G;
1800                 break;
1801         case I40E_LINK_SPEED_40GB:
1802                 link.link_speed = ETH_SPEED_NUM_40G;
1803                 break;
1804         default:
1805                 link.link_speed = ETH_SPEED_NUM_100M;
1806                 break;
1807         }
1808
1809         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1810                         ETH_LINK_SPEED_FIXED);
1811
1812 out:
1813         rte_i40e_dev_atomic_write_link_status(dev, &link);
1814         if (link.link_status == old.link_status)
1815                 return -1;
1816
1817         return 0;
1818 }
1819
1820 /* Get all the statistics of a VSI */
1821 void
1822 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1823 {
1824         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1825         struct i40e_eth_stats *nes = &vsi->eth_stats;
1826         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1827         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1828
1829         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1830                             vsi->offset_loaded, &oes->rx_bytes,
1831                             &nes->rx_bytes);
1832         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1833                             vsi->offset_loaded, &oes->rx_unicast,
1834                             &nes->rx_unicast);
1835         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1836                             vsi->offset_loaded, &oes->rx_multicast,
1837                             &nes->rx_multicast);
1838         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1839                             vsi->offset_loaded, &oes->rx_broadcast,
1840                             &nes->rx_broadcast);
1841         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1842                             &oes->rx_discards, &nes->rx_discards);
1843         /* GLV_REPC not supported */
1844         /* GLV_RMPC not supported */
1845         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1846                             &oes->rx_unknown_protocol,
1847                             &nes->rx_unknown_protocol);
1848         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1849                             vsi->offset_loaded, &oes->tx_bytes,
1850                             &nes->tx_bytes);
1851         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1852                             vsi->offset_loaded, &oes->tx_unicast,
1853                             &nes->tx_unicast);
1854         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1855                             vsi->offset_loaded, &oes->tx_multicast,
1856                             &nes->tx_multicast);
1857         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1858                             vsi->offset_loaded,  &oes->tx_broadcast,
1859                             &nes->tx_broadcast);
1860         /* GLV_TDPC not supported */
1861         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1862                             &oes->tx_errors, &nes->tx_errors);
1863         vsi->offset_loaded = true;
1864
1865         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1866                     vsi->vsi_id);
1867         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1868         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1869         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1870         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1871         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1872         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1873                     nes->rx_unknown_protocol);
1874         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1875         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1876         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1877         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1878         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1879         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1880         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1881                     vsi->vsi_id);
1882 }
1883
1884 static void
1885 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1886 {
1887         unsigned int i;
1888         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1889         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1890
1891         /* Get statistics of struct i40e_eth_stats */
1892         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1893                             I40E_GLPRT_GORCL(hw->port),
1894                             pf->offset_loaded, &os->eth.rx_bytes,
1895                             &ns->eth.rx_bytes);
1896         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1897                             I40E_GLPRT_UPRCL(hw->port),
1898                             pf->offset_loaded, &os->eth.rx_unicast,
1899                             &ns->eth.rx_unicast);
1900         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1901                             I40E_GLPRT_MPRCL(hw->port),
1902                             pf->offset_loaded, &os->eth.rx_multicast,
1903                             &ns->eth.rx_multicast);
1904         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1905                             I40E_GLPRT_BPRCL(hw->port),
1906                             pf->offset_loaded, &os->eth.rx_broadcast,
1907                             &ns->eth.rx_broadcast);
1908         /* Workaround: CRC size should not be included in byte statistics,
1909          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1910          */
1911         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1912                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1913
1914         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1915                             pf->offset_loaded, &os->eth.rx_discards,
1916                             &ns->eth.rx_discards);
1917         /* GLPRT_REPC not supported */
1918         /* GLPRT_RMPC not supported */
1919         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1920                             pf->offset_loaded,
1921                             &os->eth.rx_unknown_protocol,
1922                             &ns->eth.rx_unknown_protocol);
1923         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1924                             I40E_GLPRT_GOTCL(hw->port),
1925                             pf->offset_loaded, &os->eth.tx_bytes,
1926                             &ns->eth.tx_bytes);
1927         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1928                             I40E_GLPRT_UPTCL(hw->port),
1929                             pf->offset_loaded, &os->eth.tx_unicast,
1930                             &ns->eth.tx_unicast);
1931         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1932                             I40E_GLPRT_MPTCL(hw->port),
1933                             pf->offset_loaded, &os->eth.tx_multicast,
1934                             &ns->eth.tx_multicast);
1935         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1936                             I40E_GLPRT_BPTCL(hw->port),
1937                             pf->offset_loaded, &os->eth.tx_broadcast,
1938                             &ns->eth.tx_broadcast);
1939         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1940                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1941         /* GLPRT_TEPC not supported */
1942
1943         /* additional port specific stats */
1944         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1945                             pf->offset_loaded, &os->tx_dropped_link_down,
1946                             &ns->tx_dropped_link_down);
1947         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1948                             pf->offset_loaded, &os->crc_errors,
1949                             &ns->crc_errors);
1950         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1951                             pf->offset_loaded, &os->illegal_bytes,
1952                             &ns->illegal_bytes);
1953         /* GLPRT_ERRBC not supported */
1954         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1955                             pf->offset_loaded, &os->mac_local_faults,
1956                             &ns->mac_local_faults);
1957         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1958                             pf->offset_loaded, &os->mac_remote_faults,
1959                             &ns->mac_remote_faults);
1960         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1961                             pf->offset_loaded, &os->rx_length_errors,
1962                             &ns->rx_length_errors);
1963         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1964                             pf->offset_loaded, &os->link_xon_rx,
1965                             &ns->link_xon_rx);
1966         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1967                             pf->offset_loaded, &os->link_xoff_rx,
1968                             &ns->link_xoff_rx);
1969         for (i = 0; i < 8; i++) {
1970                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1971                                     pf->offset_loaded,
1972                                     &os->priority_xon_rx[i],
1973                                     &ns->priority_xon_rx[i]);
1974                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1975                                     pf->offset_loaded,
1976                                     &os->priority_xoff_rx[i],
1977                                     &ns->priority_xoff_rx[i]);
1978         }
1979         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1980                             pf->offset_loaded, &os->link_xon_tx,
1981                             &ns->link_xon_tx);
1982         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1983                             pf->offset_loaded, &os->link_xoff_tx,
1984                             &ns->link_xoff_tx);
1985         for (i = 0; i < 8; i++) {
1986                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1987                                     pf->offset_loaded,
1988                                     &os->priority_xon_tx[i],
1989                                     &ns->priority_xon_tx[i]);
1990                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1991                                     pf->offset_loaded,
1992                                     &os->priority_xoff_tx[i],
1993                                     &ns->priority_xoff_tx[i]);
1994                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1995                                     pf->offset_loaded,
1996                                     &os->priority_xon_2_xoff[i],
1997                                     &ns->priority_xon_2_xoff[i]);
1998         }
1999         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2000                             I40E_GLPRT_PRC64L(hw->port),
2001                             pf->offset_loaded, &os->rx_size_64,
2002                             &ns->rx_size_64);
2003         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2004                             I40E_GLPRT_PRC127L(hw->port),
2005                             pf->offset_loaded, &os->rx_size_127,
2006                             &ns->rx_size_127);
2007         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2008                             I40E_GLPRT_PRC255L(hw->port),
2009                             pf->offset_loaded, &os->rx_size_255,
2010                             &ns->rx_size_255);
2011         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2012                             I40E_GLPRT_PRC511L(hw->port),
2013                             pf->offset_loaded, &os->rx_size_511,
2014                             &ns->rx_size_511);
2015         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2016                             I40E_GLPRT_PRC1023L(hw->port),
2017                             pf->offset_loaded, &os->rx_size_1023,
2018                             &ns->rx_size_1023);
2019         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2020                             I40E_GLPRT_PRC1522L(hw->port),
2021                             pf->offset_loaded, &os->rx_size_1522,
2022                             &ns->rx_size_1522);
2023         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2024                             I40E_GLPRT_PRC9522L(hw->port),
2025                             pf->offset_loaded, &os->rx_size_big,
2026                             &ns->rx_size_big);
2027         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2028                             pf->offset_loaded, &os->rx_undersize,
2029                             &ns->rx_undersize);
2030         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2031                             pf->offset_loaded, &os->rx_fragments,
2032                             &ns->rx_fragments);
2033         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2034                             pf->offset_loaded, &os->rx_oversize,
2035                             &ns->rx_oversize);
2036         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2037                             pf->offset_loaded, &os->rx_jabber,
2038                             &ns->rx_jabber);
2039         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2040                             I40E_GLPRT_PTC64L(hw->port),
2041                             pf->offset_loaded, &os->tx_size_64,
2042                             &ns->tx_size_64);
2043         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2044                             I40E_GLPRT_PTC127L(hw->port),
2045                             pf->offset_loaded, &os->tx_size_127,
2046                             &ns->tx_size_127);
2047         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2048                             I40E_GLPRT_PTC255L(hw->port),
2049                             pf->offset_loaded, &os->tx_size_255,
2050                             &ns->tx_size_255);
2051         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2052                             I40E_GLPRT_PTC511L(hw->port),
2053                             pf->offset_loaded, &os->tx_size_511,
2054                             &ns->tx_size_511);
2055         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2056                             I40E_GLPRT_PTC1023L(hw->port),
2057                             pf->offset_loaded, &os->tx_size_1023,
2058                             &ns->tx_size_1023);
2059         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2060                             I40E_GLPRT_PTC1522L(hw->port),
2061                             pf->offset_loaded, &os->tx_size_1522,
2062                             &ns->tx_size_1522);
2063         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2064                             I40E_GLPRT_PTC9522L(hw->port),
2065                             pf->offset_loaded, &os->tx_size_big,
2066                             &ns->tx_size_big);
2067         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2068                            pf->offset_loaded,
2069                            &os->fd_sb_match, &ns->fd_sb_match);
2070         /* GLPRT_MSPDC not supported */
2071         /* GLPRT_XEC not supported */
2072
2073         pf->offset_loaded = true;
2074
2075         if (pf->main_vsi)
2076                 i40e_update_vsi_stats(pf->main_vsi);
2077 }
2078
2079 /* Get all statistics of a port */
2080 static void
2081 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2082 {
2083         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2086         unsigned i;
2087
2088         /* call read registers - updates values, now write them to struct */
2089         i40e_read_stats_registers(pf, hw);
2090
2091         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2092                         pf->main_vsi->eth_stats.rx_multicast +
2093                         pf->main_vsi->eth_stats.rx_broadcast -
2094                         pf->main_vsi->eth_stats.rx_discards;
2095         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2096                         pf->main_vsi->eth_stats.tx_multicast +
2097                         pf->main_vsi->eth_stats.tx_broadcast;
2098         stats->ibytes   = ns->eth.rx_bytes;
2099         stats->obytes   = ns->eth.tx_bytes;
2100         stats->oerrors  = ns->eth.tx_errors +
2101                         pf->main_vsi->eth_stats.tx_errors;
2102         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2103
2104         /* Rx Errors */
2105         stats->imissed  = ns->eth.rx_discards +
2106                         pf->main_vsi->eth_stats.rx_discards;
2107         stats->ierrors  = ns->crc_errors +
2108                         ns->rx_length_errors + ns->rx_undersize +
2109                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2110
2111         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2112         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2113         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2114         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2115         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2116         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2117         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2118                     ns->eth.rx_unknown_protocol);
2119         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2120         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2121         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2122         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2123         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2124         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2125
2126         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2127                     ns->tx_dropped_link_down);
2128         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2129         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2130                     ns->illegal_bytes);
2131         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2132         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2133                     ns->mac_local_faults);
2134         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2135                     ns->mac_remote_faults);
2136         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2137                     ns->rx_length_errors);
2138         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2139         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2140         for (i = 0; i < 8; i++) {
2141                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2142                                 i, ns->priority_xon_rx[i]);
2143                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2144                                 i, ns->priority_xoff_rx[i]);
2145         }
2146         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2147         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2148         for (i = 0; i < 8; i++) {
2149                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2150                                 i, ns->priority_xon_tx[i]);
2151                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2152                                 i, ns->priority_xoff_tx[i]);
2153                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2154                                 i, ns->priority_xon_2_xoff[i]);
2155         }
2156         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2157         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2158         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2159         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2160         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2161         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2162         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2163         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2164         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2165         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2166         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2167         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2168         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2169         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2170         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2171         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2172         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2173         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2174         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2175                         ns->mac_short_packet_dropped);
2176         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2177                     ns->checksum_error);
2178         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2179         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2180 }
2181
2182 /* Reset the statistics */
2183 static void
2184 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2185 {
2186         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188
2189         /* Mark PF and VSI stats to update the offset, aka "reset" */
2190         pf->offset_loaded = false;
2191         if (pf->main_vsi)
2192                 pf->main_vsi->offset_loaded = false;
2193
2194         /* read the stats, reading current register values into offset */
2195         i40e_read_stats_registers(pf, hw);
2196 }
2197
2198 static uint32_t
2199 i40e_xstats_calc_num(void)
2200 {
2201         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2202                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2203                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2204 }
2205
2206 static int
2207 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2208                     unsigned n)
2209 {
2210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         unsigned i, count, prio;
2213         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2214
2215         count = i40e_xstats_calc_num();
2216         if (n < count)
2217                 return count;
2218
2219         i40e_read_stats_registers(pf, hw);
2220
2221         if (xstats == NULL)
2222                 return 0;
2223
2224         count = 0;
2225
2226         /* Get stats from i40e_eth_stats struct */
2227         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2228                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2229                          "%s", rte_i40e_stats_strings[i].name);
2230                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2231                         rte_i40e_stats_strings[i].offset);
2232                 count++;
2233         }
2234
2235         /* Get individiual stats from i40e_hw_port struct */
2236         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2237                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2238                          "%s", rte_i40e_hw_port_strings[i].name);
2239                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2240                                 rte_i40e_hw_port_strings[i].offset);
2241                 count++;
2242         }
2243
2244         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2245                 for (prio = 0; prio < 8; prio++) {
2246                         snprintf(xstats[count].name,
2247                                  sizeof(xstats[count].name),
2248                                  "rx_priority%u_%s", prio,
2249                                  rte_i40e_rxq_prio_strings[i].name);
2250                         xstats[count].value =
2251                                 *(uint64_t *)(((char *)hw_stats) +
2252                                 rte_i40e_rxq_prio_strings[i].offset +
2253                                 (sizeof(uint64_t) * prio));
2254                         count++;
2255                 }
2256         }
2257
2258         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2259                 for (prio = 0; prio < 8; prio++) {
2260                         snprintf(xstats[count].name,
2261                                  sizeof(xstats[count].name),
2262                                  "tx_priority%u_%s", prio,
2263                                  rte_i40e_txq_prio_strings[i].name);
2264                         xstats[count].value =
2265                                 *(uint64_t *)(((char *)hw_stats) +
2266                                 rte_i40e_txq_prio_strings[i].offset +
2267                                 (sizeof(uint64_t) * prio));
2268                         count++;
2269                 }
2270         }
2271
2272         return count;
2273 }
2274
2275 static int
2276 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2277                                  __rte_unused uint16_t queue_id,
2278                                  __rte_unused uint8_t stat_idx,
2279                                  __rte_unused uint8_t is_rx)
2280 {
2281         PMD_INIT_FUNC_TRACE();
2282
2283         return -ENOSYS;
2284 }
2285
2286 static void
2287 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2288 {
2289         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2290         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         struct i40e_vsi *vsi = pf->main_vsi;
2292
2293         dev_info->max_rx_queues = vsi->nb_qps;
2294         dev_info->max_tx_queues = vsi->nb_qps;
2295         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2296         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2297         dev_info->max_mac_addrs = vsi->max_macaddrs;
2298         dev_info->max_vfs = dev->pci_dev->max_vfs;
2299         dev_info->rx_offload_capa =
2300                 DEV_RX_OFFLOAD_VLAN_STRIP |
2301                 DEV_RX_OFFLOAD_QINQ_STRIP |
2302                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2303                 DEV_RX_OFFLOAD_UDP_CKSUM |
2304                 DEV_RX_OFFLOAD_TCP_CKSUM;
2305         dev_info->tx_offload_capa =
2306                 DEV_TX_OFFLOAD_VLAN_INSERT |
2307                 DEV_TX_OFFLOAD_QINQ_INSERT |
2308                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2309                 DEV_TX_OFFLOAD_UDP_CKSUM |
2310                 DEV_TX_OFFLOAD_TCP_CKSUM |
2311                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2312                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2313                 DEV_TX_OFFLOAD_TCP_TSO;
2314         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2315                                                 sizeof(uint32_t);
2316         dev_info->reta_size = pf->hash_lut_size;
2317         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2318
2319         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2320                 .rx_thresh = {
2321                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2322                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2323                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2324                 },
2325                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2326                 .rx_drop_en = 0,
2327         };
2328
2329         dev_info->default_txconf = (struct rte_eth_txconf) {
2330                 .tx_thresh = {
2331                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2332                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2333                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2334                 },
2335                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2336                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2337                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2338                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2339         };
2340
2341         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2342                 .nb_max = I40E_MAX_RING_DESC,
2343                 .nb_min = I40E_MIN_RING_DESC,
2344                 .nb_align = I40E_ALIGN_RING_DESC,
2345         };
2346
2347         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2348                 .nb_max = I40E_MAX_RING_DESC,
2349                 .nb_min = I40E_MIN_RING_DESC,
2350                 .nb_align = I40E_ALIGN_RING_DESC,
2351         };
2352
2353         if (pf->flags & I40E_FLAG_VMDQ) {
2354                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2355                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2356                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2357                                                 pf->max_nb_vmdq_vsi;
2358                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2359                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2360                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2361         }
2362
2363         if (i40e_is_40G_device(hw->device_id))
2364                 /* For XL710 */
2365                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2366         else
2367                 /* For X710 */
2368                 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2369 }
2370
2371 static int
2372 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2373 {
2374         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2375         struct i40e_vsi *vsi = pf->main_vsi;
2376         PMD_INIT_FUNC_TRACE();
2377
2378         if (on)
2379                 return i40e_vsi_add_vlan(vsi, vlan_id);
2380         else
2381                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2382 }
2383
2384 static int
2385 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2386                    enum rte_vlan_type vlan_type,
2387                    uint16_t tpid)
2388 {
2389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390         uint64_t reg_r = 0, reg_w = 0;
2391         uint16_t reg_id = 0;
2392         int ret = 0;
2393
2394         switch (vlan_type) {
2395         case ETH_VLAN_TYPE_OUTER:
2396                 reg_id = 2;
2397                 break;
2398         case ETH_VLAN_TYPE_INNER:
2399                 reg_id = 3;
2400                 break;
2401         default:
2402                 ret = -EINVAL;
2403                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2404                 return ret;
2405         }
2406         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2407                                           &reg_r, NULL);
2408         if (ret != I40E_SUCCESS) {
2409                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2410                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2411                 ret = -EIO;
2412                 return ret;
2413         }
2414         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2415                     "0x%08"PRIx64"", reg_id, reg_r);
2416
2417         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2418         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2419         if (reg_r == reg_w) {
2420                 ret = 0;
2421                 PMD_DRV_LOG(DEBUG, "No need to write");
2422                 return ret;
2423         }
2424
2425         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2426                                            reg_w, NULL);
2427         if (ret != I40E_SUCCESS) {
2428                 ret = -EIO;
2429                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2430                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2431                 return ret;
2432         }
2433         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2434                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2435
2436         return ret;
2437 }
2438
2439 static void
2440 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2441 {
2442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2443         struct i40e_vsi *vsi = pf->main_vsi;
2444
2445         if (mask & ETH_VLAN_FILTER_MASK) {
2446                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2447                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2448                 else
2449                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2450         }
2451
2452         if (mask & ETH_VLAN_STRIP_MASK) {
2453                 /* Enable or disable VLAN stripping */
2454                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2455                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2456                 else
2457                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2458         }
2459
2460         if (mask & ETH_VLAN_EXTEND_MASK) {
2461                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2462                         i40e_vsi_config_double_vlan(vsi, TRUE);
2463                 else
2464                         i40e_vsi_config_double_vlan(vsi, FALSE);
2465         }
2466 }
2467
2468 static void
2469 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2470                           __rte_unused uint16_t queue,
2471                           __rte_unused int on)
2472 {
2473         PMD_INIT_FUNC_TRACE();
2474 }
2475
2476 static int
2477 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2478 {
2479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2480         struct i40e_vsi *vsi = pf->main_vsi;
2481         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2482         struct i40e_vsi_vlan_pvid_info info;
2483
2484         memset(&info, 0, sizeof(info));
2485         info.on = on;
2486         if (info.on)
2487                 info.config.pvid = pvid;
2488         else {
2489                 info.config.reject.tagged =
2490                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2491                 info.config.reject.untagged =
2492                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2493         }
2494
2495         return i40e_vsi_vlan_pvid_set(vsi, &info);
2496 }
2497
2498 static int
2499 i40e_dev_led_on(struct rte_eth_dev *dev)
2500 {
2501         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502         uint32_t mode = i40e_led_get(hw);
2503
2504         if (mode == 0)
2505                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2506
2507         return 0;
2508 }
2509
2510 static int
2511 i40e_dev_led_off(struct rte_eth_dev *dev)
2512 {
2513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514         uint32_t mode = i40e_led_get(hw);
2515
2516         if (mode != 0)
2517                 i40e_led_set(hw, 0, false);
2518
2519         return 0;
2520 }
2521
2522 static int
2523 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2524 {
2525         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2527
2528         fc_conf->pause_time = pf->fc_conf.pause_time;
2529         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2530         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2531
2532          /* Return current mode according to actual setting*/
2533         switch (hw->fc.current_mode) {
2534         case I40E_FC_FULL:
2535                 fc_conf->mode = RTE_FC_FULL;
2536                 break;
2537         case I40E_FC_TX_PAUSE:
2538                 fc_conf->mode = RTE_FC_TX_PAUSE;
2539                 break;
2540         case I40E_FC_RX_PAUSE:
2541                 fc_conf->mode = RTE_FC_RX_PAUSE;
2542                 break;
2543         case I40E_FC_NONE:
2544         default:
2545                 fc_conf->mode = RTE_FC_NONE;
2546         };
2547
2548         return 0;
2549 }
2550
2551 static int
2552 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2553 {
2554         uint32_t mflcn_reg, fctrl_reg, reg;
2555         uint32_t max_high_water;
2556         uint8_t i, aq_failure;
2557         int err;
2558         struct i40e_hw *hw;
2559         struct i40e_pf *pf;
2560         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2561                 [RTE_FC_NONE] = I40E_FC_NONE,
2562                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2563                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2564                 [RTE_FC_FULL] = I40E_FC_FULL
2565         };
2566
2567         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2568
2569         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2570         if ((fc_conf->high_water > max_high_water) ||
2571                         (fc_conf->high_water < fc_conf->low_water)) {
2572                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2573                         "High_water must <= %d.", max_high_water);
2574                 return -EINVAL;
2575         }
2576
2577         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2579         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2580
2581         pf->fc_conf.pause_time = fc_conf->pause_time;
2582         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2583         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2584
2585         PMD_INIT_FUNC_TRACE();
2586
2587         /* All the link flow control related enable/disable register
2588          * configuration is handle by the F/W
2589          */
2590         err = i40e_set_fc(hw, &aq_failure, true);
2591         if (err < 0)
2592                 return -ENOSYS;
2593
2594         if (i40e_is_40G_device(hw->device_id)) {
2595                 /* Configure flow control refresh threshold,
2596                  * the value for stat_tx_pause_refresh_timer[8]
2597                  * is used for global pause operation.
2598                  */
2599
2600                 I40E_WRITE_REG(hw,
2601                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2602                                pf->fc_conf.pause_time);
2603
2604                 /* configure the timer value included in transmitted pause
2605                  * frame,
2606                  * the value for stat_tx_pause_quanta[8] is used for global
2607                  * pause operation
2608                  */
2609                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2610                                pf->fc_conf.pause_time);
2611
2612                 fctrl_reg = I40E_READ_REG(hw,
2613                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2614
2615                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2616                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2617                 else
2618                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2619
2620                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2621                                fctrl_reg);
2622         } else {
2623                 /* Configure pause time (2 TCs per register) */
2624                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2625                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2626                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2627
2628                 /* Configure flow control refresh threshold value */
2629                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2630                                pf->fc_conf.pause_time / 2);
2631
2632                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2633
2634                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2635                  *depending on configuration
2636                  */
2637                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2638                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2639                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2640                 } else {
2641                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2642                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2643                 }
2644
2645                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2646         }
2647
2648         /* config the water marker both based on the packets and bytes */
2649         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2650                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2651                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2652         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2653                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2654                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2655         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2656                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2657                        << I40E_KILOSHIFT);
2658         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2659                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2660                        << I40E_KILOSHIFT);
2661
2662         I40E_WRITE_FLUSH(hw);
2663
2664         return 0;
2665 }
2666
2667 static int
2668 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2669                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2670 {
2671         PMD_INIT_FUNC_TRACE();
2672
2673         return -ENOSYS;
2674 }
2675
2676 /* Add a MAC address, and update filters */
2677 static void
2678 i40e_macaddr_add(struct rte_eth_dev *dev,
2679                  struct ether_addr *mac_addr,
2680                  __rte_unused uint32_t index,
2681                  uint32_t pool)
2682 {
2683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2684         struct i40e_mac_filter_info mac_filter;
2685         struct i40e_vsi *vsi;
2686         int ret;
2687
2688         /* If VMDQ not enabled or configured, return */
2689         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2690                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2691                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2692                         pool);
2693                 return;
2694         }
2695
2696         if (pool > pf->nb_cfg_vmdq_vsi) {
2697                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2698                                 pool, pf->nb_cfg_vmdq_vsi);
2699                 return;
2700         }
2701
2702         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2703         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2704                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2705         else
2706                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2707
2708         if (pool == 0)
2709                 vsi = pf->main_vsi;
2710         else
2711                 vsi = pf->vmdq[pool - 1].vsi;
2712
2713         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2714         if (ret != I40E_SUCCESS) {
2715                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2716                 return;
2717         }
2718 }
2719
2720 /* Remove a MAC address, and update filters */
2721 static void
2722 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2723 {
2724         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2725         struct i40e_vsi *vsi;
2726         struct rte_eth_dev_data *data = dev->data;
2727         struct ether_addr *macaddr;
2728         int ret;
2729         uint32_t i;
2730         uint64_t pool_sel;
2731
2732         macaddr = &(data->mac_addrs[index]);
2733
2734         pool_sel = dev->data->mac_pool_sel[index];
2735
2736         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2737                 if (pool_sel & (1ULL << i)) {
2738                         if (i == 0)
2739                                 vsi = pf->main_vsi;
2740                         else {
2741                                 /* No VMDQ pool enabled or configured */
2742                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2743                                         (i > pf->nb_cfg_vmdq_vsi)) {
2744                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2745                                                         "/configured");
2746                                         return;
2747                                 }
2748                                 vsi = pf->vmdq[i - 1].vsi;
2749                         }
2750                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2751
2752                         if (ret) {
2753                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2754                                 return;
2755                         }
2756                 }
2757         }
2758 }
2759
2760 /* Set perfect match or hash match of MAC and VLAN for a VF */
2761 static int
2762 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2763                  struct rte_eth_mac_filter *filter,
2764                  bool add)
2765 {
2766         struct i40e_hw *hw;
2767         struct i40e_mac_filter_info mac_filter;
2768         struct ether_addr old_mac;
2769         struct ether_addr *new_mac;
2770         struct i40e_pf_vf *vf = NULL;
2771         uint16_t vf_id;
2772         int ret;
2773
2774         if (pf == NULL) {
2775                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2776                 return -EINVAL;
2777         }
2778         hw = I40E_PF_TO_HW(pf);
2779
2780         if (filter == NULL) {
2781                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2782                 return -EINVAL;
2783         }
2784
2785         new_mac = &filter->mac_addr;
2786
2787         if (is_zero_ether_addr(new_mac)) {
2788                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2789                 return -EINVAL;
2790         }
2791
2792         vf_id = filter->dst_id;
2793
2794         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2795                 PMD_DRV_LOG(ERR, "Invalid argument.");
2796                 return -EINVAL;
2797         }
2798         vf = &pf->vfs[vf_id];
2799
2800         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2801                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2802                 return -EINVAL;
2803         }
2804
2805         if (add) {
2806                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2807                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2808                                 ETHER_ADDR_LEN);
2809                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2810                                  ETHER_ADDR_LEN);
2811
2812                 mac_filter.filter_type = filter->filter_type;
2813                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2814                 if (ret != I40E_SUCCESS) {
2815                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2816                         return -1;
2817                 }
2818                 ether_addr_copy(new_mac, &pf->dev_addr);
2819         } else {
2820                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2821                                 ETHER_ADDR_LEN);
2822                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2823                 if (ret != I40E_SUCCESS) {
2824                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2825                         return -1;
2826                 }
2827
2828                 /* Clear device address as it has been removed */
2829                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2830                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2831         }
2832
2833         return 0;
2834 }
2835
2836 /* MAC filter handle */
2837 static int
2838 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2839                 void *arg)
2840 {
2841         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2842         struct rte_eth_mac_filter *filter;
2843         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2844         int ret = I40E_NOT_SUPPORTED;
2845
2846         filter = (struct rte_eth_mac_filter *)(arg);
2847
2848         switch (filter_op) {
2849         case RTE_ETH_FILTER_NOP:
2850                 ret = I40E_SUCCESS;
2851                 break;
2852         case RTE_ETH_FILTER_ADD:
2853                 i40e_pf_disable_irq0(hw);
2854                 if (filter->is_vf)
2855                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2856                 i40e_pf_enable_irq0(hw);
2857                 break;
2858         case RTE_ETH_FILTER_DELETE:
2859                 i40e_pf_disable_irq0(hw);
2860                 if (filter->is_vf)
2861                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2862                 i40e_pf_enable_irq0(hw);
2863                 break;
2864         default:
2865                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2866                 ret = I40E_ERR_PARAM;
2867                 break;
2868         }
2869
2870         return ret;
2871 }
2872
2873 static int
2874 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2875 {
2876         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2877         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2878         int ret;
2879
2880         if (!lut)
2881                 return -EINVAL;
2882
2883         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2884                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2885                                           lut, lut_size);
2886                 if (ret) {
2887                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2888                         return ret;
2889                 }
2890         } else {
2891                 uint32_t *lut_dw = (uint32_t *)lut;
2892                 uint16_t i, lut_size_dw = lut_size / 4;
2893
2894                 for (i = 0; i < lut_size_dw; i++)
2895                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2896         }
2897
2898         return 0;
2899 }
2900
2901 static int
2902 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2903 {
2904         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2905         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2906         int ret;
2907
2908         if (!vsi || !lut)
2909                 return -EINVAL;
2910
2911         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2912                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2913                                           lut, lut_size);
2914                 if (ret) {
2915                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2916                         return ret;
2917                 }
2918         } else {
2919                 uint32_t *lut_dw = (uint32_t *)lut;
2920                 uint16_t i, lut_size_dw = lut_size / 4;
2921
2922                 for (i = 0; i < lut_size_dw; i++)
2923                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2924                 I40E_WRITE_FLUSH(hw);
2925         }
2926
2927         return 0;
2928 }
2929
2930 static int
2931 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2932                          struct rte_eth_rss_reta_entry64 *reta_conf,
2933                          uint16_t reta_size)
2934 {
2935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2936         uint16_t i, lut_size = pf->hash_lut_size;
2937         uint16_t idx, shift;
2938         uint8_t *lut;
2939         int ret;
2940
2941         if (reta_size != lut_size ||
2942                 reta_size > ETH_RSS_RETA_SIZE_512) {
2943                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2944                         "(%d) doesn't match the number hardware can supported "
2945                                         "(%d)\n", reta_size, lut_size);
2946                 return -EINVAL;
2947         }
2948
2949         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2950         if (!lut) {
2951                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2952                 return -ENOMEM;
2953         }
2954         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2955         if (ret)
2956                 goto out;
2957         for (i = 0; i < reta_size; i++) {
2958                 idx = i / RTE_RETA_GROUP_SIZE;
2959                 shift = i % RTE_RETA_GROUP_SIZE;
2960                 if (reta_conf[idx].mask & (1ULL << shift))
2961                         lut[i] = reta_conf[idx].reta[shift];
2962         }
2963         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2964
2965 out:
2966         rte_free(lut);
2967
2968         return ret;
2969 }
2970
2971 static int
2972 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2973                         struct rte_eth_rss_reta_entry64 *reta_conf,
2974                         uint16_t reta_size)
2975 {
2976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2977         uint16_t i, lut_size = pf->hash_lut_size;
2978         uint16_t idx, shift;
2979         uint8_t *lut;
2980         int ret;
2981
2982         if (reta_size != lut_size ||
2983                 reta_size > ETH_RSS_RETA_SIZE_512) {
2984                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2985                         "(%d) doesn't match the number hardware can supported "
2986                                         "(%d)\n", reta_size, lut_size);
2987                 return -EINVAL;
2988         }
2989
2990         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2991         if (!lut) {
2992                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2993                 return -ENOMEM;
2994         }
2995
2996         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2997         if (ret)
2998                 goto out;
2999         for (i = 0; i < reta_size; i++) {
3000                 idx = i / RTE_RETA_GROUP_SIZE;
3001                 shift = i % RTE_RETA_GROUP_SIZE;
3002                 if (reta_conf[idx].mask & (1ULL << shift))
3003                         reta_conf[idx].reta[shift] = lut[i];
3004         }
3005
3006 out:
3007         rte_free(lut);
3008
3009         return ret;
3010 }
3011
3012 /**
3013  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3014  * @hw:   pointer to the HW structure
3015  * @mem:  pointer to mem struct to fill out
3016  * @size: size of memory requested
3017  * @alignment: what to align the allocation to
3018  **/
3019 enum i40e_status_code
3020 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3021                         struct i40e_dma_mem *mem,
3022                         u64 size,
3023                         u32 alignment)
3024 {
3025         const struct rte_memzone *mz = NULL;
3026         char z_name[RTE_MEMZONE_NAMESIZE];
3027
3028         if (!mem)
3029                 return I40E_ERR_PARAM;
3030
3031         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3032         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3033                                          alignment, RTE_PGSIZE_2M);
3034         if (!mz)
3035                 return I40E_ERR_NO_MEMORY;
3036
3037         mem->size = size;
3038         mem->va = mz->addr;
3039         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3040         mem->zone = (const void *)mz;
3041         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3042                     "%"PRIu64, mz->name, mem->pa);
3043
3044         return I40E_SUCCESS;
3045 }
3046
3047 /**
3048  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3049  * @hw:   pointer to the HW structure
3050  * @mem:  ptr to mem struct to free
3051  **/
3052 enum i40e_status_code
3053 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3054                     struct i40e_dma_mem *mem)
3055 {
3056         if (!mem)
3057                 return I40E_ERR_PARAM;
3058
3059         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3060                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3061                     mem->pa);
3062         rte_memzone_free((const struct rte_memzone *)mem->zone);
3063         mem->zone = NULL;
3064         mem->va = NULL;
3065         mem->pa = (u64)0;
3066
3067         return I40E_SUCCESS;
3068 }
3069
3070 /**
3071  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3072  * @hw:   pointer to the HW structure
3073  * @mem:  pointer to mem struct to fill out
3074  * @size: size of memory requested
3075  **/
3076 enum i40e_status_code
3077 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3078                          struct i40e_virt_mem *mem,
3079                          u32 size)
3080 {
3081         if (!mem)
3082                 return I40E_ERR_PARAM;
3083
3084         mem->size = size;
3085         mem->va = rte_zmalloc("i40e", size, 0);
3086
3087         if (mem->va)
3088                 return I40E_SUCCESS;
3089         else
3090                 return I40E_ERR_NO_MEMORY;
3091 }
3092
3093 /**
3094  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3095  * @hw:   pointer to the HW structure
3096  * @mem:  pointer to mem struct to free
3097  **/
3098 enum i40e_status_code
3099 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3100                      struct i40e_virt_mem *mem)
3101 {
3102         if (!mem)
3103                 return I40E_ERR_PARAM;
3104
3105         rte_free(mem->va);
3106         mem->va = NULL;
3107
3108         return I40E_SUCCESS;
3109 }
3110
3111 void
3112 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3113 {
3114         rte_spinlock_init(&sp->spinlock);
3115 }
3116
3117 void
3118 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3119 {
3120         rte_spinlock_lock(&sp->spinlock);
3121 }
3122
3123 void
3124 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3125 {
3126         rte_spinlock_unlock(&sp->spinlock);
3127 }
3128
3129 void
3130 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3131 {
3132         return;
3133 }
3134
3135 /**
3136  * Get the hardware capabilities, which will be parsed
3137  * and saved into struct i40e_hw.
3138  */
3139 static int
3140 i40e_get_cap(struct i40e_hw *hw)
3141 {
3142         struct i40e_aqc_list_capabilities_element_resp *buf;
3143         uint16_t len, size = 0;
3144         int ret;
3145
3146         /* Calculate a huge enough buff for saving response data temporarily */
3147         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3148                                                 I40E_MAX_CAP_ELE_NUM;
3149         buf = rte_zmalloc("i40e", len, 0);
3150         if (!buf) {
3151                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3152                 return I40E_ERR_NO_MEMORY;
3153         }
3154
3155         /* Get, parse the capabilities and save it to hw */
3156         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3157                         i40e_aqc_opc_list_func_capabilities, NULL);
3158         if (ret != I40E_SUCCESS)
3159                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3160
3161         /* Free the temporary buffer after being used */
3162         rte_free(buf);
3163
3164         return ret;
3165 }
3166
3167 static int
3168 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3169 {
3170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3172         uint16_t qp_count = 0, vsi_count = 0;
3173
3174         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3175                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3176                 return -EINVAL;
3177         }
3178         /* Add the parameter init for LFC */
3179         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3180         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3181         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3182
3183         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3184         pf->max_num_vsi = hw->func_caps.num_vsis;
3185         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3186         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3187         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3188
3189         /* FDir queue/VSI allocation */
3190         pf->fdir_qp_offset = 0;
3191         if (hw->func_caps.fd) {
3192                 pf->flags |= I40E_FLAG_FDIR;
3193                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3194         } else {
3195                 pf->fdir_nb_qps = 0;
3196         }
3197         qp_count += pf->fdir_nb_qps;
3198         vsi_count += 1;
3199
3200         /* LAN queue/VSI allocation */
3201         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3202         if (!hw->func_caps.rss) {
3203                 pf->lan_nb_qps = 1;
3204         } else {
3205                 pf->flags |= I40E_FLAG_RSS;
3206                 if (hw->mac.type == I40E_MAC_X722)
3207                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3208                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3209         }
3210         qp_count += pf->lan_nb_qps;
3211         vsi_count += 1;
3212
3213         /* VF queue/VSI allocation */
3214         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3215         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3216                 pf->flags |= I40E_FLAG_SRIOV;
3217                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3218                 pf->vf_num = dev->pci_dev->max_vfs;
3219                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3220                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3221                             pf->vf_nb_qps * pf->vf_num);
3222         } else {
3223                 pf->vf_nb_qps = 0;
3224                 pf->vf_num = 0;
3225         }
3226         qp_count += pf->vf_nb_qps * pf->vf_num;
3227         vsi_count += pf->vf_num;
3228
3229         /* VMDq queue/VSI allocation */
3230         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3231         pf->vmdq_nb_qps = 0;
3232         pf->max_nb_vmdq_vsi = 0;
3233         if (hw->func_caps.vmdq) {
3234                 if (qp_count < hw->func_caps.num_tx_qp &&
3235                         vsi_count < hw->func_caps.num_vsis) {
3236                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3237                                 qp_count) / pf->vmdq_nb_qp_max;
3238
3239                         /* Limit the maximum number of VMDq vsi to the maximum
3240                          * ethdev can support
3241                          */
3242                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3243                                 hw->func_caps.num_vsis - vsi_count);
3244                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3245                                 ETH_64_POOLS);
3246                         if (pf->max_nb_vmdq_vsi) {
3247                                 pf->flags |= I40E_FLAG_VMDQ;
3248                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3249                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3250                                             "per VMDQ VSI, in total %u queues",
3251                                             pf->max_nb_vmdq_vsi,
3252                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3253                                             pf->max_nb_vmdq_vsi);
3254                         } else {
3255                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3256                                             "VMDq");
3257                         }
3258                 } else {
3259                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3260                 }
3261         }
3262         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3263         vsi_count += pf->max_nb_vmdq_vsi;
3264
3265         if (hw->func_caps.dcb)
3266                 pf->flags |= I40E_FLAG_DCB;
3267
3268         if (qp_count > hw->func_caps.num_tx_qp) {
3269                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3270                             "the hardware maximum %u", qp_count,
3271                             hw->func_caps.num_tx_qp);
3272                 return -EINVAL;
3273         }
3274         if (vsi_count > hw->func_caps.num_vsis) {
3275                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3276                             "the hardware maximum %u", vsi_count,
3277                             hw->func_caps.num_vsis);
3278                 return -EINVAL;
3279         }
3280
3281         return 0;
3282 }
3283
3284 static int
3285 i40e_pf_get_switch_config(struct i40e_pf *pf)
3286 {
3287         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3288         struct i40e_aqc_get_switch_config_resp *switch_config;
3289         struct i40e_aqc_switch_config_element_resp *element;
3290         uint16_t start_seid = 0, num_reported;
3291         int ret;
3292
3293         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3294                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3295         if (!switch_config) {
3296                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3297                 return -ENOMEM;
3298         }
3299
3300         /* Get the switch configurations */
3301         ret = i40e_aq_get_switch_config(hw, switch_config,
3302                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3303         if (ret != I40E_SUCCESS) {
3304                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3305                 goto fail;
3306         }
3307         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3308         if (num_reported != 1) { /* The number should be 1 */
3309                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3310                 goto fail;
3311         }
3312
3313         /* Parse the switch configuration elements */
3314         element = &(switch_config->element[0]);
3315         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3316                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3317                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3318         } else
3319                 PMD_DRV_LOG(INFO, "Unknown element type");
3320
3321 fail:
3322         rte_free(switch_config);
3323
3324         return ret;
3325 }
3326
3327 static int
3328 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3329                         uint32_t num)
3330 {
3331         struct pool_entry *entry;
3332
3333         if (pool == NULL || num == 0)
3334                 return -EINVAL;
3335
3336         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3337         if (entry == NULL) {
3338                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3339                 return -ENOMEM;
3340         }
3341
3342         /* queue heap initialize */
3343         pool->num_free = num;
3344         pool->num_alloc = 0;
3345         pool->base = base;
3346         LIST_INIT(&pool->alloc_list);
3347         LIST_INIT(&pool->free_list);
3348
3349         /* Initialize element  */
3350         entry->base = 0;
3351         entry->len = num;
3352
3353         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3354         return 0;
3355 }
3356
3357 static void
3358 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3359 {
3360         struct pool_entry *entry, *next_entry;
3361
3362         if (pool == NULL)
3363                 return;
3364
3365         for (entry = LIST_FIRST(&pool->alloc_list);
3366                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3367                         entry = next_entry) {
3368                 LIST_REMOVE(entry, next);
3369                 rte_free(entry);
3370         }
3371
3372         for (entry = LIST_FIRST(&pool->free_list);
3373                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3374                         entry = next_entry) {
3375                 LIST_REMOVE(entry, next);
3376                 rte_free(entry);
3377         }
3378
3379         pool->num_free = 0;
3380         pool->num_alloc = 0;
3381         pool->base = 0;
3382         LIST_INIT(&pool->alloc_list);
3383         LIST_INIT(&pool->free_list);
3384 }
3385
3386 static int
3387 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3388                        uint32_t base)
3389 {
3390         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3391         uint32_t pool_offset;
3392         int insert;
3393
3394         if (pool == NULL) {
3395                 PMD_DRV_LOG(ERR, "Invalid parameter");
3396                 return -EINVAL;
3397         }
3398
3399         pool_offset = base - pool->base;
3400         /* Lookup in alloc list */
3401         LIST_FOREACH(entry, &pool->alloc_list, next) {
3402                 if (entry->base == pool_offset) {
3403                         valid_entry = entry;
3404                         LIST_REMOVE(entry, next);
3405                         break;
3406                 }
3407         }
3408
3409         /* Not find, return */
3410         if (valid_entry == NULL) {
3411                 PMD_DRV_LOG(ERR, "Failed to find entry");
3412                 return -EINVAL;
3413         }
3414
3415         /**
3416          * Found it, move it to free list  and try to merge.
3417          * In order to make merge easier, always sort it by qbase.
3418          * Find adjacent prev and last entries.
3419          */
3420         prev = next = NULL;
3421         LIST_FOREACH(entry, &pool->free_list, next) {
3422                 if (entry->base > valid_entry->base) {
3423                         next = entry;
3424                         break;
3425                 }
3426                 prev = entry;
3427         }
3428
3429         insert = 0;
3430         /* Try to merge with next one*/
3431         if (next != NULL) {
3432                 /* Merge with next one */
3433                 if (valid_entry->base + valid_entry->len == next->base) {
3434                         next->base = valid_entry->base;
3435                         next->len += valid_entry->len;
3436                         rte_free(valid_entry);
3437                         valid_entry = next;
3438                         insert = 1;
3439                 }
3440         }
3441
3442         if (prev != NULL) {
3443                 /* Merge with previous one */
3444                 if (prev->base + prev->len == valid_entry->base) {
3445                         prev->len += valid_entry->len;
3446                         /* If it merge with next one, remove next node */
3447                         if (insert == 1) {
3448                                 LIST_REMOVE(valid_entry, next);
3449                                 rte_free(valid_entry);
3450                         } else {
3451                                 rte_free(valid_entry);
3452                                 insert = 1;
3453                         }
3454                 }
3455         }
3456
3457         /* Not find any entry to merge, insert */
3458         if (insert == 0) {
3459                 if (prev != NULL)
3460                         LIST_INSERT_AFTER(prev, valid_entry, next);
3461                 else if (next != NULL)
3462                         LIST_INSERT_BEFORE(next, valid_entry, next);
3463                 else /* It's empty list, insert to head */
3464                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3465         }
3466
3467         pool->num_free += valid_entry->len;
3468         pool->num_alloc -= valid_entry->len;
3469
3470         return 0;
3471 }
3472
3473 static int
3474 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3475                        uint16_t num)
3476 {
3477         struct pool_entry *entry, *valid_entry;
3478
3479         if (pool == NULL || num == 0) {
3480                 PMD_DRV_LOG(ERR, "Invalid parameter");
3481                 return -EINVAL;
3482         }
3483
3484         if (pool->num_free < num) {
3485                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3486                             num, pool->num_free);
3487                 return -ENOMEM;
3488         }
3489
3490         valid_entry = NULL;
3491         /* Lookup  in free list and find most fit one */
3492         LIST_FOREACH(entry, &pool->free_list, next) {
3493                 if (entry->len >= num) {
3494                         /* Find best one */
3495                         if (entry->len == num) {
3496                                 valid_entry = entry;
3497                                 break;
3498                         }
3499                         if (valid_entry == NULL || valid_entry->len > entry->len)
3500                                 valid_entry = entry;
3501                 }
3502         }
3503
3504         /* Not find one to satisfy the request, return */
3505         if (valid_entry == NULL) {
3506                 PMD_DRV_LOG(ERR, "No valid entry found");
3507                 return -ENOMEM;
3508         }
3509         /**
3510          * The entry have equal queue number as requested,
3511          * remove it from alloc_list.
3512          */
3513         if (valid_entry->len == num) {
3514                 LIST_REMOVE(valid_entry, next);
3515         } else {
3516                 /**
3517                  * The entry have more numbers than requested,
3518                  * create a new entry for alloc_list and minus its
3519                  * queue base and number in free_list.
3520                  */
3521                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3522                 if (entry == NULL) {
3523                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3524                                     "resource pool");
3525                         return -ENOMEM;
3526                 }
3527                 entry->base = valid_entry->base;
3528                 entry->len = num;
3529                 valid_entry->base += num;
3530                 valid_entry->len -= num;
3531                 valid_entry = entry;
3532         }
3533
3534         /* Insert it into alloc list, not sorted */
3535         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3536
3537         pool->num_free -= valid_entry->len;
3538         pool->num_alloc += valid_entry->len;
3539
3540         return valid_entry->base + pool->base;
3541 }
3542
3543 /**
3544  * bitmap_is_subset - Check whether src2 is subset of src1
3545  **/
3546 static inline int
3547 bitmap_is_subset(uint8_t src1, uint8_t src2)
3548 {
3549         return !((src1 ^ src2) & src2);
3550 }
3551
3552 static enum i40e_status_code
3553 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3554 {
3555         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3556
3557         /* If DCB is not supported, only default TC is supported */
3558         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3559                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3560                 return I40E_NOT_SUPPORTED;
3561         }
3562
3563         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3564                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3565                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3566                             enabled_tcmap);
3567                 return I40E_NOT_SUPPORTED;
3568         }
3569         return I40E_SUCCESS;
3570 }
3571
3572 int
3573 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3574                                 struct i40e_vsi_vlan_pvid_info *info)
3575 {
3576         struct i40e_hw *hw;
3577         struct i40e_vsi_context ctxt;
3578         uint8_t vlan_flags = 0;
3579         int ret;
3580
3581         if (vsi == NULL || info == NULL) {
3582                 PMD_DRV_LOG(ERR, "invalid parameters");
3583                 return I40E_ERR_PARAM;
3584         }
3585
3586         if (info->on) {
3587                 vsi->info.pvid = info->config.pvid;
3588                 /**
3589                  * If insert pvid is enabled, only tagged pkts are
3590                  * allowed to be sent out.
3591                  */
3592                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3593                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3594         } else {
3595                 vsi->info.pvid = 0;
3596                 if (info->config.reject.tagged == 0)
3597                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3598
3599                 if (info->config.reject.untagged == 0)
3600                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3601         }
3602         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3603                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3604         vsi->info.port_vlan_flags |= vlan_flags;
3605         vsi->info.valid_sections =
3606                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3607         memset(&ctxt, 0, sizeof(ctxt));
3608         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3609         ctxt.seid = vsi->seid;
3610
3611         hw = I40E_VSI_TO_HW(vsi);
3612         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3613         if (ret != I40E_SUCCESS)
3614                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3615
3616         return ret;
3617 }
3618
3619 static int
3620 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3621 {
3622         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3623         int i, ret;
3624         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3625
3626         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3627         if (ret != I40E_SUCCESS)
3628                 return ret;
3629
3630         if (!vsi->seid) {
3631                 PMD_DRV_LOG(ERR, "seid not valid");
3632                 return -EINVAL;
3633         }
3634
3635         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3636         tc_bw_data.tc_valid_bits = enabled_tcmap;
3637         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3638                 tc_bw_data.tc_bw_credits[i] =
3639                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3640
3641         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3642         if (ret != I40E_SUCCESS) {
3643                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3644                 return ret;
3645         }
3646
3647         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3648                                         sizeof(vsi->info.qs_handle));
3649         return I40E_SUCCESS;
3650 }
3651
3652 static enum i40e_status_code
3653 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3654                                  struct i40e_aqc_vsi_properties_data *info,
3655                                  uint8_t enabled_tcmap)
3656 {
3657         enum i40e_status_code ret;
3658         int i, total_tc = 0;
3659         uint16_t qpnum_per_tc, bsf, qp_idx;
3660
3661         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3662         if (ret != I40E_SUCCESS)
3663                 return ret;
3664
3665         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3666                 if (enabled_tcmap & (1 << i))
3667                         total_tc++;
3668         vsi->enabled_tc = enabled_tcmap;
3669
3670         /* Number of queues per enabled TC */
3671         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3672         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3673         bsf = rte_bsf32(qpnum_per_tc);
3674
3675         /* Adjust the queue number to actual queues that can be applied */
3676         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3677                 vsi->nb_qps = qpnum_per_tc * total_tc;
3678
3679         /**
3680          * Configure TC and queue mapping parameters, for enabled TC,
3681          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3682          * default queue will serve it.
3683          */
3684         qp_idx = 0;
3685         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3686                 if (vsi->enabled_tc & (1 << i)) {
3687                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3688                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3689                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3690                         qp_idx += qpnum_per_tc;
3691                 } else
3692                         info->tc_mapping[i] = 0;
3693         }
3694
3695         /* Associate queue number with VSI */
3696         if (vsi->type == I40E_VSI_SRIOV) {
3697                 info->mapping_flags |=
3698                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3699                 for (i = 0; i < vsi->nb_qps; i++)
3700                         info->queue_mapping[i] =
3701                                 rte_cpu_to_le_16(vsi->base_queue + i);
3702         } else {
3703                 info->mapping_flags |=
3704                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3705                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3706         }
3707         info->valid_sections |=
3708                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3709
3710         return I40E_SUCCESS;
3711 }
3712
3713 static int
3714 i40e_veb_release(struct i40e_veb *veb)
3715 {
3716         struct i40e_vsi *vsi;
3717         struct i40e_hw *hw;
3718
3719         if (veb == NULL || veb->associate_vsi == NULL)
3720                 return -EINVAL;
3721
3722         if (!TAILQ_EMPTY(&veb->head)) {
3723                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3724                 return -EACCES;
3725         }
3726
3727         vsi = veb->associate_vsi;
3728         hw = I40E_VSI_TO_HW(vsi);
3729
3730         vsi->uplink_seid = veb->uplink_seid;
3731         i40e_aq_delete_element(hw, veb->seid, NULL);
3732         rte_free(veb);
3733         vsi->veb = NULL;
3734         return I40E_SUCCESS;
3735 }
3736
3737 /* Setup a veb */
3738 static struct i40e_veb *
3739 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3740 {
3741         struct i40e_veb *veb;
3742         int ret;
3743         struct i40e_hw *hw;
3744
3745         if (NULL == pf || vsi == NULL) {
3746                 PMD_DRV_LOG(ERR, "veb setup failed, "
3747                             "associated VSI shouldn't null");
3748                 return NULL;
3749         }
3750         hw = I40E_PF_TO_HW(pf);
3751
3752         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3753         if (!veb) {
3754                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3755                 goto fail;
3756         }
3757
3758         veb->associate_vsi = vsi;
3759         TAILQ_INIT(&veb->head);
3760         veb->uplink_seid = vsi->uplink_seid;
3761
3762         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3763                 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3764
3765         if (ret != I40E_SUCCESS) {
3766                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3767                             hw->aq.asq_last_status);
3768                 goto fail;
3769         }
3770
3771         /* get statistics index */
3772         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3773                                 &veb->stats_idx, NULL, NULL, NULL);
3774         if (ret != I40E_SUCCESS) {
3775                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3776                             hw->aq.asq_last_status);
3777                 goto fail;
3778         }
3779
3780         /* Get VEB bandwidth, to be implemented */
3781         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3782         vsi->uplink_seid = veb->seid;
3783
3784         return veb;
3785 fail:
3786         rte_free(veb);
3787         return NULL;
3788 }
3789
3790 int
3791 i40e_vsi_release(struct i40e_vsi *vsi)
3792 {
3793         struct i40e_pf *pf;
3794         struct i40e_hw *hw;
3795         struct i40e_vsi_list *vsi_list;
3796         int ret;
3797         struct i40e_mac_filter *f;
3798
3799         if (!vsi)
3800                 return I40E_SUCCESS;
3801
3802         pf = I40E_VSI_TO_PF(vsi);
3803         hw = I40E_VSI_TO_HW(vsi);
3804
3805         /* VSI has child to attach, release child first */
3806         if (vsi->veb) {
3807                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3808                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3809                                 return -1;
3810                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3811                 }
3812                 i40e_veb_release(vsi->veb);
3813         }
3814
3815         /* Remove all macvlan filters of the VSI */
3816         i40e_vsi_remove_all_macvlan_filter(vsi);
3817         TAILQ_FOREACH(f, &vsi->mac_list, next)
3818                 rte_free(f);
3819
3820         if (vsi->type != I40E_VSI_MAIN) {
3821                 /* Remove vsi from parent's sibling list */
3822                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3823                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3824                         return I40E_ERR_PARAM;
3825                 }
3826                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3827                                 &vsi->sib_vsi_list, list);
3828
3829                 /* Remove all switch element of the VSI */
3830                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3831                 if (ret != I40E_SUCCESS)
3832                         PMD_DRV_LOG(ERR, "Failed to delete element");
3833         }
3834         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3835
3836         if (vsi->type != I40E_VSI_SRIOV)
3837                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3838         rte_free(vsi);
3839
3840         return I40E_SUCCESS;
3841 }
3842
3843 static int
3844 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3845 {
3846         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3847         struct i40e_aqc_remove_macvlan_element_data def_filter;
3848         struct i40e_mac_filter_info filter;
3849         int ret;
3850
3851         if (vsi->type != I40E_VSI_MAIN)
3852                 return I40E_ERR_CONFIG;
3853         memset(&def_filter, 0, sizeof(def_filter));
3854         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3855                                         ETH_ADDR_LEN);
3856         def_filter.vlan_tag = 0;
3857         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3858                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3859         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3860         if (ret != I40E_SUCCESS) {
3861                 struct i40e_mac_filter *f;
3862                 struct ether_addr *mac;
3863
3864                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3865                             "macvlan filter");
3866                 /* It needs to add the permanent mac into mac list */
3867                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3868                 if (f == NULL) {
3869                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3870                         return I40E_ERR_NO_MEMORY;
3871                 }
3872                 mac = &f->mac_info.mac_addr;
3873                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3874                                 ETH_ADDR_LEN);
3875                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3876                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3877                 vsi->mac_num++;
3878
3879                 return ret;
3880         }
3881         (void)rte_memcpy(&filter.mac_addr,
3882                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3883         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3884         return i40e_vsi_add_mac(vsi, &filter);
3885 }
3886
3887 /*
3888  * i40e_vsi_get_bw_config - Query VSI BW Information
3889  * @vsi: the VSI to be queried
3890  *
3891  * Returns 0 on success, negative value on failure
3892  */
3893 static enum i40e_status_code
3894 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3895 {
3896         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3897         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3898         struct i40e_hw *hw = &vsi->adapter->hw;
3899         i40e_status ret;
3900         int i;
3901         uint32_t bw_max;
3902
3903         memset(&bw_config, 0, sizeof(bw_config));
3904         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3905         if (ret != I40E_SUCCESS) {
3906                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3907                             hw->aq.asq_last_status);
3908                 return ret;
3909         }
3910
3911         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3912         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3913                                         &ets_sla_config, NULL);
3914         if (ret != I40E_SUCCESS) {
3915                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3916                             "configuration %u", hw->aq.asq_last_status);
3917                 return ret;
3918         }
3919
3920         /* store and print out BW info */
3921         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3922         vsi->bw_info.bw_max = bw_config.max_bw;
3923         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3924         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3925         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3926                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3927                      I40E_16_BIT_WIDTH);
3928         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3929                 vsi->bw_info.bw_ets_share_credits[i] =
3930                                 ets_sla_config.share_credits[i];
3931                 vsi->bw_info.bw_ets_credits[i] =
3932                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3933                 /* 4 bits per TC, 4th bit is reserved */
3934                 vsi->bw_info.bw_ets_max[i] =
3935                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3936                                   RTE_LEN2MASK(3, uint8_t));
3937                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3938                             vsi->bw_info.bw_ets_share_credits[i]);
3939                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3940                             vsi->bw_info.bw_ets_credits[i]);
3941                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3942                             vsi->bw_info.bw_ets_max[i]);
3943         }
3944
3945         return I40E_SUCCESS;
3946 }
3947
3948 /* i40e_enable_pf_lb
3949  * @pf: pointer to the pf structure
3950  *
3951  * allow loopback on pf
3952  */
3953 static inline void
3954 i40e_enable_pf_lb(struct i40e_pf *pf)
3955 {
3956         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3957         struct i40e_vsi_context ctxt;
3958         int ret;
3959
3960         /* Use the FW API if FW >= v5.0 */
3961         if (hw->aq.fw_maj_ver < 5) {
3962                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3963                 return;
3964         }
3965
3966         memset(&ctxt, 0, sizeof(ctxt));
3967         ctxt.seid = pf->main_vsi_seid;
3968         ctxt.pf_num = hw->pf_id;
3969         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3970         if (ret) {
3971                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3972                             ret, hw->aq.asq_last_status);
3973                 return;
3974         }
3975         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3976         ctxt.info.valid_sections =
3977                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3978         ctxt.info.switch_id |=
3979                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3980
3981         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3982         if (ret)
3983                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3984                             hw->aq.asq_last_status);
3985 }
3986
3987 /* Setup a VSI */
3988 struct i40e_vsi *
3989 i40e_vsi_setup(struct i40e_pf *pf,
3990                enum i40e_vsi_type type,
3991                struct i40e_vsi *uplink_vsi,
3992                uint16_t user_param)
3993 {
3994         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3995         struct i40e_vsi *vsi;
3996         struct i40e_mac_filter_info filter;
3997         int ret;
3998         struct i40e_vsi_context ctxt;
3999         struct ether_addr broadcast =
4000                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4001
4002         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
4003                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4004                             "VSI link shouldn't be NULL");
4005                 return NULL;
4006         }
4007
4008         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4009                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4010                             "uplink VSI should be NULL");
4011                 return NULL;
4012         }
4013
4014         /* If uplink vsi didn't setup VEB, create one first */
4015         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4016                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4017
4018                 if (NULL == uplink_vsi->veb) {
4019                         PMD_DRV_LOG(ERR, "VEB setup failed");
4020                         return NULL;
4021                 }
4022                 /* set ALLOWLOOPBACk on pf, when veb is created */
4023                 i40e_enable_pf_lb(pf);
4024         }
4025
4026         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4027         if (!vsi) {
4028                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4029                 return NULL;
4030         }
4031         TAILQ_INIT(&vsi->mac_list);
4032         vsi->type = type;
4033         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4034         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4035         vsi->parent_vsi = uplink_vsi;
4036         vsi->user_param = user_param;
4037         /* Allocate queues */
4038         switch (vsi->type) {
4039         case I40E_VSI_MAIN  :
4040                 vsi->nb_qps = pf->lan_nb_qps;
4041                 break;
4042         case I40E_VSI_SRIOV :
4043                 vsi->nb_qps = pf->vf_nb_qps;
4044                 break;
4045         case I40E_VSI_VMDQ2:
4046                 vsi->nb_qps = pf->vmdq_nb_qps;
4047                 break;
4048         case I40E_VSI_FDIR:
4049                 vsi->nb_qps = pf->fdir_nb_qps;
4050                 break;
4051         default:
4052                 goto fail_mem;
4053         }
4054         /*
4055          * The filter status descriptor is reported in rx queue 0,
4056          * while the tx queue for fdir filter programming has no
4057          * such constraints, can be non-zero queues.
4058          * To simplify it, choose FDIR vsi use queue 0 pair.
4059          * To make sure it will use queue 0 pair, queue allocation
4060          * need be done before this function is called
4061          */
4062         if (type != I40E_VSI_FDIR) {
4063                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4064                         if (ret < 0) {
4065                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4066                                                 vsi->seid, ret);
4067                                 goto fail_mem;
4068                         }
4069                         vsi->base_queue = ret;
4070         } else
4071                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4072
4073         /* VF has MSIX interrupt in VF range, don't allocate here */
4074         if (type == I40E_VSI_MAIN) {
4075                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4076                                           RTE_MIN(vsi->nb_qps,
4077                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4078                 if (ret < 0) {
4079                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4080                                     vsi->seid, ret);
4081                         goto fail_queue_alloc;
4082                 }
4083                 vsi->msix_intr = ret;
4084                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4085         } else if (type != I40E_VSI_SRIOV) {
4086                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4087                 if (ret < 0) {
4088                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4089                         goto fail_queue_alloc;
4090                 }
4091                 vsi->msix_intr = ret;
4092                 vsi->nb_msix = 1;
4093         } else {
4094                 vsi->msix_intr = 0;
4095                 vsi->nb_msix = 0;
4096         }
4097
4098         /* Add VSI */
4099         if (type == I40E_VSI_MAIN) {
4100                 /* For main VSI, no need to add since it's default one */
4101                 vsi->uplink_seid = pf->mac_seid;
4102                 vsi->seid = pf->main_vsi_seid;
4103                 /* Bind queues with specific MSIX interrupt */
4104                 /**
4105                  * Needs 2 interrupt at least, one for misc cause which will
4106                  * enabled from OS side, Another for queues binding the
4107                  * interrupt from device side only.
4108                  */
4109
4110                 /* Get default VSI parameters from hardware */
4111                 memset(&ctxt, 0, sizeof(ctxt));
4112                 ctxt.seid = vsi->seid;
4113                 ctxt.pf_num = hw->pf_id;
4114                 ctxt.uplink_seid = vsi->uplink_seid;
4115                 ctxt.vf_num = 0;
4116                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4117                 if (ret != I40E_SUCCESS) {
4118                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4119                         goto fail_msix_alloc;
4120                 }
4121                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4122                         sizeof(struct i40e_aqc_vsi_properties_data));
4123                 vsi->vsi_id = ctxt.vsi_number;
4124                 vsi->info.valid_sections = 0;
4125
4126                 /* Configure tc, enabled TC0 only */
4127                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4128                         I40E_SUCCESS) {
4129                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4130                         goto fail_msix_alloc;
4131                 }
4132
4133                 /* TC, queue mapping */
4134                 memset(&ctxt, 0, sizeof(ctxt));
4135                 vsi->info.valid_sections |=
4136                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4137                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4138                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4139                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4140                         sizeof(struct i40e_aqc_vsi_properties_data));
4141                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4142                                                 I40E_DEFAULT_TCMAP);
4143                 if (ret != I40E_SUCCESS) {
4144                         PMD_DRV_LOG(ERR, "Failed to configure "
4145                                     "TC queue mapping");
4146                         goto fail_msix_alloc;
4147                 }
4148                 ctxt.seid = vsi->seid;
4149                 ctxt.pf_num = hw->pf_id;
4150                 ctxt.uplink_seid = vsi->uplink_seid;
4151                 ctxt.vf_num = 0;
4152
4153                 /* Update VSI parameters */
4154                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4155                 if (ret != I40E_SUCCESS) {
4156                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4157                         goto fail_msix_alloc;
4158                 }
4159
4160                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4161                                                 sizeof(vsi->info.tc_mapping));
4162                 (void)rte_memcpy(&vsi->info.queue_mapping,
4163                                 &ctxt.info.queue_mapping,
4164                         sizeof(vsi->info.queue_mapping));
4165                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4166                 vsi->info.valid_sections = 0;
4167
4168                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4169                                 ETH_ADDR_LEN);
4170
4171                 /**
4172                  * Updating default filter settings are necessary to prevent
4173                  * reception of tagged packets.
4174                  * Some old firmware configurations load a default macvlan
4175                  * filter which accepts both tagged and untagged packets.
4176                  * The updating is to use a normal filter instead if needed.
4177                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4178                  * The firmware with correct configurations load the default
4179                  * macvlan filter which is expected and cannot be removed.
4180                  */
4181                 i40e_update_default_filter_setting(vsi);
4182                 i40e_config_qinq(hw, vsi);
4183         } else if (type == I40E_VSI_SRIOV) {
4184                 memset(&ctxt, 0, sizeof(ctxt));
4185                 /**
4186                  * For other VSI, the uplink_seid equals to uplink VSI's
4187                  * uplink_seid since they share same VEB
4188                  */
4189                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4190                 ctxt.pf_num = hw->pf_id;
4191                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4192                 ctxt.uplink_seid = vsi->uplink_seid;
4193                 ctxt.connection_type = 0x1;
4194                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4195
4196                 /* Use the VEB configuration if FW >= v5.0 */
4197                 if (hw->aq.fw_maj_ver >= 5) {
4198                         /* Configure switch ID */
4199                         ctxt.info.valid_sections |=
4200                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4201                         ctxt.info.switch_id =
4202                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4203                 }
4204
4205                 /* Configure port/vlan */
4206                 ctxt.info.valid_sections |=
4207                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4208                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4209                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4210                                                 I40E_DEFAULT_TCMAP);
4211                 if (ret != I40E_SUCCESS) {
4212                         PMD_DRV_LOG(ERR, "Failed to configure "
4213                                     "TC queue mapping");
4214                         goto fail_msix_alloc;
4215                 }
4216                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4217                 ctxt.info.valid_sections |=
4218                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4219                 /**
4220                  * Since VSI is not created yet, only configure parameter,
4221                  * will add vsi below.
4222                  */
4223
4224                 i40e_config_qinq(hw, vsi);
4225         } else if (type == I40E_VSI_VMDQ2) {
4226                 memset(&ctxt, 0, sizeof(ctxt));
4227                 /*
4228                  * For other VSI, the uplink_seid equals to uplink VSI's
4229                  * uplink_seid since they share same VEB
4230                  */
4231                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4232                 ctxt.pf_num = hw->pf_id;
4233                 ctxt.vf_num = 0;
4234                 ctxt.uplink_seid = vsi->uplink_seid;
4235                 ctxt.connection_type = 0x1;
4236                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4237
4238                 ctxt.info.valid_sections |=
4239                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4240                 /* user_param carries flag to enable loop back */
4241                 if (user_param) {
4242                         ctxt.info.switch_id =
4243                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4244                         ctxt.info.switch_id |=
4245                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4246                 }
4247
4248                 /* Configure port/vlan */
4249                 ctxt.info.valid_sections |=
4250                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4251                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4252                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4253                                                 I40E_DEFAULT_TCMAP);
4254                 if (ret != I40E_SUCCESS) {
4255                         PMD_DRV_LOG(ERR, "Failed to configure "
4256                                         "TC queue mapping");
4257                         goto fail_msix_alloc;
4258                 }
4259                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4260                 ctxt.info.valid_sections |=
4261                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4262         } else if (type == I40E_VSI_FDIR) {
4263                 memset(&ctxt, 0, sizeof(ctxt));
4264                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4265                 ctxt.pf_num = hw->pf_id;
4266                 ctxt.vf_num = 0;
4267                 ctxt.uplink_seid = vsi->uplink_seid;
4268                 ctxt.connection_type = 0x1;     /* regular data port */
4269                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4270                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4271                                                 I40E_DEFAULT_TCMAP);
4272                 if (ret != I40E_SUCCESS) {
4273                         PMD_DRV_LOG(ERR, "Failed to configure "
4274                                         "TC queue mapping.");
4275                         goto fail_msix_alloc;
4276                 }
4277                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4278                 ctxt.info.valid_sections |=
4279                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4280         } else {
4281                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4282                 goto fail_msix_alloc;
4283         }
4284
4285         if (vsi->type != I40E_VSI_MAIN) {
4286                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4287                 if (ret != I40E_SUCCESS) {
4288                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4289                                     hw->aq.asq_last_status);
4290                         goto fail_msix_alloc;
4291                 }
4292                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4293                 vsi->info.valid_sections = 0;
4294                 vsi->seid = ctxt.seid;
4295                 vsi->vsi_id = ctxt.vsi_number;
4296                 vsi->sib_vsi_list.vsi = vsi;
4297                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4298                                 &vsi->sib_vsi_list, list);
4299         }
4300
4301         /* MAC/VLAN configuration */
4302         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4303         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4304
4305         ret = i40e_vsi_add_mac(vsi, &filter);
4306         if (ret != I40E_SUCCESS) {
4307                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4308                 goto fail_msix_alloc;
4309         }
4310
4311         /* Get VSI BW information */
4312         i40e_vsi_get_bw_config(vsi);
4313         return vsi;
4314 fail_msix_alloc:
4315         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4316 fail_queue_alloc:
4317         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4318 fail_mem:
4319         rte_free(vsi);
4320         return NULL;
4321 }
4322
4323 /* Configure vlan filter on or off */
4324 int
4325 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4326 {
4327         int i, num;
4328         struct i40e_mac_filter *f;
4329         struct i40e_mac_filter_info *mac_filter;
4330         enum rte_mac_filter_type desired_filter;
4331         int ret = I40E_SUCCESS;
4332
4333         if (on) {
4334                 /* Filter to match MAC and VLAN */
4335                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4336         } else {
4337                 /* Filter to match only MAC */
4338                 desired_filter = RTE_MAC_PERFECT_MATCH;
4339         }
4340
4341         num = vsi->mac_num;
4342
4343         mac_filter = rte_zmalloc("mac_filter_info_data",
4344                                  num * sizeof(*mac_filter), 0);
4345         if (mac_filter == NULL) {
4346                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4347                 return I40E_ERR_NO_MEMORY;
4348         }
4349
4350         i = 0;
4351
4352         /* Remove all existing mac */
4353         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4354                 mac_filter[i] = f->mac_info;
4355                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4356                 if (ret) {
4357                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4358                                     on ? "enable" : "disable");
4359                         goto DONE;
4360                 }
4361                 i++;
4362         }
4363
4364         /* Override with new filter */
4365         for (i = 0; i < num; i++) {
4366                 mac_filter[i].filter_type = desired_filter;
4367                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4368                 if (ret) {
4369                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4370                                     on ? "enable" : "disable");
4371                         goto DONE;
4372                 }
4373         }
4374
4375 DONE:
4376         rte_free(mac_filter);
4377         return ret;
4378 }
4379
4380 /* Configure vlan stripping on or off */
4381 int
4382 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4383 {
4384         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4385         struct i40e_vsi_context ctxt;
4386         uint8_t vlan_flags;
4387         int ret = I40E_SUCCESS;
4388
4389         /* Check if it has been already on or off */
4390         if (vsi->info.valid_sections &
4391                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4392                 if (on) {
4393                         if ((vsi->info.port_vlan_flags &
4394                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4395                                 return 0; /* already on */
4396                 } else {
4397                         if ((vsi->info.port_vlan_flags &
4398                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4399                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4400                                 return 0; /* already off */
4401                 }
4402         }
4403
4404         if (on)
4405                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4406         else
4407                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4408         vsi->info.valid_sections =
4409                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4410         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4411         vsi->info.port_vlan_flags |= vlan_flags;
4412         ctxt.seid = vsi->seid;
4413         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4414         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4415         if (ret)
4416                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4417                             on ? "enable" : "disable");
4418
4419         return ret;
4420 }
4421
4422 static int
4423 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4424 {
4425         struct rte_eth_dev_data *data = dev->data;
4426         int ret;
4427         int mask = 0;
4428
4429         /* Apply vlan offload setting */
4430         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4431         i40e_vlan_offload_set(dev, mask);
4432
4433         /* Apply double-vlan setting, not implemented yet */
4434
4435         /* Apply pvid setting */
4436         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4437                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4438         if (ret)
4439                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4440
4441         return ret;
4442 }
4443
4444 static int
4445 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4446 {
4447         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4448
4449         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4450 }
4451
4452 static int
4453 i40e_update_flow_control(struct i40e_hw *hw)
4454 {
4455 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4456         struct i40e_link_status link_status;
4457         uint32_t rxfc = 0, txfc = 0, reg;
4458         uint8_t an_info;
4459         int ret;
4460
4461         memset(&link_status, 0, sizeof(link_status));
4462         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4463         if (ret != I40E_SUCCESS) {
4464                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4465                 goto write_reg; /* Disable flow control */
4466         }
4467
4468         an_info = hw->phy.link_info.an_info;
4469         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4470                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4471                 ret = I40E_ERR_NOT_READY;
4472                 goto write_reg; /* Disable flow control */
4473         }
4474         /**
4475          * If link auto negotiation is enabled, flow control needs to
4476          * be configured according to it
4477          */
4478         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4479         case I40E_LINK_PAUSE_RXTX:
4480                 rxfc = 1;
4481                 txfc = 1;
4482                 hw->fc.current_mode = I40E_FC_FULL;
4483                 break;
4484         case I40E_AQ_LINK_PAUSE_RX:
4485                 rxfc = 1;
4486                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4487                 break;
4488         case I40E_AQ_LINK_PAUSE_TX:
4489                 txfc = 1;
4490                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4491                 break;
4492         default:
4493                 hw->fc.current_mode = I40E_FC_NONE;
4494                 break;
4495         }
4496
4497 write_reg:
4498         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4499                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4500         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4501         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4502         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4503         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4504
4505         return ret;
4506 }
4507
4508 /* PF setup */
4509 static int
4510 i40e_pf_setup(struct i40e_pf *pf)
4511 {
4512         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4513         struct i40e_filter_control_settings settings;
4514         struct i40e_vsi *vsi;
4515         int ret;
4516
4517         /* Clear all stats counters */
4518         pf->offset_loaded = FALSE;
4519         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4520         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4521
4522         ret = i40e_pf_get_switch_config(pf);
4523         if (ret != I40E_SUCCESS) {
4524                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4525                 return ret;
4526         }
4527         if (pf->flags & I40E_FLAG_FDIR) {
4528                 /* make queue allocated first, let FDIR use queue pair 0*/
4529                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4530                 if (ret != I40E_FDIR_QUEUE_ID) {
4531                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4532                                     " ret =%d", ret);
4533                         pf->flags &= ~I40E_FLAG_FDIR;
4534                 }
4535         }
4536         /*  main VSI setup */
4537         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4538         if (!vsi) {
4539                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4540                 return I40E_ERR_NOT_READY;
4541         }
4542         pf->main_vsi = vsi;
4543
4544         /* Configure filter control */
4545         memset(&settings, 0, sizeof(settings));
4546         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4547                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4548         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4549                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4550         else {
4551                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4552                                                 hw->func_caps.rss_table_size);
4553                 return I40E_ERR_PARAM;
4554         }
4555         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4556                         "size: %u\n", hw->func_caps.rss_table_size);
4557         pf->hash_lut_size = hw->func_caps.rss_table_size;
4558
4559         /* Enable ethtype and macvlan filters */
4560         settings.enable_ethtype = TRUE;
4561         settings.enable_macvlan = TRUE;
4562         ret = i40e_set_filter_control(hw, &settings);
4563         if (ret)
4564                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4565                                                                 ret);
4566
4567         /* Update flow control according to the auto negotiation */
4568         i40e_update_flow_control(hw);
4569
4570         return I40E_SUCCESS;
4571 }
4572
4573 int
4574 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4575 {
4576         uint32_t reg;
4577         uint16_t j;
4578
4579         /**
4580          * Set or clear TX Queue Disable flags,
4581          * which is required by hardware.
4582          */
4583         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4584         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4585
4586         /* Wait until the request is finished */
4587         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4588                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4589                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4590                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4591                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4592                                                         & 0x1))) {
4593                         break;
4594                 }
4595         }
4596         if (on) {
4597                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4598                         return I40E_SUCCESS; /* already on, skip next steps */
4599
4600                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4601                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4602         } else {
4603                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4604                         return I40E_SUCCESS; /* already off, skip next steps */
4605                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4606         }
4607         /* Write the register */
4608         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4609         /* Check the result */
4610         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4611                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4612                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4613                 if (on) {
4614                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4615                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4616                                 break;
4617                 } else {
4618                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4619                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4620                                 break;
4621                 }
4622         }
4623         /* Check if it is timeout */
4624         if (j >= I40E_CHK_Q_ENA_COUNT) {
4625                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4626                             (on ? "enable" : "disable"), q_idx);
4627                 return I40E_ERR_TIMEOUT;
4628         }
4629
4630         return I40E_SUCCESS;
4631 }
4632
4633 /* Swith on or off the tx queues */
4634 static int
4635 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4636 {
4637         struct rte_eth_dev_data *dev_data = pf->dev_data;
4638         struct i40e_tx_queue *txq;
4639         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4640         uint16_t i;
4641         int ret;
4642
4643         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4644                 txq = dev_data->tx_queues[i];
4645                 /* Don't operate the queue if not configured or
4646                  * if starting only per queue */
4647                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4648                         continue;
4649                 if (on)
4650                         ret = i40e_dev_tx_queue_start(dev, i);
4651                 else
4652                         ret = i40e_dev_tx_queue_stop(dev, i);
4653                 if ( ret != I40E_SUCCESS)
4654                         return ret;
4655         }
4656
4657         return I40E_SUCCESS;
4658 }
4659
4660 int
4661 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4662 {
4663         uint32_t reg;
4664         uint16_t j;
4665
4666         /* Wait until the request is finished */
4667         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4668                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4669                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4670                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4671                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4672                         break;
4673         }
4674
4675         if (on) {
4676                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4677                         return I40E_SUCCESS; /* Already on, skip next steps */
4678                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4679         } else {
4680                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4681                         return I40E_SUCCESS; /* Already off, skip next steps */
4682                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4683         }
4684
4685         /* Write the register */
4686         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4687         /* Check the result */
4688         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4689                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4690                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4691                 if (on) {
4692                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4693                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4694                                 break;
4695                 } else {
4696                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4697                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4698                                 break;
4699                 }
4700         }
4701
4702         /* Check if it is timeout */
4703         if (j >= I40E_CHK_Q_ENA_COUNT) {
4704                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4705                             (on ? "enable" : "disable"), q_idx);
4706                 return I40E_ERR_TIMEOUT;
4707         }
4708
4709         return I40E_SUCCESS;
4710 }
4711 /* Switch on or off the rx queues */
4712 static int
4713 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4714 {
4715         struct rte_eth_dev_data *dev_data = pf->dev_data;
4716         struct i40e_rx_queue *rxq;
4717         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4718         uint16_t i;
4719         int ret;
4720
4721         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4722                 rxq = dev_data->rx_queues[i];
4723                 /* Don't operate the queue if not configured or
4724                  * if starting only per queue */
4725                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4726                         continue;
4727                 if (on)
4728                         ret = i40e_dev_rx_queue_start(dev, i);
4729                 else
4730                         ret = i40e_dev_rx_queue_stop(dev, i);
4731                 if (ret != I40E_SUCCESS)
4732                         return ret;
4733         }
4734
4735         return I40E_SUCCESS;
4736 }
4737
4738 /* Switch on or off all the rx/tx queues */
4739 int
4740 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4741 {
4742         int ret;
4743
4744         if (on) {
4745                 /* enable rx queues before enabling tx queues */
4746                 ret = i40e_dev_switch_rx_queues(pf, on);
4747                 if (ret) {
4748                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4749                         return ret;
4750                 }
4751                 ret = i40e_dev_switch_tx_queues(pf, on);
4752         } else {
4753                 /* Stop tx queues before stopping rx queues */
4754                 ret = i40e_dev_switch_tx_queues(pf, on);
4755                 if (ret) {
4756                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4757                         return ret;
4758                 }
4759                 ret = i40e_dev_switch_rx_queues(pf, on);
4760         }
4761
4762         return ret;
4763 }
4764
4765 /* Initialize VSI for TX */
4766 static int
4767 i40e_dev_tx_init(struct i40e_pf *pf)
4768 {
4769         struct rte_eth_dev_data *data = pf->dev_data;
4770         uint16_t i;
4771         uint32_t ret = I40E_SUCCESS;
4772         struct i40e_tx_queue *txq;
4773
4774         for (i = 0; i < data->nb_tx_queues; i++) {
4775                 txq = data->tx_queues[i];
4776                 if (!txq || !txq->q_set)
4777                         continue;
4778                 ret = i40e_tx_queue_init(txq);
4779                 if (ret != I40E_SUCCESS)
4780                         break;
4781         }
4782         if (ret == I40E_SUCCESS)
4783                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4784                                      ->eth_dev);
4785
4786         return ret;
4787 }
4788
4789 /* Initialize VSI for RX */
4790 static int
4791 i40e_dev_rx_init(struct i40e_pf *pf)
4792 {
4793         struct rte_eth_dev_data *data = pf->dev_data;
4794         int ret = I40E_SUCCESS;
4795         uint16_t i;
4796         struct i40e_rx_queue *rxq;
4797
4798         i40e_pf_config_mq_rx(pf);
4799         for (i = 0; i < data->nb_rx_queues; i++) {
4800                 rxq = data->rx_queues[i];
4801                 if (!rxq || !rxq->q_set)
4802                         continue;
4803
4804                 ret = i40e_rx_queue_init(rxq);
4805                 if (ret != I40E_SUCCESS) {
4806                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4807                                     "initialization");
4808                         break;
4809                 }
4810         }
4811         if (ret == I40E_SUCCESS)
4812                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4813                                      ->eth_dev);
4814
4815         return ret;
4816 }
4817
4818 static int
4819 i40e_dev_rxtx_init(struct i40e_pf *pf)
4820 {
4821         int err;
4822
4823         err = i40e_dev_tx_init(pf);
4824         if (err) {
4825                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4826                 return err;
4827         }
4828         err = i40e_dev_rx_init(pf);
4829         if (err) {
4830                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4831                 return err;
4832         }
4833
4834         return err;
4835 }
4836
4837 static int
4838 i40e_vmdq_setup(struct rte_eth_dev *dev)
4839 {
4840         struct rte_eth_conf *conf = &dev->data->dev_conf;
4841         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4842         int i, err, conf_vsis, j, loop;
4843         struct i40e_vsi *vsi;
4844         struct i40e_vmdq_info *vmdq_info;
4845         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4846         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4847
4848         /*
4849          * Disable interrupt to avoid message from VF. Furthermore, it will
4850          * avoid race condition in VSI creation/destroy.
4851          */
4852         i40e_pf_disable_irq0(hw);
4853
4854         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4855                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4856                 return -ENOTSUP;
4857         }
4858
4859         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4860         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4861                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4862                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4863                         pf->max_nb_vmdq_vsi);
4864                 return -ENOTSUP;
4865         }
4866
4867         if (pf->vmdq != NULL) {
4868                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4869                 return 0;
4870         }
4871
4872         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4873                                 sizeof(*vmdq_info) * conf_vsis, 0);
4874
4875         if (pf->vmdq == NULL) {
4876                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4877                 return -ENOMEM;
4878         }
4879
4880         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4881
4882         /* Create VMDQ VSI */
4883         for (i = 0; i < conf_vsis; i++) {
4884                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4885                                 vmdq_conf->enable_loop_back);
4886                 if (vsi == NULL) {
4887                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4888                         err = -1;
4889                         goto err_vsi_setup;
4890                 }
4891                 vmdq_info = &pf->vmdq[i];
4892                 vmdq_info->pf = pf;
4893                 vmdq_info->vsi = vsi;
4894         }
4895         pf->nb_cfg_vmdq_vsi = conf_vsis;
4896
4897         /* Configure Vlan */
4898         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4899         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4900                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4901                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4902                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4903                                         vmdq_conf->pool_map[i].vlan_id, j);
4904
4905                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4906                                                 vmdq_conf->pool_map[i].vlan_id);
4907                                 if (err) {
4908                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4909                                         err = -1;
4910                                         goto err_vsi_setup;
4911                                 }
4912                         }
4913                 }
4914         }
4915
4916         i40e_pf_enable_irq0(hw);
4917
4918         return 0;
4919
4920 err_vsi_setup:
4921         for (i = 0; i < conf_vsis; i++)
4922                 if (pf->vmdq[i].vsi == NULL)
4923                         break;
4924                 else
4925                         i40e_vsi_release(pf->vmdq[i].vsi);
4926
4927         rte_free(pf->vmdq);
4928         pf->vmdq = NULL;
4929         i40e_pf_enable_irq0(hw);
4930         return err;
4931 }
4932
4933 static void
4934 i40e_stat_update_32(struct i40e_hw *hw,
4935                    uint32_t reg,
4936                    bool offset_loaded,
4937                    uint64_t *offset,
4938                    uint64_t *stat)
4939 {
4940         uint64_t new_data;
4941
4942         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4943         if (!offset_loaded)
4944                 *offset = new_data;
4945
4946         if (new_data >= *offset)
4947                 *stat = (uint64_t)(new_data - *offset);
4948         else
4949                 *stat = (uint64_t)((new_data +
4950                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4951 }
4952
4953 static void
4954 i40e_stat_update_48(struct i40e_hw *hw,
4955                    uint32_t hireg,
4956                    uint32_t loreg,
4957                    bool offset_loaded,
4958                    uint64_t *offset,
4959                    uint64_t *stat)
4960 {
4961         uint64_t new_data;
4962
4963         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4964         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4965                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4966
4967         if (!offset_loaded)
4968                 *offset = new_data;
4969
4970         if (new_data >= *offset)
4971                 *stat = new_data - *offset;
4972         else
4973                 *stat = (uint64_t)((new_data +
4974                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4975
4976         *stat &= I40E_48_BIT_MASK;
4977 }
4978
4979 /* Disable IRQ0 */
4980 void
4981 i40e_pf_disable_irq0(struct i40e_hw *hw)
4982 {
4983         /* Disable all interrupt types */
4984         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4985         I40E_WRITE_FLUSH(hw);
4986 }
4987
4988 /* Enable IRQ0 */
4989 void
4990 i40e_pf_enable_irq0(struct i40e_hw *hw)
4991 {
4992         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4993                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4994                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4995                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4996         I40E_WRITE_FLUSH(hw);
4997 }
4998
4999 static void
5000 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5001 {
5002         /* read pending request and disable first */
5003         i40e_pf_disable_irq0(hw);
5004         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5005         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5006                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5007
5008         if (no_queue)
5009                 /* Link no queues with irq0 */
5010                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5011                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5012 }
5013
5014 static void
5015 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5016 {
5017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5019         int i;
5020         uint16_t abs_vf_id;
5021         uint32_t index, offset, val;
5022
5023         if (!pf->vfs)
5024                 return;
5025         /**
5026          * Try to find which VF trigger a reset, use absolute VF id to access
5027          * since the reg is global register.
5028          */
5029         for (i = 0; i < pf->vf_num; i++) {
5030                 abs_vf_id = hw->func_caps.vf_base_id + i;
5031                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5032                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5033                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5034                 /* VFR event occured */
5035                 if (val & (0x1 << offset)) {
5036                         int ret;
5037
5038                         /* Clear the event first */
5039                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5040                                                         (0x1 << offset));
5041                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5042                         /**
5043                          * Only notify a VF reset event occured,
5044                          * don't trigger another SW reset
5045                          */
5046                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5047                         if (ret != I40E_SUCCESS)
5048                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5049                 }
5050         }
5051 }
5052
5053 static void
5054 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5055 {
5056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057         struct i40e_arq_event_info info;
5058         uint16_t pending, opcode;
5059         int ret;
5060
5061         info.buf_len = I40E_AQ_BUF_SZ;
5062         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5063         if (!info.msg_buf) {
5064                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5065                 return;
5066         }
5067
5068         pending = 1;
5069         while (pending) {
5070                 ret = i40e_clean_arq_element(hw, &info, &pending);
5071
5072                 if (ret != I40E_SUCCESS) {
5073                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5074                                     "aq_err: %u", hw->aq.asq_last_status);
5075                         break;
5076                 }
5077                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5078
5079                 switch (opcode) {
5080                 case i40e_aqc_opc_send_msg_to_pf:
5081                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5082                         i40e_pf_host_handle_vf_msg(dev,
5083                                         rte_le_to_cpu_16(info.desc.retval),
5084                                         rte_le_to_cpu_32(info.desc.cookie_high),
5085                                         rte_le_to_cpu_32(info.desc.cookie_low),
5086                                         info.msg_buf,
5087                                         info.msg_len);
5088                         break;
5089                 default:
5090                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5091                                     opcode);
5092                         break;
5093                 }
5094         }
5095         rte_free(info.msg_buf);
5096 }
5097
5098 /*
5099  * Interrupt handler is registered as the alarm callback for handling LSC
5100  * interrupt in a definite of time, in order to wait the NIC into a stable
5101  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5102  * no need for link down interrupt.
5103  */
5104 static void
5105 i40e_dev_interrupt_delayed_handler(void *param)
5106 {
5107         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         uint32_t icr0;
5110
5111         /* read interrupt causes again */
5112         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5113
5114 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5115         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5116                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5117         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5118                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5119         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5120                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5121         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5122                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5123         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5124                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5125                                                                 "state\n");
5126         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5127                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5128         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5129                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5130 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5131
5132         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5133                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5134                 i40e_dev_handle_vfr_event(dev);
5135         }
5136         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5137                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5138                 i40e_dev_handle_aq_msg(dev);
5139         }
5140
5141         /* handle the link up interrupt in an alarm callback */
5142         i40e_dev_link_update(dev, 0);
5143         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5144
5145         i40e_pf_enable_irq0(hw);
5146         rte_intr_enable(&(dev->pci_dev->intr_handle));
5147 }
5148
5149 /**
5150  * Interrupt handler triggered by NIC  for handling
5151  * specific interrupt.
5152  *
5153  * @param handle
5154  *  Pointer to interrupt handle.
5155  * @param param
5156  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5157  *
5158  * @return
5159  *  void
5160  */
5161 static void
5162 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5163                            void *param)
5164 {
5165         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5167         uint32_t icr0;
5168
5169         /* Disable interrupt */
5170         i40e_pf_disable_irq0(hw);
5171
5172         /* read out interrupt causes */
5173         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5174
5175         /* No interrupt event indicated */
5176         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5177                 PMD_DRV_LOG(INFO, "No interrupt event");
5178                 goto done;
5179         }
5180 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5181         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5182                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5183         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5184                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5185         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5186                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5187         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5188                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5189         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5190                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5191         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5192                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5193         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5194                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5195 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5196
5197         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5198                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5199                 i40e_dev_handle_vfr_event(dev);
5200         }
5201         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5202                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5203                 i40e_dev_handle_aq_msg(dev);
5204         }
5205
5206         /* Link Status Change interrupt */
5207         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5208 #define I40E_US_PER_SECOND 1000000
5209                 struct rte_eth_link link;
5210
5211                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5212                 memset(&link, 0, sizeof(link));
5213                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5214                 i40e_dev_link_update(dev, 0);
5215
5216                 /*
5217                  * For link up interrupt, it needs to wait 1 second to let the
5218                  * hardware be a stable state. Otherwise several consecutive
5219                  * interrupts can be observed.
5220                  * For link down interrupt, no need to wait.
5221                  */
5222                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5223                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5224                         return;
5225                 else
5226                         _rte_eth_dev_callback_process(dev,
5227                                 RTE_ETH_EVENT_INTR_LSC);
5228         }
5229
5230 done:
5231         /* Enable interrupt */
5232         i40e_pf_enable_irq0(hw);
5233         rte_intr_enable(&(dev->pci_dev->intr_handle));
5234 }
5235
5236 static int
5237 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5238                          struct i40e_macvlan_filter *filter,
5239                          int total)
5240 {
5241         int ele_num, ele_buff_size;
5242         int num, actual_num, i;
5243         uint16_t flags;
5244         int ret = I40E_SUCCESS;
5245         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5246         struct i40e_aqc_add_macvlan_element_data *req_list;
5247
5248         if (filter == NULL  || total == 0)
5249                 return I40E_ERR_PARAM;
5250         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5251         ele_buff_size = hw->aq.asq_buf_size;
5252
5253         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5254         if (req_list == NULL) {
5255                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5256                 return I40E_ERR_NO_MEMORY;
5257         }
5258
5259         num = 0;
5260         do {
5261                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5262                 memset(req_list, 0, ele_buff_size);
5263
5264                 for (i = 0; i < actual_num; i++) {
5265                         (void)rte_memcpy(req_list[i].mac_addr,
5266                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5267                         req_list[i].vlan_tag =
5268                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5269
5270                         switch (filter[num + i].filter_type) {
5271                         case RTE_MAC_PERFECT_MATCH:
5272                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5273                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5274                                 break;
5275                         case RTE_MACVLAN_PERFECT_MATCH:
5276                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5277                                 break;
5278                         case RTE_MAC_HASH_MATCH:
5279                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5280                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5281                                 break;
5282                         case RTE_MACVLAN_HASH_MATCH:
5283                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5284                                 break;
5285                         default:
5286                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5287                                 ret = I40E_ERR_PARAM;
5288                                 goto DONE;
5289                         }
5290
5291                         req_list[i].queue_number = 0;
5292
5293                         req_list[i].flags = rte_cpu_to_le_16(flags);
5294                 }
5295
5296                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5297                                                 actual_num, NULL);
5298                 if (ret != I40E_SUCCESS) {
5299                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5300                         goto DONE;
5301                 }
5302                 num += actual_num;
5303         } while (num < total);
5304
5305 DONE:
5306         rte_free(req_list);
5307         return ret;
5308 }
5309
5310 static int
5311 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5312                             struct i40e_macvlan_filter *filter,
5313                             int total)
5314 {
5315         int ele_num, ele_buff_size;
5316         int num, actual_num, i;
5317         uint16_t flags;
5318         int ret = I40E_SUCCESS;
5319         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5320         struct i40e_aqc_remove_macvlan_element_data *req_list;
5321
5322         if (filter == NULL  || total == 0)
5323                 return I40E_ERR_PARAM;
5324
5325         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5326         ele_buff_size = hw->aq.asq_buf_size;
5327
5328         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5329         if (req_list == NULL) {
5330                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5331                 return I40E_ERR_NO_MEMORY;
5332         }
5333
5334         num = 0;
5335         do {
5336                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5337                 memset(req_list, 0, ele_buff_size);
5338
5339                 for (i = 0; i < actual_num; i++) {
5340                         (void)rte_memcpy(req_list[i].mac_addr,
5341                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5342                         req_list[i].vlan_tag =
5343                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5344
5345                         switch (filter[num + i].filter_type) {
5346                         case RTE_MAC_PERFECT_MATCH:
5347                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5348                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5349                                 break;
5350                         case RTE_MACVLAN_PERFECT_MATCH:
5351                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5352                                 break;
5353                         case RTE_MAC_HASH_MATCH:
5354                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5355                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5356                                 break;
5357                         case RTE_MACVLAN_HASH_MATCH:
5358                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5359                                 break;
5360                         default:
5361                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5362                                 ret = I40E_ERR_PARAM;
5363                                 goto DONE;
5364                         }
5365                         req_list[i].flags = rte_cpu_to_le_16(flags);
5366                 }
5367
5368                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5369                                                 actual_num, NULL);
5370                 if (ret != I40E_SUCCESS) {
5371                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5372                         goto DONE;
5373                 }
5374                 num += actual_num;
5375         } while (num < total);
5376
5377 DONE:
5378         rte_free(req_list);
5379         return ret;
5380 }
5381
5382 /* Find out specific MAC filter */
5383 static struct i40e_mac_filter *
5384 i40e_find_mac_filter(struct i40e_vsi *vsi,
5385                          struct ether_addr *macaddr)
5386 {
5387         struct i40e_mac_filter *f;
5388
5389         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5390                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5391                         return f;
5392         }
5393
5394         return NULL;
5395 }
5396
5397 static bool
5398 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5399                          uint16_t vlan_id)
5400 {
5401         uint32_t vid_idx, vid_bit;
5402
5403         if (vlan_id > ETH_VLAN_ID_MAX)
5404                 return 0;
5405
5406         vid_idx = I40E_VFTA_IDX(vlan_id);
5407         vid_bit = I40E_VFTA_BIT(vlan_id);
5408
5409         if (vsi->vfta[vid_idx] & vid_bit)
5410                 return 1;
5411         else
5412                 return 0;
5413 }
5414
5415 static void
5416 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5417                          uint16_t vlan_id, bool on)
5418 {
5419         uint32_t vid_idx, vid_bit;
5420
5421         if (vlan_id > ETH_VLAN_ID_MAX)
5422                 return;
5423
5424         vid_idx = I40E_VFTA_IDX(vlan_id);
5425         vid_bit = I40E_VFTA_BIT(vlan_id);
5426
5427         if (on)
5428                 vsi->vfta[vid_idx] |= vid_bit;
5429         else
5430                 vsi->vfta[vid_idx] &= ~vid_bit;
5431 }
5432
5433 /**
5434  * Find all vlan options for specific mac addr,
5435  * return with actual vlan found.
5436  */
5437 static inline int
5438 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5439                            struct i40e_macvlan_filter *mv_f,
5440                            int num, struct ether_addr *addr)
5441 {
5442         int i;
5443         uint32_t j, k;
5444
5445         /**
5446          * Not to use i40e_find_vlan_filter to decrease the loop time,
5447          * although the code looks complex.
5448           */
5449         if (num < vsi->vlan_num)
5450                 return I40E_ERR_PARAM;
5451
5452         i = 0;
5453         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5454                 if (vsi->vfta[j]) {
5455                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5456                                 if (vsi->vfta[j] & (1 << k)) {
5457                                         if (i > num - 1) {
5458                                                 PMD_DRV_LOG(ERR, "vlan number "
5459                                                             "not match");
5460                                                 return I40E_ERR_PARAM;
5461                                         }
5462                                         (void)rte_memcpy(&mv_f[i].macaddr,
5463                                                         addr, ETH_ADDR_LEN);
5464                                         mv_f[i].vlan_id =
5465                                                 j * I40E_UINT32_BIT_SIZE + k;
5466                                         i++;
5467                                 }
5468                         }
5469                 }
5470         }
5471         return I40E_SUCCESS;
5472 }
5473
5474 static inline int
5475 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5476                            struct i40e_macvlan_filter *mv_f,
5477                            int num,
5478                            uint16_t vlan)
5479 {
5480         int i = 0;
5481         struct i40e_mac_filter *f;
5482
5483         if (num < vsi->mac_num)
5484                 return I40E_ERR_PARAM;
5485
5486         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5487                 if (i > num - 1) {
5488                         PMD_DRV_LOG(ERR, "buffer number not match");
5489                         return I40E_ERR_PARAM;
5490                 }
5491                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5492                                 ETH_ADDR_LEN);
5493                 mv_f[i].vlan_id = vlan;
5494                 mv_f[i].filter_type = f->mac_info.filter_type;
5495                 i++;
5496         }
5497
5498         return I40E_SUCCESS;
5499 }
5500
5501 static int
5502 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5503 {
5504         int i, num;
5505         struct i40e_mac_filter *f;
5506         struct i40e_macvlan_filter *mv_f;
5507         int ret = I40E_SUCCESS;
5508
5509         if (vsi == NULL || vsi->mac_num == 0)
5510                 return I40E_ERR_PARAM;
5511
5512         /* Case that no vlan is set */
5513         if (vsi->vlan_num == 0)
5514                 num = vsi->mac_num;
5515         else
5516                 num = vsi->mac_num * vsi->vlan_num;
5517
5518         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5519         if (mv_f == NULL) {
5520                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5521                 return I40E_ERR_NO_MEMORY;
5522         }
5523
5524         i = 0;
5525         if (vsi->vlan_num == 0) {
5526                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5527                         (void)rte_memcpy(&mv_f[i].macaddr,
5528                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5529                         mv_f[i].vlan_id = 0;
5530                         i++;
5531                 }
5532         } else {
5533                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5534                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5535                                         vsi->vlan_num, &f->mac_info.mac_addr);
5536                         if (ret != I40E_SUCCESS)
5537                                 goto DONE;
5538                         i += vsi->vlan_num;
5539                 }
5540         }
5541
5542         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5543 DONE:
5544         rte_free(mv_f);
5545
5546         return ret;
5547 }
5548
5549 int
5550 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5551 {
5552         struct i40e_macvlan_filter *mv_f;
5553         int mac_num;
5554         int ret = I40E_SUCCESS;
5555
5556         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5557                 return I40E_ERR_PARAM;
5558
5559         /* If it's already set, just return */
5560         if (i40e_find_vlan_filter(vsi,vlan))
5561                 return I40E_SUCCESS;
5562
5563         mac_num = vsi->mac_num;
5564
5565         if (mac_num == 0) {
5566                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5567                 return I40E_ERR_PARAM;
5568         }
5569
5570         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5571
5572         if (mv_f == NULL) {
5573                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5574                 return I40E_ERR_NO_MEMORY;
5575         }
5576
5577         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5578
5579         if (ret != I40E_SUCCESS)
5580                 goto DONE;
5581
5582         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5583
5584         if (ret != I40E_SUCCESS)
5585                 goto DONE;
5586
5587         i40e_set_vlan_filter(vsi, vlan, 1);
5588
5589         vsi->vlan_num++;
5590         ret = I40E_SUCCESS;
5591 DONE:
5592         rte_free(mv_f);
5593         return ret;
5594 }
5595
5596 int
5597 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5598 {
5599         struct i40e_macvlan_filter *mv_f;
5600         int mac_num;
5601         int ret = I40E_SUCCESS;
5602
5603         /**
5604          * Vlan 0 is the generic filter for untagged packets
5605          * and can't be removed.
5606          */
5607         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5608                 return I40E_ERR_PARAM;
5609
5610         /* If can't find it, just return */
5611         if (!i40e_find_vlan_filter(vsi, vlan))
5612                 return I40E_ERR_PARAM;
5613
5614         mac_num = vsi->mac_num;
5615
5616         if (mac_num == 0) {
5617                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5618                 return I40E_ERR_PARAM;
5619         }
5620
5621         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5622
5623         if (mv_f == NULL) {
5624                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5625                 return I40E_ERR_NO_MEMORY;
5626         }
5627
5628         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5629
5630         if (ret != I40E_SUCCESS)
5631                 goto DONE;
5632
5633         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5634
5635         if (ret != I40E_SUCCESS)
5636                 goto DONE;
5637
5638         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5639         if (vsi->vlan_num == 1) {
5640                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5641                 if (ret != I40E_SUCCESS)
5642                         goto DONE;
5643
5644                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5645                 if (ret != I40E_SUCCESS)
5646                         goto DONE;
5647         }
5648
5649         i40e_set_vlan_filter(vsi, vlan, 0);
5650
5651         vsi->vlan_num--;
5652         ret = I40E_SUCCESS;
5653 DONE:
5654         rte_free(mv_f);
5655         return ret;
5656 }
5657
5658 int
5659 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5660 {
5661         struct i40e_mac_filter *f;
5662         struct i40e_macvlan_filter *mv_f;
5663         int i, vlan_num = 0;
5664         int ret = I40E_SUCCESS;
5665
5666         /* If it's add and we've config it, return */
5667         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5668         if (f != NULL)
5669                 return I40E_SUCCESS;
5670         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5671                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5672
5673                 /**
5674                  * If vlan_num is 0, that's the first time to add mac,
5675                  * set mask for vlan_id 0.
5676                  */
5677                 if (vsi->vlan_num == 0) {
5678                         i40e_set_vlan_filter(vsi, 0, 1);
5679                         vsi->vlan_num = 1;
5680                 }
5681                 vlan_num = vsi->vlan_num;
5682         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5683                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5684                 vlan_num = 1;
5685
5686         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5687         if (mv_f == NULL) {
5688                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5689                 return I40E_ERR_NO_MEMORY;
5690         }
5691
5692         for (i = 0; i < vlan_num; i++) {
5693                 mv_f[i].filter_type = mac_filter->filter_type;
5694                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5695                                 ETH_ADDR_LEN);
5696         }
5697
5698         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5699                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5700                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5701                                         &mac_filter->mac_addr);
5702                 if (ret != I40E_SUCCESS)
5703                         goto DONE;
5704         }
5705
5706         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5707         if (ret != I40E_SUCCESS)
5708                 goto DONE;
5709
5710         /* Add the mac addr into mac list */
5711         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5712         if (f == NULL) {
5713                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5714                 ret = I40E_ERR_NO_MEMORY;
5715                 goto DONE;
5716         }
5717         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5718                         ETH_ADDR_LEN);
5719         f->mac_info.filter_type = mac_filter->filter_type;
5720         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5721         vsi->mac_num++;
5722
5723         ret = I40E_SUCCESS;
5724 DONE:
5725         rte_free(mv_f);
5726
5727         return ret;
5728 }
5729
5730 int
5731 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5732 {
5733         struct i40e_mac_filter *f;
5734         struct i40e_macvlan_filter *mv_f;
5735         int i, vlan_num;
5736         enum rte_mac_filter_type filter_type;
5737         int ret = I40E_SUCCESS;
5738
5739         /* Can't find it, return an error */
5740         f = i40e_find_mac_filter(vsi, addr);
5741         if (f == NULL)
5742                 return I40E_ERR_PARAM;
5743
5744         vlan_num = vsi->vlan_num;
5745         filter_type = f->mac_info.filter_type;
5746         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5747                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5748                 if (vlan_num == 0) {
5749                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5750                         return I40E_ERR_PARAM;
5751                 }
5752         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5753                         filter_type == RTE_MAC_HASH_MATCH)
5754                 vlan_num = 1;
5755
5756         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5757         if (mv_f == NULL) {
5758                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5759                 return I40E_ERR_NO_MEMORY;
5760         }
5761
5762         for (i = 0; i < vlan_num; i++) {
5763                 mv_f[i].filter_type = filter_type;
5764                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5765                                 ETH_ADDR_LEN);
5766         }
5767         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5768                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5769                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5770                 if (ret != I40E_SUCCESS)
5771                         goto DONE;
5772         }
5773
5774         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5775         if (ret != I40E_SUCCESS)
5776                 goto DONE;
5777
5778         /* Remove the mac addr into mac list */
5779         TAILQ_REMOVE(&vsi->mac_list, f, next);
5780         rte_free(f);
5781         vsi->mac_num--;
5782
5783         ret = I40E_SUCCESS;
5784 DONE:
5785         rte_free(mv_f);
5786         return ret;
5787 }
5788
5789 /* Configure hash enable flags for RSS */
5790 uint64_t
5791 i40e_config_hena(uint64_t flags)
5792 {
5793         uint64_t hena = 0;
5794
5795         if (!flags)
5796                 return hena;
5797
5798         if (flags & ETH_RSS_FRAG_IPV4)
5799                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5800         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5801                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5802         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5803                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5804         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5805                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5806         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5807                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5808         if (flags & ETH_RSS_FRAG_IPV6)
5809                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5810         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5811                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5812         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5813                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5814         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5815                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5816         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5817                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5818         if (flags & ETH_RSS_L2_PAYLOAD)
5819                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5820
5821         return hena;
5822 }
5823
5824 /* Parse the hash enable flags */
5825 uint64_t
5826 i40e_parse_hena(uint64_t flags)
5827 {
5828         uint64_t rss_hf = 0;
5829
5830         if (!flags)
5831                 return rss_hf;
5832         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5833                 rss_hf |= ETH_RSS_FRAG_IPV4;
5834         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5835                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5836         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5837                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5838         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5839                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5840         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5841                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5842         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5843                 rss_hf |= ETH_RSS_FRAG_IPV6;
5844         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5845                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5846         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5847                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5848         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5849                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5850         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5851                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5852         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5853                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5854
5855         return rss_hf;
5856 }
5857
5858 /* Disable RSS */
5859 static void
5860 i40e_pf_disable_rss(struct i40e_pf *pf)
5861 {
5862         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5863         uint64_t hena;
5864
5865         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5866         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5867         hena &= ~I40E_RSS_HENA_ALL;
5868         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5869         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5870         I40E_WRITE_FLUSH(hw);
5871 }
5872
5873 static int
5874 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5875 {
5876         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5877         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5878         int ret = 0;
5879
5880         if (!key || key_len == 0) {
5881                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5882                 return 0;
5883         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5884                 sizeof(uint32_t)) {
5885                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5886                 return -EINVAL;
5887         }
5888
5889         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5890                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5891                         (struct i40e_aqc_get_set_rss_key_data *)key;
5892
5893                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5894                 if (ret)
5895                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5896                                      "via AQ");
5897         } else {
5898                 uint32_t *hash_key = (uint32_t *)key;
5899                 uint16_t i;
5900
5901                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5902                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5903                 I40E_WRITE_FLUSH(hw);
5904         }
5905
5906         return ret;
5907 }
5908
5909 static int
5910 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5911 {
5912         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5913         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5914         int ret;
5915
5916         if (!key || !key_len)
5917                 return -EINVAL;
5918
5919         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5920                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5921                         (struct i40e_aqc_get_set_rss_key_data *)key);
5922                 if (ret) {
5923                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5924                         return ret;
5925                 }
5926         } else {
5927                 uint32_t *key_dw = (uint32_t *)key;
5928                 uint16_t i;
5929
5930                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5931                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5932         }
5933         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5934
5935         return 0;
5936 }
5937
5938 static int
5939 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5940 {
5941         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5942         uint64_t rss_hf;
5943         uint64_t hena;
5944         int ret;
5945
5946         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5947                                rss_conf->rss_key_len);
5948         if (ret)
5949                 return ret;
5950
5951         rss_hf = rss_conf->rss_hf;
5952         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5953         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5954         hena &= ~I40E_RSS_HENA_ALL;
5955         hena |= i40e_config_hena(rss_hf);
5956         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5957         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5958         I40E_WRITE_FLUSH(hw);
5959
5960         return 0;
5961 }
5962
5963 static int
5964 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5965                          struct rte_eth_rss_conf *rss_conf)
5966 {
5967         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5968         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5969         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5970         uint64_t hena;
5971
5972         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5973         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5974         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5975                 if (rss_hf != 0) /* Enable RSS */
5976                         return -EINVAL;
5977                 return 0; /* Nothing to do */
5978         }
5979         /* RSS enabled */
5980         if (rss_hf == 0) /* Disable RSS */
5981                 return -EINVAL;
5982
5983         return i40e_hw_rss_hash_set(pf, rss_conf);
5984 }
5985
5986 static int
5987 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5988                            struct rte_eth_rss_conf *rss_conf)
5989 {
5990         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5991         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5992         uint64_t hena;
5993
5994         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5995                          &rss_conf->rss_key_len);
5996
5997         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5998         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5999         rss_conf->rss_hf = i40e_parse_hena(hena);
6000
6001         return 0;
6002 }
6003
6004 static int
6005 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6006 {
6007         switch (filter_type) {
6008         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6009                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6010                 break;
6011         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6012                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6013                 break;
6014         case RTE_TUNNEL_FILTER_IMAC_TENID:
6015                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6016                 break;
6017         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6018                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6019                 break;
6020         case ETH_TUNNEL_FILTER_IMAC:
6021                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6022                 break;
6023         case ETH_TUNNEL_FILTER_OIP:
6024                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6025                 break;
6026         case ETH_TUNNEL_FILTER_IIP:
6027                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6028                 break;
6029         default:
6030                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6031                 return -EINVAL;
6032         }
6033
6034         return 0;
6035 }
6036
6037 static int
6038 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6039                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6040                         uint8_t add)
6041 {
6042         uint16_t ip_type;
6043         uint32_t ipv4_addr;
6044         uint8_t i, tun_type = 0;
6045         /* internal varialbe to convert ipv6 byte order */
6046         uint32_t convert_ipv6[4];
6047         int val, ret = 0;
6048         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6049         struct i40e_vsi *vsi = pf->main_vsi;
6050         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6051         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6052
6053         cld_filter = rte_zmalloc("tunnel_filter",
6054                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6055                 0);
6056
6057         if (NULL == cld_filter) {
6058                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6059                 return -EINVAL;
6060         }
6061         pfilter = cld_filter;
6062
6063         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6064         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6065
6066         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6067         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6068                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6069                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6070                 rte_memcpy(&pfilter->ipaddr.v4.data,
6071                                 &rte_cpu_to_le_32(ipv4_addr),
6072                                 sizeof(pfilter->ipaddr.v4.data));
6073         } else {
6074                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6075                 for (i = 0; i < 4; i++) {
6076                         convert_ipv6[i] =
6077                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6078                 }
6079                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6080                                 sizeof(pfilter->ipaddr.v6.data));
6081         }
6082
6083         /* check tunneled type */
6084         switch (tunnel_filter->tunnel_type) {
6085         case RTE_TUNNEL_TYPE_VXLAN:
6086                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6087                 break;
6088         case RTE_TUNNEL_TYPE_NVGRE:
6089                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6090                 break;
6091         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6092                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6093                 break;
6094         default:
6095                 /* Other tunnel types is not supported. */
6096                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6097                 rte_free(cld_filter);
6098                 return -EINVAL;
6099         }
6100
6101         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6102                                                 &pfilter->flags);
6103         if (val < 0) {
6104                 rte_free(cld_filter);
6105                 return -EINVAL;
6106         }
6107
6108         pfilter->flags |= rte_cpu_to_le_16(
6109                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6110                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6111         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6112         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6113
6114         if (add)
6115                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6116         else
6117                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6118                                                 cld_filter, 1);
6119
6120         rte_free(cld_filter);
6121         return ret;
6122 }
6123
6124 static int
6125 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6126 {
6127         uint8_t i;
6128
6129         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6130                 if (pf->vxlan_ports[i] == port)
6131                         return i;
6132         }
6133
6134         return -1;
6135 }
6136
6137 static int
6138 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6139 {
6140         int  idx, ret;
6141         uint8_t filter_idx;
6142         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6143
6144         idx = i40e_get_vxlan_port_idx(pf, port);
6145
6146         /* Check if port already exists */
6147         if (idx >= 0) {
6148                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6149                 return -EINVAL;
6150         }
6151
6152         /* Now check if there is space to add the new port */
6153         idx = i40e_get_vxlan_port_idx(pf, 0);
6154         if (idx < 0) {
6155                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6156                         "not adding port %d", port);
6157                 return -ENOSPC;
6158         }
6159
6160         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6161                                         &filter_idx, NULL);
6162         if (ret < 0) {
6163                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6164                 return -1;
6165         }
6166
6167         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6168                          port,  filter_idx);
6169
6170         /* New port: add it and mark its index in the bitmap */
6171         pf->vxlan_ports[idx] = port;
6172         pf->vxlan_bitmap |= (1 << idx);
6173
6174         if (!(pf->flags & I40E_FLAG_VXLAN))
6175                 pf->flags |= I40E_FLAG_VXLAN;
6176
6177         return 0;
6178 }
6179
6180 static int
6181 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6182 {
6183         int idx;
6184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6185
6186         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6187                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6188                 return -EINVAL;
6189         }
6190
6191         idx = i40e_get_vxlan_port_idx(pf, port);
6192
6193         if (idx < 0) {
6194                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6195                 return -EINVAL;
6196         }
6197
6198         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6199                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6200                 return -1;
6201         }
6202
6203         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6204                         port, idx);
6205
6206         pf->vxlan_ports[idx] = 0;
6207         pf->vxlan_bitmap &= ~(1 << idx);
6208
6209         if (!pf->vxlan_bitmap)
6210                 pf->flags &= ~I40E_FLAG_VXLAN;
6211
6212         return 0;
6213 }
6214
6215 /* Add UDP tunneling port */
6216 static int
6217 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6218                              struct rte_eth_udp_tunnel *udp_tunnel)
6219 {
6220         int ret = 0;
6221         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6222
6223         if (udp_tunnel == NULL)
6224                 return -EINVAL;
6225
6226         switch (udp_tunnel->prot_type) {
6227         case RTE_TUNNEL_TYPE_VXLAN:
6228                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6229                 break;
6230
6231         case RTE_TUNNEL_TYPE_GENEVE:
6232         case RTE_TUNNEL_TYPE_TEREDO:
6233                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6234                 ret = -1;
6235                 break;
6236
6237         default:
6238                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6239                 ret = -1;
6240                 break;
6241         }
6242
6243         return ret;
6244 }
6245
6246 /* Remove UDP tunneling port */
6247 static int
6248 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6249                              struct rte_eth_udp_tunnel *udp_tunnel)
6250 {
6251         int ret = 0;
6252         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6253
6254         if (udp_tunnel == NULL)
6255                 return -EINVAL;
6256
6257         switch (udp_tunnel->prot_type) {
6258         case RTE_TUNNEL_TYPE_VXLAN:
6259                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6260                 break;
6261         case RTE_TUNNEL_TYPE_GENEVE:
6262         case RTE_TUNNEL_TYPE_TEREDO:
6263                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6264                 ret = -1;
6265                 break;
6266         default:
6267                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6268                 ret = -1;
6269                 break;
6270         }
6271
6272         return ret;
6273 }
6274
6275 /* Calculate the maximum number of contiguous PF queues that are configured */
6276 static int
6277 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6278 {
6279         struct rte_eth_dev_data *data = pf->dev_data;
6280         int i, num;
6281         struct i40e_rx_queue *rxq;
6282
6283         num = 0;
6284         for (i = 0; i < pf->lan_nb_qps; i++) {
6285                 rxq = data->rx_queues[i];
6286                 if (rxq && rxq->q_set)
6287                         num++;
6288                 else
6289                         break;
6290         }
6291
6292         return num;
6293 }
6294
6295 /* Configure RSS */
6296 static int
6297 i40e_pf_config_rss(struct i40e_pf *pf)
6298 {
6299         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6300         struct rte_eth_rss_conf rss_conf;
6301         uint32_t i, lut = 0;
6302         uint16_t j, num;
6303
6304         /*
6305          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6306          * It's necessary to calulate the actual PF queues that are configured.
6307          */
6308         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6309                 num = i40e_pf_calc_configured_queues_num(pf);
6310         else
6311                 num = pf->dev_data->nb_rx_queues;
6312
6313         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6314         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6315                         num);
6316
6317         if (num == 0) {
6318                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6319                 return -ENOTSUP;
6320         }
6321
6322         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6323                 if (j == num)
6324                         j = 0;
6325                 lut = (lut << 8) | (j & ((0x1 <<
6326                         hw->func_caps.rss_table_entry_width) - 1));
6327                 if ((i & 3) == 3)
6328                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6329         }
6330
6331         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6332         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6333                 i40e_pf_disable_rss(pf);
6334                 return 0;
6335         }
6336         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6337                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6338                 /* Random default keys */
6339                 static uint32_t rss_key_default[] = {0x6b793944,
6340                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6341                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6342                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6343
6344                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6345                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6346                                                         sizeof(uint32_t);
6347         }
6348
6349         return i40e_hw_rss_hash_set(pf, &rss_conf);
6350 }
6351
6352 static int
6353 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6354                                struct rte_eth_tunnel_filter_conf *filter)
6355 {
6356         if (pf == NULL || filter == NULL) {
6357                 PMD_DRV_LOG(ERR, "Invalid parameter");
6358                 return -EINVAL;
6359         }
6360
6361         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6362                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6363                 return -EINVAL;
6364         }
6365
6366         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6367                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6368                 return -EINVAL;
6369         }
6370
6371         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6372                 (is_zero_ether_addr(&filter->outer_mac))) {
6373                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6374                 return -EINVAL;
6375         }
6376
6377         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6378                 (is_zero_ether_addr(&filter->inner_mac))) {
6379                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6380                 return -EINVAL;
6381         }
6382
6383         return 0;
6384 }
6385
6386 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6387 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6388 static int
6389 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6390 {
6391         uint32_t val, reg;
6392         int ret = -EINVAL;
6393
6394         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6395         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6396
6397         if (len == 3) {
6398                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6399         } else if (len == 4) {
6400                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6401         } else {
6402                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6403                 return ret;
6404         }
6405
6406         if (reg != val) {
6407                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6408                                                    reg, NULL);
6409                 if (ret != 0)
6410                         return ret;
6411         } else {
6412                 ret = 0;
6413         }
6414         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6415                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6416
6417         return ret;
6418 }
6419
6420 static int
6421 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6422 {
6423         int ret = -EINVAL;
6424
6425         if (!hw || !cfg)
6426                 return -EINVAL;
6427
6428         switch (cfg->cfg_type) {
6429         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6430                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6431                 break;
6432         default:
6433                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6434                 break;
6435         }
6436
6437         return ret;
6438 }
6439
6440 static int
6441 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6442                                enum rte_filter_op filter_op,
6443                                void *arg)
6444 {
6445         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6446         int ret = I40E_ERR_PARAM;
6447
6448         switch (filter_op) {
6449         case RTE_ETH_FILTER_SET:
6450                 ret = i40e_dev_global_config_set(hw,
6451                         (struct rte_eth_global_cfg *)arg);
6452                 break;
6453         default:
6454                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6455                 break;
6456         }
6457
6458         return ret;
6459 }
6460
6461 static int
6462 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6463                           enum rte_filter_op filter_op,
6464                           void *arg)
6465 {
6466         struct rte_eth_tunnel_filter_conf *filter;
6467         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6468         int ret = I40E_SUCCESS;
6469
6470         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6471
6472         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6473                 return I40E_ERR_PARAM;
6474
6475         switch (filter_op) {
6476         case RTE_ETH_FILTER_NOP:
6477                 if (!(pf->flags & I40E_FLAG_VXLAN))
6478                         ret = I40E_NOT_SUPPORTED;
6479                 break;
6480         case RTE_ETH_FILTER_ADD:
6481                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6482                 break;
6483         case RTE_ETH_FILTER_DELETE:
6484                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6485                 break;
6486         default:
6487                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6488                 ret = I40E_ERR_PARAM;
6489                 break;
6490         }
6491
6492         return ret;
6493 }
6494
6495 static int
6496 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6497 {
6498         int ret = 0;
6499         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6500
6501         /* RSS setup */
6502         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6503                 ret = i40e_pf_config_rss(pf);
6504         else
6505                 i40e_pf_disable_rss(pf);
6506
6507         return ret;
6508 }
6509
6510 /* Get the symmetric hash enable configurations per port */
6511 static void
6512 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6513 {
6514         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6515
6516         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6517 }
6518
6519 /* Set the symmetric hash enable configurations per port */
6520 static void
6521 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6522 {
6523         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6524
6525         if (enable > 0) {
6526                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6527                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6528                                                         "been enabled");
6529                         return;
6530                 }
6531                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6532         } else {
6533                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6534                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6535                                                         "been disabled");
6536                         return;
6537                 }
6538                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6539         }
6540         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6541         I40E_WRITE_FLUSH(hw);
6542 }
6543
6544 /*
6545  * Get global configurations of hash function type and symmetric hash enable
6546  * per flow type (pctype). Note that global configuration means it affects all
6547  * the ports on the same NIC.
6548  */
6549 static int
6550 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6551                                    struct rte_eth_hash_global_conf *g_cfg)
6552 {
6553         uint32_t reg, mask = I40E_FLOW_TYPES;
6554         uint16_t i;
6555         enum i40e_filter_pctype pctype;
6556
6557         memset(g_cfg, 0, sizeof(*g_cfg));
6558         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6559         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6560                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6561         else
6562                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6563         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6564                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6565
6566         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6567                 if (!(mask & (1UL << i)))
6568                         continue;
6569                 mask &= ~(1UL << i);
6570                 /* Bit set indicats the coresponding flow type is supported */
6571                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6572                 pctype = i40e_flowtype_to_pctype(i);
6573                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6574                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6575                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6576         }
6577
6578         return 0;
6579 }
6580
6581 static int
6582 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6583 {
6584         uint32_t i;
6585         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6586
6587         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6588                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6589                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6590                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6591                                                 g_cfg->hash_func);
6592                 return -EINVAL;
6593         }
6594
6595         /*
6596          * As i40e supports less than 32 flow types, only first 32 bits need to
6597          * be checked.
6598          */
6599         mask0 = g_cfg->valid_bit_mask[0];
6600         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6601                 if (i == 0) {
6602                         /* Check if any unsupported flow type configured */
6603                         if ((mask0 | i40e_mask) ^ i40e_mask)
6604                                 goto mask_err;
6605                 } else {
6606                         if (g_cfg->valid_bit_mask[i])
6607                                 goto mask_err;
6608                 }
6609         }
6610
6611         return 0;
6612
6613 mask_err:
6614         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6615
6616         return -EINVAL;
6617 }
6618
6619 /*
6620  * Set global configurations of hash function type and symmetric hash enable
6621  * per flow type (pctype). Note any modifying global configuration will affect
6622  * all the ports on the same NIC.
6623  */
6624 static int
6625 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6626                                    struct rte_eth_hash_global_conf *g_cfg)
6627 {
6628         int ret;
6629         uint16_t i;
6630         uint32_t reg;
6631         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6632         enum i40e_filter_pctype pctype;
6633
6634         /* Check the input parameters */
6635         ret = i40e_hash_global_config_check(g_cfg);
6636         if (ret < 0)
6637                 return ret;
6638
6639         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6640                 if (!(mask0 & (1UL << i)))
6641                         continue;
6642                 mask0 &= ~(1UL << i);
6643                 pctype = i40e_flowtype_to_pctype(i);
6644                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6645                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6646                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6647         }
6648
6649         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6650         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6651                 /* Toeplitz */
6652                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6653                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6654                                                                 "Toeplitz");
6655                         goto out;
6656                 }
6657                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6658         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6659                 /* Simple XOR */
6660                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6661                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6662                                                         "Simple XOR");
6663                         goto out;
6664                 }
6665                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6666         } else
6667                 /* Use the default, and keep it as it is */
6668                 goto out;
6669
6670         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6671
6672 out:
6673         I40E_WRITE_FLUSH(hw);
6674
6675         return 0;
6676 }
6677
6678 /**
6679  * Valid input sets for hash and flow director filters per PCTYPE
6680  */
6681 static uint64_t
6682 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6683                 enum rte_filter_type filter)
6684 {
6685         uint64_t valid;
6686
6687         static const uint64_t valid_hash_inset_table[] = {
6688                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6689                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6690                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6691                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6692                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6693                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6694                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6695                         I40E_INSET_FLEX_PAYLOAD,
6696                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6697                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6698                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6699                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6700                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6701                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6702                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6703                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6704                         I40E_INSET_FLEX_PAYLOAD,
6705                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6706                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6707                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6708                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6709                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6710                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6711                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6712                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6713                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6714                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6715                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6716                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6717                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6718                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6719                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6720                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6721                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6722                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6723                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6724                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6725                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6726                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6727                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6728                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6729                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6730                         I40E_INSET_FLEX_PAYLOAD,
6731                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6732                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6733                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6734                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6735                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6736                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6737                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6738                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6739                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6740                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6741                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6742                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6743                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6744                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6745                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6746                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6747                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6748                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6749                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6750                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6751                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6752                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6753                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6754                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6755                         I40E_INSET_FLEX_PAYLOAD,
6756                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6757                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6758                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6759                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6760                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6761                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6762                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6763                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6764                         I40E_INSET_FLEX_PAYLOAD,
6765                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6766                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6767                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6768                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6769                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6770                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6771                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6772                         I40E_INSET_FLEX_PAYLOAD,
6773                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6774                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6775                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6776                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6777                         I40E_INSET_FLEX_PAYLOAD,
6778         };
6779
6780         /**
6781          * Flow director supports only fields defined in
6782          * union rte_eth_fdir_flow.
6783          */
6784         static const uint64_t valid_fdir_inset_table[] = {
6785                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6786                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6787                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6788                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6789                 I40E_INSET_IPV4_TTL,
6790                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6791                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6792                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6793                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6794                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6795                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6796                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6797                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6798                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6799                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6800                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6801                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6802                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6803                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6804                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6805                 I40E_INSET_SCTP_VT,
6806                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6807                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6808                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6809                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6810                 I40E_INSET_IPV4_TTL,
6811                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6812                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6813                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6814                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6815                 I40E_INSET_IPV6_HOP_LIMIT,
6816                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6817                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6818                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6819                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6820                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6821                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6822                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6823                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6824                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6825                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6826                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6827                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6828                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6829                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6830                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6831                 I40E_INSET_SCTP_VT,
6832                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6833                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6834                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6835                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6836                 I40E_INSET_IPV6_HOP_LIMIT,
6837                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6838                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6839                 I40E_INSET_LAST_ETHER_TYPE,
6840         };
6841
6842         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6843                 return 0;
6844         if (filter == RTE_ETH_FILTER_HASH)
6845                 valid = valid_hash_inset_table[pctype];
6846         else
6847                 valid = valid_fdir_inset_table[pctype];
6848
6849         return valid;
6850 }
6851
6852 /**
6853  * Validate if the input set is allowed for a specific PCTYPE
6854  */
6855 static int
6856 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6857                 enum rte_filter_type filter, uint64_t inset)
6858 {
6859         uint64_t valid;
6860
6861         valid = i40e_get_valid_input_set(pctype, filter);
6862         if (inset & (~valid))
6863                 return -EINVAL;
6864
6865         return 0;
6866 }
6867
6868 /* default input set fields combination per pctype */
6869 static uint64_t
6870 i40e_get_default_input_set(uint16_t pctype)
6871 {
6872         static const uint64_t default_inset_table[] = {
6873                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6874                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6875                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6876                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6877                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6878                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6879                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6880                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6881                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6882                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6883                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6884                         I40E_INSET_SCTP_VT,
6885                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6886                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6887                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6888                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6889                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6890                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6891                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6892                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6893                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6894                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6895                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6896                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6897                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6898                         I40E_INSET_SCTP_VT,
6899                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6900                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6901                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6902                         I40E_INSET_LAST_ETHER_TYPE,
6903         };
6904
6905         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6906                 return 0;
6907
6908         return default_inset_table[pctype];
6909 }
6910
6911 /**
6912  * Parse the input set from index to logical bit masks
6913  */
6914 static int
6915 i40e_parse_input_set(uint64_t *inset,
6916                      enum i40e_filter_pctype pctype,
6917                      enum rte_eth_input_set_field *field,
6918                      uint16_t size)
6919 {
6920         uint16_t i, j;
6921         int ret = -EINVAL;
6922
6923         static const struct {
6924                 enum rte_eth_input_set_field field;
6925                 uint64_t inset;
6926         } inset_convert_table[] = {
6927                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6928                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6929                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6930                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6931                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6932                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6933                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6934                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6935                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6936                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6937                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
6938                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6939                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6940                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6941                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6942                         I40E_INSET_IPV6_NEXT_HDR},
6943                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
6944                         I40E_INSET_IPV6_HOP_LIMIT},
6945                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6946                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6947                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6948                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6949                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6950                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6951                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6952                         I40E_INSET_SCTP_VT},
6953                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6954                         I40E_INSET_TUNNEL_DMAC},
6955                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6956                         I40E_INSET_VLAN_TUNNEL},
6957                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6958                         I40E_INSET_TUNNEL_ID},
6959                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6960                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6961                         I40E_INSET_FLEX_PAYLOAD_W1},
6962                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6963                         I40E_INSET_FLEX_PAYLOAD_W2},
6964                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6965                         I40E_INSET_FLEX_PAYLOAD_W3},
6966                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6967                         I40E_INSET_FLEX_PAYLOAD_W4},
6968                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6969                         I40E_INSET_FLEX_PAYLOAD_W5},
6970                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6971                         I40E_INSET_FLEX_PAYLOAD_W6},
6972                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6973                         I40E_INSET_FLEX_PAYLOAD_W7},
6974                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6975                         I40E_INSET_FLEX_PAYLOAD_W8},
6976         };
6977
6978         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6979                 return ret;
6980
6981         /* Only one item allowed for default or all */
6982         if (size == 1) {
6983                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6984                         *inset = i40e_get_default_input_set(pctype);
6985                         return 0;
6986                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6987                         *inset = I40E_INSET_NONE;
6988                         return 0;
6989                 }
6990         }
6991
6992         for (i = 0, *inset = 0; i < size; i++) {
6993                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6994                         if (field[i] == inset_convert_table[j].field) {
6995                                 *inset |= inset_convert_table[j].inset;
6996                                 break;
6997                         }
6998                 }
6999
7000                 /* It contains unsupported input set, return immediately */
7001                 if (j == RTE_DIM(inset_convert_table))
7002                         return ret;
7003         }
7004
7005         return 0;
7006 }
7007
7008 /**
7009  * Translate the input set from bit masks to register aware bit masks
7010  * and vice versa
7011  */
7012 static uint64_t
7013 i40e_translate_input_set_reg(uint64_t input)
7014 {
7015         uint64_t val = 0;
7016         uint16_t i;
7017
7018         static const struct {
7019                 uint64_t inset;
7020                 uint64_t inset_reg;
7021         } inset_map[] = {
7022                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7023                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7024                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7025                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7026                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7027                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7028                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7029                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7030                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7031                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7032                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7033                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7034                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7035                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7036                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7037                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7038                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7039                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7040                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7041                 {I40E_INSET_TUNNEL_DMAC,
7042                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7043                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7044                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7045                 {I40E_INSET_TUNNEL_SRC_PORT,
7046                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7047                 {I40E_INSET_TUNNEL_DST_PORT,
7048                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7049                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7050                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7051                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7052                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7053                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7054                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7055                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7056                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7057                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7058         };
7059
7060         if (input == 0)
7061                 return val;
7062
7063         /* Translate input set to register aware inset */
7064         for (i = 0; i < RTE_DIM(inset_map); i++) {
7065                 if (input & inset_map[i].inset)
7066                         val |= inset_map[i].inset_reg;
7067         }
7068
7069         return val;
7070 }
7071
7072 static int
7073 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7074 {
7075         uint8_t i, idx = 0;
7076         uint64_t inset_need_mask = inset;
7077
7078         static const struct {
7079                 uint64_t inset;
7080                 uint32_t mask;
7081         } inset_mask_map[] = {
7082                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7083                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7084                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7085                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7086                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7087                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7088                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7089                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7090         };
7091
7092         if (!inset || !mask || !nb_elem)
7093                 return 0;
7094
7095         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7096                 /* Clear the inset bit, if no MASK is required,
7097                  * for example proto + ttl
7098                  */
7099                 if ((inset & inset_mask_map[i].inset) ==
7100                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7101                         inset_need_mask &= ~inset_mask_map[i].inset;
7102                 if (!inset_need_mask)
7103                         return 0;
7104         }
7105         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7106                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7107                     inset_mask_map[i].inset) {
7108                         if (idx >= nb_elem) {
7109                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7110                                 return -EINVAL;
7111                         }
7112                         mask[idx] = inset_mask_map[i].mask;
7113                         idx++;
7114                 }
7115         }
7116
7117         return idx;
7118 }
7119
7120 static void
7121 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7122 {
7123         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7124
7125         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7126         if (reg != val)
7127                 i40e_write_rx_ctl(hw, addr, val);
7128         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7129                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7130 }
7131
7132 static void
7133 i40e_filter_input_set_init(struct i40e_pf *pf)
7134 {
7135         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7136         enum i40e_filter_pctype pctype;
7137         uint64_t input_set, inset_reg;
7138         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7139         int num, i;
7140
7141         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7142              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7143                 if (!I40E_VALID_PCTYPE(pctype))
7144                         continue;
7145                 input_set = i40e_get_default_input_set(pctype);
7146
7147                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7148                                                    I40E_INSET_MASK_NUM_REG);
7149                 if (num < 0)
7150                         return;
7151                 inset_reg = i40e_translate_input_set_reg(input_set);
7152
7153                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7154                                       (uint32_t)(inset_reg & UINT32_MAX));
7155                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7156                                      (uint32_t)((inset_reg >>
7157                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7158                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7159                                       (uint32_t)(inset_reg & UINT32_MAX));
7160                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7161                                      (uint32_t)((inset_reg >>
7162                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7163
7164                 for (i = 0; i < num; i++) {
7165                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7166                                              mask_reg[i]);
7167                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7168                                              mask_reg[i]);
7169                 }
7170                 /*clear unused mask registers of the pctype */
7171                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7172                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7173                                              0);
7174                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7175                                              0);
7176                 }
7177                 I40E_WRITE_FLUSH(hw);
7178
7179                 /* store the default input set */
7180                 pf->hash_input_set[pctype] = input_set;
7181                 pf->fdir.input_set[pctype] = input_set;
7182         }
7183 }
7184
7185 int
7186 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7187                          struct rte_eth_input_set_conf *conf)
7188 {
7189         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7190         enum i40e_filter_pctype pctype;
7191         uint64_t input_set, inset_reg = 0;
7192         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7193         int ret, i, num;
7194
7195         if (!conf) {
7196                 PMD_DRV_LOG(ERR, "Invalid pointer");
7197                 return -EFAULT;
7198         }
7199         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7200             conf->op != RTE_ETH_INPUT_SET_ADD) {
7201                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7202                 return -EINVAL;
7203         }
7204
7205         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7206         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7207                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7208                             conf->flow_type);
7209                 return -EINVAL;
7210         }
7211
7212         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7213                                    conf->inset_size);
7214         if (ret) {
7215                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7216                 return -EINVAL;
7217         }
7218         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7219                                     input_set) != 0) {
7220                 PMD_DRV_LOG(ERR, "Invalid input set");
7221                 return -EINVAL;
7222         }
7223         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7224                 /* get inset value in register */
7225                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7226                 inset_reg <<= I40E_32_BIT_WIDTH;
7227                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7228                 input_set |= pf->hash_input_set[pctype];
7229         }
7230         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7231                                            I40E_INSET_MASK_NUM_REG);
7232         if (num < 0)
7233                 return -EINVAL;
7234
7235         inset_reg |= i40e_translate_input_set_reg(input_set);
7236
7237         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7238                               (uint32_t)(inset_reg & UINT32_MAX));
7239         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7240                              (uint32_t)((inset_reg >>
7241                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7242
7243         for (i = 0; i < num; i++)
7244                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7245                                      mask_reg[i]);
7246         /*clear unused mask registers of the pctype */
7247         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7248                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7249                                      0);
7250         I40E_WRITE_FLUSH(hw);
7251
7252         pf->hash_input_set[pctype] = input_set;
7253         return 0;
7254 }
7255
7256 int
7257 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7258                          struct rte_eth_input_set_conf *conf)
7259 {
7260         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7261         enum i40e_filter_pctype pctype;
7262         uint64_t input_set, inset_reg = 0;
7263         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7264         int ret, i, num;
7265
7266         if (!hw || !conf) {
7267                 PMD_DRV_LOG(ERR, "Invalid pointer");
7268                 return -EFAULT;
7269         }
7270         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7271             conf->op != RTE_ETH_INPUT_SET_ADD) {
7272                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7273                 return -EINVAL;
7274         }
7275
7276         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7277         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7278                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7279                             conf->flow_type);
7280                 return -EINVAL;
7281         }
7282         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7283                                    conf->inset_size);
7284         if (ret) {
7285                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7286                 return -EINVAL;
7287         }
7288         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7289                                     input_set) != 0) {
7290                 PMD_DRV_LOG(ERR, "Invalid input set");
7291                 return -EINVAL;
7292         }
7293
7294         /* get inset value in register */
7295         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7296         inset_reg <<= I40E_32_BIT_WIDTH;
7297         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7298
7299         /* Can not change the inset reg for flex payload for fdir,
7300          * it is done by writing I40E_PRTQF_FD_FLXINSET
7301          * in i40e_set_flex_mask_on_pctype.
7302          */
7303         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7304                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7305         else
7306                 input_set |= pf->fdir.input_set[pctype];
7307         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7308                                            I40E_INSET_MASK_NUM_REG);
7309         if (num < 0)
7310                 return -EINVAL;
7311
7312         inset_reg |= i40e_translate_input_set_reg(input_set);
7313
7314         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7315                               (uint32_t)(inset_reg & UINT32_MAX));
7316         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7317                              (uint32_t)((inset_reg >>
7318                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7319
7320         for (i = 0; i < num; i++)
7321                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7322                                      mask_reg[i]);
7323         /*clear unused mask registers of the pctype */
7324         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7325                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7326                                      0);
7327         I40E_WRITE_FLUSH(hw);
7328
7329         pf->fdir.input_set[pctype] = input_set;
7330         return 0;
7331 }
7332
7333 static int
7334 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7335 {
7336         int ret = 0;
7337
7338         if (!hw || !info) {
7339                 PMD_DRV_LOG(ERR, "Invalid pointer");
7340                 return -EFAULT;
7341         }
7342
7343         switch (info->info_type) {
7344         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7345                 i40e_get_symmetric_hash_enable_per_port(hw,
7346                                         &(info->info.enable));
7347                 break;
7348         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7349                 ret = i40e_get_hash_filter_global_config(hw,
7350                                 &(info->info.global_conf));
7351                 break;
7352         default:
7353                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7354                                                         info->info_type);
7355                 ret = -EINVAL;
7356                 break;
7357         }
7358
7359         return ret;
7360 }
7361
7362 static int
7363 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7364 {
7365         int ret = 0;
7366
7367         if (!hw || !info) {
7368                 PMD_DRV_LOG(ERR, "Invalid pointer");
7369                 return -EFAULT;
7370         }
7371
7372         switch (info->info_type) {
7373         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7374                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7375                 break;
7376         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7377                 ret = i40e_set_hash_filter_global_config(hw,
7378                                 &(info->info.global_conf));
7379                 break;
7380         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7381                 ret = i40e_hash_filter_inset_select(hw,
7382                                                &(info->info.input_set_conf));
7383                 break;
7384
7385         default:
7386                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7387                                                         info->info_type);
7388                 ret = -EINVAL;
7389                 break;
7390         }
7391
7392         return ret;
7393 }
7394
7395 /* Operations for hash function */
7396 static int
7397 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7398                       enum rte_filter_op filter_op,
7399                       void *arg)
7400 {
7401         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7402         int ret = 0;
7403
7404         switch (filter_op) {
7405         case RTE_ETH_FILTER_NOP:
7406                 break;
7407         case RTE_ETH_FILTER_GET:
7408                 ret = i40e_hash_filter_get(hw,
7409                         (struct rte_eth_hash_filter_info *)arg);
7410                 break;
7411         case RTE_ETH_FILTER_SET:
7412                 ret = i40e_hash_filter_set(hw,
7413                         (struct rte_eth_hash_filter_info *)arg);
7414                 break;
7415         default:
7416                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7417                                                                 filter_op);
7418                 ret = -ENOTSUP;
7419                 break;
7420         }
7421
7422         return ret;
7423 }
7424
7425 /*
7426  * Configure ethertype filter, which can director packet by filtering
7427  * with mac address and ether_type or only ether_type
7428  */
7429 static int
7430 i40e_ethertype_filter_set(struct i40e_pf *pf,
7431                         struct rte_eth_ethertype_filter *filter,
7432                         bool add)
7433 {
7434         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7435         struct i40e_control_filter_stats stats;
7436         uint16_t flags = 0;
7437         int ret;
7438
7439         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7440                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7441                 return -EINVAL;
7442         }
7443         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7444                 filter->ether_type == ETHER_TYPE_IPv6) {
7445                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7446                         " control packet filter.", filter->ether_type);
7447                 return -EINVAL;
7448         }
7449         if (filter->ether_type == ETHER_TYPE_VLAN)
7450                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7451                         " not supported.");
7452
7453         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7454                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7455         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7456                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7457         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7458
7459         memset(&stats, 0, sizeof(stats));
7460         ret = i40e_aq_add_rem_control_packet_filter(hw,
7461                         filter->mac_addr.addr_bytes,
7462                         filter->ether_type, flags,
7463                         pf->main_vsi->seid,
7464                         filter->queue, add, &stats, NULL);
7465
7466         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7467                          " mac_etype_used = %u, etype_used = %u,"
7468                          " mac_etype_free = %u, etype_free = %u\n",
7469                          ret, stats.mac_etype_used, stats.etype_used,
7470                          stats.mac_etype_free, stats.etype_free);
7471         if (ret < 0)
7472                 return -ENOSYS;
7473         return 0;
7474 }
7475
7476 /*
7477  * Handle operations for ethertype filter.
7478  */
7479 static int
7480 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7481                                 enum rte_filter_op filter_op,
7482                                 void *arg)
7483 {
7484         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7485         int ret = 0;
7486
7487         if (filter_op == RTE_ETH_FILTER_NOP)
7488                 return ret;
7489
7490         if (arg == NULL) {
7491                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7492                             filter_op);
7493                 return -EINVAL;
7494         }
7495
7496         switch (filter_op) {
7497         case RTE_ETH_FILTER_ADD:
7498                 ret = i40e_ethertype_filter_set(pf,
7499                         (struct rte_eth_ethertype_filter *)arg,
7500                         TRUE);
7501                 break;
7502         case RTE_ETH_FILTER_DELETE:
7503                 ret = i40e_ethertype_filter_set(pf,
7504                         (struct rte_eth_ethertype_filter *)arg,
7505                         FALSE);
7506                 break;
7507         default:
7508                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7509                 ret = -ENOSYS;
7510                 break;
7511         }
7512         return ret;
7513 }
7514
7515 static int
7516 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7517                      enum rte_filter_type filter_type,
7518                      enum rte_filter_op filter_op,
7519                      void *arg)
7520 {
7521         int ret = 0;
7522
7523         if (dev == NULL)
7524                 return -EINVAL;
7525
7526         switch (filter_type) {
7527         case RTE_ETH_FILTER_NONE:
7528                 /* For global configuration */
7529                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7530                 break;
7531         case RTE_ETH_FILTER_HASH:
7532                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7533                 break;
7534         case RTE_ETH_FILTER_MACVLAN:
7535                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7536                 break;
7537         case RTE_ETH_FILTER_ETHERTYPE:
7538                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7539                 break;
7540         case RTE_ETH_FILTER_TUNNEL:
7541                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7542                 break;
7543         case RTE_ETH_FILTER_FDIR:
7544                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7545                 break;
7546         default:
7547                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7548                                                         filter_type);
7549                 ret = -EINVAL;
7550                 break;
7551         }
7552
7553         return ret;
7554 }
7555
7556 /*
7557  * Check and enable Extended Tag.
7558  * Enabling Extended Tag is important for 40G performance.
7559  */
7560 static void
7561 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7562 {
7563         uint32_t buf = 0;
7564         int ret;
7565
7566         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7567                                       PCI_DEV_CAP_REG);
7568         if (ret < 0) {
7569                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7570                             PCI_DEV_CAP_REG);
7571                 return;
7572         }
7573         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7574                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7575                 return;
7576         }
7577
7578         buf = 0;
7579         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7580                                       PCI_DEV_CTRL_REG);
7581         if (ret < 0) {
7582                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7583                             PCI_DEV_CTRL_REG);
7584                 return;
7585         }
7586         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7587                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7588                 return;
7589         }
7590         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7591         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7592                                        PCI_DEV_CTRL_REG);
7593         if (ret < 0) {
7594                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7595                             PCI_DEV_CTRL_REG);
7596                 return;
7597         }
7598 }
7599
7600 /*
7601  * As some registers wouldn't be reset unless a global hardware reset,
7602  * hardware initialization is needed to put those registers into an
7603  * expected initial state.
7604  */
7605 static void
7606 i40e_hw_init(struct rte_eth_dev *dev)
7607 {
7608         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7609
7610         i40e_enable_extended_tag(dev);
7611
7612         /* clear the PF Queue Filter control register */
7613         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7614
7615         /* Disable symmetric hash per port */
7616         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7617 }
7618
7619 enum i40e_filter_pctype
7620 i40e_flowtype_to_pctype(uint16_t flow_type)
7621 {
7622         static const enum i40e_filter_pctype pctype_table[] = {
7623                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7624                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7625                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7626                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7627                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7628                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7629                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7630                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7631                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7632                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7633                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7634                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7635                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7636                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7637                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7638                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7639                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7640                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7641                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7642         };
7643
7644         return pctype_table[flow_type];
7645 }
7646
7647 uint16_t
7648 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7649 {
7650         static const uint16_t flowtype_table[] = {
7651                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7652                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7653                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7654                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7655                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7656                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7657                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7658                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7659                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7660                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7661                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7662                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7663                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7664                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7665                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7666                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7667                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7668                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7669                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7670         };
7671
7672         return flowtype_table[pctype];
7673 }
7674
7675 /*
7676  * On X710, performance number is far from the expectation on recent firmware
7677  * versions; on XL710, performance number is also far from the expectation on
7678  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7679  * mode is enabled and port MAC address is equal to the packet destination MAC
7680  * address. The fix for this issue may not be integrated in the following
7681  * firmware version. So the workaround in software driver is needed. It needs
7682  * to modify the initial values of 3 internal only registers for both X710 and
7683  * XL710. Note that the values for X710 or XL710 could be different, and the
7684  * workaround can be removed when it is fixed in firmware in the future.
7685  */
7686
7687 /* For both X710 and XL710 */
7688 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7689 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7690
7691 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7692 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7693
7694 /* For X710 */
7695 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7696 /* For XL710 */
7697 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7698 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7699
7700 static void
7701 i40e_configure_registers(struct i40e_hw *hw)
7702 {
7703         static struct {
7704                 uint32_t addr;
7705                 uint64_t val;
7706         } reg_table[] = {
7707                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7708                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7709                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7710         };
7711         uint64_t reg;
7712         uint32_t i;
7713         int ret;
7714
7715         for (i = 0; i < RTE_DIM(reg_table); i++) {
7716                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7717                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7718                                 reg_table[i].val =
7719                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7720                         else /* For X710 */
7721                                 reg_table[i].val =
7722                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7723                 }
7724
7725                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7726                                                         &reg, NULL);
7727                 if (ret < 0) {
7728                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7729                                                         reg_table[i].addr);
7730                         break;
7731                 }
7732                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7733                                                 reg_table[i].addr, reg);
7734                 if (reg == reg_table[i].val)
7735                         continue;
7736
7737                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7738                                                 reg_table[i].val, NULL);
7739                 if (ret < 0) {
7740                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7741                                 "address of 0x%"PRIx32, reg_table[i].val,
7742                                                         reg_table[i].addr);
7743                         break;
7744                 }
7745                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7746                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7747         }
7748 }
7749
7750 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7751 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7752 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7753 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7754 static int
7755 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7756 {
7757         uint32_t reg;
7758         int ret;
7759
7760         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7761                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7762                 return -EINVAL;
7763         }
7764
7765         /* Configure for double VLAN RX stripping */
7766         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7767         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7768                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7769                 ret = i40e_aq_debug_write_register(hw,
7770                                                    I40E_VSI_TSR(vsi->vsi_id),
7771                                                    reg, NULL);
7772                 if (ret < 0) {
7773                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7774                                     vsi->vsi_id);
7775                         return I40E_ERR_CONFIG;
7776                 }
7777         }
7778
7779         /* Configure for double VLAN TX insertion */
7780         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7781         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7782                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7783                 ret = i40e_aq_debug_write_register(hw,
7784                                                    I40E_VSI_L2TAGSTXVALID(
7785                                                    vsi->vsi_id), reg, NULL);
7786                 if (ret < 0) {
7787                         PMD_DRV_LOG(ERR, "Failed to update "
7788                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7789                         return I40E_ERR_CONFIG;
7790                 }
7791         }
7792
7793         return 0;
7794 }
7795
7796 /**
7797  * i40e_aq_add_mirror_rule
7798  * @hw: pointer to the hardware structure
7799  * @seid: VEB seid to add mirror rule to
7800  * @dst_id: destination vsi seid
7801  * @entries: Buffer which contains the entities to be mirrored
7802  * @count: number of entities contained in the buffer
7803  * @rule_id:the rule_id of the rule to be added
7804  *
7805  * Add a mirror rule for a given veb.
7806  *
7807  **/
7808 static enum i40e_status_code
7809 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7810                         uint16_t seid, uint16_t dst_id,
7811                         uint16_t rule_type, uint16_t *entries,
7812                         uint16_t count, uint16_t *rule_id)
7813 {
7814         struct i40e_aq_desc desc;
7815         struct i40e_aqc_add_delete_mirror_rule cmd;
7816         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7817                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7818                 &desc.params.raw;
7819         uint16_t buff_len;
7820         enum i40e_status_code status;
7821
7822         i40e_fill_default_direct_cmd_desc(&desc,
7823                                           i40e_aqc_opc_add_mirror_rule);
7824         memset(&cmd, 0, sizeof(cmd));
7825
7826         buff_len = sizeof(uint16_t) * count;
7827         desc.datalen = rte_cpu_to_le_16(buff_len);
7828         if (buff_len > 0)
7829                 desc.flags |= rte_cpu_to_le_16(
7830                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7831         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7832                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7833         cmd.num_entries = rte_cpu_to_le_16(count);
7834         cmd.seid = rte_cpu_to_le_16(seid);
7835         cmd.destination = rte_cpu_to_le_16(dst_id);
7836
7837         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7838         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7839         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7840                          "rule_id = %u"
7841                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7842                          hw->aq.asq_last_status, resp->rule_id,
7843                          resp->mirror_rules_used, resp->mirror_rules_free);
7844         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7845
7846         return status;
7847 }
7848
7849 /**
7850  * i40e_aq_del_mirror_rule
7851  * @hw: pointer to the hardware structure
7852  * @seid: VEB seid to add mirror rule to
7853  * @entries: Buffer which contains the entities to be mirrored
7854  * @count: number of entities contained in the buffer
7855  * @rule_id:the rule_id of the rule to be delete
7856  *
7857  * Delete a mirror rule for a given veb.
7858  *
7859  **/
7860 static enum i40e_status_code
7861 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7862                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7863                 uint16_t count, uint16_t rule_id)
7864 {
7865         struct i40e_aq_desc desc;
7866         struct i40e_aqc_add_delete_mirror_rule cmd;
7867         uint16_t buff_len = 0;
7868         enum i40e_status_code status;
7869         void *buff = NULL;
7870
7871         i40e_fill_default_direct_cmd_desc(&desc,
7872                                           i40e_aqc_opc_delete_mirror_rule);
7873         memset(&cmd, 0, sizeof(cmd));
7874         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7875                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7876                                                           I40E_AQ_FLAG_RD));
7877                 cmd.num_entries = count;
7878                 buff_len = sizeof(uint16_t) * count;
7879                 desc.datalen = rte_cpu_to_le_16(buff_len);
7880                 buff = (void *)entries;
7881         } else
7882                 /* rule id is filled in destination field for deleting mirror rule */
7883                 cmd.destination = rte_cpu_to_le_16(rule_id);
7884
7885         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7886                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7887         cmd.seid = rte_cpu_to_le_16(seid);
7888
7889         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7890         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7891
7892         return status;
7893 }
7894
7895 /**
7896  * i40e_mirror_rule_set
7897  * @dev: pointer to the hardware structure
7898  * @mirror_conf: mirror rule info
7899  * @sw_id: mirror rule's sw_id
7900  * @on: enable/disable
7901  *
7902  * set a mirror rule.
7903  *
7904  **/
7905 static int
7906 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7907                         struct rte_eth_mirror_conf *mirror_conf,
7908                         uint8_t sw_id, uint8_t on)
7909 {
7910         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7912         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7913         struct i40e_mirror_rule *parent = NULL;
7914         uint16_t seid, dst_seid, rule_id;
7915         uint16_t i, j = 0;
7916         int ret;
7917
7918         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7919
7920         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7921                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7922                         " without veb or vfs.");
7923                 return -ENOSYS;
7924         }
7925         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7926                 PMD_DRV_LOG(ERR, "mirror table is full.");
7927                 return -ENOSPC;
7928         }
7929         if (mirror_conf->dst_pool > pf->vf_num) {
7930                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7931                                  mirror_conf->dst_pool);
7932                 return -EINVAL;
7933         }
7934
7935         seid = pf->main_vsi->veb->seid;
7936
7937         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7938                 if (sw_id <= it->index) {
7939                         mirr_rule = it;
7940                         break;
7941                 }
7942                 parent = it;
7943         }
7944         if (mirr_rule && sw_id == mirr_rule->index) {
7945                 if (on) {
7946                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7947                         return -EEXIST;
7948                 } else {
7949                         ret = i40e_aq_del_mirror_rule(hw, seid,
7950                                         mirr_rule->rule_type,
7951                                         mirr_rule->entries,
7952                                         mirr_rule->num_entries, mirr_rule->id);
7953                         if (ret < 0) {
7954                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7955                                                    " ret = %d, aq_err = %d.",
7956                                                    ret, hw->aq.asq_last_status);
7957                                 return -ENOSYS;
7958                         }
7959                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7960                         rte_free(mirr_rule);
7961                         pf->nb_mirror_rule--;
7962                         return 0;
7963                 }
7964         } else if (!on) {
7965                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7966                 return -ENOENT;
7967         }
7968
7969         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7970                                 sizeof(struct i40e_mirror_rule) , 0);
7971         if (!mirr_rule) {
7972                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7973                 return I40E_ERR_NO_MEMORY;
7974         }
7975         switch (mirror_conf->rule_type) {
7976         case ETH_MIRROR_VLAN:
7977                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7978                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7979                                 mirr_rule->entries[j] =
7980                                         mirror_conf->vlan.vlan_id[i];
7981                                 j++;
7982                         }
7983                 }
7984                 if (j == 0) {
7985                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7986                         rte_free(mirr_rule);
7987                         return -EINVAL;
7988                 }
7989                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7990                 break;
7991         case ETH_MIRROR_VIRTUAL_POOL_UP:
7992         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7993                 /* check if the specified pool bit is out of range */
7994                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7995                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7996                         rte_free(mirr_rule);
7997                         return -EINVAL;
7998                 }
7999                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8000                         if (mirror_conf->pool_mask & (1ULL << i)) {
8001                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8002                                 j++;
8003                         }
8004                 }
8005                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8006                         /* add pf vsi to entries */
8007                         mirr_rule->entries[j] = pf->main_vsi_seid;
8008                         j++;
8009                 }
8010                 if (j == 0) {
8011                         PMD_DRV_LOG(ERR, "pool is not specified.");
8012                         rte_free(mirr_rule);
8013                         return -EINVAL;
8014                 }
8015                 /* egress and ingress in aq commands means from switch but not port */
8016                 mirr_rule->rule_type =
8017                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8018                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8019                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8020                 break;
8021         case ETH_MIRROR_UPLINK_PORT:
8022                 /* egress and ingress in aq commands means from switch but not port*/
8023                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8024                 break;
8025         case ETH_MIRROR_DOWNLINK_PORT:
8026                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8027                 break;
8028         default:
8029                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8030                         mirror_conf->rule_type);
8031                 rte_free(mirr_rule);
8032                 return -EINVAL;
8033         }
8034
8035         /* If the dst_pool is equal to vf_num, consider it as PF */
8036         if (mirror_conf->dst_pool == pf->vf_num)
8037                 dst_seid = pf->main_vsi_seid;
8038         else
8039                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8040
8041         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8042                                       mirr_rule->rule_type, mirr_rule->entries,
8043                                       j, &rule_id);
8044         if (ret < 0) {
8045                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8046                                    " ret = %d, aq_err = %d.",
8047                                    ret, hw->aq.asq_last_status);
8048                 rte_free(mirr_rule);
8049                 return -ENOSYS;
8050         }
8051
8052         mirr_rule->index = sw_id;
8053         mirr_rule->num_entries = j;
8054         mirr_rule->id = rule_id;
8055         mirr_rule->dst_vsi_seid = dst_seid;
8056
8057         if (parent)
8058                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8059         else
8060                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8061
8062         pf->nb_mirror_rule++;
8063         return 0;
8064 }
8065
8066 /**
8067  * i40e_mirror_rule_reset
8068  * @dev: pointer to the device
8069  * @sw_id: mirror rule's sw_id
8070  *
8071  * reset a mirror rule.
8072  *
8073  **/
8074 static int
8075 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8076 {
8077         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8079         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8080         uint16_t seid;
8081         int ret;
8082
8083         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8084
8085         seid = pf->main_vsi->veb->seid;
8086
8087         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8088                 if (sw_id == it->index) {
8089                         mirr_rule = it;
8090                         break;
8091                 }
8092         }
8093         if (mirr_rule) {
8094                 ret = i40e_aq_del_mirror_rule(hw, seid,
8095                                 mirr_rule->rule_type,
8096                                 mirr_rule->entries,
8097                                 mirr_rule->num_entries, mirr_rule->id);
8098                 if (ret < 0) {
8099                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8100                                            " status = %d, aq_err = %d.",
8101                                            ret, hw->aq.asq_last_status);
8102                         return -ENOSYS;
8103                 }
8104                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8105                 rte_free(mirr_rule);
8106                 pf->nb_mirror_rule--;
8107         } else {
8108                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8109                 return -ENOENT;
8110         }
8111         return 0;
8112 }
8113
8114 static uint64_t
8115 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8116 {
8117         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8118         uint64_t systim_cycles;
8119
8120         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8121         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8122                         << 32;
8123
8124         return systim_cycles;
8125 }
8126
8127 static uint64_t
8128 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8129 {
8130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8131         uint64_t rx_tstamp;
8132
8133         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8134         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8135                         << 32;
8136
8137         return rx_tstamp;
8138 }
8139
8140 static uint64_t
8141 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8142 {
8143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8144         uint64_t tx_tstamp;
8145
8146         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8147         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8148                         << 32;
8149
8150         return tx_tstamp;
8151 }
8152
8153 static void
8154 i40e_start_timecounters(struct rte_eth_dev *dev)
8155 {
8156         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8157         struct i40e_adapter *adapter =
8158                         (struct i40e_adapter *)dev->data->dev_private;
8159         struct rte_eth_link link;
8160         uint32_t tsync_inc_l;
8161         uint32_t tsync_inc_h;
8162
8163         /* Get current link speed. */
8164         memset(&link, 0, sizeof(link));
8165         i40e_dev_link_update(dev, 1);
8166         rte_i40e_dev_atomic_read_link_status(dev, &link);
8167
8168         switch (link.link_speed) {
8169         case ETH_SPEED_NUM_40G:
8170                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8171                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8172                 break;
8173         case ETH_SPEED_NUM_10G:
8174                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8175                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8176                 break;
8177         case ETH_SPEED_NUM_1G:
8178                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8179                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8180                 break;
8181         default:
8182                 tsync_inc_l = 0x0;
8183                 tsync_inc_h = 0x0;
8184         }
8185
8186         /* Set the timesync increment value. */
8187         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8188         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8189
8190         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8191         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8192         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8193
8194         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8195         adapter->systime_tc.cc_shift = 0;
8196         adapter->systime_tc.nsec_mask = 0;
8197
8198         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8199         adapter->rx_tstamp_tc.cc_shift = 0;
8200         adapter->rx_tstamp_tc.nsec_mask = 0;
8201
8202         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8203         adapter->tx_tstamp_tc.cc_shift = 0;
8204         adapter->tx_tstamp_tc.nsec_mask = 0;
8205 }
8206
8207 static int
8208 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8209 {
8210         struct i40e_adapter *adapter =
8211                         (struct i40e_adapter *)dev->data->dev_private;
8212
8213         adapter->systime_tc.nsec += delta;
8214         adapter->rx_tstamp_tc.nsec += delta;
8215         adapter->tx_tstamp_tc.nsec += delta;
8216
8217         return 0;
8218 }
8219
8220 static int
8221 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8222 {
8223         uint64_t ns;
8224         struct i40e_adapter *adapter =
8225                         (struct i40e_adapter *)dev->data->dev_private;
8226
8227         ns = rte_timespec_to_ns(ts);
8228
8229         /* Set the timecounters to a new value. */
8230         adapter->systime_tc.nsec = ns;
8231         adapter->rx_tstamp_tc.nsec = ns;
8232         adapter->tx_tstamp_tc.nsec = ns;
8233
8234         return 0;
8235 }
8236
8237 static int
8238 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8239 {
8240         uint64_t ns, systime_cycles;
8241         struct i40e_adapter *adapter =
8242                         (struct i40e_adapter *)dev->data->dev_private;
8243
8244         systime_cycles = i40e_read_systime_cyclecounter(dev);
8245         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8246         *ts = rte_ns_to_timespec(ns);
8247
8248         return 0;
8249 }
8250
8251 static int
8252 i40e_timesync_enable(struct rte_eth_dev *dev)
8253 {
8254         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8255         uint32_t tsync_ctl_l;
8256         uint32_t tsync_ctl_h;
8257
8258         /* Stop the timesync system time. */
8259         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8260         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8261         /* Reset the timesync system time value. */
8262         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8263         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8264
8265         i40e_start_timecounters(dev);
8266
8267         /* Clear timesync registers. */
8268         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8269         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8270         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8271         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8272         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8273         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8274
8275         /* Enable timestamping of PTP packets. */
8276         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8277         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8278
8279         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8280         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8281         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8282
8283         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8284         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8285
8286         return 0;
8287 }
8288
8289 static int
8290 i40e_timesync_disable(struct rte_eth_dev *dev)
8291 {
8292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8293         uint32_t tsync_ctl_l;
8294         uint32_t tsync_ctl_h;
8295
8296         /* Disable timestamping of transmitted PTP packets. */
8297         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8298         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8299
8300         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8301         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8302
8303         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8304         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8305
8306         /* Reset the timesync increment value. */
8307         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8308         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8309
8310         return 0;
8311 }
8312
8313 static int
8314 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8315                                 struct timespec *timestamp, uint32_t flags)
8316 {
8317         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8318         struct i40e_adapter *adapter =
8319                 (struct i40e_adapter *)dev->data->dev_private;
8320
8321         uint32_t sync_status;
8322         uint32_t index = flags & 0x03;
8323         uint64_t rx_tstamp_cycles;
8324         uint64_t ns;
8325
8326         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8327         if ((sync_status & (1 << index)) == 0)
8328                 return -EINVAL;
8329
8330         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8331         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8332         *timestamp = rte_ns_to_timespec(ns);
8333
8334         return 0;
8335 }
8336
8337 static int
8338 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8339                                 struct timespec *timestamp)
8340 {
8341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8342         struct i40e_adapter *adapter =
8343                 (struct i40e_adapter *)dev->data->dev_private;
8344
8345         uint32_t sync_status;
8346         uint64_t tx_tstamp_cycles;
8347         uint64_t ns;
8348
8349         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8350         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8351                 return -EINVAL;
8352
8353         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8354         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8355         *timestamp = rte_ns_to_timespec(ns);
8356
8357         return 0;
8358 }
8359
8360 /*
8361  * i40e_parse_dcb_configure - parse dcb configure from user
8362  * @dev: the device being configured
8363  * @dcb_cfg: pointer of the result of parse
8364  * @*tc_map: bit map of enabled traffic classes
8365  *
8366  * Returns 0 on success, negative value on failure
8367  */
8368 static int
8369 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8370                          struct i40e_dcbx_config *dcb_cfg,
8371                          uint8_t *tc_map)
8372 {
8373         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8374         uint8_t i, tc_bw, bw_lf;
8375
8376         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8377
8378         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8379         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8380                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8381                 return -EINVAL;
8382         }
8383
8384         /* assume each tc has the same bw */
8385         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8386         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8387                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8388         /* to ensure the sum of tcbw is equal to 100 */
8389         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8390         for (i = 0; i < bw_lf; i++)
8391                 dcb_cfg->etscfg.tcbwtable[i]++;
8392
8393         /* assume each tc has the same Transmission Selection Algorithm */
8394         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8395                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8396
8397         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8398                 dcb_cfg->etscfg.prioritytable[i] =
8399                                 dcb_rx_conf->dcb_tc[i];
8400
8401         /* FW needs one App to configure HW */
8402         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8403         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8404         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8405         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8406
8407         if (dcb_rx_conf->nb_tcs == 0)
8408                 *tc_map = 1; /* tc0 only */
8409         else
8410                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8411
8412         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8413                 dcb_cfg->pfc.willing = 0;
8414                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8415                 dcb_cfg->pfc.pfcenable = *tc_map;
8416         }
8417         return 0;
8418 }
8419
8420
8421 static enum i40e_status_code
8422 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8423                               struct i40e_aqc_vsi_properties_data *info,
8424                               uint8_t enabled_tcmap)
8425 {
8426         enum i40e_status_code ret;
8427         int i, total_tc = 0;
8428         uint16_t qpnum_per_tc, bsf, qp_idx;
8429         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8430         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8431         uint16_t used_queues;
8432
8433         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8434         if (ret != I40E_SUCCESS)
8435                 return ret;
8436
8437         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8438                 if (enabled_tcmap & (1 << i))
8439                         total_tc++;
8440         }
8441         if (total_tc == 0)
8442                 total_tc = 1;
8443         vsi->enabled_tc = enabled_tcmap;
8444
8445         /* different VSI has different queues assigned */
8446         if (vsi->type == I40E_VSI_MAIN)
8447                 used_queues = dev_data->nb_rx_queues -
8448                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8449         else if (vsi->type == I40E_VSI_VMDQ2)
8450                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8451         else {
8452                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8453                 return I40E_ERR_NO_AVAILABLE_VSI;
8454         }
8455
8456         qpnum_per_tc = used_queues / total_tc;
8457         /* Number of queues per enabled TC */
8458         if (qpnum_per_tc == 0) {
8459                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8460                 return I40E_ERR_INVALID_QP_ID;
8461         }
8462         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8463                                 I40E_MAX_Q_PER_TC);
8464         bsf = rte_bsf32(qpnum_per_tc);
8465
8466         /**
8467          * Configure TC and queue mapping parameters, for enabled TC,
8468          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8469          * default queue will serve it.
8470          */
8471         qp_idx = 0;
8472         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8473                 if (vsi->enabled_tc & (1 << i)) {
8474                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8475                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8476                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8477                         qp_idx += qpnum_per_tc;
8478                 } else
8479                         info->tc_mapping[i] = 0;
8480         }
8481
8482         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8483         if (vsi->type == I40E_VSI_SRIOV) {
8484                 info->mapping_flags |=
8485                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8486                 for (i = 0; i < vsi->nb_qps; i++)
8487                         info->queue_mapping[i] =
8488                                 rte_cpu_to_le_16(vsi->base_queue + i);
8489         } else {
8490                 info->mapping_flags |=
8491                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8492                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8493         }
8494         info->valid_sections |=
8495                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8496
8497         return I40E_SUCCESS;
8498 }
8499
8500 /*
8501  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8502  * @veb: VEB to be configured
8503  * @tc_map: enabled TC bitmap
8504  *
8505  * Returns 0 on success, negative value on failure
8506  */
8507 static enum i40e_status_code
8508 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8509 {
8510         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8511         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8512         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8513         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8514         enum i40e_status_code ret = I40E_SUCCESS;
8515         int i;
8516         uint32_t bw_max;
8517
8518         /* Check if enabled_tc is same as existing or new TCs */
8519         if (veb->enabled_tc == tc_map)
8520                 return ret;
8521
8522         /* configure tc bandwidth */
8523         memset(&veb_bw, 0, sizeof(veb_bw));
8524         veb_bw.tc_valid_bits = tc_map;
8525         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8526         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8527                 if (tc_map & BIT_ULL(i))
8528                         veb_bw.tc_bw_share_credits[i] = 1;
8529         }
8530         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8531                                                    &veb_bw, NULL);
8532         if (ret) {
8533                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8534                                   " per TC failed = %d",
8535                                   hw->aq.asq_last_status);
8536                 return ret;
8537         }
8538
8539         memset(&ets_query, 0, sizeof(ets_query));
8540         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8541                                                    &ets_query, NULL);
8542         if (ret != I40E_SUCCESS) {
8543                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8544                                  " configuration %u", hw->aq.asq_last_status);
8545                 return ret;
8546         }
8547         memset(&bw_query, 0, sizeof(bw_query));
8548         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8549                                                   &bw_query, NULL);
8550         if (ret != I40E_SUCCESS) {
8551                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8552                                  " configuration %u", hw->aq.asq_last_status);
8553                 return ret;
8554         }
8555
8556         /* store and print out BW info */
8557         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8558         veb->bw_info.bw_max = ets_query.tc_bw_max;
8559         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8560         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8561         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8562                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8563                      I40E_16_BIT_WIDTH);
8564         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8565                 veb->bw_info.bw_ets_share_credits[i] =
8566                                 bw_query.tc_bw_share_credits[i];
8567                 veb->bw_info.bw_ets_credits[i] =
8568                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8569                 /* 4 bits per TC, 4th bit is reserved */
8570                 veb->bw_info.bw_ets_max[i] =
8571                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8572                                   RTE_LEN2MASK(3, uint8_t));
8573                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8574                             veb->bw_info.bw_ets_share_credits[i]);
8575                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8576                             veb->bw_info.bw_ets_credits[i]);
8577                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8578                             veb->bw_info.bw_ets_max[i]);
8579         }
8580
8581         veb->enabled_tc = tc_map;
8582
8583         return ret;
8584 }
8585
8586
8587 /*
8588  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8589  * @vsi: VSI to be configured
8590  * @tc_map: enabled TC bitmap
8591  *
8592  * Returns 0 on success, negative value on failure
8593  */
8594 static enum i40e_status_code
8595 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8596 {
8597         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8598         struct i40e_vsi_context ctxt;
8599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8600         enum i40e_status_code ret = I40E_SUCCESS;
8601         int i;
8602
8603         /* Check if enabled_tc is same as existing or new TCs */
8604         if (vsi->enabled_tc == tc_map)
8605                 return ret;
8606
8607         /* configure tc bandwidth */
8608         memset(&bw_data, 0, sizeof(bw_data));
8609         bw_data.tc_valid_bits = tc_map;
8610         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8611         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8612                 if (tc_map & BIT_ULL(i))
8613                         bw_data.tc_bw_credits[i] = 1;
8614         }
8615         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8616         if (ret) {
8617                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8618                         " per TC failed = %d",
8619                         hw->aq.asq_last_status);
8620                 goto out;
8621         }
8622         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8623                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8624
8625         /* Update Queue Pairs Mapping for currently enabled UPs */
8626         ctxt.seid = vsi->seid;
8627         ctxt.pf_num = hw->pf_id;
8628         ctxt.vf_num = 0;
8629         ctxt.uplink_seid = vsi->uplink_seid;
8630         ctxt.info = vsi->info;
8631         i40e_get_cap(hw);
8632         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8633         if (ret)
8634                 goto out;
8635
8636         /* Update the VSI after updating the VSI queue-mapping information */
8637         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8638         if (ret) {
8639                 PMD_INIT_LOG(ERR, "Failed to configure "
8640                             "TC queue mapping = %d",
8641                             hw->aq.asq_last_status);
8642                 goto out;
8643         }
8644         /* update the local VSI info with updated queue map */
8645         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8646                                         sizeof(vsi->info.tc_mapping));
8647         (void)rte_memcpy(&vsi->info.queue_mapping,
8648                         &ctxt.info.queue_mapping,
8649                 sizeof(vsi->info.queue_mapping));
8650         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8651         vsi->info.valid_sections = 0;
8652
8653         /* query and update current VSI BW information */
8654         ret = i40e_vsi_get_bw_config(vsi);
8655         if (ret) {
8656                 PMD_INIT_LOG(ERR,
8657                          "Failed updating vsi bw info, err %s aq_err %s",
8658                          i40e_stat_str(hw, ret),
8659                          i40e_aq_str(hw, hw->aq.asq_last_status));
8660                 goto out;
8661         }
8662
8663         vsi->enabled_tc = tc_map;
8664
8665 out:
8666         return ret;
8667 }
8668
8669 /*
8670  * i40e_dcb_hw_configure - program the dcb setting to hw
8671  * @pf: pf the configuration is taken on
8672  * @new_cfg: new configuration
8673  * @tc_map: enabled TC bitmap
8674  *
8675  * Returns 0 on success, negative value on failure
8676  */
8677 static enum i40e_status_code
8678 i40e_dcb_hw_configure(struct i40e_pf *pf,
8679                       struct i40e_dcbx_config *new_cfg,
8680                       uint8_t tc_map)
8681 {
8682         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8683         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8684         struct i40e_vsi *main_vsi = pf->main_vsi;
8685         struct i40e_vsi_list *vsi_list;
8686         enum i40e_status_code ret;
8687         int i;
8688         uint32_t val;
8689
8690         /* Use the FW API if FW > v4.4*/
8691         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8692               (hw->aq.fw_maj_ver >= 5))) {
8693                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8694                                   " to configure DCB");
8695                 return I40E_ERR_FIRMWARE_API_VERSION;
8696         }
8697
8698         /* Check if need reconfiguration */
8699         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8700                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8701                 return I40E_SUCCESS;
8702         }
8703
8704         /* Copy the new config to the current config */
8705         *old_cfg = *new_cfg;
8706         old_cfg->etsrec = old_cfg->etscfg;
8707         ret = i40e_set_dcb_config(hw);
8708         if (ret) {
8709                 PMD_INIT_LOG(ERR,
8710                          "Set DCB Config failed, err %s aq_err %s\n",
8711                          i40e_stat_str(hw, ret),
8712                          i40e_aq_str(hw, hw->aq.asq_last_status));
8713                 return ret;
8714         }
8715         /* set receive Arbiter to RR mode and ETS scheme by default */
8716         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8717                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8718                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8719                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8720                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8721                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8722                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8723                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8724                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8725                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8726                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8727                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8728                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8729         }
8730         /* get local mib to check whether it is configured correctly */
8731         /* IEEE mode */
8732         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8733         /* Get Local DCB Config */
8734         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8735                                      &hw->local_dcbx_config);
8736
8737         /* if Veb is created, need to update TC of it at first */
8738         if (main_vsi->veb) {
8739                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8740                 if (ret)
8741                         PMD_INIT_LOG(WARNING,
8742                                  "Failed configuring TC for VEB seid=%d\n",
8743                                  main_vsi->veb->seid);
8744         }
8745         /* Update each VSI */
8746         i40e_vsi_config_tc(main_vsi, tc_map);
8747         if (main_vsi->veb) {
8748                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8749                         /* Beside main VSI and VMDQ VSIs, only enable default
8750                          * TC for other VSIs
8751                          */
8752                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8753                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8754                                                          tc_map);
8755                         else
8756                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8757                                                          I40E_DEFAULT_TCMAP);
8758                         if (ret)
8759                                 PMD_INIT_LOG(WARNING,
8760                                          "Failed configuring TC for VSI seid=%d\n",
8761                                          vsi_list->vsi->seid);
8762                         /* continue */
8763                 }
8764         }
8765         return I40E_SUCCESS;
8766 }
8767
8768 /*
8769  * i40e_dcb_init_configure - initial dcb config
8770  * @dev: device being configured
8771  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8772  *
8773  * Returns 0 on success, negative value on failure
8774  */
8775 static int
8776 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8777 {
8778         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8780         int ret = 0;
8781
8782         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8783                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8784                 return -ENOTSUP;
8785         }
8786
8787         /* DCB initialization:
8788          * Update DCB configuration from the Firmware and configure
8789          * LLDP MIB change event.
8790          */
8791         if (sw_dcb == TRUE) {
8792                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8793                 if (ret != I40E_SUCCESS)
8794                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8795
8796                 ret = i40e_init_dcb(hw);
8797                 /* if sw_dcb, lldp agent is stopped, the return from
8798                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8799                  * adminq status.
8800                  */
8801                 if (ret != I40E_SUCCESS &&
8802                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8803                         memset(&hw->local_dcbx_config, 0,
8804                                 sizeof(struct i40e_dcbx_config));
8805                         /* set dcb default configuration */
8806                         hw->local_dcbx_config.etscfg.willing = 0;
8807                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8808                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8809                         hw->local_dcbx_config.etscfg.tsatable[0] =
8810                                                 I40E_IEEE_TSA_ETS;
8811                         hw->local_dcbx_config.etsrec =
8812                                 hw->local_dcbx_config.etscfg;
8813                         hw->local_dcbx_config.pfc.willing = 0;
8814                         hw->local_dcbx_config.pfc.pfccap =
8815                                                 I40E_MAX_TRAFFIC_CLASS;
8816                         /* FW needs one App to configure HW */
8817                         hw->local_dcbx_config.numapps = 1;
8818                         hw->local_dcbx_config.app[0].selector =
8819                                                 I40E_APP_SEL_ETHTYPE;
8820                         hw->local_dcbx_config.app[0].priority = 3;
8821                         hw->local_dcbx_config.app[0].protocolid =
8822                                                 I40E_APP_PROTOID_FCOE;
8823                         ret = i40e_set_dcb_config(hw);
8824                         if (ret) {
8825                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8826                                         " err = %d, aq_err = %d.", ret,
8827                                           hw->aq.asq_last_status);
8828                                 return -ENOSYS;
8829                         }
8830                 } else {
8831                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8832                                           " aq_err = %d.", ret,
8833                                           hw->aq.asq_last_status);
8834                         return -ENOTSUP;
8835                 }
8836         } else {
8837                 ret = i40e_aq_start_lldp(hw, NULL);
8838                 if (ret != I40E_SUCCESS)
8839                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8840
8841                 ret = i40e_init_dcb(hw);
8842                 if (!ret) {
8843                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8844                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8845                                                   " DCBX offload.");
8846                                 return -ENOTSUP;
8847                         }
8848                 } else {
8849                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8850                                           " aq_err = %d.", ret,
8851                                           hw->aq.asq_last_status);
8852                         return -ENOTSUP;
8853                 }
8854         }
8855         return 0;
8856 }
8857
8858 /*
8859  * i40e_dcb_setup - setup dcb related config
8860  * @dev: device being configured
8861  *
8862  * Returns 0 on success, negative value on failure
8863  */
8864 static int
8865 i40e_dcb_setup(struct rte_eth_dev *dev)
8866 {
8867         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8868         struct i40e_dcbx_config dcb_cfg;
8869         uint8_t tc_map = 0;
8870         int ret = 0;
8871
8872         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8873                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8874                 return -ENOTSUP;
8875         }
8876
8877         if (pf->vf_num != 0)
8878                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8879
8880         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8881         if (ret) {
8882                 PMD_INIT_LOG(ERR, "invalid dcb config");
8883                 return -EINVAL;
8884         }
8885         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8886         if (ret) {
8887                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8888                 return -ENOSYS;
8889         }
8890
8891         return 0;
8892 }
8893
8894 static int
8895 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8896                       struct rte_eth_dcb_info *dcb_info)
8897 {
8898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8899         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8900         struct i40e_vsi *vsi = pf->main_vsi;
8901         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8902         uint16_t bsf, tc_mapping;
8903         int i, j = 0;
8904
8905         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8906                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8907         else
8908                 dcb_info->nb_tcs = 1;
8909         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8910                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8911         for (i = 0; i < dcb_info->nb_tcs; i++)
8912                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8913
8914         /* get queue mapping if vmdq is disabled */
8915         if (!pf->nb_cfg_vmdq_vsi) {
8916                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8917                         if (!(vsi->enabled_tc & (1 << i)))
8918                                 continue;
8919                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8920                         dcb_info->tc_queue.tc_rxq[j][i].base =
8921                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8922                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8923                         dcb_info->tc_queue.tc_txq[j][i].base =
8924                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8925                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8926                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8927                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8928                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8929                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8930                 }
8931                 return 0;
8932         }
8933
8934         /* get queue mapping if vmdq is enabled */
8935         do {
8936                 vsi = pf->vmdq[j].vsi;
8937                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8938                         if (!(vsi->enabled_tc & (1 << i)))
8939                                 continue;
8940                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8941                         dcb_info->tc_queue.tc_rxq[j][i].base =
8942                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8943                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8944                         dcb_info->tc_queue.tc_txq[j][i].base =
8945                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8946                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8947                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8948                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8949                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8950                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8951                 }
8952                 j++;
8953         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8954         return 0;
8955 }
8956
8957 static int
8958 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8959 {
8960         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8962         uint16_t interval =
8963                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8964         uint16_t msix_intr;
8965
8966         msix_intr = intr_handle->intr_vec[queue_id];
8967         if (msix_intr == I40E_MISC_VEC_ID)
8968                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8969                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8970                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8971                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8972                                (interval <<
8973                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8974         else
8975                 I40E_WRITE_REG(hw,
8976                                I40E_PFINT_DYN_CTLN(msix_intr -
8977                                                    I40E_RX_VEC_START),
8978                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8979                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8980                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8981                                (interval <<
8982                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8983
8984         I40E_WRITE_FLUSH(hw);
8985         rte_intr_enable(&dev->pci_dev->intr_handle);
8986
8987         return 0;
8988 }
8989
8990 static int
8991 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8992 {
8993         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8994         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8995         uint16_t msix_intr;
8996
8997         msix_intr = intr_handle->intr_vec[queue_id];
8998         if (msix_intr == I40E_MISC_VEC_ID)
8999                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9000         else
9001                 I40E_WRITE_REG(hw,
9002                                I40E_PFINT_DYN_CTLN(msix_intr -
9003                                                    I40E_RX_VEC_START),
9004                                0);
9005         I40E_WRITE_FLUSH(hw);
9006
9007         return 0;
9008 }
9009
9010 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9011 {
9012         /* Highest base addr + 32-bit word */
9013         return I40E_GLGEN_STAT_CLEAR + 4;
9014 }
9015
9016 static int i40e_get_regs(struct rte_eth_dev *dev,
9017                          struct rte_dev_reg_info *regs)
9018 {
9019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9020         uint32_t *ptr_data = regs->data;
9021         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9022         const struct i40e_reg_info *reg_info;
9023
9024         /* The first few registers have to be read using AQ operations */
9025         reg_idx = 0;
9026         while (i40e_regs_adminq[reg_idx].name) {
9027                 reg_info = &i40e_regs_adminq[reg_idx++];
9028                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9029                         for (arr_idx2 = 0;
9030                                         arr_idx2 <= reg_info->count2;
9031                                         arr_idx2++) {
9032                                 reg_offset = arr_idx * reg_info->stride1 +
9033                                         arr_idx2 * reg_info->stride2;
9034                                 ptr_data[reg_offset >> 2] =
9035                                         i40e_read_rx_ctl(hw, reg_offset);
9036                         }
9037         }
9038
9039         /* The remaining registers can be read using primitives */
9040         reg_idx = 0;
9041         while (i40e_regs_others[reg_idx].name) {
9042                 reg_info = &i40e_regs_others[reg_idx++];
9043                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9044                         for (arr_idx2 = 0;
9045                                         arr_idx2 <= reg_info->count2;
9046                                         arr_idx2++) {
9047                                 reg_offset = arr_idx * reg_info->stride1 +
9048                                         arr_idx2 * reg_info->stride2;
9049                                 ptr_data[reg_offset >> 2] =
9050                                         I40E_READ_REG(hw, reg_offset);
9051                         }
9052         }
9053
9054         return 0;
9055 }
9056
9057 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9058 {
9059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9060
9061         /* Convert word count to byte count */
9062         return hw->nvm.sr_size << 1;
9063 }
9064
9065 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9066                            struct rte_dev_eeprom_info *eeprom)
9067 {
9068         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9069         uint16_t *data = eeprom->data;
9070         uint16_t offset, length, cnt_words;
9071         int ret_code;
9072
9073         offset = eeprom->offset >> 1;
9074         length = eeprom->length >> 1;
9075         cnt_words = length;
9076
9077         if (offset > hw->nvm.sr_size ||
9078                 offset + length > hw->nvm.sr_size) {
9079                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9080                 return -EINVAL;
9081         }
9082
9083         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9084
9085         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9086         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9087                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9088                 return -EIO;
9089         }
9090
9091         return 0;
9092 }
9093
9094 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9095                                       struct ether_addr *mac_addr)
9096 {
9097         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9098
9099         if (!is_valid_assigned_ether_addr(mac_addr)) {
9100                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9101                 return;
9102         }
9103
9104         /* Flags: 0x3 updates port address */
9105         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9106 }