drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(
 377                 __rte_unused struct rte_intr_handle *handle, void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 426                         struct rte_eth_mirror_conf *mirror_conf,
 427                         uint8_t sw_id, uint8_t on);
 428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 429
 430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 433                                            struct timespec *timestamp,
 434                                            uint32_t flags);
 435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp);
 437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 438
 439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 440
 441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 442                                    struct timespec *timestamp);
 443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 444                                     const struct timespec *timestamp);
 445
 446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 447                                          uint16_t queue_id);
 448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 449                                           uint16_t queue_id);
 450
 451 static int i40e_get_regs(struct rte_eth_dev *dev,
 452                          struct rte_dev_reg_info *regs);
 453
 454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 455
 456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 457                            struct rte_dev_eeprom_info *eeprom);
 458
 459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 460                                       struct ether_addr *mac_addr);
 461
 462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 463
 464 static const struct rte_pci_id pci_id_i40e_map[] = {
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct eth_dev_ops i40e_eth_dev_ops = {
 489         .dev_configure                = i40e_dev_configure,
 490         .dev_start                    = i40e_dev_start,
 491         .dev_stop                     = i40e_dev_stop,
 492         .dev_close                    = i40e_dev_close,
 493         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 494         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 495         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 496         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 497         .dev_set_link_up              = i40e_dev_set_link_up,
 498         .dev_set_link_down            = i40e_dev_set_link_down,
 499         .link_update                  = i40e_dev_link_update,
 500         .stats_get                    = i40e_dev_stats_get,
 501         .xstats_get                   = i40e_dev_xstats_get,
 502         .xstats_get_names             = i40e_dev_xstats_get_names,
 503         .stats_reset                  = i40e_dev_stats_reset,
 504         .xstats_reset                 = i40e_dev_stats_reset,
 505         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 506         .dev_infos_get                = i40e_dev_info_get,
 507         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 508         .vlan_filter_set              = i40e_vlan_filter_set,
 509         .vlan_tpid_set                = i40e_vlan_tpid_set,
 510         .vlan_offload_set             = i40e_vlan_offload_set,
 511         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 512         .vlan_pvid_set                = i40e_vlan_pvid_set,
 513         .rx_queue_start               = i40e_dev_rx_queue_start,
 514         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 515         .tx_queue_start               = i40e_dev_tx_queue_start,
 516         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 517         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 518         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 519         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 520         .rx_queue_release             = i40e_dev_rx_queue_release,
 521         .rx_queue_count               = i40e_dev_rx_queue_count,
 522         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 523         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 524         .tx_queue_release             = i40e_dev_tx_queue_release,
 525         .dev_led_on                   = i40e_dev_led_on,
 526         .dev_led_off                  = i40e_dev_led_off,
 527         .flow_ctrl_get                = i40e_flow_ctrl_get,
 528         .flow_ctrl_set                = i40e_flow_ctrl_set,
 529         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 530         .mac_addr_add                 = i40e_macaddr_add,
 531         .mac_addr_remove              = i40e_macaddr_remove,
 532         .reta_update                  = i40e_dev_rss_reta_update,
 533         .reta_query                   = i40e_dev_rss_reta_query,
 534         .rss_hash_update              = i40e_dev_rss_hash_update,
 535         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 536         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 537         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 538         .filter_ctrl                  = i40e_dev_filter_ctrl,
 539         .rxq_info_get                 = i40e_rxq_info_get,
 540         .txq_info_get                 = i40e_txq_info_get,
 541         .mirror_rule_set              = i40e_mirror_rule_set,
 542         .mirror_rule_reset            = i40e_mirror_rule_reset,
 543         .timesync_enable              = i40e_timesync_enable,
 544         .timesync_disable             = i40e_timesync_disable,
 545         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 547         .get_dcb_info                 = i40e_dev_get_dcb_info,
 548         .timesync_adjust_time         = i40e_timesync_adjust_time,
 549         .timesync_read_time           = i40e_timesync_read_time,
 550         .timesync_write_time          = i40e_timesync_write_time,
 551         .get_reg                      = i40e_get_regs,
 552         .get_eeprom_length            = i40e_get_eeprom_length,
 553         .get_eeprom                   = i40e_get_eeprom,
 554         .mac_addr_set                 = i40e_set_default_mac_addr,
 555         .mtu_set                      = i40e_dev_mtu_set,
 556 };
 557
 558 /* store statistics names and its offset in stats structure */
 559 struct rte_i40e_xstats_name_off {
 560         char name[RTE_ETH_XSTATS_NAME_SIZE];
 561         unsigned offset;
 562 };
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 565         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 566         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 567         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 568         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 569         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 570                 rx_unknown_protocol)},
 571         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 572         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 573         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 574         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 575 };
 576
 577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 578                 sizeof(rte_i40e_stats_strings[0]))
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 581         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 582                 tx_dropped_link_down)},
 583         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 584         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 585                 illegal_bytes)},
 586         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 587         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 588                 mac_local_faults)},
 589         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 590                 mac_remote_faults)},
 591         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_length_errors)},
 593         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 594         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 595         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 596         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 597         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 598         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 599                 rx_size_127)},
 600         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 601                 rx_size_255)},
 602         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 603                 rx_size_511)},
 604         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 605                 rx_size_1023)},
 606         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 607                 rx_size_1522)},
 608         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 609                 rx_size_big)},
 610         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_undersize)},
 612         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 613                 rx_oversize)},
 614         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 615                 mac_short_packet_dropped)},
 616         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 617                 rx_fragments)},
 618         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 619         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 620         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 621                 tx_size_127)},
 622         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 623                 tx_size_255)},
 624         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 625                 tx_size_511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 627                 tx_size_1023)},
 628         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 629                 tx_size_1522)},
 630         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 631                 tx_size_big)},
 632         {"rx_flow_director_atr_match_packets",
 633                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 634         {"rx_flow_director_sb_match_packets",
 635                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 636         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 637                 tx_lpi_status)},
 638         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 639                 rx_lpi_status)},
 640         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 641                 tx_lpi_count)},
 642         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 643                 rx_lpi_count)},
 644 };
 645
 646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 647                 sizeof(rte_i40e_hw_port_strings[0]))
 648
 649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 650         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 651                 priority_xon_rx)},
 652         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 653                 priority_xoff_rx)},
 654 };
 655
 656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 657                 sizeof(rte_i40e_rxq_prio_strings[0]))
 658
 659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 660         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 661                 priority_xon_tx)},
 662         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 663                 priority_xoff_tx)},
 664         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 665                 priority_xon_2_xoff)},
 666 };
 667
 668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 669                 sizeof(rte_i40e_txq_prio_strings[0]))
 670
 671 static struct eth_driver rte_i40e_pmd = {
 672         .pci_drv = {
 673                 .id_table = pci_id_i40e_map,
 674                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 675                         RTE_PCI_DRV_DETACHABLE,
 676                 .probe = rte_eth_dev_pci_probe,
 677                 .remove = rte_eth_dev_pci_remove,
 678         },
 679         .eth_dev_init = eth_i40e_dev_init,
 680         .eth_dev_uninit = eth_i40e_dev_uninit,
 681         .dev_private_size = sizeof(struct i40e_adapter),
 682 };
 683
 684 static inline int
 685 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 686                                      struct rte_eth_link *link)
 687 {
 688         struct rte_eth_link *dst = link;
 689         struct rte_eth_link *src = &(dev->data->dev_link);
 690
 691         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 692                                         *(uint64_t *)src) == 0)
 693                 return -1;
 694
 695         return 0;
 696 }
 697
 698 static inline int
 699 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 700                                       struct rte_eth_link *link)
 701 {
 702         struct rte_eth_link *dst = &(dev->data->dev_link);
 703         struct rte_eth_link *src = link;
 704
 705         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 706                                         *(uint64_t *)src) == 0)
 707                 return -1;
 708
 709         return 0;
 710 }
 711
 712 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 713 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 714
 715 #ifndef I40E_GLQF_ORT
 716 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 717 #endif
 718 #ifndef I40E_GLQF_PIT
 719 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 720 #endif
 721
 722 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 723 {
 724         /*
 725          * Initialize registers for flexible payload, which should be set by NVM.
 726          * This should be removed from code once it is fixed in NVM.
 727          */
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 738         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 739         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 740
 741         /* Initialize registers for parsing packet type of QinQ */
 742         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 743         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 744 }
 745
 746 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 747
 748 /*
 749  * Add a ethertype filter to drop all flow control frames transmitted
 750  * from VSIs.
 751 */
 752 static void
 753 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 754 {
 755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 756         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 757                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 758                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 759         int ret;
 760
 761         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 762                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 763                                 pf->main_vsi_seid, 0,
 764                                 TRUE, NULL, NULL);
 765         if (ret)
 766                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 767                                   " frames from VSIs.");
 768 }
 769
 770 static int
 771 floating_veb_list_handler(__rte_unused const char *key,
 772                           const char *floating_veb_value,
 773                           void *opaque)
 774 {
 775         int idx = 0;
 776         unsigned int count = 0;
 777         char *end = NULL;
 778         int min, max;
 779         bool *vf_floating_veb = opaque;
 780
 781         while (isblank(*floating_veb_value))
 782                 floating_veb_value++;
 783
 784         /* Reset floating VEB configuration for VFs */
 785         for (idx = 0; idx < I40E_MAX_VF; idx++)
 786                 vf_floating_veb[idx] = false;
 787
 788         min = I40E_MAX_VF;
 789         do {
 790                 while (isblank(*floating_veb_value))
 791                         floating_veb_value++;
 792                 if (*floating_veb_value == '\0')
 793                         return -1;
 794                 errno = 0;
 795                 idx = strtoul(floating_veb_value, &end, 10);
 796                 if (errno || end == NULL)
 797                         return -1;
 798                 while (isblank(*end))
 799                         end++;
 800                 if (*end == '-') {
 801                         min = idx;
 802                 } else if ((*end == ';') || (*end == '\0')) {
 803                         max = idx;
 804                         if (min == I40E_MAX_VF)
 805                                 min = idx;
 806                         if (max >= I40E_MAX_VF)
 807                                 max = I40E_MAX_VF - 1;
 808                         for (idx = min; idx <= max; idx++) {
 809                                 vf_floating_veb[idx] = true;
 810                                 count++;
 811                         }
 812                         min = I40E_MAX_VF;
 813                 } else {
 814                         return -1;
 815                 }
 816                 floating_veb_value = end + 1;
 817         } while (*end != '\0');
 818
 819         if (count == 0)
 820                 return -1;
 821
 822         return 0;
 823 }
 824
 825 static void
 826 config_vf_floating_veb(struct rte_devargs *devargs,
 827                        uint16_t floating_veb,
 828                        bool *vf_floating_veb)
 829 {
 830         struct rte_kvargs *kvlist;
 831         int i;
 832         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 833
 834         if (!floating_veb)
 835                 return;
 836         /* All the VFs attach to the floating VEB by default
 837          * when the floating VEB is enabled.
 838          */
 839         for (i = 0; i < I40E_MAX_VF; i++)
 840                 vf_floating_veb[i] = true;
 841
 842         if (devargs == NULL)
 843                 return;
 844
 845         kvlist = rte_kvargs_parse(devargs->args, NULL);
 846         if (kvlist == NULL)
 847                 return;
 848
 849         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 850                 rte_kvargs_free(kvlist);
 851                 return;
 852         }
 853         /* When the floating_veb_list parameter exists, all the VFs
 854          * will attach to the legacy VEB firstly, then configure VFs
 855          * to the floating VEB according to the floating_veb_list.
 856          */
 857         if (rte_kvargs_process(kvlist, floating_veb_list,
 858                                floating_veb_list_handler,
 859                                vf_floating_veb) < 0) {
 860                 rte_kvargs_free(kvlist);
 861                 return;
 862         }
 863         rte_kvargs_free(kvlist);
 864 }
 865
 866 static int
 867 i40e_check_floating_handler(__rte_unused const char *key,
 868                             const char *value,
 869                             __rte_unused void *opaque)
 870 {
 871         if (strcmp(value, "1"))
 872                 return -1;
 873
 874         return 0;
 875 }
 876
 877 static int
 878 is_floating_veb_supported(struct rte_devargs *devargs)
 879 {
 880         struct rte_kvargs *kvlist;
 881         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 882
 883         if (devargs == NULL)
 884                 return 0;
 885
 886         kvlist = rte_kvargs_parse(devargs->args, NULL);
 887         if (kvlist == NULL)
 888                 return 0;
 889
 890         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 891                 rte_kvargs_free(kvlist);
 892                 return 0;
 893         }
 894         /* Floating VEB is enabled when there's key-value:
 895          * enable_floating_veb=1
 896          */
 897         if (rte_kvargs_process(kvlist, floating_veb_key,
 898                                i40e_check_floating_handler, NULL) < 0) {
 899                 rte_kvargs_free(kvlist);
 900                 return 0;
 901         }
 902         rte_kvargs_free(kvlist);
 903
 904         return 1;
 905 }
 906
 907 static void
 908 config_floating_veb(struct rte_eth_dev *dev)
 909 {
 910         struct rte_pci_device *pci_dev = dev->pci_dev;
 911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 913
 914         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 915
 916         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 917                 pf->floating_veb =
 918                         is_floating_veb_supported(pci_dev->device.devargs);
 919                 config_vf_floating_veb(pci_dev->device.devargs,
 920                                        pf->floating_veb,
 921                                        pf->floating_veb_list);
 922         } else {
 923                 pf->floating_veb = false;
 924         }
 925 }
 926
 927 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 928 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 929
 930 static int
 931 eth_i40e_dev_init(struct rte_eth_dev *dev)
 932 {
 933         struct rte_pci_device *pci_dev;
 934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         struct i40e_vsi *vsi;
 937         int ret;
 938         uint32_t len;
 939         uint8_t aq_fail = 0;
 940
 941         PMD_INIT_FUNC_TRACE();
 942
 943         dev->dev_ops = &i40e_eth_dev_ops;
 944         dev->rx_pkt_burst = i40e_recv_pkts;
 945         dev->tx_pkt_burst = i40e_xmit_pkts;
 946
 947         /* for secondary processes, we don't initialise any further as primary
 948          * has already done this work. Only check we don't need a different
 949          * RX function */
 950         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 951                 i40e_set_rx_function(dev);
 952                 i40e_set_tx_function(dev);
 953                 return 0;
 954         }
 955         pci_dev = dev->pci_dev;
 956
 957         rte_eth_copy_pci_info(dev, pci_dev);
 958
 959         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 960         pf->adapter->eth_dev = dev;
 961         pf->dev_data = dev->data;
 962
 963         hw->back = I40E_PF_TO_ADAPTER(pf);
 964         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 965         if (!hw->hw_addr) {
 966                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 967                              "as address is NULL");
 968                 return -ENODEV;
 969         }
 970
 971         hw->vendor_id = pci_dev->id.vendor_id;
 972         hw->device_id = pci_dev->id.device_id;
 973         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 974         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 975         hw->bus.device = pci_dev->addr.devid;
 976         hw->bus.func = pci_dev->addr.function;
 977         hw->adapter_stopped = 0;
 978
 979         /* Make sure all is clean before doing PF reset */
 980         i40e_clear_hw(hw);
 981
 982         /* Initialize the hardware */
 983         i40e_hw_init(dev);
 984
 985         /* Reset here to make sure all is clean for each PF */
 986         ret = i40e_pf_reset(hw);
 987         if (ret) {
 988                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 989                 return ret;
 990         }
 991
 992         /* Initialize the shared code (base driver) */
 993         ret = i40e_init_shared_code(hw);
 994         if (ret) {
 995                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 996                 return ret;
 997         }
 998
 999         /*
1000          * To work around the NVM issue, initialize registers
1001          * for flexible payload and packet type of QinQ by
1002          * software. It should be removed once issues are fixed
1003          * in NVM.
1004          */
1005         i40e_GLQF_reg_init(hw);
1006
1007         /* Initialize the input set for filters (hash and fd) to default value */
1008         i40e_filter_input_set_init(pf);
1009
1010         /* Initialize the parameters for adminq */
1011         i40e_init_adminq_parameter(hw);
1012         ret = i40e_init_adminq(hw);
1013         if (ret != I40E_SUCCESS) {
1014                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1015                 return -EIO;
1016         }
1017         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1018                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1019                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1020                      ((hw->nvm.version >> 12) & 0xf),
1021                      ((hw->nvm.version >> 4) & 0xff),
1022                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1023
1024         /* Need the special FW version to support floating VEB */
1025         config_floating_veb(dev);
1026         /* Clear PXE mode */
1027         i40e_clear_pxe_mode(hw);
1028         ret = i40e_dev_sync_phy_type(hw);
1029         if (ret) {
1030                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1031                 goto err_sync_phy_type;
1032         }
1033         /*
1034          * On X710, performance number is far from the expectation on recent
1035          * firmware versions. The fix for this issue may not be integrated in
1036          * the following firmware version. So the workaround in software driver
1037          * is needed. It needs to modify the initial values of 3 internal only
1038          * registers. Note that the workaround can be removed when it is fixed
1039          * in firmware in the future.
1040          */
1041         i40e_configure_registers(hw);
1042
1043         /* Get hw capabilities */
1044         ret = i40e_get_cap(hw);
1045         if (ret != I40E_SUCCESS) {
1046                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1047                 goto err_get_capabilities;
1048         }
1049
1050         /* Initialize parameters for PF */
1051         ret = i40e_pf_parameter_init(dev);
1052         if (ret != 0) {
1053                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1054                 goto err_parameter_init;
1055         }
1056
1057         /* Initialize the queue management */
1058         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1059         if (ret < 0) {
1060                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1061                 goto err_qp_pool_init;
1062         }
1063         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1064                                 hw->func_caps.num_msix_vectors - 1);
1065         if (ret < 0) {
1066                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1067                 goto err_msix_pool_init;
1068         }
1069
1070         /* Initialize lan hmc */
1071         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1072                                 hw->func_caps.num_rx_qp, 0, 0);
1073         if (ret != I40E_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1075                 goto err_init_lan_hmc;
1076         }
1077
1078         /* Configure lan hmc */
1079         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1080         if (ret != I40E_SUCCESS) {
1081                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1082                 goto err_configure_lan_hmc;
1083         }
1084
1085         /* Get and check the mac address */
1086         i40e_get_mac_addr(hw, hw->mac.addr);
1087         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "mac address is not valid");
1089                 ret = -EIO;
1090                 goto err_get_mac_addr;
1091         }
1092         /* Copy the permanent MAC address */
1093         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1094                         (struct ether_addr *) hw->mac.perm_addr);
1095
1096         /* Disable flow control */
1097         hw->fc.requested_mode = I40E_FC_NONE;
1098         i40e_set_fc(hw, &aq_fail, TRUE);
1099
1100         /* Set the global registers with default ether type value */
1101         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1102         if (ret != I40E_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1104                              "VLAN ether type");
1105                 goto err_setup_pf_switch;
1106         }
1107
1108         /* PF setup, which includes VSI setup */
1109         ret = i40e_pf_setup(pf);
1110         if (ret) {
1111                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1112                 goto err_setup_pf_switch;
1113         }
1114
1115         /* reset all stats of the device, including pf and main vsi */
1116         i40e_dev_stats_reset(dev);
1117
1118         vsi = pf->main_vsi;
1119
1120         /* Disable double vlan by default */
1121         i40e_vsi_config_double_vlan(vsi, FALSE);
1122
1123         /* Disable S-TAG identification when floating_veb is disabled */
1124         if (!pf->floating_veb) {
1125                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1126                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1127                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1128                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1129                 }
1130         }
1131
1132         if (!vsi->max_macaddrs)
1133                 len = ETHER_ADDR_LEN;
1134         else
1135                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1136
1137         /* Should be after VSI initialized */
1138         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1139         if (!dev->data->mac_addrs) {
1140                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1141                                         "for storing mac address");
1142                 goto err_mac_alloc;
1143         }
1144         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1145                                         &dev->data->mac_addrs[0]);
1146
1147         /* initialize pf host driver to setup SRIOV resource if applicable */
1148         i40e_pf_host_init(dev);
1149
1150         /* register callback func to eal lib */
1151         rte_intr_callback_register(&(pci_dev->intr_handle),
1152                 i40e_dev_interrupt_handler, (void *)dev);
1153
1154         /* configure and enable device interrupt */
1155         i40e_pf_config_irq0(hw, TRUE);
1156         i40e_pf_enable_irq0(hw);
1157
1158         /* enable uio intr after callback register */
1159         rte_intr_enable(&(pci_dev->intr_handle));
1160         /*
1161          * Add an ethertype filter to drop all flow control frames transmitted
1162          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1163          * frames to wire.
1164          */
1165         i40e_add_tx_flow_control_drop_filter(pf);
1166
1167         /* Set the max frame size to 0x2600 by default,
1168          * in case other drivers changed the default value.
1169          */
1170         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1171
1172         /* initialize mirror rule list */
1173         TAILQ_INIT(&pf->mirror_list);
1174
1175         /* Init dcb to sw mode by default */
1176         ret = i40e_dcb_init_configure(dev, TRUE);
1177         if (ret != I40E_SUCCESS) {
1178                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1179                 pf->flags &= ~I40E_FLAG_DCB;
1180         }
1181
1182         return 0;
1183
1184 err_mac_alloc:
1185         i40e_vsi_release(pf->main_vsi);
1186 err_setup_pf_switch:
1187 err_get_mac_addr:
1188 err_configure_lan_hmc:
1189         (void)i40e_shutdown_lan_hmc(hw);
1190 err_init_lan_hmc:
1191         i40e_res_pool_destroy(&pf->msix_pool);
1192 err_msix_pool_init:
1193         i40e_res_pool_destroy(&pf->qp_pool);
1194 err_qp_pool_init:
1195 err_parameter_init:
1196 err_get_capabilities:
1197 err_sync_phy_type:
1198         (void)i40e_shutdown_adminq(hw);
1199
1200         return ret;
1201 }
1202
1203 static int
1204 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1205 {
1206         struct rte_pci_device *pci_dev;
1207         struct i40e_hw *hw;
1208         struct i40e_filter_control_settings settings;
1209         int ret;
1210         uint8_t aq_fail = 0;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1215                 return 0;
1216
1217         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218         pci_dev = dev->pci_dev;
1219
1220         if (hw->adapter_stopped == 0)
1221                 i40e_dev_close(dev);
1222
1223         dev->dev_ops = NULL;
1224         dev->rx_pkt_burst = NULL;
1225         dev->tx_pkt_burst = NULL;
1226
1227         /* Clear PXE mode */
1228         i40e_clear_pxe_mode(hw);
1229
1230         /* Unconfigure filter control */
1231         memset(&settings, 0, sizeof(settings));
1232         ret = i40e_set_filter_control(hw, &settings);
1233         if (ret)
1234                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1235                                         ret);
1236
1237         /* Disable flow control */
1238         hw->fc.requested_mode = I40E_FC_NONE;
1239         i40e_set_fc(hw, &aq_fail, TRUE);
1240
1241         /* uninitialize pf host driver */
1242         i40e_pf_host_uninit(dev);
1243
1244         rte_free(dev->data->mac_addrs);
1245         dev->data->mac_addrs = NULL;
1246
1247         /* disable uio intr before callback unregister */
1248         rte_intr_disable(&(pci_dev->intr_handle));
1249
1250         /* register callback func to eal lib */
1251         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1252                 i40e_dev_interrupt_handler, (void *)dev);
1253
1254         return 0;
1255 }
1256
1257 static int
1258 i40e_dev_configure(struct rte_eth_dev *dev)
1259 {
1260         struct i40e_adapter *ad =
1261                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1262         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1263         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1264         int i, ret;
1265
1266         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1267          * bulk allocation or vector Rx preconditions we will reset it.
1268          */
1269         ad->rx_bulk_alloc_allowed = true;
1270         ad->rx_vec_allowed = true;
1271         ad->tx_simple_allowed = true;
1272         ad->tx_vec_allowed = true;
1273
1274         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1275                 ret = i40e_fdir_setup(pf);
1276                 if (ret != I40E_SUCCESS) {
1277                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1278                         return -ENOTSUP;
1279                 }
1280                 ret = i40e_fdir_configure(dev);
1281                 if (ret < 0) {
1282                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1283                         goto err;
1284                 }
1285         } else
1286                 i40e_fdir_teardown(pf);
1287
1288         ret = i40e_dev_init_vlan(dev);
1289         if (ret < 0)
1290                 goto err;
1291
1292         /* VMDQ setup.
1293          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1294          *  RSS setting have different requirements.
1295          *  General PMD driver call sequence are NIC init, configure,
1296          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1297          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1298          *  applicable. So, VMDQ setting has to be done before
1299          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1300          *  For RSS setting, it will try to calculate actual configured RX queue
1301          *  number, which will be available after rx_queue_setup(). dev_start()
1302          *  function is good to place RSS setup.
1303          */
1304         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1305                 ret = i40e_vmdq_setup(dev);
1306                 if (ret)
1307                         goto err;
1308         }
1309
1310         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1311                 ret = i40e_dcb_setup(dev);
1312                 if (ret) {
1313                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1314                         goto err_dcb;
1315                 }
1316         }
1317
1318         return 0;
1319
1320 err_dcb:
1321         /* need to release vmdq resource if exists */
1322         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1323                 i40e_vsi_release(pf->vmdq[i].vsi);
1324                 pf->vmdq[i].vsi = NULL;
1325         }
1326         rte_free(pf->vmdq);
1327         pf->vmdq = NULL;
1328 err:
1329         /* need to release fdir resource if exists */
1330         i40e_fdir_teardown(pf);
1331         return ret;
1332 }
1333
1334 void
1335 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1336 {
1337         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1338         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1339         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1340         uint16_t msix_vect = vsi->msix_intr;
1341         uint16_t i;
1342
1343         for (i = 0; i < vsi->nb_qps; i++) {
1344                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1345                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1346                 rte_wmb();
1347         }
1348
1349         if (vsi->type != I40E_VSI_SRIOV) {
1350                 if (!rte_intr_allow_others(intr_handle)) {
1351                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1352                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1353                         I40E_WRITE_REG(hw,
1354                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1355                                        0);
1356                 } else {
1357                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1358                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1359                         I40E_WRITE_REG(hw,
1360                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1361                                                        msix_vect - 1), 0);
1362                 }
1363         } else {
1364                 uint32_t reg;
1365                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1366                         vsi->user_param + (msix_vect - 1);
1367
1368                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1369                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1370         }
1371         I40E_WRITE_FLUSH(hw);
1372 }
1373
1374 static void
1375 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1376                        int base_queue, int nb_queue)
1377 {
1378         int i;
1379         uint32_t val;
1380         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1381
1382         /* Bind all RX queues to allocated MSIX interrupt */
1383         for (i = 0; i < nb_queue; i++) {
1384                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1385                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1386                         ((base_queue + i + 1) <<
1387                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1388                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1389                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1390
1391                 if (i == nb_queue - 1)
1392                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1393                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1394         }
1395
1396         /* Write first RX queue to Link list register as the head element */
1397         if (vsi->type != I40E_VSI_SRIOV) {
1398                 uint16_t interval =
1399                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1400
1401                 if (msix_vect == I40E_MISC_VEC_ID) {
1402                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1403                                        (base_queue <<
1404                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1405                                        (0x0 <<
1406                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1407                         I40E_WRITE_REG(hw,
1408                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1409                                        interval);
1410                 } else {
1411                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1412                                        (base_queue <<
1413                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1414                                        (0x0 <<
1415                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1416                         I40E_WRITE_REG(hw,
1417                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1418                                                        msix_vect - 1),
1419                                        interval);
1420                 }
1421         } else {
1422                 uint32_t reg;
1423
1424                 if (msix_vect == I40E_MISC_VEC_ID) {
1425                         I40E_WRITE_REG(hw,
1426                                        I40E_VPINT_LNKLST0(vsi->user_param),
1427                                        (base_queue <<
1428                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1429                                        (0x0 <<
1430                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1431                 } else {
1432                         /* num_msix_vectors_vf needs to minus irq0 */
1433                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1434                                 vsi->user_param + (msix_vect - 1);
1435
1436                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1437                                        (base_queue <<
1438                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1439                                        (0x0 <<
1440                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1441                 }
1442         }
1443
1444         I40E_WRITE_FLUSH(hw);
1445 }
1446
1447 void
1448 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1449 {
1450         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1451         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1452         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1453         uint16_t msix_vect = vsi->msix_intr;
1454         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1455         uint16_t queue_idx = 0;
1456         int record = 0;
1457         uint32_t val;
1458         int i;
1459
1460         for (i = 0; i < vsi->nb_qps; i++) {
1461                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1462                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1463         }
1464
1465         /* INTENA flag is not auto-cleared for interrupt */
1466         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1467         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1468                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1469                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1470         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1471
1472         /* VF bind interrupt */
1473         if (vsi->type == I40E_VSI_SRIOV) {
1474                 __vsi_queues_bind_intr(vsi, msix_vect,
1475                                        vsi->base_queue, vsi->nb_qps);
1476                 return;
1477         }
1478
1479         /* PF & VMDq bind interrupt */
1480         if (rte_intr_dp_is_en(intr_handle)) {
1481                 if (vsi->type == I40E_VSI_MAIN) {
1482                         queue_idx = 0;
1483                         record = 1;
1484                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1485                         struct i40e_vsi *main_vsi =
1486                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1487                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1488                         record = 1;
1489                 }
1490         }
1491
1492         for (i = 0; i < vsi->nb_used_qps; i++) {
1493                 if (nb_msix <= 1) {
1494                         if (!rte_intr_allow_others(intr_handle))
1495                                 /* allow to share MISC_VEC_ID */
1496                                 msix_vect = I40E_MISC_VEC_ID;
1497
1498                         /* no enough msix_vect, map all to one */
1499                         __vsi_queues_bind_intr(vsi, msix_vect,
1500                                                vsi->base_queue + i,
1501                                                vsi->nb_used_qps - i);
1502                         for (; !!record && i < vsi->nb_used_qps; i++)
1503                                 intr_handle->intr_vec[queue_idx + i] =
1504                                         msix_vect;
1505                         break;
1506                 }
1507                 /* 1:1 queue/msix_vect mapping */
1508                 __vsi_queues_bind_intr(vsi, msix_vect,
1509                                        vsi->base_queue + i, 1);
1510                 if (!!record)
1511                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1512
1513                 msix_vect++;
1514                 nb_msix--;
1515         }
1516 }
1517
1518 static void
1519 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1520 {
1521         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1522         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1524         uint16_t interval = i40e_calc_itr_interval(\
1525                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1526         uint16_t msix_intr, i;
1527
1528         if (rte_intr_allow_others(intr_handle))
1529                 for (i = 0; i < vsi->nb_msix; i++) {
1530                         msix_intr = vsi->msix_intr + i;
1531                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1532                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1533                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1534                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1535                                 (interval <<
1536                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1537                 }
1538         else
1539                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1540                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1541                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1542                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1543                                (interval <<
1544                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1545
1546         I40E_WRITE_FLUSH(hw);
1547 }
1548
1549 static void
1550 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1551 {
1552         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1553         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1554         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1555         uint16_t msix_intr, i;
1556
1557         if (rte_intr_allow_others(intr_handle))
1558                 for (i = 0; i < vsi->nb_msix; i++) {
1559                         msix_intr = vsi->msix_intr + i;
1560                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1561                                        0);
1562                 }
1563         else
1564                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1565
1566         I40E_WRITE_FLUSH(hw);
1567 }
1568
1569 static inline uint8_t
1570 i40e_parse_link_speeds(uint16_t link_speeds)
1571 {
1572         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1573
1574         if (link_speeds & ETH_LINK_SPEED_40G)
1575                 link_speed |= I40E_LINK_SPEED_40GB;
1576         if (link_speeds & ETH_LINK_SPEED_25G)
1577                 link_speed |= I40E_LINK_SPEED_25GB;
1578         if (link_speeds & ETH_LINK_SPEED_20G)
1579                 link_speed |= I40E_LINK_SPEED_20GB;
1580         if (link_speeds & ETH_LINK_SPEED_10G)
1581                 link_speed |= I40E_LINK_SPEED_10GB;
1582         if (link_speeds & ETH_LINK_SPEED_1G)
1583                 link_speed |= I40E_LINK_SPEED_1GB;
1584         if (link_speeds & ETH_LINK_SPEED_100M)
1585                 link_speed |= I40E_LINK_SPEED_100MB;
1586
1587         return link_speed;
1588 }
1589
1590 static int
1591 i40e_phy_conf_link(struct i40e_hw *hw,
1592                    uint8_t abilities,
1593                    uint8_t force_speed)
1594 {
1595         enum i40e_status_code status;
1596         struct i40e_aq_get_phy_abilities_resp phy_ab;
1597         struct i40e_aq_set_phy_config phy_conf;
1598         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1599                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1600                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1601                         I40E_AQ_PHY_FLAG_LOW_POWER;
1602         const uint8_t advt = I40E_LINK_SPEED_40GB |
1603                         I40E_LINK_SPEED_25GB |
1604                         I40E_LINK_SPEED_10GB |
1605                         I40E_LINK_SPEED_1GB |
1606                         I40E_LINK_SPEED_100MB;
1607         int ret = -ENOTSUP;
1608
1609
1610         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1611                                               NULL);
1612         if (status)
1613                 return ret;
1614
1615         memset(&phy_conf, 0, sizeof(phy_conf));
1616
1617         /* bits 0-2 use the values from get_phy_abilities_resp */
1618         abilities &= ~mask;
1619         abilities |= phy_ab.abilities & mask;
1620
1621         /* update ablities and speed */
1622         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1623                 phy_conf.link_speed = advt;
1624         else
1625                 phy_conf.link_speed = force_speed;
1626
1627         phy_conf.abilities = abilities;
1628
1629         /* use get_phy_abilities_resp value for the rest */
1630         phy_conf.phy_type = phy_ab.phy_type;
1631         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1632         phy_conf.fec_config = phy_ab.mod_type_ext;
1633         phy_conf.eee_capability = phy_ab.eee_capability;
1634         phy_conf.eeer = phy_ab.eeer_val;
1635         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1636
1637         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1638                     phy_ab.abilities, phy_ab.link_speed);
1639         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1640                     phy_conf.abilities, phy_conf.link_speed);
1641
1642         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1643         if (status)
1644                 return ret;
1645
1646         return I40E_SUCCESS;
1647 }
1648
1649 static int
1650 i40e_apply_link_speed(struct rte_eth_dev *dev)
1651 {
1652         uint8_t speed;
1653         uint8_t abilities = 0;
1654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         struct rte_eth_conf *conf = &dev->data->dev_conf;
1656
1657         speed = i40e_parse_link_speeds(conf->link_speeds);
1658         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1659         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1660                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1661         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1662
1663         /* Skip changing speed on 40G interfaces, FW does not support */
1664         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1665                 speed =  I40E_LINK_SPEED_UNKNOWN;
1666                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1667         }
1668
1669         return i40e_phy_conf_link(hw, abilities, speed);
1670 }
1671
1672 static int
1673 i40e_dev_start(struct rte_eth_dev *dev)
1674 {
1675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         struct i40e_vsi *main_vsi = pf->main_vsi;
1678         int ret, i;
1679         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1680         uint32_t intr_vector = 0;
1681
1682         hw->adapter_stopped = 0;
1683
1684         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1685                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1686                              dev->data->port_id);
1687                 return -EINVAL;
1688         }
1689
1690         rte_intr_disable(intr_handle);
1691
1692         if ((rte_intr_cap_multiple(intr_handle) ||
1693              !RTE_ETH_DEV_SRIOV(dev).active) &&
1694             dev->data->dev_conf.intr_conf.rxq != 0) {
1695                 intr_vector = dev->data->nb_rx_queues;
1696                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1697                         return -1;
1698         }
1699
1700         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1701                 intr_handle->intr_vec =
1702                         rte_zmalloc("intr_vec",
1703                                     dev->data->nb_rx_queues * sizeof(int),
1704                                     0);
1705                 if (!intr_handle->intr_vec) {
1706                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1707                                      " intr_vec\n", dev->data->nb_rx_queues);
1708                         return -ENOMEM;
1709                 }
1710         }
1711
1712         /* Initialize VSI */
1713         ret = i40e_dev_rxtx_init(pf);
1714         if (ret != I40E_SUCCESS) {
1715                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1716                 goto err_up;
1717         }
1718
1719         /* Map queues with MSIX interrupt */
1720         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1721                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1722         i40e_vsi_queues_bind_intr(main_vsi);
1723         i40e_vsi_enable_queues_intr(main_vsi);
1724
1725         /* Map VMDQ VSI queues with MSIX interrupt */
1726         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1727                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1728                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1729                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1730         }
1731
1732         /* enable FDIR MSIX interrupt */
1733         if (pf->fdir.fdir_vsi) {
1734                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1735                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1736         }
1737
1738         /* Enable all queues which have been configured */
1739         ret = i40e_dev_switch_queues(pf, TRUE);
1740         if (ret != I40E_SUCCESS) {
1741                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1742                 goto err_up;
1743         }
1744
1745         /* Enable receiving broadcast packets */
1746         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1747         if (ret != I40E_SUCCESS)
1748                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1749
1750         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1751                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1752                                                 true, NULL);
1753                 if (ret != I40E_SUCCESS)
1754                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1755         }
1756
1757         /* Apply link configure */
1758         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1759                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1760                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1761                                 ETH_LINK_SPEED_40G)) {
1762                 PMD_DRV_LOG(ERR, "Invalid link setting");
1763                 goto err_up;
1764         }
1765         ret = i40e_apply_link_speed(dev);
1766         if (I40E_SUCCESS != ret) {
1767                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1768                 goto err_up;
1769         }
1770
1771         if (!rte_intr_allow_others(intr_handle)) {
1772                 rte_intr_callback_unregister(intr_handle,
1773                                              i40e_dev_interrupt_handler,
1774                                              (void *)dev);
1775                 /* configure and enable device interrupt */
1776                 i40e_pf_config_irq0(hw, FALSE);
1777                 i40e_pf_enable_irq0(hw);
1778
1779                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1780                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1781                                      " no intr multiplex\n");
1782         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1783                 ret = i40e_aq_set_phy_int_mask(hw,
1784                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1785                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1786                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1787                 if (ret != I40E_SUCCESS)
1788                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1789
1790                 /* Call get_link_info aq commond to enable LSE */
1791                 i40e_dev_link_update(dev, 0);
1792         }
1793
1794         /* enable uio intr after callback register */
1795         rte_intr_enable(intr_handle);
1796
1797         return I40E_SUCCESS;
1798
1799 err_up:
1800         i40e_dev_switch_queues(pf, FALSE);
1801         i40e_dev_clear_queues(dev);
1802
1803         return ret;
1804 }
1805
1806 static void
1807 i40e_dev_stop(struct rte_eth_dev *dev)
1808 {
1809         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1810         struct i40e_vsi *main_vsi = pf->main_vsi;
1811         struct i40e_mirror_rule *p_mirror;
1812         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1813         int i;
1814
1815         /* Disable all queues */
1816         i40e_dev_switch_queues(pf, FALSE);
1817
1818         /* un-map queues with interrupt registers */
1819         i40e_vsi_disable_queues_intr(main_vsi);
1820         i40e_vsi_queues_unbind_intr(main_vsi);
1821
1822         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1823                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1824                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1825         }
1826
1827         if (pf->fdir.fdir_vsi) {
1828                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1829                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1830         }
1831         /* Clear all queues and release memory */
1832         i40e_dev_clear_queues(dev);
1833
1834         /* Set link down */
1835         i40e_dev_set_link_down(dev);
1836
1837         /* Remove all mirror rules */
1838         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1839                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1840                 rte_free(p_mirror);
1841         }
1842         pf->nb_mirror_rule = 0;
1843
1844         if (!rte_intr_allow_others(intr_handle))
1845                 /* resume to the default handler */
1846                 rte_intr_callback_register(intr_handle,
1847                                            i40e_dev_interrupt_handler,
1848                                            (void *)dev);
1849
1850         /* Clean datapath event and queue/vec mapping */
1851         rte_intr_efd_disable(intr_handle);
1852         if (intr_handle->intr_vec) {
1853                 rte_free(intr_handle->intr_vec);
1854                 intr_handle->intr_vec = NULL;
1855         }
1856 }
1857
1858 static void
1859 i40e_dev_close(struct rte_eth_dev *dev)
1860 {
1861         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1862         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863         uint32_t reg;
1864         int i;
1865
1866         PMD_INIT_FUNC_TRACE();
1867
1868         i40e_dev_stop(dev);
1869         hw->adapter_stopped = 1;
1870         i40e_dev_free_queues(dev);
1871
1872         /* Disable interrupt */
1873         i40e_pf_disable_irq0(hw);
1874         rte_intr_disable(&(dev->pci_dev->intr_handle));
1875
1876         /* shutdown and destroy the HMC */
1877         i40e_shutdown_lan_hmc(hw);
1878
1879         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1880                 i40e_vsi_release(pf->vmdq[i].vsi);
1881                 pf->vmdq[i].vsi = NULL;
1882         }
1883         rte_free(pf->vmdq);
1884         pf->vmdq = NULL;
1885
1886         /* release all the existing VSIs and VEBs */
1887         i40e_fdir_teardown(pf);
1888         i40e_vsi_release(pf->main_vsi);
1889
1890         /* shutdown the adminq */
1891         i40e_aq_queue_shutdown(hw, true);
1892         i40e_shutdown_adminq(hw);
1893
1894         i40e_res_pool_destroy(&pf->qp_pool);
1895         i40e_res_pool_destroy(&pf->msix_pool);
1896
1897         /* force a PF reset to clean anything leftover */
1898         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1899         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1900                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1901         I40E_WRITE_FLUSH(hw);
1902 }
1903
1904 static void
1905 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_vsi *vsi = pf->main_vsi;
1910         int status;
1911
1912         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1913                                                      true, NULL, true);
1914         if (status != I40E_SUCCESS)
1915                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1916
1917         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1918                                                         TRUE, NULL);
1919         if (status != I40E_SUCCESS)
1920                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1921
1922 }
1923
1924 static void
1925 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1926 {
1927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct i40e_vsi *vsi = pf->main_vsi;
1930         int status;
1931
1932         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1933                                                      false, NULL, true);
1934         if (status != I40E_SUCCESS)
1935                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1936
1937         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1938                                                         false, NULL);
1939         if (status != I40E_SUCCESS)
1940                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1941 }
1942
1943 static void
1944 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1945 {
1946         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1947         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         struct i40e_vsi *vsi = pf->main_vsi;
1949         int ret;
1950
1951         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1952         if (ret != I40E_SUCCESS)
1953                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1954 }
1955
1956 static void
1957 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1958 {
1959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961         struct i40e_vsi *vsi = pf->main_vsi;
1962         int ret;
1963
1964         if (dev->data->promiscuous == 1)
1965                 return; /* must remain in all_multicast mode */
1966
1967         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1968                                 vsi->seid, FALSE, NULL);
1969         if (ret != I40E_SUCCESS)
1970                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1971 }
1972
1973 /*
1974  * Set device link up.
1975  */
1976 static int
1977 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1978 {
1979         /* re-apply link speed setting */
1980         return i40e_apply_link_speed(dev);
1981 }
1982
1983 /*
1984  * Set device link down.
1985  */
1986 static int
1987 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1988 {
1989         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1990         uint8_t abilities = 0;
1991         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1992
1993         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1994         return i40e_phy_conf_link(hw, abilities, speed);
1995 }
1996
1997 int
1998 i40e_dev_link_update(struct rte_eth_dev *dev,
1999                      int wait_to_complete)
2000 {
2001 #define CHECK_INTERVAL 100  /* 100ms */
2002 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2003         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         struct i40e_link_status link_status;
2005         struct rte_eth_link link, old;
2006         int status;
2007         unsigned rep_cnt = MAX_REPEAT_TIME;
2008         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2009
2010         memset(&link, 0, sizeof(link));
2011         memset(&old, 0, sizeof(old));
2012         memset(&link_status, 0, sizeof(link_status));
2013         rte_i40e_dev_atomic_read_link_status(dev, &old);
2014
2015         do {
2016                 /* Get link status information from hardware */
2017                 status = i40e_aq_get_link_info(hw, enable_lse,
2018                                                 &link_status, NULL);
2019                 if (status != I40E_SUCCESS) {
2020                         link.link_speed = ETH_SPEED_NUM_100M;
2021                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2022                         PMD_DRV_LOG(ERR, "Failed to get link info");
2023                         goto out;
2024                 }
2025
2026                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2027                 if (!wait_to_complete || link.link_status)
2028                         break;
2029
2030                 rte_delay_ms(CHECK_INTERVAL);
2031         } while (--rep_cnt);
2032
2033         if (!link.link_status)
2034                 goto out;
2035
2036         /* i40e uses full duplex only */
2037         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2038
2039         /* Parse the link status */
2040         switch (link_status.link_speed) {
2041         case I40E_LINK_SPEED_100MB:
2042                 link.link_speed = ETH_SPEED_NUM_100M;
2043                 break;
2044         case I40E_LINK_SPEED_1GB:
2045                 link.link_speed = ETH_SPEED_NUM_1G;
2046                 break;
2047         case I40E_LINK_SPEED_10GB:
2048                 link.link_speed = ETH_SPEED_NUM_10G;
2049                 break;
2050         case I40E_LINK_SPEED_20GB:
2051                 link.link_speed = ETH_SPEED_NUM_20G;
2052                 break;
2053         case I40E_LINK_SPEED_25GB:
2054                 link.link_speed = ETH_SPEED_NUM_25G;
2055                 break;
2056         case I40E_LINK_SPEED_40GB:
2057                 link.link_speed = ETH_SPEED_NUM_40G;
2058                 break;
2059         default:
2060                 link.link_speed = ETH_SPEED_NUM_100M;
2061                 break;
2062         }
2063
2064         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2065                         ETH_LINK_SPEED_FIXED);
2066
2067 out:
2068         rte_i40e_dev_atomic_write_link_status(dev, &link);
2069         if (link.link_status == old.link_status)
2070                 return -1;
2071
2072         return 0;
2073 }
2074
2075 /* Get all the statistics of a VSI */
2076 void
2077 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2078 {
2079         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2080         struct i40e_eth_stats *nes = &vsi->eth_stats;
2081         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2082         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2083
2084         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2085                             vsi->offset_loaded, &oes->rx_bytes,
2086                             &nes->rx_bytes);
2087         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2088                             vsi->offset_loaded, &oes->rx_unicast,
2089                             &nes->rx_unicast);
2090         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2091                             vsi->offset_loaded, &oes->rx_multicast,
2092                             &nes->rx_multicast);
2093         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2094                             vsi->offset_loaded, &oes->rx_broadcast,
2095                             &nes->rx_broadcast);
2096         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2097                             &oes->rx_discards, &nes->rx_discards);
2098         /* GLV_REPC not supported */
2099         /* GLV_RMPC not supported */
2100         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2101                             &oes->rx_unknown_protocol,
2102                             &nes->rx_unknown_protocol);
2103         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2104                             vsi->offset_loaded, &oes->tx_bytes,
2105                             &nes->tx_bytes);
2106         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2107                             vsi->offset_loaded, &oes->tx_unicast,
2108                             &nes->tx_unicast);
2109         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2110                             vsi->offset_loaded, &oes->tx_multicast,
2111                             &nes->tx_multicast);
2112         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2113                             vsi->offset_loaded,  &oes->tx_broadcast,
2114                             &nes->tx_broadcast);
2115         /* GLV_TDPC not supported */
2116         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2117                             &oes->tx_errors, &nes->tx_errors);
2118         vsi->offset_loaded = true;
2119
2120         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2121                     vsi->vsi_id);
2122         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2123         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2124         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2125         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2126         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2127         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2128                     nes->rx_unknown_protocol);
2129         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2130         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2131         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2132         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2133         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2134         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2135         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2136                     vsi->vsi_id);
2137 }
2138
2139 static void
2140 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2141 {
2142         unsigned int i;
2143         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2144         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2145
2146         /* Get statistics of struct i40e_eth_stats */
2147         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2148                             I40E_GLPRT_GORCL(hw->port),
2149                             pf->offset_loaded, &os->eth.rx_bytes,
2150                             &ns->eth.rx_bytes);
2151         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2152                             I40E_GLPRT_UPRCL(hw->port),
2153                             pf->offset_loaded, &os->eth.rx_unicast,
2154                             &ns->eth.rx_unicast);
2155         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2156                             I40E_GLPRT_MPRCL(hw->port),
2157                             pf->offset_loaded, &os->eth.rx_multicast,
2158                             &ns->eth.rx_multicast);
2159         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2160                             I40E_GLPRT_BPRCL(hw->port),
2161                             pf->offset_loaded, &os->eth.rx_broadcast,
2162                             &ns->eth.rx_broadcast);
2163         /* Workaround: CRC size should not be included in byte statistics,
2164          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2165          */
2166         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2167                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2168
2169         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2170                             pf->offset_loaded, &os->eth.rx_discards,
2171                             &ns->eth.rx_discards);
2172         /* GLPRT_REPC not supported */
2173         /* GLPRT_RMPC not supported */
2174         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2175                             pf->offset_loaded,
2176                             &os->eth.rx_unknown_protocol,
2177                             &ns->eth.rx_unknown_protocol);
2178         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2179                             I40E_GLPRT_GOTCL(hw->port),
2180                             pf->offset_loaded, &os->eth.tx_bytes,
2181                             &ns->eth.tx_bytes);
2182         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2183                             I40E_GLPRT_UPTCL(hw->port),
2184                             pf->offset_loaded, &os->eth.tx_unicast,
2185                             &ns->eth.tx_unicast);
2186         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2187                             I40E_GLPRT_MPTCL(hw->port),
2188                             pf->offset_loaded, &os->eth.tx_multicast,
2189                             &ns->eth.tx_multicast);
2190         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2191                             I40E_GLPRT_BPTCL(hw->port),
2192                             pf->offset_loaded, &os->eth.tx_broadcast,
2193                             &ns->eth.tx_broadcast);
2194         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2195                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2196         /* GLPRT_TEPC not supported */
2197
2198         /* additional port specific stats */
2199         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2200                             pf->offset_loaded, &os->tx_dropped_link_down,
2201                             &ns->tx_dropped_link_down);
2202         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2203                             pf->offset_loaded, &os->crc_errors,
2204                             &ns->crc_errors);
2205         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2206                             pf->offset_loaded, &os->illegal_bytes,
2207                             &ns->illegal_bytes);
2208         /* GLPRT_ERRBC not supported */
2209         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2210                             pf->offset_loaded, &os->mac_local_faults,
2211                             &ns->mac_local_faults);
2212         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2213                             pf->offset_loaded, &os->mac_remote_faults,
2214                             &ns->mac_remote_faults);
2215         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2216                             pf->offset_loaded, &os->rx_length_errors,
2217                             &ns->rx_length_errors);
2218         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2219                             pf->offset_loaded, &os->link_xon_rx,
2220                             &ns->link_xon_rx);
2221         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2222                             pf->offset_loaded, &os->link_xoff_rx,
2223                             &ns->link_xoff_rx);
2224         for (i = 0; i < 8; i++) {
2225                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2226                                     pf->offset_loaded,
2227                                     &os->priority_xon_rx[i],
2228                                     &ns->priority_xon_rx[i]);
2229                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2230                                     pf->offset_loaded,
2231                                     &os->priority_xoff_rx[i],
2232                                     &ns->priority_xoff_rx[i]);
2233         }
2234         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2235                             pf->offset_loaded, &os->link_xon_tx,
2236                             &ns->link_xon_tx);
2237         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2238                             pf->offset_loaded, &os->link_xoff_tx,
2239                             &ns->link_xoff_tx);
2240         for (i = 0; i < 8; i++) {
2241                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2242                                     pf->offset_loaded,
2243                                     &os->priority_xon_tx[i],
2244                                     &ns->priority_xon_tx[i]);
2245                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2246                                     pf->offset_loaded,
2247                                     &os->priority_xoff_tx[i],
2248                                     &ns->priority_xoff_tx[i]);
2249                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2250                                     pf->offset_loaded,
2251                                     &os->priority_xon_2_xoff[i],
2252                                     &ns->priority_xon_2_xoff[i]);
2253         }
2254         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2255                             I40E_GLPRT_PRC64L(hw->port),
2256                             pf->offset_loaded, &os->rx_size_64,
2257                             &ns->rx_size_64);
2258         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2259                             I40E_GLPRT_PRC127L(hw->port),
2260                             pf->offset_loaded, &os->rx_size_127,
2261                             &ns->rx_size_127);
2262         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2263                             I40E_GLPRT_PRC255L(hw->port),
2264                             pf->offset_loaded, &os->rx_size_255,
2265                             &ns->rx_size_255);
2266         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2267                             I40E_GLPRT_PRC511L(hw->port),
2268                             pf->offset_loaded, &os->rx_size_511,
2269                             &ns->rx_size_511);
2270         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2271                             I40E_GLPRT_PRC1023L(hw->port),
2272                             pf->offset_loaded, &os->rx_size_1023,
2273                             &ns->rx_size_1023);
2274         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2275                             I40E_GLPRT_PRC1522L(hw->port),
2276                             pf->offset_loaded, &os->rx_size_1522,
2277                             &ns->rx_size_1522);
2278         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2279                             I40E_GLPRT_PRC9522L(hw->port),
2280                             pf->offset_loaded, &os->rx_size_big,
2281                             &ns->rx_size_big);
2282         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2283                             pf->offset_loaded, &os->rx_undersize,
2284                             &ns->rx_undersize);
2285         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2286                             pf->offset_loaded, &os->rx_fragments,
2287                             &ns->rx_fragments);
2288         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2289                             pf->offset_loaded, &os->rx_oversize,
2290                             &ns->rx_oversize);
2291         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2292                             pf->offset_loaded, &os->rx_jabber,
2293                             &ns->rx_jabber);
2294         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2295                             I40E_GLPRT_PTC64L(hw->port),
2296                             pf->offset_loaded, &os->tx_size_64,
2297                             &ns->tx_size_64);
2298         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2299                             I40E_GLPRT_PTC127L(hw->port),
2300                             pf->offset_loaded, &os->tx_size_127,
2301                             &ns->tx_size_127);
2302         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2303                             I40E_GLPRT_PTC255L(hw->port),
2304                             pf->offset_loaded, &os->tx_size_255,
2305                             &ns->tx_size_255);
2306         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2307                             I40E_GLPRT_PTC511L(hw->port),
2308                             pf->offset_loaded, &os->tx_size_511,
2309                             &ns->tx_size_511);
2310         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2311                             I40E_GLPRT_PTC1023L(hw->port),
2312                             pf->offset_loaded, &os->tx_size_1023,
2313                             &ns->tx_size_1023);
2314         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2315                             I40E_GLPRT_PTC1522L(hw->port),
2316                             pf->offset_loaded, &os->tx_size_1522,
2317                             &ns->tx_size_1522);
2318         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2319                             I40E_GLPRT_PTC9522L(hw->port),
2320                             pf->offset_loaded, &os->tx_size_big,
2321                             &ns->tx_size_big);
2322         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2323                            pf->offset_loaded,
2324                            &os->fd_sb_match, &ns->fd_sb_match);
2325         /* GLPRT_MSPDC not supported */
2326         /* GLPRT_XEC not supported */
2327
2328         pf->offset_loaded = true;
2329
2330         if (pf->main_vsi)
2331                 i40e_update_vsi_stats(pf->main_vsi);
2332 }
2333
2334 /* Get all statistics of a port */
2335 static void
2336 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2337 {
2338         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2341         unsigned i;
2342
2343         /* call read registers - updates values, now write them to struct */
2344         i40e_read_stats_registers(pf, hw);
2345
2346         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2347                         pf->main_vsi->eth_stats.rx_multicast +
2348                         pf->main_vsi->eth_stats.rx_broadcast -
2349                         pf->main_vsi->eth_stats.rx_discards;
2350         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2351                         pf->main_vsi->eth_stats.tx_multicast +
2352                         pf->main_vsi->eth_stats.tx_broadcast;
2353         stats->ibytes   = ns->eth.rx_bytes;
2354         stats->obytes   = ns->eth.tx_bytes;
2355         stats->oerrors  = ns->eth.tx_errors +
2356                         pf->main_vsi->eth_stats.tx_errors;
2357
2358         /* Rx Errors */
2359         stats->imissed  = ns->eth.rx_discards +
2360                         pf->main_vsi->eth_stats.rx_discards;
2361         stats->ierrors  = ns->crc_errors +
2362                         ns->rx_length_errors + ns->rx_undersize +
2363                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2364
2365         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2366         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2367         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2368         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2369         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2370         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2371         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2372                     ns->eth.rx_unknown_protocol);
2373         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2374         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2375         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2376         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2377         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2378         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2379
2380         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2381                     ns->tx_dropped_link_down);
2382         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2383         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2384                     ns->illegal_bytes);
2385         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2386         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2387                     ns->mac_local_faults);
2388         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2389                     ns->mac_remote_faults);
2390         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2391                     ns->rx_length_errors);
2392         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2393         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2394         for (i = 0; i < 8; i++) {
2395                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2396                                 i, ns->priority_xon_rx[i]);
2397                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2398                                 i, ns->priority_xoff_rx[i]);
2399         }
2400         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2401         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2402         for (i = 0; i < 8; i++) {
2403                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2404                                 i, ns->priority_xon_tx[i]);
2405                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2406                                 i, ns->priority_xoff_tx[i]);
2407                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2408                                 i, ns->priority_xon_2_xoff[i]);
2409         }
2410         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2411         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2412         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2413         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2414         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2415         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2416         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2417         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2418         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2419         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2420         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2421         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2422         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2423         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2424         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2425         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2426         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2427         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2428         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2429                         ns->mac_short_packet_dropped);
2430         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2431                     ns->checksum_error);
2432         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2433         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2434 }
2435
2436 /* Reset the statistics */
2437 static void
2438 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2439 {
2440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2441         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442
2443         /* Mark PF and VSI stats to update the offset, aka "reset" */
2444         pf->offset_loaded = false;
2445         if (pf->main_vsi)
2446                 pf->main_vsi->offset_loaded = false;
2447
2448         /* read the stats, reading current register values into offset */
2449         i40e_read_stats_registers(pf, hw);
2450 }
2451
2452 static uint32_t
2453 i40e_xstats_calc_num(void)
2454 {
2455         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2456                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2457                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2458 }
2459
2460 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2461                                      struct rte_eth_xstat_name *xstats_names,
2462                                      __rte_unused unsigned limit)
2463 {
2464         unsigned count = 0;
2465         unsigned i, prio;
2466
2467         if (xstats_names == NULL)
2468                 return i40e_xstats_calc_num();
2469
2470         /* Note: limit checked in rte_eth_xstats_names() */
2471
2472         /* Get stats from i40e_eth_stats struct */
2473         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2474                 snprintf(xstats_names[count].name,
2475                          sizeof(xstats_names[count].name),
2476                          "%s", rte_i40e_stats_strings[i].name);
2477                 count++;
2478         }
2479
2480         /* Get individiual stats from i40e_hw_port struct */
2481         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2482                 snprintf(xstats_names[count].name,
2483                         sizeof(xstats_names[count].name),
2484                          "%s", rte_i40e_hw_port_strings[i].name);
2485                 count++;
2486         }
2487
2488         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2489                 for (prio = 0; prio < 8; prio++) {
2490                         snprintf(xstats_names[count].name,
2491                                  sizeof(xstats_names[count].name),
2492                                  "rx_priority%u_%s", prio,
2493                                  rte_i40e_rxq_prio_strings[i].name);
2494                         count++;
2495                 }
2496         }
2497
2498         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2499                 for (prio = 0; prio < 8; prio++) {
2500                         snprintf(xstats_names[count].name,
2501                                  sizeof(xstats_names[count].name),
2502                                  "tx_priority%u_%s", prio,
2503                                  rte_i40e_txq_prio_strings[i].name);
2504                         count++;
2505                 }
2506         }
2507         return count;
2508 }
2509
2510 static int
2511 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2512                     unsigned n)
2513 {
2514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516         unsigned i, count, prio;
2517         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2518
2519         count = i40e_xstats_calc_num();
2520         if (n < count)
2521                 return count;
2522
2523         i40e_read_stats_registers(pf, hw);
2524
2525         if (xstats == NULL)
2526                 return 0;
2527
2528         count = 0;
2529
2530         /* Get stats from i40e_eth_stats struct */
2531         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2532                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2533                         rte_i40e_stats_strings[i].offset);
2534                 xstats[count].id = count;
2535                 count++;
2536         }
2537
2538         /* Get individiual stats from i40e_hw_port struct */
2539         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2540                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2541                         rte_i40e_hw_port_strings[i].offset);
2542                 xstats[count].id = count;
2543                 count++;
2544         }
2545
2546         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2547                 for (prio = 0; prio < 8; prio++) {
2548                         xstats[count].value =
2549                                 *(uint64_t *)(((char *)hw_stats) +
2550                                 rte_i40e_rxq_prio_strings[i].offset +
2551                                 (sizeof(uint64_t) * prio));
2552                         xstats[count].id = count;
2553                         count++;
2554                 }
2555         }
2556
2557         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2558                 for (prio = 0; prio < 8; prio++) {
2559                         xstats[count].value =
2560                                 *(uint64_t *)(((char *)hw_stats) +
2561                                 rte_i40e_txq_prio_strings[i].offset +
2562                                 (sizeof(uint64_t) * prio));
2563                         xstats[count].id = count;
2564                         count++;
2565                 }
2566         }
2567
2568         return count;
2569 }
2570
2571 static int
2572 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2573                                  __rte_unused uint16_t queue_id,
2574                                  __rte_unused uint8_t stat_idx,
2575                                  __rte_unused uint8_t is_rx)
2576 {
2577         PMD_INIT_FUNC_TRACE();
2578
2579         return -ENOSYS;
2580 }
2581
2582 static void
2583 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2584 {
2585         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2586         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587         struct i40e_vsi *vsi = pf->main_vsi;
2588
2589         dev_info->max_rx_queues = vsi->nb_qps;
2590         dev_info->max_tx_queues = vsi->nb_qps;
2591         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2592         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2593         dev_info->max_mac_addrs = vsi->max_macaddrs;
2594         dev_info->max_vfs = dev->pci_dev->max_vfs;
2595         dev_info->rx_offload_capa =
2596                 DEV_RX_OFFLOAD_VLAN_STRIP |
2597                 DEV_RX_OFFLOAD_QINQ_STRIP |
2598                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2599                 DEV_RX_OFFLOAD_UDP_CKSUM |
2600                 DEV_RX_OFFLOAD_TCP_CKSUM;
2601         dev_info->tx_offload_capa =
2602                 DEV_TX_OFFLOAD_VLAN_INSERT |
2603                 DEV_TX_OFFLOAD_QINQ_INSERT |
2604                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2605                 DEV_TX_OFFLOAD_UDP_CKSUM |
2606                 DEV_TX_OFFLOAD_TCP_CKSUM |
2607                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2608                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2609                 DEV_TX_OFFLOAD_TCP_TSO |
2610                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2611                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2612                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2613                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2614         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2615                                                 sizeof(uint32_t);
2616         dev_info->reta_size = pf->hash_lut_size;
2617         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2618
2619         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2620                 .rx_thresh = {
2621                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2622                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2623                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2624                 },
2625                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2626                 .rx_drop_en = 0,
2627         };
2628
2629         dev_info->default_txconf = (struct rte_eth_txconf) {
2630                 .tx_thresh = {
2631                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2632                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2633                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2634                 },
2635                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2636                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2637                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2638                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2639         };
2640
2641         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2642                 .nb_max = I40E_MAX_RING_DESC,
2643                 .nb_min = I40E_MIN_RING_DESC,
2644                 .nb_align = I40E_ALIGN_RING_DESC,
2645         };
2646
2647         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2648                 .nb_max = I40E_MAX_RING_DESC,
2649                 .nb_min = I40E_MIN_RING_DESC,
2650                 .nb_align = I40E_ALIGN_RING_DESC,
2651         };
2652
2653         if (pf->flags & I40E_FLAG_VMDQ) {
2654                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2655                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2656                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2657                                                 pf->max_nb_vmdq_vsi;
2658                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2659                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2660                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2661         }
2662
2663         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2664                 /* For XL710 */
2665                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2666         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2667                 /* For XXV710 */
2668                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2669         else
2670                 /* For X710 */
2671                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2672 }
2673
2674 static int
2675 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2676 {
2677         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2678         struct i40e_vsi *vsi = pf->main_vsi;
2679         PMD_INIT_FUNC_TRACE();
2680
2681         if (on)
2682                 return i40e_vsi_add_vlan(vsi, vlan_id);
2683         else
2684                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2685 }
2686
2687 static int
2688 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2689                    enum rte_vlan_type vlan_type,
2690                    uint16_t tpid)
2691 {
2692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2693         uint64_t reg_r = 0, reg_w = 0;
2694         uint16_t reg_id = 0;
2695         int ret = 0;
2696         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2697
2698         switch (vlan_type) {
2699         case ETH_VLAN_TYPE_OUTER:
2700                 if (qinq)
2701                         reg_id = 2;
2702                 else
2703                         reg_id = 3;
2704                 break;
2705         case ETH_VLAN_TYPE_INNER:
2706                 if (qinq)
2707                         reg_id = 3;
2708                 else {
2709                         ret = -EINVAL;
2710                         PMD_DRV_LOG(ERR,
2711                                 "Unsupported vlan type in single vlan.\n");
2712                         return ret;
2713                 }
2714                 break;
2715         default:
2716                 ret = -EINVAL;
2717                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2718                 return ret;
2719         }
2720         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2721                                           &reg_r, NULL);
2722         if (ret != I40E_SUCCESS) {
2723                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2724                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2725                 ret = -EIO;
2726                 return ret;
2727         }
2728         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2729                     "0x%08"PRIx64"", reg_id, reg_r);
2730
2731         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2732         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2733         if (reg_r == reg_w) {
2734                 ret = 0;
2735                 PMD_DRV_LOG(DEBUG, "No need to write");
2736                 return ret;
2737         }
2738
2739         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2740                                            reg_w, NULL);
2741         if (ret != I40E_SUCCESS) {
2742                 ret = -EIO;
2743                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2744                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2745                 return ret;
2746         }
2747         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2748                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2749
2750         return ret;
2751 }
2752
2753 static void
2754 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2755 {
2756         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2757         struct i40e_vsi *vsi = pf->main_vsi;
2758
2759         if (mask & ETH_VLAN_FILTER_MASK) {
2760                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2761                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2762                 else
2763                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2764         }
2765
2766         if (mask & ETH_VLAN_STRIP_MASK) {
2767                 /* Enable or disable VLAN stripping */
2768                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2769                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2770                 else
2771                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2772         }
2773
2774         if (mask & ETH_VLAN_EXTEND_MASK) {
2775                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2776                         i40e_vsi_config_double_vlan(vsi, TRUE);
2777                         /* Set global registers with default ether type value */
2778                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2779                                            ETHER_TYPE_VLAN);
2780                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2781                                            ETHER_TYPE_VLAN);
2782                 }
2783                 else
2784                         i40e_vsi_config_double_vlan(vsi, FALSE);
2785         }
2786 }
2787
2788 static void
2789 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2790                           __rte_unused uint16_t queue,
2791                           __rte_unused int on)
2792 {
2793         PMD_INIT_FUNC_TRACE();
2794 }
2795
2796 static int
2797 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2798 {
2799         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2800         struct i40e_vsi *vsi = pf->main_vsi;
2801         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2802         struct i40e_vsi_vlan_pvid_info info;
2803
2804         memset(&info, 0, sizeof(info));
2805         info.on = on;
2806         if (info.on)
2807                 info.config.pvid = pvid;
2808         else {
2809                 info.config.reject.tagged =
2810                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2811                 info.config.reject.untagged =
2812                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2813         }
2814
2815         return i40e_vsi_vlan_pvid_set(vsi, &info);
2816 }
2817
2818 static int
2819 i40e_dev_led_on(struct rte_eth_dev *dev)
2820 {
2821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822         uint32_t mode = i40e_led_get(hw);
2823
2824         if (mode == 0)
2825                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2826
2827         return 0;
2828 }
2829
2830 static int
2831 i40e_dev_led_off(struct rte_eth_dev *dev)
2832 {
2833         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2834         uint32_t mode = i40e_led_get(hw);
2835
2836         if (mode != 0)
2837                 i40e_led_set(hw, 0, false);
2838
2839         return 0;
2840 }
2841
2842 static int
2843 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2844 {
2845         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2847
2848         fc_conf->pause_time = pf->fc_conf.pause_time;
2849         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2850         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2851
2852          /* Return current mode according to actual setting*/
2853         switch (hw->fc.current_mode) {
2854         case I40E_FC_FULL:
2855                 fc_conf->mode = RTE_FC_FULL;
2856                 break;
2857         case I40E_FC_TX_PAUSE:
2858                 fc_conf->mode = RTE_FC_TX_PAUSE;
2859                 break;
2860         case I40E_FC_RX_PAUSE:
2861                 fc_conf->mode = RTE_FC_RX_PAUSE;
2862                 break;
2863         case I40E_FC_NONE:
2864         default:
2865                 fc_conf->mode = RTE_FC_NONE;
2866         };
2867
2868         return 0;
2869 }
2870
2871 static int
2872 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2873 {
2874         uint32_t mflcn_reg, fctrl_reg, reg;
2875         uint32_t max_high_water;
2876         uint8_t i, aq_failure;
2877         int err;
2878         struct i40e_hw *hw;
2879         struct i40e_pf *pf;
2880         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2881                 [RTE_FC_NONE] = I40E_FC_NONE,
2882                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2883                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2884                 [RTE_FC_FULL] = I40E_FC_FULL
2885         };
2886
2887         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2888
2889         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2890         if ((fc_conf->high_water > max_high_water) ||
2891                         (fc_conf->high_water < fc_conf->low_water)) {
2892                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2893                         "High_water must <= %d.", max_high_water);
2894                 return -EINVAL;
2895         }
2896
2897         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2900
2901         pf->fc_conf.pause_time = fc_conf->pause_time;
2902         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2903         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2904
2905         PMD_INIT_FUNC_TRACE();
2906
2907         /* All the link flow control related enable/disable register
2908          * configuration is handle by the F/W
2909          */
2910         err = i40e_set_fc(hw, &aq_failure, true);
2911         if (err < 0)
2912                 return -ENOSYS;
2913
2914         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2915                 /* Configure flow control refresh threshold,
2916                  * the value for stat_tx_pause_refresh_timer[8]
2917                  * is used for global pause operation.
2918                  */
2919
2920                 I40E_WRITE_REG(hw,
2921                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2922                                pf->fc_conf.pause_time);
2923
2924                 /* configure the timer value included in transmitted pause
2925                  * frame,
2926                  * the value for stat_tx_pause_quanta[8] is used for global
2927                  * pause operation
2928                  */
2929                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2930                                pf->fc_conf.pause_time);
2931
2932                 fctrl_reg = I40E_READ_REG(hw,
2933                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2934
2935                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2936                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2937                 else
2938                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2939
2940                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2941                                fctrl_reg);
2942         } else {
2943                 /* Configure pause time (2 TCs per register) */
2944                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2945                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2946                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2947
2948                 /* Configure flow control refresh threshold value */
2949                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2950                                pf->fc_conf.pause_time / 2);
2951
2952                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2953
2954                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2955                  *depending on configuration
2956                  */
2957                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2958                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2959                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2960                 } else {
2961                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2962                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2963                 }
2964
2965                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2966         }
2967
2968         /* config the water marker both based on the packets and bytes */
2969         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2970                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2971                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2972         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2973                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2974                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2975         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2976                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2977                        << I40E_KILOSHIFT);
2978         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2979                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2980                        << I40E_KILOSHIFT);
2981
2982         I40E_WRITE_FLUSH(hw);
2983
2984         return 0;
2985 }
2986
2987 static int
2988 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2989                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2990 {
2991         PMD_INIT_FUNC_TRACE();
2992
2993         return -ENOSYS;
2994 }
2995
2996 /* Add a MAC address, and update filters */
2997 static void
2998 i40e_macaddr_add(struct rte_eth_dev *dev,
2999                  struct ether_addr *mac_addr,
3000                  __rte_unused uint32_t index,
3001                  uint32_t pool)
3002 {
3003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3004         struct i40e_mac_filter_info mac_filter;
3005         struct i40e_vsi *vsi;
3006         int ret;
3007
3008         /* If VMDQ not enabled or configured, return */
3009         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3010                           !pf->nb_cfg_vmdq_vsi)) {
3011                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3012                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3013                         pool);
3014                 return;
3015         }
3016
3017         if (pool > pf->nb_cfg_vmdq_vsi) {
3018                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3019                                 pool, pf->nb_cfg_vmdq_vsi);
3020                 return;
3021         }
3022
3023         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3024         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3025                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3026         else
3027                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3028
3029         if (pool == 0)
3030                 vsi = pf->main_vsi;
3031         else
3032                 vsi = pf->vmdq[pool - 1].vsi;
3033
3034         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3035         if (ret != I40E_SUCCESS) {
3036                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3037                 return;
3038         }
3039 }
3040
3041 /* Remove a MAC address, and update filters */
3042 static void
3043 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3044 {
3045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3046         struct i40e_vsi *vsi;
3047         struct rte_eth_dev_data *data = dev->data;
3048         struct ether_addr *macaddr;
3049         int ret;
3050         uint32_t i;
3051         uint64_t pool_sel;
3052
3053         macaddr = &(data->mac_addrs[index]);
3054
3055         pool_sel = dev->data->mac_pool_sel[index];
3056
3057         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3058                 if (pool_sel & (1ULL << i)) {
3059                         if (i == 0)
3060                                 vsi = pf->main_vsi;
3061                         else {
3062                                 /* No VMDQ pool enabled or configured */
3063                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3064                                         (i > pf->nb_cfg_vmdq_vsi)) {
3065                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3066                                                         "/configured");
3067                                         return;
3068                                 }
3069                                 vsi = pf->vmdq[i - 1].vsi;
3070                         }
3071                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3072
3073                         if (ret) {
3074                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3075                                 return;
3076                         }
3077                 }
3078         }
3079 }
3080
3081 /* Set perfect match or hash match of MAC and VLAN for a VF */
3082 static int
3083 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3084                  struct rte_eth_mac_filter *filter,
3085                  bool add)
3086 {
3087         struct i40e_hw *hw;
3088         struct i40e_mac_filter_info mac_filter;
3089         struct ether_addr old_mac;
3090         struct ether_addr *new_mac;
3091         struct i40e_pf_vf *vf = NULL;
3092         uint16_t vf_id;
3093         int ret;
3094
3095         if (pf == NULL) {
3096                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3097                 return -EINVAL;
3098         }
3099         hw = I40E_PF_TO_HW(pf);
3100
3101         if (filter == NULL) {
3102                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3103                 return -EINVAL;
3104         }
3105
3106         new_mac = &filter->mac_addr;
3107
3108         if (is_zero_ether_addr(new_mac)) {
3109                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3110                 return -EINVAL;
3111         }
3112
3113         vf_id = filter->dst_id;
3114
3115         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3116                 PMD_DRV_LOG(ERR, "Invalid argument.");
3117                 return -EINVAL;
3118         }
3119         vf = &pf->vfs[vf_id];
3120
3121         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3122                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3123                 return -EINVAL;
3124         }
3125
3126         if (add) {
3127                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3128                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3129                                 ETHER_ADDR_LEN);
3130                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3131                                  ETHER_ADDR_LEN);
3132
3133                 mac_filter.filter_type = filter->filter_type;
3134                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3135                 if (ret != I40E_SUCCESS) {
3136                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3137                         return -1;
3138                 }
3139                 ether_addr_copy(new_mac, &pf->dev_addr);
3140         } else {
3141                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3142                                 ETHER_ADDR_LEN);
3143                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3144                 if (ret != I40E_SUCCESS) {
3145                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3146                         return -1;
3147                 }
3148
3149                 /* Clear device address as it has been removed */
3150                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3151                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3152         }
3153
3154         return 0;
3155 }
3156
3157 /* MAC filter handle */
3158 static int
3159 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3160                 void *arg)
3161 {
3162         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3163         struct rte_eth_mac_filter *filter;
3164         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3165         int ret = I40E_NOT_SUPPORTED;
3166
3167         filter = (struct rte_eth_mac_filter *)(arg);
3168
3169         switch (filter_op) {
3170         case RTE_ETH_FILTER_NOP:
3171                 ret = I40E_SUCCESS;
3172                 break;
3173         case RTE_ETH_FILTER_ADD:
3174                 i40e_pf_disable_irq0(hw);
3175                 if (filter->is_vf)
3176                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3177                 i40e_pf_enable_irq0(hw);
3178                 break;
3179         case RTE_ETH_FILTER_DELETE:
3180                 i40e_pf_disable_irq0(hw);
3181                 if (filter->is_vf)
3182                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3183                 i40e_pf_enable_irq0(hw);
3184                 break;
3185         default:
3186                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3187                 ret = I40E_ERR_PARAM;
3188                 break;
3189         }
3190
3191         return ret;
3192 }
3193
3194 static int
3195 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3196 {
3197         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3198         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3199         int ret;
3200
3201         if (!lut)
3202                 return -EINVAL;
3203
3204         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3205                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3206                                           lut, lut_size);
3207                 if (ret) {
3208                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3209                         return ret;
3210                 }
3211         } else {
3212                 uint32_t *lut_dw = (uint32_t *)lut;
3213                 uint16_t i, lut_size_dw = lut_size / 4;
3214
3215                 for (i = 0; i < lut_size_dw; i++)
3216                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3217         }
3218
3219         return 0;
3220 }
3221
3222 static int
3223 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3224 {
3225         struct i40e_pf *pf;
3226         struct i40e_hw *hw;
3227         int ret;
3228
3229         if (!vsi || !lut)
3230                 return -EINVAL;
3231
3232         pf = I40E_VSI_TO_PF(vsi);
3233         hw = I40E_VSI_TO_HW(vsi);
3234
3235         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3236                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3237                                           lut, lut_size);
3238                 if (ret) {
3239                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3240                         return ret;
3241                 }
3242         } else {
3243                 uint32_t *lut_dw = (uint32_t *)lut;
3244                 uint16_t i, lut_size_dw = lut_size / 4;
3245
3246                 for (i = 0; i < lut_size_dw; i++)
3247                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3248                 I40E_WRITE_FLUSH(hw);
3249         }
3250
3251         return 0;
3252 }
3253
3254 static int
3255 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3256                          struct rte_eth_rss_reta_entry64 *reta_conf,
3257                          uint16_t reta_size)
3258 {
3259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3260         uint16_t i, lut_size = pf->hash_lut_size;
3261         uint16_t idx, shift;
3262         uint8_t *lut;
3263         int ret;
3264
3265         if (reta_size != lut_size ||
3266                 reta_size > ETH_RSS_RETA_SIZE_512) {
3267                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3268                         "(%d) doesn't match the number hardware can supported "
3269                                         "(%d)\n", reta_size, lut_size);
3270                 return -EINVAL;
3271         }
3272
3273         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3274         if (!lut) {
3275                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3276                 return -ENOMEM;
3277         }
3278         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3279         if (ret)
3280                 goto out;
3281         for (i = 0; i < reta_size; i++) {
3282                 idx = i / RTE_RETA_GROUP_SIZE;
3283                 shift = i % RTE_RETA_GROUP_SIZE;
3284                 if (reta_conf[idx].mask & (1ULL << shift))
3285                         lut[i] = reta_conf[idx].reta[shift];
3286         }
3287         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3288
3289 out:
3290         rte_free(lut);
3291
3292         return ret;
3293 }
3294
3295 static int
3296 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3297                         struct rte_eth_rss_reta_entry64 *reta_conf,
3298                         uint16_t reta_size)
3299 {
3300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3301         uint16_t i, lut_size = pf->hash_lut_size;
3302         uint16_t idx, shift;
3303         uint8_t *lut;
3304         int ret;
3305
3306         if (reta_size != lut_size ||
3307                 reta_size > ETH_RSS_RETA_SIZE_512) {
3308                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3309                         "(%d) doesn't match the number hardware can supported "
3310                                         "(%d)\n", reta_size, lut_size);
3311                 return -EINVAL;
3312         }
3313
3314         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3315         if (!lut) {
3316                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3317                 return -ENOMEM;
3318         }
3319
3320         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3321         if (ret)
3322                 goto out;
3323         for (i = 0; i < reta_size; i++) {
3324                 idx = i / RTE_RETA_GROUP_SIZE;
3325                 shift = i % RTE_RETA_GROUP_SIZE;
3326                 if (reta_conf[idx].mask & (1ULL << shift))
3327                         reta_conf[idx].reta[shift] = lut[i];
3328         }
3329
3330 out:
3331         rte_free(lut);
3332
3333         return ret;
3334 }
3335
3336 /**
3337  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3338  * @hw:   pointer to the HW structure
3339  * @mem:  pointer to mem struct to fill out
3340  * @size: size of memory requested
3341  * @alignment: what to align the allocation to
3342  **/
3343 enum i40e_status_code
3344 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3345                         struct i40e_dma_mem *mem,
3346                         u64 size,
3347                         u32 alignment)
3348 {
3349         const struct rte_memzone *mz = NULL;
3350         char z_name[RTE_MEMZONE_NAMESIZE];
3351
3352         if (!mem)
3353                 return I40E_ERR_PARAM;
3354
3355         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3356         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3357                                          alignment, RTE_PGSIZE_2M);
3358         if (!mz)
3359                 return I40E_ERR_NO_MEMORY;
3360
3361         mem->size = size;
3362         mem->va = mz->addr;
3363         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3364         mem->zone = (const void *)mz;
3365         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3366                     "%"PRIu64, mz->name, mem->pa);
3367
3368         return I40E_SUCCESS;
3369 }
3370
3371 /**
3372  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3373  * @hw:   pointer to the HW structure
3374  * @mem:  ptr to mem struct to free
3375  **/
3376 enum i40e_status_code
3377 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3378                     struct i40e_dma_mem *mem)
3379 {
3380         if (!mem)
3381                 return I40E_ERR_PARAM;
3382
3383         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3384                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3385                     mem->pa);
3386         rte_memzone_free((const struct rte_memzone *)mem->zone);
3387         mem->zone = NULL;
3388         mem->va = NULL;
3389         mem->pa = (u64)0;
3390
3391         return I40E_SUCCESS;
3392 }
3393
3394 /**
3395  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3396  * @hw:   pointer to the HW structure
3397  * @mem:  pointer to mem struct to fill out
3398  * @size: size of memory requested
3399  **/
3400 enum i40e_status_code
3401 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3402                          struct i40e_virt_mem *mem,
3403                          u32 size)
3404 {
3405         if (!mem)
3406                 return I40E_ERR_PARAM;
3407
3408         mem->size = size;
3409         mem->va = rte_zmalloc("i40e", size, 0);
3410
3411         if (mem->va)
3412                 return I40E_SUCCESS;
3413         else
3414                 return I40E_ERR_NO_MEMORY;
3415 }
3416
3417 /**
3418  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3419  * @hw:   pointer to the HW structure
3420  * @mem:  pointer to mem struct to free
3421  **/
3422 enum i40e_status_code
3423 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3424                      struct i40e_virt_mem *mem)
3425 {
3426         if (!mem)
3427                 return I40E_ERR_PARAM;
3428
3429         rte_free(mem->va);
3430         mem->va = NULL;
3431
3432         return I40E_SUCCESS;
3433 }
3434
3435 void
3436 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3437 {
3438         rte_spinlock_init(&sp->spinlock);
3439 }
3440
3441 void
3442 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3443 {
3444         rte_spinlock_lock(&sp->spinlock);
3445 }
3446
3447 void
3448 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3449 {
3450         rte_spinlock_unlock(&sp->spinlock);
3451 }
3452
3453 void
3454 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3455 {
3456         return;
3457 }
3458
3459 /**
3460  * Get the hardware capabilities, which will be parsed
3461  * and saved into struct i40e_hw.
3462  */
3463 static int
3464 i40e_get_cap(struct i40e_hw *hw)
3465 {
3466         struct i40e_aqc_list_capabilities_element_resp *buf;
3467         uint16_t len, size = 0;
3468         int ret;
3469
3470         /* Calculate a huge enough buff for saving response data temporarily */
3471         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3472                                                 I40E_MAX_CAP_ELE_NUM;
3473         buf = rte_zmalloc("i40e", len, 0);
3474         if (!buf) {
3475                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3476                 return I40E_ERR_NO_MEMORY;
3477         }
3478
3479         /* Get, parse the capabilities and save it to hw */
3480         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3481                         i40e_aqc_opc_list_func_capabilities, NULL);
3482         if (ret != I40E_SUCCESS)
3483                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3484
3485         /* Free the temporary buffer after being used */
3486         rte_free(buf);
3487
3488         return ret;
3489 }
3490
3491 static int
3492 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3493 {
3494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3495         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3496         uint16_t qp_count = 0, vsi_count = 0;
3497
3498         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3499                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3500                 return -EINVAL;
3501         }
3502         /* Add the parameter init for LFC */
3503         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3504         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3505         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3506
3507         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3508         pf->max_num_vsi = hw->func_caps.num_vsis;
3509         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3510         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3511         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3512
3513         /* FDir queue/VSI allocation */
3514         pf->fdir_qp_offset = 0;
3515         if (hw->func_caps.fd) {
3516                 pf->flags |= I40E_FLAG_FDIR;
3517                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3518         } else {
3519                 pf->fdir_nb_qps = 0;
3520         }
3521         qp_count += pf->fdir_nb_qps;
3522         vsi_count += 1;
3523
3524         /* LAN queue/VSI allocation */
3525         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3526         if (!hw->func_caps.rss) {
3527                 pf->lan_nb_qps = 1;
3528         } else {
3529                 pf->flags |= I40E_FLAG_RSS;
3530                 if (hw->mac.type == I40E_MAC_X722)
3531                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3532                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3533         }
3534         qp_count += pf->lan_nb_qps;
3535         vsi_count += 1;
3536
3537         /* VF queue/VSI allocation */
3538         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3539         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3540                 pf->flags |= I40E_FLAG_SRIOV;
3541                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3542                 pf->vf_num = dev->pci_dev->max_vfs;
3543                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3544                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3545                             pf->vf_nb_qps * pf->vf_num);
3546         } else {
3547                 pf->vf_nb_qps = 0;
3548                 pf->vf_num = 0;
3549         }
3550         qp_count += pf->vf_nb_qps * pf->vf_num;
3551         vsi_count += pf->vf_num;
3552
3553         /* VMDq queue/VSI allocation */
3554         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3555         pf->vmdq_nb_qps = 0;
3556         pf->max_nb_vmdq_vsi = 0;
3557         if (hw->func_caps.vmdq) {
3558                 if (qp_count < hw->func_caps.num_tx_qp &&
3559                         vsi_count < hw->func_caps.num_vsis) {
3560                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3561                                 qp_count) / pf->vmdq_nb_qp_max;
3562
3563                         /* Limit the maximum number of VMDq vsi to the maximum
3564                          * ethdev can support
3565                          */
3566                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3567                                 hw->func_caps.num_vsis - vsi_count);
3568                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3569                                 ETH_64_POOLS);
3570                         if (pf->max_nb_vmdq_vsi) {
3571                                 pf->flags |= I40E_FLAG_VMDQ;
3572                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3573                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3574                                             "per VMDQ VSI, in total %u queues",
3575                                             pf->max_nb_vmdq_vsi,
3576                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3577                                             pf->max_nb_vmdq_vsi);
3578                         } else {
3579                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3580                                             "VMDq");
3581                         }
3582                 } else {
3583                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3584                 }
3585         }
3586         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3587         vsi_count += pf->max_nb_vmdq_vsi;
3588
3589         if (hw->func_caps.dcb)
3590                 pf->flags |= I40E_FLAG_DCB;
3591
3592         if (qp_count > hw->func_caps.num_tx_qp) {
3593                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3594                             "the hardware maximum %u", qp_count,
3595                             hw->func_caps.num_tx_qp);
3596                 return -EINVAL;
3597         }
3598         if (vsi_count > hw->func_caps.num_vsis) {
3599                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3600                             "the hardware maximum %u", vsi_count,
3601                             hw->func_caps.num_vsis);
3602                 return -EINVAL;
3603         }
3604
3605         return 0;
3606 }
3607
3608 static int
3609 i40e_pf_get_switch_config(struct i40e_pf *pf)
3610 {
3611         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3612         struct i40e_aqc_get_switch_config_resp *switch_config;
3613         struct i40e_aqc_switch_config_element_resp *element;
3614         uint16_t start_seid = 0, num_reported;
3615         int ret;
3616
3617         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3618                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3619         if (!switch_config) {
3620                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3621                 return -ENOMEM;
3622         }
3623
3624         /* Get the switch configurations */
3625         ret = i40e_aq_get_switch_config(hw, switch_config,
3626                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3627         if (ret != I40E_SUCCESS) {
3628                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3629                 goto fail;
3630         }
3631         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3632         if (num_reported != 1) { /* The number should be 1 */
3633                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3634                 goto fail;
3635         }
3636
3637         /* Parse the switch configuration elements */
3638         element = &(switch_config->element[0]);
3639         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3640                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3641                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3642         } else
3643                 PMD_DRV_LOG(INFO, "Unknown element type");
3644
3645 fail:
3646         rte_free(switch_config);
3647
3648         return ret;
3649 }
3650
3651 static int
3652 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3653                         uint32_t num)
3654 {
3655         struct pool_entry *entry;
3656
3657         if (pool == NULL || num == 0)
3658                 return -EINVAL;
3659
3660         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3661         if (entry == NULL) {
3662                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3663                 return -ENOMEM;
3664         }
3665
3666         /* queue heap initialize */
3667         pool->num_free = num;
3668         pool->num_alloc = 0;
3669         pool->base = base;
3670         LIST_INIT(&pool->alloc_list);
3671         LIST_INIT(&pool->free_list);
3672
3673         /* Initialize element  */
3674         entry->base = 0;
3675         entry->len = num;
3676
3677         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3678         return 0;
3679 }
3680
3681 static void
3682 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3683 {
3684         struct pool_entry *entry, *next_entry;
3685
3686         if (pool == NULL)
3687                 return;
3688
3689         for (entry = LIST_FIRST(&pool->alloc_list);
3690                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3691                         entry = next_entry) {
3692                 LIST_REMOVE(entry, next);
3693                 rte_free(entry);
3694         }
3695
3696         for (entry = LIST_FIRST(&pool->free_list);
3697                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3698                         entry = next_entry) {
3699                 LIST_REMOVE(entry, next);
3700                 rte_free(entry);
3701         }
3702
3703         pool->num_free = 0;
3704         pool->num_alloc = 0;
3705         pool->base = 0;
3706         LIST_INIT(&pool->alloc_list);
3707         LIST_INIT(&pool->free_list);
3708 }
3709
3710 static int
3711 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3712                        uint32_t base)
3713 {
3714         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3715         uint32_t pool_offset;
3716         int insert;
3717
3718         if (pool == NULL) {
3719                 PMD_DRV_LOG(ERR, "Invalid parameter");
3720                 return -EINVAL;
3721         }
3722
3723         pool_offset = base - pool->base;
3724         /* Lookup in alloc list */
3725         LIST_FOREACH(entry, &pool->alloc_list, next) {
3726                 if (entry->base == pool_offset) {
3727                         valid_entry = entry;
3728                         LIST_REMOVE(entry, next);
3729                         break;
3730                 }
3731         }
3732
3733         /* Not find, return */
3734         if (valid_entry == NULL) {
3735                 PMD_DRV_LOG(ERR, "Failed to find entry");
3736                 return -EINVAL;
3737         }
3738
3739         /**
3740          * Found it, move it to free list  and try to merge.
3741          * In order to make merge easier, always sort it by qbase.
3742          * Find adjacent prev and last entries.
3743          */
3744         prev = next = NULL;
3745         LIST_FOREACH(entry, &pool->free_list, next) {
3746                 if (entry->base > valid_entry->base) {
3747                         next = entry;
3748                         break;
3749                 }
3750                 prev = entry;
3751         }
3752
3753         insert = 0;
3754         /* Try to merge with next one*/
3755         if (next != NULL) {
3756                 /* Merge with next one */
3757                 if (valid_entry->base + valid_entry->len == next->base) {
3758                         next->base = valid_entry->base;
3759                         next->len += valid_entry->len;
3760                         rte_free(valid_entry);
3761                         valid_entry = next;
3762                         insert = 1;
3763                 }
3764         }
3765
3766         if (prev != NULL) {
3767                 /* Merge with previous one */
3768                 if (prev->base + prev->len == valid_entry->base) {
3769                         prev->len += valid_entry->len;
3770                         /* If it merge with next one, remove next node */
3771                         if (insert == 1) {
3772                                 LIST_REMOVE(valid_entry, next);
3773                                 rte_free(valid_entry);
3774                         } else {
3775                                 rte_free(valid_entry);
3776                                 insert = 1;
3777                         }
3778                 }
3779         }
3780
3781         /* Not find any entry to merge, insert */
3782         if (insert == 0) {
3783                 if (prev != NULL)
3784                         LIST_INSERT_AFTER(prev, valid_entry, next);
3785                 else if (next != NULL)
3786                         LIST_INSERT_BEFORE(next, valid_entry, next);
3787                 else /* It's empty list, insert to head */
3788                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3789         }
3790
3791         pool->num_free += valid_entry->len;
3792         pool->num_alloc -= valid_entry->len;
3793
3794         return 0;
3795 }
3796
3797 static int
3798 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3799                        uint16_t num)
3800 {
3801         struct pool_entry *entry, *valid_entry;
3802
3803         if (pool == NULL || num == 0) {
3804                 PMD_DRV_LOG(ERR, "Invalid parameter");
3805                 return -EINVAL;
3806         }
3807
3808         if (pool->num_free < num) {
3809                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3810                             num, pool->num_free);
3811                 return -ENOMEM;
3812         }
3813
3814         valid_entry = NULL;
3815         /* Lookup  in free list and find most fit one */
3816         LIST_FOREACH(entry, &pool->free_list, next) {
3817                 if (entry->len >= num) {
3818                         /* Find best one */
3819                         if (entry->len == num) {
3820                                 valid_entry = entry;
3821                                 break;
3822                         }
3823                         if (valid_entry == NULL || valid_entry->len > entry->len)
3824                                 valid_entry = entry;
3825                 }
3826         }
3827
3828         /* Not find one to satisfy the request, return */
3829         if (valid_entry == NULL) {
3830                 PMD_DRV_LOG(ERR, "No valid entry found");
3831                 return -ENOMEM;
3832         }
3833         /**
3834          * The entry have equal queue number as requested,
3835          * remove it from alloc_list.
3836          */
3837         if (valid_entry->len == num) {
3838                 LIST_REMOVE(valid_entry, next);
3839         } else {
3840                 /**
3841                  * The entry have more numbers than requested,
3842                  * create a new entry for alloc_list and minus its
3843                  * queue base and number in free_list.
3844                  */
3845                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3846                 if (entry == NULL) {
3847                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3848                                     "resource pool");
3849                         return -ENOMEM;
3850                 }
3851                 entry->base = valid_entry->base;
3852                 entry->len = num;
3853                 valid_entry->base += num;
3854                 valid_entry->len -= num;
3855                 valid_entry = entry;
3856         }
3857
3858         /* Insert it into alloc list, not sorted */
3859         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3860
3861         pool->num_free -= valid_entry->len;
3862         pool->num_alloc += valid_entry->len;
3863
3864         return valid_entry->base + pool->base;
3865 }
3866
3867 /**
3868  * bitmap_is_subset - Check whether src2 is subset of src1
3869  **/
3870 static inline int
3871 bitmap_is_subset(uint8_t src1, uint8_t src2)
3872 {
3873         return !((src1 ^ src2) & src2);
3874 }
3875
3876 static enum i40e_status_code
3877 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3878 {
3879         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3880
3881         /* If DCB is not supported, only default TC is supported */
3882         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3883                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3884                 return I40E_NOT_SUPPORTED;
3885         }
3886
3887         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3888                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3889                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3890                             enabled_tcmap);
3891                 return I40E_NOT_SUPPORTED;
3892         }
3893         return I40E_SUCCESS;
3894 }
3895
3896 int
3897 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3898                                 struct i40e_vsi_vlan_pvid_info *info)
3899 {
3900         struct i40e_hw *hw;
3901         struct i40e_vsi_context ctxt;
3902         uint8_t vlan_flags = 0;
3903         int ret;
3904
3905         if (vsi == NULL || info == NULL) {
3906                 PMD_DRV_LOG(ERR, "invalid parameters");
3907                 return I40E_ERR_PARAM;
3908         }
3909
3910         if (info->on) {
3911                 vsi->info.pvid = info->config.pvid;
3912                 /**
3913                  * If insert pvid is enabled, only tagged pkts are
3914                  * allowed to be sent out.
3915                  */
3916                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3917                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3918         } else {
3919                 vsi->info.pvid = 0;
3920                 if (info->config.reject.tagged == 0)
3921                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3922
3923                 if (info->config.reject.untagged == 0)
3924                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3925         }
3926         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3927                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3928         vsi->info.port_vlan_flags |= vlan_flags;
3929         vsi->info.valid_sections =
3930                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3931         memset(&ctxt, 0, sizeof(ctxt));
3932         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3933         ctxt.seid = vsi->seid;
3934
3935         hw = I40E_VSI_TO_HW(vsi);
3936         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3937         if (ret != I40E_SUCCESS)
3938                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3939
3940         return ret;
3941 }
3942
3943 static int
3944 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3945 {
3946         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3947         int i, ret;
3948         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3949
3950         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3951         if (ret != I40E_SUCCESS)
3952                 return ret;
3953
3954         if (!vsi->seid) {
3955                 PMD_DRV_LOG(ERR, "seid not valid");
3956                 return -EINVAL;
3957         }
3958
3959         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3960         tc_bw_data.tc_valid_bits = enabled_tcmap;
3961         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3962                 tc_bw_data.tc_bw_credits[i] =
3963                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3964
3965         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3966         if (ret != I40E_SUCCESS) {
3967                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3968                 return ret;
3969         }
3970
3971         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3972                                         sizeof(vsi->info.qs_handle));
3973         return I40E_SUCCESS;
3974 }
3975
3976 static enum i40e_status_code
3977 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3978                                  struct i40e_aqc_vsi_properties_data *info,
3979                                  uint8_t enabled_tcmap)
3980 {
3981         enum i40e_status_code ret;
3982         int i, total_tc = 0;
3983         uint16_t qpnum_per_tc, bsf, qp_idx;
3984
3985         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3986         if (ret != I40E_SUCCESS)
3987                 return ret;
3988
3989         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3990                 if (enabled_tcmap & (1 << i))
3991                         total_tc++;
3992         vsi->enabled_tc = enabled_tcmap;
3993
3994         /* Number of queues per enabled TC */
3995         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3996         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3997         bsf = rte_bsf32(qpnum_per_tc);
3998
3999         /* Adjust the queue number to actual queues that can be applied */
4000         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4001                 vsi->nb_qps = qpnum_per_tc * total_tc;
4002
4003         /**
4004          * Configure TC and queue mapping parameters, for enabled TC,
4005          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4006          * default queue will serve it.
4007          */
4008         qp_idx = 0;
4009         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4010                 if (vsi->enabled_tc & (1 << i)) {
4011                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4012                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4013                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4014                         qp_idx += qpnum_per_tc;
4015                 } else
4016                         info->tc_mapping[i] = 0;
4017         }
4018
4019         /* Associate queue number with VSI */
4020         if (vsi->type == I40E_VSI_SRIOV) {
4021                 info->mapping_flags |=
4022                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4023                 for (i = 0; i < vsi->nb_qps; i++)
4024                         info->queue_mapping[i] =
4025                                 rte_cpu_to_le_16(vsi->base_queue + i);
4026         } else {
4027                 info->mapping_flags |=
4028                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4029                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4030         }
4031         info->valid_sections |=
4032                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4033
4034         return I40E_SUCCESS;
4035 }
4036
4037 static int
4038 i40e_veb_release(struct i40e_veb *veb)
4039 {
4040         struct i40e_vsi *vsi;
4041         struct i40e_hw *hw;
4042
4043         if (veb == NULL)
4044                 return -EINVAL;
4045
4046         if (!TAILQ_EMPTY(&veb->head)) {
4047                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4048                 return -EACCES;
4049         }
4050         /* associate_vsi field is NULL for floating VEB */
4051         if (veb->associate_vsi != NULL) {
4052                 vsi = veb->associate_vsi;
4053                 hw = I40E_VSI_TO_HW(vsi);
4054
4055                 vsi->uplink_seid = veb->uplink_seid;
4056                 vsi->veb = NULL;
4057         } else {
4058                 veb->associate_pf->main_vsi->floating_veb = NULL;
4059                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4060         }
4061
4062         i40e_aq_delete_element(hw, veb->seid, NULL);
4063         rte_free(veb);
4064         return I40E_SUCCESS;
4065 }
4066
4067 /* Setup a veb */
4068 static struct i40e_veb *
4069 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4070 {
4071         struct i40e_veb *veb;
4072         int ret;
4073         struct i40e_hw *hw;
4074
4075         if (pf == NULL) {
4076                 PMD_DRV_LOG(ERR,
4077                             "veb setup failed, associated PF shouldn't null");
4078                 return NULL;
4079         }
4080         hw = I40E_PF_TO_HW(pf);
4081
4082         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4083         if (!veb) {
4084                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4085                 goto fail;
4086         }
4087
4088         veb->associate_vsi = vsi;
4089         veb->associate_pf = pf;
4090         TAILQ_INIT(&veb->head);
4091         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4092
4093         /* create floating veb if vsi is NULL */
4094         if (vsi != NULL) {
4095                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4096                                       I40E_DEFAULT_TCMAP, false,
4097                                       &veb->seid, false, NULL);
4098         } else {
4099                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4100                                       true, &veb->seid, false, NULL);
4101         }
4102
4103         if (ret != I40E_SUCCESS) {
4104                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4105                             hw->aq.asq_last_status);
4106                 goto fail;
4107         }
4108
4109         /* get statistics index */
4110         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4111                                 &veb->stats_idx, NULL, NULL, NULL);
4112         if (ret != I40E_SUCCESS) {
4113                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4114                             hw->aq.asq_last_status);
4115                 goto fail;
4116         }
4117         /* Get VEB bandwidth, to be implemented */
4118         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4119         if (vsi)
4120                 vsi->uplink_seid = veb->seid;
4121
4122         return veb;
4123 fail:
4124         rte_free(veb);
4125         return NULL;
4126 }
4127
4128 int
4129 i40e_vsi_release(struct i40e_vsi *vsi)
4130 {
4131         struct i40e_pf *pf;
4132         struct i40e_hw *hw;
4133         struct i40e_vsi_list *vsi_list;
4134         void *temp;
4135         int ret;
4136         struct i40e_mac_filter *f;
4137         uint16_t user_param;
4138
4139         if (!vsi)
4140                 return I40E_SUCCESS;
4141
4142         if (!vsi->adapter)
4143                 return -EFAULT;
4144
4145         user_param = vsi->user_param;
4146
4147         pf = I40E_VSI_TO_PF(vsi);
4148         hw = I40E_VSI_TO_HW(vsi);
4149
4150         /* VSI has child to attach, release child first */
4151         if (vsi->veb) {
4152                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4153                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4154                                 return -1;
4155                 }
4156                 i40e_veb_release(vsi->veb);
4157         }
4158
4159         if (vsi->floating_veb) {
4160                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4161                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4162                                 return -1;
4163                 }
4164         }
4165
4166         /* Remove all macvlan filters of the VSI */
4167         i40e_vsi_remove_all_macvlan_filter(vsi);
4168         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4169                 rte_free(f);
4170
4171         if (vsi->type != I40E_VSI_MAIN &&
4172             ((vsi->type != I40E_VSI_SRIOV) ||
4173             !pf->floating_veb_list[user_param])) {
4174                 /* Remove vsi from parent's sibling list */
4175                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4176                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4177                         return I40E_ERR_PARAM;
4178                 }
4179                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4180                                 &vsi->sib_vsi_list, list);
4181
4182                 /* Remove all switch element of the VSI */
4183                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4184                 if (ret != I40E_SUCCESS)
4185                         PMD_DRV_LOG(ERR, "Failed to delete element");
4186         }
4187
4188         if ((vsi->type == I40E_VSI_SRIOV) &&
4189             pf->floating_veb_list[user_param]) {
4190                 /* Remove vsi from parent's sibling list */
4191                 if (vsi->parent_vsi == NULL ||
4192                     vsi->parent_vsi->floating_veb == NULL) {
4193                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4194                         return I40E_ERR_PARAM;
4195                 }
4196                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4197                              &vsi->sib_vsi_list, list);
4198
4199                 /* Remove all switch element of the VSI */
4200                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4201                 if (ret != I40E_SUCCESS)
4202                         PMD_DRV_LOG(ERR, "Failed to delete element");
4203         }
4204
4205         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4206
4207         if (vsi->type != I40E_VSI_SRIOV)
4208                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4209         rte_free(vsi);
4210
4211         return I40E_SUCCESS;
4212 }
4213
4214 static int
4215 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4216 {
4217         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4218         struct i40e_aqc_remove_macvlan_element_data def_filter;
4219         struct i40e_mac_filter_info filter;
4220         int ret;
4221
4222         if (vsi->type != I40E_VSI_MAIN)
4223                 return I40E_ERR_CONFIG;
4224         memset(&def_filter, 0, sizeof(def_filter));
4225         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4226                                         ETH_ADDR_LEN);
4227         def_filter.vlan_tag = 0;
4228         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4229                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4230         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4231         if (ret != I40E_SUCCESS) {
4232                 struct i40e_mac_filter *f;
4233                 struct ether_addr *mac;
4234
4235                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4236                             "macvlan filter");
4237                 /* It needs to add the permanent mac into mac list */
4238                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4239                 if (f == NULL) {
4240                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4241                         return I40E_ERR_NO_MEMORY;
4242                 }
4243                 mac = &f->mac_info.mac_addr;
4244                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4245                                 ETH_ADDR_LEN);
4246                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4247                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4248                 vsi->mac_num++;
4249
4250                 return ret;
4251         }
4252         (void)rte_memcpy(&filter.mac_addr,
4253                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4254         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4255         return i40e_vsi_add_mac(vsi, &filter);
4256 }
4257
4258 /*
4259  * i40e_vsi_get_bw_config - Query VSI BW Information
4260  * @vsi: the VSI to be queried
4261  *
4262  * Returns 0 on success, negative value on failure
4263  */
4264 static enum i40e_status_code
4265 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4266 {
4267         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4268         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4269         struct i40e_hw *hw = &vsi->adapter->hw;
4270         i40e_status ret;
4271         int i;
4272         uint32_t bw_max;
4273
4274         memset(&bw_config, 0, sizeof(bw_config));
4275         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4276         if (ret != I40E_SUCCESS) {
4277                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4278                             hw->aq.asq_last_status);
4279                 return ret;
4280         }
4281
4282         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4283         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4284                                         &ets_sla_config, NULL);
4285         if (ret != I40E_SUCCESS) {
4286                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4287                             "configuration %u", hw->aq.asq_last_status);
4288                 return ret;
4289         }
4290
4291         /* store and print out BW info */
4292         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4293         vsi->bw_info.bw_max = bw_config.max_bw;
4294         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4295         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4296         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4297                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4298                      I40E_16_BIT_WIDTH);
4299         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4300                 vsi->bw_info.bw_ets_share_credits[i] =
4301                                 ets_sla_config.share_credits[i];
4302                 vsi->bw_info.bw_ets_credits[i] =
4303                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4304                 /* 4 bits per TC, 4th bit is reserved */
4305                 vsi->bw_info.bw_ets_max[i] =
4306                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4307                                   RTE_LEN2MASK(3, uint8_t));
4308                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4309                             vsi->bw_info.bw_ets_share_credits[i]);
4310                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4311                             vsi->bw_info.bw_ets_credits[i]);
4312                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4313                             vsi->bw_info.bw_ets_max[i]);
4314         }
4315
4316         return I40E_SUCCESS;
4317 }
4318
4319 /* i40e_enable_pf_lb
4320  * @pf: pointer to the pf structure
4321  *
4322  * allow loopback on pf
4323  */
4324 static inline void
4325 i40e_enable_pf_lb(struct i40e_pf *pf)
4326 {
4327         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4328         struct i40e_vsi_context ctxt;
4329         int ret;
4330
4331         /* Use the FW API if FW >= v5.0 */
4332         if (hw->aq.fw_maj_ver < 5) {
4333                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4334                 return;
4335         }
4336
4337         memset(&ctxt, 0, sizeof(ctxt));
4338         ctxt.seid = pf->main_vsi_seid;
4339         ctxt.pf_num = hw->pf_id;
4340         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4341         if (ret) {
4342                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4343                             ret, hw->aq.asq_last_status);
4344                 return;
4345         }
4346         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4347         ctxt.info.valid_sections =
4348                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4349         ctxt.info.switch_id |=
4350                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4351
4352         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4353         if (ret)
4354                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4355                             hw->aq.asq_last_status);
4356 }
4357
4358 /* Setup a VSI */
4359 struct i40e_vsi *
4360 i40e_vsi_setup(struct i40e_pf *pf,
4361                enum i40e_vsi_type type,
4362                struct i40e_vsi *uplink_vsi,
4363                uint16_t user_param)
4364 {
4365         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4366         struct i40e_vsi *vsi;
4367         struct i40e_mac_filter_info filter;
4368         int ret;
4369         struct i40e_vsi_context ctxt;
4370         struct ether_addr broadcast =
4371                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4372
4373         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4374             uplink_vsi == NULL) {
4375                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4376                             "VSI link shouldn't be NULL");
4377                 return NULL;
4378         }
4379
4380         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4381                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4382                             "uplink VSI should be NULL");
4383                 return NULL;
4384         }
4385
4386         /* two situations
4387          * 1.type is not MAIN and uplink vsi is not NULL
4388          * If uplink vsi didn't setup VEB, create one first under veb field
4389          * 2.type is SRIOV and the uplink is NULL
4390          * If floating VEB is NULL, create one veb under floating veb field
4391          */
4392
4393         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4394             uplink_vsi->veb == NULL) {
4395                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4396
4397                 if (uplink_vsi->veb == NULL) {
4398                         PMD_DRV_LOG(ERR, "VEB setup failed");
4399                         return NULL;
4400                 }
4401                 /* set ALLOWLOOPBACk on pf, when veb is created */
4402                 i40e_enable_pf_lb(pf);
4403         }
4404
4405         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4406             pf->main_vsi->floating_veb == NULL) {
4407                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4408
4409                 if (pf->main_vsi->floating_veb == NULL) {
4410                         PMD_DRV_LOG(ERR, "VEB setup failed");
4411                         return NULL;
4412                 }
4413         }
4414
4415         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4416         if (!vsi) {
4417                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4418                 return NULL;
4419         }
4420         TAILQ_INIT(&vsi->mac_list);
4421         vsi->type = type;
4422         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4423         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4424         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4425         vsi->user_param = user_param;
4426         /* Allocate queues */
4427         switch (vsi->type) {
4428         case I40E_VSI_MAIN  :
4429                 vsi->nb_qps = pf->lan_nb_qps;
4430                 break;
4431         case I40E_VSI_SRIOV :
4432                 vsi->nb_qps = pf->vf_nb_qps;
4433                 break;
4434         case I40E_VSI_VMDQ2:
4435                 vsi->nb_qps = pf->vmdq_nb_qps;
4436                 break;
4437         case I40E_VSI_FDIR:
4438                 vsi->nb_qps = pf->fdir_nb_qps;
4439                 break;
4440         default:
4441                 goto fail_mem;
4442         }
4443         /*
4444          * The filter status descriptor is reported in rx queue 0,
4445          * while the tx queue for fdir filter programming has no
4446          * such constraints, can be non-zero queues.
4447          * To simplify it, choose FDIR vsi use queue 0 pair.
4448          * To make sure it will use queue 0 pair, queue allocation
4449          * need be done before this function is called
4450          */
4451         if (type != I40E_VSI_FDIR) {
4452                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4453                         if (ret < 0) {
4454                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4455                                                 vsi->seid, ret);
4456                                 goto fail_mem;
4457                         }
4458                         vsi->base_queue = ret;
4459         } else
4460                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4461
4462         /* VF has MSIX interrupt in VF range, don't allocate here */
4463         if (type == I40E_VSI_MAIN) {
4464                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4465                                           RTE_MIN(vsi->nb_qps,
4466                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4467                 if (ret < 0) {
4468                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4469                                     vsi->seid, ret);
4470                         goto fail_queue_alloc;
4471                 }
4472                 vsi->msix_intr = ret;
4473                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4474         } else if (type != I40E_VSI_SRIOV) {
4475                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4476                 if (ret < 0) {
4477                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4478                         goto fail_queue_alloc;
4479                 }
4480                 vsi->msix_intr = ret;
4481                 vsi->nb_msix = 1;
4482         } else {
4483                 vsi->msix_intr = 0;
4484                 vsi->nb_msix = 0;
4485         }
4486
4487         /* Add VSI */
4488         if (type == I40E_VSI_MAIN) {
4489                 /* For main VSI, no need to add since it's default one */
4490                 vsi->uplink_seid = pf->mac_seid;
4491                 vsi->seid = pf->main_vsi_seid;
4492                 /* Bind queues with specific MSIX interrupt */
4493                 /**
4494                  * Needs 2 interrupt at least, one for misc cause which will
4495                  * enabled from OS side, Another for queues binding the
4496                  * interrupt from device side only.
4497                  */
4498
4499                 /* Get default VSI parameters from hardware */
4500                 memset(&ctxt, 0, sizeof(ctxt));
4501                 ctxt.seid = vsi->seid;
4502                 ctxt.pf_num = hw->pf_id;
4503                 ctxt.uplink_seid = vsi->uplink_seid;
4504                 ctxt.vf_num = 0;
4505                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4506                 if (ret != I40E_SUCCESS) {
4507                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4508                         goto fail_msix_alloc;
4509                 }
4510                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4511                         sizeof(struct i40e_aqc_vsi_properties_data));
4512                 vsi->vsi_id = ctxt.vsi_number;
4513                 vsi->info.valid_sections = 0;
4514
4515                 /* Configure tc, enabled TC0 only */
4516                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4517                         I40E_SUCCESS) {
4518                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4519                         goto fail_msix_alloc;
4520                 }
4521
4522                 /* TC, queue mapping */
4523                 memset(&ctxt, 0, sizeof(ctxt));
4524                 vsi->info.valid_sections |=
4525                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4526                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4527                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4528                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4529                         sizeof(struct i40e_aqc_vsi_properties_data));
4530                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4531                                                 I40E_DEFAULT_TCMAP);
4532                 if (ret != I40E_SUCCESS) {
4533                         PMD_DRV_LOG(ERR, "Failed to configure "
4534                                     "TC queue mapping");
4535                         goto fail_msix_alloc;
4536                 }
4537                 ctxt.seid = vsi->seid;
4538                 ctxt.pf_num = hw->pf_id;
4539                 ctxt.uplink_seid = vsi->uplink_seid;
4540                 ctxt.vf_num = 0;
4541
4542                 /* Update VSI parameters */
4543                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4544                 if (ret != I40E_SUCCESS) {
4545                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4546                         goto fail_msix_alloc;
4547                 }
4548
4549                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4550                                                 sizeof(vsi->info.tc_mapping));
4551                 (void)rte_memcpy(&vsi->info.queue_mapping,
4552                                 &ctxt.info.queue_mapping,
4553                         sizeof(vsi->info.queue_mapping));
4554                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4555                 vsi->info.valid_sections = 0;
4556
4557                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4558                                 ETH_ADDR_LEN);
4559
4560                 /**
4561                  * Updating default filter settings are necessary to prevent
4562                  * reception of tagged packets.
4563                  * Some old firmware configurations load a default macvlan
4564                  * filter which accepts both tagged and untagged packets.
4565                  * The updating is to use a normal filter instead if needed.
4566                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4567                  * The firmware with correct configurations load the default
4568                  * macvlan filter which is expected and cannot be removed.
4569                  */
4570                 i40e_update_default_filter_setting(vsi);
4571                 i40e_config_qinq(hw, vsi);
4572         } else if (type == I40E_VSI_SRIOV) {
4573                 memset(&ctxt, 0, sizeof(ctxt));
4574                 /**
4575                  * For other VSI, the uplink_seid equals to uplink VSI's
4576                  * uplink_seid since they share same VEB
4577                  */
4578                 if (uplink_vsi == NULL)
4579                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4580                 else
4581                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4582                 ctxt.pf_num = hw->pf_id;
4583                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4584                 ctxt.uplink_seid = vsi->uplink_seid;
4585                 ctxt.connection_type = 0x1;
4586                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4587
4588                 /* Use the VEB configuration if FW >= v5.0 */
4589                 if (hw->aq.fw_maj_ver >= 5) {
4590                         /* Configure switch ID */
4591                         ctxt.info.valid_sections |=
4592                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4593                         ctxt.info.switch_id =
4594                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4595                 }
4596
4597                 /* Configure port/vlan */
4598                 ctxt.info.valid_sections |=
4599                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4600                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4601                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4602                                                 I40E_DEFAULT_TCMAP);
4603                 if (ret != I40E_SUCCESS) {
4604                         PMD_DRV_LOG(ERR, "Failed to configure "
4605                                     "TC queue mapping");
4606                         goto fail_msix_alloc;
4607                 }
4608                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4609                 ctxt.info.valid_sections |=
4610                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4611                 /**
4612                  * Since VSI is not created yet, only configure parameter,
4613                  * will add vsi below.
4614                  */
4615
4616                 i40e_config_qinq(hw, vsi);
4617         } else if (type == I40E_VSI_VMDQ2) {
4618                 memset(&ctxt, 0, sizeof(ctxt));
4619                 /*
4620                  * For other VSI, the uplink_seid equals to uplink VSI's
4621                  * uplink_seid since they share same VEB
4622                  */
4623                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4624                 ctxt.pf_num = hw->pf_id;
4625                 ctxt.vf_num = 0;
4626                 ctxt.uplink_seid = vsi->uplink_seid;
4627                 ctxt.connection_type = 0x1;
4628                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4629
4630                 ctxt.info.valid_sections |=
4631                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4632                 /* user_param carries flag to enable loop back */
4633                 if (user_param) {
4634                         ctxt.info.switch_id =
4635                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4636                         ctxt.info.switch_id |=
4637                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4638                 }
4639
4640                 /* Configure port/vlan */
4641                 ctxt.info.valid_sections |=
4642                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4643                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4644                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4645                                                 I40E_DEFAULT_TCMAP);
4646                 if (ret != I40E_SUCCESS) {
4647                         PMD_DRV_LOG(ERR, "Failed to configure "
4648                                         "TC queue mapping");
4649                         goto fail_msix_alloc;
4650                 }
4651                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4652                 ctxt.info.valid_sections |=
4653                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4654         } else if (type == I40E_VSI_FDIR) {
4655                 memset(&ctxt, 0, sizeof(ctxt));
4656                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4657                 ctxt.pf_num = hw->pf_id;
4658                 ctxt.vf_num = 0;
4659                 ctxt.uplink_seid = vsi->uplink_seid;
4660                 ctxt.connection_type = 0x1;     /* regular data port */
4661                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4662                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4663                                                 I40E_DEFAULT_TCMAP);
4664                 if (ret != I40E_SUCCESS) {
4665                         PMD_DRV_LOG(ERR, "Failed to configure "
4666                                         "TC queue mapping.");
4667                         goto fail_msix_alloc;
4668                 }
4669                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4670                 ctxt.info.valid_sections |=
4671                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4672         } else {
4673                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4674                 goto fail_msix_alloc;
4675         }
4676
4677         if (vsi->type != I40E_VSI_MAIN) {
4678                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4679                 if (ret != I40E_SUCCESS) {
4680                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4681                                     hw->aq.asq_last_status);
4682                         goto fail_msix_alloc;
4683                 }
4684                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4685                 vsi->info.valid_sections = 0;
4686                 vsi->seid = ctxt.seid;
4687                 vsi->vsi_id = ctxt.vsi_number;
4688                 vsi->sib_vsi_list.vsi = vsi;
4689                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4690                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4691                                           &vsi->sib_vsi_list, list);
4692                 } else {
4693                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4694                                           &vsi->sib_vsi_list, list);
4695                 }
4696         }
4697
4698         /* MAC/VLAN configuration */
4699         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4700         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4701
4702         ret = i40e_vsi_add_mac(vsi, &filter);
4703         if (ret != I40E_SUCCESS) {
4704                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4705                 goto fail_msix_alloc;
4706         }
4707
4708         /* Get VSI BW information */
4709         i40e_vsi_get_bw_config(vsi);
4710         return vsi;
4711 fail_msix_alloc:
4712         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4713 fail_queue_alloc:
4714         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4715 fail_mem:
4716         rte_free(vsi);
4717         return NULL;
4718 }
4719
4720 /* Configure vlan filter on or off */
4721 int
4722 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4723 {
4724         int i, num;
4725         struct i40e_mac_filter *f;
4726         void *temp;
4727         struct i40e_mac_filter_info *mac_filter;
4728         enum rte_mac_filter_type desired_filter;
4729         int ret = I40E_SUCCESS;
4730
4731         if (on) {
4732                 /* Filter to match MAC and VLAN */
4733                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4734         } else {
4735                 /* Filter to match only MAC */
4736                 desired_filter = RTE_MAC_PERFECT_MATCH;
4737         }
4738
4739         num = vsi->mac_num;
4740
4741         mac_filter = rte_zmalloc("mac_filter_info_data",
4742                                  num * sizeof(*mac_filter), 0);
4743         if (mac_filter == NULL) {
4744                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4745                 return I40E_ERR_NO_MEMORY;
4746         }
4747
4748         i = 0;
4749
4750         /* Remove all existing mac */
4751         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4752                 mac_filter[i] = f->mac_info;
4753                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4754                 if (ret) {
4755                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4756                                     on ? "enable" : "disable");
4757                         goto DONE;
4758                 }
4759                 i++;
4760         }
4761
4762         /* Override with new filter */
4763         for (i = 0; i < num; i++) {
4764                 mac_filter[i].filter_type = desired_filter;
4765                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4766                 if (ret) {
4767                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4768                                     on ? "enable" : "disable");
4769                         goto DONE;
4770                 }
4771         }
4772
4773 DONE:
4774         rte_free(mac_filter);
4775         return ret;
4776 }
4777
4778 /* Configure vlan stripping on or off */
4779 int
4780 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4781 {
4782         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4783         struct i40e_vsi_context ctxt;
4784         uint8_t vlan_flags;
4785         int ret = I40E_SUCCESS;
4786
4787         /* Check if it has been already on or off */
4788         if (vsi->info.valid_sections &
4789                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4790                 if (on) {
4791                         if ((vsi->info.port_vlan_flags &
4792                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4793                                 return 0; /* already on */
4794                 } else {
4795                         if ((vsi->info.port_vlan_flags &
4796                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4797                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4798                                 return 0; /* already off */
4799                 }
4800         }
4801
4802         if (on)
4803                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4804         else
4805                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4806         vsi->info.valid_sections =
4807                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4808         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4809         vsi->info.port_vlan_flags |= vlan_flags;
4810         ctxt.seid = vsi->seid;
4811         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4812         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4813         if (ret)
4814                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4815                             on ? "enable" : "disable");
4816
4817         return ret;
4818 }
4819
4820 static int
4821 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4822 {
4823         struct rte_eth_dev_data *data = dev->data;
4824         int ret;
4825         int mask = 0;
4826
4827         /* Apply vlan offload setting */
4828         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4829         i40e_vlan_offload_set(dev, mask);
4830
4831         /* Apply double-vlan setting, not implemented yet */
4832
4833         /* Apply pvid setting */
4834         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4835                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4836         if (ret)
4837                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4838
4839         return ret;
4840 }
4841
4842 static int
4843 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4844 {
4845         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4846
4847         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4848 }
4849
4850 static int
4851 i40e_update_flow_control(struct i40e_hw *hw)
4852 {
4853 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4854         struct i40e_link_status link_status;
4855         uint32_t rxfc = 0, txfc = 0, reg;
4856         uint8_t an_info;
4857         int ret;
4858
4859         memset(&link_status, 0, sizeof(link_status));
4860         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4861         if (ret != I40E_SUCCESS) {
4862                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4863                 goto write_reg; /* Disable flow control */
4864         }
4865
4866         an_info = hw->phy.link_info.an_info;
4867         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4868                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4869                 ret = I40E_ERR_NOT_READY;
4870                 goto write_reg; /* Disable flow control */
4871         }
4872         /**
4873          * If link auto negotiation is enabled, flow control needs to
4874          * be configured according to it
4875          */
4876         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4877         case I40E_LINK_PAUSE_RXTX:
4878                 rxfc = 1;
4879                 txfc = 1;
4880                 hw->fc.current_mode = I40E_FC_FULL;
4881                 break;
4882         case I40E_AQ_LINK_PAUSE_RX:
4883                 rxfc = 1;
4884                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4885                 break;
4886         case I40E_AQ_LINK_PAUSE_TX:
4887                 txfc = 1;
4888                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4889                 break;
4890         default:
4891                 hw->fc.current_mode = I40E_FC_NONE;
4892                 break;
4893         }
4894
4895 write_reg:
4896         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4897                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4898         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4899         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4900         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4901         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4902
4903         return ret;
4904 }
4905
4906 /* PF setup */
4907 static int
4908 i40e_pf_setup(struct i40e_pf *pf)
4909 {
4910         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4911         struct i40e_filter_control_settings settings;
4912         struct i40e_vsi *vsi;
4913         int ret;
4914
4915         /* Clear all stats counters */
4916         pf->offset_loaded = FALSE;
4917         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4918         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4919
4920         ret = i40e_pf_get_switch_config(pf);
4921         if (ret != I40E_SUCCESS) {
4922                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4923                 return ret;
4924         }
4925         if (pf->flags & I40E_FLAG_FDIR) {
4926                 /* make queue allocated first, let FDIR use queue pair 0*/
4927                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4928                 if (ret != I40E_FDIR_QUEUE_ID) {
4929                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4930                                     " ret =%d", ret);
4931                         pf->flags &= ~I40E_FLAG_FDIR;
4932                 }
4933         }
4934         /*  main VSI setup */
4935         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4936         if (!vsi) {
4937                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4938                 return I40E_ERR_NOT_READY;
4939         }
4940         pf->main_vsi = vsi;
4941
4942         /* Configure filter control */
4943         memset(&settings, 0, sizeof(settings));
4944         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4945                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4946         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4947                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4948         else {
4949                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4950                                                 hw->func_caps.rss_table_size);
4951                 return I40E_ERR_PARAM;
4952         }
4953         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4954                         "size: %u\n", hw->func_caps.rss_table_size);
4955         pf->hash_lut_size = hw->func_caps.rss_table_size;
4956
4957         /* Enable ethtype and macvlan filters */
4958         settings.enable_ethtype = TRUE;
4959         settings.enable_macvlan = TRUE;
4960         ret = i40e_set_filter_control(hw, &settings);
4961         if (ret)
4962                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4963                                                                 ret);
4964
4965         /* Update flow control according to the auto negotiation */
4966         i40e_update_flow_control(hw);
4967
4968         return I40E_SUCCESS;
4969 }
4970
4971 int
4972 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4973 {
4974         uint32_t reg;
4975         uint16_t j;
4976
4977         /**
4978          * Set or clear TX Queue Disable flags,
4979          * which is required by hardware.
4980          */
4981         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4982         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4983
4984         /* Wait until the request is finished */
4985         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4986                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4987                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4988                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4989                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4990                                                         & 0x1))) {
4991                         break;
4992                 }
4993         }
4994         if (on) {
4995                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4996                         return I40E_SUCCESS; /* already on, skip next steps */
4997
4998                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4999                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5000         } else {
5001                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5002                         return I40E_SUCCESS; /* already off, skip next steps */
5003                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5004         }
5005         /* Write the register */
5006         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5007         /* Check the result */
5008         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5009                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5010                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5011                 if (on) {
5012                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5013                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5014                                 break;
5015                 } else {
5016                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5017                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5018                                 break;
5019                 }
5020         }
5021         /* Check if it is timeout */
5022         if (j >= I40E_CHK_Q_ENA_COUNT) {
5023                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5024                             (on ? "enable" : "disable"), q_idx);
5025                 return I40E_ERR_TIMEOUT;
5026         }
5027
5028         return I40E_SUCCESS;
5029 }
5030
5031 /* Swith on or off the tx queues */
5032 static int
5033 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5034 {
5035         struct rte_eth_dev_data *dev_data = pf->dev_data;
5036         struct i40e_tx_queue *txq;
5037         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5038         uint16_t i;
5039         int ret;
5040
5041         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5042                 txq = dev_data->tx_queues[i];
5043                 /* Don't operate the queue if not configured or
5044                  * if starting only per queue */
5045                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5046                         continue;
5047                 if (on)
5048                         ret = i40e_dev_tx_queue_start(dev, i);
5049                 else
5050                         ret = i40e_dev_tx_queue_stop(dev, i);
5051                 if ( ret != I40E_SUCCESS)
5052                         return ret;
5053         }
5054
5055         return I40E_SUCCESS;
5056 }
5057
5058 int
5059 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5060 {
5061         uint32_t reg;
5062         uint16_t j;
5063
5064         /* Wait until the request is finished */
5065         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5066                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5067                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5068                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5069                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5070                         break;
5071         }
5072
5073         if (on) {
5074                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5075                         return I40E_SUCCESS; /* Already on, skip next steps */
5076                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5077         } else {
5078                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5079                         return I40E_SUCCESS; /* Already off, skip next steps */
5080                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5081         }
5082
5083         /* Write the register */
5084         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5085         /* Check the result */
5086         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5087                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5088                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5089                 if (on) {
5090                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5091                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5092                                 break;
5093                 } else {
5094                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5095                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5096                                 break;
5097                 }
5098         }
5099
5100         /* Check if it is timeout */
5101         if (j >= I40E_CHK_Q_ENA_COUNT) {
5102                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5103                             (on ? "enable" : "disable"), q_idx);
5104                 return I40E_ERR_TIMEOUT;
5105         }
5106
5107         return I40E_SUCCESS;
5108 }
5109 /* Switch on or off the rx queues */
5110 static int
5111 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5112 {
5113         struct rte_eth_dev_data *dev_data = pf->dev_data;
5114         struct i40e_rx_queue *rxq;
5115         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5116         uint16_t i;
5117         int ret;
5118
5119         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5120                 rxq = dev_data->rx_queues[i];
5121                 /* Don't operate the queue if not configured or
5122                  * if starting only per queue */
5123                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5124                         continue;
5125                 if (on)
5126                         ret = i40e_dev_rx_queue_start(dev, i);
5127                 else
5128                         ret = i40e_dev_rx_queue_stop(dev, i);
5129                 if (ret != I40E_SUCCESS)
5130                         return ret;
5131         }
5132
5133         return I40E_SUCCESS;
5134 }
5135
5136 /* Switch on or off all the rx/tx queues */
5137 int
5138 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5139 {
5140         int ret;
5141
5142         if (on) {
5143                 /* enable rx queues before enabling tx queues */
5144                 ret = i40e_dev_switch_rx_queues(pf, on);
5145                 if (ret) {
5146                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5147                         return ret;
5148                 }
5149                 ret = i40e_dev_switch_tx_queues(pf, on);
5150         } else {
5151                 /* Stop tx queues before stopping rx queues */
5152                 ret = i40e_dev_switch_tx_queues(pf, on);
5153                 if (ret) {
5154                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5155                         return ret;
5156                 }
5157                 ret = i40e_dev_switch_rx_queues(pf, on);
5158         }
5159
5160         return ret;
5161 }
5162
5163 /* Initialize VSI for TX */
5164 static int
5165 i40e_dev_tx_init(struct i40e_pf *pf)
5166 {
5167         struct rte_eth_dev_data *data = pf->dev_data;
5168         uint16_t i;
5169         uint32_t ret = I40E_SUCCESS;
5170         struct i40e_tx_queue *txq;
5171
5172         for (i = 0; i < data->nb_tx_queues; i++) {
5173                 txq = data->tx_queues[i];
5174                 if (!txq || !txq->q_set)
5175                         continue;
5176                 ret = i40e_tx_queue_init(txq);
5177                 if (ret != I40E_SUCCESS)
5178                         break;
5179         }
5180         if (ret == I40E_SUCCESS)
5181                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5182                                      ->eth_dev);
5183
5184         return ret;
5185 }
5186
5187 /* Initialize VSI for RX */
5188 static int
5189 i40e_dev_rx_init(struct i40e_pf *pf)
5190 {
5191         struct rte_eth_dev_data *data = pf->dev_data;
5192         int ret = I40E_SUCCESS;
5193         uint16_t i;
5194         struct i40e_rx_queue *rxq;
5195
5196         i40e_pf_config_mq_rx(pf);
5197         for (i = 0; i < data->nb_rx_queues; i++) {
5198                 rxq = data->rx_queues[i];
5199                 if (!rxq || !rxq->q_set)
5200                         continue;
5201
5202                 ret = i40e_rx_queue_init(rxq);
5203                 if (ret != I40E_SUCCESS) {
5204                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5205                                     "initialization");
5206                         break;
5207                 }
5208         }
5209         if (ret == I40E_SUCCESS)
5210                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5211                                      ->eth_dev);
5212
5213         return ret;
5214 }
5215
5216 static int
5217 i40e_dev_rxtx_init(struct i40e_pf *pf)
5218 {
5219         int err;
5220
5221         err = i40e_dev_tx_init(pf);
5222         if (err) {
5223                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5224                 return err;
5225         }
5226         err = i40e_dev_rx_init(pf);
5227         if (err) {
5228                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5229                 return err;
5230         }
5231
5232         return err;
5233 }
5234
5235 static int
5236 i40e_vmdq_setup(struct rte_eth_dev *dev)
5237 {
5238         struct rte_eth_conf *conf = &dev->data->dev_conf;
5239         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5240         int i, err, conf_vsis, j, loop;
5241         struct i40e_vsi *vsi;
5242         struct i40e_vmdq_info *vmdq_info;
5243         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5244         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5245
5246         /*
5247          * Disable interrupt to avoid message from VF. Furthermore, it will
5248          * avoid race condition in VSI creation/destroy.
5249          */
5250         i40e_pf_disable_irq0(hw);
5251
5252         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5253                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5254                 return -ENOTSUP;
5255         }
5256
5257         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5258         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5259                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5260                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5261                         pf->max_nb_vmdq_vsi);
5262                 return -ENOTSUP;
5263         }
5264
5265         if (pf->vmdq != NULL) {
5266                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5267                 return 0;
5268         }
5269
5270         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5271                                 sizeof(*vmdq_info) * conf_vsis, 0);
5272
5273         if (pf->vmdq == NULL) {
5274                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5275                 return -ENOMEM;
5276         }
5277
5278         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5279
5280         /* Create VMDQ VSI */
5281         for (i = 0; i < conf_vsis; i++) {
5282                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5283                                 vmdq_conf->enable_loop_back);
5284                 if (vsi == NULL) {
5285                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5286                         err = -1;
5287                         goto err_vsi_setup;
5288                 }
5289                 vmdq_info = &pf->vmdq[i];
5290                 vmdq_info->pf = pf;
5291                 vmdq_info->vsi = vsi;
5292         }
5293         pf->nb_cfg_vmdq_vsi = conf_vsis;
5294
5295         /* Configure Vlan */
5296         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5297         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5298                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5299                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5300                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5301                                         vmdq_conf->pool_map[i].vlan_id, j);
5302
5303                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5304                                                 vmdq_conf->pool_map[i].vlan_id);
5305                                 if (err) {
5306                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5307                                         err = -1;
5308                                         goto err_vsi_setup;
5309                                 }
5310                         }
5311                 }
5312         }
5313
5314         i40e_pf_enable_irq0(hw);
5315
5316         return 0;
5317
5318 err_vsi_setup:
5319         for (i = 0; i < conf_vsis; i++)
5320                 if (pf->vmdq[i].vsi == NULL)
5321                         break;
5322                 else
5323                         i40e_vsi_release(pf->vmdq[i].vsi);
5324
5325         rte_free(pf->vmdq);
5326         pf->vmdq = NULL;
5327         i40e_pf_enable_irq0(hw);
5328         return err;
5329 }
5330
5331 static void
5332 i40e_stat_update_32(struct i40e_hw *hw,
5333                    uint32_t reg,
5334                    bool offset_loaded,
5335                    uint64_t *offset,
5336                    uint64_t *stat)
5337 {
5338         uint64_t new_data;
5339
5340         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5341         if (!offset_loaded)
5342                 *offset = new_data;
5343
5344         if (new_data >= *offset)
5345                 *stat = (uint64_t)(new_data - *offset);
5346         else
5347                 *stat = (uint64_t)((new_data +
5348                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5349 }
5350
5351 static void
5352 i40e_stat_update_48(struct i40e_hw *hw,
5353                    uint32_t hireg,
5354                    uint32_t loreg,
5355                    bool offset_loaded,
5356                    uint64_t *offset,
5357                    uint64_t *stat)
5358 {
5359         uint64_t new_data;
5360
5361         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5362         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5363                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5364
5365         if (!offset_loaded)
5366                 *offset = new_data;
5367
5368         if (new_data >= *offset)
5369                 *stat = new_data - *offset;
5370         else
5371                 *stat = (uint64_t)((new_data +
5372                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5373
5374         *stat &= I40E_48_BIT_MASK;
5375 }
5376
5377 /* Disable IRQ0 */
5378 void
5379 i40e_pf_disable_irq0(struct i40e_hw *hw)
5380 {
5381         /* Disable all interrupt types */
5382         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5383         I40E_WRITE_FLUSH(hw);
5384 }
5385
5386 /* Enable IRQ0 */
5387 void
5388 i40e_pf_enable_irq0(struct i40e_hw *hw)
5389 {
5390         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5391                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5392                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5393                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5394         I40E_WRITE_FLUSH(hw);
5395 }
5396
5397 static void
5398 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5399 {
5400         /* read pending request and disable first */
5401         i40e_pf_disable_irq0(hw);
5402         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5403         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5404                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5405
5406         if (no_queue)
5407                 /* Link no queues with irq0 */
5408                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5409                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5410 }
5411
5412 static void
5413 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5414 {
5415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5416         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5417         int i;
5418         uint16_t abs_vf_id;
5419         uint32_t index, offset, val;
5420
5421         if (!pf->vfs)
5422                 return;
5423         /**
5424          * Try to find which VF trigger a reset, use absolute VF id to access
5425          * since the reg is global register.
5426          */
5427         for (i = 0; i < pf->vf_num; i++) {
5428                 abs_vf_id = hw->func_caps.vf_base_id + i;
5429                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5430                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5431                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5432                 /* VFR event occured */
5433                 if (val & (0x1 << offset)) {
5434                         int ret;
5435
5436                         /* Clear the event first */
5437                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5438                                                         (0x1 << offset));
5439                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5440                         /**
5441                          * Only notify a VF reset event occured,
5442                          * don't trigger another SW reset
5443                          */
5444                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5445                         if (ret != I40E_SUCCESS)
5446                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5447                 }
5448         }
5449 }
5450
5451 static void
5452 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5453 {
5454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5455         struct i40e_virtchnl_pf_event event;
5456         int i;
5457
5458         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5459         event.event_data.link_event.link_status =
5460                 dev->data->dev_link.link_status;
5461         event.event_data.link_event.link_speed =
5462                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5463
5464         for (i = 0; i < pf->vf_num; i++)
5465                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5466                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5467 }
5468
5469 static void
5470 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5471 {
5472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5473         struct i40e_arq_event_info info;
5474         uint16_t pending, opcode;
5475         int ret;
5476
5477         info.buf_len = I40E_AQ_BUF_SZ;
5478         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5479         if (!info.msg_buf) {
5480                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5481                 return;
5482         }
5483
5484         pending = 1;
5485         while (pending) {
5486                 ret = i40e_clean_arq_element(hw, &info, &pending);
5487
5488                 if (ret != I40E_SUCCESS) {
5489                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5490                                     "aq_err: %u", hw->aq.asq_last_status);
5491                         break;
5492                 }
5493                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5494
5495                 switch (opcode) {
5496                 case i40e_aqc_opc_send_msg_to_pf:
5497                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5498                         i40e_pf_host_handle_vf_msg(dev,
5499                                         rte_le_to_cpu_16(info.desc.retval),
5500                                         rte_le_to_cpu_32(info.desc.cookie_high),
5501                                         rte_le_to_cpu_32(info.desc.cookie_low),
5502                                         info.msg_buf,
5503                                         info.msg_len);
5504                         break;
5505                 case i40e_aqc_opc_get_link_status:
5506                         ret = i40e_dev_link_update(dev, 0);
5507                         if (!ret) {
5508                                 i40e_notify_all_vfs_link_status(dev);
5509                                 _rte_eth_dev_callback_process(dev,
5510                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5511                         }
5512                         break;
5513                 default:
5514                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5515                                     opcode);
5516                         break;
5517                 }
5518         }
5519         rte_free(info.msg_buf);
5520 }
5521
5522 /**
5523  * Interrupt handler triggered by NIC  for handling
5524  * specific interrupt.
5525  *
5526  * @param handle
5527  *  Pointer to interrupt handle.
5528  * @param param
5529  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5530  *
5531  * @return
5532  *  void
5533  */
5534 static void
5535 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5536                            void *param)
5537 {
5538         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5540         uint32_t icr0;
5541
5542         /* Disable interrupt */
5543         i40e_pf_disable_irq0(hw);
5544
5545         /* read out interrupt causes */
5546         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5547
5548         /* No interrupt event indicated */
5549         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5550                 PMD_DRV_LOG(INFO, "No interrupt event");
5551                 goto done;
5552         }
5553 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5554         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5555                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5556         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5557                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5558         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5559                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5560         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5561                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5562         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5563                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5564         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5565                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5566         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5567                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5568 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5569
5570         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5571                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5572                 i40e_dev_handle_vfr_event(dev);
5573         }
5574         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5575                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5576                 i40e_dev_handle_aq_msg(dev);
5577         }
5578
5579 done:
5580         /* Enable interrupt */
5581         i40e_pf_enable_irq0(hw);
5582         rte_intr_enable(&(dev->pci_dev->intr_handle));
5583 }
5584
5585 static int
5586 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5587                          struct i40e_macvlan_filter *filter,
5588                          int total)
5589 {
5590         int ele_num, ele_buff_size;
5591         int num, actual_num, i;
5592         uint16_t flags;
5593         int ret = I40E_SUCCESS;
5594         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5595         struct i40e_aqc_add_macvlan_element_data *req_list;
5596
5597         if (filter == NULL  || total == 0)
5598                 return I40E_ERR_PARAM;
5599         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5600         ele_buff_size = hw->aq.asq_buf_size;
5601
5602         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5603         if (req_list == NULL) {
5604                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5605                 return I40E_ERR_NO_MEMORY;
5606         }
5607
5608         num = 0;
5609         do {
5610                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5611                 memset(req_list, 0, ele_buff_size);
5612
5613                 for (i = 0; i < actual_num; i++) {
5614                         (void)rte_memcpy(req_list[i].mac_addr,
5615                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5616                         req_list[i].vlan_tag =
5617                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5618
5619                         switch (filter[num + i].filter_type) {
5620                         case RTE_MAC_PERFECT_MATCH:
5621                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5622                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5623                                 break;
5624                         case RTE_MACVLAN_PERFECT_MATCH:
5625                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5626                                 break;
5627                         case RTE_MAC_HASH_MATCH:
5628                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5629                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5630                                 break;
5631                         case RTE_MACVLAN_HASH_MATCH:
5632                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5633                                 break;
5634                         default:
5635                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5636                                 ret = I40E_ERR_PARAM;
5637                                 goto DONE;
5638                         }
5639
5640                         req_list[i].queue_number = 0;
5641
5642                         req_list[i].flags = rte_cpu_to_le_16(flags);
5643                 }
5644
5645                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5646                                                 actual_num, NULL);
5647                 if (ret != I40E_SUCCESS) {
5648                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5649                         goto DONE;
5650                 }
5651                 num += actual_num;
5652         } while (num < total);
5653
5654 DONE:
5655         rte_free(req_list);
5656         return ret;
5657 }
5658
5659 static int
5660 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5661                             struct i40e_macvlan_filter *filter,
5662                             int total)
5663 {
5664         int ele_num, ele_buff_size;
5665         int num, actual_num, i;
5666         uint16_t flags;
5667         int ret = I40E_SUCCESS;
5668         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5669         struct i40e_aqc_remove_macvlan_element_data *req_list;
5670
5671         if (filter == NULL  || total == 0)
5672                 return I40E_ERR_PARAM;
5673
5674         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5675         ele_buff_size = hw->aq.asq_buf_size;
5676
5677         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5678         if (req_list == NULL) {
5679                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5680                 return I40E_ERR_NO_MEMORY;
5681         }
5682
5683         num = 0;
5684         do {
5685                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5686                 memset(req_list, 0, ele_buff_size);
5687
5688                 for (i = 0; i < actual_num; i++) {
5689                         (void)rte_memcpy(req_list[i].mac_addr,
5690                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5691                         req_list[i].vlan_tag =
5692                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5693
5694                         switch (filter[num + i].filter_type) {
5695                         case RTE_MAC_PERFECT_MATCH:
5696                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5697                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5698                                 break;
5699                         case RTE_MACVLAN_PERFECT_MATCH:
5700                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5701                                 break;
5702                         case RTE_MAC_HASH_MATCH:
5703                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5704                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5705                                 break;
5706                         case RTE_MACVLAN_HASH_MATCH:
5707                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5708                                 break;
5709                         default:
5710                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5711                                 ret = I40E_ERR_PARAM;
5712                                 goto DONE;
5713                         }
5714                         req_list[i].flags = rte_cpu_to_le_16(flags);
5715                 }
5716
5717                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5718                                                 actual_num, NULL);
5719                 if (ret != I40E_SUCCESS) {
5720                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5721                         goto DONE;
5722                 }
5723                 num += actual_num;
5724         } while (num < total);
5725
5726 DONE:
5727         rte_free(req_list);
5728         return ret;
5729 }
5730
5731 /* Find out specific MAC filter */
5732 static struct i40e_mac_filter *
5733 i40e_find_mac_filter(struct i40e_vsi *vsi,
5734                          struct ether_addr *macaddr)
5735 {
5736         struct i40e_mac_filter *f;
5737
5738         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5739                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5740                         return f;
5741         }
5742
5743         return NULL;
5744 }
5745
5746 static bool
5747 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5748                          uint16_t vlan_id)
5749 {
5750         uint32_t vid_idx, vid_bit;
5751
5752         if (vlan_id > ETH_VLAN_ID_MAX)
5753                 return 0;
5754
5755         vid_idx = I40E_VFTA_IDX(vlan_id);
5756         vid_bit = I40E_VFTA_BIT(vlan_id);
5757
5758         if (vsi->vfta[vid_idx] & vid_bit)
5759                 return 1;
5760         else
5761                 return 0;
5762 }
5763
5764 static void
5765 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5766                          uint16_t vlan_id, bool on)
5767 {
5768         uint32_t vid_idx, vid_bit;
5769
5770         if (vlan_id > ETH_VLAN_ID_MAX)
5771                 return;
5772
5773         vid_idx = I40E_VFTA_IDX(vlan_id);
5774         vid_bit = I40E_VFTA_BIT(vlan_id);
5775
5776         if (on)
5777                 vsi->vfta[vid_idx] |= vid_bit;
5778         else
5779                 vsi->vfta[vid_idx] &= ~vid_bit;
5780 }
5781
5782 /**
5783  * Find all vlan options for specific mac addr,
5784  * return with actual vlan found.
5785  */
5786 static inline int
5787 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5788                            struct i40e_macvlan_filter *mv_f,
5789                            int num, struct ether_addr *addr)
5790 {
5791         int i;
5792         uint32_t j, k;
5793
5794         /**
5795          * Not to use i40e_find_vlan_filter to decrease the loop time,
5796          * although the code looks complex.
5797           */
5798         if (num < vsi->vlan_num)
5799                 return I40E_ERR_PARAM;
5800
5801         i = 0;
5802         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5803                 if (vsi->vfta[j]) {
5804                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5805                                 if (vsi->vfta[j] & (1 << k)) {
5806                                         if (i > num - 1) {
5807                                                 PMD_DRV_LOG(ERR, "vlan number "
5808                                                             "not match");
5809                                                 return I40E_ERR_PARAM;
5810                                         }
5811                                         (void)rte_memcpy(&mv_f[i].macaddr,
5812                                                         addr, ETH_ADDR_LEN);
5813                                         mv_f[i].vlan_id =
5814                                                 j * I40E_UINT32_BIT_SIZE + k;
5815                                         i++;
5816                                 }
5817                         }
5818                 }
5819         }
5820         return I40E_SUCCESS;
5821 }
5822
5823 static inline int
5824 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5825                            struct i40e_macvlan_filter *mv_f,
5826                            int num,
5827                            uint16_t vlan)
5828 {
5829         int i = 0;
5830         struct i40e_mac_filter *f;
5831
5832         if (num < vsi->mac_num)
5833                 return I40E_ERR_PARAM;
5834
5835         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5836                 if (i > num - 1) {
5837                         PMD_DRV_LOG(ERR, "buffer number not match");
5838                         return I40E_ERR_PARAM;
5839                 }
5840                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5841                                 ETH_ADDR_LEN);
5842                 mv_f[i].vlan_id = vlan;
5843                 mv_f[i].filter_type = f->mac_info.filter_type;
5844                 i++;
5845         }
5846
5847         return I40E_SUCCESS;
5848 }
5849
5850 static int
5851 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5852 {
5853         int i, j, num;
5854         struct i40e_mac_filter *f;
5855         struct i40e_macvlan_filter *mv_f;
5856         int ret = I40E_SUCCESS;
5857
5858         if (vsi == NULL || vsi->mac_num == 0)
5859                 return I40E_ERR_PARAM;
5860
5861         /* Case that no vlan is set */
5862         if (vsi->vlan_num == 0)
5863                 num = vsi->mac_num;
5864         else
5865                 num = vsi->mac_num * vsi->vlan_num;
5866
5867         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5868         if (mv_f == NULL) {
5869                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5870                 return I40E_ERR_NO_MEMORY;
5871         }
5872
5873         i = 0;
5874         if (vsi->vlan_num == 0) {
5875                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5876                         (void)rte_memcpy(&mv_f[i].macaddr,
5877                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5878                         mv_f[i].filter_type = f->mac_info.filter_type;
5879                         mv_f[i].vlan_id = 0;
5880                         i++;
5881                 }
5882         } else {
5883                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5884                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5885                                         vsi->vlan_num, &f->mac_info.mac_addr);
5886                         if (ret != I40E_SUCCESS)
5887                                 goto DONE;
5888                         for (j = i; j < i + vsi->vlan_num; j++)
5889                                 mv_f[j].filter_type = f->mac_info.filter_type;
5890                         i += vsi->vlan_num;
5891                 }
5892         }
5893
5894         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5895 DONE:
5896         rte_free(mv_f);
5897
5898         return ret;
5899 }
5900
5901 int
5902 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5903 {
5904         struct i40e_macvlan_filter *mv_f;
5905         int mac_num;
5906         int ret = I40E_SUCCESS;
5907
5908         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5909                 return I40E_ERR_PARAM;
5910
5911         /* If it's already set, just return */
5912         if (i40e_find_vlan_filter(vsi,vlan))
5913                 return I40E_SUCCESS;
5914
5915         mac_num = vsi->mac_num;
5916
5917         if (mac_num == 0) {
5918                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5919                 return I40E_ERR_PARAM;
5920         }
5921
5922         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5923
5924         if (mv_f == NULL) {
5925                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5926                 return I40E_ERR_NO_MEMORY;
5927         }
5928
5929         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5930
5931         if (ret != I40E_SUCCESS)
5932                 goto DONE;
5933
5934         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5935
5936         if (ret != I40E_SUCCESS)
5937                 goto DONE;
5938
5939         i40e_set_vlan_filter(vsi, vlan, 1);
5940
5941         vsi->vlan_num++;
5942         ret = I40E_SUCCESS;
5943 DONE:
5944         rte_free(mv_f);
5945         return ret;
5946 }
5947
5948 int
5949 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5950 {
5951         struct i40e_macvlan_filter *mv_f;
5952         int mac_num;
5953         int ret = I40E_SUCCESS;
5954
5955         /**
5956          * Vlan 0 is the generic filter for untagged packets
5957          * and can't be removed.
5958          */
5959         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5960                 return I40E_ERR_PARAM;
5961
5962         /* If can't find it, just return */
5963         if (!i40e_find_vlan_filter(vsi, vlan))
5964                 return I40E_ERR_PARAM;
5965
5966         mac_num = vsi->mac_num;
5967
5968         if (mac_num == 0) {
5969                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5970                 return I40E_ERR_PARAM;
5971         }
5972
5973         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5974
5975         if (mv_f == NULL) {
5976                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5977                 return I40E_ERR_NO_MEMORY;
5978         }
5979
5980         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5981
5982         if (ret != I40E_SUCCESS)
5983                 goto DONE;
5984
5985         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5986
5987         if (ret != I40E_SUCCESS)
5988                 goto DONE;
5989
5990         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5991         if (vsi->vlan_num == 1) {
5992                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5993                 if (ret != I40E_SUCCESS)
5994                         goto DONE;
5995
5996                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5997                 if (ret != I40E_SUCCESS)
5998                         goto DONE;
5999         }
6000
6001         i40e_set_vlan_filter(vsi, vlan, 0);
6002
6003         vsi->vlan_num--;
6004         ret = I40E_SUCCESS;
6005 DONE:
6006         rte_free(mv_f);
6007         return ret;
6008 }
6009
6010 int
6011 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6012 {
6013         struct i40e_mac_filter *f;
6014         struct i40e_macvlan_filter *mv_f;
6015         int i, vlan_num = 0;
6016         int ret = I40E_SUCCESS;
6017
6018         /* If it's add and we've config it, return */
6019         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6020         if (f != NULL)
6021                 return I40E_SUCCESS;
6022         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6023                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6024
6025                 /**
6026                  * If vlan_num is 0, that's the first time to add mac,
6027                  * set mask for vlan_id 0.
6028                  */
6029                 if (vsi->vlan_num == 0) {
6030                         i40e_set_vlan_filter(vsi, 0, 1);
6031                         vsi->vlan_num = 1;
6032                 }
6033                 vlan_num = vsi->vlan_num;
6034         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6035                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6036                 vlan_num = 1;
6037
6038         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6039         if (mv_f == NULL) {
6040                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6041                 return I40E_ERR_NO_MEMORY;
6042         }
6043
6044         for (i = 0; i < vlan_num; i++) {
6045                 mv_f[i].filter_type = mac_filter->filter_type;
6046                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6047                                 ETH_ADDR_LEN);
6048         }
6049
6050         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6051                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6052                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6053                                         &mac_filter->mac_addr);
6054                 if (ret != I40E_SUCCESS)
6055                         goto DONE;
6056         }
6057
6058         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6059         if (ret != I40E_SUCCESS)
6060                 goto DONE;
6061
6062         /* Add the mac addr into mac list */
6063         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6064         if (f == NULL) {
6065                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6066                 ret = I40E_ERR_NO_MEMORY;
6067                 goto DONE;
6068         }
6069         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6070                         ETH_ADDR_LEN);
6071         f->mac_info.filter_type = mac_filter->filter_type;
6072         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6073         vsi->mac_num++;
6074
6075         ret = I40E_SUCCESS;
6076 DONE:
6077         rte_free(mv_f);
6078
6079         return ret;
6080 }
6081
6082 int
6083 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6084 {
6085         struct i40e_mac_filter *f;
6086         struct i40e_macvlan_filter *mv_f;
6087         int i, vlan_num;
6088         enum rte_mac_filter_type filter_type;
6089         int ret = I40E_SUCCESS;
6090
6091         /* Can't find it, return an error */
6092         f = i40e_find_mac_filter(vsi, addr);
6093         if (f == NULL)
6094                 return I40E_ERR_PARAM;
6095
6096         vlan_num = vsi->vlan_num;
6097         filter_type = f->mac_info.filter_type;
6098         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6099                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6100                 if (vlan_num == 0) {
6101                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6102                         return I40E_ERR_PARAM;
6103                 }
6104         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6105                         filter_type == RTE_MAC_HASH_MATCH)
6106                 vlan_num = 1;
6107
6108         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6109         if (mv_f == NULL) {
6110                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6111                 return I40E_ERR_NO_MEMORY;
6112         }
6113
6114         for (i = 0; i < vlan_num; i++) {
6115                 mv_f[i].filter_type = filter_type;
6116                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6117                                 ETH_ADDR_LEN);
6118         }
6119         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6120                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6121                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6122                 if (ret != I40E_SUCCESS)
6123                         goto DONE;
6124         }
6125
6126         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6127         if (ret != I40E_SUCCESS)
6128                 goto DONE;
6129
6130         /* Remove the mac addr into mac list */
6131         TAILQ_REMOVE(&vsi->mac_list, f, next);
6132         rte_free(f);
6133         vsi->mac_num--;
6134
6135         ret = I40E_SUCCESS;
6136 DONE:
6137         rte_free(mv_f);
6138         return ret;
6139 }
6140
6141 /* Configure hash enable flags for RSS */
6142 uint64_t
6143 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6144 {
6145         uint64_t hena = 0;
6146
6147         if (!flags)
6148                 return hena;
6149
6150         if (flags & ETH_RSS_FRAG_IPV4)
6151                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6152         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6153                 if (type == I40E_MAC_X722) {
6154                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6155                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6156                 } else
6157                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6158         }
6159         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6160                 if (type == I40E_MAC_X722) {
6161                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6162                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6163                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6164                 } else
6165                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6166         }
6167         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6168                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6169         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6170                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6171         if (flags & ETH_RSS_FRAG_IPV6)
6172                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6173         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6174                 if (type == I40E_MAC_X722) {
6175                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6176                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6177                 } else
6178                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6179         }
6180         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6181                 if (type == I40E_MAC_X722) {
6182                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6183                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6184                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6185                 } else
6186                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6187         }
6188         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6189                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6190         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6191                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6192         if (flags & ETH_RSS_L2_PAYLOAD)
6193                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6194
6195         return hena;
6196 }
6197
6198 /* Parse the hash enable flags */
6199 uint64_t
6200 i40e_parse_hena(uint64_t flags)
6201 {
6202         uint64_t rss_hf = 0;
6203
6204         if (!flags)
6205                 return rss_hf;
6206         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6207                 rss_hf |= ETH_RSS_FRAG_IPV4;
6208         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6209                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6210 #ifdef X722_SUPPORT
6211         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6212                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6213 #endif
6214         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6215                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6216 #ifdef X722_SUPPORT
6217         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6218                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6219         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6220                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6221 #endif
6222         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6223                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6224         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6225                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6226         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6227                 rss_hf |= ETH_RSS_FRAG_IPV6;
6228         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6229                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6230 #ifdef X722_SUPPORT
6231         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6232                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6233 #endif
6234         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6235                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6236 #ifdef X722_SUPPORT
6237         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6238                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6239         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6240                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6241 #endif
6242         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6243                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6244         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6245                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6246         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6247                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6248
6249         return rss_hf;
6250 }
6251
6252 /* Disable RSS */
6253 static void
6254 i40e_pf_disable_rss(struct i40e_pf *pf)
6255 {
6256         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6257         uint64_t hena;
6258
6259         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6260         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6261         if (hw->mac.type == I40E_MAC_X722)
6262                 hena &= ~I40E_RSS_HENA_ALL_X722;
6263         else
6264                 hena &= ~I40E_RSS_HENA_ALL;
6265         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6266         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6267         I40E_WRITE_FLUSH(hw);
6268 }
6269
6270 static int
6271 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6272 {
6273         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6274         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6275         int ret = 0;
6276
6277         if (!key || key_len == 0) {
6278                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6279                 return 0;
6280         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6281                 sizeof(uint32_t)) {
6282                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6283                 return -EINVAL;
6284         }
6285
6286         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6287                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6288                         (struct i40e_aqc_get_set_rss_key_data *)key;
6289
6290                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6291                 if (ret)
6292                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6293                                      "via AQ");
6294         } else {
6295                 uint32_t *hash_key = (uint32_t *)key;
6296                 uint16_t i;
6297
6298                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6299                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6300                 I40E_WRITE_FLUSH(hw);
6301         }
6302
6303         return ret;
6304 }
6305
6306 static int
6307 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6308 {
6309         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6310         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6311         int ret;
6312
6313         if (!key || !key_len)
6314                 return -EINVAL;
6315
6316         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6317                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6318                         (struct i40e_aqc_get_set_rss_key_data *)key);
6319                 if (ret) {
6320                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6321                         return ret;
6322                 }
6323         } else {
6324                 uint32_t *key_dw = (uint32_t *)key;
6325                 uint16_t i;
6326
6327                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6328                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6329         }
6330         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6331
6332         return 0;
6333 }
6334
6335 static int
6336 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6337 {
6338         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6339         uint64_t rss_hf;
6340         uint64_t hena;
6341         int ret;
6342
6343         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6344                                rss_conf->rss_key_len);
6345         if (ret)
6346                 return ret;
6347
6348         rss_hf = rss_conf->rss_hf;
6349         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6350         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6351         if (hw->mac.type == I40E_MAC_X722)
6352                 hena &= ~I40E_RSS_HENA_ALL_X722;
6353         else
6354                 hena &= ~I40E_RSS_HENA_ALL;
6355         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6356         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6357         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6358         I40E_WRITE_FLUSH(hw);
6359
6360         return 0;
6361 }
6362
6363 static int
6364 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6365                          struct rte_eth_rss_conf *rss_conf)
6366 {
6367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6369         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6370         uint64_t hena;
6371
6372         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6373         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6374         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6375                  ? I40E_RSS_HENA_ALL_X722
6376                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6377                 if (rss_hf != 0) /* Enable RSS */
6378                         return -EINVAL;
6379                 return 0; /* Nothing to do */
6380         }
6381         /* RSS enabled */
6382         if (rss_hf == 0) /* Disable RSS */
6383                 return -EINVAL;
6384
6385         return i40e_hw_rss_hash_set(pf, rss_conf);
6386 }
6387
6388 static int
6389 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6390                            struct rte_eth_rss_conf *rss_conf)
6391 {
6392         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6393         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6394         uint64_t hena;
6395
6396         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6397                          &rss_conf->rss_key_len);
6398
6399         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6400         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6401         rss_conf->rss_hf = i40e_parse_hena(hena);
6402
6403         return 0;
6404 }
6405
6406 static int
6407 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6408 {
6409         switch (filter_type) {
6410         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6411                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6412                 break;
6413         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6414                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6415                 break;
6416         case RTE_TUNNEL_FILTER_IMAC_TENID:
6417                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6418                 break;
6419         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6420                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6421                 break;
6422         case ETH_TUNNEL_FILTER_IMAC:
6423                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6424                 break;
6425         case ETH_TUNNEL_FILTER_OIP:
6426                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6427                 break;
6428         case ETH_TUNNEL_FILTER_IIP:
6429                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6430                 break;
6431         default:
6432                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6433                 return -EINVAL;
6434         }
6435
6436         return 0;
6437 }
6438
6439 static int
6440 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6441                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6442                         uint8_t add)
6443 {
6444         uint16_t ip_type;
6445         uint32_t ipv4_addr;
6446         uint8_t i, tun_type = 0;
6447         /* internal varialbe to convert ipv6 byte order */
6448         uint32_t convert_ipv6[4];
6449         int val, ret = 0;
6450         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6451         struct i40e_vsi *vsi = pf->main_vsi;
6452         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6453         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6454
6455         cld_filter = rte_zmalloc("tunnel_filter",
6456                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6457                 0);
6458
6459         if (NULL == cld_filter) {
6460                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6461                 return -EINVAL;
6462         }
6463         pfilter = cld_filter;
6464
6465         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6466         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6467
6468         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6469         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6470                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6471                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6472                 rte_memcpy(&pfilter->ipaddr.v4.data,
6473                                 &rte_cpu_to_le_32(ipv4_addr),
6474                                 sizeof(pfilter->ipaddr.v4.data));
6475         } else {
6476                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6477                 for (i = 0; i < 4; i++) {
6478                         convert_ipv6[i] =
6479                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6480                 }
6481                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6482                                 sizeof(pfilter->ipaddr.v6.data));
6483         }
6484
6485         /* check tunneled type */
6486         switch (tunnel_filter->tunnel_type) {
6487         case RTE_TUNNEL_TYPE_VXLAN:
6488                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6489                 break;
6490         case RTE_TUNNEL_TYPE_NVGRE:
6491                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6492                 break;
6493         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6494                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6495                 break;
6496         default:
6497                 /* Other tunnel types is not supported. */
6498                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6499                 rte_free(cld_filter);
6500                 return -EINVAL;
6501         }
6502
6503         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6504                                                 &pfilter->flags);
6505         if (val < 0) {
6506                 rte_free(cld_filter);
6507                 return -EINVAL;
6508         }
6509
6510         pfilter->flags |= rte_cpu_to_le_16(
6511                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6512                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6513         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6514         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6515
6516         if (add)
6517                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6518         else
6519                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6520                                                 cld_filter, 1);
6521
6522         rte_free(cld_filter);
6523         return ret;
6524 }
6525
6526 static int
6527 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6528 {
6529         uint8_t i;
6530
6531         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6532                 if (pf->vxlan_ports[i] == port)
6533                         return i;
6534         }
6535
6536         return -1;
6537 }
6538
6539 static int
6540 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6541 {
6542         int  idx, ret;
6543         uint8_t filter_idx;
6544         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6545
6546         idx = i40e_get_vxlan_port_idx(pf, port);
6547
6548         /* Check if port already exists */
6549         if (idx >= 0) {
6550                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6551                 return -EINVAL;
6552         }
6553
6554         /* Now check if there is space to add the new port */
6555         idx = i40e_get_vxlan_port_idx(pf, 0);
6556         if (idx < 0) {
6557                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6558                         "not adding port %d", port);
6559                 return -ENOSPC;
6560         }
6561
6562         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6563                                         &filter_idx, NULL);
6564         if (ret < 0) {
6565                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6566                 return -1;
6567         }
6568
6569         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6570                          port,  filter_idx);
6571
6572         /* New port: add it and mark its index in the bitmap */
6573         pf->vxlan_ports[idx] = port;
6574         pf->vxlan_bitmap |= (1 << idx);
6575
6576         if (!(pf->flags & I40E_FLAG_VXLAN))
6577                 pf->flags |= I40E_FLAG_VXLAN;
6578
6579         return 0;
6580 }
6581
6582 static int
6583 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6584 {
6585         int idx;
6586         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6587
6588         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6589                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6590                 return -EINVAL;
6591         }
6592
6593         idx = i40e_get_vxlan_port_idx(pf, port);
6594
6595         if (idx < 0) {
6596                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6597                 return -EINVAL;
6598         }
6599
6600         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6601                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6602                 return -1;
6603         }
6604
6605         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6606                         port, idx);
6607
6608         pf->vxlan_ports[idx] = 0;
6609         pf->vxlan_bitmap &= ~(1 << idx);
6610
6611         if (!pf->vxlan_bitmap)
6612                 pf->flags &= ~I40E_FLAG_VXLAN;
6613
6614         return 0;
6615 }
6616
6617 /* Add UDP tunneling port */
6618 static int
6619 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6620                              struct rte_eth_udp_tunnel *udp_tunnel)
6621 {
6622         int ret = 0;
6623         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6624
6625         if (udp_tunnel == NULL)
6626                 return -EINVAL;
6627
6628         switch (udp_tunnel->prot_type) {
6629         case RTE_TUNNEL_TYPE_VXLAN:
6630                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6631                 break;
6632
6633         case RTE_TUNNEL_TYPE_GENEVE:
6634         case RTE_TUNNEL_TYPE_TEREDO:
6635                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6636                 ret = -1;
6637                 break;
6638
6639         default:
6640                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6641                 ret = -1;
6642                 break;
6643         }
6644
6645         return ret;
6646 }
6647
6648 /* Remove UDP tunneling port */
6649 static int
6650 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6651                              struct rte_eth_udp_tunnel *udp_tunnel)
6652 {
6653         int ret = 0;
6654         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6655
6656         if (udp_tunnel == NULL)
6657                 return -EINVAL;
6658
6659         switch (udp_tunnel->prot_type) {
6660         case RTE_TUNNEL_TYPE_VXLAN:
6661                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6662                 break;
6663         case RTE_TUNNEL_TYPE_GENEVE:
6664         case RTE_TUNNEL_TYPE_TEREDO:
6665                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6666                 ret = -1;
6667                 break;
6668         default:
6669                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6670                 ret = -1;
6671                 break;
6672         }
6673
6674         return ret;
6675 }
6676
6677 /* Calculate the maximum number of contiguous PF queues that are configured */
6678 static int
6679 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6680 {
6681         struct rte_eth_dev_data *data = pf->dev_data;
6682         int i, num;
6683         struct i40e_rx_queue *rxq;
6684
6685         num = 0;
6686         for (i = 0; i < pf->lan_nb_qps; i++) {
6687                 rxq = data->rx_queues[i];
6688                 if (rxq && rxq->q_set)
6689                         num++;
6690                 else
6691                         break;
6692         }
6693
6694         return num;
6695 }
6696
6697 /* Configure RSS */
6698 static int
6699 i40e_pf_config_rss(struct i40e_pf *pf)
6700 {
6701         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6702         struct rte_eth_rss_conf rss_conf;
6703         uint32_t i, lut = 0;
6704         uint16_t j, num;
6705
6706         /*
6707          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6708          * It's necessary to calulate the actual PF queues that are configured.
6709          */
6710         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6711                 num = i40e_pf_calc_configured_queues_num(pf);
6712         else
6713                 num = pf->dev_data->nb_rx_queues;
6714
6715         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6716         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6717                         num);
6718
6719         if (num == 0) {
6720                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6721                 return -ENOTSUP;
6722         }
6723
6724         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6725                 if (j == num)
6726                         j = 0;
6727                 lut = (lut << 8) | (j & ((0x1 <<
6728                         hw->func_caps.rss_table_entry_width) - 1));
6729                 if ((i & 3) == 3)
6730                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6731         }
6732
6733         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6734         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6735                 i40e_pf_disable_rss(pf);
6736                 return 0;
6737         }
6738         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6739                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6740                 /* Random default keys */
6741                 static uint32_t rss_key_default[] = {0x6b793944,
6742                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6743                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6744                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6745
6746                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6747                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6748                                                         sizeof(uint32_t);
6749         }
6750
6751         return i40e_hw_rss_hash_set(pf, &rss_conf);
6752 }
6753
6754 static int
6755 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6756                                struct rte_eth_tunnel_filter_conf *filter)
6757 {
6758         if (pf == NULL || filter == NULL) {
6759                 PMD_DRV_LOG(ERR, "Invalid parameter");
6760                 return -EINVAL;
6761         }
6762
6763         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6764                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6765                 return -EINVAL;
6766         }
6767
6768         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6769                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6770                 return -EINVAL;
6771         }
6772
6773         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6774                 (is_zero_ether_addr(&filter->outer_mac))) {
6775                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6776                 return -EINVAL;
6777         }
6778
6779         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6780                 (is_zero_ether_addr(&filter->inner_mac))) {
6781                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6782                 return -EINVAL;
6783         }
6784
6785         return 0;
6786 }
6787
6788 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6789 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6790 static int
6791 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6792 {
6793         uint32_t val, reg;
6794         int ret = -EINVAL;
6795
6796         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6797         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6798
6799         if (len == 3) {
6800                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6801         } else if (len == 4) {
6802                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6803         } else {
6804                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6805                 return ret;
6806         }
6807
6808         if (reg != val) {
6809                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6810                                                    reg, NULL);
6811                 if (ret != 0)
6812                         return ret;
6813         } else {
6814                 ret = 0;
6815         }
6816         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6817                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6818
6819         return ret;
6820 }
6821
6822 static int
6823 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6824 {
6825         int ret = -EINVAL;
6826
6827         if (!hw || !cfg)
6828                 return -EINVAL;
6829
6830         switch (cfg->cfg_type) {
6831         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6832                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6833                 break;
6834         default:
6835                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6836                 break;
6837         }
6838
6839         return ret;
6840 }
6841
6842 static int
6843 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6844                                enum rte_filter_op filter_op,
6845                                void *arg)
6846 {
6847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6848         int ret = I40E_ERR_PARAM;
6849
6850         switch (filter_op) {
6851         case RTE_ETH_FILTER_SET:
6852                 ret = i40e_dev_global_config_set(hw,
6853                         (struct rte_eth_global_cfg *)arg);
6854                 break;
6855         default:
6856                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6857                 break;
6858         }
6859
6860         return ret;
6861 }
6862
6863 static int
6864 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6865                           enum rte_filter_op filter_op,
6866                           void *arg)
6867 {
6868         struct rte_eth_tunnel_filter_conf *filter;
6869         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6870         int ret = I40E_SUCCESS;
6871
6872         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6873
6874         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6875                 return I40E_ERR_PARAM;
6876
6877         switch (filter_op) {
6878         case RTE_ETH_FILTER_NOP:
6879                 if (!(pf->flags & I40E_FLAG_VXLAN))
6880                         ret = I40E_NOT_SUPPORTED;
6881                 break;
6882         case RTE_ETH_FILTER_ADD:
6883                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6884                 break;
6885         case RTE_ETH_FILTER_DELETE:
6886                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6887                 break;
6888         default:
6889                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6890                 ret = I40E_ERR_PARAM;
6891                 break;
6892         }
6893
6894         return ret;
6895 }
6896
6897 static int
6898 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6899 {
6900         int ret = 0;
6901         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6902
6903         /* RSS setup */
6904         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6905                 ret = i40e_pf_config_rss(pf);
6906         else
6907                 i40e_pf_disable_rss(pf);
6908
6909         return ret;
6910 }
6911
6912 /* Get the symmetric hash enable configurations per port */
6913 static void
6914 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6915 {
6916         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6917
6918         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6919 }
6920
6921 /* Set the symmetric hash enable configurations per port */
6922 static void
6923 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6924 {
6925         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6926
6927         if (enable > 0) {
6928                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6929                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6930                                                         "been enabled");
6931                         return;
6932                 }
6933                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6934         } else {
6935                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6936                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6937                                                         "been disabled");
6938                         return;
6939                 }
6940                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6941         }
6942         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6943         I40E_WRITE_FLUSH(hw);
6944 }
6945
6946 /*
6947  * Get global configurations of hash function type and symmetric hash enable
6948  * per flow type (pctype). Note that global configuration means it affects all
6949  * the ports on the same NIC.
6950  */
6951 static int
6952 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6953                                    struct rte_eth_hash_global_conf *g_cfg)
6954 {
6955         uint32_t reg, mask = I40E_FLOW_TYPES;
6956         uint16_t i;
6957         enum i40e_filter_pctype pctype;
6958
6959         memset(g_cfg, 0, sizeof(*g_cfg));
6960         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6961         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6962                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6963         else
6964                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6965         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6966                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6967
6968         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6969                 if (!(mask & (1UL << i)))
6970                         continue;
6971                 mask &= ~(1UL << i);
6972                 /* Bit set indicats the coresponding flow type is supported */
6973                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6974                 /* if flowtype is invalid, continue */
6975                 if (!I40E_VALID_FLOW(i))
6976                         continue;
6977                 pctype = i40e_flowtype_to_pctype(i);
6978                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6979                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6980                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6981         }
6982
6983         return 0;
6984 }
6985
6986 static int
6987 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6988 {
6989         uint32_t i;
6990         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6991
6992         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6993                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6994                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6995                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6996                                                 g_cfg->hash_func);
6997                 return -EINVAL;
6998         }
6999
7000         /*
7001          * As i40e supports less than 32 flow types, only first 32 bits need to
7002          * be checked.
7003          */
7004         mask0 = g_cfg->valid_bit_mask[0];
7005         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7006                 if (i == 0) {
7007                         /* Check if any unsupported flow type configured */
7008                         if ((mask0 | i40e_mask) ^ i40e_mask)
7009                                 goto mask_err;
7010                 } else {
7011                         if (g_cfg->valid_bit_mask[i])
7012                                 goto mask_err;
7013                 }
7014         }
7015
7016         return 0;
7017
7018 mask_err:
7019         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7020
7021         return -EINVAL;
7022 }
7023
7024 /*
7025  * Set global configurations of hash function type and symmetric hash enable
7026  * per flow type (pctype). Note any modifying global configuration will affect
7027  * all the ports on the same NIC.
7028  */
7029 static int
7030 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7031                                    struct rte_eth_hash_global_conf *g_cfg)
7032 {
7033         int ret;
7034         uint16_t i;
7035         uint32_t reg;
7036         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7037         enum i40e_filter_pctype pctype;
7038
7039         /* Check the input parameters */
7040         ret = i40e_hash_global_config_check(g_cfg);
7041         if (ret < 0)
7042                 return ret;
7043
7044         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7045                 if (!(mask0 & (1UL << i)))
7046                         continue;
7047                 mask0 &= ~(1UL << i);
7048                 /* if flowtype is invalid, continue */
7049                 if (!I40E_VALID_FLOW(i))
7050                         continue;
7051                 pctype = i40e_flowtype_to_pctype(i);
7052                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7053                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7054                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7055         }
7056
7057         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7058         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7059                 /* Toeplitz */
7060                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7061                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7062                                                                 "Toeplitz");
7063                         goto out;
7064                 }
7065                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7066         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7067                 /* Simple XOR */
7068                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7069                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7070                                                         "Simple XOR");
7071                         goto out;
7072                 }
7073                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7074         } else
7075                 /* Use the default, and keep it as it is */
7076                 goto out;
7077
7078         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7079
7080 out:
7081         I40E_WRITE_FLUSH(hw);
7082
7083         return 0;
7084 }
7085
7086 /**
7087  * Valid input sets for hash and flow director filters per PCTYPE
7088  */
7089 static uint64_t
7090 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7091                 enum rte_filter_type filter)
7092 {
7093         uint64_t valid;
7094
7095         static const uint64_t valid_hash_inset_table[] = {
7096                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7100                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7101                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7102                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7103                         I40E_INSET_FLEX_PAYLOAD,
7104                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7105                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7106                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7107                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7108                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7109                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7110                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7111                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7112                         I40E_INSET_FLEX_PAYLOAD,
7113 #ifdef X722_SUPPORT
7114                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7118                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7119                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7120                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7121                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7122                         I40E_INSET_FLEX_PAYLOAD,
7123                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7124                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7125                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7126                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7127                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7128                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7129                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7130                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7131                         I40E_INSET_FLEX_PAYLOAD,
7132 #endif
7133                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7134                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7135                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7136                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7137                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7138                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7139                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7140                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7141                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7142 #ifdef X722_SUPPORT
7143                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7144                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7145                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7146                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7147                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7148                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7149                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7150                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7151                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7152 #endif
7153                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7154                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7155                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7156                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7157                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7158                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7159                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7160                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7161                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7162                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7163                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7164                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7165                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7166                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7167                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7168                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7169                         I40E_INSET_FLEX_PAYLOAD,
7170                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7171                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7172                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7173                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7174                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7175                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7176                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7177                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7178                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7179                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7180                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7181                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7182                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7183                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7184                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7185                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7186 #ifdef X722_SUPPORT
7187                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7188                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7189                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7190                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7191                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7192                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7193                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7194                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7195                         I40E_INSET_FLEX_PAYLOAD,
7196                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7197                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7198                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7199                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7200                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7201                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7202                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7203                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7204                         I40E_INSET_FLEX_PAYLOAD,
7205 #endif
7206                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7207                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7208                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7209                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7210                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7211                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7212                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7213                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7214                         I40E_INSET_FLEX_PAYLOAD,
7215 #ifdef X722_SUPPORT
7216                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7217                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7218                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7219                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7220                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7221                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7222                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7223                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7224                         I40E_INSET_FLEX_PAYLOAD,
7225 #endif
7226                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7227                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7228                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7229                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7230                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7231                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7232                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7233                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7234                         I40E_INSET_FLEX_PAYLOAD,
7235                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7236                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7237                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7238                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7239                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7240                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7241                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7242                         I40E_INSET_FLEX_PAYLOAD,
7243                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7244                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7245                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7246                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7247                         I40E_INSET_FLEX_PAYLOAD,
7248         };
7249
7250         /**
7251          * Flow director supports only fields defined in
7252          * union rte_eth_fdir_flow.
7253          */
7254         static const uint64_t valid_fdir_inset_table[] = {
7255                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7256                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7257                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7258                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7259                 I40E_INSET_IPV4_TTL,
7260                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7261                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7262                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7263                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7264                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7265 #ifdef X722_SUPPORT
7266                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7267                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7268                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7269                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7270                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7271                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7272                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7273                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7274                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7275                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7276 #endif
7277                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7278                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7279                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7280                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7281                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7282 #ifdef X722_SUPPORT
7283                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7284                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7285                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7286                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7287                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7288 #endif
7289                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7290                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7291                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7292                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7293                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7294                 I40E_INSET_SCTP_VT,
7295                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7296                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7297                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7298                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7299                 I40E_INSET_IPV4_TTL,
7300                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7301                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7302                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7303                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7304                 I40E_INSET_IPV6_HOP_LIMIT,
7305                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7306                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7307                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7308                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7309                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7310 #ifdef X722_SUPPORT
7311                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7312                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7313                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7314                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7315                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7316                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7317                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7318                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7319                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7320                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7321 #endif
7322                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7323                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7324                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7325                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7326                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7327 #ifdef X722_SUPPORT
7328                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7329                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7330                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7331                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7332                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7333 #endif
7334                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7335                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7336                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7337                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7338                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7339                 I40E_INSET_SCTP_VT,
7340                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7341                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7342                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7343                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7344                 I40E_INSET_IPV6_HOP_LIMIT,
7345                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7346                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7347                 I40E_INSET_LAST_ETHER_TYPE,
7348         };
7349
7350         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7351                 return 0;
7352         if (filter == RTE_ETH_FILTER_HASH)
7353                 valid = valid_hash_inset_table[pctype];
7354         else
7355                 valid = valid_fdir_inset_table[pctype];
7356
7357         return valid;
7358 }
7359
7360 /**
7361  * Validate if the input set is allowed for a specific PCTYPE
7362  */
7363 static int
7364 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7365                 enum rte_filter_type filter, uint64_t inset)
7366 {
7367         uint64_t valid;
7368
7369         valid = i40e_get_valid_input_set(pctype, filter);
7370         if (inset & (~valid))
7371                 return -EINVAL;
7372
7373         return 0;
7374 }
7375
7376 /* default input set fields combination per pctype */
7377 static uint64_t
7378 i40e_get_default_input_set(uint16_t pctype)
7379 {
7380         static const uint64_t default_inset_table[] = {
7381                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7382                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7383                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7384                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7385                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7386 #ifdef X722_SUPPORT
7387                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7388                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7389                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7390                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7391                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7392                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7393 #endif
7394                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7395                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7396                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7397 #ifdef X722_SUPPORT
7398                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7399                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7400                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7401 #endif
7402                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7403                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7404                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7405                         I40E_INSET_SCTP_VT,
7406                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7407                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7408                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7409                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7410                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7411                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7412                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7413 #ifdef X722_SUPPORT
7414                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7415                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7416                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7417                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7418                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7419                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7420 #endif
7421                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7422                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7423                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7424 #ifdef X722_SUPPORT
7425                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7426                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7427                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7428 #endif
7429                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7430                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7431                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7432                         I40E_INSET_SCTP_VT,
7433                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7434                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7435                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7436                         I40E_INSET_LAST_ETHER_TYPE,
7437         };
7438
7439         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7440                 return 0;
7441
7442         return default_inset_table[pctype];
7443 }
7444
7445 /**
7446  * Parse the input set from index to logical bit masks
7447  */
7448 static int
7449 i40e_parse_input_set(uint64_t *inset,
7450                      enum i40e_filter_pctype pctype,
7451                      enum rte_eth_input_set_field *field,
7452                      uint16_t size)
7453 {
7454         uint16_t i, j;
7455         int ret = -EINVAL;
7456
7457         static const struct {
7458                 enum rte_eth_input_set_field field;
7459                 uint64_t inset;
7460         } inset_convert_table[] = {
7461                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7462                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7463                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7464                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7465                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7466                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7467                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7468                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7469                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7470                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7471                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7472                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7473                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7474                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7475                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7476                         I40E_INSET_IPV6_NEXT_HDR},
7477                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7478                         I40E_INSET_IPV6_HOP_LIMIT},
7479                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7480                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7481                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7482                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7483                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7484                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7485                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7486                         I40E_INSET_SCTP_VT},
7487                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7488                         I40E_INSET_TUNNEL_DMAC},
7489                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7490                         I40E_INSET_VLAN_TUNNEL},
7491                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7492                         I40E_INSET_TUNNEL_ID},
7493                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7494                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7495                         I40E_INSET_FLEX_PAYLOAD_W1},
7496                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7497                         I40E_INSET_FLEX_PAYLOAD_W2},
7498                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7499                         I40E_INSET_FLEX_PAYLOAD_W3},
7500                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7501                         I40E_INSET_FLEX_PAYLOAD_W4},
7502                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7503                         I40E_INSET_FLEX_PAYLOAD_W5},
7504                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7505                         I40E_INSET_FLEX_PAYLOAD_W6},
7506                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7507                         I40E_INSET_FLEX_PAYLOAD_W7},
7508                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7509                         I40E_INSET_FLEX_PAYLOAD_W8},
7510         };
7511
7512         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7513                 return ret;
7514
7515         /* Only one item allowed for default or all */
7516         if (size == 1) {
7517                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7518                         *inset = i40e_get_default_input_set(pctype);
7519                         return 0;
7520                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7521                         *inset = I40E_INSET_NONE;
7522                         return 0;
7523                 }
7524         }
7525
7526         for (i = 0, *inset = 0; i < size; i++) {
7527                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7528                         if (field[i] == inset_convert_table[j].field) {
7529                                 *inset |= inset_convert_table[j].inset;
7530                                 break;
7531                         }
7532                 }
7533
7534                 /* It contains unsupported input set, return immediately */
7535                 if (j == RTE_DIM(inset_convert_table))
7536                         return ret;
7537         }
7538
7539         return 0;
7540 }
7541
7542 /**
7543  * Translate the input set from bit masks to register aware bit masks
7544  * and vice versa
7545  */
7546 static uint64_t
7547 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7548 {
7549         uint64_t val = 0;
7550         uint16_t i;
7551
7552         struct inset_map {
7553                 uint64_t inset;
7554                 uint64_t inset_reg;
7555         };
7556
7557         static const struct inset_map inset_map_common[] = {
7558                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7559                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7560                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7561                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7562                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7563                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7564                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7565                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7566                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7567                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7568                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7569                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7570                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7571                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7572                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7573                 {I40E_INSET_TUNNEL_DMAC,
7574                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7575                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7576                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7577                 {I40E_INSET_TUNNEL_SRC_PORT,
7578                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7579                 {I40E_INSET_TUNNEL_DST_PORT,
7580                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7581                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7582                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7583                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7584                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7585                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7586                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7587                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7588                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7589                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7590         };
7591
7592     /* some different registers map in x722*/
7593         static const struct inset_map inset_map_diff_x722[] = {
7594                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7595                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7596                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7597                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7598         };
7599
7600         static const struct inset_map inset_map_diff_not_x722[] = {
7601                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7602                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7603                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7604                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7605         };
7606
7607         if (input == 0)
7608                 return val;
7609
7610         /* Translate input set to register aware inset */
7611         if (type == I40E_MAC_X722) {
7612                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7613                         if (input & inset_map_diff_x722[i].inset)
7614                                 val |= inset_map_diff_x722[i].inset_reg;
7615                 }
7616         } else {
7617                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7618                         if (input & inset_map_diff_not_x722[i].inset)
7619                                 val |= inset_map_diff_not_x722[i].inset_reg;
7620                 }
7621         }
7622
7623         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7624                 if (input & inset_map_common[i].inset)
7625                         val |= inset_map_common[i].inset_reg;
7626         }
7627
7628         return val;
7629 }
7630
7631 static int
7632 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7633 {
7634         uint8_t i, idx = 0;
7635         uint64_t inset_need_mask = inset;
7636
7637         static const struct {
7638                 uint64_t inset;
7639                 uint32_t mask;
7640         } inset_mask_map[] = {
7641                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7642                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7643                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7644                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7645                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7646                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7647                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7648                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7649         };
7650
7651         if (!inset || !mask || !nb_elem)
7652                 return 0;
7653
7654         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7655                 /* Clear the inset bit, if no MASK is required,
7656                  * for example proto + ttl
7657                  */
7658                 if ((inset & inset_mask_map[i].inset) ==
7659                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7660                         inset_need_mask &= ~inset_mask_map[i].inset;
7661                 if (!inset_need_mask)
7662                         return 0;
7663         }
7664         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7665                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7666                     inset_mask_map[i].inset) {
7667                         if (idx >= nb_elem) {
7668                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7669                                 return -EINVAL;
7670                         }
7671                         mask[idx] = inset_mask_map[i].mask;
7672                         idx++;
7673                 }
7674         }
7675
7676         return idx;
7677 }
7678
7679 static void
7680 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7681 {
7682         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7683
7684         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7685         if (reg != val)
7686                 i40e_write_rx_ctl(hw, addr, val);
7687         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7688                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7689 }
7690
7691 static void
7692 i40e_filter_input_set_init(struct i40e_pf *pf)
7693 {
7694         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7695         enum i40e_filter_pctype pctype;
7696         uint64_t input_set, inset_reg;
7697         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7698         int num, i;
7699
7700         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7701              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7702                 if (hw->mac.type == I40E_MAC_X722) {
7703                         if (!I40E_VALID_PCTYPE_X722(pctype))
7704                                 continue;
7705                 } else {
7706                         if (!I40E_VALID_PCTYPE(pctype))
7707                                 continue;
7708                 }
7709
7710                 input_set = i40e_get_default_input_set(pctype);
7711
7712                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7713                                                    I40E_INSET_MASK_NUM_REG);
7714                 if (num < 0)
7715                         return;
7716                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7717                                         input_set);
7718
7719                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7720                                       (uint32_t)(inset_reg & UINT32_MAX));
7721                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7722                                      (uint32_t)((inset_reg >>
7723                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7724                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7725                                       (uint32_t)(inset_reg & UINT32_MAX));
7726                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7727                                      (uint32_t)((inset_reg >>
7728                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7729
7730                 for (i = 0; i < num; i++) {
7731                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7732                                              mask_reg[i]);
7733                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7734                                              mask_reg[i]);
7735                 }
7736                 /*clear unused mask registers of the pctype */
7737                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7738                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7739                                              0);
7740                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7741                                              0);
7742                 }
7743                 I40E_WRITE_FLUSH(hw);
7744
7745                 /* store the default input set */
7746                 pf->hash_input_set[pctype] = input_set;
7747                 pf->fdir.input_set[pctype] = input_set;
7748         }
7749 }
7750
7751 int
7752 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7753                          struct rte_eth_input_set_conf *conf)
7754 {
7755         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7756         enum i40e_filter_pctype pctype;
7757         uint64_t input_set, inset_reg = 0;
7758         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7759         int ret, i, num;
7760
7761         if (!conf) {
7762                 PMD_DRV_LOG(ERR, "Invalid pointer");
7763                 return -EFAULT;
7764         }
7765         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7766             conf->op != RTE_ETH_INPUT_SET_ADD) {
7767                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7768                 return -EINVAL;
7769         }
7770
7771         if (!I40E_VALID_FLOW(conf->flow_type)) {
7772                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7773                 return -EINVAL;
7774         }
7775
7776         if (hw->mac.type == I40E_MAC_X722) {
7777                 /* get translated pctype value in fd pctype register */
7778                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7779                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7780                         conf->flow_type)));
7781         } else
7782                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7783
7784         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7785                                    conf->inset_size);
7786         if (ret) {
7787                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7788                 return -EINVAL;
7789         }
7790         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7791                                     input_set) != 0) {
7792                 PMD_DRV_LOG(ERR, "Invalid input set");
7793                 return -EINVAL;
7794         }
7795         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7796                 /* get inset value in register */
7797                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7798                 inset_reg <<= I40E_32_BIT_WIDTH;
7799                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7800                 input_set |= pf->hash_input_set[pctype];
7801         }
7802         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7803                                            I40E_INSET_MASK_NUM_REG);
7804         if (num < 0)
7805                 return -EINVAL;
7806
7807         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7808
7809         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7810                               (uint32_t)(inset_reg & UINT32_MAX));
7811         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7812                              (uint32_t)((inset_reg >>
7813                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7814
7815         for (i = 0; i < num; i++)
7816                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7817                                      mask_reg[i]);
7818         /*clear unused mask registers of the pctype */
7819         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7820                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7821                                      0);
7822         I40E_WRITE_FLUSH(hw);
7823
7824         pf->hash_input_set[pctype] = input_set;
7825         return 0;
7826 }
7827
7828 int
7829 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7830                          struct rte_eth_input_set_conf *conf)
7831 {
7832         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7833         enum i40e_filter_pctype pctype;
7834         uint64_t input_set, inset_reg = 0;
7835         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7836         int ret, i, num;
7837
7838         if (!hw || !conf) {
7839                 PMD_DRV_LOG(ERR, "Invalid pointer");
7840                 return -EFAULT;
7841         }
7842         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7843             conf->op != RTE_ETH_INPUT_SET_ADD) {
7844                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7845                 return -EINVAL;
7846         }
7847
7848         if (!I40E_VALID_FLOW(conf->flow_type)) {
7849                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7850                 return -EINVAL;
7851         }
7852
7853         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7854
7855         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7856                                    conf->inset_size);
7857         if (ret) {
7858                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7859                 return -EINVAL;
7860         }
7861         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7862                                     input_set) != 0) {
7863                 PMD_DRV_LOG(ERR, "Invalid input set");
7864                 return -EINVAL;
7865         }
7866
7867         /* get inset value in register */
7868         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7869         inset_reg <<= I40E_32_BIT_WIDTH;
7870         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7871
7872         /* Can not change the inset reg for flex payload for fdir,
7873          * it is done by writing I40E_PRTQF_FD_FLXINSET
7874          * in i40e_set_flex_mask_on_pctype.
7875          */
7876         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7877                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7878         else
7879                 input_set |= pf->fdir.input_set[pctype];
7880         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7881                                            I40E_INSET_MASK_NUM_REG);
7882         if (num < 0)
7883                 return -EINVAL;
7884
7885         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7886
7887         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7888                               (uint32_t)(inset_reg & UINT32_MAX));
7889         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7890                              (uint32_t)((inset_reg >>
7891                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7892
7893         for (i = 0; i < num; i++)
7894                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7895                                      mask_reg[i]);
7896         /*clear unused mask registers of the pctype */
7897         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7898                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7899                                      0);
7900         I40E_WRITE_FLUSH(hw);
7901
7902         pf->fdir.input_set[pctype] = input_set;
7903         return 0;
7904 }
7905
7906 static int
7907 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7908 {
7909         int ret = 0;
7910
7911         if (!hw || !info) {
7912                 PMD_DRV_LOG(ERR, "Invalid pointer");
7913                 return -EFAULT;
7914         }
7915
7916         switch (info->info_type) {
7917         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7918                 i40e_get_symmetric_hash_enable_per_port(hw,
7919                                         &(info->info.enable));
7920                 break;
7921         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7922                 ret = i40e_get_hash_filter_global_config(hw,
7923                                 &(info->info.global_conf));
7924                 break;
7925         default:
7926                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7927                                                         info->info_type);
7928                 ret = -EINVAL;
7929                 break;
7930         }
7931
7932         return ret;
7933 }
7934
7935 static int
7936 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7937 {
7938         int ret = 0;
7939
7940         if (!hw || !info) {
7941                 PMD_DRV_LOG(ERR, "Invalid pointer");
7942                 return -EFAULT;
7943         }
7944
7945         switch (info->info_type) {
7946         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7947                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7948                 break;
7949         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7950                 ret = i40e_set_hash_filter_global_config(hw,
7951                                 &(info->info.global_conf));
7952                 break;
7953         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7954                 ret = i40e_hash_filter_inset_select(hw,
7955                                                &(info->info.input_set_conf));
7956                 break;
7957
7958         default:
7959                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7960                                                         info->info_type);
7961                 ret = -EINVAL;
7962                 break;
7963         }
7964
7965         return ret;
7966 }
7967
7968 /* Operations for hash function */
7969 static int
7970 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7971                       enum rte_filter_op filter_op,
7972                       void *arg)
7973 {
7974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7975         int ret = 0;
7976
7977         switch (filter_op) {
7978         case RTE_ETH_FILTER_NOP:
7979                 break;
7980         case RTE_ETH_FILTER_GET:
7981                 ret = i40e_hash_filter_get(hw,
7982                         (struct rte_eth_hash_filter_info *)arg);
7983                 break;
7984         case RTE_ETH_FILTER_SET:
7985                 ret = i40e_hash_filter_set(hw,
7986                         (struct rte_eth_hash_filter_info *)arg);
7987                 break;
7988         default:
7989                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7990                                                                 filter_op);
7991                 ret = -ENOTSUP;
7992                 break;
7993         }
7994
7995         return ret;
7996 }
7997
7998 /*
7999  * Configure ethertype filter, which can director packet by filtering
8000  * with mac address and ether_type or only ether_type
8001  */
8002 static int
8003 i40e_ethertype_filter_set(struct i40e_pf *pf,
8004                         struct rte_eth_ethertype_filter *filter,
8005                         bool add)
8006 {
8007         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8008         struct i40e_control_filter_stats stats;
8009         uint16_t flags = 0;
8010         int ret;
8011
8012         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8013                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8014                 return -EINVAL;
8015         }
8016         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8017                 filter->ether_type == ETHER_TYPE_IPv6) {
8018                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8019                         " control packet filter.", filter->ether_type);
8020                 return -EINVAL;
8021         }
8022         if (filter->ether_type == ETHER_TYPE_VLAN)
8023                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8024                         " not supported.");
8025
8026         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8027                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8028         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8029                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8030         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8031
8032         memset(&stats, 0, sizeof(stats));
8033         ret = i40e_aq_add_rem_control_packet_filter(hw,
8034                         filter->mac_addr.addr_bytes,
8035                         filter->ether_type, flags,
8036                         pf->main_vsi->seid,
8037                         filter->queue, add, &stats, NULL);
8038
8039         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8040                          " mac_etype_used = %u, etype_used = %u,"
8041                          " mac_etype_free = %u, etype_free = %u\n",
8042                          ret, stats.mac_etype_used, stats.etype_used,
8043                          stats.mac_etype_free, stats.etype_free);
8044         if (ret < 0)
8045                 return -ENOSYS;
8046         return 0;
8047 }
8048
8049 /*
8050  * Handle operations for ethertype filter.
8051  */
8052 static int
8053 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8054                                 enum rte_filter_op filter_op,
8055                                 void *arg)
8056 {
8057         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8058         int ret = 0;
8059
8060         if (filter_op == RTE_ETH_FILTER_NOP)
8061                 return ret;
8062
8063         if (arg == NULL) {
8064                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8065                             filter_op);
8066                 return -EINVAL;
8067         }
8068
8069         switch (filter_op) {
8070         case RTE_ETH_FILTER_ADD:
8071                 ret = i40e_ethertype_filter_set(pf,
8072                         (struct rte_eth_ethertype_filter *)arg,
8073                         TRUE);
8074                 break;
8075         case RTE_ETH_FILTER_DELETE:
8076                 ret = i40e_ethertype_filter_set(pf,
8077                         (struct rte_eth_ethertype_filter *)arg,
8078                         FALSE);
8079                 break;
8080         default:
8081                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8082                 ret = -ENOSYS;
8083                 break;
8084         }
8085         return ret;
8086 }
8087
8088 static int
8089 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8090                      enum rte_filter_type filter_type,
8091                      enum rte_filter_op filter_op,
8092                      void *arg)
8093 {
8094         int ret = 0;
8095
8096         if (dev == NULL)
8097                 return -EINVAL;
8098
8099         switch (filter_type) {
8100         case RTE_ETH_FILTER_NONE:
8101                 /* For global configuration */
8102                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8103                 break;
8104         case RTE_ETH_FILTER_HASH:
8105                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8106                 break;
8107         case RTE_ETH_FILTER_MACVLAN:
8108                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8109                 break;
8110         case RTE_ETH_FILTER_ETHERTYPE:
8111                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8112                 break;
8113         case RTE_ETH_FILTER_TUNNEL:
8114                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8115                 break;
8116         case RTE_ETH_FILTER_FDIR:
8117                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8118                 break;
8119         default:
8120                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8121                                                         filter_type);
8122                 ret = -EINVAL;
8123                 break;
8124         }
8125
8126         return ret;
8127 }
8128
8129 /*
8130  * Check and enable Extended Tag.
8131  * Enabling Extended Tag is important for 40G performance.
8132  */
8133 static void
8134 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8135 {
8136         uint32_t buf = 0;
8137         int ret;
8138
8139         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8140                                       PCI_DEV_CAP_REG);
8141         if (ret < 0) {
8142                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8143                             PCI_DEV_CAP_REG);
8144                 return;
8145         }
8146         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8147                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8148                 return;
8149         }
8150
8151         buf = 0;
8152         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8153                                       PCI_DEV_CTRL_REG);
8154         if (ret < 0) {
8155                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8156                             PCI_DEV_CTRL_REG);
8157                 return;
8158         }
8159         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8160                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8161                 return;
8162         }
8163         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8164         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8165                                        PCI_DEV_CTRL_REG);
8166         if (ret < 0) {
8167                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8168                             PCI_DEV_CTRL_REG);
8169                 return;
8170         }
8171 }
8172
8173 /*
8174  * As some registers wouldn't be reset unless a global hardware reset,
8175  * hardware initialization is needed to put those registers into an
8176  * expected initial state.
8177  */
8178 static void
8179 i40e_hw_init(struct rte_eth_dev *dev)
8180 {
8181         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8182
8183         i40e_enable_extended_tag(dev);
8184
8185         /* clear the PF Queue Filter control register */
8186         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8187
8188         /* Disable symmetric hash per port */
8189         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8190 }
8191
8192 enum i40e_filter_pctype
8193 i40e_flowtype_to_pctype(uint16_t flow_type)
8194 {
8195         static const enum i40e_filter_pctype pctype_table[] = {
8196                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8197                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8198                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8199                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8200                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8201                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8202                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8203                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8204                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8205                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8206                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8207                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8208                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8209                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8210                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8211                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8212                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8213                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8214                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8215         };
8216
8217         return pctype_table[flow_type];
8218 }
8219
8220 uint16_t
8221 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8222 {
8223         static const uint16_t flowtype_table[] = {
8224                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8225                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8226                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8227 #ifdef X722_SUPPORT
8228                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8229                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8230                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8231                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8232 #endif
8233                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8234                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8235 #ifdef X722_SUPPORT
8236                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8237                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8238 #endif
8239                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8240                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8241                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8242                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8243                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8244                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8245                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8246 #ifdef X722_SUPPORT
8247                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8248                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8249                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8250                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8251 #endif
8252                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8253                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8254 #ifdef X722_SUPPORT
8255                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8256                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8257 #endif
8258                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8259                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8260                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8261                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8262                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8263         };
8264
8265         return flowtype_table[pctype];
8266 }
8267
8268 /*
8269  * On X710, performance number is far from the expectation on recent firmware
8270  * versions; on XL710, performance number is also far from the expectation on
8271  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8272  * mode is enabled and port MAC address is equal to the packet destination MAC
8273  * address. The fix for this issue may not be integrated in the following
8274  * firmware version. So the workaround in software driver is needed. It needs
8275  * to modify the initial values of 3 internal only registers for both X710 and
8276  * XL710. Note that the values for X710 or XL710 could be different, and the
8277  * workaround can be removed when it is fixed in firmware in the future.
8278  */
8279
8280 /* For both X710 and XL710 */
8281 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8282 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8283
8284 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8285 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8286
8287 /* For X722 */
8288 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8289 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8290
8291 /* For X710 */
8292 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8293 /* For XL710 */
8294 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8295 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8296
8297 static int
8298 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8299 {
8300         enum i40e_status_code status;
8301         struct i40e_aq_get_phy_abilities_resp phy_ab;
8302         int ret = -ENOTSUP;
8303
8304         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8305                                               NULL);
8306
8307         if (status)
8308                 return ret;
8309
8310         return 0;
8311 }
8312
8313 static void
8314 i40e_configure_registers(struct i40e_hw *hw)
8315 {
8316         static struct {
8317                 uint32_t addr;
8318                 uint64_t val;
8319         } reg_table[] = {
8320                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8321                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8322                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8323         };
8324         uint64_t reg;
8325         uint32_t i;
8326         int ret;
8327
8328         for (i = 0; i < RTE_DIM(reg_table); i++) {
8329                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8330                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8331                                 reg_table[i].val =
8332                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8333                         else /* For X710/XL710/XXV710 */
8334                                 reg_table[i].val =
8335                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8336                 }
8337
8338                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8339                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8340                                 reg_table[i].val =
8341                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8342                         else /* For X710/XL710/XXV710 */
8343                                 reg_table[i].val =
8344                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8345                 }
8346
8347                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8348                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8349                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8350                                 reg_table[i].val =
8351                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8352                         else /* For X710 */
8353                                 reg_table[i].val =
8354                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8355                 }
8356
8357                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8358                                                         &reg, NULL);
8359                 if (ret < 0) {
8360                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8361                                                         reg_table[i].addr);
8362                         break;
8363                 }
8364                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8365                                                 reg_table[i].addr, reg);
8366                 if (reg == reg_table[i].val)
8367                         continue;
8368
8369                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8370                                                 reg_table[i].val, NULL);
8371                 if (ret < 0) {
8372                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8373                                 "address of 0x%"PRIx32, reg_table[i].val,
8374                                                         reg_table[i].addr);
8375                         break;
8376                 }
8377                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8378                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8379         }
8380 }
8381
8382 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8383 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8384 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8385 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8386 static int
8387 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8388 {
8389         uint32_t reg;
8390         int ret;
8391
8392         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8393                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8394                 return -EINVAL;
8395         }
8396
8397         /* Configure for double VLAN RX stripping */
8398         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8399         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8400                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8401                 ret = i40e_aq_debug_write_register(hw,
8402                                                    I40E_VSI_TSR(vsi->vsi_id),
8403                                                    reg, NULL);
8404                 if (ret < 0) {
8405                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8406                                     vsi->vsi_id);
8407                         return I40E_ERR_CONFIG;
8408                 }
8409         }
8410
8411         /* Configure for double VLAN TX insertion */
8412         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8413         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8414                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8415                 ret = i40e_aq_debug_write_register(hw,
8416                                                    I40E_VSI_L2TAGSTXVALID(
8417                                                    vsi->vsi_id), reg, NULL);
8418                 if (ret < 0) {
8419                         PMD_DRV_LOG(ERR, "Failed to update "
8420                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8421                         return I40E_ERR_CONFIG;
8422                 }
8423         }
8424
8425         return 0;
8426 }
8427
8428 /**
8429  * i40e_aq_add_mirror_rule
8430  * @hw: pointer to the hardware structure
8431  * @seid: VEB seid to add mirror rule to
8432  * @dst_id: destination vsi seid
8433  * @entries: Buffer which contains the entities to be mirrored
8434  * @count: number of entities contained in the buffer
8435  * @rule_id:the rule_id of the rule to be added
8436  *
8437  * Add a mirror rule for a given veb.
8438  *
8439  **/
8440 static enum i40e_status_code
8441 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8442                         uint16_t seid, uint16_t dst_id,
8443                         uint16_t rule_type, uint16_t *entries,
8444                         uint16_t count, uint16_t *rule_id)
8445 {
8446         struct i40e_aq_desc desc;
8447         struct i40e_aqc_add_delete_mirror_rule cmd;
8448         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8449                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8450                 &desc.params.raw;
8451         uint16_t buff_len;
8452         enum i40e_status_code status;
8453
8454         i40e_fill_default_direct_cmd_desc(&desc,
8455                                           i40e_aqc_opc_add_mirror_rule);
8456         memset(&cmd, 0, sizeof(cmd));
8457
8458         buff_len = sizeof(uint16_t) * count;
8459         desc.datalen = rte_cpu_to_le_16(buff_len);
8460         if (buff_len > 0)
8461                 desc.flags |= rte_cpu_to_le_16(
8462                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8463         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8464                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8465         cmd.num_entries = rte_cpu_to_le_16(count);
8466         cmd.seid = rte_cpu_to_le_16(seid);
8467         cmd.destination = rte_cpu_to_le_16(dst_id);
8468
8469         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8470         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8471         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8472                          "rule_id = %u"
8473                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8474                          hw->aq.asq_last_status, resp->rule_id,
8475                          resp->mirror_rules_used, resp->mirror_rules_free);
8476         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8477
8478         return status;
8479 }
8480
8481 /**
8482  * i40e_aq_del_mirror_rule
8483  * @hw: pointer to the hardware structure
8484  * @seid: VEB seid to add mirror rule to
8485  * @entries: Buffer which contains the entities to be mirrored
8486  * @count: number of entities contained in the buffer
8487  * @rule_id:the rule_id of the rule to be delete
8488  *
8489  * Delete a mirror rule for a given veb.
8490  *
8491  **/
8492 static enum i40e_status_code
8493 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8494                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8495                 uint16_t count, uint16_t rule_id)
8496 {
8497         struct i40e_aq_desc desc;
8498         struct i40e_aqc_add_delete_mirror_rule cmd;
8499         uint16_t buff_len = 0;
8500         enum i40e_status_code status;
8501         void *buff = NULL;
8502
8503         i40e_fill_default_direct_cmd_desc(&desc,
8504                                           i40e_aqc_opc_delete_mirror_rule);
8505         memset(&cmd, 0, sizeof(cmd));
8506         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8507                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8508                                                           I40E_AQ_FLAG_RD));
8509                 cmd.num_entries = count;
8510                 buff_len = sizeof(uint16_t) * count;
8511                 desc.datalen = rte_cpu_to_le_16(buff_len);
8512                 buff = (void *)entries;
8513         } else
8514                 /* rule id is filled in destination field for deleting mirror rule */
8515                 cmd.destination = rte_cpu_to_le_16(rule_id);
8516
8517         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8518                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8519         cmd.seid = rte_cpu_to_le_16(seid);
8520
8521         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8522         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8523
8524         return status;
8525 }
8526
8527 /**
8528  * i40e_mirror_rule_set
8529  * @dev: pointer to the hardware structure
8530  * @mirror_conf: mirror rule info
8531  * @sw_id: mirror rule's sw_id
8532  * @on: enable/disable
8533  *
8534  * set a mirror rule.
8535  *
8536  **/
8537 static int
8538 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8539                         struct rte_eth_mirror_conf *mirror_conf,
8540                         uint8_t sw_id, uint8_t on)
8541 {
8542         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8543         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8544         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8545         struct i40e_mirror_rule *parent = NULL;
8546         uint16_t seid, dst_seid, rule_id;
8547         uint16_t i, j = 0;
8548         int ret;
8549
8550         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8551
8552         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8553                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8554                         " without veb or vfs.");
8555                 return -ENOSYS;
8556         }
8557         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8558                 PMD_DRV_LOG(ERR, "mirror table is full.");
8559                 return -ENOSPC;
8560         }
8561         if (mirror_conf->dst_pool > pf->vf_num) {
8562                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8563                                  mirror_conf->dst_pool);
8564                 return -EINVAL;
8565         }
8566
8567         seid = pf->main_vsi->veb->seid;
8568
8569         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8570                 if (sw_id <= it->index) {
8571                         mirr_rule = it;
8572                         break;
8573                 }
8574                 parent = it;
8575         }
8576         if (mirr_rule && sw_id == mirr_rule->index) {
8577                 if (on) {
8578                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8579                         return -EEXIST;
8580                 } else {
8581                         ret = i40e_aq_del_mirror_rule(hw, seid,
8582                                         mirr_rule->rule_type,
8583                                         mirr_rule->entries,
8584                                         mirr_rule->num_entries, mirr_rule->id);
8585                         if (ret < 0) {
8586                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8587                                                    " ret = %d, aq_err = %d.",
8588                                                    ret, hw->aq.asq_last_status);
8589                                 return -ENOSYS;
8590                         }
8591                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8592                         rte_free(mirr_rule);
8593                         pf->nb_mirror_rule--;
8594                         return 0;
8595                 }
8596         } else if (!on) {
8597                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8598                 return -ENOENT;
8599         }
8600
8601         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8602                                 sizeof(struct i40e_mirror_rule) , 0);
8603         if (!mirr_rule) {
8604                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8605                 return I40E_ERR_NO_MEMORY;
8606         }
8607         switch (mirror_conf->rule_type) {
8608         case ETH_MIRROR_VLAN:
8609                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8610                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8611                                 mirr_rule->entries[j] =
8612                                         mirror_conf->vlan.vlan_id[i];
8613                                 j++;
8614                         }
8615                 }
8616                 if (j == 0) {
8617                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8618                         rte_free(mirr_rule);
8619                         return -EINVAL;
8620                 }
8621                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8622                 break;
8623         case ETH_MIRROR_VIRTUAL_POOL_UP:
8624         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8625                 /* check if the specified pool bit is out of range */
8626                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8627                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8628                         rte_free(mirr_rule);
8629                         return -EINVAL;
8630                 }
8631                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8632                         if (mirror_conf->pool_mask & (1ULL << i)) {
8633                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8634                                 j++;
8635                         }
8636                 }
8637                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8638                         /* add pf vsi to entries */
8639                         mirr_rule->entries[j] = pf->main_vsi_seid;
8640                         j++;
8641                 }
8642                 if (j == 0) {
8643                         PMD_DRV_LOG(ERR, "pool is not specified.");
8644                         rte_free(mirr_rule);
8645                         return -EINVAL;
8646                 }
8647                 /* egress and ingress in aq commands means from switch but not port */
8648                 mirr_rule->rule_type =
8649                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8650                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8651                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8652                 break;
8653         case ETH_MIRROR_UPLINK_PORT:
8654                 /* egress and ingress in aq commands means from switch but not port*/
8655                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8656                 break;
8657         case ETH_MIRROR_DOWNLINK_PORT:
8658                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8659                 break;
8660         default:
8661                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8662                         mirror_conf->rule_type);
8663                 rte_free(mirr_rule);
8664                 return -EINVAL;
8665         }
8666
8667         /* If the dst_pool is equal to vf_num, consider it as PF */
8668         if (mirror_conf->dst_pool == pf->vf_num)
8669                 dst_seid = pf->main_vsi_seid;
8670         else
8671                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8672
8673         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8674                                       mirr_rule->rule_type, mirr_rule->entries,
8675                                       j, &rule_id);
8676         if (ret < 0) {
8677                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8678                                    " ret = %d, aq_err = %d.",
8679                                    ret, hw->aq.asq_last_status);
8680                 rte_free(mirr_rule);
8681                 return -ENOSYS;
8682         }
8683
8684         mirr_rule->index = sw_id;
8685         mirr_rule->num_entries = j;
8686         mirr_rule->id = rule_id;
8687         mirr_rule->dst_vsi_seid = dst_seid;
8688
8689         if (parent)
8690                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8691         else
8692                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8693
8694         pf->nb_mirror_rule++;
8695         return 0;
8696 }
8697
8698 /**
8699  * i40e_mirror_rule_reset
8700  * @dev: pointer to the device
8701  * @sw_id: mirror rule's sw_id
8702  *
8703  * reset a mirror rule.
8704  *
8705  **/
8706 static int
8707 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8708 {
8709         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8710         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8711         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8712         uint16_t seid;
8713         int ret;
8714
8715         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8716
8717         seid = pf->main_vsi->veb->seid;
8718
8719         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8720                 if (sw_id == it->index) {
8721                         mirr_rule = it;
8722                         break;
8723                 }
8724         }
8725         if (mirr_rule) {
8726                 ret = i40e_aq_del_mirror_rule(hw, seid,
8727                                 mirr_rule->rule_type,
8728                                 mirr_rule->entries,
8729                                 mirr_rule->num_entries, mirr_rule->id);
8730                 if (ret < 0) {
8731                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8732                                            " status = %d, aq_err = %d.",
8733                                            ret, hw->aq.asq_last_status);
8734                         return -ENOSYS;
8735                 }
8736                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8737                 rte_free(mirr_rule);
8738                 pf->nb_mirror_rule--;
8739         } else {
8740                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8741                 return -ENOENT;
8742         }
8743         return 0;
8744 }
8745
8746 static uint64_t
8747 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8748 {
8749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8750         uint64_t systim_cycles;
8751
8752         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8753         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8754                         << 32;
8755
8756         return systim_cycles;
8757 }
8758
8759 static uint64_t
8760 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8761 {
8762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8763         uint64_t rx_tstamp;
8764
8765         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8766         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8767                         << 32;
8768
8769         return rx_tstamp;
8770 }
8771
8772 static uint64_t
8773 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8774 {
8775         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8776         uint64_t tx_tstamp;
8777
8778         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8779         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8780                         << 32;
8781
8782         return tx_tstamp;
8783 }
8784
8785 static void
8786 i40e_start_timecounters(struct rte_eth_dev *dev)
8787 {
8788         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8789         struct i40e_adapter *adapter =
8790                         (struct i40e_adapter *)dev->data->dev_private;
8791         struct rte_eth_link link;
8792         uint32_t tsync_inc_l;
8793         uint32_t tsync_inc_h;
8794
8795         /* Get current link speed. */
8796         memset(&link, 0, sizeof(link));
8797         i40e_dev_link_update(dev, 1);
8798         rte_i40e_dev_atomic_read_link_status(dev, &link);
8799
8800         switch (link.link_speed) {
8801         case ETH_SPEED_NUM_40G:
8802                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8803                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8804                 break;
8805         case ETH_SPEED_NUM_10G:
8806                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8807                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8808                 break;
8809         case ETH_SPEED_NUM_1G:
8810                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8811                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8812                 break;
8813         default:
8814                 tsync_inc_l = 0x0;
8815                 tsync_inc_h = 0x0;
8816         }
8817
8818         /* Set the timesync increment value. */
8819         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8820         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8821
8822         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8823         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8824         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8825
8826         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8827         adapter->systime_tc.cc_shift = 0;
8828         adapter->systime_tc.nsec_mask = 0;
8829
8830         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8831         adapter->rx_tstamp_tc.cc_shift = 0;
8832         adapter->rx_tstamp_tc.nsec_mask = 0;
8833
8834         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8835         adapter->tx_tstamp_tc.cc_shift = 0;
8836         adapter->tx_tstamp_tc.nsec_mask = 0;
8837 }
8838
8839 static int
8840 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8841 {
8842         struct i40e_adapter *adapter =
8843                         (struct i40e_adapter *)dev->data->dev_private;
8844
8845         adapter->systime_tc.nsec += delta;
8846         adapter->rx_tstamp_tc.nsec += delta;
8847         adapter->tx_tstamp_tc.nsec += delta;
8848
8849         return 0;
8850 }
8851
8852 static int
8853 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8854 {
8855         uint64_t ns;
8856         struct i40e_adapter *adapter =
8857                         (struct i40e_adapter *)dev->data->dev_private;
8858
8859         ns = rte_timespec_to_ns(ts);
8860
8861         /* Set the timecounters to a new value. */
8862         adapter->systime_tc.nsec = ns;
8863         adapter->rx_tstamp_tc.nsec = ns;
8864         adapter->tx_tstamp_tc.nsec = ns;
8865
8866         return 0;
8867 }
8868
8869 static int
8870 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8871 {
8872         uint64_t ns, systime_cycles;
8873         struct i40e_adapter *adapter =
8874                         (struct i40e_adapter *)dev->data->dev_private;
8875
8876         systime_cycles = i40e_read_systime_cyclecounter(dev);
8877         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8878         *ts = rte_ns_to_timespec(ns);
8879
8880         return 0;
8881 }
8882
8883 static int
8884 i40e_timesync_enable(struct rte_eth_dev *dev)
8885 {
8886         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8887         uint32_t tsync_ctl_l;
8888         uint32_t tsync_ctl_h;
8889
8890         /* Stop the timesync system time. */
8891         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8892         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8893         /* Reset the timesync system time value. */
8894         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8895         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8896
8897         i40e_start_timecounters(dev);
8898
8899         /* Clear timesync registers. */
8900         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8901         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8902         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8903         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8904         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8905         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8906
8907         /* Enable timestamping of PTP packets. */
8908         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8909         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8910
8911         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8912         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8913         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8914
8915         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8916         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8917
8918         return 0;
8919 }
8920
8921 static int
8922 i40e_timesync_disable(struct rte_eth_dev *dev)
8923 {
8924         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8925         uint32_t tsync_ctl_l;
8926         uint32_t tsync_ctl_h;
8927
8928         /* Disable timestamping of transmitted PTP packets. */
8929         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8930         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8931
8932         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8933         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8934
8935         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8936         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8937
8938         /* Reset the timesync increment value. */
8939         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8940         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8941
8942         return 0;
8943 }
8944
8945 static int
8946 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8947                                 struct timespec *timestamp, uint32_t flags)
8948 {
8949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8950         struct i40e_adapter *adapter =
8951                 (struct i40e_adapter *)dev->data->dev_private;
8952
8953         uint32_t sync_status;
8954         uint32_t index = flags & 0x03;
8955         uint64_t rx_tstamp_cycles;
8956         uint64_t ns;
8957
8958         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8959         if ((sync_status & (1 << index)) == 0)
8960                 return -EINVAL;
8961
8962         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8963         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8964         *timestamp = rte_ns_to_timespec(ns);
8965
8966         return 0;
8967 }
8968
8969 static int
8970 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8971                                 struct timespec *timestamp)
8972 {
8973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8974         struct i40e_adapter *adapter =
8975                 (struct i40e_adapter *)dev->data->dev_private;
8976
8977         uint32_t sync_status;
8978         uint64_t tx_tstamp_cycles;
8979         uint64_t ns;
8980
8981         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8982         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8983                 return -EINVAL;
8984
8985         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8986         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8987         *timestamp = rte_ns_to_timespec(ns);
8988
8989         return 0;
8990 }
8991
8992 /*
8993  * i40e_parse_dcb_configure - parse dcb configure from user
8994  * @dev: the device being configured
8995  * @dcb_cfg: pointer of the result of parse
8996  * @*tc_map: bit map of enabled traffic classes
8997  *
8998  * Returns 0 on success, negative value on failure
8999  */
9000 static int
9001 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9002                          struct i40e_dcbx_config *dcb_cfg,
9003                          uint8_t *tc_map)
9004 {
9005         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9006         uint8_t i, tc_bw, bw_lf;
9007
9008         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9009
9010         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9011         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9012                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9013                 return -EINVAL;
9014         }
9015
9016         /* assume each tc has the same bw */
9017         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9018         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9019                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9020         /* to ensure the sum of tcbw is equal to 100 */
9021         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9022         for (i = 0; i < bw_lf; i++)
9023                 dcb_cfg->etscfg.tcbwtable[i]++;
9024
9025         /* assume each tc has the same Transmission Selection Algorithm */
9026         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9027                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9028
9029         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9030                 dcb_cfg->etscfg.prioritytable[i] =
9031                                 dcb_rx_conf->dcb_tc[i];
9032
9033         /* FW needs one App to configure HW */
9034         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9035         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9036         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9037         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9038
9039         if (dcb_rx_conf->nb_tcs == 0)
9040                 *tc_map = 1; /* tc0 only */
9041         else
9042                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9043
9044         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9045                 dcb_cfg->pfc.willing = 0;
9046                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9047                 dcb_cfg->pfc.pfcenable = *tc_map;
9048         }
9049         return 0;
9050 }
9051
9052
9053 static enum i40e_status_code
9054 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9055                               struct i40e_aqc_vsi_properties_data *info,
9056                               uint8_t enabled_tcmap)
9057 {
9058         enum i40e_status_code ret;
9059         int i, total_tc = 0;
9060         uint16_t qpnum_per_tc, bsf, qp_idx;
9061         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9062         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9063         uint16_t used_queues;
9064
9065         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9066         if (ret != I40E_SUCCESS)
9067                 return ret;
9068
9069         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9070                 if (enabled_tcmap & (1 << i))
9071                         total_tc++;
9072         }
9073         if (total_tc == 0)
9074                 total_tc = 1;
9075         vsi->enabled_tc = enabled_tcmap;
9076
9077         /* different VSI has different queues assigned */
9078         if (vsi->type == I40E_VSI_MAIN)
9079                 used_queues = dev_data->nb_rx_queues -
9080                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9081         else if (vsi->type == I40E_VSI_VMDQ2)
9082                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9083         else {
9084                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9085                 return I40E_ERR_NO_AVAILABLE_VSI;
9086         }
9087
9088         qpnum_per_tc = used_queues / total_tc;
9089         /* Number of queues per enabled TC */
9090         if (qpnum_per_tc == 0) {
9091                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9092                 return I40E_ERR_INVALID_QP_ID;
9093         }
9094         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9095                                 I40E_MAX_Q_PER_TC);
9096         bsf = rte_bsf32(qpnum_per_tc);
9097
9098         /**
9099          * Configure TC and queue mapping parameters, for enabled TC,
9100          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9101          * default queue will serve it.
9102          */
9103         qp_idx = 0;
9104         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9105                 if (vsi->enabled_tc & (1 << i)) {
9106                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9107                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9108                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9109                         qp_idx += qpnum_per_tc;
9110                 } else
9111                         info->tc_mapping[i] = 0;
9112         }
9113
9114         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9115         if (vsi->type == I40E_VSI_SRIOV) {
9116                 info->mapping_flags |=
9117                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9118                 for (i = 0; i < vsi->nb_qps; i++)
9119                         info->queue_mapping[i] =
9120                                 rte_cpu_to_le_16(vsi->base_queue + i);
9121         } else {
9122                 info->mapping_flags |=
9123                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9124                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9125         }
9126         info->valid_sections |=
9127                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9128
9129         return I40E_SUCCESS;
9130 }
9131
9132 /*
9133  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9134  * @veb: VEB to be configured
9135  * @tc_map: enabled TC bitmap
9136  *
9137  * Returns 0 on success, negative value on failure
9138  */
9139 static enum i40e_status_code
9140 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9141 {
9142         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9143         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9144         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9145         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9146         enum i40e_status_code ret = I40E_SUCCESS;
9147         int i;
9148         uint32_t bw_max;
9149
9150         /* Check if enabled_tc is same as existing or new TCs */
9151         if (veb->enabled_tc == tc_map)
9152                 return ret;
9153
9154         /* configure tc bandwidth */
9155         memset(&veb_bw, 0, sizeof(veb_bw));
9156         veb_bw.tc_valid_bits = tc_map;
9157         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9158         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9159                 if (tc_map & BIT_ULL(i))
9160                         veb_bw.tc_bw_share_credits[i] = 1;
9161         }
9162         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9163                                                    &veb_bw, NULL);
9164         if (ret) {
9165                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9166                                   " per TC failed = %d",
9167                                   hw->aq.asq_last_status);
9168                 return ret;
9169         }
9170
9171         memset(&ets_query, 0, sizeof(ets_query));
9172         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9173                                                    &ets_query, NULL);
9174         if (ret != I40E_SUCCESS) {
9175                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9176                                  " configuration %u", hw->aq.asq_last_status);
9177                 return ret;
9178         }
9179         memset(&bw_query, 0, sizeof(bw_query));
9180         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9181                                                   &bw_query, NULL);
9182         if (ret != I40E_SUCCESS) {
9183                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9184                                  " configuration %u", hw->aq.asq_last_status);
9185                 return ret;
9186         }
9187
9188         /* store and print out BW info */
9189         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9190         veb->bw_info.bw_max = ets_query.tc_bw_max;
9191         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9192         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9193         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9194                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9195                      I40E_16_BIT_WIDTH);
9196         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9197                 veb->bw_info.bw_ets_share_credits[i] =
9198                                 bw_query.tc_bw_share_credits[i];
9199                 veb->bw_info.bw_ets_credits[i] =
9200                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9201                 /* 4 bits per TC, 4th bit is reserved */
9202                 veb->bw_info.bw_ets_max[i] =
9203                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9204                                   RTE_LEN2MASK(3, uint8_t));
9205                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9206                             veb->bw_info.bw_ets_share_credits[i]);
9207                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9208                             veb->bw_info.bw_ets_credits[i]);
9209                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9210                             veb->bw_info.bw_ets_max[i]);
9211         }
9212
9213         veb->enabled_tc = tc_map;
9214
9215         return ret;
9216 }
9217
9218
9219 /*
9220  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9221  * @vsi: VSI to be configured
9222  * @tc_map: enabled TC bitmap
9223  *
9224  * Returns 0 on success, negative value on failure
9225  */
9226 static enum i40e_status_code
9227 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9228 {
9229         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9230         struct i40e_vsi_context ctxt;
9231         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9232         enum i40e_status_code ret = I40E_SUCCESS;
9233         int i;
9234
9235         /* Check if enabled_tc is same as existing or new TCs */
9236         if (vsi->enabled_tc == tc_map)
9237                 return ret;
9238
9239         /* configure tc bandwidth */
9240         memset(&bw_data, 0, sizeof(bw_data));
9241         bw_data.tc_valid_bits = tc_map;
9242         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9243         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9244                 if (tc_map & BIT_ULL(i))
9245                         bw_data.tc_bw_credits[i] = 1;
9246         }
9247         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9248         if (ret) {
9249                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9250                         " per TC failed = %d",
9251                         hw->aq.asq_last_status);
9252                 goto out;
9253         }
9254         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9255                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9256
9257         /* Update Queue Pairs Mapping for currently enabled UPs */
9258         ctxt.seid = vsi->seid;
9259         ctxt.pf_num = hw->pf_id;
9260         ctxt.vf_num = 0;
9261         ctxt.uplink_seid = vsi->uplink_seid;
9262         ctxt.info = vsi->info;
9263         i40e_get_cap(hw);
9264         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9265         if (ret)
9266                 goto out;
9267
9268         /* Update the VSI after updating the VSI queue-mapping information */
9269         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9270         if (ret) {
9271                 PMD_INIT_LOG(ERR, "Failed to configure "
9272                             "TC queue mapping = %d",
9273                             hw->aq.asq_last_status);
9274                 goto out;
9275         }
9276         /* update the local VSI info with updated queue map */
9277         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9278                                         sizeof(vsi->info.tc_mapping));
9279         (void)rte_memcpy(&vsi->info.queue_mapping,
9280                         &ctxt.info.queue_mapping,
9281                 sizeof(vsi->info.queue_mapping));
9282         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9283         vsi->info.valid_sections = 0;
9284
9285         /* query and update current VSI BW information */
9286         ret = i40e_vsi_get_bw_config(vsi);
9287         if (ret) {
9288                 PMD_INIT_LOG(ERR,
9289                          "Failed updating vsi bw info, err %s aq_err %s",
9290                          i40e_stat_str(hw, ret),
9291                          i40e_aq_str(hw, hw->aq.asq_last_status));
9292                 goto out;
9293         }
9294
9295         vsi->enabled_tc = tc_map;
9296
9297 out:
9298         return ret;
9299 }
9300
9301 /*
9302  * i40e_dcb_hw_configure - program the dcb setting to hw
9303  * @pf: pf the configuration is taken on
9304  * @new_cfg: new configuration
9305  * @tc_map: enabled TC bitmap
9306  *
9307  * Returns 0 on success, negative value on failure
9308  */
9309 static enum i40e_status_code
9310 i40e_dcb_hw_configure(struct i40e_pf *pf,
9311                       struct i40e_dcbx_config *new_cfg,
9312                       uint8_t tc_map)
9313 {
9314         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9315         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9316         struct i40e_vsi *main_vsi = pf->main_vsi;
9317         struct i40e_vsi_list *vsi_list;
9318         enum i40e_status_code ret;
9319         int i;
9320         uint32_t val;
9321
9322         /* Use the FW API if FW > v4.4*/
9323         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9324               (hw->aq.fw_maj_ver >= 5))) {
9325                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9326                                   " to configure DCB");
9327                 return I40E_ERR_FIRMWARE_API_VERSION;
9328         }
9329
9330         /* Check if need reconfiguration */
9331         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9332                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9333                 return I40E_SUCCESS;
9334         }
9335
9336         /* Copy the new config to the current config */
9337         *old_cfg = *new_cfg;
9338         old_cfg->etsrec = old_cfg->etscfg;
9339         ret = i40e_set_dcb_config(hw);
9340         if (ret) {
9341                 PMD_INIT_LOG(ERR,
9342                          "Set DCB Config failed, err %s aq_err %s\n",
9343                          i40e_stat_str(hw, ret),
9344                          i40e_aq_str(hw, hw->aq.asq_last_status));
9345                 return ret;
9346         }
9347         /* set receive Arbiter to RR mode and ETS scheme by default */
9348         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9349                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9350                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9351                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9352                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9353                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9354                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9355                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9356                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9357                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9358                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9359                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9360                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9361         }
9362         /* get local mib to check whether it is configured correctly */
9363         /* IEEE mode */
9364         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9365         /* Get Local DCB Config */
9366         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9367                                      &hw->local_dcbx_config);
9368
9369         /* if Veb is created, need to update TC of it at first */
9370         if (main_vsi->veb) {
9371                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9372                 if (ret)
9373                         PMD_INIT_LOG(WARNING,
9374                                  "Failed configuring TC for VEB seid=%d\n",
9375                                  main_vsi->veb->seid);
9376         }
9377         /* Update each VSI */
9378         i40e_vsi_config_tc(main_vsi, tc_map);
9379         if (main_vsi->veb) {
9380                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9381                         /* Beside main VSI and VMDQ VSIs, only enable default
9382                          * TC for other VSIs
9383                          */
9384                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9385                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9386                                                          tc_map);
9387                         else
9388                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9389                                                          I40E_DEFAULT_TCMAP);
9390                         if (ret)
9391                                 PMD_INIT_LOG(WARNING,
9392                                          "Failed configuring TC for VSI seid=%d\n",
9393                                          vsi_list->vsi->seid);
9394                         /* continue */
9395                 }
9396         }
9397         return I40E_SUCCESS;
9398 }
9399
9400 /*
9401  * i40e_dcb_init_configure - initial dcb config
9402  * @dev: device being configured
9403  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9404  *
9405  * Returns 0 on success, negative value on failure
9406  */
9407 static int
9408 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9409 {
9410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9412         int ret = 0;
9413
9414         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9415                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9416                 return -ENOTSUP;
9417         }
9418
9419         /* DCB initialization:
9420          * Update DCB configuration from the Firmware and configure
9421          * LLDP MIB change event.
9422          */
9423         if (sw_dcb == TRUE) {
9424                 ret = i40e_init_dcb(hw);
9425                 /* If lldp agent is stopped, the return value from
9426                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9427                  * adminq status. Otherwise, it should return success.
9428                  */
9429                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9430                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9431                         memset(&hw->local_dcbx_config, 0,
9432                                 sizeof(struct i40e_dcbx_config));
9433                         /* set dcb default configuration */
9434                         hw->local_dcbx_config.etscfg.willing = 0;
9435                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9436                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9437                         hw->local_dcbx_config.etscfg.tsatable[0] =
9438                                                 I40E_IEEE_TSA_ETS;
9439                         hw->local_dcbx_config.etsrec =
9440                                 hw->local_dcbx_config.etscfg;
9441                         hw->local_dcbx_config.pfc.willing = 0;
9442                         hw->local_dcbx_config.pfc.pfccap =
9443                                                 I40E_MAX_TRAFFIC_CLASS;
9444                         /* FW needs one App to configure HW */
9445                         hw->local_dcbx_config.numapps = 1;
9446                         hw->local_dcbx_config.app[0].selector =
9447                                                 I40E_APP_SEL_ETHTYPE;
9448                         hw->local_dcbx_config.app[0].priority = 3;
9449                         hw->local_dcbx_config.app[0].protocolid =
9450                                                 I40E_APP_PROTOID_FCOE;
9451                         ret = i40e_set_dcb_config(hw);
9452                         if (ret) {
9453                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9454                                         " err = %d, aq_err = %d.", ret,
9455                                           hw->aq.asq_last_status);
9456                                 return -ENOSYS;
9457                         }
9458                 } else {
9459                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9460                                           " err = %d, aq_err = %d.", ret,
9461                                           hw->aq.asq_last_status);
9462                         return -ENOTSUP;
9463                 }
9464         } else {
9465                 ret = i40e_aq_start_lldp(hw, NULL);
9466                 if (ret != I40E_SUCCESS)
9467                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9468
9469                 ret = i40e_init_dcb(hw);
9470                 if (!ret) {
9471                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9472                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9473                                                   " DCBX offload.");
9474                                 return -ENOTSUP;
9475                         }
9476                 } else {
9477                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9478                                           " aq_err = %d.", ret,
9479                                           hw->aq.asq_last_status);
9480                         return -ENOTSUP;
9481                 }
9482         }
9483         return 0;
9484 }
9485
9486 /*
9487  * i40e_dcb_setup - setup dcb related config
9488  * @dev: device being configured
9489  *
9490  * Returns 0 on success, negative value on failure
9491  */
9492 static int
9493 i40e_dcb_setup(struct rte_eth_dev *dev)
9494 {
9495         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9496         struct i40e_dcbx_config dcb_cfg;
9497         uint8_t tc_map = 0;
9498         int ret = 0;
9499
9500         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9501                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9502                 return -ENOTSUP;
9503         }
9504
9505         if (pf->vf_num != 0)
9506                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9507
9508         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9509         if (ret) {
9510                 PMD_INIT_LOG(ERR, "invalid dcb config");
9511                 return -EINVAL;
9512         }
9513         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9514         if (ret) {
9515                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9516                 return -ENOSYS;
9517         }
9518
9519         return 0;
9520 }
9521
9522 static int
9523 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9524                       struct rte_eth_dcb_info *dcb_info)
9525 {
9526         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9527         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9528         struct i40e_vsi *vsi = pf->main_vsi;
9529         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9530         uint16_t bsf, tc_mapping;
9531         int i, j = 0;
9532
9533         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9534                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9535         else
9536                 dcb_info->nb_tcs = 1;
9537         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9538                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9539         for (i = 0; i < dcb_info->nb_tcs; i++)
9540                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9541
9542         /* get queue mapping if vmdq is disabled */
9543         if (!pf->nb_cfg_vmdq_vsi) {
9544                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9545                         if (!(vsi->enabled_tc & (1 << i)))
9546                                 continue;
9547                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9548                         dcb_info->tc_queue.tc_rxq[j][i].base =
9549                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9550                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9551                         dcb_info->tc_queue.tc_txq[j][i].base =
9552                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9553                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9554                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9555                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9556                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9557                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9558                 }
9559                 return 0;
9560         }
9561
9562         /* get queue mapping if vmdq is enabled */
9563         do {
9564                 vsi = pf->vmdq[j].vsi;
9565                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9566                         if (!(vsi->enabled_tc & (1 << i)))
9567                                 continue;
9568                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9569                         dcb_info->tc_queue.tc_rxq[j][i].base =
9570                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9571                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9572                         dcb_info->tc_queue.tc_txq[j][i].base =
9573                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9574                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9575                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9576                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9577                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9578                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9579                 }
9580                 j++;
9581         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9582         return 0;
9583 }
9584
9585 static int
9586 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9587 {
9588         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9590         uint16_t interval =
9591                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9592         uint16_t msix_intr;
9593
9594         msix_intr = intr_handle->intr_vec[queue_id];
9595         if (msix_intr == I40E_MISC_VEC_ID)
9596                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9597                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9598                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9599                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9600                                (interval <<
9601                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9602         else
9603                 I40E_WRITE_REG(hw,
9604                                I40E_PFINT_DYN_CTLN(msix_intr -
9605                                                    I40E_RX_VEC_START),
9606                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9607                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9608                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9609                                (interval <<
9610                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9611
9612         I40E_WRITE_FLUSH(hw);
9613         rte_intr_enable(&dev->pci_dev->intr_handle);
9614
9615         return 0;
9616 }
9617
9618 static int
9619 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9620 {
9621         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9622         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9623         uint16_t msix_intr;
9624
9625         msix_intr = intr_handle->intr_vec[queue_id];
9626         if (msix_intr == I40E_MISC_VEC_ID)
9627                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9628         else
9629                 I40E_WRITE_REG(hw,
9630                                I40E_PFINT_DYN_CTLN(msix_intr -
9631                                                    I40E_RX_VEC_START),
9632                                0);
9633         I40E_WRITE_FLUSH(hw);
9634
9635         return 0;
9636 }
9637
9638 static int i40e_get_regs(struct rte_eth_dev *dev,
9639                          struct rte_dev_reg_info *regs)
9640 {
9641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9642         uint32_t *ptr_data = regs->data;
9643         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9644         const struct i40e_reg_info *reg_info;
9645
9646         if (ptr_data == NULL) {
9647                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9648                 regs->width = sizeof(uint32_t);
9649                 return 0;
9650         }
9651
9652         /* The first few registers have to be read using AQ operations */
9653         reg_idx = 0;
9654         while (i40e_regs_adminq[reg_idx].name) {
9655                 reg_info = &i40e_regs_adminq[reg_idx++];
9656                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9657                         for (arr_idx2 = 0;
9658                                         arr_idx2 <= reg_info->count2;
9659                                         arr_idx2++) {
9660                                 reg_offset = arr_idx * reg_info->stride1 +
9661                                         arr_idx2 * reg_info->stride2;
9662                                 reg_offset += reg_info->base_addr;
9663                                 ptr_data[reg_offset >> 2] =
9664                                         i40e_read_rx_ctl(hw, reg_offset);
9665                         }
9666         }
9667
9668         /* The remaining registers can be read using primitives */
9669         reg_idx = 0;
9670         while (i40e_regs_others[reg_idx].name) {
9671                 reg_info = &i40e_regs_others[reg_idx++];
9672                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9673                         for (arr_idx2 = 0;
9674                                         arr_idx2 <= reg_info->count2;
9675                                         arr_idx2++) {
9676                                 reg_offset = arr_idx * reg_info->stride1 +
9677                                         arr_idx2 * reg_info->stride2;
9678                                 reg_offset += reg_info->base_addr;
9679                                 ptr_data[reg_offset >> 2] =
9680                                         I40E_READ_REG(hw, reg_offset);
9681                         }
9682         }
9683
9684         return 0;
9685 }
9686
9687 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9688 {
9689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9690
9691         /* Convert word count to byte count */
9692         return hw->nvm.sr_size << 1;
9693 }
9694
9695 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9696                            struct rte_dev_eeprom_info *eeprom)
9697 {
9698         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9699         uint16_t *data = eeprom->data;
9700         uint16_t offset, length, cnt_words;
9701         int ret_code;
9702
9703         offset = eeprom->offset >> 1;
9704         length = eeprom->length >> 1;
9705         cnt_words = length;
9706
9707         if (offset > hw->nvm.sr_size ||
9708                 offset + length > hw->nvm.sr_size) {
9709                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9710                 return -EINVAL;
9711         }
9712
9713         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9714
9715         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9716         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9717                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9718                 return -EIO;
9719         }
9720
9721         return 0;
9722 }
9723
9724 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9725                                       struct ether_addr *mac_addr)
9726 {
9727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9728
9729         if (!is_valid_assigned_ether_addr(mac_addr)) {
9730                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9731                 return;
9732         }
9733
9734         /* Flags: 0x3 updates port address */
9735         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9736 }
9737
9738 static int
9739 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9740 {
9741         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9742         struct rte_eth_dev_data *dev_data = pf->dev_data;
9743         uint32_t frame_size = mtu + ETHER_HDR_LEN
9744                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9745         int ret = 0;
9746
9747         /* check if mtu is within the allowed range */
9748         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9749                 return -EINVAL;
9750
9751         /* mtu setting is forbidden if port is start */
9752         if (dev_data->dev_started) {
9753                 PMD_DRV_LOG(ERR,
9754                             "port %d must be stopped before configuration\n",
9755                             dev_data->port_id);
9756                 return -EBUSY;
9757         }
9758
9759         if (frame_size > ETHER_MAX_LEN)
9760                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9761         else
9762                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9763
9764         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9765
9766         return ret;
9767 }