drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 458         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 459         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 460         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 461         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 462         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 463         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct eth_dev_ops i40e_eth_dev_ops = {
 482         .dev_configure                = i40e_dev_configure,
 483         .dev_start                    = i40e_dev_start,
 484         .dev_stop                     = i40e_dev_stop,
 485         .dev_close                    = i40e_dev_close,
 486         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 487         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 488         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 489         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 490         .dev_set_link_up              = i40e_dev_set_link_up,
 491         .dev_set_link_down            = i40e_dev_set_link_down,
 492         .link_update                  = i40e_dev_link_update,
 493         .stats_get                    = i40e_dev_stats_get,
 494         .xstats_get                   = i40e_dev_xstats_get,
 495         .xstats_get_names             = i40e_dev_xstats_get_names,
 496         .stats_reset                  = i40e_dev_stats_reset,
 497         .xstats_reset                 = i40e_dev_stats_reset,
 498         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 499         .dev_infos_get                = i40e_dev_info_get,
 500         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 501         .vlan_filter_set              = i40e_vlan_filter_set,
 502         .vlan_tpid_set                = i40e_vlan_tpid_set,
 503         .vlan_offload_set             = i40e_vlan_offload_set,
 504         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 505         .vlan_pvid_set                = i40e_vlan_pvid_set,
 506         .rx_queue_start               = i40e_dev_rx_queue_start,
 507         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 508         .tx_queue_start               = i40e_dev_tx_queue_start,
 509         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 510         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 511         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 512         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 513         .rx_queue_release             = i40e_dev_rx_queue_release,
 514         .rx_queue_count               = i40e_dev_rx_queue_count,
 515         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 516         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 517         .tx_queue_release             = i40e_dev_tx_queue_release,
 518         .dev_led_on                   = i40e_dev_led_on,
 519         .dev_led_off                  = i40e_dev_led_off,
 520         .flow_ctrl_get                = i40e_flow_ctrl_get,
 521         .flow_ctrl_set                = i40e_flow_ctrl_set,
 522         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 523         .mac_addr_add                 = i40e_macaddr_add,
 524         .mac_addr_remove              = i40e_macaddr_remove,
 525         .reta_update                  = i40e_dev_rss_reta_update,
 526         .reta_query                   = i40e_dev_rss_reta_query,
 527         .rss_hash_update              = i40e_dev_rss_hash_update,
 528         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 529         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 530         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 531         .filter_ctrl                  = i40e_dev_filter_ctrl,
 532         .rxq_info_get                 = i40e_rxq_info_get,
 533         .txq_info_get                 = i40e_txq_info_get,
 534         .mirror_rule_set              = i40e_mirror_rule_set,
 535         .mirror_rule_reset            = i40e_mirror_rule_reset,
 536         .timesync_enable              = i40e_timesync_enable,
 537         .timesync_disable             = i40e_timesync_disable,
 538         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 540         .get_dcb_info                 = i40e_dev_get_dcb_info,
 541         .timesync_adjust_time         = i40e_timesync_adjust_time,
 542         .timesync_read_time           = i40e_timesync_read_time,
 543         .timesync_write_time          = i40e_timesync_write_time,
 544         .get_reg                      = i40e_get_regs,
 545         .get_eeprom_length            = i40e_get_eeprom_length,
 546         .get_eeprom                   = i40e_get_eeprom,
 547         .mac_addr_set                 = i40e_set_default_mac_addr,
 548         .mtu_set                      = i40e_dev_mtu_set,
 549 };
 550
 551 /* store statistics names and its offset in stats structure */
 552 struct rte_i40e_xstats_name_off {
 553         char name[RTE_ETH_XSTATS_NAME_SIZE];
 554         unsigned offset;
 555 };
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 558         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 559         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 560         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 561         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 562         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 563                 rx_unknown_protocol)},
 564         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 565         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 566         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 567         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 568 };
 569
 570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 571                 sizeof(rte_i40e_stats_strings[0]))
 572
 573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 574         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 575                 tx_dropped_link_down)},
 576         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 577         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 578                 illegal_bytes)},
 579         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 580         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 581                 mac_local_faults)},
 582         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 583                 mac_remote_faults)},
 584         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_length_errors)},
 586         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 587         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 588         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 589         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 590         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 591         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 rx_size_127)},
 593         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 rx_size_255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 rx_size_511)},
 597         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 rx_size_1023)},
 599         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_1522)},
 601         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_big)},
 603         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 604                 rx_undersize)},
 605         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 606                 rx_oversize)},
 607         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 608                 mac_short_packet_dropped)},
 609         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 610                 rx_fragments)},
 611         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 612         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 614                 tx_size_127)},
 615         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 616                 tx_size_255)},
 617         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 618                 tx_size_511)},
 619         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 620                 tx_size_1023)},
 621         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_1522)},
 623         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_big)},
 625         {"rx_flow_director_atr_match_packets",
 626                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 627         {"rx_flow_director_sb_match_packets",
 628                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 629         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 630                 tx_lpi_status)},
 631         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 632                 rx_lpi_status)},
 633         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 634                 tx_lpi_count)},
 635         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 636                 rx_lpi_count)},
 637 };
 638
 639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 640                 sizeof(rte_i40e_hw_port_strings[0]))
 641
 642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 643         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 644                 priority_xon_rx)},
 645         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 646                 priority_xoff_rx)},
 647 };
 648
 649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 650                 sizeof(rte_i40e_rxq_prio_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_tx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_tx)},
 657         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_2_xoff)},
 659 };
 660
 661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 662                 sizeof(rte_i40e_txq_prio_strings[0]))
 663
 664 static struct eth_driver rte_i40e_pmd = {
 665         .pci_drv = {
 666                 .name = "rte_i40e_pmd",
 667                 .id_table = pci_id_i40e_map,
 668                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 669                         RTE_PCI_DRV_DETACHABLE,
 670         },
 671         .eth_dev_init = eth_i40e_dev_init,
 672         .eth_dev_uninit = eth_i40e_dev_uninit,
 673         .dev_private_size = sizeof(struct i40e_adapter),
 674 };
 675
 676 static inline int
 677 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 678                                      struct rte_eth_link *link)
 679 {
 680         struct rte_eth_link *dst = link;
 681         struct rte_eth_link *src = &(dev->data->dev_link);
 682
 683         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 684                                         *(uint64_t *)src) == 0)
 685                 return -1;
 686
 687         return 0;
 688 }
 689
 690 static inline int
 691 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 692                                       struct rte_eth_link *link)
 693 {
 694         struct rte_eth_link *dst = &(dev->data->dev_link);
 695         struct rte_eth_link *src = link;
 696
 697         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 698                                         *(uint64_t *)src) == 0)
 699                 return -1;
 700
 701         return 0;
 702 }
 703
 704 /*
 705  * Driver initialization routine.
 706  * Invoked once at EAL init time.
 707  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 708  */
 709 static int
 710 rte_i40e_pmd_init(const char *name __rte_unused,
 711                   const char *params __rte_unused)
 712 {
 713         PMD_INIT_FUNC_TRACE();
 714         rte_eth_driver_register(&rte_i40e_pmd);
 715
 716         return 0;
 717 }
 718
 719 static struct rte_driver rte_i40e_driver = {
 720         .type = PMD_PDEV,
 721         .init = rte_i40e_pmd_init,
 722 };
 723
 724 PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
 725 DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
 726
 727 /*
 728  * Initialize registers for flexible payload, which should be set by NVM.
 729  * This should be removed from code once it is fixed in NVM.
 730  */
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737
 738 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 739 {
 740         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 741         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 742         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 743         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 744         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 745         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 746         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 747         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 748         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 749         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 750
 751         /* GLQF_PIT Registers */
 752         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 753         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 754 }
 755
 756 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 757
 758 /*
 759  * Add a ethertype filter to drop all flow control frames transmitted
 760  * from VSIs.
 761 */
 762 static void
 763 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 764 {
 765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 766         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 767                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 768                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 769         int ret;
 770
 771         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 772                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 773                                 pf->main_vsi_seid, 0,
 774                                 TRUE, NULL, NULL);
 775         if (ret)
 776                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 777                                   " frames from VSIs.");
 778 }
 779
 780 static int
 781 floating_veb_list_handler(__rte_unused const char *key,
 782                           const char *floating_veb_value,
 783                           void *opaque)
 784 {
 785         int idx = 0;
 786         unsigned int count = 0;
 787         char *end = NULL;
 788         int min, max;
 789         bool *vf_floating_veb = opaque;
 790
 791         while (isblank(*floating_veb_value))
 792                 floating_veb_value++;
 793
 794         /* Reset floating VEB configuration for VFs */
 795         for (idx = 0; idx < I40E_MAX_VF; idx++)
 796                 vf_floating_veb[idx] = false;
 797
 798         min = I40E_MAX_VF;
 799         do {
 800                 while (isblank(*floating_veb_value))
 801                         floating_veb_value++;
 802                 if (*floating_veb_value == '\0')
 803                         return -1;
 804                 errno = 0;
 805                 idx = strtoul(floating_veb_value, &end, 10);
 806                 if (errno || end == NULL)
 807                         return -1;
 808                 while (isblank(*end))
 809                         end++;
 810                 if (*end == '-') {
 811                         min = idx;
 812                 } else if ((*end == ';') || (*end == '\0')) {
 813                         max = idx;
 814                         if (min == I40E_MAX_VF)
 815                                 min = idx;
 816                         if (max >= I40E_MAX_VF)
 817                                 max = I40E_MAX_VF - 1;
 818                         for (idx = min; idx <= max; idx++) {
 819                                 vf_floating_veb[idx] = true;
 820                                 count++;
 821                         }
 822                         min = I40E_MAX_VF;
 823                 } else {
 824                         return -1;
 825                 }
 826                 floating_veb_value = end + 1;
 827         } while (*end != '\0');
 828
 829         if (count == 0)
 830                 return -1;
 831
 832         return 0;
 833 }
 834
 835 static void
 836 config_vf_floating_veb(struct rte_devargs *devargs,
 837                        uint16_t floating_veb,
 838                        bool *vf_floating_veb)
 839 {
 840         struct rte_kvargs *kvlist;
 841         int i;
 842         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 843
 844         if (!floating_veb)
 845                 return;
 846         /* All the VFs attach to the floating VEB by default
 847          * when the floating VEB is enabled.
 848          */
 849         for (i = 0; i < I40E_MAX_VF; i++)
 850                 vf_floating_veb[i] = true;
 851
 852         if (devargs == NULL)
 853                 return;
 854
 855         kvlist = rte_kvargs_parse(devargs->args, NULL);
 856         if (kvlist == NULL)
 857                 return;
 858
 859         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 860                 rte_kvargs_free(kvlist);
 861                 return;
 862         }
 863         /* When the floating_veb_list parameter exists, all the VFs
 864          * will attach to the legacy VEB firstly, then configure VFs
 865          * to the floating VEB according to the floating_veb_list.
 866          */
 867         if (rte_kvargs_process(kvlist, floating_veb_list,
 868                                floating_veb_list_handler,
 869                                vf_floating_veb) < 0) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         rte_kvargs_free(kvlist);
 874 }
 875
 876 static int
 877 i40e_check_floating_handler(__rte_unused const char *key,
 878                             const char *value,
 879                             __rte_unused void *opaque)
 880 {
 881         if (strcmp(value, "1"))
 882                 return -1;
 883
 884         return 0;
 885 }
 886
 887 static int
 888 is_floating_veb_supported(struct rte_devargs *devargs)
 889 {
 890         struct rte_kvargs *kvlist;
 891         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 892
 893         if (devargs == NULL)
 894                 return 0;
 895
 896         kvlist = rte_kvargs_parse(devargs->args, NULL);
 897         if (kvlist == NULL)
 898                 return 0;
 899
 900         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 901                 rte_kvargs_free(kvlist);
 902                 return 0;
 903         }
 904         /* Floating VEB is enabled when there's key-value:
 905          * enable_floating_veb=1
 906          */
 907         if (rte_kvargs_process(kvlist, floating_veb_key,
 908                                i40e_check_floating_handler, NULL) < 0) {
 909                 rte_kvargs_free(kvlist);
 910                 return 0;
 911         }
 912         rte_kvargs_free(kvlist);
 913
 914         return 1;
 915 }
 916
 917 static void
 918 config_floating_veb(struct rte_eth_dev *dev)
 919 {
 920         struct rte_pci_device *pci_dev = dev->pci_dev;
 921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 925
 926         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 927                 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
 928                 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
 929                                        pf->floating_veb_list);
 930         } else {
 931                 pf->floating_veb = false;
 932         }
 933 }
 934
 935 static int
 936 eth_i40e_dev_init(struct rte_eth_dev *dev)
 937 {
 938         struct rte_pci_device *pci_dev;
 939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 941         struct i40e_vsi *vsi;
 942         int ret;
 943         uint32_t len;
 944         uint8_t aq_fail = 0;
 945
 946         PMD_INIT_FUNC_TRACE();
 947
 948         dev->dev_ops = &i40e_eth_dev_ops;
 949         dev->rx_pkt_burst = i40e_recv_pkts;
 950         dev->tx_pkt_burst = i40e_xmit_pkts;
 951
 952         /* for secondary processes, we don't initialise any further as primary
 953          * has already done this work. Only check we don't need a different
 954          * RX function */
 955         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 956                 i40e_set_rx_function(dev);
 957                 i40e_set_tx_function(dev);
 958                 return 0;
 959         }
 960         pci_dev = dev->pci_dev;
 961
 962         rte_eth_copy_pci_info(dev, pci_dev);
 963
 964         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 965         pf->adapter->eth_dev = dev;
 966         pf->dev_data = dev->data;
 967
 968         hw->back = I40E_PF_TO_ADAPTER(pf);
 969         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 970         if (!hw->hw_addr) {
 971                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 972                              "as address is NULL");
 973                 return -ENODEV;
 974         }
 975
 976         hw->vendor_id = pci_dev->id.vendor_id;
 977         hw->device_id = pci_dev->id.device_id;
 978         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 979         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 980         hw->bus.device = pci_dev->addr.devid;
 981         hw->bus.func = pci_dev->addr.function;
 982         hw->adapter_stopped = 0;
 983
 984         /* Make sure all is clean before doing PF reset */
 985         i40e_clear_hw(hw);
 986
 987         /* Initialize the hardware */
 988         i40e_hw_init(dev);
 989
 990         /* Reset here to make sure all is clean for each PF */
 991         ret = i40e_pf_reset(hw);
 992         if (ret) {
 993                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 994                 return ret;
 995         }
 996
 997         /* Initialize the shared code (base driver) */
 998         ret = i40e_init_shared_code(hw);
 999         if (ret) {
1000                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1001                 return ret;
1002         }
1003
1004         /*
1005          * To work around the NVM issue,initialize registers
1006          * for flexible payload by software.
1007          * It should be removed once issues are fixed in NVM.
1008          */
1009         i40e_flex_payload_reg_init(hw);
1010
1011         /* Initialize the input set for filters (hash and fd) to default value */
1012         i40e_filter_input_set_init(pf);
1013
1014         /* Initialize the parameters for adminq */
1015         i40e_init_adminq_parameter(hw);
1016         ret = i40e_init_adminq(hw);
1017         if (ret != I40E_SUCCESS) {
1018                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1019                 return -EIO;
1020         }
1021         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1022                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1023                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1024                      ((hw->nvm.version >> 12) & 0xf),
1025                      ((hw->nvm.version >> 4) & 0xff),
1026                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1027
1028         /* Need the special FW version to support floating VEB */
1029         config_floating_veb(dev);
1030         /* Clear PXE mode */
1031         i40e_clear_pxe_mode(hw);
1032
1033         /*
1034          * On X710, performance number is far from the expectation on recent
1035          * firmware versions. The fix for this issue may not be integrated in
1036          * the following firmware version. So the workaround in software driver
1037          * is needed. It needs to modify the initial values of 3 internal only
1038          * registers. Note that the workaround can be removed when it is fixed
1039          * in firmware in the future.
1040          */
1041         i40e_configure_registers(hw);
1042
1043         /* Get hw capabilities */
1044         ret = i40e_get_cap(hw);
1045         if (ret != I40E_SUCCESS) {
1046                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1047                 goto err_get_capabilities;
1048         }
1049
1050         /* Initialize parameters for PF */
1051         ret = i40e_pf_parameter_init(dev);
1052         if (ret != 0) {
1053                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1054                 goto err_parameter_init;
1055         }
1056
1057         /* Initialize the queue management */
1058         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1059         if (ret < 0) {
1060                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1061                 goto err_qp_pool_init;
1062         }
1063         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1064                                 hw->func_caps.num_msix_vectors - 1);
1065         if (ret < 0) {
1066                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1067                 goto err_msix_pool_init;
1068         }
1069
1070         /* Initialize lan hmc */
1071         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1072                                 hw->func_caps.num_rx_qp, 0, 0);
1073         if (ret != I40E_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1075                 goto err_init_lan_hmc;
1076         }
1077
1078         /* Configure lan hmc */
1079         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1080         if (ret != I40E_SUCCESS) {
1081                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1082                 goto err_configure_lan_hmc;
1083         }
1084
1085         /* Get and check the mac address */
1086         i40e_get_mac_addr(hw, hw->mac.addr);
1087         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "mac address is not valid");
1089                 ret = -EIO;
1090                 goto err_get_mac_addr;
1091         }
1092         /* Copy the permanent MAC address */
1093         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1094                         (struct ether_addr *) hw->mac.perm_addr);
1095
1096         /* Disable flow control */
1097         hw->fc.requested_mode = I40E_FC_NONE;
1098         i40e_set_fc(hw, &aq_fail, TRUE);
1099
1100         /* Set the global registers with default ether type value */
1101         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1102         if (ret != I40E_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1104                              "VLAN ether type");
1105                 goto err_setup_pf_switch;
1106         }
1107
1108         /* PF setup, which includes VSI setup */
1109         ret = i40e_pf_setup(pf);
1110         if (ret) {
1111                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1112                 goto err_setup_pf_switch;
1113         }
1114
1115         /* reset all stats of the device, including pf and main vsi */
1116         i40e_dev_stats_reset(dev);
1117
1118         vsi = pf->main_vsi;
1119
1120         /* Disable double vlan by default */
1121         i40e_vsi_config_double_vlan(vsi, FALSE);
1122
1123         if (!vsi->max_macaddrs)
1124                 len = ETHER_ADDR_LEN;
1125         else
1126                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1127
1128         /* Should be after VSI initialized */
1129         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1130         if (!dev->data->mac_addrs) {
1131                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1132                                         "for storing mac address");
1133                 goto err_mac_alloc;
1134         }
1135         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1136                                         &dev->data->mac_addrs[0]);
1137
1138         /* initialize pf host driver to setup SRIOV resource if applicable */
1139         i40e_pf_host_init(dev);
1140
1141         /* register callback func to eal lib */
1142         rte_intr_callback_register(&(pci_dev->intr_handle),
1143                 i40e_dev_interrupt_handler, (void *)dev);
1144
1145         /* configure and enable device interrupt */
1146         i40e_pf_config_irq0(hw, TRUE);
1147         i40e_pf_enable_irq0(hw);
1148
1149         /* enable uio intr after callback register */
1150         rte_intr_enable(&(pci_dev->intr_handle));
1151         /*
1152          * Add an ethertype filter to drop all flow control frames transmitted
1153          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1154          * frames to wire.
1155          */
1156         i40e_add_tx_flow_control_drop_filter(pf);
1157
1158         /* Set the max frame size to 0x2600 by default,
1159          * in case other drivers changed the default value.
1160          */
1161         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1162
1163         /* initialize mirror rule list */
1164         TAILQ_INIT(&pf->mirror_list);
1165
1166         /* Init dcb to sw mode by default */
1167         ret = i40e_dcb_init_configure(dev, TRUE);
1168         if (ret != I40E_SUCCESS) {
1169                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1170                 pf->flags &= ~I40E_FLAG_DCB;
1171         }
1172
1173         return 0;
1174
1175 err_mac_alloc:
1176         i40e_vsi_release(pf->main_vsi);
1177 err_setup_pf_switch:
1178 err_get_mac_addr:
1179 err_configure_lan_hmc:
1180         (void)i40e_shutdown_lan_hmc(hw);
1181 err_init_lan_hmc:
1182         i40e_res_pool_destroy(&pf->msix_pool);
1183 err_msix_pool_init:
1184         i40e_res_pool_destroy(&pf->qp_pool);
1185 err_qp_pool_init:
1186 err_parameter_init:
1187 err_get_capabilities:
1188         (void)i40e_shutdown_adminq(hw);
1189
1190         return ret;
1191 }
1192
1193 static int
1194 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1195 {
1196         struct rte_pci_device *pci_dev;
1197         struct i40e_hw *hw;
1198         struct i40e_filter_control_settings settings;
1199         int ret;
1200         uint8_t aq_fail = 0;
1201
1202         PMD_INIT_FUNC_TRACE();
1203
1204         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1205                 return 0;
1206
1207         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1208         pci_dev = dev->pci_dev;
1209
1210         if (hw->adapter_stopped == 0)
1211                 i40e_dev_close(dev);
1212
1213         dev->dev_ops = NULL;
1214         dev->rx_pkt_burst = NULL;
1215         dev->tx_pkt_burst = NULL;
1216
1217         /* Disable LLDP */
1218         ret = i40e_aq_stop_lldp(hw, true, NULL);
1219         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1220                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1221
1222         /* Clear PXE mode */
1223         i40e_clear_pxe_mode(hw);
1224
1225         /* Unconfigure filter control */
1226         memset(&settings, 0, sizeof(settings));
1227         ret = i40e_set_filter_control(hw, &settings);
1228         if (ret)
1229                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1230                                         ret);
1231
1232         /* Disable flow control */
1233         hw->fc.requested_mode = I40E_FC_NONE;
1234         i40e_set_fc(hw, &aq_fail, TRUE);
1235
1236         /* uninitialize pf host driver */
1237         i40e_pf_host_uninit(dev);
1238
1239         rte_free(dev->data->mac_addrs);
1240         dev->data->mac_addrs = NULL;
1241
1242         /* disable uio intr before callback unregister */
1243         rte_intr_disable(&(pci_dev->intr_handle));
1244
1245         /* register callback func to eal lib */
1246         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1247                 i40e_dev_interrupt_handler, (void *)dev);
1248
1249         return 0;
1250 }
1251
1252 static int
1253 i40e_dev_configure(struct rte_eth_dev *dev)
1254 {
1255         struct i40e_adapter *ad =
1256                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1258         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1259         int i, ret;
1260
1261         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1262          * bulk allocation or vector Rx preconditions we will reset it.
1263          */
1264         ad->rx_bulk_alloc_allowed = true;
1265         ad->rx_vec_allowed = true;
1266         ad->tx_simple_allowed = true;
1267         ad->tx_vec_allowed = true;
1268
1269         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1270                 ret = i40e_fdir_setup(pf);
1271                 if (ret != I40E_SUCCESS) {
1272                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1273                         return -ENOTSUP;
1274                 }
1275                 ret = i40e_fdir_configure(dev);
1276                 if (ret < 0) {
1277                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1278                         goto err;
1279                 }
1280         } else
1281                 i40e_fdir_teardown(pf);
1282
1283         ret = i40e_dev_init_vlan(dev);
1284         if (ret < 0)
1285                 goto err;
1286
1287         /* VMDQ setup.
1288          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1289          *  RSS setting have different requirements.
1290          *  General PMD driver call sequence are NIC init, configure,
1291          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1292          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1293          *  applicable. So, VMDQ setting has to be done before
1294          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1295          *  For RSS setting, it will try to calculate actual configured RX queue
1296          *  number, which will be available after rx_queue_setup(). dev_start()
1297          *  function is good to place RSS setup.
1298          */
1299         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1300                 ret = i40e_vmdq_setup(dev);
1301                 if (ret)
1302                         goto err;
1303         }
1304
1305         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1306                 ret = i40e_dcb_setup(dev);
1307                 if (ret) {
1308                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1309                         goto err_dcb;
1310                 }
1311         }
1312
1313         return 0;
1314
1315 err_dcb:
1316         /* need to release vmdq resource if exists */
1317         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1318                 i40e_vsi_release(pf->vmdq[i].vsi);
1319                 pf->vmdq[i].vsi = NULL;
1320         }
1321         rte_free(pf->vmdq);
1322         pf->vmdq = NULL;
1323 err:
1324         /* need to release fdir resource if exists */
1325         i40e_fdir_teardown(pf);
1326         return ret;
1327 }
1328
1329 void
1330 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1331 {
1332         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1333         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1334         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1335         uint16_t msix_vect = vsi->msix_intr;
1336         uint16_t i;
1337
1338         for (i = 0; i < vsi->nb_qps; i++) {
1339                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1340                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1341                 rte_wmb();
1342         }
1343
1344         if (vsi->type != I40E_VSI_SRIOV) {
1345                 if (!rte_intr_allow_others(intr_handle)) {
1346                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1347                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1348                         I40E_WRITE_REG(hw,
1349                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1350                                        0);
1351                 } else {
1352                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1353                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1354                         I40E_WRITE_REG(hw,
1355                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1356                                                        msix_vect - 1), 0);
1357                 }
1358         } else {
1359                 uint32_t reg;
1360                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1361                         vsi->user_param + (msix_vect - 1);
1362
1363                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1364                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1365         }
1366         I40E_WRITE_FLUSH(hw);
1367 }
1368
1369 static void
1370 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1371                        int base_queue, int nb_queue)
1372 {
1373         int i;
1374         uint32_t val;
1375         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1376
1377         /* Bind all RX queues to allocated MSIX interrupt */
1378         for (i = 0; i < nb_queue; i++) {
1379                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1380                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1381                         ((base_queue + i + 1) <<
1382                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1383                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1384                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1385
1386                 if (i == nb_queue - 1)
1387                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1388                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1389         }
1390
1391         /* Write first RX queue to Link list register as the head element */
1392         if (vsi->type != I40E_VSI_SRIOV) {
1393                 uint16_t interval =
1394                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1395
1396                 if (msix_vect == I40E_MISC_VEC_ID) {
1397                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1398                                        (base_queue <<
1399                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1400                                        (0x0 <<
1401                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1402                         I40E_WRITE_REG(hw,
1403                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1404                                        interval);
1405                 } else {
1406                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1407                                        (base_queue <<
1408                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1409                                        (0x0 <<
1410                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1411                         I40E_WRITE_REG(hw,
1412                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1413                                                        msix_vect - 1),
1414                                        interval);
1415                 }
1416         } else {
1417                 uint32_t reg;
1418
1419                 if (msix_vect == I40E_MISC_VEC_ID) {
1420                         I40E_WRITE_REG(hw,
1421                                        I40E_VPINT_LNKLST0(vsi->user_param),
1422                                        (base_queue <<
1423                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1424                                        (0x0 <<
1425                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1426                 } else {
1427                         /* num_msix_vectors_vf needs to minus irq0 */
1428                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1429                                 vsi->user_param + (msix_vect - 1);
1430
1431                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1432                                        (base_queue <<
1433                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1434                                        (0x0 <<
1435                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1436                 }
1437         }
1438
1439         I40E_WRITE_FLUSH(hw);
1440 }
1441
1442 void
1443 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1444 {
1445         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1446         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1447         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1448         uint16_t msix_vect = vsi->msix_intr;
1449         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1450         uint16_t queue_idx = 0;
1451         int record = 0;
1452         uint32_t val;
1453         int i;
1454
1455         for (i = 0; i < vsi->nb_qps; i++) {
1456                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1457                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1458         }
1459
1460         /* INTENA flag is not auto-cleared for interrupt */
1461         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1462         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1463                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1464                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1465         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1466
1467         /* VF bind interrupt */
1468         if (vsi->type == I40E_VSI_SRIOV) {
1469                 __vsi_queues_bind_intr(vsi, msix_vect,
1470                                        vsi->base_queue, vsi->nb_qps);
1471                 return;
1472         }
1473
1474         /* PF & VMDq bind interrupt */
1475         if (rte_intr_dp_is_en(intr_handle)) {
1476                 if (vsi->type == I40E_VSI_MAIN) {
1477                         queue_idx = 0;
1478                         record = 1;
1479                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1480                         struct i40e_vsi *main_vsi =
1481                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1482                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1483                         record = 1;
1484                 }
1485         }
1486
1487         for (i = 0; i < vsi->nb_used_qps; i++) {
1488                 if (nb_msix <= 1) {
1489                         if (!rte_intr_allow_others(intr_handle))
1490                                 /* allow to share MISC_VEC_ID */
1491                                 msix_vect = I40E_MISC_VEC_ID;
1492
1493                         /* no enough msix_vect, map all to one */
1494                         __vsi_queues_bind_intr(vsi, msix_vect,
1495                                                vsi->base_queue + i,
1496                                                vsi->nb_used_qps - i);
1497                         for (; !!record && i < vsi->nb_used_qps; i++)
1498                                 intr_handle->intr_vec[queue_idx + i] =
1499                                         msix_vect;
1500                         break;
1501                 }
1502                 /* 1:1 queue/msix_vect mapping */
1503                 __vsi_queues_bind_intr(vsi, msix_vect,
1504                                        vsi->base_queue + i, 1);
1505                 if (!!record)
1506                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1507
1508                 msix_vect++;
1509                 nb_msix--;
1510         }
1511 }
1512
1513 static void
1514 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1515 {
1516         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1517         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1518         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1519         uint16_t interval = i40e_calc_itr_interval(\
1520                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1521         uint16_t msix_intr, i;
1522
1523         if (rte_intr_allow_others(intr_handle))
1524                 for (i = 0; i < vsi->nb_msix; i++) {
1525                         msix_intr = vsi->msix_intr + i;
1526                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1527                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1528                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1529                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1530                                 (interval <<
1531                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1532                 }
1533         else
1534                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1535                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1536                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1537                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1538                                (interval <<
1539                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1540
1541         I40E_WRITE_FLUSH(hw);
1542 }
1543
1544 static void
1545 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1546 {
1547         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1548         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1549         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1550         uint16_t msix_intr, i;
1551
1552         if (rte_intr_allow_others(intr_handle))
1553                 for (i = 0; i < vsi->nb_msix; i++) {
1554                         msix_intr = vsi->msix_intr + i;
1555                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1556                                        0);
1557                 }
1558         else
1559                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1560
1561         I40E_WRITE_FLUSH(hw);
1562 }
1563
1564 static inline uint8_t
1565 i40e_parse_link_speeds(uint16_t link_speeds)
1566 {
1567         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1568
1569         if (link_speeds & ETH_LINK_SPEED_40G)
1570                 link_speed |= I40E_LINK_SPEED_40GB;
1571         if (link_speeds & ETH_LINK_SPEED_20G)
1572                 link_speed |= I40E_LINK_SPEED_20GB;
1573         if (link_speeds & ETH_LINK_SPEED_10G)
1574                 link_speed |= I40E_LINK_SPEED_10GB;
1575         if (link_speeds & ETH_LINK_SPEED_1G)
1576                 link_speed |= I40E_LINK_SPEED_1GB;
1577         if (link_speeds & ETH_LINK_SPEED_100M)
1578                 link_speed |= I40E_LINK_SPEED_100MB;
1579
1580         return link_speed;
1581 }
1582
1583 static int
1584 i40e_phy_conf_link(struct i40e_hw *hw,
1585                    uint8_t abilities,
1586                    uint8_t force_speed)
1587 {
1588         enum i40e_status_code status;
1589         struct i40e_aq_get_phy_abilities_resp phy_ab;
1590         struct i40e_aq_set_phy_config phy_conf;
1591         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1592                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1593                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1594                         I40E_AQ_PHY_FLAG_LOW_POWER;
1595         const uint8_t advt = I40E_LINK_SPEED_40GB |
1596                         I40E_LINK_SPEED_10GB |
1597                         I40E_LINK_SPEED_1GB |
1598                         I40E_LINK_SPEED_100MB;
1599         int ret = -ENOTSUP;
1600
1601
1602         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1603                                               NULL);
1604         if (status)
1605                 return ret;
1606
1607         memset(&phy_conf, 0, sizeof(phy_conf));
1608
1609         /* bits 0-2 use the values from get_phy_abilities_resp */
1610         abilities &= ~mask;
1611         abilities |= phy_ab.abilities & mask;
1612
1613         /* update ablities and speed */
1614         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1615                 phy_conf.link_speed = advt;
1616         else
1617                 phy_conf.link_speed = force_speed;
1618
1619         phy_conf.abilities = abilities;
1620
1621         /* use get_phy_abilities_resp value for the rest */
1622         phy_conf.phy_type = phy_ab.phy_type;
1623         phy_conf.eee_capability = phy_ab.eee_capability;
1624         phy_conf.eeer = phy_ab.eeer_val;
1625         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1626
1627         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1628                     phy_ab.abilities, phy_ab.link_speed);
1629         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1630                     phy_conf.abilities, phy_conf.link_speed);
1631
1632         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1633         if (status)
1634                 return ret;
1635
1636         return I40E_SUCCESS;
1637 }
1638
1639 static int
1640 i40e_apply_link_speed(struct rte_eth_dev *dev)
1641 {
1642         uint8_t speed;
1643         uint8_t abilities = 0;
1644         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1645         struct rte_eth_conf *conf = &dev->data->dev_conf;
1646
1647         speed = i40e_parse_link_speeds(conf->link_speeds);
1648         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1649         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1650                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1651         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1652
1653         /* Skip changing speed on 40G interfaces, FW does not support */
1654         if (i40e_is_40G_device(hw->device_id)) {
1655                 speed =  I40E_LINK_SPEED_UNKNOWN;
1656                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1657         }
1658
1659         return i40e_phy_conf_link(hw, abilities, speed);
1660 }
1661
1662 static int
1663 i40e_dev_start(struct rte_eth_dev *dev)
1664 {
1665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667         struct i40e_vsi *main_vsi = pf->main_vsi;
1668         int ret, i;
1669         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1670         uint32_t intr_vector = 0;
1671
1672         hw->adapter_stopped = 0;
1673
1674         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1675                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1676                              dev->data->port_id);
1677                 return -EINVAL;
1678         }
1679
1680         rte_intr_disable(intr_handle);
1681
1682         if ((rte_intr_cap_multiple(intr_handle) ||
1683              !RTE_ETH_DEV_SRIOV(dev).active) &&
1684             dev->data->dev_conf.intr_conf.rxq != 0) {
1685                 intr_vector = dev->data->nb_rx_queues;
1686                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1687                         return -1;
1688         }
1689
1690         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1691                 intr_handle->intr_vec =
1692                         rte_zmalloc("intr_vec",
1693                                     dev->data->nb_rx_queues * sizeof(int),
1694                                     0);
1695                 if (!intr_handle->intr_vec) {
1696                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1697                                      " intr_vec\n", dev->data->nb_rx_queues);
1698                         return -ENOMEM;
1699                 }
1700         }
1701
1702         /* Initialize VSI */
1703         ret = i40e_dev_rxtx_init(pf);
1704         if (ret != I40E_SUCCESS) {
1705                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1706                 goto err_up;
1707         }
1708
1709         /* Map queues with MSIX interrupt */
1710         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1711                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1712         i40e_vsi_queues_bind_intr(main_vsi);
1713         i40e_vsi_enable_queues_intr(main_vsi);
1714
1715         /* Map VMDQ VSI queues with MSIX interrupt */
1716         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1717                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1718                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1719                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1720         }
1721
1722         /* enable FDIR MSIX interrupt */
1723         if (pf->fdir.fdir_vsi) {
1724                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1725                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1726         }
1727
1728         /* Enable all queues which have been configured */
1729         ret = i40e_dev_switch_queues(pf, TRUE);
1730         if (ret != I40E_SUCCESS) {
1731                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1732                 goto err_up;
1733         }
1734
1735         /* Enable receiving broadcast packets */
1736         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1737         if (ret != I40E_SUCCESS)
1738                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1739
1740         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1741                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1742                                                 true, NULL);
1743                 if (ret != I40E_SUCCESS)
1744                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1745         }
1746
1747         /* Apply link configure */
1748         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1749                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1750                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1751                 PMD_DRV_LOG(ERR, "Invalid link setting");
1752                 goto err_up;
1753         }
1754         ret = i40e_apply_link_speed(dev);
1755         if (I40E_SUCCESS != ret) {
1756                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1757                 goto err_up;
1758         }
1759
1760         if (!rte_intr_allow_others(intr_handle)) {
1761                 rte_intr_callback_unregister(intr_handle,
1762                                              i40e_dev_interrupt_handler,
1763                                              (void *)dev);
1764                 /* configure and enable device interrupt */
1765                 i40e_pf_config_irq0(hw, FALSE);
1766                 i40e_pf_enable_irq0(hw);
1767
1768                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1769                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1770                                      " no intr multiplex\n");
1771         }
1772
1773         /* enable uio intr after callback register */
1774         rte_intr_enable(intr_handle);
1775
1776         return I40E_SUCCESS;
1777
1778 err_up:
1779         i40e_dev_switch_queues(pf, FALSE);
1780         i40e_dev_clear_queues(dev);
1781
1782         return ret;
1783 }
1784
1785 static void
1786 i40e_dev_stop(struct rte_eth_dev *dev)
1787 {
1788         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1789         struct i40e_vsi *main_vsi = pf->main_vsi;
1790         struct i40e_mirror_rule *p_mirror;
1791         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1792         int i;
1793
1794         /* Disable all queues */
1795         i40e_dev_switch_queues(pf, FALSE);
1796
1797         /* un-map queues with interrupt registers */
1798         i40e_vsi_disable_queues_intr(main_vsi);
1799         i40e_vsi_queues_unbind_intr(main_vsi);
1800
1801         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1802                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1803                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1804         }
1805
1806         if (pf->fdir.fdir_vsi) {
1807                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1808                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1809         }
1810         /* Clear all queues and release memory */
1811         i40e_dev_clear_queues(dev);
1812
1813         /* Set link down */
1814         i40e_dev_set_link_down(dev);
1815
1816         /* Remove all mirror rules */
1817         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1818                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1819                 rte_free(p_mirror);
1820         }
1821         pf->nb_mirror_rule = 0;
1822
1823         if (!rte_intr_allow_others(intr_handle))
1824                 /* resume to the default handler */
1825                 rte_intr_callback_register(intr_handle,
1826                                            i40e_dev_interrupt_handler,
1827                                            (void *)dev);
1828
1829         /* Clean datapath event and queue/vec mapping */
1830         rte_intr_efd_disable(intr_handle);
1831         if (intr_handle->intr_vec) {
1832                 rte_free(intr_handle->intr_vec);
1833                 intr_handle->intr_vec = NULL;
1834         }
1835 }
1836
1837 static void
1838 i40e_dev_close(struct rte_eth_dev *dev)
1839 {
1840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         uint32_t reg;
1843         int i;
1844
1845         PMD_INIT_FUNC_TRACE();
1846
1847         i40e_dev_stop(dev);
1848         hw->adapter_stopped = 1;
1849         i40e_dev_free_queues(dev);
1850
1851         /* Disable interrupt */
1852         i40e_pf_disable_irq0(hw);
1853         rte_intr_disable(&(dev->pci_dev->intr_handle));
1854
1855         /* shutdown and destroy the HMC */
1856         i40e_shutdown_lan_hmc(hw);
1857
1858         /* release all the existing VSIs and VEBs */
1859         i40e_fdir_teardown(pf);
1860         i40e_vsi_release(pf->main_vsi);
1861
1862         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1863                 i40e_vsi_release(pf->vmdq[i].vsi);
1864                 pf->vmdq[i].vsi = NULL;
1865         }
1866
1867         rte_free(pf->vmdq);
1868         pf->vmdq = NULL;
1869
1870         /* shutdown the adminq */
1871         i40e_aq_queue_shutdown(hw, true);
1872         i40e_shutdown_adminq(hw);
1873
1874         i40e_res_pool_destroy(&pf->qp_pool);
1875         i40e_res_pool_destroy(&pf->msix_pool);
1876
1877         /* force a PF reset to clean anything leftover */
1878         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1879         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1880                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1881         I40E_WRITE_FLUSH(hw);
1882 }
1883
1884 static void
1885 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1886 {
1887         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1888         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889         struct i40e_vsi *vsi = pf->main_vsi;
1890         int status;
1891
1892         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1893                                                      true, NULL, true);
1894         if (status != I40E_SUCCESS)
1895                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1896
1897         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1898                                                         TRUE, NULL);
1899         if (status != I40E_SUCCESS)
1900                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1901
1902 }
1903
1904 static void
1905 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_vsi *vsi = pf->main_vsi;
1910         int status;
1911
1912         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1913                                                      false, NULL, true);
1914         if (status != I40E_SUCCESS)
1915                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1916
1917         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1918                                                         false, NULL);
1919         if (status != I40E_SUCCESS)
1920                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1921 }
1922
1923 static void
1924 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1925 {
1926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct i40e_vsi *vsi = pf->main_vsi;
1929         int ret;
1930
1931         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1932         if (ret != I40E_SUCCESS)
1933                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1934 }
1935
1936 static void
1937 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1938 {
1939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct i40e_vsi *vsi = pf->main_vsi;
1942         int ret;
1943
1944         if (dev->data->promiscuous == 1)
1945                 return; /* must remain in all_multicast mode */
1946
1947         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1948                                 vsi->seid, FALSE, NULL);
1949         if (ret != I40E_SUCCESS)
1950                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1951 }
1952
1953 /*
1954  * Set device link up.
1955  */
1956 static int
1957 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1958 {
1959         /* re-apply link speed setting */
1960         return i40e_apply_link_speed(dev);
1961 }
1962
1963 /*
1964  * Set device link down.
1965  */
1966 static int
1967 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1968 {
1969         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1970         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972
1973         return i40e_phy_conf_link(hw, abilities, speed);
1974 }
1975
1976 int
1977 i40e_dev_link_update(struct rte_eth_dev *dev,
1978                      int wait_to_complete)
1979 {
1980 #define CHECK_INTERVAL 100  /* 100ms */
1981 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         struct i40e_link_status link_status;
1984         struct rte_eth_link link, old;
1985         int status;
1986         unsigned rep_cnt = MAX_REPEAT_TIME;
1987
1988         memset(&link, 0, sizeof(link));
1989         memset(&old, 0, sizeof(old));
1990         memset(&link_status, 0, sizeof(link_status));
1991         rte_i40e_dev_atomic_read_link_status(dev, &old);
1992
1993         do {
1994                 /* Get link status information from hardware */
1995                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1996                 if (status != I40E_SUCCESS) {
1997                         link.link_speed = ETH_SPEED_NUM_100M;
1998                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1999                         PMD_DRV_LOG(ERR, "Failed to get link info");
2000                         goto out;
2001                 }
2002
2003                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2004                 if (!wait_to_complete)
2005                         break;
2006
2007                 rte_delay_ms(CHECK_INTERVAL);
2008         } while (!link.link_status && rep_cnt--);
2009
2010         if (!link.link_status)
2011                 goto out;
2012
2013         /* i40e uses full duplex only */
2014         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2015
2016         /* Parse the link status */
2017         switch (link_status.link_speed) {
2018         case I40E_LINK_SPEED_100MB:
2019                 link.link_speed = ETH_SPEED_NUM_100M;
2020                 break;
2021         case I40E_LINK_SPEED_1GB:
2022                 link.link_speed = ETH_SPEED_NUM_1G;
2023                 break;
2024         case I40E_LINK_SPEED_10GB:
2025                 link.link_speed = ETH_SPEED_NUM_10G;
2026                 break;
2027         case I40E_LINK_SPEED_20GB:
2028                 link.link_speed = ETH_SPEED_NUM_20G;
2029                 break;
2030         case I40E_LINK_SPEED_40GB:
2031                 link.link_speed = ETH_SPEED_NUM_40G;
2032                 break;
2033         default:
2034                 link.link_speed = ETH_SPEED_NUM_100M;
2035                 break;
2036         }
2037
2038         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2039                         ETH_LINK_SPEED_FIXED);
2040
2041 out:
2042         rte_i40e_dev_atomic_write_link_status(dev, &link);
2043         if (link.link_status == old.link_status)
2044                 return -1;
2045
2046         return 0;
2047 }
2048
2049 /* Get all the statistics of a VSI */
2050 void
2051 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2052 {
2053         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2054         struct i40e_eth_stats *nes = &vsi->eth_stats;
2055         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2057
2058         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2059                             vsi->offset_loaded, &oes->rx_bytes,
2060                             &nes->rx_bytes);
2061         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2062                             vsi->offset_loaded, &oes->rx_unicast,
2063                             &nes->rx_unicast);
2064         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2065                             vsi->offset_loaded, &oes->rx_multicast,
2066                             &nes->rx_multicast);
2067         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2068                             vsi->offset_loaded, &oes->rx_broadcast,
2069                             &nes->rx_broadcast);
2070         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2071                             &oes->rx_discards, &nes->rx_discards);
2072         /* GLV_REPC not supported */
2073         /* GLV_RMPC not supported */
2074         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2075                             &oes->rx_unknown_protocol,
2076                             &nes->rx_unknown_protocol);
2077         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2078                             vsi->offset_loaded, &oes->tx_bytes,
2079                             &nes->tx_bytes);
2080         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2081                             vsi->offset_loaded, &oes->tx_unicast,
2082                             &nes->tx_unicast);
2083         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2084                             vsi->offset_loaded, &oes->tx_multicast,
2085                             &nes->tx_multicast);
2086         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2087                             vsi->offset_loaded,  &oes->tx_broadcast,
2088                             &nes->tx_broadcast);
2089         /* GLV_TDPC not supported */
2090         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2091                             &oes->tx_errors, &nes->tx_errors);
2092         vsi->offset_loaded = true;
2093
2094         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2095                     vsi->vsi_id);
2096         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2097         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2098         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2099         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2100         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2101         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2102                     nes->rx_unknown_protocol);
2103         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2104         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2105         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2106         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2107         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2108         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2109         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2110                     vsi->vsi_id);
2111 }
2112
2113 static void
2114 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2115 {
2116         unsigned int i;
2117         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2118         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2119
2120         /* Get statistics of struct i40e_eth_stats */
2121         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2122                             I40E_GLPRT_GORCL(hw->port),
2123                             pf->offset_loaded, &os->eth.rx_bytes,
2124                             &ns->eth.rx_bytes);
2125         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2126                             I40E_GLPRT_UPRCL(hw->port),
2127                             pf->offset_loaded, &os->eth.rx_unicast,
2128                             &ns->eth.rx_unicast);
2129         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2130                             I40E_GLPRT_MPRCL(hw->port),
2131                             pf->offset_loaded, &os->eth.rx_multicast,
2132                             &ns->eth.rx_multicast);
2133         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2134                             I40E_GLPRT_BPRCL(hw->port),
2135                             pf->offset_loaded, &os->eth.rx_broadcast,
2136                             &ns->eth.rx_broadcast);
2137         /* Workaround: CRC size should not be included in byte statistics,
2138          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2139          */
2140         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2141                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2142
2143         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2144                             pf->offset_loaded, &os->eth.rx_discards,
2145                             &ns->eth.rx_discards);
2146         /* GLPRT_REPC not supported */
2147         /* GLPRT_RMPC not supported */
2148         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2149                             pf->offset_loaded,
2150                             &os->eth.rx_unknown_protocol,
2151                             &ns->eth.rx_unknown_protocol);
2152         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2153                             I40E_GLPRT_GOTCL(hw->port),
2154                             pf->offset_loaded, &os->eth.tx_bytes,
2155                             &ns->eth.tx_bytes);
2156         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2157                             I40E_GLPRT_UPTCL(hw->port),
2158                             pf->offset_loaded, &os->eth.tx_unicast,
2159                             &ns->eth.tx_unicast);
2160         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2161                             I40E_GLPRT_MPTCL(hw->port),
2162                             pf->offset_loaded, &os->eth.tx_multicast,
2163                             &ns->eth.tx_multicast);
2164         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2165                             I40E_GLPRT_BPTCL(hw->port),
2166                             pf->offset_loaded, &os->eth.tx_broadcast,
2167                             &ns->eth.tx_broadcast);
2168         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2169                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2170         /* GLPRT_TEPC not supported */
2171
2172         /* additional port specific stats */
2173         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2174                             pf->offset_loaded, &os->tx_dropped_link_down,
2175                             &ns->tx_dropped_link_down);
2176         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2177                             pf->offset_loaded, &os->crc_errors,
2178                             &ns->crc_errors);
2179         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2180                             pf->offset_loaded, &os->illegal_bytes,
2181                             &ns->illegal_bytes);
2182         /* GLPRT_ERRBC not supported */
2183         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2184                             pf->offset_loaded, &os->mac_local_faults,
2185                             &ns->mac_local_faults);
2186         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2187                             pf->offset_loaded, &os->mac_remote_faults,
2188                             &ns->mac_remote_faults);
2189         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2190                             pf->offset_loaded, &os->rx_length_errors,
2191                             &ns->rx_length_errors);
2192         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2193                             pf->offset_loaded, &os->link_xon_rx,
2194                             &ns->link_xon_rx);
2195         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2196                             pf->offset_loaded, &os->link_xoff_rx,
2197                             &ns->link_xoff_rx);
2198         for (i = 0; i < 8; i++) {
2199                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2200                                     pf->offset_loaded,
2201                                     &os->priority_xon_rx[i],
2202                                     &ns->priority_xon_rx[i]);
2203                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2204                                     pf->offset_loaded,
2205                                     &os->priority_xoff_rx[i],
2206                                     &ns->priority_xoff_rx[i]);
2207         }
2208         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2209                             pf->offset_loaded, &os->link_xon_tx,
2210                             &ns->link_xon_tx);
2211         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2212                             pf->offset_loaded, &os->link_xoff_tx,
2213                             &ns->link_xoff_tx);
2214         for (i = 0; i < 8; i++) {
2215                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2216                                     pf->offset_loaded,
2217                                     &os->priority_xon_tx[i],
2218                                     &ns->priority_xon_tx[i]);
2219                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2220                                     pf->offset_loaded,
2221                                     &os->priority_xoff_tx[i],
2222                                     &ns->priority_xoff_tx[i]);
2223                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2224                                     pf->offset_loaded,
2225                                     &os->priority_xon_2_xoff[i],
2226                                     &ns->priority_xon_2_xoff[i]);
2227         }
2228         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2229                             I40E_GLPRT_PRC64L(hw->port),
2230                             pf->offset_loaded, &os->rx_size_64,
2231                             &ns->rx_size_64);
2232         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2233                             I40E_GLPRT_PRC127L(hw->port),
2234                             pf->offset_loaded, &os->rx_size_127,
2235                             &ns->rx_size_127);
2236         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2237                             I40E_GLPRT_PRC255L(hw->port),
2238                             pf->offset_loaded, &os->rx_size_255,
2239                             &ns->rx_size_255);
2240         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2241                             I40E_GLPRT_PRC511L(hw->port),
2242                             pf->offset_loaded, &os->rx_size_511,
2243                             &ns->rx_size_511);
2244         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2245                             I40E_GLPRT_PRC1023L(hw->port),
2246                             pf->offset_loaded, &os->rx_size_1023,
2247                             &ns->rx_size_1023);
2248         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2249                             I40E_GLPRT_PRC1522L(hw->port),
2250                             pf->offset_loaded, &os->rx_size_1522,
2251                             &ns->rx_size_1522);
2252         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2253                             I40E_GLPRT_PRC9522L(hw->port),
2254                             pf->offset_loaded, &os->rx_size_big,
2255                             &ns->rx_size_big);
2256         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2257                             pf->offset_loaded, &os->rx_undersize,
2258                             &ns->rx_undersize);
2259         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2260                             pf->offset_loaded, &os->rx_fragments,
2261                             &ns->rx_fragments);
2262         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2263                             pf->offset_loaded, &os->rx_oversize,
2264                             &ns->rx_oversize);
2265         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2266                             pf->offset_loaded, &os->rx_jabber,
2267                             &ns->rx_jabber);
2268         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2269                             I40E_GLPRT_PTC64L(hw->port),
2270                             pf->offset_loaded, &os->tx_size_64,
2271                             &ns->tx_size_64);
2272         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2273                             I40E_GLPRT_PTC127L(hw->port),
2274                             pf->offset_loaded, &os->tx_size_127,
2275                             &ns->tx_size_127);
2276         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2277                             I40E_GLPRT_PTC255L(hw->port),
2278                             pf->offset_loaded, &os->tx_size_255,
2279                             &ns->tx_size_255);
2280         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2281                             I40E_GLPRT_PTC511L(hw->port),
2282                             pf->offset_loaded, &os->tx_size_511,
2283                             &ns->tx_size_511);
2284         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2285                             I40E_GLPRT_PTC1023L(hw->port),
2286                             pf->offset_loaded, &os->tx_size_1023,
2287                             &ns->tx_size_1023);
2288         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2289                             I40E_GLPRT_PTC1522L(hw->port),
2290                             pf->offset_loaded, &os->tx_size_1522,
2291                             &ns->tx_size_1522);
2292         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2293                             I40E_GLPRT_PTC9522L(hw->port),
2294                             pf->offset_loaded, &os->tx_size_big,
2295                             &ns->tx_size_big);
2296         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2297                            pf->offset_loaded,
2298                            &os->fd_sb_match, &ns->fd_sb_match);
2299         /* GLPRT_MSPDC not supported */
2300         /* GLPRT_XEC not supported */
2301
2302         pf->offset_loaded = true;
2303
2304         if (pf->main_vsi)
2305                 i40e_update_vsi_stats(pf->main_vsi);
2306 }
2307
2308 /* Get all statistics of a port */
2309 static void
2310 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2311 {
2312         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2315         unsigned i;
2316
2317         /* call read registers - updates values, now write them to struct */
2318         i40e_read_stats_registers(pf, hw);
2319
2320         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2321                         pf->main_vsi->eth_stats.rx_multicast +
2322                         pf->main_vsi->eth_stats.rx_broadcast -
2323                         pf->main_vsi->eth_stats.rx_discards;
2324         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2325                         pf->main_vsi->eth_stats.tx_multicast +
2326                         pf->main_vsi->eth_stats.tx_broadcast;
2327         stats->ibytes   = ns->eth.rx_bytes;
2328         stats->obytes   = ns->eth.tx_bytes;
2329         stats->oerrors  = ns->eth.tx_errors +
2330                         pf->main_vsi->eth_stats.tx_errors;
2331
2332         /* Rx Errors */
2333         stats->imissed  = ns->eth.rx_discards +
2334                         pf->main_vsi->eth_stats.rx_discards;
2335         stats->ierrors  = ns->crc_errors +
2336                         ns->rx_length_errors + ns->rx_undersize +
2337                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2338
2339         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2340         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2341         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2342         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2343         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2344         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2345         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2346                     ns->eth.rx_unknown_protocol);
2347         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2348         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2349         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2350         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2351         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2352         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2353
2354         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2355                     ns->tx_dropped_link_down);
2356         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2357         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2358                     ns->illegal_bytes);
2359         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2360         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2361                     ns->mac_local_faults);
2362         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2363                     ns->mac_remote_faults);
2364         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2365                     ns->rx_length_errors);
2366         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2367         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2368         for (i = 0; i < 8; i++) {
2369                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2370                                 i, ns->priority_xon_rx[i]);
2371                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2372                                 i, ns->priority_xoff_rx[i]);
2373         }
2374         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2375         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2376         for (i = 0; i < 8; i++) {
2377                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2378                                 i, ns->priority_xon_tx[i]);
2379                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2380                                 i, ns->priority_xoff_tx[i]);
2381                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2382                                 i, ns->priority_xon_2_xoff[i]);
2383         }
2384         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2385         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2386         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2387         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2388         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2389         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2390         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2391         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2392         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2393         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2394         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2395         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2396         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2397         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2398         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2399         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2400         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2401         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2402         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2403                         ns->mac_short_packet_dropped);
2404         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2405                     ns->checksum_error);
2406         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2407         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2408 }
2409
2410 /* Reset the statistics */
2411 static void
2412 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2413 {
2414         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2416
2417         /* Mark PF and VSI stats to update the offset, aka "reset" */
2418         pf->offset_loaded = false;
2419         if (pf->main_vsi)
2420                 pf->main_vsi->offset_loaded = false;
2421
2422         /* read the stats, reading current register values into offset */
2423         i40e_read_stats_registers(pf, hw);
2424 }
2425
2426 static uint32_t
2427 i40e_xstats_calc_num(void)
2428 {
2429         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2430                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2431                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2432 }
2433
2434 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2435                                      struct rte_eth_xstat_name *xstats_names,
2436                                      __rte_unused unsigned limit)
2437 {
2438         unsigned count = 0;
2439         unsigned i, prio;
2440
2441         if (xstats_names == NULL)
2442                 return i40e_xstats_calc_num();
2443
2444         /* Note: limit checked in rte_eth_xstats_names() */
2445
2446         /* Get stats from i40e_eth_stats struct */
2447         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2448                 snprintf(xstats_names[count].name,
2449                          sizeof(xstats_names[count].name),
2450                          "%s", rte_i40e_stats_strings[i].name);
2451                 count++;
2452         }
2453
2454         /* Get individiual stats from i40e_hw_port struct */
2455         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2456                 snprintf(xstats_names[count].name,
2457                         sizeof(xstats_names[count].name),
2458                          "%s", rte_i40e_hw_port_strings[i].name);
2459                 count++;
2460         }
2461
2462         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2463                 for (prio = 0; prio < 8; prio++) {
2464                         snprintf(xstats_names[count].name,
2465                                  sizeof(xstats_names[count].name),
2466                                  "rx_priority%u_%s", prio,
2467                                  rte_i40e_rxq_prio_strings[i].name);
2468                         count++;
2469                 }
2470         }
2471
2472         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2473                 for (prio = 0; prio < 8; prio++) {
2474                         snprintf(xstats_names[count].name,
2475                                  sizeof(xstats_names[count].name),
2476                                  "tx_priority%u_%s", prio,
2477                                  rte_i40e_txq_prio_strings[i].name);
2478                         count++;
2479                 }
2480         }
2481         return count;
2482 }
2483
2484 static int
2485 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2486                     unsigned n)
2487 {
2488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490         unsigned i, count, prio;
2491         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2492
2493         count = i40e_xstats_calc_num();
2494         if (n < count)
2495                 return count;
2496
2497         i40e_read_stats_registers(pf, hw);
2498
2499         if (xstats == NULL)
2500                 return 0;
2501
2502         count = 0;
2503
2504         /* Get stats from i40e_eth_stats struct */
2505         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2506                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2507                         rte_i40e_stats_strings[i].offset);
2508                 count++;
2509         }
2510
2511         /* Get individiual stats from i40e_hw_port struct */
2512         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2513                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2514                         rte_i40e_hw_port_strings[i].offset);
2515                 count++;
2516         }
2517
2518         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2519                 for (prio = 0; prio < 8; prio++) {
2520                         xstats[count].value =
2521                                 *(uint64_t *)(((char *)hw_stats) +
2522                                 rte_i40e_rxq_prio_strings[i].offset +
2523                                 (sizeof(uint64_t) * prio));
2524                         count++;
2525                 }
2526         }
2527
2528         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2529                 for (prio = 0; prio < 8; prio++) {
2530                         xstats[count].value =
2531                                 *(uint64_t *)(((char *)hw_stats) +
2532                                 rte_i40e_txq_prio_strings[i].offset +
2533                                 (sizeof(uint64_t) * prio));
2534                         count++;
2535                 }
2536         }
2537
2538         return count;
2539 }
2540
2541 static int
2542 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2543                                  __rte_unused uint16_t queue_id,
2544                                  __rte_unused uint8_t stat_idx,
2545                                  __rte_unused uint8_t is_rx)
2546 {
2547         PMD_INIT_FUNC_TRACE();
2548
2549         return -ENOSYS;
2550 }
2551
2552 static void
2553 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2554 {
2555         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2556         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557         struct i40e_vsi *vsi = pf->main_vsi;
2558
2559         dev_info->max_rx_queues = vsi->nb_qps;
2560         dev_info->max_tx_queues = vsi->nb_qps;
2561         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2562         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2563         dev_info->max_mac_addrs = vsi->max_macaddrs;
2564         dev_info->max_vfs = dev->pci_dev->max_vfs;
2565         dev_info->rx_offload_capa =
2566                 DEV_RX_OFFLOAD_VLAN_STRIP |
2567                 DEV_RX_OFFLOAD_QINQ_STRIP |
2568                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2569                 DEV_RX_OFFLOAD_UDP_CKSUM |
2570                 DEV_RX_OFFLOAD_TCP_CKSUM;
2571         dev_info->tx_offload_capa =
2572                 DEV_TX_OFFLOAD_VLAN_INSERT |
2573                 DEV_TX_OFFLOAD_QINQ_INSERT |
2574                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2575                 DEV_TX_OFFLOAD_UDP_CKSUM |
2576                 DEV_TX_OFFLOAD_TCP_CKSUM |
2577                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2578                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2579                 DEV_TX_OFFLOAD_TCP_TSO;
2580         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2581                                                 sizeof(uint32_t);
2582         dev_info->reta_size = pf->hash_lut_size;
2583         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2584
2585         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2586                 .rx_thresh = {
2587                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2588                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2589                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2590                 },
2591                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2592                 .rx_drop_en = 0,
2593         };
2594
2595         dev_info->default_txconf = (struct rte_eth_txconf) {
2596                 .tx_thresh = {
2597                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2598                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2599                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2600                 },
2601                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2602                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2603                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2604                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2605         };
2606
2607         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2608                 .nb_max = I40E_MAX_RING_DESC,
2609                 .nb_min = I40E_MIN_RING_DESC,
2610                 .nb_align = I40E_ALIGN_RING_DESC,
2611         };
2612
2613         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2614                 .nb_max = I40E_MAX_RING_DESC,
2615                 .nb_min = I40E_MIN_RING_DESC,
2616                 .nb_align = I40E_ALIGN_RING_DESC,
2617         };
2618
2619         if (pf->flags & I40E_FLAG_VMDQ) {
2620                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2621                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2622                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2623                                                 pf->max_nb_vmdq_vsi;
2624                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2625                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2626                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2627         }
2628
2629         if (i40e_is_40G_device(hw->device_id))
2630                 /* For XL710 */
2631                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2632         else
2633                 /* For X710 */
2634                 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2635 }
2636
2637 static int
2638 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2639 {
2640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2641         struct i40e_vsi *vsi = pf->main_vsi;
2642         PMD_INIT_FUNC_TRACE();
2643
2644         if (on)
2645                 return i40e_vsi_add_vlan(vsi, vlan_id);
2646         else
2647                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2648 }
2649
2650 static int
2651 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2652                    enum rte_vlan_type vlan_type,
2653                    uint16_t tpid)
2654 {
2655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656         uint64_t reg_r = 0, reg_w = 0;
2657         uint16_t reg_id = 0;
2658         int ret = 0;
2659         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2660
2661         switch (vlan_type) {
2662         case ETH_VLAN_TYPE_OUTER:
2663                 if (qinq)
2664                         reg_id = 2;
2665                 else
2666                         reg_id = 3;
2667                 break;
2668         case ETH_VLAN_TYPE_INNER:
2669                 if (qinq)
2670                         reg_id = 3;
2671                 else {
2672                         ret = -EINVAL;
2673                         PMD_DRV_LOG(ERR,
2674                                 "Unsupported vlan type in single vlan.\n");
2675                         return ret;
2676                 }
2677                 break;
2678         default:
2679                 ret = -EINVAL;
2680                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2681                 return ret;
2682         }
2683         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2684                                           &reg_r, NULL);
2685         if (ret != I40E_SUCCESS) {
2686                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2687                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2688                 ret = -EIO;
2689                 return ret;
2690         }
2691         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2692                     "0x%08"PRIx64"", reg_id, reg_r);
2693
2694         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2695         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2696         if (reg_r == reg_w) {
2697                 ret = 0;
2698                 PMD_DRV_LOG(DEBUG, "No need to write");
2699                 return ret;
2700         }
2701
2702         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2703                                            reg_w, NULL);
2704         if (ret != I40E_SUCCESS) {
2705                 ret = -EIO;
2706                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2707                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2708                 return ret;
2709         }
2710         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2711                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2712
2713         return ret;
2714 }
2715
2716 static void
2717 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2718 {
2719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2720         struct i40e_vsi *vsi = pf->main_vsi;
2721         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722
2723         if (mask & ETH_VLAN_FILTER_MASK) {
2724                 if (dev->data->dev_conf.rxmode.hw_vlan_filter) {
2725                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, false, NULL);
2726                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2727                 } else {
2728                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, true, NULL);
2729                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2730                 }
2731         }
2732
2733         if (mask & ETH_VLAN_STRIP_MASK) {
2734                 /* Enable or disable VLAN stripping */
2735                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2736                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2737                 else
2738                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2739         }
2740
2741         if (mask & ETH_VLAN_EXTEND_MASK) {
2742                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2743                         i40e_vsi_config_double_vlan(vsi, TRUE);
2744                         /* Set global registers with default ether type value */
2745                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2746                                            ETHER_TYPE_VLAN);
2747                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2748                                            ETHER_TYPE_VLAN);
2749                 }
2750                 else
2751                         i40e_vsi_config_double_vlan(vsi, FALSE);
2752         }
2753 }
2754
2755 static void
2756 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2757                           __rte_unused uint16_t queue,
2758                           __rte_unused int on)
2759 {
2760         PMD_INIT_FUNC_TRACE();
2761 }
2762
2763 static int
2764 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2765 {
2766         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2767         struct i40e_vsi *vsi = pf->main_vsi;
2768         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2769         struct i40e_vsi_vlan_pvid_info info;
2770
2771         memset(&info, 0, sizeof(info));
2772         info.on = on;
2773         if (info.on)
2774                 info.config.pvid = pvid;
2775         else {
2776                 info.config.reject.tagged =
2777                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2778                 info.config.reject.untagged =
2779                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2780         }
2781
2782         return i40e_vsi_vlan_pvid_set(vsi, &info);
2783 }
2784
2785 static int
2786 i40e_dev_led_on(struct rte_eth_dev *dev)
2787 {
2788         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789         uint32_t mode = i40e_led_get(hw);
2790
2791         if (mode == 0)
2792                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2793
2794         return 0;
2795 }
2796
2797 static int
2798 i40e_dev_led_off(struct rte_eth_dev *dev)
2799 {
2800         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801         uint32_t mode = i40e_led_get(hw);
2802
2803         if (mode != 0)
2804                 i40e_led_set(hw, 0, false);
2805
2806         return 0;
2807 }
2808
2809 static int
2810 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2811 {
2812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2814
2815         fc_conf->pause_time = pf->fc_conf.pause_time;
2816         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2817         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2818
2819          /* Return current mode according to actual setting*/
2820         switch (hw->fc.current_mode) {
2821         case I40E_FC_FULL:
2822                 fc_conf->mode = RTE_FC_FULL;
2823                 break;
2824         case I40E_FC_TX_PAUSE:
2825                 fc_conf->mode = RTE_FC_TX_PAUSE;
2826                 break;
2827         case I40E_FC_RX_PAUSE:
2828                 fc_conf->mode = RTE_FC_RX_PAUSE;
2829                 break;
2830         case I40E_FC_NONE:
2831         default:
2832                 fc_conf->mode = RTE_FC_NONE;
2833         };
2834
2835         return 0;
2836 }
2837
2838 static int
2839 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2840 {
2841         uint32_t mflcn_reg, fctrl_reg, reg;
2842         uint32_t max_high_water;
2843         uint8_t i, aq_failure;
2844         int err;
2845         struct i40e_hw *hw;
2846         struct i40e_pf *pf;
2847         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2848                 [RTE_FC_NONE] = I40E_FC_NONE,
2849                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2850                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2851                 [RTE_FC_FULL] = I40E_FC_FULL
2852         };
2853
2854         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2855
2856         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2857         if ((fc_conf->high_water > max_high_water) ||
2858                         (fc_conf->high_water < fc_conf->low_water)) {
2859                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2860                         "High_water must <= %d.", max_high_water);
2861                 return -EINVAL;
2862         }
2863
2864         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2866         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2867
2868         pf->fc_conf.pause_time = fc_conf->pause_time;
2869         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2870         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2871
2872         PMD_INIT_FUNC_TRACE();
2873
2874         /* All the link flow control related enable/disable register
2875          * configuration is handle by the F/W
2876          */
2877         err = i40e_set_fc(hw, &aq_failure, true);
2878         if (err < 0)
2879                 return -ENOSYS;
2880
2881         if (i40e_is_40G_device(hw->device_id)) {
2882                 /* Configure flow control refresh threshold,
2883                  * the value for stat_tx_pause_refresh_timer[8]
2884                  * is used for global pause operation.
2885                  */
2886
2887                 I40E_WRITE_REG(hw,
2888                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2889                                pf->fc_conf.pause_time);
2890
2891                 /* configure the timer value included in transmitted pause
2892                  * frame,
2893                  * the value for stat_tx_pause_quanta[8] is used for global
2894                  * pause operation
2895                  */
2896                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2897                                pf->fc_conf.pause_time);
2898
2899                 fctrl_reg = I40E_READ_REG(hw,
2900                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2901
2902                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2903                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2904                 else
2905                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2906
2907                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2908                                fctrl_reg);
2909         } else {
2910                 /* Configure pause time (2 TCs per register) */
2911                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2912                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2913                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2914
2915                 /* Configure flow control refresh threshold value */
2916                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2917                                pf->fc_conf.pause_time / 2);
2918
2919                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2920
2921                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2922                  *depending on configuration
2923                  */
2924                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2925                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2926                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2927                 } else {
2928                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2929                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2930                 }
2931
2932                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2933         }
2934
2935         /* config the water marker both based on the packets and bytes */
2936         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2937                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2938                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2939         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2940                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2941                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2942         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2943                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2944                        << I40E_KILOSHIFT);
2945         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2946                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2947                        << I40E_KILOSHIFT);
2948
2949         I40E_WRITE_FLUSH(hw);
2950
2951         return 0;
2952 }
2953
2954 static int
2955 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2956                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2957 {
2958         PMD_INIT_FUNC_TRACE();
2959
2960         return -ENOSYS;
2961 }
2962
2963 /* Add a MAC address, and update filters */
2964 static void
2965 i40e_macaddr_add(struct rte_eth_dev *dev,
2966                  struct ether_addr *mac_addr,
2967                  __rte_unused uint32_t index,
2968                  uint32_t pool)
2969 {
2970         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2971         struct i40e_mac_filter_info mac_filter;
2972         struct i40e_vsi *vsi;
2973         int ret;
2974
2975         /* If VMDQ not enabled or configured, return */
2976         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2977                           !pf->nb_cfg_vmdq_vsi)) {
2978                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2979                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2980                         pool);
2981                 return;
2982         }
2983
2984         if (pool > pf->nb_cfg_vmdq_vsi) {
2985                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2986                                 pool, pf->nb_cfg_vmdq_vsi);
2987                 return;
2988         }
2989
2990         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2991         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2992                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2993         else
2994                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2995
2996         if (pool == 0)
2997                 vsi = pf->main_vsi;
2998         else
2999                 vsi = pf->vmdq[pool - 1].vsi;
3000
3001         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3002         if (ret != I40E_SUCCESS) {
3003                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3004                 return;
3005         }
3006 }
3007
3008 /* Remove a MAC address, and update filters */
3009 static void
3010 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3011 {
3012         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3013         struct i40e_vsi *vsi;
3014         struct rte_eth_dev_data *data = dev->data;
3015         struct ether_addr *macaddr;
3016         int ret;
3017         uint32_t i;
3018         uint64_t pool_sel;
3019
3020         macaddr = &(data->mac_addrs[index]);
3021
3022         pool_sel = dev->data->mac_pool_sel[index];
3023
3024         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3025                 if (pool_sel & (1ULL << i)) {
3026                         if (i == 0)
3027                                 vsi = pf->main_vsi;
3028                         else {
3029                                 /* No VMDQ pool enabled or configured */
3030                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3031                                         (i > pf->nb_cfg_vmdq_vsi)) {
3032                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3033                                                         "/configured");
3034                                         return;
3035                                 }
3036                                 vsi = pf->vmdq[i - 1].vsi;
3037                         }
3038                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3039
3040                         if (ret) {
3041                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3042                                 return;
3043                         }
3044                 }
3045         }
3046 }
3047
3048 /* Set perfect match or hash match of MAC and VLAN for a VF */
3049 static int
3050 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3051                  struct rte_eth_mac_filter *filter,
3052                  bool add)
3053 {
3054         struct i40e_hw *hw;
3055         struct i40e_mac_filter_info mac_filter;
3056         struct ether_addr old_mac;
3057         struct ether_addr *new_mac;
3058         struct i40e_pf_vf *vf = NULL;
3059         uint16_t vf_id;
3060         int ret;
3061
3062         if (pf == NULL) {
3063                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3064                 return -EINVAL;
3065         }
3066         hw = I40E_PF_TO_HW(pf);
3067
3068         if (filter == NULL) {
3069                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3070                 return -EINVAL;
3071         }
3072
3073         new_mac = &filter->mac_addr;
3074
3075         if (is_zero_ether_addr(new_mac)) {
3076                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3077                 return -EINVAL;
3078         }
3079
3080         vf_id = filter->dst_id;
3081
3082         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3083                 PMD_DRV_LOG(ERR, "Invalid argument.");
3084                 return -EINVAL;
3085         }
3086         vf = &pf->vfs[vf_id];
3087
3088         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3089                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3090                 return -EINVAL;
3091         }
3092
3093         if (add) {
3094                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3095                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3096                                 ETHER_ADDR_LEN);
3097                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3098                                  ETHER_ADDR_LEN);
3099
3100                 mac_filter.filter_type = filter->filter_type;
3101                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3102                 if (ret != I40E_SUCCESS) {
3103                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3104                         return -1;
3105                 }
3106                 ether_addr_copy(new_mac, &pf->dev_addr);
3107         } else {
3108                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3109                                 ETHER_ADDR_LEN);
3110                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3111                 if (ret != I40E_SUCCESS) {
3112                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3113                         return -1;
3114                 }
3115
3116                 /* Clear device address as it has been removed */
3117                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3118                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3119         }
3120
3121         return 0;
3122 }
3123
3124 /* MAC filter handle */
3125 static int
3126 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3127                 void *arg)
3128 {
3129         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3130         struct rte_eth_mac_filter *filter;
3131         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3132         int ret = I40E_NOT_SUPPORTED;
3133
3134         filter = (struct rte_eth_mac_filter *)(arg);
3135
3136         switch (filter_op) {
3137         case RTE_ETH_FILTER_NOP:
3138                 ret = I40E_SUCCESS;
3139                 break;
3140         case RTE_ETH_FILTER_ADD:
3141                 i40e_pf_disable_irq0(hw);
3142                 if (filter->is_vf)
3143                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3144                 i40e_pf_enable_irq0(hw);
3145                 break;
3146         case RTE_ETH_FILTER_DELETE:
3147                 i40e_pf_disable_irq0(hw);
3148                 if (filter->is_vf)
3149                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3150                 i40e_pf_enable_irq0(hw);
3151                 break;
3152         default:
3153                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3154                 ret = I40E_ERR_PARAM;
3155                 break;
3156         }
3157
3158         return ret;
3159 }
3160
3161 static int
3162 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3163 {
3164         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3165         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3166         int ret;
3167
3168         if (!lut)
3169                 return -EINVAL;
3170
3171         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3172                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3173                                           lut, lut_size);
3174                 if (ret) {
3175                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3176                         return ret;
3177                 }
3178         } else {
3179                 uint32_t *lut_dw = (uint32_t *)lut;
3180                 uint16_t i, lut_size_dw = lut_size / 4;
3181
3182                 for (i = 0; i < lut_size_dw; i++)
3183                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3184         }
3185
3186         return 0;
3187 }
3188
3189 static int
3190 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3191 {
3192         struct i40e_pf *pf;
3193         struct i40e_hw *hw;
3194         int ret;
3195
3196         if (!vsi || !lut)
3197                 return -EINVAL;
3198
3199         pf = I40E_VSI_TO_PF(vsi);
3200         hw = I40E_VSI_TO_HW(vsi);
3201
3202         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3203                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3204                                           lut, lut_size);
3205                 if (ret) {
3206                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3207                         return ret;
3208                 }
3209         } else {
3210                 uint32_t *lut_dw = (uint32_t *)lut;
3211                 uint16_t i, lut_size_dw = lut_size / 4;
3212
3213                 for (i = 0; i < lut_size_dw; i++)
3214                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3215                 I40E_WRITE_FLUSH(hw);
3216         }
3217
3218         return 0;
3219 }
3220
3221 static int
3222 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3223                          struct rte_eth_rss_reta_entry64 *reta_conf,
3224                          uint16_t reta_size)
3225 {
3226         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3227         uint16_t i, lut_size = pf->hash_lut_size;
3228         uint16_t idx, shift;
3229         uint8_t *lut;
3230         int ret;
3231
3232         if (reta_size != lut_size ||
3233                 reta_size > ETH_RSS_RETA_SIZE_512) {
3234                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3235                         "(%d) doesn't match the number hardware can supported "
3236                                         "(%d)\n", reta_size, lut_size);
3237                 return -EINVAL;
3238         }
3239
3240         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3241         if (!lut) {
3242                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3243                 return -ENOMEM;
3244         }
3245         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3246         if (ret)
3247                 goto out;
3248         for (i = 0; i < reta_size; i++) {
3249                 idx = i / RTE_RETA_GROUP_SIZE;
3250                 shift = i % RTE_RETA_GROUP_SIZE;
3251                 if (reta_conf[idx].mask & (1ULL << shift))
3252                         lut[i] = reta_conf[idx].reta[shift];
3253         }
3254         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3255
3256 out:
3257         rte_free(lut);
3258
3259         return ret;
3260 }
3261
3262 static int
3263 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3264                         struct rte_eth_rss_reta_entry64 *reta_conf,
3265                         uint16_t reta_size)
3266 {
3267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3268         uint16_t i, lut_size = pf->hash_lut_size;
3269         uint16_t idx, shift;
3270         uint8_t *lut;
3271         int ret;
3272
3273         if (reta_size != lut_size ||
3274                 reta_size > ETH_RSS_RETA_SIZE_512) {
3275                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3276                         "(%d) doesn't match the number hardware can supported "
3277                                         "(%d)\n", reta_size, lut_size);
3278                 return -EINVAL;
3279         }
3280
3281         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3282         if (!lut) {
3283                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3284                 return -ENOMEM;
3285         }
3286
3287         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3288         if (ret)
3289                 goto out;
3290         for (i = 0; i < reta_size; i++) {
3291                 idx = i / RTE_RETA_GROUP_SIZE;
3292                 shift = i % RTE_RETA_GROUP_SIZE;
3293                 if (reta_conf[idx].mask & (1ULL << shift))
3294                         reta_conf[idx].reta[shift] = lut[i];
3295         }
3296
3297 out:
3298         rte_free(lut);
3299
3300         return ret;
3301 }
3302
3303 /**
3304  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3305  * @hw:   pointer to the HW structure
3306  * @mem:  pointer to mem struct to fill out
3307  * @size: size of memory requested
3308  * @alignment: what to align the allocation to
3309  **/
3310 enum i40e_status_code
3311 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3312                         struct i40e_dma_mem *mem,
3313                         u64 size,
3314                         u32 alignment)
3315 {
3316         const struct rte_memzone *mz = NULL;
3317         char z_name[RTE_MEMZONE_NAMESIZE];
3318
3319         if (!mem)
3320                 return I40E_ERR_PARAM;
3321
3322         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3323         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3324                                          alignment, RTE_PGSIZE_2M);
3325         if (!mz)
3326                 return I40E_ERR_NO_MEMORY;
3327
3328         mem->size = size;
3329         mem->va = mz->addr;
3330         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3331         mem->zone = (const void *)mz;
3332         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3333                     "%"PRIu64, mz->name, mem->pa);
3334
3335         return I40E_SUCCESS;
3336 }
3337
3338 /**
3339  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3340  * @hw:   pointer to the HW structure
3341  * @mem:  ptr to mem struct to free
3342  **/
3343 enum i40e_status_code
3344 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3345                     struct i40e_dma_mem *mem)
3346 {
3347         if (!mem)
3348                 return I40E_ERR_PARAM;
3349
3350         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3351                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3352                     mem->pa);
3353         rte_memzone_free((const struct rte_memzone *)mem->zone);
3354         mem->zone = NULL;
3355         mem->va = NULL;
3356         mem->pa = (u64)0;
3357
3358         return I40E_SUCCESS;
3359 }
3360
3361 /**
3362  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3363  * @hw:   pointer to the HW structure
3364  * @mem:  pointer to mem struct to fill out
3365  * @size: size of memory requested
3366  **/
3367 enum i40e_status_code
3368 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3369                          struct i40e_virt_mem *mem,
3370                          u32 size)
3371 {
3372         if (!mem)
3373                 return I40E_ERR_PARAM;
3374
3375         mem->size = size;
3376         mem->va = rte_zmalloc("i40e", size, 0);
3377
3378         if (mem->va)
3379                 return I40E_SUCCESS;
3380         else
3381                 return I40E_ERR_NO_MEMORY;
3382 }
3383
3384 /**
3385  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3386  * @hw:   pointer to the HW structure
3387  * @mem:  pointer to mem struct to free
3388  **/
3389 enum i40e_status_code
3390 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3391                      struct i40e_virt_mem *mem)
3392 {
3393         if (!mem)
3394                 return I40E_ERR_PARAM;
3395
3396         rte_free(mem->va);
3397         mem->va = NULL;
3398
3399         return I40E_SUCCESS;
3400 }
3401
3402 void
3403 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3404 {
3405         rte_spinlock_init(&sp->spinlock);
3406 }
3407
3408 void
3409 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3410 {
3411         rte_spinlock_lock(&sp->spinlock);
3412 }
3413
3414 void
3415 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3416 {
3417         rte_spinlock_unlock(&sp->spinlock);
3418 }
3419
3420 void
3421 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3422 {
3423         return;
3424 }
3425
3426 /**
3427  * Get the hardware capabilities, which will be parsed
3428  * and saved into struct i40e_hw.
3429  */
3430 static int
3431 i40e_get_cap(struct i40e_hw *hw)
3432 {
3433         struct i40e_aqc_list_capabilities_element_resp *buf;
3434         uint16_t len, size = 0;
3435         int ret;
3436
3437         /* Calculate a huge enough buff for saving response data temporarily */
3438         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3439                                                 I40E_MAX_CAP_ELE_NUM;
3440         buf = rte_zmalloc("i40e", len, 0);
3441         if (!buf) {
3442                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3443                 return I40E_ERR_NO_MEMORY;
3444         }
3445
3446         /* Get, parse the capabilities and save it to hw */
3447         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3448                         i40e_aqc_opc_list_func_capabilities, NULL);
3449         if (ret != I40E_SUCCESS)
3450                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3451
3452         /* Free the temporary buffer after being used */
3453         rte_free(buf);
3454
3455         return ret;
3456 }
3457
3458 static int
3459 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3460 {
3461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3462         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3463         uint16_t qp_count = 0, vsi_count = 0;
3464
3465         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3466                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3467                 return -EINVAL;
3468         }
3469         /* Add the parameter init for LFC */
3470         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3471         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3472         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3473
3474         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3475         pf->max_num_vsi = hw->func_caps.num_vsis;
3476         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3477         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3478         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3479
3480         /* FDir queue/VSI allocation */
3481         pf->fdir_qp_offset = 0;
3482         if (hw->func_caps.fd) {
3483                 pf->flags |= I40E_FLAG_FDIR;
3484                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3485         } else {
3486                 pf->fdir_nb_qps = 0;
3487         }
3488         qp_count += pf->fdir_nb_qps;
3489         vsi_count += 1;
3490
3491         /* LAN queue/VSI allocation */
3492         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3493         if (!hw->func_caps.rss) {
3494                 pf->lan_nb_qps = 1;
3495         } else {
3496                 pf->flags |= I40E_FLAG_RSS;
3497                 if (hw->mac.type == I40E_MAC_X722)
3498                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3499                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3500         }
3501         qp_count += pf->lan_nb_qps;
3502         vsi_count += 1;
3503
3504         /* VF queue/VSI allocation */
3505         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3506         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3507                 pf->flags |= I40E_FLAG_SRIOV;
3508                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3509                 pf->vf_num = dev->pci_dev->max_vfs;
3510                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3511                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3512                             pf->vf_nb_qps * pf->vf_num);
3513         } else {
3514                 pf->vf_nb_qps = 0;
3515                 pf->vf_num = 0;
3516         }
3517         qp_count += pf->vf_nb_qps * pf->vf_num;
3518         vsi_count += pf->vf_num;
3519
3520         /* VMDq queue/VSI allocation */
3521         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3522         pf->vmdq_nb_qps = 0;
3523         pf->max_nb_vmdq_vsi = 0;
3524         if (hw->func_caps.vmdq) {
3525                 if (qp_count < hw->func_caps.num_tx_qp &&
3526                         vsi_count < hw->func_caps.num_vsis) {
3527                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3528                                 qp_count) / pf->vmdq_nb_qp_max;
3529
3530                         /* Limit the maximum number of VMDq vsi to the maximum
3531                          * ethdev can support
3532                          */
3533                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3534                                 hw->func_caps.num_vsis - vsi_count);
3535                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3536                                 ETH_64_POOLS);
3537                         if (pf->max_nb_vmdq_vsi) {
3538                                 pf->flags |= I40E_FLAG_VMDQ;
3539                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3540                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3541                                             "per VMDQ VSI, in total %u queues",
3542                                             pf->max_nb_vmdq_vsi,
3543                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3544                                             pf->max_nb_vmdq_vsi);
3545                         } else {
3546                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3547                                             "VMDq");
3548                         }
3549                 } else {
3550                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3551                 }
3552         }
3553         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3554         vsi_count += pf->max_nb_vmdq_vsi;
3555
3556         if (hw->func_caps.dcb)
3557                 pf->flags |= I40E_FLAG_DCB;
3558
3559         if (qp_count > hw->func_caps.num_tx_qp) {
3560                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3561                             "the hardware maximum %u", qp_count,
3562                             hw->func_caps.num_tx_qp);
3563                 return -EINVAL;
3564         }
3565         if (vsi_count > hw->func_caps.num_vsis) {
3566                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3567                             "the hardware maximum %u", vsi_count,
3568                             hw->func_caps.num_vsis);
3569                 return -EINVAL;
3570         }
3571
3572         return 0;
3573 }
3574
3575 static int
3576 i40e_pf_get_switch_config(struct i40e_pf *pf)
3577 {
3578         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3579         struct i40e_aqc_get_switch_config_resp *switch_config;
3580         struct i40e_aqc_switch_config_element_resp *element;
3581         uint16_t start_seid = 0, num_reported;
3582         int ret;
3583
3584         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3585                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3586         if (!switch_config) {
3587                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3588                 return -ENOMEM;
3589         }
3590
3591         /* Get the switch configurations */
3592         ret = i40e_aq_get_switch_config(hw, switch_config,
3593                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3594         if (ret != I40E_SUCCESS) {
3595                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3596                 goto fail;
3597         }
3598         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3599         if (num_reported != 1) { /* The number should be 1 */
3600                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3601                 goto fail;
3602         }
3603
3604         /* Parse the switch configuration elements */
3605         element = &(switch_config->element[0]);
3606         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3607                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3608                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3609         } else
3610                 PMD_DRV_LOG(INFO, "Unknown element type");
3611
3612 fail:
3613         rte_free(switch_config);
3614
3615         return ret;
3616 }
3617
3618 static int
3619 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3620                         uint32_t num)
3621 {
3622         struct pool_entry *entry;
3623
3624         if (pool == NULL || num == 0)
3625                 return -EINVAL;
3626
3627         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3628         if (entry == NULL) {
3629                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3630                 return -ENOMEM;
3631         }
3632
3633         /* queue heap initialize */
3634         pool->num_free = num;
3635         pool->num_alloc = 0;
3636         pool->base = base;
3637         LIST_INIT(&pool->alloc_list);
3638         LIST_INIT(&pool->free_list);
3639
3640         /* Initialize element  */
3641         entry->base = 0;
3642         entry->len = num;
3643
3644         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3645         return 0;
3646 }
3647
3648 static void
3649 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3650 {
3651         struct pool_entry *entry, *next_entry;
3652
3653         if (pool == NULL)
3654                 return;
3655
3656         for (entry = LIST_FIRST(&pool->alloc_list);
3657                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3658                         entry = next_entry) {
3659                 LIST_REMOVE(entry, next);
3660                 rte_free(entry);
3661         }
3662
3663         for (entry = LIST_FIRST(&pool->free_list);
3664                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3665                         entry = next_entry) {
3666                 LIST_REMOVE(entry, next);
3667                 rte_free(entry);
3668         }
3669
3670         pool->num_free = 0;
3671         pool->num_alloc = 0;
3672         pool->base = 0;
3673         LIST_INIT(&pool->alloc_list);
3674         LIST_INIT(&pool->free_list);
3675 }
3676
3677 static int
3678 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3679                        uint32_t base)
3680 {
3681         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3682         uint32_t pool_offset;
3683         int insert;
3684
3685         if (pool == NULL) {
3686                 PMD_DRV_LOG(ERR, "Invalid parameter");
3687                 return -EINVAL;
3688         }
3689
3690         pool_offset = base - pool->base;
3691         /* Lookup in alloc list */
3692         LIST_FOREACH(entry, &pool->alloc_list, next) {
3693                 if (entry->base == pool_offset) {
3694                         valid_entry = entry;
3695                         LIST_REMOVE(entry, next);
3696                         break;
3697                 }
3698         }
3699
3700         /* Not find, return */
3701         if (valid_entry == NULL) {
3702                 PMD_DRV_LOG(ERR, "Failed to find entry");
3703                 return -EINVAL;
3704         }
3705
3706         /**
3707          * Found it, move it to free list  and try to merge.
3708          * In order to make merge easier, always sort it by qbase.
3709          * Find adjacent prev and last entries.
3710          */
3711         prev = next = NULL;
3712         LIST_FOREACH(entry, &pool->free_list, next) {
3713                 if (entry->base > valid_entry->base) {
3714                         next = entry;
3715                         break;
3716                 }
3717                 prev = entry;
3718         }
3719
3720         insert = 0;
3721         /* Try to merge with next one*/
3722         if (next != NULL) {
3723                 /* Merge with next one */
3724                 if (valid_entry->base + valid_entry->len == next->base) {
3725                         next->base = valid_entry->base;
3726                         next->len += valid_entry->len;
3727                         rte_free(valid_entry);
3728                         valid_entry = next;
3729                         insert = 1;
3730                 }
3731         }
3732
3733         if (prev != NULL) {
3734                 /* Merge with previous one */
3735                 if (prev->base + prev->len == valid_entry->base) {
3736                         prev->len += valid_entry->len;
3737                         /* If it merge with next one, remove next node */
3738                         if (insert == 1) {
3739                                 LIST_REMOVE(valid_entry, next);
3740                                 rte_free(valid_entry);
3741                         } else {
3742                                 rte_free(valid_entry);
3743                                 insert = 1;
3744                         }
3745                 }
3746         }
3747
3748         /* Not find any entry to merge, insert */
3749         if (insert == 0) {
3750                 if (prev != NULL)
3751                         LIST_INSERT_AFTER(prev, valid_entry, next);
3752                 else if (next != NULL)
3753                         LIST_INSERT_BEFORE(next, valid_entry, next);
3754                 else /* It's empty list, insert to head */
3755                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3756         }
3757
3758         pool->num_free += valid_entry->len;
3759         pool->num_alloc -= valid_entry->len;
3760
3761         return 0;
3762 }
3763
3764 static int
3765 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3766                        uint16_t num)
3767 {
3768         struct pool_entry *entry, *valid_entry;
3769
3770         if (pool == NULL || num == 0) {
3771                 PMD_DRV_LOG(ERR, "Invalid parameter");
3772                 return -EINVAL;
3773         }
3774
3775         if (pool->num_free < num) {
3776                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3777                             num, pool->num_free);
3778                 return -ENOMEM;
3779         }
3780
3781         valid_entry = NULL;
3782         /* Lookup  in free list and find most fit one */
3783         LIST_FOREACH(entry, &pool->free_list, next) {
3784                 if (entry->len >= num) {
3785                         /* Find best one */
3786                         if (entry->len == num) {
3787                                 valid_entry = entry;
3788                                 break;
3789                         }
3790                         if (valid_entry == NULL || valid_entry->len > entry->len)
3791                                 valid_entry = entry;
3792                 }
3793         }
3794
3795         /* Not find one to satisfy the request, return */
3796         if (valid_entry == NULL) {
3797                 PMD_DRV_LOG(ERR, "No valid entry found");
3798                 return -ENOMEM;
3799         }
3800         /**
3801          * The entry have equal queue number as requested,
3802          * remove it from alloc_list.
3803          */
3804         if (valid_entry->len == num) {
3805                 LIST_REMOVE(valid_entry, next);
3806         } else {
3807                 /**
3808                  * The entry have more numbers than requested,
3809                  * create a new entry for alloc_list and minus its
3810                  * queue base and number in free_list.
3811                  */
3812                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3813                 if (entry == NULL) {
3814                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3815                                     "resource pool");
3816                         return -ENOMEM;
3817                 }
3818                 entry->base = valid_entry->base;
3819                 entry->len = num;
3820                 valid_entry->base += num;
3821                 valid_entry->len -= num;
3822                 valid_entry = entry;
3823         }
3824
3825         /* Insert it into alloc list, not sorted */
3826         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3827
3828         pool->num_free -= valid_entry->len;
3829         pool->num_alloc += valid_entry->len;
3830
3831         return valid_entry->base + pool->base;
3832 }
3833
3834 /**
3835  * bitmap_is_subset - Check whether src2 is subset of src1
3836  **/
3837 static inline int
3838 bitmap_is_subset(uint8_t src1, uint8_t src2)
3839 {
3840         return !((src1 ^ src2) & src2);
3841 }
3842
3843 static enum i40e_status_code
3844 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3845 {
3846         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3847
3848         /* If DCB is not supported, only default TC is supported */
3849         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3850                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3851                 return I40E_NOT_SUPPORTED;
3852         }
3853
3854         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3855                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3856                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3857                             enabled_tcmap);
3858                 return I40E_NOT_SUPPORTED;
3859         }
3860         return I40E_SUCCESS;
3861 }
3862
3863 int
3864 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3865                                 struct i40e_vsi_vlan_pvid_info *info)
3866 {
3867         struct i40e_hw *hw;
3868         struct i40e_vsi_context ctxt;
3869         uint8_t vlan_flags = 0;
3870         int ret;
3871
3872         if (vsi == NULL || info == NULL) {
3873                 PMD_DRV_LOG(ERR, "invalid parameters");
3874                 return I40E_ERR_PARAM;
3875         }
3876
3877         if (info->on) {
3878                 vsi->info.pvid = info->config.pvid;
3879                 /**
3880                  * If insert pvid is enabled, only tagged pkts are
3881                  * allowed to be sent out.
3882                  */
3883                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3884                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3885         } else {
3886                 vsi->info.pvid = 0;
3887                 if (info->config.reject.tagged == 0)
3888                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3889
3890                 if (info->config.reject.untagged == 0)
3891                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3892         }
3893         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3894                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3895         vsi->info.port_vlan_flags |= vlan_flags;
3896         vsi->info.valid_sections =
3897                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3898         memset(&ctxt, 0, sizeof(ctxt));
3899         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3900         ctxt.seid = vsi->seid;
3901
3902         hw = I40E_VSI_TO_HW(vsi);
3903         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3904         if (ret != I40E_SUCCESS)
3905                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3906
3907         return ret;
3908 }
3909
3910 static int
3911 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3912 {
3913         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3914         int i, ret;
3915         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3916
3917         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3918         if (ret != I40E_SUCCESS)
3919                 return ret;
3920
3921         if (!vsi->seid) {
3922                 PMD_DRV_LOG(ERR, "seid not valid");
3923                 return -EINVAL;
3924         }
3925
3926         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3927         tc_bw_data.tc_valid_bits = enabled_tcmap;
3928         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3929                 tc_bw_data.tc_bw_credits[i] =
3930                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3931
3932         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3933         if (ret != I40E_SUCCESS) {
3934                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3935                 return ret;
3936         }
3937
3938         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3939                                         sizeof(vsi->info.qs_handle));
3940         return I40E_SUCCESS;
3941 }
3942
3943 static enum i40e_status_code
3944 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3945                                  struct i40e_aqc_vsi_properties_data *info,
3946                                  uint8_t enabled_tcmap)
3947 {
3948         enum i40e_status_code ret;
3949         int i, total_tc = 0;
3950         uint16_t qpnum_per_tc, bsf, qp_idx;
3951
3952         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3953         if (ret != I40E_SUCCESS)
3954                 return ret;
3955
3956         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3957                 if (enabled_tcmap & (1 << i))
3958                         total_tc++;
3959         vsi->enabled_tc = enabled_tcmap;
3960
3961         /* Number of queues per enabled TC */
3962         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3963         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3964         bsf = rte_bsf32(qpnum_per_tc);
3965
3966         /* Adjust the queue number to actual queues that can be applied */
3967         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3968                 vsi->nb_qps = qpnum_per_tc * total_tc;
3969
3970         /**
3971          * Configure TC and queue mapping parameters, for enabled TC,
3972          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3973          * default queue will serve it.
3974          */
3975         qp_idx = 0;
3976         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3977                 if (vsi->enabled_tc & (1 << i)) {
3978                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3979                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3980                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3981                         qp_idx += qpnum_per_tc;
3982                 } else
3983                         info->tc_mapping[i] = 0;
3984         }
3985
3986         /* Associate queue number with VSI */
3987         if (vsi->type == I40E_VSI_SRIOV) {
3988                 info->mapping_flags |=
3989                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3990                 for (i = 0; i < vsi->nb_qps; i++)
3991                         info->queue_mapping[i] =
3992                                 rte_cpu_to_le_16(vsi->base_queue + i);
3993         } else {
3994                 info->mapping_flags |=
3995                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3996                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3997         }
3998         info->valid_sections |=
3999                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4000
4001         return I40E_SUCCESS;
4002 }
4003
4004 static int
4005 i40e_veb_release(struct i40e_veb *veb)
4006 {
4007         struct i40e_vsi *vsi;
4008         struct i40e_hw *hw;
4009
4010         if (veb == NULL)
4011                 return -EINVAL;
4012
4013         if (!TAILQ_EMPTY(&veb->head)) {
4014                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4015                 return -EACCES;
4016         }
4017         /* associate_vsi field is NULL for floating VEB */
4018         if (veb->associate_vsi != NULL) {
4019                 vsi = veb->associate_vsi;
4020                 hw = I40E_VSI_TO_HW(vsi);
4021
4022                 vsi->uplink_seid = veb->uplink_seid;
4023                 vsi->veb = NULL;
4024         } else {
4025                 veb->associate_pf->main_vsi->floating_veb = NULL;
4026                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4027         }
4028
4029         i40e_aq_delete_element(hw, veb->seid, NULL);
4030         rte_free(veb);
4031         return I40E_SUCCESS;
4032 }
4033
4034 /* Setup a veb */
4035 static struct i40e_veb *
4036 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4037 {
4038         struct i40e_veb *veb;
4039         int ret;
4040         struct i40e_hw *hw;
4041
4042         if (pf == NULL) {
4043                 PMD_DRV_LOG(ERR,
4044                             "veb setup failed, associated PF shouldn't null");
4045                 return NULL;
4046         }
4047         hw = I40E_PF_TO_HW(pf);
4048
4049         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4050         if (!veb) {
4051                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4052                 goto fail;
4053         }
4054
4055         veb->associate_vsi = vsi;
4056         veb->associate_pf = pf;
4057         TAILQ_INIT(&veb->head);
4058         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4059
4060         /* create floating veb if vsi is NULL */
4061         if (vsi != NULL) {
4062                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4063                                       I40E_DEFAULT_TCMAP, false,
4064                                       &veb->seid, false, NULL);
4065         } else {
4066                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4067                                       true, &veb->seid, false, NULL);
4068         }
4069
4070         if (ret != I40E_SUCCESS) {
4071                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4072                             hw->aq.asq_last_status);
4073                 goto fail;
4074         }
4075
4076         /* get statistics index */
4077         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4078                                 &veb->stats_idx, NULL, NULL, NULL);
4079         if (ret != I40E_SUCCESS) {
4080                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4081                             hw->aq.asq_last_status);
4082                 goto fail;
4083         }
4084         /* Get VEB bandwidth, to be implemented */
4085         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4086         if (vsi)
4087                 vsi->uplink_seid = veb->seid;
4088
4089         return veb;
4090 fail:
4091         rte_free(veb);
4092         return NULL;
4093 }
4094
4095 int
4096 i40e_vsi_release(struct i40e_vsi *vsi)
4097 {
4098         struct i40e_pf *pf;
4099         struct i40e_hw *hw;
4100         struct i40e_vsi_list *vsi_list;
4101         int ret;
4102         struct i40e_mac_filter *f;
4103         uint16_t user_param = vsi->user_param;
4104
4105         if (!vsi)
4106                 return I40E_SUCCESS;
4107
4108         pf = I40E_VSI_TO_PF(vsi);
4109         hw = I40E_VSI_TO_HW(vsi);
4110
4111         /* VSI has child to attach, release child first */
4112         if (vsi->veb) {
4113                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
4114                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4115                                 return -1;
4116                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
4117                 }
4118                 i40e_veb_release(vsi->veb);
4119         }
4120
4121         if (vsi->floating_veb) {
4122                 TAILQ_FOREACH(vsi_list, &vsi->floating_veb->head, list) {
4123                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4124                                 return -1;
4125                         TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
4126                 }
4127         }
4128
4129         /* Remove all macvlan filters of the VSI */
4130         i40e_vsi_remove_all_macvlan_filter(vsi);
4131         TAILQ_FOREACH(f, &vsi->mac_list, next)
4132                 rte_free(f);
4133
4134         if (vsi->type != I40E_VSI_MAIN &&
4135             ((vsi->type != I40E_VSI_SRIOV) ||
4136             !pf->floating_veb_list[user_param])) {
4137                 /* Remove vsi from parent's sibling list */
4138                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4139                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4140                         return I40E_ERR_PARAM;
4141                 }
4142                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4143                                 &vsi->sib_vsi_list, list);
4144
4145                 /* Remove all switch element of the VSI */
4146                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4147                 if (ret != I40E_SUCCESS)
4148                         PMD_DRV_LOG(ERR, "Failed to delete element");
4149         }
4150
4151         if ((vsi->type == I40E_VSI_SRIOV) &&
4152             pf->floating_veb_list[user_param]) {
4153                 /* Remove vsi from parent's sibling list */
4154                 if (vsi->parent_vsi == NULL ||
4155                     vsi->parent_vsi->floating_veb == NULL) {
4156                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4157                         return I40E_ERR_PARAM;
4158                 }
4159                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4160                              &vsi->sib_vsi_list, list);
4161
4162                 /* Remove all switch element of the VSI */
4163                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4164                 if (ret != I40E_SUCCESS)
4165                         PMD_DRV_LOG(ERR, "Failed to delete element");
4166         }
4167
4168         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4169
4170         if (vsi->type != I40E_VSI_SRIOV)
4171                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4172         rte_free(vsi);
4173
4174         return I40E_SUCCESS;
4175 }
4176
4177 static int
4178 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4179 {
4180         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4181         struct i40e_aqc_remove_macvlan_element_data def_filter;
4182         struct i40e_mac_filter_info filter;
4183         int ret;
4184
4185         if (vsi->type != I40E_VSI_MAIN)
4186                 return I40E_ERR_CONFIG;
4187         memset(&def_filter, 0, sizeof(def_filter));
4188         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4189                                         ETH_ADDR_LEN);
4190         def_filter.vlan_tag = 0;
4191         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4192                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4193         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4194         if (ret != I40E_SUCCESS) {
4195                 struct i40e_mac_filter *f;
4196                 struct ether_addr *mac;
4197
4198                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4199                             "macvlan filter");
4200                 /* It needs to add the permanent mac into mac list */
4201                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4202                 if (f == NULL) {
4203                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4204                         return I40E_ERR_NO_MEMORY;
4205                 }
4206                 mac = &f->mac_info.mac_addr;
4207                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4208                                 ETH_ADDR_LEN);
4209                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4210                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4211                 vsi->mac_num++;
4212
4213                 return ret;
4214         }
4215         (void)rte_memcpy(&filter.mac_addr,
4216                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4217         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4218         return i40e_vsi_add_mac(vsi, &filter);
4219 }
4220
4221 /*
4222  * i40e_vsi_get_bw_config - Query VSI BW Information
4223  * @vsi: the VSI to be queried
4224  *
4225  * Returns 0 on success, negative value on failure
4226  */
4227 static enum i40e_status_code
4228 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4229 {
4230         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4231         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4232         struct i40e_hw *hw = &vsi->adapter->hw;
4233         i40e_status ret;
4234         int i;
4235         uint32_t bw_max;
4236
4237         memset(&bw_config, 0, sizeof(bw_config));
4238         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4239         if (ret != I40E_SUCCESS) {
4240                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4241                             hw->aq.asq_last_status);
4242                 return ret;
4243         }
4244
4245         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4246         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4247                                         &ets_sla_config, NULL);
4248         if (ret != I40E_SUCCESS) {
4249                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4250                             "configuration %u", hw->aq.asq_last_status);
4251                 return ret;
4252         }
4253
4254         /* store and print out BW info */
4255         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4256         vsi->bw_info.bw_max = bw_config.max_bw;
4257         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4258         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4259         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4260                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4261                      I40E_16_BIT_WIDTH);
4262         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4263                 vsi->bw_info.bw_ets_share_credits[i] =
4264                                 ets_sla_config.share_credits[i];
4265                 vsi->bw_info.bw_ets_credits[i] =
4266                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4267                 /* 4 bits per TC, 4th bit is reserved */
4268                 vsi->bw_info.bw_ets_max[i] =
4269                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4270                                   RTE_LEN2MASK(3, uint8_t));
4271                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4272                             vsi->bw_info.bw_ets_share_credits[i]);
4273                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4274                             vsi->bw_info.bw_ets_credits[i]);
4275                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4276                             vsi->bw_info.bw_ets_max[i]);
4277         }
4278
4279         return I40E_SUCCESS;
4280 }
4281
4282 /* i40e_enable_pf_lb
4283  * @pf: pointer to the pf structure
4284  *
4285  * allow loopback on pf
4286  */
4287 static inline void
4288 i40e_enable_pf_lb(struct i40e_pf *pf)
4289 {
4290         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4291         struct i40e_vsi_context ctxt;
4292         int ret;
4293
4294         /* Use the FW API if FW >= v5.0 */
4295         if (hw->aq.fw_maj_ver < 5) {
4296                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4297                 return;
4298         }
4299
4300         memset(&ctxt, 0, sizeof(ctxt));
4301         ctxt.seid = pf->main_vsi_seid;
4302         ctxt.pf_num = hw->pf_id;
4303         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4304         if (ret) {
4305                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4306                             ret, hw->aq.asq_last_status);
4307                 return;
4308         }
4309         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4310         ctxt.info.valid_sections =
4311                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4312         ctxt.info.switch_id |=
4313                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4314
4315         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4316         if (ret)
4317                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4318                             hw->aq.asq_last_status);
4319 }
4320
4321 /* Setup a VSI */
4322 struct i40e_vsi *
4323 i40e_vsi_setup(struct i40e_pf *pf,
4324                enum i40e_vsi_type type,
4325                struct i40e_vsi *uplink_vsi,
4326                uint16_t user_param)
4327 {
4328         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4329         struct i40e_vsi *vsi;
4330         struct i40e_mac_filter_info filter;
4331         int ret;
4332         struct i40e_vsi_context ctxt;
4333         struct ether_addr broadcast =
4334                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4335
4336         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4337             uplink_vsi == NULL) {
4338                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4339                             "VSI link shouldn't be NULL");
4340                 return NULL;
4341         }
4342
4343         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4344                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4345                             "uplink VSI should be NULL");
4346                 return NULL;
4347         }
4348
4349         /* two situations
4350          * 1.type is not MAIN and uplink vsi is not NULL
4351          * If uplink vsi didn't setup VEB, create one first under veb field
4352          * 2.type is SRIOV and the uplink is NULL
4353          * If floating VEB is NULL, create one veb under floating veb field
4354          */
4355
4356         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4357             uplink_vsi->veb == NULL) {
4358                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4359
4360                 if (uplink_vsi->veb == NULL) {
4361                         PMD_DRV_LOG(ERR, "VEB setup failed");
4362                         return NULL;
4363                 }
4364                 /* set ALLOWLOOPBACk on pf, when veb is created */
4365                 i40e_enable_pf_lb(pf);
4366         }
4367
4368         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4369             pf->main_vsi->floating_veb == NULL) {
4370                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4371
4372                 if (pf->main_vsi->floating_veb == NULL) {
4373                         PMD_DRV_LOG(ERR, "VEB setup failed");
4374                         return NULL;
4375                 }
4376         }
4377
4378         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4379         if (!vsi) {
4380                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4381                 return NULL;
4382         }
4383         TAILQ_INIT(&vsi->mac_list);
4384         vsi->type = type;
4385         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4386         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4387         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4388         vsi->user_param = user_param;
4389         /* Allocate queues */
4390         switch (vsi->type) {
4391         case I40E_VSI_MAIN  :
4392                 vsi->nb_qps = pf->lan_nb_qps;
4393                 break;
4394         case I40E_VSI_SRIOV :
4395                 vsi->nb_qps = pf->vf_nb_qps;
4396                 break;
4397         case I40E_VSI_VMDQ2:
4398                 vsi->nb_qps = pf->vmdq_nb_qps;
4399                 break;
4400         case I40E_VSI_FDIR:
4401                 vsi->nb_qps = pf->fdir_nb_qps;
4402                 break;
4403         default:
4404                 goto fail_mem;
4405         }
4406         /*
4407          * The filter status descriptor is reported in rx queue 0,
4408          * while the tx queue for fdir filter programming has no
4409          * such constraints, can be non-zero queues.
4410          * To simplify it, choose FDIR vsi use queue 0 pair.
4411          * To make sure it will use queue 0 pair, queue allocation
4412          * need be done before this function is called
4413          */
4414         if (type != I40E_VSI_FDIR) {
4415                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4416                         if (ret < 0) {
4417                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4418                                                 vsi->seid, ret);
4419                                 goto fail_mem;
4420                         }
4421                         vsi->base_queue = ret;
4422         } else
4423                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4424
4425         /* VF has MSIX interrupt in VF range, don't allocate here */
4426         if (type == I40E_VSI_MAIN) {
4427                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4428                                           RTE_MIN(vsi->nb_qps,
4429                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4430                 if (ret < 0) {
4431                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4432                                     vsi->seid, ret);
4433                         goto fail_queue_alloc;
4434                 }
4435                 vsi->msix_intr = ret;
4436                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4437         } else if (type != I40E_VSI_SRIOV) {
4438                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4439                 if (ret < 0) {
4440                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4441                         goto fail_queue_alloc;
4442                 }
4443                 vsi->msix_intr = ret;
4444                 vsi->nb_msix = 1;
4445         } else {
4446                 vsi->msix_intr = 0;
4447                 vsi->nb_msix = 0;
4448         }
4449
4450         /* Add VSI */
4451         if (type == I40E_VSI_MAIN) {
4452                 /* For main VSI, no need to add since it's default one */
4453                 vsi->uplink_seid = pf->mac_seid;
4454                 vsi->seid = pf->main_vsi_seid;
4455                 /* Bind queues with specific MSIX interrupt */
4456                 /**
4457                  * Needs 2 interrupt at least, one for misc cause which will
4458                  * enabled from OS side, Another for queues binding the
4459                  * interrupt from device side only.
4460                  */
4461
4462                 /* Get default VSI parameters from hardware */
4463                 memset(&ctxt, 0, sizeof(ctxt));
4464                 ctxt.seid = vsi->seid;
4465                 ctxt.pf_num = hw->pf_id;
4466                 ctxt.uplink_seid = vsi->uplink_seid;
4467                 ctxt.vf_num = 0;
4468                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4469                 if (ret != I40E_SUCCESS) {
4470                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4471                         goto fail_msix_alloc;
4472                 }
4473                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4474                         sizeof(struct i40e_aqc_vsi_properties_data));
4475                 vsi->vsi_id = ctxt.vsi_number;
4476                 vsi->info.valid_sections = 0;
4477
4478                 /* Configure tc, enabled TC0 only */
4479                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4480                         I40E_SUCCESS) {
4481                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4482                         goto fail_msix_alloc;
4483                 }
4484
4485                 /* TC, queue mapping */
4486                 memset(&ctxt, 0, sizeof(ctxt));
4487                 vsi->info.valid_sections |=
4488                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4489                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4490                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4491                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4492                         sizeof(struct i40e_aqc_vsi_properties_data));
4493                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4494                                                 I40E_DEFAULT_TCMAP);
4495                 if (ret != I40E_SUCCESS) {
4496                         PMD_DRV_LOG(ERR, "Failed to configure "
4497                                     "TC queue mapping");
4498                         goto fail_msix_alloc;
4499                 }
4500                 ctxt.seid = vsi->seid;
4501                 ctxt.pf_num = hw->pf_id;
4502                 ctxt.uplink_seid = vsi->uplink_seid;
4503                 ctxt.vf_num = 0;
4504
4505                 /* Update VSI parameters */
4506                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4507                 if (ret != I40E_SUCCESS) {
4508                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4509                         goto fail_msix_alloc;
4510                 }
4511
4512                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4513                                                 sizeof(vsi->info.tc_mapping));
4514                 (void)rte_memcpy(&vsi->info.queue_mapping,
4515                                 &ctxt.info.queue_mapping,
4516                         sizeof(vsi->info.queue_mapping));
4517                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4518                 vsi->info.valid_sections = 0;
4519
4520                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4521                                 ETH_ADDR_LEN);
4522
4523                 /**
4524                  * Updating default filter settings are necessary to prevent
4525                  * reception of tagged packets.
4526                  * Some old firmware configurations load a default macvlan
4527                  * filter which accepts both tagged and untagged packets.
4528                  * The updating is to use a normal filter instead if needed.
4529                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4530                  * The firmware with correct configurations load the default
4531                  * macvlan filter which is expected and cannot be removed.
4532                  */
4533                 i40e_update_default_filter_setting(vsi);
4534                 i40e_config_qinq(hw, vsi);
4535         } else if (type == I40E_VSI_SRIOV) {
4536                 memset(&ctxt, 0, sizeof(ctxt));
4537                 /**
4538                  * For other VSI, the uplink_seid equals to uplink VSI's
4539                  * uplink_seid since they share same VEB
4540                  */
4541                 if (uplink_vsi == NULL)
4542                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4543                 else
4544                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4545                 ctxt.pf_num = hw->pf_id;
4546                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4547                 ctxt.uplink_seid = vsi->uplink_seid;
4548                 ctxt.connection_type = 0x1;
4549                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4550
4551                 /* Use the VEB configuration if FW >= v5.0 */
4552                 if (hw->aq.fw_maj_ver >= 5) {
4553                         /* Configure switch ID */
4554                         ctxt.info.valid_sections |=
4555                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4556                         ctxt.info.switch_id =
4557                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4558                 }
4559
4560                 /* Configure port/vlan */
4561                 ctxt.info.valid_sections |=
4562                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4563                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4564                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4565                                                 I40E_DEFAULT_TCMAP);
4566                 if (ret != I40E_SUCCESS) {
4567                         PMD_DRV_LOG(ERR, "Failed to configure "
4568                                     "TC queue mapping");
4569                         goto fail_msix_alloc;
4570                 }
4571                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4572                 ctxt.info.valid_sections |=
4573                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4574                 /**
4575                  * Since VSI is not created yet, only configure parameter,
4576                  * will add vsi below.
4577                  */
4578
4579                 i40e_config_qinq(hw, vsi);
4580         } else if (type == I40E_VSI_VMDQ2) {
4581                 memset(&ctxt, 0, sizeof(ctxt));
4582                 /*
4583                  * For other VSI, the uplink_seid equals to uplink VSI's
4584                  * uplink_seid since they share same VEB
4585                  */
4586                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4587                 ctxt.pf_num = hw->pf_id;
4588                 ctxt.vf_num = 0;
4589                 ctxt.uplink_seid = vsi->uplink_seid;
4590                 ctxt.connection_type = 0x1;
4591                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4592
4593                 ctxt.info.valid_sections |=
4594                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4595                 /* user_param carries flag to enable loop back */
4596                 if (user_param) {
4597                         ctxt.info.switch_id =
4598                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4599                         ctxt.info.switch_id |=
4600                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4601                 }
4602
4603                 /* Configure port/vlan */
4604                 ctxt.info.valid_sections |=
4605                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4606                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4607                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4608                                                 I40E_DEFAULT_TCMAP);
4609                 if (ret != I40E_SUCCESS) {
4610                         PMD_DRV_LOG(ERR, "Failed to configure "
4611                                         "TC queue mapping");
4612                         goto fail_msix_alloc;
4613                 }
4614                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4615                 ctxt.info.valid_sections |=
4616                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4617         } else if (type == I40E_VSI_FDIR) {
4618                 memset(&ctxt, 0, sizeof(ctxt));
4619                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4620                 ctxt.pf_num = hw->pf_id;
4621                 ctxt.vf_num = 0;
4622                 ctxt.uplink_seid = vsi->uplink_seid;
4623                 ctxt.connection_type = 0x1;     /* regular data port */
4624                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4625                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4626                                                 I40E_DEFAULT_TCMAP);
4627                 if (ret != I40E_SUCCESS) {
4628                         PMD_DRV_LOG(ERR, "Failed to configure "
4629                                         "TC queue mapping.");
4630                         goto fail_msix_alloc;
4631                 }
4632                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4633                 ctxt.info.valid_sections |=
4634                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4635         } else {
4636                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4637                 goto fail_msix_alloc;
4638         }
4639
4640         if (vsi->type != I40E_VSI_MAIN) {
4641                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4642                 if (ret != I40E_SUCCESS) {
4643                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4644                                     hw->aq.asq_last_status);
4645                         goto fail_msix_alloc;
4646                 }
4647                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4648                 vsi->info.valid_sections = 0;
4649                 vsi->seid = ctxt.seid;
4650                 vsi->vsi_id = ctxt.vsi_number;
4651                 vsi->sib_vsi_list.vsi = vsi;
4652                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4653                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4654                                           &vsi->sib_vsi_list, list);
4655                 } else {
4656                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4657                                           &vsi->sib_vsi_list, list);
4658                 }
4659         }
4660
4661         /* MAC/VLAN configuration */
4662         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4663         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4664
4665         ret = i40e_vsi_add_mac(vsi, &filter);
4666         if (ret != I40E_SUCCESS) {
4667                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4668                 goto fail_msix_alloc;
4669         }
4670
4671         /* Get VSI BW information */
4672         i40e_vsi_get_bw_config(vsi);
4673         return vsi;
4674 fail_msix_alloc:
4675         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4676 fail_queue_alloc:
4677         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4678 fail_mem:
4679         rte_free(vsi);
4680         return NULL;
4681 }
4682
4683 /* Configure vlan filter on or off */
4684 int
4685 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4686 {
4687         int i, num;
4688         struct i40e_mac_filter *f;
4689         struct i40e_mac_filter_info *mac_filter;
4690         enum rte_mac_filter_type desired_filter;
4691         int ret = I40E_SUCCESS;
4692
4693         if (on) {
4694                 /* Filter to match MAC and VLAN */
4695                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4696         } else {
4697                 /* Filter to match only MAC */
4698                 desired_filter = RTE_MAC_PERFECT_MATCH;
4699         }
4700
4701         num = vsi->mac_num;
4702
4703         mac_filter = rte_zmalloc("mac_filter_info_data",
4704                                  num * sizeof(*mac_filter), 0);
4705         if (mac_filter == NULL) {
4706                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4707                 return I40E_ERR_NO_MEMORY;
4708         }
4709
4710         i = 0;
4711
4712         /* Remove all existing mac */
4713         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4714                 mac_filter[i] = f->mac_info;
4715                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4716                 if (ret) {
4717                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4718                                     on ? "enable" : "disable");
4719                         goto DONE;
4720                 }
4721                 i++;
4722         }
4723
4724         /* Override with new filter */
4725         for (i = 0; i < num; i++) {
4726                 mac_filter[i].filter_type = desired_filter;
4727                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4728                 if (ret) {
4729                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4730                                     on ? "enable" : "disable");
4731                         goto DONE;
4732                 }
4733         }
4734
4735 DONE:
4736         rte_free(mac_filter);
4737         return ret;
4738 }
4739
4740 /* Configure vlan stripping on or off */
4741 int
4742 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4743 {
4744         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4745         struct i40e_vsi_context ctxt;
4746         uint8_t vlan_flags;
4747         int ret = I40E_SUCCESS;
4748
4749         /* Check if it has been already on or off */
4750         if (vsi->info.valid_sections &
4751                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4752                 if (on) {
4753                         if ((vsi->info.port_vlan_flags &
4754                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4755                                 return 0; /* already on */
4756                 } else {
4757                         if ((vsi->info.port_vlan_flags &
4758                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4759                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4760                                 return 0; /* already off */
4761                 }
4762         }
4763
4764         if (on)
4765                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4766         else
4767                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4768         vsi->info.valid_sections =
4769                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4770         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4771         vsi->info.port_vlan_flags |= vlan_flags;
4772         ctxt.seid = vsi->seid;
4773         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4774         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4775         if (ret)
4776                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4777                             on ? "enable" : "disable");
4778
4779         return ret;
4780 }
4781
4782 static int
4783 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4784 {
4785         struct rte_eth_dev_data *data = dev->data;
4786         int ret;
4787         int mask = 0;
4788
4789         /* Apply vlan offload setting */
4790         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4791         i40e_vlan_offload_set(dev, mask);
4792
4793         /* Apply double-vlan setting, not implemented yet */
4794
4795         /* Apply pvid setting */
4796         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4797                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4798         if (ret)
4799                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4800
4801         return ret;
4802 }
4803
4804 static int
4805 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4806 {
4807         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4808
4809         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4810 }
4811
4812 static int
4813 i40e_update_flow_control(struct i40e_hw *hw)
4814 {
4815 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4816         struct i40e_link_status link_status;
4817         uint32_t rxfc = 0, txfc = 0, reg;
4818         uint8_t an_info;
4819         int ret;
4820
4821         memset(&link_status, 0, sizeof(link_status));
4822         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4823         if (ret != I40E_SUCCESS) {
4824                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4825                 goto write_reg; /* Disable flow control */
4826         }
4827
4828         an_info = hw->phy.link_info.an_info;
4829         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4830                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4831                 ret = I40E_ERR_NOT_READY;
4832                 goto write_reg; /* Disable flow control */
4833         }
4834         /**
4835          * If link auto negotiation is enabled, flow control needs to
4836          * be configured according to it
4837          */
4838         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4839         case I40E_LINK_PAUSE_RXTX:
4840                 rxfc = 1;
4841                 txfc = 1;
4842                 hw->fc.current_mode = I40E_FC_FULL;
4843                 break;
4844         case I40E_AQ_LINK_PAUSE_RX:
4845                 rxfc = 1;
4846                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4847                 break;
4848         case I40E_AQ_LINK_PAUSE_TX:
4849                 txfc = 1;
4850                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4851                 break;
4852         default:
4853                 hw->fc.current_mode = I40E_FC_NONE;
4854                 break;
4855         }
4856
4857 write_reg:
4858         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4859                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4860         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4861         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4862         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4863         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4864
4865         return ret;
4866 }
4867
4868 /* PF setup */
4869 static int
4870 i40e_pf_setup(struct i40e_pf *pf)
4871 {
4872         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4873         struct i40e_filter_control_settings settings;
4874         struct i40e_vsi *vsi;
4875         int ret;
4876
4877         /* Clear all stats counters */
4878         pf->offset_loaded = FALSE;
4879         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4880         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4881
4882         ret = i40e_pf_get_switch_config(pf);
4883         if (ret != I40E_SUCCESS) {
4884                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4885                 return ret;
4886         }
4887         if (pf->flags & I40E_FLAG_FDIR) {
4888                 /* make queue allocated first, let FDIR use queue pair 0*/
4889                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4890                 if (ret != I40E_FDIR_QUEUE_ID) {
4891                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4892                                     " ret =%d", ret);
4893                         pf->flags &= ~I40E_FLAG_FDIR;
4894                 }
4895         }
4896         /*  main VSI setup */
4897         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4898         if (!vsi) {
4899                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4900                 return I40E_ERR_NOT_READY;
4901         }
4902         pf->main_vsi = vsi;
4903
4904         /* Configure filter control */
4905         memset(&settings, 0, sizeof(settings));
4906         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4907                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4908         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4909                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4910         else {
4911                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4912                                                 hw->func_caps.rss_table_size);
4913                 return I40E_ERR_PARAM;
4914         }
4915         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4916                         "size: %u\n", hw->func_caps.rss_table_size);
4917         pf->hash_lut_size = hw->func_caps.rss_table_size;
4918
4919         /* Enable ethtype and macvlan filters */
4920         settings.enable_ethtype = TRUE;
4921         settings.enable_macvlan = TRUE;
4922         ret = i40e_set_filter_control(hw, &settings);
4923         if (ret)
4924                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4925                                                                 ret);
4926
4927         /* Update flow control according to the auto negotiation */
4928         i40e_update_flow_control(hw);
4929
4930         return I40E_SUCCESS;
4931 }
4932
4933 int
4934 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4935 {
4936         uint32_t reg;
4937         uint16_t j;
4938
4939         /**
4940          * Set or clear TX Queue Disable flags,
4941          * which is required by hardware.
4942          */
4943         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4944         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4945
4946         /* Wait until the request is finished */
4947         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4948                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4949                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4950                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4951                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4952                                                         & 0x1))) {
4953                         break;
4954                 }
4955         }
4956         if (on) {
4957                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4958                         return I40E_SUCCESS; /* already on, skip next steps */
4959
4960                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4961                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4962         } else {
4963                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4964                         return I40E_SUCCESS; /* already off, skip next steps */
4965                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4966         }
4967         /* Write the register */
4968         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4969         /* Check the result */
4970         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4971                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4972                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4973                 if (on) {
4974                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4975                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4976                                 break;
4977                 } else {
4978                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4979                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4980                                 break;
4981                 }
4982         }
4983         /* Check if it is timeout */
4984         if (j >= I40E_CHK_Q_ENA_COUNT) {
4985                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4986                             (on ? "enable" : "disable"), q_idx);
4987                 return I40E_ERR_TIMEOUT;
4988         }
4989
4990         return I40E_SUCCESS;
4991 }
4992
4993 /* Swith on or off the tx queues */
4994 static int
4995 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4996 {
4997         struct rte_eth_dev_data *dev_data = pf->dev_data;
4998         struct i40e_tx_queue *txq;
4999         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5000         uint16_t i;
5001         int ret;
5002
5003         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5004                 txq = dev_data->tx_queues[i];
5005                 /* Don't operate the queue if not configured or
5006                  * if starting only per queue */
5007                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5008                         continue;
5009                 if (on)
5010                         ret = i40e_dev_tx_queue_start(dev, i);
5011                 else
5012                         ret = i40e_dev_tx_queue_stop(dev, i);
5013                 if ( ret != I40E_SUCCESS)
5014                         return ret;
5015         }
5016
5017         return I40E_SUCCESS;
5018 }
5019
5020 int
5021 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5022 {
5023         uint32_t reg;
5024         uint16_t j;
5025
5026         /* Wait until the request is finished */
5027         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5028                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5029                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5030                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5031                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5032                         break;
5033         }
5034
5035         if (on) {
5036                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5037                         return I40E_SUCCESS; /* Already on, skip next steps */
5038                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5039         } else {
5040                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5041                         return I40E_SUCCESS; /* Already off, skip next steps */
5042                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5043         }
5044
5045         /* Write the register */
5046         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5047         /* Check the result */
5048         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5049                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5050                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5051                 if (on) {
5052                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5053                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5054                                 break;
5055                 } else {
5056                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5057                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5058                                 break;
5059                 }
5060         }
5061
5062         /* Check if it is timeout */
5063         if (j >= I40E_CHK_Q_ENA_COUNT) {
5064                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5065                             (on ? "enable" : "disable"), q_idx);
5066                 return I40E_ERR_TIMEOUT;
5067         }
5068
5069         return I40E_SUCCESS;
5070 }
5071 /* Switch on or off the rx queues */
5072 static int
5073 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5074 {
5075         struct rte_eth_dev_data *dev_data = pf->dev_data;
5076         struct i40e_rx_queue *rxq;
5077         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5078         uint16_t i;
5079         int ret;
5080
5081         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5082                 rxq = dev_data->rx_queues[i];
5083                 /* Don't operate the queue if not configured or
5084                  * if starting only per queue */
5085                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5086                         continue;
5087                 if (on)
5088                         ret = i40e_dev_rx_queue_start(dev, i);
5089                 else
5090                         ret = i40e_dev_rx_queue_stop(dev, i);
5091                 if (ret != I40E_SUCCESS)
5092                         return ret;
5093         }
5094
5095         return I40E_SUCCESS;
5096 }
5097
5098 /* Switch on or off all the rx/tx queues */
5099 int
5100 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5101 {
5102         int ret;
5103
5104         if (on) {
5105                 /* enable rx queues before enabling tx queues */
5106                 ret = i40e_dev_switch_rx_queues(pf, on);
5107                 if (ret) {
5108                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5109                         return ret;
5110                 }
5111                 ret = i40e_dev_switch_tx_queues(pf, on);
5112         } else {
5113                 /* Stop tx queues before stopping rx queues */
5114                 ret = i40e_dev_switch_tx_queues(pf, on);
5115                 if (ret) {
5116                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5117                         return ret;
5118                 }
5119                 ret = i40e_dev_switch_rx_queues(pf, on);
5120         }
5121
5122         return ret;
5123 }
5124
5125 /* Initialize VSI for TX */
5126 static int
5127 i40e_dev_tx_init(struct i40e_pf *pf)
5128 {
5129         struct rte_eth_dev_data *data = pf->dev_data;
5130         uint16_t i;
5131         uint32_t ret = I40E_SUCCESS;
5132         struct i40e_tx_queue *txq;
5133
5134         for (i = 0; i < data->nb_tx_queues; i++) {
5135                 txq = data->tx_queues[i];
5136                 if (!txq || !txq->q_set)
5137                         continue;
5138                 ret = i40e_tx_queue_init(txq);
5139                 if (ret != I40E_SUCCESS)
5140                         break;
5141         }
5142         if (ret == I40E_SUCCESS)
5143                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5144                                      ->eth_dev);
5145
5146         return ret;
5147 }
5148
5149 /* Initialize VSI for RX */
5150 static int
5151 i40e_dev_rx_init(struct i40e_pf *pf)
5152 {
5153         struct rte_eth_dev_data *data = pf->dev_data;
5154         int ret = I40E_SUCCESS;
5155         uint16_t i;
5156         struct i40e_rx_queue *rxq;
5157
5158         i40e_pf_config_mq_rx(pf);
5159         for (i = 0; i < data->nb_rx_queues; i++) {
5160                 rxq = data->rx_queues[i];
5161                 if (!rxq || !rxq->q_set)
5162                         continue;
5163
5164                 ret = i40e_rx_queue_init(rxq);
5165                 if (ret != I40E_SUCCESS) {
5166                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5167                                     "initialization");
5168                         break;
5169                 }
5170         }
5171         if (ret == I40E_SUCCESS)
5172                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5173                                      ->eth_dev);
5174
5175         return ret;
5176 }
5177
5178 static int
5179 i40e_dev_rxtx_init(struct i40e_pf *pf)
5180 {
5181         int err;
5182
5183         err = i40e_dev_tx_init(pf);
5184         if (err) {
5185                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5186                 return err;
5187         }
5188         err = i40e_dev_rx_init(pf);
5189         if (err) {
5190                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5191                 return err;
5192         }
5193
5194         return err;
5195 }
5196
5197 static int
5198 i40e_vmdq_setup(struct rte_eth_dev *dev)
5199 {
5200         struct rte_eth_conf *conf = &dev->data->dev_conf;
5201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5202         int i, err, conf_vsis, j, loop;
5203         struct i40e_vsi *vsi;
5204         struct i40e_vmdq_info *vmdq_info;
5205         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5206         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5207
5208         /*
5209          * Disable interrupt to avoid message from VF. Furthermore, it will
5210          * avoid race condition in VSI creation/destroy.
5211          */
5212         i40e_pf_disable_irq0(hw);
5213
5214         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5215                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5216                 return -ENOTSUP;
5217         }
5218
5219         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5220         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5221                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5222                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5223                         pf->max_nb_vmdq_vsi);
5224                 return -ENOTSUP;
5225         }
5226
5227         if (pf->vmdq != NULL) {
5228                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5229                 return 0;
5230         }
5231
5232         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5233                                 sizeof(*vmdq_info) * conf_vsis, 0);
5234
5235         if (pf->vmdq == NULL) {
5236                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5237                 return -ENOMEM;
5238         }
5239
5240         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5241
5242         /* Create VMDQ VSI */
5243         for (i = 0; i < conf_vsis; i++) {
5244                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5245                                 vmdq_conf->enable_loop_back);
5246                 if (vsi == NULL) {
5247                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5248                         err = -1;
5249                         goto err_vsi_setup;
5250                 }
5251                 vmdq_info = &pf->vmdq[i];
5252                 vmdq_info->pf = pf;
5253                 vmdq_info->vsi = vsi;
5254         }
5255         pf->nb_cfg_vmdq_vsi = conf_vsis;
5256
5257         /* Configure Vlan */
5258         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5259         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5260                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5261                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5262                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5263                                         vmdq_conf->pool_map[i].vlan_id, j);
5264
5265                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5266                                                 vmdq_conf->pool_map[i].vlan_id);
5267                                 if (err) {
5268                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5269                                         err = -1;
5270                                         goto err_vsi_setup;
5271                                 }
5272                         }
5273                 }
5274         }
5275
5276         i40e_pf_enable_irq0(hw);
5277
5278         return 0;
5279
5280 err_vsi_setup:
5281         for (i = 0; i < conf_vsis; i++)
5282                 if (pf->vmdq[i].vsi == NULL)
5283                         break;
5284                 else
5285                         i40e_vsi_release(pf->vmdq[i].vsi);
5286
5287         rte_free(pf->vmdq);
5288         pf->vmdq = NULL;
5289         i40e_pf_enable_irq0(hw);
5290         return err;
5291 }
5292
5293 static void
5294 i40e_stat_update_32(struct i40e_hw *hw,
5295                    uint32_t reg,
5296                    bool offset_loaded,
5297                    uint64_t *offset,
5298                    uint64_t *stat)
5299 {
5300         uint64_t new_data;
5301
5302         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5303         if (!offset_loaded)
5304                 *offset = new_data;
5305
5306         if (new_data >= *offset)
5307                 *stat = (uint64_t)(new_data - *offset);
5308         else
5309                 *stat = (uint64_t)((new_data +
5310                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5311 }
5312
5313 static void
5314 i40e_stat_update_48(struct i40e_hw *hw,
5315                    uint32_t hireg,
5316                    uint32_t loreg,
5317                    bool offset_loaded,
5318                    uint64_t *offset,
5319                    uint64_t *stat)
5320 {
5321         uint64_t new_data;
5322
5323         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5324         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5325                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5326
5327         if (!offset_loaded)
5328                 *offset = new_data;
5329
5330         if (new_data >= *offset)
5331                 *stat = new_data - *offset;
5332         else
5333                 *stat = (uint64_t)((new_data +
5334                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5335
5336         *stat &= I40E_48_BIT_MASK;
5337 }
5338
5339 /* Disable IRQ0 */
5340 void
5341 i40e_pf_disable_irq0(struct i40e_hw *hw)
5342 {
5343         /* Disable all interrupt types */
5344         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5345         I40E_WRITE_FLUSH(hw);
5346 }
5347
5348 /* Enable IRQ0 */
5349 void
5350 i40e_pf_enable_irq0(struct i40e_hw *hw)
5351 {
5352         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5353                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5354                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5355                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5356         I40E_WRITE_FLUSH(hw);
5357 }
5358
5359 static void
5360 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5361 {
5362         /* read pending request and disable first */
5363         i40e_pf_disable_irq0(hw);
5364         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5365         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5366                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5367
5368         if (no_queue)
5369                 /* Link no queues with irq0 */
5370                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5371                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5372 }
5373
5374 static void
5375 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5376 {
5377         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5379         int i;
5380         uint16_t abs_vf_id;
5381         uint32_t index, offset, val;
5382
5383         if (!pf->vfs)
5384                 return;
5385         /**
5386          * Try to find which VF trigger a reset, use absolute VF id to access
5387          * since the reg is global register.
5388          */
5389         for (i = 0; i < pf->vf_num; i++) {
5390                 abs_vf_id = hw->func_caps.vf_base_id + i;
5391                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5392                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5393                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5394                 /* VFR event occured */
5395                 if (val & (0x1 << offset)) {
5396                         int ret;
5397
5398                         /* Clear the event first */
5399                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5400                                                         (0x1 << offset));
5401                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5402                         /**
5403                          * Only notify a VF reset event occured,
5404                          * don't trigger another SW reset
5405                          */
5406                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5407                         if (ret != I40E_SUCCESS)
5408                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5409                 }
5410         }
5411 }
5412
5413 static void
5414 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5415 {
5416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5417         struct i40e_arq_event_info info;
5418         uint16_t pending, opcode;
5419         int ret;
5420
5421         info.buf_len = I40E_AQ_BUF_SZ;
5422         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5423         if (!info.msg_buf) {
5424                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5425                 return;
5426         }
5427
5428         pending = 1;
5429         while (pending) {
5430                 ret = i40e_clean_arq_element(hw, &info, &pending);
5431
5432                 if (ret != I40E_SUCCESS) {
5433                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5434                                     "aq_err: %u", hw->aq.asq_last_status);
5435                         break;
5436                 }
5437                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5438
5439                 switch (opcode) {
5440                 case i40e_aqc_opc_send_msg_to_pf:
5441                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5442                         i40e_pf_host_handle_vf_msg(dev,
5443                                         rte_le_to_cpu_16(info.desc.retval),
5444                                         rte_le_to_cpu_32(info.desc.cookie_high),
5445                                         rte_le_to_cpu_32(info.desc.cookie_low),
5446                                         info.msg_buf,
5447                                         info.msg_len);
5448                         break;
5449                 default:
5450                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5451                                     opcode);
5452                         break;
5453                 }
5454         }
5455         rte_free(info.msg_buf);
5456 }
5457
5458 /*
5459  * Interrupt handler is registered as the alarm callback for handling LSC
5460  * interrupt in a definite of time, in order to wait the NIC into a stable
5461  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5462  * no need for link down interrupt.
5463  */
5464 static void
5465 i40e_dev_interrupt_delayed_handler(void *param)
5466 {
5467         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5468         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5469         uint32_t icr0;
5470
5471         /* read interrupt causes again */
5472         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5473
5474 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5475         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5476                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5477         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5478                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5479         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5480                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5481         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5482                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5483         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5484                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5485                                                                 "state\n");
5486         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5487                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5488         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5489                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5490 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5491
5492         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5493                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5494                 i40e_dev_handle_vfr_event(dev);
5495         }
5496         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5497                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5498                 i40e_dev_handle_aq_msg(dev);
5499         }
5500
5501         /* handle the link up interrupt in an alarm callback */
5502         i40e_dev_link_update(dev, 0);
5503         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5504
5505         i40e_pf_enable_irq0(hw);
5506         rte_intr_enable(&(dev->pci_dev->intr_handle));
5507 }
5508
5509 /**
5510  * Interrupt handler triggered by NIC  for handling
5511  * specific interrupt.
5512  *
5513  * @param handle
5514  *  Pointer to interrupt handle.
5515  * @param param
5516  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5517  *
5518  * @return
5519  *  void
5520  */
5521 static void
5522 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5523                            void *param)
5524 {
5525         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5526         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5527         uint32_t icr0;
5528
5529         /* Disable interrupt */
5530         i40e_pf_disable_irq0(hw);
5531
5532         /* read out interrupt causes */
5533         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5534
5535         /* No interrupt event indicated */
5536         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5537                 PMD_DRV_LOG(INFO, "No interrupt event");
5538                 goto done;
5539         }
5540 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5541         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5542                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5543         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5544                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5545         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5546                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5547         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5548                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5549         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5550                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5551         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5552                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5553         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5554                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5555 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5556
5557         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5558                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5559                 i40e_dev_handle_vfr_event(dev);
5560         }
5561         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5562                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5563                 i40e_dev_handle_aq_msg(dev);
5564         }
5565
5566         /* Link Status Change interrupt */
5567         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5568 #define I40E_US_PER_SECOND 1000000
5569                 struct rte_eth_link link;
5570
5571                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5572                 memset(&link, 0, sizeof(link));
5573                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5574                 i40e_dev_link_update(dev, 0);
5575
5576                 /*
5577                  * For link up interrupt, it needs to wait 1 second to let the
5578                  * hardware be a stable state. Otherwise several consecutive
5579                  * interrupts can be observed.
5580                  * For link down interrupt, no need to wait.
5581                  */
5582                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5583                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5584                         return;
5585                 else
5586                         _rte_eth_dev_callback_process(dev,
5587                                 RTE_ETH_EVENT_INTR_LSC);
5588         }
5589
5590 done:
5591         /* Enable interrupt */
5592         i40e_pf_enable_irq0(hw);
5593         rte_intr_enable(&(dev->pci_dev->intr_handle));
5594 }
5595
5596 static int
5597 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5598                          struct i40e_macvlan_filter *filter,
5599                          int total)
5600 {
5601         int ele_num, ele_buff_size;
5602         int num, actual_num, i;
5603         uint16_t flags;
5604         int ret = I40E_SUCCESS;
5605         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5606         struct i40e_aqc_add_macvlan_element_data *req_list;
5607
5608         if (filter == NULL  || total == 0)
5609                 return I40E_ERR_PARAM;
5610         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5611         ele_buff_size = hw->aq.asq_buf_size;
5612
5613         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5614         if (req_list == NULL) {
5615                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5616                 return I40E_ERR_NO_MEMORY;
5617         }
5618
5619         num = 0;
5620         do {
5621                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5622                 memset(req_list, 0, ele_buff_size);
5623
5624                 for (i = 0; i < actual_num; i++) {
5625                         (void)rte_memcpy(req_list[i].mac_addr,
5626                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5627                         req_list[i].vlan_tag =
5628                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5629
5630                         switch (filter[num + i].filter_type) {
5631                         case RTE_MAC_PERFECT_MATCH:
5632                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5633                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5634                                 break;
5635                         case RTE_MACVLAN_PERFECT_MATCH:
5636                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5637                                 break;
5638                         case RTE_MAC_HASH_MATCH:
5639                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5640                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5641                                 break;
5642                         case RTE_MACVLAN_HASH_MATCH:
5643                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5644                                 break;
5645                         default:
5646                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5647                                 ret = I40E_ERR_PARAM;
5648                                 goto DONE;
5649                         }
5650
5651                         req_list[i].queue_number = 0;
5652
5653                         req_list[i].flags = rte_cpu_to_le_16(flags);
5654                 }
5655
5656                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5657                                                 actual_num, NULL);
5658                 if (ret != I40E_SUCCESS) {
5659                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5660                         goto DONE;
5661                 }
5662                 num += actual_num;
5663         } while (num < total);
5664
5665 DONE:
5666         rte_free(req_list);
5667         return ret;
5668 }
5669
5670 static int
5671 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5672                             struct i40e_macvlan_filter *filter,
5673                             int total)
5674 {
5675         int ele_num, ele_buff_size;
5676         int num, actual_num, i;
5677         uint16_t flags;
5678         int ret = I40E_SUCCESS;
5679         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5680         struct i40e_aqc_remove_macvlan_element_data *req_list;
5681
5682         if (filter == NULL  || total == 0)
5683                 return I40E_ERR_PARAM;
5684
5685         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5686         ele_buff_size = hw->aq.asq_buf_size;
5687
5688         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5689         if (req_list == NULL) {
5690                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5691                 return I40E_ERR_NO_MEMORY;
5692         }
5693
5694         num = 0;
5695         do {
5696                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5697                 memset(req_list, 0, ele_buff_size);
5698
5699                 for (i = 0; i < actual_num; i++) {
5700                         (void)rte_memcpy(req_list[i].mac_addr,
5701                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5702                         req_list[i].vlan_tag =
5703                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5704
5705                         switch (filter[num + i].filter_type) {
5706                         case RTE_MAC_PERFECT_MATCH:
5707                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5708                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5709                                 break;
5710                         case RTE_MACVLAN_PERFECT_MATCH:
5711                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5712                                 break;
5713                         case RTE_MAC_HASH_MATCH:
5714                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5715                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5716                                 break;
5717                         case RTE_MACVLAN_HASH_MATCH:
5718                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5719                                 break;
5720                         default:
5721                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5722                                 ret = I40E_ERR_PARAM;
5723                                 goto DONE;
5724                         }
5725                         req_list[i].flags = rte_cpu_to_le_16(flags);
5726                 }
5727
5728                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5729                                                 actual_num, NULL);
5730                 if (ret != I40E_SUCCESS) {
5731                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5732                         goto DONE;
5733                 }
5734                 num += actual_num;
5735         } while (num < total);
5736
5737 DONE:
5738         rte_free(req_list);
5739         return ret;
5740 }
5741
5742 /* Find out specific MAC filter */
5743 static struct i40e_mac_filter *
5744 i40e_find_mac_filter(struct i40e_vsi *vsi,
5745                          struct ether_addr *macaddr)
5746 {
5747         struct i40e_mac_filter *f;
5748
5749         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5750                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5751                         return f;
5752         }
5753
5754         return NULL;
5755 }
5756
5757 static bool
5758 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5759                          uint16_t vlan_id)
5760 {
5761         uint32_t vid_idx, vid_bit;
5762
5763         if (vlan_id > ETH_VLAN_ID_MAX)
5764                 return 0;
5765
5766         vid_idx = I40E_VFTA_IDX(vlan_id);
5767         vid_bit = I40E_VFTA_BIT(vlan_id);
5768
5769         if (vsi->vfta[vid_idx] & vid_bit)
5770                 return 1;
5771         else
5772                 return 0;
5773 }
5774
5775 static void
5776 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5777                          uint16_t vlan_id, bool on)
5778 {
5779         uint32_t vid_idx, vid_bit;
5780         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5781         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
5782         int ret;
5783
5784         if (vlan_id > ETH_VLAN_ID_MAX)
5785                 return;
5786
5787         vid_idx = I40E_VFTA_IDX(vlan_id);
5788         vid_bit = I40E_VFTA_BIT(vlan_id);
5789         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
5790
5791         if (on) {
5792                 ret = i40e_aq_add_vlan(hw, vsi->seid, &vlan_data, 1, NULL);
5793                 if (ret != I40E_SUCCESS)
5794                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
5795                 vsi->vfta[vid_idx] |= vid_bit;
5796         } else {
5797                 ret = i40e_aq_remove_vlan(hw, vsi->seid, &vlan_data, 1, NULL);
5798                 if (ret != I40E_SUCCESS)
5799                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
5800                 vsi->vfta[vid_idx] &= ~vid_bit;
5801         }
5802 }
5803
5804 /**
5805  * Find all vlan options for specific mac addr,
5806  * return with actual vlan found.
5807  */
5808 static inline int
5809 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5810                            struct i40e_macvlan_filter *mv_f,
5811                            int num, struct ether_addr *addr)
5812 {
5813         int i;
5814         uint32_t j, k;
5815
5816         /**
5817          * Not to use i40e_find_vlan_filter to decrease the loop time,
5818          * although the code looks complex.
5819           */
5820         if (num < vsi->vlan_num)
5821                 return I40E_ERR_PARAM;
5822
5823         i = 0;
5824         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5825                 if (vsi->vfta[j]) {
5826                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5827                                 if (vsi->vfta[j] & (1 << k)) {
5828                                         if (i > num - 1) {
5829                                                 PMD_DRV_LOG(ERR, "vlan number "
5830                                                             "not match");
5831                                                 return I40E_ERR_PARAM;
5832                                         }
5833                                         (void)rte_memcpy(&mv_f[i].macaddr,
5834                                                         addr, ETH_ADDR_LEN);
5835                                         mv_f[i].vlan_id =
5836                                                 j * I40E_UINT32_BIT_SIZE + k;
5837                                         i++;
5838                                 }
5839                         }
5840                 }
5841         }
5842         return I40E_SUCCESS;
5843 }
5844
5845 static inline int
5846 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5847                            struct i40e_macvlan_filter *mv_f,
5848                            int num,
5849                            uint16_t vlan)
5850 {
5851         int i = 0;
5852         struct i40e_mac_filter *f;
5853
5854         if (num < vsi->mac_num)
5855                 return I40E_ERR_PARAM;
5856
5857         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5858                 if (i > num - 1) {
5859                         PMD_DRV_LOG(ERR, "buffer number not match");
5860                         return I40E_ERR_PARAM;
5861                 }
5862                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5863                                 ETH_ADDR_LEN);
5864                 mv_f[i].vlan_id = vlan;
5865                 mv_f[i].filter_type = f->mac_info.filter_type;
5866                 i++;
5867         }
5868
5869         return I40E_SUCCESS;
5870 }
5871
5872 static int
5873 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5874 {
5875         int i, num;
5876         struct i40e_mac_filter *f;
5877         struct i40e_macvlan_filter *mv_f;
5878         int ret = I40E_SUCCESS;
5879
5880         if (vsi == NULL || vsi->mac_num == 0)
5881                 return I40E_ERR_PARAM;
5882
5883         /* Case that no vlan is set */
5884         if (vsi->vlan_num == 0)
5885                 num = vsi->mac_num;
5886         else
5887                 num = vsi->mac_num * vsi->vlan_num;
5888
5889         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5890         if (mv_f == NULL) {
5891                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5892                 return I40E_ERR_NO_MEMORY;
5893         }
5894
5895         i = 0;
5896         if (vsi->vlan_num == 0) {
5897                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5898                         (void)rte_memcpy(&mv_f[i].macaddr,
5899                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5900                         mv_f[i].vlan_id = 0;
5901                         i++;
5902                 }
5903         } else {
5904                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5905                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5906                                         vsi->vlan_num, &f->mac_info.mac_addr);
5907                         if (ret != I40E_SUCCESS)
5908                                 goto DONE;
5909                         i += vsi->vlan_num;
5910                 }
5911         }
5912
5913         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5914 DONE:
5915         rte_free(mv_f);
5916
5917         return ret;
5918 }
5919
5920 int
5921 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5922 {
5923         struct i40e_macvlan_filter *mv_f;
5924         int mac_num;
5925         int ret = I40E_SUCCESS;
5926
5927         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5928                 return I40E_ERR_PARAM;
5929
5930         /* If it's already set, just return */
5931         if (i40e_find_vlan_filter(vsi,vlan))
5932                 return I40E_SUCCESS;
5933
5934         mac_num = vsi->mac_num;
5935
5936         if (mac_num == 0) {
5937                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5938                 return I40E_ERR_PARAM;
5939         }
5940
5941         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5942
5943         if (mv_f == NULL) {
5944                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5945                 return I40E_ERR_NO_MEMORY;
5946         }
5947
5948         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5949
5950         if (ret != I40E_SUCCESS)
5951                 goto DONE;
5952
5953         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5954
5955         if (ret != I40E_SUCCESS)
5956                 goto DONE;
5957
5958         i40e_set_vlan_filter(vsi, vlan, 1);
5959
5960         vsi->vlan_num++;
5961         ret = I40E_SUCCESS;
5962 DONE:
5963         rte_free(mv_f);
5964         return ret;
5965 }
5966
5967 int
5968 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5969 {
5970         struct i40e_macvlan_filter *mv_f;
5971         int mac_num;
5972         int ret = I40E_SUCCESS;
5973
5974         /**
5975          * Vlan 0 is the generic filter for untagged packets
5976          * and can't be removed.
5977          */
5978         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5979                 return I40E_ERR_PARAM;
5980
5981         /* If can't find it, just return */
5982         if (!i40e_find_vlan_filter(vsi, vlan))
5983                 return I40E_ERR_PARAM;
5984
5985         mac_num = vsi->mac_num;
5986
5987         if (mac_num == 0) {
5988                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5989                 return I40E_ERR_PARAM;
5990         }
5991
5992         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5993
5994         if (mv_f == NULL) {
5995                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5996                 return I40E_ERR_NO_MEMORY;
5997         }
5998
5999         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6000
6001         if (ret != I40E_SUCCESS)
6002                 goto DONE;
6003
6004         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6005
6006         if (ret != I40E_SUCCESS)
6007                 goto DONE;
6008
6009         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6010         if (vsi->vlan_num == 1) {
6011                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6012                 if (ret != I40E_SUCCESS)
6013                         goto DONE;
6014
6015                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6016                 if (ret != I40E_SUCCESS)
6017                         goto DONE;
6018         }
6019
6020         i40e_set_vlan_filter(vsi, vlan, 0);
6021
6022         vsi->vlan_num--;
6023         ret = I40E_SUCCESS;
6024 DONE:
6025         rte_free(mv_f);
6026         return ret;
6027 }
6028
6029 int
6030 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6031 {
6032         struct i40e_mac_filter *f;
6033         struct i40e_macvlan_filter *mv_f;
6034         int i, vlan_num = 0;
6035         int ret = I40E_SUCCESS;
6036
6037         /* If it's add and we've config it, return */
6038         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6039         if (f != NULL)
6040                 return I40E_SUCCESS;
6041         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6042                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6043
6044                 /**
6045                  * If vlan_num is 0, that's the first time to add mac,
6046                  * set mask for vlan_id 0.
6047                  */
6048                 if (vsi->vlan_num == 0) {
6049                         i40e_set_vlan_filter(vsi, 0, 1);
6050                         vsi->vlan_num = 1;
6051                 }
6052                 vlan_num = vsi->vlan_num;
6053         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6054                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6055                 vlan_num = 1;
6056
6057         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6058         if (mv_f == NULL) {
6059                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6060                 return I40E_ERR_NO_MEMORY;
6061         }
6062
6063         for (i = 0; i < vlan_num; i++) {
6064                 mv_f[i].filter_type = mac_filter->filter_type;
6065                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6066                                 ETH_ADDR_LEN);
6067         }
6068
6069         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6070                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6071                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6072                                         &mac_filter->mac_addr);
6073                 if (ret != I40E_SUCCESS)
6074                         goto DONE;
6075         }
6076
6077         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6078         if (ret != I40E_SUCCESS)
6079                 goto DONE;
6080
6081         /* Add the mac addr into mac list */
6082         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6083         if (f == NULL) {
6084                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6085                 ret = I40E_ERR_NO_MEMORY;
6086                 goto DONE;
6087         }
6088         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6089                         ETH_ADDR_LEN);
6090         f->mac_info.filter_type = mac_filter->filter_type;
6091         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6092         vsi->mac_num++;
6093
6094         ret = I40E_SUCCESS;
6095 DONE:
6096         rte_free(mv_f);
6097
6098         return ret;
6099 }
6100
6101 int
6102 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6103 {
6104         struct i40e_mac_filter *f;
6105         struct i40e_macvlan_filter *mv_f;
6106         int i, vlan_num;
6107         enum rte_mac_filter_type filter_type;
6108         int ret = I40E_SUCCESS;
6109
6110         /* Can't find it, return an error */
6111         f = i40e_find_mac_filter(vsi, addr);
6112         if (f == NULL)
6113                 return I40E_ERR_PARAM;
6114
6115         vlan_num = vsi->vlan_num;
6116         filter_type = f->mac_info.filter_type;
6117         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6118                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6119                 if (vlan_num == 0) {
6120                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6121                         return I40E_ERR_PARAM;
6122                 }
6123         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6124                         filter_type == RTE_MAC_HASH_MATCH)
6125                 vlan_num = 1;
6126
6127         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6128         if (mv_f == NULL) {
6129                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6130                 return I40E_ERR_NO_MEMORY;
6131         }
6132
6133         for (i = 0; i < vlan_num; i++) {
6134                 mv_f[i].filter_type = filter_type;
6135                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6136                                 ETH_ADDR_LEN);
6137         }
6138         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6139                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6140                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6141                 if (ret != I40E_SUCCESS)
6142                         goto DONE;
6143         }
6144
6145         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6146         if (ret != I40E_SUCCESS)
6147                 goto DONE;
6148
6149         /* Remove the mac addr into mac list */
6150         TAILQ_REMOVE(&vsi->mac_list, f, next);
6151         rte_free(f);
6152         vsi->mac_num--;
6153
6154         ret = I40E_SUCCESS;
6155 DONE:
6156         rte_free(mv_f);
6157         return ret;
6158 }
6159
6160 /* Configure hash enable flags for RSS */
6161 uint64_t
6162 i40e_config_hena(uint64_t flags)
6163 {
6164         uint64_t hena = 0;
6165
6166         if (!flags)
6167                 return hena;
6168
6169         if (flags & ETH_RSS_FRAG_IPV4)
6170                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6171         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6172                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6173         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6174                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6175         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6176                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6177         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6178                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6179         if (flags & ETH_RSS_FRAG_IPV6)
6180                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6181         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6182                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6183         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6184                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6185         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6186                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6187         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6188                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6189         if (flags & ETH_RSS_L2_PAYLOAD)
6190                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6191
6192         return hena;
6193 }
6194
6195 /* Parse the hash enable flags */
6196 uint64_t
6197 i40e_parse_hena(uint64_t flags)
6198 {
6199         uint64_t rss_hf = 0;
6200
6201         if (!flags)
6202                 return rss_hf;
6203         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6204                 rss_hf |= ETH_RSS_FRAG_IPV4;
6205         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6206                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6207         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6208                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6209         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6210                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6211         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6212                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6213         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6214                 rss_hf |= ETH_RSS_FRAG_IPV6;
6215         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6216                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6217         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6218                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6219         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6220                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6221         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6222                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6223         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6224                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6225
6226         return rss_hf;
6227 }
6228
6229 /* Disable RSS */
6230 static void
6231 i40e_pf_disable_rss(struct i40e_pf *pf)
6232 {
6233         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6234         uint64_t hena;
6235
6236         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6237         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6238         hena &= ~I40E_RSS_HENA_ALL;
6239         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6240         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6241         I40E_WRITE_FLUSH(hw);
6242 }
6243
6244 static int
6245 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6246 {
6247         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6248         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6249         int ret = 0;
6250
6251         if (!key || key_len == 0) {
6252                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6253                 return 0;
6254         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6255                 sizeof(uint32_t)) {
6256                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6257                 return -EINVAL;
6258         }
6259
6260         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6261                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6262                         (struct i40e_aqc_get_set_rss_key_data *)key;
6263
6264                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6265                 if (ret)
6266                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6267                                      "via AQ");
6268         } else {
6269                 uint32_t *hash_key = (uint32_t *)key;
6270                 uint16_t i;
6271
6272                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6273                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6274                 I40E_WRITE_FLUSH(hw);
6275         }
6276
6277         return ret;
6278 }
6279
6280 static int
6281 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6282 {
6283         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6284         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6285         int ret;
6286
6287         if (!key || !key_len)
6288                 return -EINVAL;
6289
6290         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6291                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6292                         (struct i40e_aqc_get_set_rss_key_data *)key);
6293                 if (ret) {
6294                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6295                         return ret;
6296                 }
6297         } else {
6298                 uint32_t *key_dw = (uint32_t *)key;
6299                 uint16_t i;
6300
6301                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6302                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6303         }
6304         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6305
6306         return 0;
6307 }
6308
6309 static int
6310 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6311 {
6312         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6313         uint64_t rss_hf;
6314         uint64_t hena;
6315         int ret;
6316
6317         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6318                                rss_conf->rss_key_len);
6319         if (ret)
6320                 return ret;
6321
6322         rss_hf = rss_conf->rss_hf;
6323         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6324         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6325         hena &= ~I40E_RSS_HENA_ALL;
6326         hena |= i40e_config_hena(rss_hf);
6327         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6328         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6329         I40E_WRITE_FLUSH(hw);
6330
6331         return 0;
6332 }
6333
6334 static int
6335 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6336                          struct rte_eth_rss_conf *rss_conf)
6337 {
6338         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6340         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6341         uint64_t hena;
6342
6343         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6344         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6345         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6346                 if (rss_hf != 0) /* Enable RSS */
6347                         return -EINVAL;
6348                 return 0; /* Nothing to do */
6349         }
6350         /* RSS enabled */
6351         if (rss_hf == 0) /* Disable RSS */
6352                 return -EINVAL;
6353
6354         return i40e_hw_rss_hash_set(pf, rss_conf);
6355 }
6356
6357 static int
6358 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6359                            struct rte_eth_rss_conf *rss_conf)
6360 {
6361         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6363         uint64_t hena;
6364
6365         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6366                          &rss_conf->rss_key_len);
6367
6368         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6369         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6370         rss_conf->rss_hf = i40e_parse_hena(hena);
6371
6372         return 0;
6373 }
6374
6375 static int
6376 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6377 {
6378         switch (filter_type) {
6379         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6380                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6381                 break;
6382         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6383                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6384                 break;
6385         case RTE_TUNNEL_FILTER_IMAC_TENID:
6386                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6387                 break;
6388         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6389                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6390                 break;
6391         case ETH_TUNNEL_FILTER_IMAC:
6392                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6393                 break;
6394         case ETH_TUNNEL_FILTER_OIP:
6395                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6396                 break;
6397         case ETH_TUNNEL_FILTER_IIP:
6398                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6399                 break;
6400         default:
6401                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6402                 return -EINVAL;
6403         }
6404
6405         return 0;
6406 }
6407
6408 static int
6409 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6410                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6411                         uint8_t add)
6412 {
6413         uint16_t ip_type;
6414         uint32_t ipv4_addr;
6415         uint8_t i, tun_type = 0;
6416         /* internal varialbe to convert ipv6 byte order */
6417         uint32_t convert_ipv6[4];
6418         int val, ret = 0;
6419         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6420         struct i40e_vsi *vsi = pf->main_vsi;
6421         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6422         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6423
6424         cld_filter = rte_zmalloc("tunnel_filter",
6425                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6426                 0);
6427
6428         if (NULL == cld_filter) {
6429                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6430                 return -EINVAL;
6431         }
6432         pfilter = cld_filter;
6433
6434         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6435         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6436
6437         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6438         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6439                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6440                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6441                 rte_memcpy(&pfilter->ipaddr.v4.data,
6442                                 &rte_cpu_to_le_32(ipv4_addr),
6443                                 sizeof(pfilter->ipaddr.v4.data));
6444         } else {
6445                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6446                 for (i = 0; i < 4; i++) {
6447                         convert_ipv6[i] =
6448                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6449                 }
6450                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6451                                 sizeof(pfilter->ipaddr.v6.data));
6452         }
6453
6454         /* check tunneled type */
6455         switch (tunnel_filter->tunnel_type) {
6456         case RTE_TUNNEL_TYPE_VXLAN:
6457                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6458                 break;
6459         case RTE_TUNNEL_TYPE_NVGRE:
6460                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6461                 break;
6462         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6463                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6464                 break;
6465         default:
6466                 /* Other tunnel types is not supported. */
6467                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6468                 rte_free(cld_filter);
6469                 return -EINVAL;
6470         }
6471
6472         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6473                                                 &pfilter->flags);
6474         if (val < 0) {
6475                 rte_free(cld_filter);
6476                 return -EINVAL;
6477         }
6478
6479         pfilter->flags |= rte_cpu_to_le_16(
6480                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6481                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6482         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6483         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6484
6485         if (add)
6486                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6487         else
6488                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6489                                                 cld_filter, 1);
6490
6491         rte_free(cld_filter);
6492         return ret;
6493 }
6494
6495 static int
6496 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6497 {
6498         uint8_t i;
6499
6500         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6501                 if (pf->vxlan_ports[i] == port)
6502                         return i;
6503         }
6504
6505         return -1;
6506 }
6507
6508 static int
6509 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6510 {
6511         int  idx, ret;
6512         uint8_t filter_idx;
6513         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6514
6515         idx = i40e_get_vxlan_port_idx(pf, port);
6516
6517         /* Check if port already exists */
6518         if (idx >= 0) {
6519                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6520                 return -EINVAL;
6521         }
6522
6523         /* Now check if there is space to add the new port */
6524         idx = i40e_get_vxlan_port_idx(pf, 0);
6525         if (idx < 0) {
6526                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6527                         "not adding port %d", port);
6528                 return -ENOSPC;
6529         }
6530
6531         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6532                                         &filter_idx, NULL);
6533         if (ret < 0) {
6534                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6535                 return -1;
6536         }
6537
6538         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6539                          port,  filter_idx);
6540
6541         /* New port: add it and mark its index in the bitmap */
6542         pf->vxlan_ports[idx] = port;
6543         pf->vxlan_bitmap |= (1 << idx);
6544
6545         if (!(pf->flags & I40E_FLAG_VXLAN))
6546                 pf->flags |= I40E_FLAG_VXLAN;
6547
6548         return 0;
6549 }
6550
6551 static int
6552 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6553 {
6554         int idx;
6555         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6556
6557         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6558                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6559                 return -EINVAL;
6560         }
6561
6562         idx = i40e_get_vxlan_port_idx(pf, port);
6563
6564         if (idx < 0) {
6565                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6566                 return -EINVAL;
6567         }
6568
6569         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6570                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6571                 return -1;
6572         }
6573
6574         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6575                         port, idx);
6576
6577         pf->vxlan_ports[idx] = 0;
6578         pf->vxlan_bitmap &= ~(1 << idx);
6579
6580         if (!pf->vxlan_bitmap)
6581                 pf->flags &= ~I40E_FLAG_VXLAN;
6582
6583         return 0;
6584 }
6585
6586 /* Add UDP tunneling port */
6587 static int
6588 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6589                              struct rte_eth_udp_tunnel *udp_tunnel)
6590 {
6591         int ret = 0;
6592         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6593
6594         if (udp_tunnel == NULL)
6595                 return -EINVAL;
6596
6597         switch (udp_tunnel->prot_type) {
6598         case RTE_TUNNEL_TYPE_VXLAN:
6599                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6600                 break;
6601
6602         case RTE_TUNNEL_TYPE_GENEVE:
6603         case RTE_TUNNEL_TYPE_TEREDO:
6604                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6605                 ret = -1;
6606                 break;
6607
6608         default:
6609                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6610                 ret = -1;
6611                 break;
6612         }
6613
6614         return ret;
6615 }
6616
6617 /* Remove UDP tunneling port */
6618 static int
6619 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6620                              struct rte_eth_udp_tunnel *udp_tunnel)
6621 {
6622         int ret = 0;
6623         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6624
6625         if (udp_tunnel == NULL)
6626                 return -EINVAL;
6627
6628         switch (udp_tunnel->prot_type) {
6629         case RTE_TUNNEL_TYPE_VXLAN:
6630                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6631                 break;
6632         case RTE_TUNNEL_TYPE_GENEVE:
6633         case RTE_TUNNEL_TYPE_TEREDO:
6634                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6635                 ret = -1;
6636                 break;
6637         default:
6638                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6639                 ret = -1;
6640                 break;
6641         }
6642
6643         return ret;
6644 }
6645
6646 /* Calculate the maximum number of contiguous PF queues that are configured */
6647 static int
6648 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6649 {
6650         struct rte_eth_dev_data *data = pf->dev_data;
6651         int i, num;
6652         struct i40e_rx_queue *rxq;
6653
6654         num = 0;
6655         for (i = 0; i < pf->lan_nb_qps; i++) {
6656                 rxq = data->rx_queues[i];
6657                 if (rxq && rxq->q_set)
6658                         num++;
6659                 else
6660                         break;
6661         }
6662
6663         return num;
6664 }
6665
6666 /* Configure RSS */
6667 static int
6668 i40e_pf_config_rss(struct i40e_pf *pf)
6669 {
6670         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6671         struct rte_eth_rss_conf rss_conf;
6672         uint32_t i, lut = 0;
6673         uint16_t j, num;
6674
6675         /*
6676          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6677          * It's necessary to calulate the actual PF queues that are configured.
6678          */
6679         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6680                 num = i40e_pf_calc_configured_queues_num(pf);
6681         else
6682                 num = pf->dev_data->nb_rx_queues;
6683
6684         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6685         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6686                         num);
6687
6688         if (num == 0) {
6689                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6690                 return -ENOTSUP;
6691         }
6692
6693         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6694                 if (j == num)
6695                         j = 0;
6696                 lut = (lut << 8) | (j & ((0x1 <<
6697                         hw->func_caps.rss_table_entry_width) - 1));
6698                 if ((i & 3) == 3)
6699                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6700         }
6701
6702         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6703         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6704                 i40e_pf_disable_rss(pf);
6705                 return 0;
6706         }
6707         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6708                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6709                 /* Random default keys */
6710                 static uint32_t rss_key_default[] = {0x6b793944,
6711                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6712                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6713                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6714
6715                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6716                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6717                                                         sizeof(uint32_t);
6718         }
6719
6720         return i40e_hw_rss_hash_set(pf, &rss_conf);
6721 }
6722
6723 static int
6724 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6725                                struct rte_eth_tunnel_filter_conf *filter)
6726 {
6727         if (pf == NULL || filter == NULL) {
6728                 PMD_DRV_LOG(ERR, "Invalid parameter");
6729                 return -EINVAL;
6730         }
6731
6732         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6733                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6734                 return -EINVAL;
6735         }
6736
6737         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6738                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6739                 return -EINVAL;
6740         }
6741
6742         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6743                 (is_zero_ether_addr(&filter->outer_mac))) {
6744                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6745                 return -EINVAL;
6746         }
6747
6748         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6749                 (is_zero_ether_addr(&filter->inner_mac))) {
6750                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6751                 return -EINVAL;
6752         }
6753
6754         return 0;
6755 }
6756
6757 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6758 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6759 static int
6760 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6761 {
6762         uint32_t val, reg;
6763         int ret = -EINVAL;
6764
6765         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6766         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6767
6768         if (len == 3) {
6769                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6770         } else if (len == 4) {
6771                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6772         } else {
6773                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6774                 return ret;
6775         }
6776
6777         if (reg != val) {
6778                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6779                                                    reg, NULL);
6780                 if (ret != 0)
6781                         return ret;
6782         } else {
6783                 ret = 0;
6784         }
6785         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6786                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6787
6788         return ret;
6789 }
6790
6791 static int
6792 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6793 {
6794         int ret = -EINVAL;
6795
6796         if (!hw || !cfg)
6797                 return -EINVAL;
6798
6799         switch (cfg->cfg_type) {
6800         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6801                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6802                 break;
6803         default:
6804                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6805                 break;
6806         }
6807
6808         return ret;
6809 }
6810
6811 static int
6812 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6813                                enum rte_filter_op filter_op,
6814                                void *arg)
6815 {
6816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6817         int ret = I40E_ERR_PARAM;
6818
6819         switch (filter_op) {
6820         case RTE_ETH_FILTER_SET:
6821                 ret = i40e_dev_global_config_set(hw,
6822                         (struct rte_eth_global_cfg *)arg);
6823                 break;
6824         default:
6825                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6826                 break;
6827         }
6828
6829         return ret;
6830 }
6831
6832 static int
6833 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6834                           enum rte_filter_op filter_op,
6835                           void *arg)
6836 {
6837         struct rte_eth_tunnel_filter_conf *filter;
6838         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6839         int ret = I40E_SUCCESS;
6840
6841         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6842
6843         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6844                 return I40E_ERR_PARAM;
6845
6846         switch (filter_op) {
6847         case RTE_ETH_FILTER_NOP:
6848                 if (!(pf->flags & I40E_FLAG_VXLAN))
6849                         ret = I40E_NOT_SUPPORTED;
6850                 break;
6851         case RTE_ETH_FILTER_ADD:
6852                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6853                 break;
6854         case RTE_ETH_FILTER_DELETE:
6855                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6856                 break;
6857         default:
6858                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6859                 ret = I40E_ERR_PARAM;
6860                 break;
6861         }
6862
6863         return ret;
6864 }
6865
6866 static int
6867 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6868 {
6869         int ret = 0;
6870         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6871
6872         /* RSS setup */
6873         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6874                 ret = i40e_pf_config_rss(pf);
6875         else
6876                 i40e_pf_disable_rss(pf);
6877
6878         return ret;
6879 }
6880
6881 /* Get the symmetric hash enable configurations per port */
6882 static void
6883 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6884 {
6885         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6886
6887         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6888 }
6889
6890 /* Set the symmetric hash enable configurations per port */
6891 static void
6892 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6893 {
6894         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6895
6896         if (enable > 0) {
6897                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6898                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6899                                                         "been enabled");
6900                         return;
6901                 }
6902                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6903         } else {
6904                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6905                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6906                                                         "been disabled");
6907                         return;
6908                 }
6909                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6910         }
6911         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6912         I40E_WRITE_FLUSH(hw);
6913 }
6914
6915 /*
6916  * Get global configurations of hash function type and symmetric hash enable
6917  * per flow type (pctype). Note that global configuration means it affects all
6918  * the ports on the same NIC.
6919  */
6920 static int
6921 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6922                                    struct rte_eth_hash_global_conf *g_cfg)
6923 {
6924         uint32_t reg, mask = I40E_FLOW_TYPES;
6925         uint16_t i;
6926         enum i40e_filter_pctype pctype;
6927
6928         memset(g_cfg, 0, sizeof(*g_cfg));
6929         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6930         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6931                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6932         else
6933                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6934         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6935                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6936
6937         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6938                 if (!(mask & (1UL << i)))
6939                         continue;
6940                 mask &= ~(1UL << i);
6941                 /* Bit set indicats the coresponding flow type is supported */
6942                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6943                 /* if flowtype is invalid, continue */
6944                 if (!I40E_VALID_FLOW(i))
6945                         continue;
6946                 pctype = i40e_flowtype_to_pctype(i);
6947                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6948                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6949                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6950         }
6951
6952         return 0;
6953 }
6954
6955 static int
6956 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6957 {
6958         uint32_t i;
6959         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6960
6961         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6962                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6963                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6964                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6965                                                 g_cfg->hash_func);
6966                 return -EINVAL;
6967         }
6968
6969         /*
6970          * As i40e supports less than 32 flow types, only first 32 bits need to
6971          * be checked.
6972          */
6973         mask0 = g_cfg->valid_bit_mask[0];
6974         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6975                 if (i == 0) {
6976                         /* Check if any unsupported flow type configured */
6977                         if ((mask0 | i40e_mask) ^ i40e_mask)
6978                                 goto mask_err;
6979                 } else {
6980                         if (g_cfg->valid_bit_mask[i])
6981                                 goto mask_err;
6982                 }
6983         }
6984
6985         return 0;
6986
6987 mask_err:
6988         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6989
6990         return -EINVAL;
6991 }
6992
6993 /*
6994  * Set global configurations of hash function type and symmetric hash enable
6995  * per flow type (pctype). Note any modifying global configuration will affect
6996  * all the ports on the same NIC.
6997  */
6998 static int
6999 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7000                                    struct rte_eth_hash_global_conf *g_cfg)
7001 {
7002         int ret;
7003         uint16_t i;
7004         uint32_t reg;
7005         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7006         enum i40e_filter_pctype pctype;
7007
7008         /* Check the input parameters */
7009         ret = i40e_hash_global_config_check(g_cfg);
7010         if (ret < 0)
7011                 return ret;
7012
7013         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7014                 if (!(mask0 & (1UL << i)))
7015                         continue;
7016                 mask0 &= ~(1UL << i);
7017                 /* if flowtype is invalid, continue */
7018                 if (!I40E_VALID_FLOW(i))
7019                         continue;
7020                 pctype = i40e_flowtype_to_pctype(i);
7021                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7022                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7023                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7024         }
7025
7026         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7027         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7028                 /* Toeplitz */
7029                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7030                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7031                                                                 "Toeplitz");
7032                         goto out;
7033                 }
7034                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7035         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7036                 /* Simple XOR */
7037                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7038                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7039                                                         "Simple XOR");
7040                         goto out;
7041                 }
7042                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7043         } else
7044                 /* Use the default, and keep it as it is */
7045                 goto out;
7046
7047         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7048
7049 out:
7050         I40E_WRITE_FLUSH(hw);
7051
7052         return 0;
7053 }
7054
7055 /**
7056  * Valid input sets for hash and flow director filters per PCTYPE
7057  */
7058 static uint64_t
7059 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7060                 enum rte_filter_type filter)
7061 {
7062         uint64_t valid;
7063
7064         static const uint64_t valid_hash_inset_table[] = {
7065                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7066                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7067                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7068                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7069                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7070                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7071                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7072                         I40E_INSET_FLEX_PAYLOAD,
7073                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7074                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7075                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7076                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7077                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7078                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7079                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7080                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7081                         I40E_INSET_FLEX_PAYLOAD,
7082                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7083                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7084                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7085                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7086                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7087                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7088                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7089                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7090                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7091                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7092                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7093                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7094                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7095                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7096                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7097                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7098                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7099                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7100                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7101                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7102                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7103                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7104                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7105                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7106                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7107                         I40E_INSET_FLEX_PAYLOAD,
7108                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7109                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7110                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7111                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7112                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7113                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7114                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7115                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7116                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7117                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7118                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7119                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7120                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7121                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7122                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7123                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7124                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7125                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7126                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7127                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7128                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7129                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7130                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7131                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7132                         I40E_INSET_FLEX_PAYLOAD,
7133                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7134                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7135                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7136                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7137                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7138                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7139                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7140                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7141                         I40E_INSET_FLEX_PAYLOAD,
7142                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7143                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7144                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7145                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7146                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7147                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7148                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7149                         I40E_INSET_FLEX_PAYLOAD,
7150                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7151                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7152                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7153                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7154                         I40E_INSET_FLEX_PAYLOAD,
7155         };
7156
7157         /**
7158          * Flow director supports only fields defined in
7159          * union rte_eth_fdir_flow.
7160          */
7161         static const uint64_t valid_fdir_inset_table[] = {
7162                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7163                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7164                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7165                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7166                 I40E_INSET_IPV4_TTL,
7167                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7168                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7169                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7170                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7171                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7172                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7173                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7174                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7175                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7176                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7177                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7178                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7179                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7180                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7181                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7182                 I40E_INSET_SCTP_VT,
7183                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7184                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7185                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7186                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7187                 I40E_INSET_IPV4_TTL,
7188                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7189                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7190                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7191                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7192                 I40E_INSET_IPV6_HOP_LIMIT,
7193                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7194                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7195                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7196                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7197                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7198                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7199                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7200                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7201                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7202                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7203                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7204                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7205                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7206                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7207                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7208                 I40E_INSET_SCTP_VT,
7209                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7210                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7211                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7212                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7213                 I40E_INSET_IPV6_HOP_LIMIT,
7214                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7215                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7216                 I40E_INSET_LAST_ETHER_TYPE,
7217         };
7218
7219         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7220                 return 0;
7221         if (filter == RTE_ETH_FILTER_HASH)
7222                 valid = valid_hash_inset_table[pctype];
7223         else
7224                 valid = valid_fdir_inset_table[pctype];
7225
7226         return valid;
7227 }
7228
7229 /**
7230  * Validate if the input set is allowed for a specific PCTYPE
7231  */
7232 static int
7233 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7234                 enum rte_filter_type filter, uint64_t inset)
7235 {
7236         uint64_t valid;
7237
7238         valid = i40e_get_valid_input_set(pctype, filter);
7239         if (inset & (~valid))
7240                 return -EINVAL;
7241
7242         return 0;
7243 }
7244
7245 /* default input set fields combination per pctype */
7246 static uint64_t
7247 i40e_get_default_input_set(uint16_t pctype)
7248 {
7249         static const uint64_t default_inset_table[] = {
7250                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7251                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7252                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7253                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7254                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7255                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7256                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7257                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7258                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7259                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7260                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7261                         I40E_INSET_SCTP_VT,
7262                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7263                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7264                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7265                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7266                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7267                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7268                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7269                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7270                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7271                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7272                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7273                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7274                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7275                         I40E_INSET_SCTP_VT,
7276                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7277                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7278                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7279                         I40E_INSET_LAST_ETHER_TYPE,
7280         };
7281
7282         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7283                 return 0;
7284
7285         return default_inset_table[pctype];
7286 }
7287
7288 /**
7289  * Parse the input set from index to logical bit masks
7290  */
7291 static int
7292 i40e_parse_input_set(uint64_t *inset,
7293                      enum i40e_filter_pctype pctype,
7294                      enum rte_eth_input_set_field *field,
7295                      uint16_t size)
7296 {
7297         uint16_t i, j;
7298         int ret = -EINVAL;
7299
7300         static const struct {
7301                 enum rte_eth_input_set_field field;
7302                 uint64_t inset;
7303         } inset_convert_table[] = {
7304                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7305                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7306                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7307                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7308                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7309                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7310                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7311                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7312                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7313                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7314                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7315                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7316                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7317                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7318                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7319                         I40E_INSET_IPV6_NEXT_HDR},
7320                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7321                         I40E_INSET_IPV6_HOP_LIMIT},
7322                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7323                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7324                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7325                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7326                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7327                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7328                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7329                         I40E_INSET_SCTP_VT},
7330                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7331                         I40E_INSET_TUNNEL_DMAC},
7332                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7333                         I40E_INSET_VLAN_TUNNEL},
7334                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7335                         I40E_INSET_TUNNEL_ID},
7336                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7337                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7338                         I40E_INSET_FLEX_PAYLOAD_W1},
7339                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7340                         I40E_INSET_FLEX_PAYLOAD_W2},
7341                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7342                         I40E_INSET_FLEX_PAYLOAD_W3},
7343                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7344                         I40E_INSET_FLEX_PAYLOAD_W4},
7345                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7346                         I40E_INSET_FLEX_PAYLOAD_W5},
7347                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7348                         I40E_INSET_FLEX_PAYLOAD_W6},
7349                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7350                         I40E_INSET_FLEX_PAYLOAD_W7},
7351                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7352                         I40E_INSET_FLEX_PAYLOAD_W8},
7353         };
7354
7355         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7356                 return ret;
7357
7358         /* Only one item allowed for default or all */
7359         if (size == 1) {
7360                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7361                         *inset = i40e_get_default_input_set(pctype);
7362                         return 0;
7363                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7364                         *inset = I40E_INSET_NONE;
7365                         return 0;
7366                 }
7367         }
7368
7369         for (i = 0, *inset = 0; i < size; i++) {
7370                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7371                         if (field[i] == inset_convert_table[j].field) {
7372                                 *inset |= inset_convert_table[j].inset;
7373                                 break;
7374                         }
7375                 }
7376
7377                 /* It contains unsupported input set, return immediately */
7378                 if (j == RTE_DIM(inset_convert_table))
7379                         return ret;
7380         }
7381
7382         return 0;
7383 }
7384
7385 /**
7386  * Translate the input set from bit masks to register aware bit masks
7387  * and vice versa
7388  */
7389 static uint64_t
7390 i40e_translate_input_set_reg(uint64_t input)
7391 {
7392         uint64_t val = 0;
7393         uint16_t i;
7394
7395         static const struct {
7396                 uint64_t inset;
7397                 uint64_t inset_reg;
7398         } inset_map[] = {
7399                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7400                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7401                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7402                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7403                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7404                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7405                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7406                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7407                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7408                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7409                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7410                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7411                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7412                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7413                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7414                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7415                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7416                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7417                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7418                 {I40E_INSET_TUNNEL_DMAC,
7419                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7420                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7421                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7422                 {I40E_INSET_TUNNEL_SRC_PORT,
7423                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7424                 {I40E_INSET_TUNNEL_DST_PORT,
7425                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7426                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7427                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7428                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7429                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7430                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7431                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7432                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7433                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7434                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7435         };
7436
7437         if (input == 0)
7438                 return val;
7439
7440         /* Translate input set to register aware inset */
7441         for (i = 0; i < RTE_DIM(inset_map); i++) {
7442                 if (input & inset_map[i].inset)
7443                         val |= inset_map[i].inset_reg;
7444         }
7445
7446         return val;
7447 }
7448
7449 static int
7450 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7451 {
7452         uint8_t i, idx = 0;
7453         uint64_t inset_need_mask = inset;
7454
7455         static const struct {
7456                 uint64_t inset;
7457                 uint32_t mask;
7458         } inset_mask_map[] = {
7459                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7460                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7461                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7462                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7463                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7464                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7465                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7466                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7467         };
7468
7469         if (!inset || !mask || !nb_elem)
7470                 return 0;
7471
7472         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7473                 /* Clear the inset bit, if no MASK is required,
7474                  * for example proto + ttl
7475                  */
7476                 if ((inset & inset_mask_map[i].inset) ==
7477                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7478                         inset_need_mask &= ~inset_mask_map[i].inset;
7479                 if (!inset_need_mask)
7480                         return 0;
7481         }
7482         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7483                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7484                     inset_mask_map[i].inset) {
7485                         if (idx >= nb_elem) {
7486                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7487                                 return -EINVAL;
7488                         }
7489                         mask[idx] = inset_mask_map[i].mask;
7490                         idx++;
7491                 }
7492         }
7493
7494         return idx;
7495 }
7496
7497 static void
7498 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7499 {
7500         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7501
7502         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7503         if (reg != val)
7504                 i40e_write_rx_ctl(hw, addr, val);
7505         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7506                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7507 }
7508
7509 static void
7510 i40e_filter_input_set_init(struct i40e_pf *pf)
7511 {
7512         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7513         enum i40e_filter_pctype pctype;
7514         uint64_t input_set, inset_reg;
7515         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7516         int num, i;
7517
7518         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7519              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7520                 if (!I40E_VALID_PCTYPE(pctype))
7521                         continue;
7522                 input_set = i40e_get_default_input_set(pctype);
7523
7524                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7525                                                    I40E_INSET_MASK_NUM_REG);
7526                 if (num < 0)
7527                         return;
7528                 inset_reg = i40e_translate_input_set_reg(input_set);
7529
7530                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7531                                       (uint32_t)(inset_reg & UINT32_MAX));
7532                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7533                                      (uint32_t)((inset_reg >>
7534                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7535                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7536                                       (uint32_t)(inset_reg & UINT32_MAX));
7537                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7538                                      (uint32_t)((inset_reg >>
7539                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7540
7541                 for (i = 0; i < num; i++) {
7542                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7543                                              mask_reg[i]);
7544                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7545                                              mask_reg[i]);
7546                 }
7547                 /*clear unused mask registers of the pctype */
7548                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7549                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7550                                              0);
7551                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7552                                              0);
7553                 }
7554                 I40E_WRITE_FLUSH(hw);
7555
7556                 /* store the default input set */
7557                 pf->hash_input_set[pctype] = input_set;
7558                 pf->fdir.input_set[pctype] = input_set;
7559         }
7560 }
7561
7562 int
7563 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7564                          struct rte_eth_input_set_conf *conf)
7565 {
7566         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7567         enum i40e_filter_pctype pctype;
7568         uint64_t input_set, inset_reg = 0;
7569         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7570         int ret, i, num;
7571
7572         if (!conf) {
7573                 PMD_DRV_LOG(ERR, "Invalid pointer");
7574                 return -EFAULT;
7575         }
7576         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7577             conf->op != RTE_ETH_INPUT_SET_ADD) {
7578                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7579                 return -EINVAL;
7580         }
7581
7582         if (!I40E_VALID_FLOW(conf->flow_type)) {
7583                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7584                 return -EINVAL;
7585         }
7586         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7587         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7588                                    conf->inset_size);
7589         if (ret) {
7590                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7591                 return -EINVAL;
7592         }
7593         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7594                                     input_set) != 0) {
7595                 PMD_DRV_LOG(ERR, "Invalid input set");
7596                 return -EINVAL;
7597         }
7598         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7599                 /* get inset value in register */
7600                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7601                 inset_reg <<= I40E_32_BIT_WIDTH;
7602                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7603                 input_set |= pf->hash_input_set[pctype];
7604         }
7605         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7606                                            I40E_INSET_MASK_NUM_REG);
7607         if (num < 0)
7608                 return -EINVAL;
7609
7610         inset_reg |= i40e_translate_input_set_reg(input_set);
7611
7612         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7613                               (uint32_t)(inset_reg & UINT32_MAX));
7614         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7615                              (uint32_t)((inset_reg >>
7616                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7617
7618         for (i = 0; i < num; i++)
7619                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7620                                      mask_reg[i]);
7621         /*clear unused mask registers of the pctype */
7622         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7623                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7624                                      0);
7625         I40E_WRITE_FLUSH(hw);
7626
7627         pf->hash_input_set[pctype] = input_set;
7628         return 0;
7629 }
7630
7631 int
7632 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7633                          struct rte_eth_input_set_conf *conf)
7634 {
7635         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7636         enum i40e_filter_pctype pctype;
7637         uint64_t input_set, inset_reg = 0;
7638         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7639         int ret, i, num;
7640
7641         if (!hw || !conf) {
7642                 PMD_DRV_LOG(ERR, "Invalid pointer");
7643                 return -EFAULT;
7644         }
7645         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7646             conf->op != RTE_ETH_INPUT_SET_ADD) {
7647                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7648                 return -EINVAL;
7649         }
7650
7651         if (!I40E_VALID_FLOW(conf->flow_type)) {
7652                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7653                 return -EINVAL;
7654         }
7655         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7656         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7657                                    conf->inset_size);
7658         if (ret) {
7659                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7660                 return -EINVAL;
7661         }
7662         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7663                                     input_set) != 0) {
7664                 PMD_DRV_LOG(ERR, "Invalid input set");
7665                 return -EINVAL;
7666         }
7667
7668         /* get inset value in register */
7669         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7670         inset_reg <<= I40E_32_BIT_WIDTH;
7671         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7672
7673         /* Can not change the inset reg for flex payload for fdir,
7674          * it is done by writing I40E_PRTQF_FD_FLXINSET
7675          * in i40e_set_flex_mask_on_pctype.
7676          */
7677         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7678                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7679         else
7680                 input_set |= pf->fdir.input_set[pctype];
7681         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7682                                            I40E_INSET_MASK_NUM_REG);
7683         if (num < 0)
7684                 return -EINVAL;
7685
7686         inset_reg |= i40e_translate_input_set_reg(input_set);
7687
7688         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7689                               (uint32_t)(inset_reg & UINT32_MAX));
7690         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7691                              (uint32_t)((inset_reg >>
7692                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7693
7694         for (i = 0; i < num; i++)
7695                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7696                                      mask_reg[i]);
7697         /*clear unused mask registers of the pctype */
7698         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7699                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7700                                      0);
7701         I40E_WRITE_FLUSH(hw);
7702
7703         pf->fdir.input_set[pctype] = input_set;
7704         return 0;
7705 }
7706
7707 static int
7708 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7709 {
7710         int ret = 0;
7711
7712         if (!hw || !info) {
7713                 PMD_DRV_LOG(ERR, "Invalid pointer");
7714                 return -EFAULT;
7715         }
7716
7717         switch (info->info_type) {
7718         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7719                 i40e_get_symmetric_hash_enable_per_port(hw,
7720                                         &(info->info.enable));
7721                 break;
7722         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7723                 ret = i40e_get_hash_filter_global_config(hw,
7724                                 &(info->info.global_conf));
7725                 break;
7726         default:
7727                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7728                                                         info->info_type);
7729                 ret = -EINVAL;
7730                 break;
7731         }
7732
7733         return ret;
7734 }
7735
7736 static int
7737 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7738 {
7739         int ret = 0;
7740
7741         if (!hw || !info) {
7742                 PMD_DRV_LOG(ERR, "Invalid pointer");
7743                 return -EFAULT;
7744         }
7745
7746         switch (info->info_type) {
7747         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7748                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7749                 break;
7750         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7751                 ret = i40e_set_hash_filter_global_config(hw,
7752                                 &(info->info.global_conf));
7753                 break;
7754         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7755                 ret = i40e_hash_filter_inset_select(hw,
7756                                                &(info->info.input_set_conf));
7757                 break;
7758
7759         default:
7760                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7761                                                         info->info_type);
7762                 ret = -EINVAL;
7763                 break;
7764         }
7765
7766         return ret;
7767 }
7768
7769 /* Operations for hash function */
7770 static int
7771 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7772                       enum rte_filter_op filter_op,
7773                       void *arg)
7774 {
7775         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7776         int ret = 0;
7777
7778         switch (filter_op) {
7779         case RTE_ETH_FILTER_NOP:
7780                 break;
7781         case RTE_ETH_FILTER_GET:
7782                 ret = i40e_hash_filter_get(hw,
7783                         (struct rte_eth_hash_filter_info *)arg);
7784                 break;
7785         case RTE_ETH_FILTER_SET:
7786                 ret = i40e_hash_filter_set(hw,
7787                         (struct rte_eth_hash_filter_info *)arg);
7788                 break;
7789         default:
7790                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7791                                                                 filter_op);
7792                 ret = -ENOTSUP;
7793                 break;
7794         }
7795
7796         return ret;
7797 }
7798
7799 /*
7800  * Configure ethertype filter, which can director packet by filtering
7801  * with mac address and ether_type or only ether_type
7802  */
7803 static int
7804 i40e_ethertype_filter_set(struct i40e_pf *pf,
7805                         struct rte_eth_ethertype_filter *filter,
7806                         bool add)
7807 {
7808         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7809         struct i40e_control_filter_stats stats;
7810         uint16_t flags = 0;
7811         int ret;
7812
7813         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7814                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7815                 return -EINVAL;
7816         }
7817         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7818                 filter->ether_type == ETHER_TYPE_IPv6) {
7819                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7820                         " control packet filter.", filter->ether_type);
7821                 return -EINVAL;
7822         }
7823         if (filter->ether_type == ETHER_TYPE_VLAN)
7824                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7825                         " not supported.");
7826
7827         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7828                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7829         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7830                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7831         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7832
7833         memset(&stats, 0, sizeof(stats));
7834         ret = i40e_aq_add_rem_control_packet_filter(hw,
7835                         filter->mac_addr.addr_bytes,
7836                         filter->ether_type, flags,
7837                         pf->main_vsi->seid,
7838                         filter->queue, add, &stats, NULL);
7839
7840         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7841                          " mac_etype_used = %u, etype_used = %u,"
7842                          " mac_etype_free = %u, etype_free = %u\n",
7843                          ret, stats.mac_etype_used, stats.etype_used,
7844                          stats.mac_etype_free, stats.etype_free);
7845         if (ret < 0)
7846                 return -ENOSYS;
7847         return 0;
7848 }
7849
7850 /*
7851  * Handle operations for ethertype filter.
7852  */
7853 static int
7854 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7855                                 enum rte_filter_op filter_op,
7856                                 void *arg)
7857 {
7858         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7859         int ret = 0;
7860
7861         if (filter_op == RTE_ETH_FILTER_NOP)
7862                 return ret;
7863
7864         if (arg == NULL) {
7865                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7866                             filter_op);
7867                 return -EINVAL;
7868         }
7869
7870         switch (filter_op) {
7871         case RTE_ETH_FILTER_ADD:
7872                 ret = i40e_ethertype_filter_set(pf,
7873                         (struct rte_eth_ethertype_filter *)arg,
7874                         TRUE);
7875                 break;
7876         case RTE_ETH_FILTER_DELETE:
7877                 ret = i40e_ethertype_filter_set(pf,
7878                         (struct rte_eth_ethertype_filter *)arg,
7879                         FALSE);
7880                 break;
7881         default:
7882                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7883                 ret = -ENOSYS;
7884                 break;
7885         }
7886         return ret;
7887 }
7888
7889 static int
7890 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7891                      enum rte_filter_type filter_type,
7892                      enum rte_filter_op filter_op,
7893                      void *arg)
7894 {
7895         int ret = 0;
7896
7897         if (dev == NULL)
7898                 return -EINVAL;
7899
7900         switch (filter_type) {
7901         case RTE_ETH_FILTER_NONE:
7902                 /* For global configuration */
7903                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7904                 break;
7905         case RTE_ETH_FILTER_HASH:
7906                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7907                 break;
7908         case RTE_ETH_FILTER_MACVLAN:
7909                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7910                 break;
7911         case RTE_ETH_FILTER_ETHERTYPE:
7912                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7913                 break;
7914         case RTE_ETH_FILTER_TUNNEL:
7915                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7916                 break;
7917         case RTE_ETH_FILTER_FDIR:
7918                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7919                 break;
7920         default:
7921                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7922                                                         filter_type);
7923                 ret = -EINVAL;
7924                 break;
7925         }
7926
7927         return ret;
7928 }
7929
7930 /*
7931  * Check and enable Extended Tag.
7932  * Enabling Extended Tag is important for 40G performance.
7933  */
7934 static void
7935 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7936 {
7937         uint32_t buf = 0;
7938         int ret;
7939
7940         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7941                                       PCI_DEV_CAP_REG);
7942         if (ret < 0) {
7943                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7944                             PCI_DEV_CAP_REG);
7945                 return;
7946         }
7947         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7948                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7949                 return;
7950         }
7951
7952         buf = 0;
7953         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7954                                       PCI_DEV_CTRL_REG);
7955         if (ret < 0) {
7956                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7957                             PCI_DEV_CTRL_REG);
7958                 return;
7959         }
7960         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7961                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7962                 return;
7963         }
7964         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7965         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7966                                        PCI_DEV_CTRL_REG);
7967         if (ret < 0) {
7968                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7969                             PCI_DEV_CTRL_REG);
7970                 return;
7971         }
7972 }
7973
7974 /*
7975  * As some registers wouldn't be reset unless a global hardware reset,
7976  * hardware initialization is needed to put those registers into an
7977  * expected initial state.
7978  */
7979 static void
7980 i40e_hw_init(struct rte_eth_dev *dev)
7981 {
7982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7983
7984         i40e_enable_extended_tag(dev);
7985
7986         /* clear the PF Queue Filter control register */
7987         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7988
7989         /* Disable symmetric hash per port */
7990         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7991 }
7992
7993 enum i40e_filter_pctype
7994 i40e_flowtype_to_pctype(uint16_t flow_type)
7995 {
7996         static const enum i40e_filter_pctype pctype_table[] = {
7997                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7998                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7999                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8000                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8001                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8002                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8003                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8004                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8005                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8006                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8007                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8008                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8009                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8010                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8011                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8012                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8013                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8014                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8015                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8016         };
8017
8018         return pctype_table[flow_type];
8019 }
8020
8021 uint16_t
8022 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8023 {
8024         static const uint16_t flowtype_table[] = {
8025                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8026                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8027                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8028                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8029                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8030                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8031                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8032                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8033                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8034                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8035                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8036                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8037                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8038                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8039                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8040                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8041                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8042                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8043                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8044         };
8045
8046         return flowtype_table[pctype];
8047 }
8048
8049 /*
8050  * On X710, performance number is far from the expectation on recent firmware
8051  * versions; on XL710, performance number is also far from the expectation on
8052  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8053  * mode is enabled and port MAC address is equal to the packet destination MAC
8054  * address. The fix for this issue may not be integrated in the following
8055  * firmware version. So the workaround in software driver is needed. It needs
8056  * to modify the initial values of 3 internal only registers for both X710 and
8057  * XL710. Note that the values for X710 or XL710 could be different, and the
8058  * workaround can be removed when it is fixed in firmware in the future.
8059  */
8060
8061 /* For both X710 and XL710 */
8062 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8063 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8064
8065 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8066 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8067
8068 /* For X710 */
8069 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8070 /* For XL710 */
8071 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8072 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8073
8074 static void
8075 i40e_configure_registers(struct i40e_hw *hw)
8076 {
8077         static struct {
8078                 uint32_t addr;
8079                 uint64_t val;
8080         } reg_table[] = {
8081                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8082                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8083                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8084         };
8085         uint64_t reg;
8086         uint32_t i;
8087         int ret;
8088
8089         for (i = 0; i < RTE_DIM(reg_table); i++) {
8090                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8091                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8092                                 reg_table[i].val =
8093                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8094                         else /* For X710 */
8095                                 reg_table[i].val =
8096                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8097                 }
8098
8099                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8100                                                         &reg, NULL);
8101                 if (ret < 0) {
8102                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8103                                                         reg_table[i].addr);
8104                         break;
8105                 }
8106                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8107                                                 reg_table[i].addr, reg);
8108                 if (reg == reg_table[i].val)
8109                         continue;
8110
8111                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8112                                                 reg_table[i].val, NULL);
8113                 if (ret < 0) {
8114                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8115                                 "address of 0x%"PRIx32, reg_table[i].val,
8116                                                         reg_table[i].addr);
8117                         break;
8118                 }
8119                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8120                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8121         }
8122 }
8123
8124 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8125 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8126 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8127 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8128 static int
8129 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8130 {
8131         uint32_t reg;
8132         int ret;
8133
8134         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8135                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8136                 return -EINVAL;
8137         }
8138
8139         /* Configure for double VLAN RX stripping */
8140         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8141         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8142                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8143                 ret = i40e_aq_debug_write_register(hw,
8144                                                    I40E_VSI_TSR(vsi->vsi_id),
8145                                                    reg, NULL);
8146                 if (ret < 0) {
8147                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8148                                     vsi->vsi_id);
8149                         return I40E_ERR_CONFIG;
8150                 }
8151         }
8152
8153         /* Configure for double VLAN TX insertion */
8154         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8155         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8156                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8157                 ret = i40e_aq_debug_write_register(hw,
8158                                                    I40E_VSI_L2TAGSTXVALID(
8159                                                    vsi->vsi_id), reg, NULL);
8160                 if (ret < 0) {
8161                         PMD_DRV_LOG(ERR, "Failed to update "
8162                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8163                         return I40E_ERR_CONFIG;
8164                 }
8165         }
8166
8167         return 0;
8168 }
8169
8170 /**
8171  * i40e_aq_add_mirror_rule
8172  * @hw: pointer to the hardware structure
8173  * @seid: VEB seid to add mirror rule to
8174  * @dst_id: destination vsi seid
8175  * @entries: Buffer which contains the entities to be mirrored
8176  * @count: number of entities contained in the buffer
8177  * @rule_id:the rule_id of the rule to be added
8178  *
8179  * Add a mirror rule for a given veb.
8180  *
8181  **/
8182 static enum i40e_status_code
8183 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8184                         uint16_t seid, uint16_t dst_id,
8185                         uint16_t rule_type, uint16_t *entries,
8186                         uint16_t count, uint16_t *rule_id)
8187 {
8188         struct i40e_aq_desc desc;
8189         struct i40e_aqc_add_delete_mirror_rule cmd;
8190         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8191                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8192                 &desc.params.raw;
8193         uint16_t buff_len;
8194         enum i40e_status_code status;
8195
8196         i40e_fill_default_direct_cmd_desc(&desc,
8197                                           i40e_aqc_opc_add_mirror_rule);
8198         memset(&cmd, 0, sizeof(cmd));
8199
8200         buff_len = sizeof(uint16_t) * count;
8201         desc.datalen = rte_cpu_to_le_16(buff_len);
8202         if (buff_len > 0)
8203                 desc.flags |= rte_cpu_to_le_16(
8204                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8205         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8206                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8207         cmd.num_entries = rte_cpu_to_le_16(count);
8208         cmd.seid = rte_cpu_to_le_16(seid);
8209         cmd.destination = rte_cpu_to_le_16(dst_id);
8210
8211         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8212         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8213         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8214                          "rule_id = %u"
8215                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8216                          hw->aq.asq_last_status, resp->rule_id,
8217                          resp->mirror_rules_used, resp->mirror_rules_free);
8218         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8219
8220         return status;
8221 }
8222
8223 /**
8224  * i40e_aq_del_mirror_rule
8225  * @hw: pointer to the hardware structure
8226  * @seid: VEB seid to add mirror rule to
8227  * @entries: Buffer which contains the entities to be mirrored
8228  * @count: number of entities contained in the buffer
8229  * @rule_id:the rule_id of the rule to be delete
8230  *
8231  * Delete a mirror rule for a given veb.
8232  *
8233  **/
8234 static enum i40e_status_code
8235 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8236                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8237                 uint16_t count, uint16_t rule_id)
8238 {
8239         struct i40e_aq_desc desc;
8240         struct i40e_aqc_add_delete_mirror_rule cmd;
8241         uint16_t buff_len = 0;
8242         enum i40e_status_code status;
8243         void *buff = NULL;
8244
8245         i40e_fill_default_direct_cmd_desc(&desc,
8246                                           i40e_aqc_opc_delete_mirror_rule);
8247         memset(&cmd, 0, sizeof(cmd));
8248         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8249                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8250                                                           I40E_AQ_FLAG_RD));
8251                 cmd.num_entries = count;
8252                 buff_len = sizeof(uint16_t) * count;
8253                 desc.datalen = rte_cpu_to_le_16(buff_len);
8254                 buff = (void *)entries;
8255         } else
8256                 /* rule id is filled in destination field for deleting mirror rule */
8257                 cmd.destination = rte_cpu_to_le_16(rule_id);
8258
8259         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8260                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8261         cmd.seid = rte_cpu_to_le_16(seid);
8262
8263         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8264         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8265
8266         return status;
8267 }
8268
8269 /**
8270  * i40e_mirror_rule_set
8271  * @dev: pointer to the hardware structure
8272  * @mirror_conf: mirror rule info
8273  * @sw_id: mirror rule's sw_id
8274  * @on: enable/disable
8275  *
8276  * set a mirror rule.
8277  *
8278  **/
8279 static int
8280 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8281                         struct rte_eth_mirror_conf *mirror_conf,
8282                         uint8_t sw_id, uint8_t on)
8283 {
8284         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8285         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8286         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8287         struct i40e_mirror_rule *parent = NULL;
8288         uint16_t seid, dst_seid, rule_id;
8289         uint16_t i, j = 0;
8290         int ret;
8291
8292         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8293
8294         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8295                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8296                         " without veb or vfs.");
8297                 return -ENOSYS;
8298         }
8299         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8300                 PMD_DRV_LOG(ERR, "mirror table is full.");
8301                 return -ENOSPC;
8302         }
8303         if (mirror_conf->dst_pool > pf->vf_num) {
8304                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8305                                  mirror_conf->dst_pool);
8306                 return -EINVAL;
8307         }
8308
8309         seid = pf->main_vsi->veb->seid;
8310
8311         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8312                 if (sw_id <= it->index) {
8313                         mirr_rule = it;
8314                         break;
8315                 }
8316                 parent = it;
8317         }
8318         if (mirr_rule && sw_id == mirr_rule->index) {
8319                 if (on) {
8320                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8321                         return -EEXIST;
8322                 } else {
8323                         ret = i40e_aq_del_mirror_rule(hw, seid,
8324                                         mirr_rule->rule_type,
8325                                         mirr_rule->entries,
8326                                         mirr_rule->num_entries, mirr_rule->id);
8327                         if (ret < 0) {
8328                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8329                                                    " ret = %d, aq_err = %d.",
8330                                                    ret, hw->aq.asq_last_status);
8331                                 return -ENOSYS;
8332                         }
8333                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8334                         rte_free(mirr_rule);
8335                         pf->nb_mirror_rule--;
8336                         return 0;
8337                 }
8338         } else if (!on) {
8339                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8340                 return -ENOENT;
8341         }
8342
8343         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8344                                 sizeof(struct i40e_mirror_rule) , 0);
8345         if (!mirr_rule) {
8346                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8347                 return I40E_ERR_NO_MEMORY;
8348         }
8349         switch (mirror_conf->rule_type) {
8350         case ETH_MIRROR_VLAN:
8351                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8352                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8353                                 mirr_rule->entries[j] =
8354                                         mirror_conf->vlan.vlan_id[i];
8355                                 j++;
8356                         }
8357                 }
8358                 if (j == 0) {
8359                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8360                         rte_free(mirr_rule);
8361                         return -EINVAL;
8362                 }
8363                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8364                 break;
8365         case ETH_MIRROR_VIRTUAL_POOL_UP:
8366         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8367                 /* check if the specified pool bit is out of range */
8368                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8369                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8370                         rte_free(mirr_rule);
8371                         return -EINVAL;
8372                 }
8373                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8374                         if (mirror_conf->pool_mask & (1ULL << i)) {
8375                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8376                                 j++;
8377                         }
8378                 }
8379                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8380                         /* add pf vsi to entries */
8381                         mirr_rule->entries[j] = pf->main_vsi_seid;
8382                         j++;
8383                 }
8384                 if (j == 0) {
8385                         PMD_DRV_LOG(ERR, "pool is not specified.");
8386                         rte_free(mirr_rule);
8387                         return -EINVAL;
8388                 }
8389                 /* egress and ingress in aq commands means from switch but not port */
8390                 mirr_rule->rule_type =
8391                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8392                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8393                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8394                 break;
8395         case ETH_MIRROR_UPLINK_PORT:
8396                 /* egress and ingress in aq commands means from switch but not port*/
8397                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8398                 break;
8399         case ETH_MIRROR_DOWNLINK_PORT:
8400                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8401                 break;
8402         default:
8403                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8404                         mirror_conf->rule_type);
8405                 rte_free(mirr_rule);
8406                 return -EINVAL;
8407         }
8408
8409         /* If the dst_pool is equal to vf_num, consider it as PF */
8410         if (mirror_conf->dst_pool == pf->vf_num)
8411                 dst_seid = pf->main_vsi_seid;
8412         else
8413                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8414
8415         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8416                                       mirr_rule->rule_type, mirr_rule->entries,
8417                                       j, &rule_id);
8418         if (ret < 0) {
8419                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8420                                    " ret = %d, aq_err = %d.",
8421                                    ret, hw->aq.asq_last_status);
8422                 rte_free(mirr_rule);
8423                 return -ENOSYS;
8424         }
8425
8426         mirr_rule->index = sw_id;
8427         mirr_rule->num_entries = j;
8428         mirr_rule->id = rule_id;
8429         mirr_rule->dst_vsi_seid = dst_seid;
8430
8431         if (parent)
8432                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8433         else
8434                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8435
8436         pf->nb_mirror_rule++;
8437         return 0;
8438 }
8439
8440 /**
8441  * i40e_mirror_rule_reset
8442  * @dev: pointer to the device
8443  * @sw_id: mirror rule's sw_id
8444  *
8445  * reset a mirror rule.
8446  *
8447  **/
8448 static int
8449 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8450 {
8451         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8452         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8453         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8454         uint16_t seid;
8455         int ret;
8456
8457         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8458
8459         seid = pf->main_vsi->veb->seid;
8460
8461         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8462                 if (sw_id == it->index) {
8463                         mirr_rule = it;
8464                         break;
8465                 }
8466         }
8467         if (mirr_rule) {
8468                 ret = i40e_aq_del_mirror_rule(hw, seid,
8469                                 mirr_rule->rule_type,
8470                                 mirr_rule->entries,
8471                                 mirr_rule->num_entries, mirr_rule->id);
8472                 if (ret < 0) {
8473                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8474                                            " status = %d, aq_err = %d.",
8475                                            ret, hw->aq.asq_last_status);
8476                         return -ENOSYS;
8477                 }
8478                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8479                 rte_free(mirr_rule);
8480                 pf->nb_mirror_rule--;
8481         } else {
8482                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8483                 return -ENOENT;
8484         }
8485         return 0;
8486 }
8487
8488 static uint64_t
8489 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8490 {
8491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8492         uint64_t systim_cycles;
8493
8494         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8495         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8496                         << 32;
8497
8498         return systim_cycles;
8499 }
8500
8501 static uint64_t
8502 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8503 {
8504         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8505         uint64_t rx_tstamp;
8506
8507         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8508         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8509                         << 32;
8510
8511         return rx_tstamp;
8512 }
8513
8514 static uint64_t
8515 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8516 {
8517         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8518         uint64_t tx_tstamp;
8519
8520         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8521         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8522                         << 32;
8523
8524         return tx_tstamp;
8525 }
8526
8527 static void
8528 i40e_start_timecounters(struct rte_eth_dev *dev)
8529 {
8530         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8531         struct i40e_adapter *adapter =
8532                         (struct i40e_adapter *)dev->data->dev_private;
8533         struct rte_eth_link link;
8534         uint32_t tsync_inc_l;
8535         uint32_t tsync_inc_h;
8536
8537         /* Get current link speed. */
8538         memset(&link, 0, sizeof(link));
8539         i40e_dev_link_update(dev, 1);
8540         rte_i40e_dev_atomic_read_link_status(dev, &link);
8541
8542         switch (link.link_speed) {
8543         case ETH_SPEED_NUM_40G:
8544                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8545                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8546                 break;
8547         case ETH_SPEED_NUM_10G:
8548                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8549                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8550                 break;
8551         case ETH_SPEED_NUM_1G:
8552                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8553                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8554                 break;
8555         default:
8556                 tsync_inc_l = 0x0;
8557                 tsync_inc_h = 0x0;
8558         }
8559
8560         /* Set the timesync increment value. */
8561         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8562         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8563
8564         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8565         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8566         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8567
8568         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8569         adapter->systime_tc.cc_shift = 0;
8570         adapter->systime_tc.nsec_mask = 0;
8571
8572         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8573         adapter->rx_tstamp_tc.cc_shift = 0;
8574         adapter->rx_tstamp_tc.nsec_mask = 0;
8575
8576         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8577         adapter->tx_tstamp_tc.cc_shift = 0;
8578         adapter->tx_tstamp_tc.nsec_mask = 0;
8579 }
8580
8581 static int
8582 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8583 {
8584         struct i40e_adapter *adapter =
8585                         (struct i40e_adapter *)dev->data->dev_private;
8586
8587         adapter->systime_tc.nsec += delta;
8588         adapter->rx_tstamp_tc.nsec += delta;
8589         adapter->tx_tstamp_tc.nsec += delta;
8590
8591         return 0;
8592 }
8593
8594 static int
8595 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8596 {
8597         uint64_t ns;
8598         struct i40e_adapter *adapter =
8599                         (struct i40e_adapter *)dev->data->dev_private;
8600
8601         ns = rte_timespec_to_ns(ts);
8602
8603         /* Set the timecounters to a new value. */
8604         adapter->systime_tc.nsec = ns;
8605         adapter->rx_tstamp_tc.nsec = ns;
8606         adapter->tx_tstamp_tc.nsec = ns;
8607
8608         return 0;
8609 }
8610
8611 static int
8612 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8613 {
8614         uint64_t ns, systime_cycles;
8615         struct i40e_adapter *adapter =
8616                         (struct i40e_adapter *)dev->data->dev_private;
8617
8618         systime_cycles = i40e_read_systime_cyclecounter(dev);
8619         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8620         *ts = rte_ns_to_timespec(ns);
8621
8622         return 0;
8623 }
8624
8625 static int
8626 i40e_timesync_enable(struct rte_eth_dev *dev)
8627 {
8628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8629         uint32_t tsync_ctl_l;
8630         uint32_t tsync_ctl_h;
8631
8632         /* Stop the timesync system time. */
8633         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8634         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8635         /* Reset the timesync system time value. */
8636         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8637         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8638
8639         i40e_start_timecounters(dev);
8640
8641         /* Clear timesync registers. */
8642         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8643         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8644         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8645         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8646         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8647         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8648
8649         /* Enable timestamping of PTP packets. */
8650         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8651         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8652
8653         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8654         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8655         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8656
8657         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8658         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8659
8660         return 0;
8661 }
8662
8663 static int
8664 i40e_timesync_disable(struct rte_eth_dev *dev)
8665 {
8666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8667         uint32_t tsync_ctl_l;
8668         uint32_t tsync_ctl_h;
8669
8670         /* Disable timestamping of transmitted PTP packets. */
8671         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8672         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8673
8674         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8675         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8676
8677         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8678         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8679
8680         /* Reset the timesync increment value. */
8681         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8682         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8683
8684         return 0;
8685 }
8686
8687 static int
8688 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8689                                 struct timespec *timestamp, uint32_t flags)
8690 {
8691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8692         struct i40e_adapter *adapter =
8693                 (struct i40e_adapter *)dev->data->dev_private;
8694
8695         uint32_t sync_status;
8696         uint32_t index = flags & 0x03;
8697         uint64_t rx_tstamp_cycles;
8698         uint64_t ns;
8699
8700         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8701         if ((sync_status & (1 << index)) == 0)
8702                 return -EINVAL;
8703
8704         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8705         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8706         *timestamp = rte_ns_to_timespec(ns);
8707
8708         return 0;
8709 }
8710
8711 static int
8712 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8713                                 struct timespec *timestamp)
8714 {
8715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8716         struct i40e_adapter *adapter =
8717                 (struct i40e_adapter *)dev->data->dev_private;
8718
8719         uint32_t sync_status;
8720         uint64_t tx_tstamp_cycles;
8721         uint64_t ns;
8722
8723         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8724         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8725                 return -EINVAL;
8726
8727         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8728         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8729         *timestamp = rte_ns_to_timespec(ns);
8730
8731         return 0;
8732 }
8733
8734 /*
8735  * i40e_parse_dcb_configure - parse dcb configure from user
8736  * @dev: the device being configured
8737  * @dcb_cfg: pointer of the result of parse
8738  * @*tc_map: bit map of enabled traffic classes
8739  *
8740  * Returns 0 on success, negative value on failure
8741  */
8742 static int
8743 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8744                          struct i40e_dcbx_config *dcb_cfg,
8745                          uint8_t *tc_map)
8746 {
8747         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8748         uint8_t i, tc_bw, bw_lf;
8749
8750         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8751
8752         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8753         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8754                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8755                 return -EINVAL;
8756         }
8757
8758         /* assume each tc has the same bw */
8759         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8760         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8761                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8762         /* to ensure the sum of tcbw is equal to 100 */
8763         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8764         for (i = 0; i < bw_lf; i++)
8765                 dcb_cfg->etscfg.tcbwtable[i]++;
8766
8767         /* assume each tc has the same Transmission Selection Algorithm */
8768         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8769                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8770
8771         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8772                 dcb_cfg->etscfg.prioritytable[i] =
8773                                 dcb_rx_conf->dcb_tc[i];
8774
8775         /* FW needs one App to configure HW */
8776         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8777         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8778         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8779         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8780
8781         if (dcb_rx_conf->nb_tcs == 0)
8782                 *tc_map = 1; /* tc0 only */
8783         else
8784                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8785
8786         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8787                 dcb_cfg->pfc.willing = 0;
8788                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8789                 dcb_cfg->pfc.pfcenable = *tc_map;
8790         }
8791         return 0;
8792 }
8793
8794
8795 static enum i40e_status_code
8796 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8797                               struct i40e_aqc_vsi_properties_data *info,
8798                               uint8_t enabled_tcmap)
8799 {
8800         enum i40e_status_code ret;
8801         int i, total_tc = 0;
8802         uint16_t qpnum_per_tc, bsf, qp_idx;
8803         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8804         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8805         uint16_t used_queues;
8806
8807         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8808         if (ret != I40E_SUCCESS)
8809                 return ret;
8810
8811         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8812                 if (enabled_tcmap & (1 << i))
8813                         total_tc++;
8814         }
8815         if (total_tc == 0)
8816                 total_tc = 1;
8817         vsi->enabled_tc = enabled_tcmap;
8818
8819         /* different VSI has different queues assigned */
8820         if (vsi->type == I40E_VSI_MAIN)
8821                 used_queues = dev_data->nb_rx_queues -
8822                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8823         else if (vsi->type == I40E_VSI_VMDQ2)
8824                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8825         else {
8826                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8827                 return I40E_ERR_NO_AVAILABLE_VSI;
8828         }
8829
8830         qpnum_per_tc = used_queues / total_tc;
8831         /* Number of queues per enabled TC */
8832         if (qpnum_per_tc == 0) {
8833                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8834                 return I40E_ERR_INVALID_QP_ID;
8835         }
8836         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8837                                 I40E_MAX_Q_PER_TC);
8838         bsf = rte_bsf32(qpnum_per_tc);
8839
8840         /**
8841          * Configure TC and queue mapping parameters, for enabled TC,
8842          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8843          * default queue will serve it.
8844          */
8845         qp_idx = 0;
8846         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8847                 if (vsi->enabled_tc & (1 << i)) {
8848                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8849                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8850                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8851                         qp_idx += qpnum_per_tc;
8852                 } else
8853                         info->tc_mapping[i] = 0;
8854         }
8855
8856         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8857         if (vsi->type == I40E_VSI_SRIOV) {
8858                 info->mapping_flags |=
8859                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8860                 for (i = 0; i < vsi->nb_qps; i++)
8861                         info->queue_mapping[i] =
8862                                 rte_cpu_to_le_16(vsi->base_queue + i);
8863         } else {
8864                 info->mapping_flags |=
8865                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8866                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8867         }
8868         info->valid_sections |=
8869                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8870
8871         return I40E_SUCCESS;
8872 }
8873
8874 /*
8875  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8876  * @veb: VEB to be configured
8877  * @tc_map: enabled TC bitmap
8878  *
8879  * Returns 0 on success, negative value on failure
8880  */
8881 static enum i40e_status_code
8882 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8883 {
8884         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8885         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8886         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8887         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8888         enum i40e_status_code ret = I40E_SUCCESS;
8889         int i;
8890         uint32_t bw_max;
8891
8892         /* Check if enabled_tc is same as existing or new TCs */
8893         if (veb->enabled_tc == tc_map)
8894                 return ret;
8895
8896         /* configure tc bandwidth */
8897         memset(&veb_bw, 0, sizeof(veb_bw));
8898         veb_bw.tc_valid_bits = tc_map;
8899         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8900         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8901                 if (tc_map & BIT_ULL(i))
8902                         veb_bw.tc_bw_share_credits[i] = 1;
8903         }
8904         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8905                                                    &veb_bw, NULL);
8906         if (ret) {
8907                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8908                                   " per TC failed = %d",
8909                                   hw->aq.asq_last_status);
8910                 return ret;
8911         }
8912
8913         memset(&ets_query, 0, sizeof(ets_query));
8914         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8915                                                    &ets_query, NULL);
8916         if (ret != I40E_SUCCESS) {
8917                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8918                                  " configuration %u", hw->aq.asq_last_status);
8919                 return ret;
8920         }
8921         memset(&bw_query, 0, sizeof(bw_query));
8922         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8923                                                   &bw_query, NULL);
8924         if (ret != I40E_SUCCESS) {
8925                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8926                                  " configuration %u", hw->aq.asq_last_status);
8927                 return ret;
8928         }
8929
8930         /* store and print out BW info */
8931         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8932         veb->bw_info.bw_max = ets_query.tc_bw_max;
8933         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8934         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8935         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8936                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8937                      I40E_16_BIT_WIDTH);
8938         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8939                 veb->bw_info.bw_ets_share_credits[i] =
8940                                 bw_query.tc_bw_share_credits[i];
8941                 veb->bw_info.bw_ets_credits[i] =
8942                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8943                 /* 4 bits per TC, 4th bit is reserved */
8944                 veb->bw_info.bw_ets_max[i] =
8945                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8946                                   RTE_LEN2MASK(3, uint8_t));
8947                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8948                             veb->bw_info.bw_ets_share_credits[i]);
8949                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8950                             veb->bw_info.bw_ets_credits[i]);
8951                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8952                             veb->bw_info.bw_ets_max[i]);
8953         }
8954
8955         veb->enabled_tc = tc_map;
8956
8957         return ret;
8958 }
8959
8960
8961 /*
8962  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8963  * @vsi: VSI to be configured
8964  * @tc_map: enabled TC bitmap
8965  *
8966  * Returns 0 on success, negative value on failure
8967  */
8968 static enum i40e_status_code
8969 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8970 {
8971         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8972         struct i40e_vsi_context ctxt;
8973         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8974         enum i40e_status_code ret = I40E_SUCCESS;
8975         int i;
8976
8977         /* Check if enabled_tc is same as existing or new TCs */
8978         if (vsi->enabled_tc == tc_map)
8979                 return ret;
8980
8981         /* configure tc bandwidth */
8982         memset(&bw_data, 0, sizeof(bw_data));
8983         bw_data.tc_valid_bits = tc_map;
8984         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8985         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8986                 if (tc_map & BIT_ULL(i))
8987                         bw_data.tc_bw_credits[i] = 1;
8988         }
8989         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8990         if (ret) {
8991                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8992                         " per TC failed = %d",
8993                         hw->aq.asq_last_status);
8994                 goto out;
8995         }
8996         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8997                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8998
8999         /* Update Queue Pairs Mapping for currently enabled UPs */
9000         ctxt.seid = vsi->seid;
9001         ctxt.pf_num = hw->pf_id;
9002         ctxt.vf_num = 0;
9003         ctxt.uplink_seid = vsi->uplink_seid;
9004         ctxt.info = vsi->info;
9005         i40e_get_cap(hw);
9006         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9007         if (ret)
9008                 goto out;
9009
9010         /* Update the VSI after updating the VSI queue-mapping information */
9011         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9012         if (ret) {
9013                 PMD_INIT_LOG(ERR, "Failed to configure "
9014                             "TC queue mapping = %d",
9015                             hw->aq.asq_last_status);
9016                 goto out;
9017         }
9018         /* update the local VSI info with updated queue map */
9019         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9020                                         sizeof(vsi->info.tc_mapping));
9021         (void)rte_memcpy(&vsi->info.queue_mapping,
9022                         &ctxt.info.queue_mapping,
9023                 sizeof(vsi->info.queue_mapping));
9024         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9025         vsi->info.valid_sections = 0;
9026
9027         /* query and update current VSI BW information */
9028         ret = i40e_vsi_get_bw_config(vsi);
9029         if (ret) {
9030                 PMD_INIT_LOG(ERR,
9031                          "Failed updating vsi bw info, err %s aq_err %s",
9032                          i40e_stat_str(hw, ret),
9033                          i40e_aq_str(hw, hw->aq.asq_last_status));
9034                 goto out;
9035         }
9036
9037         vsi->enabled_tc = tc_map;
9038
9039 out:
9040         return ret;
9041 }
9042
9043 /*
9044  * i40e_dcb_hw_configure - program the dcb setting to hw
9045  * @pf: pf the configuration is taken on
9046  * @new_cfg: new configuration
9047  * @tc_map: enabled TC bitmap
9048  *
9049  * Returns 0 on success, negative value on failure
9050  */
9051 static enum i40e_status_code
9052 i40e_dcb_hw_configure(struct i40e_pf *pf,
9053                       struct i40e_dcbx_config *new_cfg,
9054                       uint8_t tc_map)
9055 {
9056         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9057         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9058         struct i40e_vsi *main_vsi = pf->main_vsi;
9059         struct i40e_vsi_list *vsi_list;
9060         enum i40e_status_code ret;
9061         int i;
9062         uint32_t val;
9063
9064         /* Use the FW API if FW > v4.4*/
9065         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9066               (hw->aq.fw_maj_ver >= 5))) {
9067                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9068                                   " to configure DCB");
9069                 return I40E_ERR_FIRMWARE_API_VERSION;
9070         }
9071
9072         /* Check if need reconfiguration */
9073         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9074                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9075                 return I40E_SUCCESS;
9076         }
9077
9078         /* Copy the new config to the current config */
9079         *old_cfg = *new_cfg;
9080         old_cfg->etsrec = old_cfg->etscfg;
9081         ret = i40e_set_dcb_config(hw);
9082         if (ret) {
9083                 PMD_INIT_LOG(ERR,
9084                          "Set DCB Config failed, err %s aq_err %s\n",
9085                          i40e_stat_str(hw, ret),
9086                          i40e_aq_str(hw, hw->aq.asq_last_status));
9087                 return ret;
9088         }
9089         /* set receive Arbiter to RR mode and ETS scheme by default */
9090         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9091                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9092                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9093                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9094                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9095                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9096                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9097                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9098                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9099                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9100                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9101                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9102                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9103         }
9104         /* get local mib to check whether it is configured correctly */
9105         /* IEEE mode */
9106         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9107         /* Get Local DCB Config */
9108         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9109                                      &hw->local_dcbx_config);
9110
9111         /* if Veb is created, need to update TC of it at first */
9112         if (main_vsi->veb) {
9113                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9114                 if (ret)
9115                         PMD_INIT_LOG(WARNING,
9116                                  "Failed configuring TC for VEB seid=%d\n",
9117                                  main_vsi->veb->seid);
9118         }
9119         /* Update each VSI */
9120         i40e_vsi_config_tc(main_vsi, tc_map);
9121         if (main_vsi->veb) {
9122                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9123                         /* Beside main VSI and VMDQ VSIs, only enable default
9124                          * TC for other VSIs
9125                          */
9126                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9127                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9128                                                          tc_map);
9129                         else
9130                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9131                                                          I40E_DEFAULT_TCMAP);
9132                         if (ret)
9133                                 PMD_INIT_LOG(WARNING,
9134                                          "Failed configuring TC for VSI seid=%d\n",
9135                                          vsi_list->vsi->seid);
9136                         /* continue */
9137                 }
9138         }
9139         return I40E_SUCCESS;
9140 }
9141
9142 /*
9143  * i40e_dcb_init_configure - initial dcb config
9144  * @dev: device being configured
9145  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9146  *
9147  * Returns 0 on success, negative value on failure
9148  */
9149 static int
9150 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9151 {
9152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9154         int ret = 0;
9155
9156         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9157                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9158                 return -ENOTSUP;
9159         }
9160
9161         /* DCB initialization:
9162          * Update DCB configuration from the Firmware and configure
9163          * LLDP MIB change event.
9164          */
9165         if (sw_dcb == TRUE) {
9166                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9167                 if (ret != I40E_SUCCESS)
9168                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9169
9170                 ret = i40e_init_dcb(hw);
9171                 /* if sw_dcb, lldp agent is stopped, the return from
9172                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9173                  * adminq status.
9174                  */
9175                 if (ret != I40E_SUCCESS &&
9176                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9177                         memset(&hw->local_dcbx_config, 0,
9178                                 sizeof(struct i40e_dcbx_config));
9179                         /* set dcb default configuration */
9180                         hw->local_dcbx_config.etscfg.willing = 0;
9181                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9182                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9183                         hw->local_dcbx_config.etscfg.tsatable[0] =
9184                                                 I40E_IEEE_TSA_ETS;
9185                         hw->local_dcbx_config.etsrec =
9186                                 hw->local_dcbx_config.etscfg;
9187                         hw->local_dcbx_config.pfc.willing = 0;
9188                         hw->local_dcbx_config.pfc.pfccap =
9189                                                 I40E_MAX_TRAFFIC_CLASS;
9190                         /* FW needs one App to configure HW */
9191                         hw->local_dcbx_config.numapps = 1;
9192                         hw->local_dcbx_config.app[0].selector =
9193                                                 I40E_APP_SEL_ETHTYPE;
9194                         hw->local_dcbx_config.app[0].priority = 3;
9195                         hw->local_dcbx_config.app[0].protocolid =
9196                                                 I40E_APP_PROTOID_FCOE;
9197                         ret = i40e_set_dcb_config(hw);
9198                         if (ret) {
9199                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9200                                         " err = %d, aq_err = %d.", ret,
9201                                           hw->aq.asq_last_status);
9202                                 return -ENOSYS;
9203                         }
9204                 } else {
9205                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9206                                           " aq_err = %d.", ret,
9207                                           hw->aq.asq_last_status);
9208                         return -ENOTSUP;
9209                 }
9210         } else {
9211                 ret = i40e_aq_start_lldp(hw, NULL);
9212                 if (ret != I40E_SUCCESS)
9213                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9214
9215                 ret = i40e_init_dcb(hw);
9216                 if (!ret) {
9217                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9218                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9219                                                   " DCBX offload.");
9220                                 return -ENOTSUP;
9221                         }
9222                 } else {
9223                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9224                                           " aq_err = %d.", ret,
9225                                           hw->aq.asq_last_status);
9226                         return -ENOTSUP;
9227                 }
9228         }
9229         return 0;
9230 }
9231
9232 /*
9233  * i40e_dcb_setup - setup dcb related config
9234  * @dev: device being configured
9235  *
9236  * Returns 0 on success, negative value on failure
9237  */
9238 static int
9239 i40e_dcb_setup(struct rte_eth_dev *dev)
9240 {
9241         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9242         struct i40e_dcbx_config dcb_cfg;
9243         uint8_t tc_map = 0;
9244         int ret = 0;
9245
9246         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9247                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9248                 return -ENOTSUP;
9249         }
9250
9251         if (pf->vf_num != 0)
9252                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9253
9254         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9255         if (ret) {
9256                 PMD_INIT_LOG(ERR, "invalid dcb config");
9257                 return -EINVAL;
9258         }
9259         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9260         if (ret) {
9261                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9262                 return -ENOSYS;
9263         }
9264
9265         return 0;
9266 }
9267
9268 static int
9269 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9270                       struct rte_eth_dcb_info *dcb_info)
9271 {
9272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9274         struct i40e_vsi *vsi = pf->main_vsi;
9275         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9276         uint16_t bsf, tc_mapping;
9277         int i, j = 0;
9278
9279         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9280                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9281         else
9282                 dcb_info->nb_tcs = 1;
9283         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9284                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9285         for (i = 0; i < dcb_info->nb_tcs; i++)
9286                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9287
9288         /* get queue mapping if vmdq is disabled */
9289         if (!pf->nb_cfg_vmdq_vsi) {
9290                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9291                         if (!(vsi->enabled_tc & (1 << i)))
9292                                 continue;
9293                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9294                         dcb_info->tc_queue.tc_rxq[j][i].base =
9295                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9296                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9297                         dcb_info->tc_queue.tc_txq[j][i].base =
9298                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9299                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9300                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9301                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9302                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9303                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9304                 }
9305                 return 0;
9306         }
9307
9308         /* get queue mapping if vmdq is enabled */
9309         do {
9310                 vsi = pf->vmdq[j].vsi;
9311                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9312                         if (!(vsi->enabled_tc & (1 << i)))
9313                                 continue;
9314                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9315                         dcb_info->tc_queue.tc_rxq[j][i].base =
9316                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9317                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9318                         dcb_info->tc_queue.tc_txq[j][i].base =
9319                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9320                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9321                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9322                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9323                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9324                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9325                 }
9326                 j++;
9327         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9328         return 0;
9329 }
9330
9331 static int
9332 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9333 {
9334         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9335         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9336         uint16_t interval =
9337                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9338         uint16_t msix_intr;
9339
9340         msix_intr = intr_handle->intr_vec[queue_id];
9341         if (msix_intr == I40E_MISC_VEC_ID)
9342                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9343                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9344                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9345                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9346                                (interval <<
9347                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9348         else
9349                 I40E_WRITE_REG(hw,
9350                                I40E_PFINT_DYN_CTLN(msix_intr -
9351                                                    I40E_RX_VEC_START),
9352                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9353                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9354                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9355                                (interval <<
9356                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9357
9358         I40E_WRITE_FLUSH(hw);
9359         rte_intr_enable(&dev->pci_dev->intr_handle);
9360
9361         return 0;
9362 }
9363
9364 static int
9365 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9366 {
9367         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9369         uint16_t msix_intr;
9370
9371         msix_intr = intr_handle->intr_vec[queue_id];
9372         if (msix_intr == I40E_MISC_VEC_ID)
9373                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9374         else
9375                 I40E_WRITE_REG(hw,
9376                                I40E_PFINT_DYN_CTLN(msix_intr -
9377                                                    I40E_RX_VEC_START),
9378                                0);
9379         I40E_WRITE_FLUSH(hw);
9380
9381         return 0;
9382 }
9383
9384 static int i40e_get_regs(struct rte_eth_dev *dev,
9385                          struct rte_dev_reg_info *regs)
9386 {
9387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9388         uint32_t *ptr_data = regs->data;
9389         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9390         const struct i40e_reg_info *reg_info;
9391
9392         if (ptr_data == NULL) {
9393                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9394                 regs->width = sizeof(uint32_t);
9395                 return 0;
9396         }
9397
9398         /* The first few registers have to be read using AQ operations */
9399         reg_idx = 0;
9400         while (i40e_regs_adminq[reg_idx].name) {
9401                 reg_info = &i40e_regs_adminq[reg_idx++];
9402                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9403                         for (arr_idx2 = 0;
9404                                         arr_idx2 <= reg_info->count2;
9405                                         arr_idx2++) {
9406                                 reg_offset = arr_idx * reg_info->stride1 +
9407                                         arr_idx2 * reg_info->stride2;
9408                                 reg_offset += reg_info->base_addr;
9409                                 ptr_data[reg_offset >> 2] =
9410                                         i40e_read_rx_ctl(hw, reg_offset);
9411                         }
9412         }
9413
9414         /* The remaining registers can be read using primitives */
9415         reg_idx = 0;
9416         while (i40e_regs_others[reg_idx].name) {
9417                 reg_info = &i40e_regs_others[reg_idx++];
9418                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9419                         for (arr_idx2 = 0;
9420                                         arr_idx2 <= reg_info->count2;
9421                                         arr_idx2++) {
9422                                 reg_offset = arr_idx * reg_info->stride1 +
9423                                         arr_idx2 * reg_info->stride2;
9424                                 reg_offset += reg_info->base_addr;
9425                                 ptr_data[reg_offset >> 2] =
9426                                         I40E_READ_REG(hw, reg_offset);
9427                         }
9428         }
9429
9430         return 0;
9431 }
9432
9433 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9434 {
9435         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9436
9437         /* Convert word count to byte count */
9438         return hw->nvm.sr_size << 1;
9439 }
9440
9441 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9442                            struct rte_dev_eeprom_info *eeprom)
9443 {
9444         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9445         uint16_t *data = eeprom->data;
9446         uint16_t offset, length, cnt_words;
9447         int ret_code;
9448
9449         offset = eeprom->offset >> 1;
9450         length = eeprom->length >> 1;
9451         cnt_words = length;
9452
9453         if (offset > hw->nvm.sr_size ||
9454                 offset + length > hw->nvm.sr_size) {
9455                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9456                 return -EINVAL;
9457         }
9458
9459         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9460
9461         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9462         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9463                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9464                 return -EIO;
9465         }
9466
9467         return 0;
9468 }
9469
9470 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9471                                       struct ether_addr *mac_addr)
9472 {
9473         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9474
9475         if (!is_valid_assigned_ether_addr(mac_addr)) {
9476                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9477                 return;
9478         }
9479
9480         /* Flags: 0x3 updates port address */
9481         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9482 }
9483
9484 static int
9485 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9486 {
9487         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9488         struct rte_eth_dev_data *dev_data = pf->dev_data;
9489         uint32_t frame_size = mtu + ETHER_HDR_LEN
9490                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9491         int ret = 0;
9492
9493         /* check if mtu is within the allowed range */
9494         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9495                 return -EINVAL;
9496
9497         /* mtu setting is forbidden if port is start */
9498         if (dev_data->dev_started) {
9499                 PMD_DRV_LOG(ERR,
9500                             "port %d must be stopped before configuration\n",
9501                             dev_data->port_id);
9502                 return -EBUSY;
9503         }
9504
9505         if (frame_size > ETHER_MAX_LEN)
9506                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9507         else
9508                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9509
9510         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9511
9512         return ret;
9513 }