drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_reg_length(struct rte_eth_dev *dev);
 444
 445 static int i40e_get_regs(struct rte_eth_dev *dev,
 446                          struct rte_dev_reg_info *regs);
 447
 448 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 449
 450 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 451                            struct rte_dev_eeprom_info *eeprom);
 452
 453 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 454                                       struct ether_addr *mac_addr);
 455
 456 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 457
 458 static const struct rte_pci_id pci_id_i40e_map[] = {
 459 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 460 #include "rte_pci_dev_ids.h"
 461 { .vendor_id = 0, /* sentinel */ },
 462 };
 463
 464 static const struct eth_dev_ops i40e_eth_dev_ops = {
 465         .dev_configure                = i40e_dev_configure,
 466         .dev_start                    = i40e_dev_start,
 467         .dev_stop                     = i40e_dev_stop,
 468         .dev_close                    = i40e_dev_close,
 469         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 470         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 471         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 472         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 473         .dev_set_link_up              = i40e_dev_set_link_up,
 474         .dev_set_link_down            = i40e_dev_set_link_down,
 475         .link_update                  = i40e_dev_link_update,
 476         .stats_get                    = i40e_dev_stats_get,
 477         .xstats_get                   = i40e_dev_xstats_get,
 478         .xstats_get_names             = i40e_dev_xstats_get_names,
 479         .stats_reset                  = i40e_dev_stats_reset,
 480         .xstats_reset                 = i40e_dev_stats_reset,
 481         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 482         .dev_infos_get                = i40e_dev_info_get,
 483         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 484         .vlan_filter_set              = i40e_vlan_filter_set,
 485         .vlan_tpid_set                = i40e_vlan_tpid_set,
 486         .vlan_offload_set             = i40e_vlan_offload_set,
 487         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 488         .vlan_pvid_set                = i40e_vlan_pvid_set,
 489         .rx_queue_start               = i40e_dev_rx_queue_start,
 490         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 491         .tx_queue_start               = i40e_dev_tx_queue_start,
 492         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 493         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 494         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 495         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 496         .rx_queue_release             = i40e_dev_rx_queue_release,
 497         .rx_queue_count               = i40e_dev_rx_queue_count,
 498         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 499         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 500         .tx_queue_release             = i40e_dev_tx_queue_release,
 501         .dev_led_on                   = i40e_dev_led_on,
 502         .dev_led_off                  = i40e_dev_led_off,
 503         .flow_ctrl_get                = i40e_flow_ctrl_get,
 504         .flow_ctrl_set                = i40e_flow_ctrl_set,
 505         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 506         .mac_addr_add                 = i40e_macaddr_add,
 507         .mac_addr_remove              = i40e_macaddr_remove,
 508         .reta_update                  = i40e_dev_rss_reta_update,
 509         .reta_query                   = i40e_dev_rss_reta_query,
 510         .rss_hash_update              = i40e_dev_rss_hash_update,
 511         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 512         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 513         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 514         .filter_ctrl                  = i40e_dev_filter_ctrl,
 515         .rxq_info_get                 = i40e_rxq_info_get,
 516         .txq_info_get                 = i40e_txq_info_get,
 517         .mirror_rule_set              = i40e_mirror_rule_set,
 518         .mirror_rule_reset            = i40e_mirror_rule_reset,
 519         .timesync_enable              = i40e_timesync_enable,
 520         .timesync_disable             = i40e_timesync_disable,
 521         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 522         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 523         .get_dcb_info                 = i40e_dev_get_dcb_info,
 524         .timesync_adjust_time         = i40e_timesync_adjust_time,
 525         .timesync_read_time           = i40e_timesync_read_time,
 526         .timesync_write_time          = i40e_timesync_write_time,
 527         .get_reg_length               = i40e_get_reg_length,
 528         .get_reg                      = i40e_get_regs,
 529         .get_eeprom_length            = i40e_get_eeprom_length,
 530         .get_eeprom                   = i40e_get_eeprom,
 531         .mac_addr_set                 = i40e_set_default_mac_addr,
 532         .mtu_set                      = i40e_dev_mtu_set,
 533 };
 534
 535 /* store statistics names and its offset in stats structure */
 536 struct rte_i40e_xstats_name_off {
 537         char name[RTE_ETH_XSTATS_NAME_SIZE];
 538         unsigned offset;
 539 };
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 542         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 543         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 544         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 545         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 546         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 547                 rx_unknown_protocol)},
 548         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 549         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 550         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 551         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 552 };
 553
 554 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 555                 sizeof(rte_i40e_stats_strings[0]))
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 558         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 559                 tx_dropped_link_down)},
 560         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 561         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 562                 illegal_bytes)},
 563         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 564         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 565                 mac_local_faults)},
 566         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 567                 mac_remote_faults)},
 568         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 569                 rx_length_errors)},
 570         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 571         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 572         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 573         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 574         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 575         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_127)},
 577         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_255)},
 579         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 580                 rx_size_511)},
 581         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 582                 rx_size_1023)},
 583         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 584                 rx_size_1522)},
 585         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 586                 rx_size_big)},
 587         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 588                 rx_undersize)},
 589         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 590                 rx_oversize)},
 591         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 592                 mac_short_packet_dropped)},
 593         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 594                 rx_fragments)},
 595         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 596         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 597         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_127)},
 599         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_255)},
 601         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 602                 tx_size_511)},
 603         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 604                 tx_size_1023)},
 605         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 606                 tx_size_1522)},
 607         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 608                 tx_size_big)},
 609         {"rx_flow_director_atr_match_packets",
 610                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 611         {"rx_flow_director_sb_match_packets",
 612                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 613         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 614                 tx_lpi_status)},
 615         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 616                 rx_lpi_status)},
 617         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 618                 tx_lpi_count)},
 619         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 620                 rx_lpi_count)},
 621 };
 622
 623 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 624                 sizeof(rte_i40e_hw_port_strings[0]))
 625
 626 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 627         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_rx)},
 629         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xoff_rx)},
 631 };
 632
 633 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 634                 sizeof(rte_i40e_rxq_prio_strings[0]))
 635
 636 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 637         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 638                 priority_xon_tx)},
 639         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 640                 priority_xoff_tx)},
 641         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 642                 priority_xon_2_xoff)},
 643 };
 644
 645 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 646                 sizeof(rte_i40e_txq_prio_strings[0]))
 647
 648 static struct eth_driver rte_i40e_pmd = {
 649         .pci_drv = {
 650                 .name = "rte_i40e_pmd",
 651                 .id_table = pci_id_i40e_map,
 652                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 653                         RTE_PCI_DRV_DETACHABLE,
 654         },
 655         .eth_dev_init = eth_i40e_dev_init,
 656         .eth_dev_uninit = eth_i40e_dev_uninit,
 657         .dev_private_size = sizeof(struct i40e_adapter),
 658 };
 659
 660 static inline int
 661 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 662                                      struct rte_eth_link *link)
 663 {
 664         struct rte_eth_link *dst = link;
 665         struct rte_eth_link *src = &(dev->data->dev_link);
 666
 667         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 668                                         *(uint64_t *)src) == 0)
 669                 return -1;
 670
 671         return 0;
 672 }
 673
 674 static inline int
 675 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 676                                       struct rte_eth_link *link)
 677 {
 678         struct rte_eth_link *dst = &(dev->data->dev_link);
 679         struct rte_eth_link *src = link;
 680
 681         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 682                                         *(uint64_t *)src) == 0)
 683                 return -1;
 684
 685         return 0;
 686 }
 687
 688 /*
 689  * Driver initialization routine.
 690  * Invoked once at EAL init time.
 691  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 692  */
 693 static int
 694 rte_i40e_pmd_init(const char *name __rte_unused,
 695                   const char *params __rte_unused)
 696 {
 697         PMD_INIT_FUNC_TRACE();
 698         rte_eth_driver_register(&rte_i40e_pmd);
 699
 700         return 0;
 701 }
 702
 703 static struct rte_driver rte_i40e_driver = {
 704         .type = PMD_PDEV,
 705         .init = rte_i40e_pmd_init,
 706 };
 707
 708 PMD_REGISTER_DRIVER(rte_i40e_driver);
 709
 710 /*
 711  * Initialize registers for flexible payload, which should be set by NVM.
 712  * This should be removed from code once it is fixed in NVM.
 713  */
 714 #ifndef I40E_GLQF_ORT
 715 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 716 #endif
 717 #ifndef I40E_GLQF_PIT
 718 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 719 #endif
 720
 721 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 722 {
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 733
 734         /* GLQF_PIT Registers */
 735         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 736         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 737 }
 738
 739 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 740
 741 /*
 742  * Add a ethertype filter to drop all flow control frames transmitted
 743  * from VSIs.
 744 */
 745 static void
 746 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 747 {
 748         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 749         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 750                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 751                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 752         int ret;
 753
 754         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 755                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 756                                 pf->main_vsi_seid, 0,
 757                                 TRUE, NULL, NULL);
 758         if (ret)
 759                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 760                                   " frames from VSIs.");
 761 }
 762
 763 static int
 764 floating_veb_list_handler(__rte_unused const char *key,
 765                           const char *floating_veb_value,
 766                           void *opaque)
 767 {
 768         int idx = 0;
 769         unsigned int count = 0;
 770         char *end = NULL;
 771         int min, max;
 772         bool *vf_floating_veb = opaque;
 773
 774         while (isblank(*floating_veb_value))
 775                 floating_veb_value++;
 776
 777         /* Reset floating VEB configuration for VFs */
 778         for (idx = 0; idx < I40E_MAX_VF; idx++)
 779                 vf_floating_veb[idx] = false;
 780
 781         min = I40E_MAX_VF;
 782         do {
 783                 while (isblank(*floating_veb_value))
 784                         floating_veb_value++;
 785                 if (*floating_veb_value == '\0')
 786                         return -1;
 787                 errno = 0;
 788                 idx = strtoul(floating_veb_value, &end, 10);
 789                 if (errno || end == NULL)
 790                         return -1;
 791                 while (isblank(*end))
 792                         end++;
 793                 if (*end == '-') {
 794                         min = idx;
 795                 } else if ((*end == ';') || (*end == '\0')) {
 796                         max = idx;
 797                         if (min == I40E_MAX_VF)
 798                                 min = idx;
 799                         if (max >= I40E_MAX_VF)
 800                                 max = I40E_MAX_VF - 1;
 801                         for (idx = min; idx <= max; idx++) {
 802                                 vf_floating_veb[idx] = true;
 803                                 count++;
 804                         }
 805                         min = I40E_MAX_VF;
 806                 } else {
 807                         return -1;
 808                 }
 809                 floating_veb_value = end + 1;
 810         } while (*end != '\0');
 811
 812         if (count == 0)
 813                 return -1;
 814
 815         return 0;
 816 }
 817
 818 static void
 819 config_vf_floating_veb(struct rte_devargs *devargs,
 820                        uint16_t floating_veb,
 821                        bool *vf_floating_veb)
 822 {
 823         struct rte_kvargs *kvlist;
 824         int i;
 825         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 826
 827         if (!floating_veb)
 828                 return;
 829         /* All the VFs attach to the floating VEB by default
 830          * when the floating VEB is enabled.
 831          */
 832         for (i = 0; i < I40E_MAX_VF; i++)
 833                 vf_floating_veb[i] = true;
 834
 835         if (devargs == NULL)
 836                 return;
 837
 838         kvlist = rte_kvargs_parse(devargs->args, NULL);
 839         if (kvlist == NULL)
 840                 return;
 841
 842         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 843                 rte_kvargs_free(kvlist);
 844                 return;
 845         }
 846         /* When the floating_veb_list parameter exists, all the VFs
 847          * will attach to the legacy VEB firstly, then configure VFs
 848          * to the floating VEB according to the floating_veb_list.
 849          */
 850         if (rte_kvargs_process(kvlist, floating_veb_list,
 851                                floating_veb_list_handler,
 852                                vf_floating_veb) < 0) {
 853                 rte_kvargs_free(kvlist);
 854                 return;
 855         }
 856         rte_kvargs_free(kvlist);
 857 }
 858
 859 static int
 860 i40e_check_floating_handler(__rte_unused const char *key,
 861                             const char *value,
 862                             __rte_unused void *opaque)
 863 {
 864         if (strcmp(value, "1"))
 865                 return -1;
 866
 867         return 0;
 868 }
 869
 870 static int
 871 is_floating_veb_supported(struct rte_devargs *devargs)
 872 {
 873         struct rte_kvargs *kvlist;
 874         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 875
 876         if (devargs == NULL)
 877                 return 0;
 878
 879         kvlist = rte_kvargs_parse(devargs->args, NULL);
 880         if (kvlist == NULL)
 881                 return 0;
 882
 883         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 884                 rte_kvargs_free(kvlist);
 885                 return 0;
 886         }
 887         /* Floating VEB is enabled when there's key-value:
 888          * enable_floating_veb=1
 889          */
 890         if (rte_kvargs_process(kvlist, floating_veb_key,
 891                                i40e_check_floating_handler, NULL) < 0) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         rte_kvargs_free(kvlist);
 896
 897         return 1;
 898 }
 899
 900 static void
 901 config_floating_veb(struct rte_eth_dev *dev)
 902 {
 903         struct rte_pci_device *pci_dev = dev->pci_dev;
 904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 906
 907         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 908
 909         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 910                 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
 911                 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
 912                                        pf->floating_veb_list);
 913         } else {
 914                 pf->floating_veb = false;
 915         }
 916 }
 917
 918 static int
 919 eth_i40e_dev_init(struct rte_eth_dev *dev)
 920 {
 921         struct rte_pci_device *pci_dev;
 922         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 923         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 924         struct i40e_vsi *vsi;
 925         int ret;
 926         uint32_t len;
 927         uint8_t aq_fail = 0;
 928
 929         PMD_INIT_FUNC_TRACE();
 930
 931         dev->dev_ops = &i40e_eth_dev_ops;
 932         dev->rx_pkt_burst = i40e_recv_pkts;
 933         dev->tx_pkt_burst = i40e_xmit_pkts;
 934
 935         /* for secondary processes, we don't initialise any further as primary
 936          * has already done this work. Only check we don't need a different
 937          * RX function */
 938         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 939                 i40e_set_rx_function(dev);
 940                 i40e_set_tx_function(dev);
 941                 return 0;
 942         }
 943         pci_dev = dev->pci_dev;
 944
 945         rte_eth_copy_pci_info(dev, pci_dev);
 946
 947         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 948         pf->adapter->eth_dev = dev;
 949         pf->dev_data = dev->data;
 950
 951         hw->back = I40E_PF_TO_ADAPTER(pf);
 952         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 953         if (!hw->hw_addr) {
 954                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 955                              "as address is NULL");
 956                 return -ENODEV;
 957         }
 958
 959         hw->vendor_id = pci_dev->id.vendor_id;
 960         hw->device_id = pci_dev->id.device_id;
 961         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 962         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 963         hw->bus.device = pci_dev->addr.devid;
 964         hw->bus.func = pci_dev->addr.function;
 965         hw->adapter_stopped = 0;
 966
 967         /* Make sure all is clean before doing PF reset */
 968         i40e_clear_hw(hw);
 969
 970         /* Initialize the hardware */
 971         i40e_hw_init(dev);
 972
 973         /* Reset here to make sure all is clean for each PF */
 974         ret = i40e_pf_reset(hw);
 975         if (ret) {
 976                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 977                 return ret;
 978         }
 979
 980         /* Initialize the shared code (base driver) */
 981         ret = i40e_init_shared_code(hw);
 982         if (ret) {
 983                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 984                 return ret;
 985         }
 986
 987         /*
 988          * To work around the NVM issue,initialize registers
 989          * for flexible payload by software.
 990          * It should be removed once issues are fixed in NVM.
 991          */
 992         i40e_flex_payload_reg_init(hw);
 993
 994         /* Initialize the input set for filters (hash and fd) to default value */
 995         i40e_filter_input_set_init(pf);
 996
 997         /* Initialize the parameters for adminq */
 998         i40e_init_adminq_parameter(hw);
 999         ret = i40e_init_adminq(hw);
1000         if (ret != I40E_SUCCESS) {
1001                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1002                 return -EIO;
1003         }
1004         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1005                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1006                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1007                      ((hw->nvm.version >> 12) & 0xf),
1008                      ((hw->nvm.version >> 4) & 0xff),
1009                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1010
1011         /* Need the special FW version to support floating VEB */
1012         config_floating_veb(dev);
1013         /* Clear PXE mode */
1014         i40e_clear_pxe_mode(hw);
1015
1016         /*
1017          * On X710, performance number is far from the expectation on recent
1018          * firmware versions. The fix for this issue may not be integrated in
1019          * the following firmware version. So the workaround in software driver
1020          * is needed. It needs to modify the initial values of 3 internal only
1021          * registers. Note that the workaround can be removed when it is fixed
1022          * in firmware in the future.
1023          */
1024         i40e_configure_registers(hw);
1025
1026         /* Get hw capabilities */
1027         ret = i40e_get_cap(hw);
1028         if (ret != I40E_SUCCESS) {
1029                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1030                 goto err_get_capabilities;
1031         }
1032
1033         /* Initialize parameters for PF */
1034         ret = i40e_pf_parameter_init(dev);
1035         if (ret != 0) {
1036                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1037                 goto err_parameter_init;
1038         }
1039
1040         /* Initialize the queue management */
1041         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1042         if (ret < 0) {
1043                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1044                 goto err_qp_pool_init;
1045         }
1046         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1047                                 hw->func_caps.num_msix_vectors - 1);
1048         if (ret < 0) {
1049                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1050                 goto err_msix_pool_init;
1051         }
1052
1053         /* Initialize lan hmc */
1054         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1055                                 hw->func_caps.num_rx_qp, 0, 0);
1056         if (ret != I40E_SUCCESS) {
1057                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1058                 goto err_init_lan_hmc;
1059         }
1060
1061         /* Configure lan hmc */
1062         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1063         if (ret != I40E_SUCCESS) {
1064                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1065                 goto err_configure_lan_hmc;
1066         }
1067
1068         /* Get and check the mac address */
1069         i40e_get_mac_addr(hw, hw->mac.addr);
1070         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1071                 PMD_INIT_LOG(ERR, "mac address is not valid");
1072                 ret = -EIO;
1073                 goto err_get_mac_addr;
1074         }
1075         /* Copy the permanent MAC address */
1076         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1077                         (struct ether_addr *) hw->mac.perm_addr);
1078
1079         /* Disable flow control */
1080         hw->fc.requested_mode = I40E_FC_NONE;
1081         i40e_set_fc(hw, &aq_fail, TRUE);
1082
1083         /* Set the global registers with default ether type value */
1084         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1085         if (ret != I40E_SUCCESS) {
1086                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1087                              "VLAN ether type");
1088                 goto err_setup_pf_switch;
1089         }
1090
1091         /* PF setup, which includes VSI setup */
1092         ret = i40e_pf_setup(pf);
1093         if (ret) {
1094                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1095                 goto err_setup_pf_switch;
1096         }
1097
1098         /* reset all stats of the device, including pf and main vsi */
1099         i40e_dev_stats_reset(dev);
1100
1101         vsi = pf->main_vsi;
1102
1103         /* Disable double vlan by default */
1104         i40e_vsi_config_double_vlan(vsi, FALSE);
1105
1106         if (!vsi->max_macaddrs)
1107                 len = ETHER_ADDR_LEN;
1108         else
1109                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1110
1111         /* Should be after VSI initialized */
1112         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1113         if (!dev->data->mac_addrs) {
1114                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1115                                         "for storing mac address");
1116                 goto err_mac_alloc;
1117         }
1118         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1119                                         &dev->data->mac_addrs[0]);
1120
1121         /* initialize pf host driver to setup SRIOV resource if applicable */
1122         i40e_pf_host_init(dev);
1123
1124         /* register callback func to eal lib */
1125         rte_intr_callback_register(&(pci_dev->intr_handle),
1126                 i40e_dev_interrupt_handler, (void *)dev);
1127
1128         /* configure and enable device interrupt */
1129         i40e_pf_config_irq0(hw, TRUE);
1130         i40e_pf_enable_irq0(hw);
1131
1132         /* enable uio intr after callback register */
1133         rte_intr_enable(&(pci_dev->intr_handle));
1134         /*
1135          * Add an ethertype filter to drop all flow control frames transmitted
1136          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1137          * frames to wire.
1138          */
1139         i40e_add_tx_flow_control_drop_filter(pf);
1140
1141         /* Set the max frame size to 0x2600 by default,
1142          * in case other drivers changed the default value.
1143          */
1144         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1145
1146         /* initialize mirror rule list */
1147         TAILQ_INIT(&pf->mirror_list);
1148
1149         /* Init dcb to sw mode by default */
1150         ret = i40e_dcb_init_configure(dev, TRUE);
1151         if (ret != I40E_SUCCESS) {
1152                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1153                 pf->flags &= ~I40E_FLAG_DCB;
1154         }
1155
1156         return 0;
1157
1158 err_mac_alloc:
1159         i40e_vsi_release(pf->main_vsi);
1160 err_setup_pf_switch:
1161 err_get_mac_addr:
1162 err_configure_lan_hmc:
1163         (void)i40e_shutdown_lan_hmc(hw);
1164 err_init_lan_hmc:
1165         i40e_res_pool_destroy(&pf->msix_pool);
1166 err_msix_pool_init:
1167         i40e_res_pool_destroy(&pf->qp_pool);
1168 err_qp_pool_init:
1169 err_parameter_init:
1170 err_get_capabilities:
1171         (void)i40e_shutdown_adminq(hw);
1172
1173         return ret;
1174 }
1175
1176 static int
1177 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1178 {
1179         struct rte_pci_device *pci_dev;
1180         struct i40e_hw *hw;
1181         struct i40e_filter_control_settings settings;
1182         int ret;
1183         uint8_t aq_fail = 0;
1184
1185         PMD_INIT_FUNC_TRACE();
1186
1187         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1188                 return 0;
1189
1190         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         pci_dev = dev->pci_dev;
1192
1193         if (hw->adapter_stopped == 0)
1194                 i40e_dev_close(dev);
1195
1196         dev->dev_ops = NULL;
1197         dev->rx_pkt_burst = NULL;
1198         dev->tx_pkt_burst = NULL;
1199
1200         /* Disable LLDP */
1201         ret = i40e_aq_stop_lldp(hw, true, NULL);
1202         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1203                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1204
1205         /* Clear PXE mode */
1206         i40e_clear_pxe_mode(hw);
1207
1208         /* Unconfigure filter control */
1209         memset(&settings, 0, sizeof(settings));
1210         ret = i40e_set_filter_control(hw, &settings);
1211         if (ret)
1212                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1213                                         ret);
1214
1215         /* Disable flow control */
1216         hw->fc.requested_mode = I40E_FC_NONE;
1217         i40e_set_fc(hw, &aq_fail, TRUE);
1218
1219         /* uninitialize pf host driver */
1220         i40e_pf_host_uninit(dev);
1221
1222         rte_free(dev->data->mac_addrs);
1223         dev->data->mac_addrs = NULL;
1224
1225         /* disable uio intr before callback unregister */
1226         rte_intr_disable(&(pci_dev->intr_handle));
1227
1228         /* register callback func to eal lib */
1229         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1230                 i40e_dev_interrupt_handler, (void *)dev);
1231
1232         return 0;
1233 }
1234
1235 static int
1236 i40e_dev_configure(struct rte_eth_dev *dev)
1237 {
1238         struct i40e_adapter *ad =
1239                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1240         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1241         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1242         int i, ret;
1243
1244         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1245          * bulk allocation or vector Rx preconditions we will reset it.
1246          */
1247         ad->rx_bulk_alloc_allowed = true;
1248         ad->rx_vec_allowed = true;
1249         ad->tx_simple_allowed = true;
1250         ad->tx_vec_allowed = true;
1251
1252         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1253                 ret = i40e_fdir_setup(pf);
1254                 if (ret != I40E_SUCCESS) {
1255                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1256                         return -ENOTSUP;
1257                 }
1258                 ret = i40e_fdir_configure(dev);
1259                 if (ret < 0) {
1260                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1261                         goto err;
1262                 }
1263         } else
1264                 i40e_fdir_teardown(pf);
1265
1266         ret = i40e_dev_init_vlan(dev);
1267         if (ret < 0)
1268                 goto err;
1269
1270         /* VMDQ setup.
1271          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1272          *  RSS setting have different requirements.
1273          *  General PMD driver call sequence are NIC init, configure,
1274          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1275          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1276          *  applicable. So, VMDQ setting has to be done before
1277          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1278          *  For RSS setting, it will try to calculate actual configured RX queue
1279          *  number, which will be available after rx_queue_setup(). dev_start()
1280          *  function is good to place RSS setup.
1281          */
1282         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1283                 ret = i40e_vmdq_setup(dev);
1284                 if (ret)
1285                         goto err;
1286         }
1287
1288         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1289                 ret = i40e_dcb_setup(dev);
1290                 if (ret) {
1291                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1292                         goto err_dcb;
1293                 }
1294         }
1295
1296         return 0;
1297
1298 err_dcb:
1299         /* need to release vmdq resource if exists */
1300         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1301                 i40e_vsi_release(pf->vmdq[i].vsi);
1302                 pf->vmdq[i].vsi = NULL;
1303         }
1304         rte_free(pf->vmdq);
1305         pf->vmdq = NULL;
1306 err:
1307         /* need to release fdir resource if exists */
1308         i40e_fdir_teardown(pf);
1309         return ret;
1310 }
1311
1312 void
1313 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1314 {
1315         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1316         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1317         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1318         uint16_t msix_vect = vsi->msix_intr;
1319         uint16_t i;
1320
1321         for (i = 0; i < vsi->nb_qps; i++) {
1322                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1323                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1324                 rte_wmb();
1325         }
1326
1327         if (vsi->type != I40E_VSI_SRIOV) {
1328                 if (!rte_intr_allow_others(intr_handle)) {
1329                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1330                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1331                         I40E_WRITE_REG(hw,
1332                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1333                                        0);
1334                 } else {
1335                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1336                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1337                         I40E_WRITE_REG(hw,
1338                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1339                                                        msix_vect - 1), 0);
1340                 }
1341         } else {
1342                 uint32_t reg;
1343                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1344                         vsi->user_param + (msix_vect - 1);
1345
1346                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1347                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1348         }
1349         I40E_WRITE_FLUSH(hw);
1350 }
1351
1352 static void
1353 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1354                        int base_queue, int nb_queue)
1355 {
1356         int i;
1357         uint32_t val;
1358         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1359
1360         /* Bind all RX queues to allocated MSIX interrupt */
1361         for (i = 0; i < nb_queue; i++) {
1362                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1363                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1364                         ((base_queue + i + 1) <<
1365                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1366                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1367                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1368
1369                 if (i == nb_queue - 1)
1370                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1371                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1372         }
1373
1374         /* Write first RX queue to Link list register as the head element */
1375         if (vsi->type != I40E_VSI_SRIOV) {
1376                 uint16_t interval =
1377                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1378
1379                 if (msix_vect == I40E_MISC_VEC_ID) {
1380                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1381                                        (base_queue <<
1382                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1383                                        (0x0 <<
1384                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1385                         I40E_WRITE_REG(hw,
1386                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1387                                        interval);
1388                 } else {
1389                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1390                                        (base_queue <<
1391                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1392                                        (0x0 <<
1393                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1394                         I40E_WRITE_REG(hw,
1395                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1396                                                        msix_vect - 1),
1397                                        interval);
1398                 }
1399         } else {
1400                 uint32_t reg;
1401
1402                 if (msix_vect == I40E_MISC_VEC_ID) {
1403                         I40E_WRITE_REG(hw,
1404                                        I40E_VPINT_LNKLST0(vsi->user_param),
1405                                        (base_queue <<
1406                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1407                                        (0x0 <<
1408                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1409                 } else {
1410                         /* num_msix_vectors_vf needs to minus irq0 */
1411                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1412                                 vsi->user_param + (msix_vect - 1);
1413
1414                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1415                                        (base_queue <<
1416                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1417                                        (0x0 <<
1418                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1419                 }
1420         }
1421
1422         I40E_WRITE_FLUSH(hw);
1423 }
1424
1425 void
1426 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1427 {
1428         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1429         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1430         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1431         uint16_t msix_vect = vsi->msix_intr;
1432         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1433         uint16_t queue_idx = 0;
1434         int record = 0;
1435         uint32_t val;
1436         int i;
1437
1438         for (i = 0; i < vsi->nb_qps; i++) {
1439                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1440                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1441         }
1442
1443         /* INTENA flag is not auto-cleared for interrupt */
1444         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1445         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1446                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1447                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1448         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1449
1450         /* VF bind interrupt */
1451         if (vsi->type == I40E_VSI_SRIOV) {
1452                 __vsi_queues_bind_intr(vsi, msix_vect,
1453                                        vsi->base_queue, vsi->nb_qps);
1454                 return;
1455         }
1456
1457         /* PF & VMDq bind interrupt */
1458         if (rte_intr_dp_is_en(intr_handle)) {
1459                 if (vsi->type == I40E_VSI_MAIN) {
1460                         queue_idx = 0;
1461                         record = 1;
1462                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1463                         struct i40e_vsi *main_vsi =
1464                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1465                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1466                         record = 1;
1467                 }
1468         }
1469
1470         for (i = 0; i < vsi->nb_used_qps; i++) {
1471                 if (nb_msix <= 1) {
1472                         if (!rte_intr_allow_others(intr_handle))
1473                                 /* allow to share MISC_VEC_ID */
1474                                 msix_vect = I40E_MISC_VEC_ID;
1475
1476                         /* no enough msix_vect, map all to one */
1477                         __vsi_queues_bind_intr(vsi, msix_vect,
1478                                                vsi->base_queue + i,
1479                                                vsi->nb_used_qps - i);
1480                         for (; !!record && i < vsi->nb_used_qps; i++)
1481                                 intr_handle->intr_vec[queue_idx + i] =
1482                                         msix_vect;
1483                         break;
1484                 }
1485                 /* 1:1 queue/msix_vect mapping */
1486                 __vsi_queues_bind_intr(vsi, msix_vect,
1487                                        vsi->base_queue + i, 1);
1488                 if (!!record)
1489                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1490
1491                 msix_vect++;
1492                 nb_msix--;
1493         }
1494 }
1495
1496 static void
1497 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1498 {
1499         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1500         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1501         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1502         uint16_t interval = i40e_calc_itr_interval(\
1503                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1504         uint16_t msix_intr, i;
1505
1506         if (rte_intr_allow_others(intr_handle))
1507                 for (i = 0; i < vsi->nb_msix; i++) {
1508                         msix_intr = vsi->msix_intr + i;
1509                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1510                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1511                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1512                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1513                                 (interval <<
1514                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1515                 }
1516         else
1517                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1518                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1519                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1520                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1521                                (interval <<
1522                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1523
1524         I40E_WRITE_FLUSH(hw);
1525 }
1526
1527 static void
1528 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1529 {
1530         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1531         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1532         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1533         uint16_t msix_intr, i;
1534
1535         if (rte_intr_allow_others(intr_handle))
1536                 for (i = 0; i < vsi->nb_msix; i++) {
1537                         msix_intr = vsi->msix_intr + i;
1538                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1539                                        0);
1540                 }
1541         else
1542                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1543
1544         I40E_WRITE_FLUSH(hw);
1545 }
1546
1547 static inline uint8_t
1548 i40e_parse_link_speeds(uint16_t link_speeds)
1549 {
1550         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1551
1552         if (link_speeds & ETH_LINK_SPEED_40G)
1553                 link_speed |= I40E_LINK_SPEED_40GB;
1554         if (link_speeds & ETH_LINK_SPEED_20G)
1555                 link_speed |= I40E_LINK_SPEED_20GB;
1556         if (link_speeds & ETH_LINK_SPEED_10G)
1557                 link_speed |= I40E_LINK_SPEED_10GB;
1558         if (link_speeds & ETH_LINK_SPEED_1G)
1559                 link_speed |= I40E_LINK_SPEED_1GB;
1560         if (link_speeds & ETH_LINK_SPEED_100M)
1561                 link_speed |= I40E_LINK_SPEED_100MB;
1562
1563         return link_speed;
1564 }
1565
1566 static int
1567 i40e_phy_conf_link(struct i40e_hw *hw,
1568                    uint8_t abilities,
1569                    uint8_t force_speed)
1570 {
1571         enum i40e_status_code status;
1572         struct i40e_aq_get_phy_abilities_resp phy_ab;
1573         struct i40e_aq_set_phy_config phy_conf;
1574         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1575                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1576                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1577                         I40E_AQ_PHY_FLAG_LOW_POWER;
1578         const uint8_t advt = I40E_LINK_SPEED_40GB |
1579                         I40E_LINK_SPEED_10GB |
1580                         I40E_LINK_SPEED_1GB |
1581                         I40E_LINK_SPEED_100MB;
1582         int ret = -ENOTSUP;
1583
1584
1585         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1586                                               NULL);
1587         if (status)
1588                 return ret;
1589
1590         memset(&phy_conf, 0, sizeof(phy_conf));
1591
1592         /* bits 0-2 use the values from get_phy_abilities_resp */
1593         abilities &= ~mask;
1594         abilities |= phy_ab.abilities & mask;
1595
1596         /* update ablities and speed */
1597         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1598                 phy_conf.link_speed = advt;
1599         else
1600                 phy_conf.link_speed = force_speed;
1601
1602         phy_conf.abilities = abilities;
1603
1604         /* use get_phy_abilities_resp value for the rest */
1605         phy_conf.phy_type = phy_ab.phy_type;
1606         phy_conf.eee_capability = phy_ab.eee_capability;
1607         phy_conf.eeer = phy_ab.eeer_val;
1608         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1609
1610         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1611                     phy_ab.abilities, phy_ab.link_speed);
1612         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1613                     phy_conf.abilities, phy_conf.link_speed);
1614
1615         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1616         if (status)
1617                 return ret;
1618
1619         return I40E_SUCCESS;
1620 }
1621
1622 static int
1623 i40e_apply_link_speed(struct rte_eth_dev *dev)
1624 {
1625         uint8_t speed;
1626         uint8_t abilities = 0;
1627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628         struct rte_eth_conf *conf = &dev->data->dev_conf;
1629
1630         speed = i40e_parse_link_speeds(conf->link_speeds);
1631         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1632         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1633                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1634         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1635
1636         /* Skip changing speed on 40G interfaces, FW does not support */
1637         if (i40e_is_40G_device(hw->device_id)) {
1638                 speed =  I40E_LINK_SPEED_UNKNOWN;
1639                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1640         }
1641
1642         return i40e_phy_conf_link(hw, abilities, speed);
1643 }
1644
1645 static int
1646 i40e_dev_start(struct rte_eth_dev *dev)
1647 {
1648         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         struct i40e_vsi *main_vsi = pf->main_vsi;
1651         int ret, i;
1652         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1653         uint32_t intr_vector = 0;
1654
1655         hw->adapter_stopped = 0;
1656
1657         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1658                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1659                              dev->data->port_id);
1660                 return -EINVAL;
1661         }
1662
1663         rte_intr_disable(intr_handle);
1664
1665         if ((rte_intr_cap_multiple(intr_handle) ||
1666              !RTE_ETH_DEV_SRIOV(dev).active) &&
1667             dev->data->dev_conf.intr_conf.rxq != 0) {
1668                 intr_vector = dev->data->nb_rx_queues;
1669                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1670                         return -1;
1671         }
1672
1673         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1674                 intr_handle->intr_vec =
1675                         rte_zmalloc("intr_vec",
1676                                     dev->data->nb_rx_queues * sizeof(int),
1677                                     0);
1678                 if (!intr_handle->intr_vec) {
1679                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1680                                      " intr_vec\n", dev->data->nb_rx_queues);
1681                         return -ENOMEM;
1682                 }
1683         }
1684
1685         /* Initialize VSI */
1686         ret = i40e_dev_rxtx_init(pf);
1687         if (ret != I40E_SUCCESS) {
1688                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1689                 goto err_up;
1690         }
1691
1692         /* Map queues with MSIX interrupt */
1693         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1694                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1695         i40e_vsi_queues_bind_intr(main_vsi);
1696         i40e_vsi_enable_queues_intr(main_vsi);
1697
1698         /* Map VMDQ VSI queues with MSIX interrupt */
1699         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1700                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1701                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1702                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1703         }
1704
1705         /* enable FDIR MSIX interrupt */
1706         if (pf->fdir.fdir_vsi) {
1707                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1708                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1709         }
1710
1711         /* Enable all queues which have been configured */
1712         ret = i40e_dev_switch_queues(pf, TRUE);
1713         if (ret != I40E_SUCCESS) {
1714                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1715                 goto err_up;
1716         }
1717
1718         /* Enable receiving broadcast packets */
1719         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1720         if (ret != I40E_SUCCESS)
1721                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1722
1723         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1724                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1725                                                 true, NULL);
1726                 if (ret != I40E_SUCCESS)
1727                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1728         }
1729
1730         /* Apply link configure */
1731         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1732                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1733                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1734                 PMD_DRV_LOG(ERR, "Invalid link setting");
1735                 goto err_up;
1736         }
1737         ret = i40e_apply_link_speed(dev);
1738         if (I40E_SUCCESS != ret) {
1739                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1740                 goto err_up;
1741         }
1742
1743         if (!rte_intr_allow_others(intr_handle)) {
1744                 rte_intr_callback_unregister(intr_handle,
1745                                              i40e_dev_interrupt_handler,
1746                                              (void *)dev);
1747                 /* configure and enable device interrupt */
1748                 i40e_pf_config_irq0(hw, FALSE);
1749                 i40e_pf_enable_irq0(hw);
1750
1751                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1752                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1753                                      " no intr multiplex\n");
1754         }
1755
1756         /* enable uio intr after callback register */
1757         rte_intr_enable(intr_handle);
1758
1759         return I40E_SUCCESS;
1760
1761 err_up:
1762         i40e_dev_switch_queues(pf, FALSE);
1763         i40e_dev_clear_queues(dev);
1764
1765         return ret;
1766 }
1767
1768 static void
1769 i40e_dev_stop(struct rte_eth_dev *dev)
1770 {
1771         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1772         struct i40e_vsi *main_vsi = pf->main_vsi;
1773         struct i40e_mirror_rule *p_mirror;
1774         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1775         int i;
1776
1777         /* Disable all queues */
1778         i40e_dev_switch_queues(pf, FALSE);
1779
1780         /* un-map queues with interrupt registers */
1781         i40e_vsi_disable_queues_intr(main_vsi);
1782         i40e_vsi_queues_unbind_intr(main_vsi);
1783
1784         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1785                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1786                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1787         }
1788
1789         if (pf->fdir.fdir_vsi) {
1790                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1791                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1792         }
1793         /* Clear all queues and release memory */
1794         i40e_dev_clear_queues(dev);
1795
1796         /* Set link down */
1797         i40e_dev_set_link_down(dev);
1798
1799         /* Remove all mirror rules */
1800         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1801                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1802                 rte_free(p_mirror);
1803         }
1804         pf->nb_mirror_rule = 0;
1805
1806         if (!rte_intr_allow_others(intr_handle))
1807                 /* resume to the default handler */
1808                 rte_intr_callback_register(intr_handle,
1809                                            i40e_dev_interrupt_handler,
1810                                            (void *)dev);
1811
1812         /* Clean datapath event and queue/vec mapping */
1813         rte_intr_efd_disable(intr_handle);
1814         if (intr_handle->intr_vec) {
1815                 rte_free(intr_handle->intr_vec);
1816                 intr_handle->intr_vec = NULL;
1817         }
1818 }
1819
1820 static void
1821 i40e_dev_close(struct rte_eth_dev *dev)
1822 {
1823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1824         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         uint32_t reg;
1826         int i;
1827
1828         PMD_INIT_FUNC_TRACE();
1829
1830         i40e_dev_stop(dev);
1831         hw->adapter_stopped = 1;
1832         i40e_dev_free_queues(dev);
1833
1834         /* Disable interrupt */
1835         i40e_pf_disable_irq0(hw);
1836         rte_intr_disable(&(dev->pci_dev->intr_handle));
1837
1838         /* shutdown and destroy the HMC */
1839         i40e_shutdown_lan_hmc(hw);
1840
1841         /* release all the existing VSIs and VEBs */
1842         i40e_fdir_teardown(pf);
1843         i40e_vsi_release(pf->main_vsi);
1844
1845         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1846                 i40e_vsi_release(pf->vmdq[i].vsi);
1847                 pf->vmdq[i].vsi = NULL;
1848         }
1849
1850         rte_free(pf->vmdq);
1851         pf->vmdq = NULL;
1852
1853         /* shutdown the adminq */
1854         i40e_aq_queue_shutdown(hw, true);
1855         i40e_shutdown_adminq(hw);
1856
1857         i40e_res_pool_destroy(&pf->qp_pool);
1858         i40e_res_pool_destroy(&pf->msix_pool);
1859
1860         /* force a PF reset to clean anything leftover */
1861         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1862         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1863                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1864         I40E_WRITE_FLUSH(hw);
1865 }
1866
1867 static void
1868 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1869 {
1870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct i40e_vsi *vsi = pf->main_vsi;
1873         int status;
1874
1875         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1876                                                      true, NULL, true);
1877         if (status != I40E_SUCCESS)
1878                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1879
1880         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1881                                                         TRUE, NULL);
1882         if (status != I40E_SUCCESS)
1883                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1884
1885 }
1886
1887 static void
1888 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1889 {
1890         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1892         struct i40e_vsi *vsi = pf->main_vsi;
1893         int status;
1894
1895         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1896                                                      false, NULL, true);
1897         if (status != I40E_SUCCESS)
1898                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1899
1900         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1901                                                         false, NULL);
1902         if (status != I40E_SUCCESS)
1903                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1904 }
1905
1906 static void
1907 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1908 {
1909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         struct i40e_vsi *vsi = pf->main_vsi;
1912         int ret;
1913
1914         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1915         if (ret != I40E_SUCCESS)
1916                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1917 }
1918
1919 static void
1920 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1921 {
1922         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1923         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924         struct i40e_vsi *vsi = pf->main_vsi;
1925         int ret;
1926
1927         if (dev->data->promiscuous == 1)
1928                 return; /* must remain in all_multicast mode */
1929
1930         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1931                                 vsi->seid, FALSE, NULL);
1932         if (ret != I40E_SUCCESS)
1933                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1934 }
1935
1936 /*
1937  * Set device link up.
1938  */
1939 static int
1940 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1941 {
1942         /* re-apply link speed setting */
1943         return i40e_apply_link_speed(dev);
1944 }
1945
1946 /*
1947  * Set device link down.
1948  */
1949 static int
1950 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1951 {
1952         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1953         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1954         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955
1956         return i40e_phy_conf_link(hw, abilities, speed);
1957 }
1958
1959 int
1960 i40e_dev_link_update(struct rte_eth_dev *dev,
1961                      int wait_to_complete)
1962 {
1963 #define CHECK_INTERVAL 100  /* 100ms */
1964 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966         struct i40e_link_status link_status;
1967         struct rte_eth_link link, old;
1968         int status;
1969         unsigned rep_cnt = MAX_REPEAT_TIME;
1970
1971         memset(&link, 0, sizeof(link));
1972         memset(&old, 0, sizeof(old));
1973         memset(&link_status, 0, sizeof(link_status));
1974         rte_i40e_dev_atomic_read_link_status(dev, &old);
1975
1976         do {
1977                 /* Get link status information from hardware */
1978                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1979                 if (status != I40E_SUCCESS) {
1980                         link.link_speed = ETH_SPEED_NUM_100M;
1981                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1982                         PMD_DRV_LOG(ERR, "Failed to get link info");
1983                         goto out;
1984                 }
1985
1986                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1987                 if (!wait_to_complete)
1988                         break;
1989
1990                 rte_delay_ms(CHECK_INTERVAL);
1991         } while (!link.link_status && rep_cnt--);
1992
1993         if (!link.link_status)
1994                 goto out;
1995
1996         /* i40e uses full duplex only */
1997         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1998
1999         /* Parse the link status */
2000         switch (link_status.link_speed) {
2001         case I40E_LINK_SPEED_100MB:
2002                 link.link_speed = ETH_SPEED_NUM_100M;
2003                 break;
2004         case I40E_LINK_SPEED_1GB:
2005                 link.link_speed = ETH_SPEED_NUM_1G;
2006                 break;
2007         case I40E_LINK_SPEED_10GB:
2008                 link.link_speed = ETH_SPEED_NUM_10G;
2009                 break;
2010         case I40E_LINK_SPEED_20GB:
2011                 link.link_speed = ETH_SPEED_NUM_20G;
2012                 break;
2013         case I40E_LINK_SPEED_40GB:
2014                 link.link_speed = ETH_SPEED_NUM_40G;
2015                 break;
2016         default:
2017                 link.link_speed = ETH_SPEED_NUM_100M;
2018                 break;
2019         }
2020
2021         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2022                         ETH_LINK_SPEED_FIXED);
2023
2024 out:
2025         rte_i40e_dev_atomic_write_link_status(dev, &link);
2026         if (link.link_status == old.link_status)
2027                 return -1;
2028
2029         return 0;
2030 }
2031
2032 /* Get all the statistics of a VSI */
2033 void
2034 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2035 {
2036         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2037         struct i40e_eth_stats *nes = &vsi->eth_stats;
2038         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2039         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2040
2041         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2042                             vsi->offset_loaded, &oes->rx_bytes,
2043                             &nes->rx_bytes);
2044         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2045                             vsi->offset_loaded, &oes->rx_unicast,
2046                             &nes->rx_unicast);
2047         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2048                             vsi->offset_loaded, &oes->rx_multicast,
2049                             &nes->rx_multicast);
2050         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2051                             vsi->offset_loaded, &oes->rx_broadcast,
2052                             &nes->rx_broadcast);
2053         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2054                             &oes->rx_discards, &nes->rx_discards);
2055         /* GLV_REPC not supported */
2056         /* GLV_RMPC not supported */
2057         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2058                             &oes->rx_unknown_protocol,
2059                             &nes->rx_unknown_protocol);
2060         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2061                             vsi->offset_loaded, &oes->tx_bytes,
2062                             &nes->tx_bytes);
2063         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2064                             vsi->offset_loaded, &oes->tx_unicast,
2065                             &nes->tx_unicast);
2066         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2067                             vsi->offset_loaded, &oes->tx_multicast,
2068                             &nes->tx_multicast);
2069         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2070                             vsi->offset_loaded,  &oes->tx_broadcast,
2071                             &nes->tx_broadcast);
2072         /* GLV_TDPC not supported */
2073         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2074                             &oes->tx_errors, &nes->tx_errors);
2075         vsi->offset_loaded = true;
2076
2077         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2078                     vsi->vsi_id);
2079         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2080         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2081         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2082         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2083         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2084         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2085                     nes->rx_unknown_protocol);
2086         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2087         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2088         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2089         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2090         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2091         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2092         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2093                     vsi->vsi_id);
2094 }
2095
2096 static void
2097 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2098 {
2099         unsigned int i;
2100         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2101         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2102
2103         /* Get statistics of struct i40e_eth_stats */
2104         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2105                             I40E_GLPRT_GORCL(hw->port),
2106                             pf->offset_loaded, &os->eth.rx_bytes,
2107                             &ns->eth.rx_bytes);
2108         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2109                             I40E_GLPRT_UPRCL(hw->port),
2110                             pf->offset_loaded, &os->eth.rx_unicast,
2111                             &ns->eth.rx_unicast);
2112         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2113                             I40E_GLPRT_MPRCL(hw->port),
2114                             pf->offset_loaded, &os->eth.rx_multicast,
2115                             &ns->eth.rx_multicast);
2116         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2117                             I40E_GLPRT_BPRCL(hw->port),
2118                             pf->offset_loaded, &os->eth.rx_broadcast,
2119                             &ns->eth.rx_broadcast);
2120         /* Workaround: CRC size should not be included in byte statistics,
2121          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2122          */
2123         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2124                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2125
2126         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2127                             pf->offset_loaded, &os->eth.rx_discards,
2128                             &ns->eth.rx_discards);
2129         /* GLPRT_REPC not supported */
2130         /* GLPRT_RMPC not supported */
2131         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2132                             pf->offset_loaded,
2133                             &os->eth.rx_unknown_protocol,
2134                             &ns->eth.rx_unknown_protocol);
2135         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2136                             I40E_GLPRT_GOTCL(hw->port),
2137                             pf->offset_loaded, &os->eth.tx_bytes,
2138                             &ns->eth.tx_bytes);
2139         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2140                             I40E_GLPRT_UPTCL(hw->port),
2141                             pf->offset_loaded, &os->eth.tx_unicast,
2142                             &ns->eth.tx_unicast);
2143         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2144                             I40E_GLPRT_MPTCL(hw->port),
2145                             pf->offset_loaded, &os->eth.tx_multicast,
2146                             &ns->eth.tx_multicast);
2147         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2148                             I40E_GLPRT_BPTCL(hw->port),
2149                             pf->offset_loaded, &os->eth.tx_broadcast,
2150                             &ns->eth.tx_broadcast);
2151         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2152                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2153         /* GLPRT_TEPC not supported */
2154
2155         /* additional port specific stats */
2156         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2157                             pf->offset_loaded, &os->tx_dropped_link_down,
2158                             &ns->tx_dropped_link_down);
2159         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2160                             pf->offset_loaded, &os->crc_errors,
2161                             &ns->crc_errors);
2162         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2163                             pf->offset_loaded, &os->illegal_bytes,
2164                             &ns->illegal_bytes);
2165         /* GLPRT_ERRBC not supported */
2166         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2167                             pf->offset_loaded, &os->mac_local_faults,
2168                             &ns->mac_local_faults);
2169         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2170                             pf->offset_loaded, &os->mac_remote_faults,
2171                             &ns->mac_remote_faults);
2172         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2173                             pf->offset_loaded, &os->rx_length_errors,
2174                             &ns->rx_length_errors);
2175         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2176                             pf->offset_loaded, &os->link_xon_rx,
2177                             &ns->link_xon_rx);
2178         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2179                             pf->offset_loaded, &os->link_xoff_rx,
2180                             &ns->link_xoff_rx);
2181         for (i = 0; i < 8; i++) {
2182                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2183                                     pf->offset_loaded,
2184                                     &os->priority_xon_rx[i],
2185                                     &ns->priority_xon_rx[i]);
2186                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2187                                     pf->offset_loaded,
2188                                     &os->priority_xoff_rx[i],
2189                                     &ns->priority_xoff_rx[i]);
2190         }
2191         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2192                             pf->offset_loaded, &os->link_xon_tx,
2193                             &ns->link_xon_tx);
2194         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2195                             pf->offset_loaded, &os->link_xoff_tx,
2196                             &ns->link_xoff_tx);
2197         for (i = 0; i < 8; i++) {
2198                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2199                                     pf->offset_loaded,
2200                                     &os->priority_xon_tx[i],
2201                                     &ns->priority_xon_tx[i]);
2202                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2203                                     pf->offset_loaded,
2204                                     &os->priority_xoff_tx[i],
2205                                     &ns->priority_xoff_tx[i]);
2206                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2207                                     pf->offset_loaded,
2208                                     &os->priority_xon_2_xoff[i],
2209                                     &ns->priority_xon_2_xoff[i]);
2210         }
2211         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2212                             I40E_GLPRT_PRC64L(hw->port),
2213                             pf->offset_loaded, &os->rx_size_64,
2214                             &ns->rx_size_64);
2215         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2216                             I40E_GLPRT_PRC127L(hw->port),
2217                             pf->offset_loaded, &os->rx_size_127,
2218                             &ns->rx_size_127);
2219         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2220                             I40E_GLPRT_PRC255L(hw->port),
2221                             pf->offset_loaded, &os->rx_size_255,
2222                             &ns->rx_size_255);
2223         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2224                             I40E_GLPRT_PRC511L(hw->port),
2225                             pf->offset_loaded, &os->rx_size_511,
2226                             &ns->rx_size_511);
2227         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2228                             I40E_GLPRT_PRC1023L(hw->port),
2229                             pf->offset_loaded, &os->rx_size_1023,
2230                             &ns->rx_size_1023);
2231         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2232                             I40E_GLPRT_PRC1522L(hw->port),
2233                             pf->offset_loaded, &os->rx_size_1522,
2234                             &ns->rx_size_1522);
2235         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2236                             I40E_GLPRT_PRC9522L(hw->port),
2237                             pf->offset_loaded, &os->rx_size_big,
2238                             &ns->rx_size_big);
2239         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2240                             pf->offset_loaded, &os->rx_undersize,
2241                             &ns->rx_undersize);
2242         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2243                             pf->offset_loaded, &os->rx_fragments,
2244                             &ns->rx_fragments);
2245         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2246                             pf->offset_loaded, &os->rx_oversize,
2247                             &ns->rx_oversize);
2248         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2249                             pf->offset_loaded, &os->rx_jabber,
2250                             &ns->rx_jabber);
2251         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2252                             I40E_GLPRT_PTC64L(hw->port),
2253                             pf->offset_loaded, &os->tx_size_64,
2254                             &ns->tx_size_64);
2255         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2256                             I40E_GLPRT_PTC127L(hw->port),
2257                             pf->offset_loaded, &os->tx_size_127,
2258                             &ns->tx_size_127);
2259         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2260                             I40E_GLPRT_PTC255L(hw->port),
2261                             pf->offset_loaded, &os->tx_size_255,
2262                             &ns->tx_size_255);
2263         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2264                             I40E_GLPRT_PTC511L(hw->port),
2265                             pf->offset_loaded, &os->tx_size_511,
2266                             &ns->tx_size_511);
2267         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2268                             I40E_GLPRT_PTC1023L(hw->port),
2269                             pf->offset_loaded, &os->tx_size_1023,
2270                             &ns->tx_size_1023);
2271         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2272                             I40E_GLPRT_PTC1522L(hw->port),
2273                             pf->offset_loaded, &os->tx_size_1522,
2274                             &ns->tx_size_1522);
2275         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2276                             I40E_GLPRT_PTC9522L(hw->port),
2277                             pf->offset_loaded, &os->tx_size_big,
2278                             &ns->tx_size_big);
2279         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2280                            pf->offset_loaded,
2281                            &os->fd_sb_match, &ns->fd_sb_match);
2282         /* GLPRT_MSPDC not supported */
2283         /* GLPRT_XEC not supported */
2284
2285         pf->offset_loaded = true;
2286
2287         if (pf->main_vsi)
2288                 i40e_update_vsi_stats(pf->main_vsi);
2289 }
2290
2291 /* Get all statistics of a port */
2292 static void
2293 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2294 {
2295         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2296         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2298         unsigned i;
2299
2300         /* call read registers - updates values, now write them to struct */
2301         i40e_read_stats_registers(pf, hw);
2302
2303         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2304                         pf->main_vsi->eth_stats.rx_multicast +
2305                         pf->main_vsi->eth_stats.rx_broadcast -
2306                         pf->main_vsi->eth_stats.rx_discards;
2307         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2308                         pf->main_vsi->eth_stats.tx_multicast +
2309                         pf->main_vsi->eth_stats.tx_broadcast;
2310         stats->ibytes   = ns->eth.rx_bytes;
2311         stats->obytes   = ns->eth.tx_bytes;
2312         stats->oerrors  = ns->eth.tx_errors +
2313                         pf->main_vsi->eth_stats.tx_errors;
2314
2315         /* Rx Errors */
2316         stats->imissed  = ns->eth.rx_discards +
2317                         pf->main_vsi->eth_stats.rx_discards;
2318         stats->ierrors  = ns->crc_errors +
2319                         ns->rx_length_errors + ns->rx_undersize +
2320                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2321
2322         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2323         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2324         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2325         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2326         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2327         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2328         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2329                     ns->eth.rx_unknown_protocol);
2330         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2331         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2332         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2333         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2334         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2335         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2336
2337         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2338                     ns->tx_dropped_link_down);
2339         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2340         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2341                     ns->illegal_bytes);
2342         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2343         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2344                     ns->mac_local_faults);
2345         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2346                     ns->mac_remote_faults);
2347         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2348                     ns->rx_length_errors);
2349         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2350         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2351         for (i = 0; i < 8; i++) {
2352                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2353                                 i, ns->priority_xon_rx[i]);
2354                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2355                                 i, ns->priority_xoff_rx[i]);
2356         }
2357         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2358         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2359         for (i = 0; i < 8; i++) {
2360                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2361                                 i, ns->priority_xon_tx[i]);
2362                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2363                                 i, ns->priority_xoff_tx[i]);
2364                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2365                                 i, ns->priority_xon_2_xoff[i]);
2366         }
2367         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2368         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2369         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2370         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2371         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2372         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2373         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2374         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2375         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2376         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2377         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2378         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2379         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2380         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2381         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2382         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2383         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2384         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2385         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2386                         ns->mac_short_packet_dropped);
2387         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2388                     ns->checksum_error);
2389         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2390         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2391 }
2392
2393 /* Reset the statistics */
2394 static void
2395 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2396 {
2397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399
2400         /* Mark PF and VSI stats to update the offset, aka "reset" */
2401         pf->offset_loaded = false;
2402         if (pf->main_vsi)
2403                 pf->main_vsi->offset_loaded = false;
2404
2405         /* read the stats, reading current register values into offset */
2406         i40e_read_stats_registers(pf, hw);
2407 }
2408
2409 static uint32_t
2410 i40e_xstats_calc_num(void)
2411 {
2412         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2413                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2414                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2415 }
2416
2417 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2418                                      struct rte_eth_xstat_name *xstats_names,
2419                                      __rte_unused unsigned limit)
2420 {
2421         unsigned count = 0;
2422         unsigned i, prio;
2423
2424         if (xstats_names == NULL)
2425                 return i40e_xstats_calc_num();
2426
2427         /* Note: limit checked in rte_eth_xstats_names() */
2428
2429         /* Get stats from i40e_eth_stats struct */
2430         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2431                 snprintf(xstats_names[count].name,
2432                          sizeof(xstats_names[count].name),
2433                          "%s", rte_i40e_stats_strings[i].name);
2434                 count++;
2435         }
2436
2437         /* Get individiual stats from i40e_hw_port struct */
2438         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2439                 snprintf(xstats_names[count].name,
2440                         sizeof(xstats_names[count].name),
2441                          "%s", rte_i40e_hw_port_strings[i].name);
2442                 count++;
2443         }
2444
2445         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2446                 for (prio = 0; prio < 8; prio++) {
2447                         snprintf(xstats_names[count].name,
2448                                  sizeof(xstats_names[count].name),
2449                                  "rx_priority%u_%s", prio,
2450                                  rte_i40e_rxq_prio_strings[i].name);
2451                         count++;
2452                 }
2453         }
2454
2455         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2456                 for (prio = 0; prio < 8; prio++) {
2457                         snprintf(xstats_names[count].name,
2458                                  sizeof(xstats_names[count].name),
2459                                  "tx_priority%u_%s", prio,
2460                                  rte_i40e_txq_prio_strings[i].name);
2461                         count++;
2462                 }
2463         }
2464         return count;
2465 }
2466
2467 static int
2468 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2469                     unsigned n)
2470 {
2471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473         unsigned i, count, prio;
2474         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2475
2476         count = i40e_xstats_calc_num();
2477         if (n < count)
2478                 return count;
2479
2480         i40e_read_stats_registers(pf, hw);
2481
2482         if (xstats == NULL)
2483                 return 0;
2484
2485         count = 0;
2486
2487         /* Get stats from i40e_eth_stats struct */
2488         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2489                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2490                         rte_i40e_stats_strings[i].offset);
2491                 count++;
2492         }
2493
2494         /* Get individiual stats from i40e_hw_port struct */
2495         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2496                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2497                         rte_i40e_hw_port_strings[i].offset);
2498                 count++;
2499         }
2500
2501         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2502                 for (prio = 0; prio < 8; prio++) {
2503                         xstats[count].value =
2504                                 *(uint64_t *)(((char *)hw_stats) +
2505                                 rte_i40e_rxq_prio_strings[i].offset +
2506                                 (sizeof(uint64_t) * prio));
2507                         count++;
2508                 }
2509         }
2510
2511         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2512                 for (prio = 0; prio < 8; prio++) {
2513                         xstats[count].value =
2514                                 *(uint64_t *)(((char *)hw_stats) +
2515                                 rte_i40e_txq_prio_strings[i].offset +
2516                                 (sizeof(uint64_t) * prio));
2517                         count++;
2518                 }
2519         }
2520
2521         return count;
2522 }
2523
2524 static int
2525 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2526                                  __rte_unused uint16_t queue_id,
2527                                  __rte_unused uint8_t stat_idx,
2528                                  __rte_unused uint8_t is_rx)
2529 {
2530         PMD_INIT_FUNC_TRACE();
2531
2532         return -ENOSYS;
2533 }
2534
2535 static void
2536 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2537 {
2538         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2540         struct i40e_vsi *vsi = pf->main_vsi;
2541
2542         dev_info->max_rx_queues = vsi->nb_qps;
2543         dev_info->max_tx_queues = vsi->nb_qps;
2544         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2545         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2546         dev_info->max_mac_addrs = vsi->max_macaddrs;
2547         dev_info->max_vfs = dev->pci_dev->max_vfs;
2548         dev_info->rx_offload_capa =
2549                 DEV_RX_OFFLOAD_VLAN_STRIP |
2550                 DEV_RX_OFFLOAD_QINQ_STRIP |
2551                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2552                 DEV_RX_OFFLOAD_UDP_CKSUM |
2553                 DEV_RX_OFFLOAD_TCP_CKSUM;
2554         dev_info->tx_offload_capa =
2555                 DEV_TX_OFFLOAD_VLAN_INSERT |
2556                 DEV_TX_OFFLOAD_QINQ_INSERT |
2557                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2558                 DEV_TX_OFFLOAD_UDP_CKSUM |
2559                 DEV_TX_OFFLOAD_TCP_CKSUM |
2560                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2561                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2562                 DEV_TX_OFFLOAD_TCP_TSO;
2563         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2564                                                 sizeof(uint32_t);
2565         dev_info->reta_size = pf->hash_lut_size;
2566         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2567
2568         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2569                 .rx_thresh = {
2570                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2571                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2572                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2573                 },
2574                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2575                 .rx_drop_en = 0,
2576         };
2577
2578         dev_info->default_txconf = (struct rte_eth_txconf) {
2579                 .tx_thresh = {
2580                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2581                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2582                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2583                 },
2584                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2585                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2586                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2587                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2588         };
2589
2590         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2591                 .nb_max = I40E_MAX_RING_DESC,
2592                 .nb_min = I40E_MIN_RING_DESC,
2593                 .nb_align = I40E_ALIGN_RING_DESC,
2594         };
2595
2596         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2597                 .nb_max = I40E_MAX_RING_DESC,
2598                 .nb_min = I40E_MIN_RING_DESC,
2599                 .nb_align = I40E_ALIGN_RING_DESC,
2600         };
2601
2602         if (pf->flags & I40E_FLAG_VMDQ) {
2603                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2604                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2605                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2606                                                 pf->max_nb_vmdq_vsi;
2607                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2608                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2609                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2610         }
2611
2612         if (i40e_is_40G_device(hw->device_id))
2613                 /* For XL710 */
2614                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2615         else
2616                 /* For X710 */
2617                 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2618 }
2619
2620 static int
2621 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2622 {
2623         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2624         struct i40e_vsi *vsi = pf->main_vsi;
2625         PMD_INIT_FUNC_TRACE();
2626
2627         if (on)
2628                 return i40e_vsi_add_vlan(vsi, vlan_id);
2629         else
2630                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2631 }
2632
2633 static int
2634 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2635                    enum rte_vlan_type vlan_type,
2636                    uint16_t tpid)
2637 {
2638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639         uint64_t reg_r = 0, reg_w = 0;
2640         uint16_t reg_id = 0;
2641         int ret = 0;
2642         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2643
2644         switch (vlan_type) {
2645         case ETH_VLAN_TYPE_OUTER:
2646                 if (qinq)
2647                         reg_id = 2;
2648                 else
2649                         reg_id = 3;
2650                 break;
2651         case ETH_VLAN_TYPE_INNER:
2652                 if (qinq)
2653                         reg_id = 3;
2654                 else {
2655                         ret = -EINVAL;
2656                         PMD_DRV_LOG(ERR,
2657                                 "Unsupported vlan type in single vlan.\n");
2658                         return ret;
2659                 }
2660                 break;
2661         default:
2662                 ret = -EINVAL;
2663                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2664                 return ret;
2665         }
2666         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2667                                           &reg_r, NULL);
2668         if (ret != I40E_SUCCESS) {
2669                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2670                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2671                 ret = -EIO;
2672                 return ret;
2673         }
2674         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2675                     "0x%08"PRIx64"", reg_id, reg_r);
2676
2677         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2678         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2679         if (reg_r == reg_w) {
2680                 ret = 0;
2681                 PMD_DRV_LOG(DEBUG, "No need to write");
2682                 return ret;
2683         }
2684
2685         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2686                                            reg_w, NULL);
2687         if (ret != I40E_SUCCESS) {
2688                 ret = -EIO;
2689                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2690                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2691                 return ret;
2692         }
2693         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2694                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2695
2696         return ret;
2697 }
2698
2699 static void
2700 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2701 {
2702         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2703         struct i40e_vsi *vsi = pf->main_vsi;
2704
2705         if (mask & ETH_VLAN_FILTER_MASK) {
2706                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2707                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2708                 else
2709                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2710         }
2711
2712         if (mask & ETH_VLAN_STRIP_MASK) {
2713                 /* Enable or disable VLAN stripping */
2714                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2715                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2716                 else
2717                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2718         }
2719
2720         if (mask & ETH_VLAN_EXTEND_MASK) {
2721                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2722                         i40e_vsi_config_double_vlan(vsi, TRUE);
2723                         /* Set global registers with default ether type value */
2724                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2725                                            ETHER_TYPE_VLAN);
2726                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2727                                            ETHER_TYPE_VLAN);
2728                 }
2729                 else
2730                         i40e_vsi_config_double_vlan(vsi, FALSE);
2731         }
2732 }
2733
2734 static void
2735 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2736                           __rte_unused uint16_t queue,
2737                           __rte_unused int on)
2738 {
2739         PMD_INIT_FUNC_TRACE();
2740 }
2741
2742 static int
2743 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2744 {
2745         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2746         struct i40e_vsi *vsi = pf->main_vsi;
2747         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2748         struct i40e_vsi_vlan_pvid_info info;
2749
2750         memset(&info, 0, sizeof(info));
2751         info.on = on;
2752         if (info.on)
2753                 info.config.pvid = pvid;
2754         else {
2755                 info.config.reject.tagged =
2756                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2757                 info.config.reject.untagged =
2758                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2759         }
2760
2761         return i40e_vsi_vlan_pvid_set(vsi, &info);
2762 }
2763
2764 static int
2765 i40e_dev_led_on(struct rte_eth_dev *dev)
2766 {
2767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768         uint32_t mode = i40e_led_get(hw);
2769
2770         if (mode == 0)
2771                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2772
2773         return 0;
2774 }
2775
2776 static int
2777 i40e_dev_led_off(struct rte_eth_dev *dev)
2778 {
2779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2780         uint32_t mode = i40e_led_get(hw);
2781
2782         if (mode != 0)
2783                 i40e_led_set(hw, 0, false);
2784
2785         return 0;
2786 }
2787
2788 static int
2789 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2790 {
2791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2793
2794         fc_conf->pause_time = pf->fc_conf.pause_time;
2795         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2796         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2797
2798          /* Return current mode according to actual setting*/
2799         switch (hw->fc.current_mode) {
2800         case I40E_FC_FULL:
2801                 fc_conf->mode = RTE_FC_FULL;
2802                 break;
2803         case I40E_FC_TX_PAUSE:
2804                 fc_conf->mode = RTE_FC_TX_PAUSE;
2805                 break;
2806         case I40E_FC_RX_PAUSE:
2807                 fc_conf->mode = RTE_FC_RX_PAUSE;
2808                 break;
2809         case I40E_FC_NONE:
2810         default:
2811                 fc_conf->mode = RTE_FC_NONE;
2812         };
2813
2814         return 0;
2815 }
2816
2817 static int
2818 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2819 {
2820         uint32_t mflcn_reg, fctrl_reg, reg;
2821         uint32_t max_high_water;
2822         uint8_t i, aq_failure;
2823         int err;
2824         struct i40e_hw *hw;
2825         struct i40e_pf *pf;
2826         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2827                 [RTE_FC_NONE] = I40E_FC_NONE,
2828                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2829                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2830                 [RTE_FC_FULL] = I40E_FC_FULL
2831         };
2832
2833         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2834
2835         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2836         if ((fc_conf->high_water > max_high_water) ||
2837                         (fc_conf->high_water < fc_conf->low_water)) {
2838                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2839                         "High_water must <= %d.", max_high_water);
2840                 return -EINVAL;
2841         }
2842
2843         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2845         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2846
2847         pf->fc_conf.pause_time = fc_conf->pause_time;
2848         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2849         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2850
2851         PMD_INIT_FUNC_TRACE();
2852
2853         /* All the link flow control related enable/disable register
2854          * configuration is handle by the F/W
2855          */
2856         err = i40e_set_fc(hw, &aq_failure, true);
2857         if (err < 0)
2858                 return -ENOSYS;
2859
2860         if (i40e_is_40G_device(hw->device_id)) {
2861                 /* Configure flow control refresh threshold,
2862                  * the value for stat_tx_pause_refresh_timer[8]
2863                  * is used for global pause operation.
2864                  */
2865
2866                 I40E_WRITE_REG(hw,
2867                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2868                                pf->fc_conf.pause_time);
2869
2870                 /* configure the timer value included in transmitted pause
2871                  * frame,
2872                  * the value for stat_tx_pause_quanta[8] is used for global
2873                  * pause operation
2874                  */
2875                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2876                                pf->fc_conf.pause_time);
2877
2878                 fctrl_reg = I40E_READ_REG(hw,
2879                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2880
2881                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2882                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2883                 else
2884                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2885
2886                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2887                                fctrl_reg);
2888         } else {
2889                 /* Configure pause time (2 TCs per register) */
2890                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2891                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2892                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2893
2894                 /* Configure flow control refresh threshold value */
2895                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2896                                pf->fc_conf.pause_time / 2);
2897
2898                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2899
2900                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2901                  *depending on configuration
2902                  */
2903                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2904                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2905                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2906                 } else {
2907                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2908                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2909                 }
2910
2911                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2912         }
2913
2914         /* config the water marker both based on the packets and bytes */
2915         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2916                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2917                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2918         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2919                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2920                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2921         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2922                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2923                        << I40E_KILOSHIFT);
2924         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2925                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2926                        << I40E_KILOSHIFT);
2927
2928         I40E_WRITE_FLUSH(hw);
2929
2930         return 0;
2931 }
2932
2933 static int
2934 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2935                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2936 {
2937         PMD_INIT_FUNC_TRACE();
2938
2939         return -ENOSYS;
2940 }
2941
2942 /* Add a MAC address, and update filters */
2943 static void
2944 i40e_macaddr_add(struct rte_eth_dev *dev,
2945                  struct ether_addr *mac_addr,
2946                  __rte_unused uint32_t index,
2947                  uint32_t pool)
2948 {
2949         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2950         struct i40e_mac_filter_info mac_filter;
2951         struct i40e_vsi *vsi;
2952         int ret;
2953
2954         /* If VMDQ not enabled or configured, return */
2955         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2956                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2957                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2958                         pool);
2959                 return;
2960         }
2961
2962         if (pool > pf->nb_cfg_vmdq_vsi) {
2963                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2964                                 pool, pf->nb_cfg_vmdq_vsi);
2965                 return;
2966         }
2967
2968         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2969         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2970                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2971         else
2972                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2973
2974         if (pool == 0)
2975                 vsi = pf->main_vsi;
2976         else
2977                 vsi = pf->vmdq[pool - 1].vsi;
2978
2979         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2980         if (ret != I40E_SUCCESS) {
2981                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2982                 return;
2983         }
2984 }
2985
2986 /* Remove a MAC address, and update filters */
2987 static void
2988 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2989 {
2990         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2991         struct i40e_vsi *vsi;
2992         struct rte_eth_dev_data *data = dev->data;
2993         struct ether_addr *macaddr;
2994         int ret;
2995         uint32_t i;
2996         uint64_t pool_sel;
2997
2998         macaddr = &(data->mac_addrs[index]);
2999
3000         pool_sel = dev->data->mac_pool_sel[index];
3001
3002         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3003                 if (pool_sel & (1ULL << i)) {
3004                         if (i == 0)
3005                                 vsi = pf->main_vsi;
3006                         else {
3007                                 /* No VMDQ pool enabled or configured */
3008                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
3009                                         (i > pf->nb_cfg_vmdq_vsi)) {
3010                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3011                                                         "/configured");
3012                                         return;
3013                                 }
3014                                 vsi = pf->vmdq[i - 1].vsi;
3015                         }
3016                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3017
3018                         if (ret) {
3019                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3020                                 return;
3021                         }
3022                 }
3023         }
3024 }
3025
3026 /* Set perfect match or hash match of MAC and VLAN for a VF */
3027 static int
3028 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3029                  struct rte_eth_mac_filter *filter,
3030                  bool add)
3031 {
3032         struct i40e_hw *hw;
3033         struct i40e_mac_filter_info mac_filter;
3034         struct ether_addr old_mac;
3035         struct ether_addr *new_mac;
3036         struct i40e_pf_vf *vf = NULL;
3037         uint16_t vf_id;
3038         int ret;
3039
3040         if (pf == NULL) {
3041                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3042                 return -EINVAL;
3043         }
3044         hw = I40E_PF_TO_HW(pf);
3045
3046         if (filter == NULL) {
3047                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3048                 return -EINVAL;
3049         }
3050
3051         new_mac = &filter->mac_addr;
3052
3053         if (is_zero_ether_addr(new_mac)) {
3054                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3055                 return -EINVAL;
3056         }
3057
3058         vf_id = filter->dst_id;
3059
3060         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3061                 PMD_DRV_LOG(ERR, "Invalid argument.");
3062                 return -EINVAL;
3063         }
3064         vf = &pf->vfs[vf_id];
3065
3066         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3067                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3068                 return -EINVAL;
3069         }
3070
3071         if (add) {
3072                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3073                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3074                                 ETHER_ADDR_LEN);
3075                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3076                                  ETHER_ADDR_LEN);
3077
3078                 mac_filter.filter_type = filter->filter_type;
3079                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3080                 if (ret != I40E_SUCCESS) {
3081                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3082                         return -1;
3083                 }
3084                 ether_addr_copy(new_mac, &pf->dev_addr);
3085         } else {
3086                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3087                                 ETHER_ADDR_LEN);
3088                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3089                 if (ret != I40E_SUCCESS) {
3090                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3091                         return -1;
3092                 }
3093
3094                 /* Clear device address as it has been removed */
3095                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3096                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3097         }
3098
3099         return 0;
3100 }
3101
3102 /* MAC filter handle */
3103 static int
3104 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3105                 void *arg)
3106 {
3107         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3108         struct rte_eth_mac_filter *filter;
3109         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3110         int ret = I40E_NOT_SUPPORTED;
3111
3112         filter = (struct rte_eth_mac_filter *)(arg);
3113
3114         switch (filter_op) {
3115         case RTE_ETH_FILTER_NOP:
3116                 ret = I40E_SUCCESS;
3117                 break;
3118         case RTE_ETH_FILTER_ADD:
3119                 i40e_pf_disable_irq0(hw);
3120                 if (filter->is_vf)
3121                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3122                 i40e_pf_enable_irq0(hw);
3123                 break;
3124         case RTE_ETH_FILTER_DELETE:
3125                 i40e_pf_disable_irq0(hw);
3126                 if (filter->is_vf)
3127                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3128                 i40e_pf_enable_irq0(hw);
3129                 break;
3130         default:
3131                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3132                 ret = I40E_ERR_PARAM;
3133                 break;
3134         }
3135
3136         return ret;
3137 }
3138
3139 static int
3140 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3141 {
3142         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3143         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3144         int ret;
3145
3146         if (!lut)
3147                 return -EINVAL;
3148
3149         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3150                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3151                                           lut, lut_size);
3152                 if (ret) {
3153                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3154                         return ret;
3155                 }
3156         } else {
3157                 uint32_t *lut_dw = (uint32_t *)lut;
3158                 uint16_t i, lut_size_dw = lut_size / 4;
3159
3160                 for (i = 0; i < lut_size_dw; i++)
3161                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3162         }
3163
3164         return 0;
3165 }
3166
3167 static int
3168 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3169 {
3170         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3171         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3172         int ret;
3173
3174         if (!vsi || !lut)
3175                 return -EINVAL;
3176
3177         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3178                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3179                                           lut, lut_size);
3180                 if (ret) {
3181                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3182                         return ret;
3183                 }
3184         } else {
3185                 uint32_t *lut_dw = (uint32_t *)lut;
3186                 uint16_t i, lut_size_dw = lut_size / 4;
3187
3188                 for (i = 0; i < lut_size_dw; i++)
3189                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3190                 I40E_WRITE_FLUSH(hw);
3191         }
3192
3193         return 0;
3194 }
3195
3196 static int
3197 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3198                          struct rte_eth_rss_reta_entry64 *reta_conf,
3199                          uint16_t reta_size)
3200 {
3201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3202         uint16_t i, lut_size = pf->hash_lut_size;
3203         uint16_t idx, shift;
3204         uint8_t *lut;
3205         int ret;
3206
3207         if (reta_size != lut_size ||
3208                 reta_size > ETH_RSS_RETA_SIZE_512) {
3209                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3210                         "(%d) doesn't match the number hardware can supported "
3211                                         "(%d)\n", reta_size, lut_size);
3212                 return -EINVAL;
3213         }
3214
3215         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3216         if (!lut) {
3217                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3218                 return -ENOMEM;
3219         }
3220         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3221         if (ret)
3222                 goto out;
3223         for (i = 0; i < reta_size; i++) {
3224                 idx = i / RTE_RETA_GROUP_SIZE;
3225                 shift = i % RTE_RETA_GROUP_SIZE;
3226                 if (reta_conf[idx].mask & (1ULL << shift))
3227                         lut[i] = reta_conf[idx].reta[shift];
3228         }
3229         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3230
3231 out:
3232         rte_free(lut);
3233
3234         return ret;
3235 }
3236
3237 static int
3238 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3239                         struct rte_eth_rss_reta_entry64 *reta_conf,
3240                         uint16_t reta_size)
3241 {
3242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3243         uint16_t i, lut_size = pf->hash_lut_size;
3244         uint16_t idx, shift;
3245         uint8_t *lut;
3246         int ret;
3247
3248         if (reta_size != lut_size ||
3249                 reta_size > ETH_RSS_RETA_SIZE_512) {
3250                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3251                         "(%d) doesn't match the number hardware can supported "
3252                                         "(%d)\n", reta_size, lut_size);
3253                 return -EINVAL;
3254         }
3255
3256         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3257         if (!lut) {
3258                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3259                 return -ENOMEM;
3260         }
3261
3262         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3263         if (ret)
3264                 goto out;
3265         for (i = 0; i < reta_size; i++) {
3266                 idx = i / RTE_RETA_GROUP_SIZE;
3267                 shift = i % RTE_RETA_GROUP_SIZE;
3268                 if (reta_conf[idx].mask & (1ULL << shift))
3269                         reta_conf[idx].reta[shift] = lut[i];
3270         }
3271
3272 out:
3273         rte_free(lut);
3274
3275         return ret;
3276 }
3277
3278 /**
3279  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3280  * @hw:   pointer to the HW structure
3281  * @mem:  pointer to mem struct to fill out
3282  * @size: size of memory requested
3283  * @alignment: what to align the allocation to
3284  **/
3285 enum i40e_status_code
3286 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3287                         struct i40e_dma_mem *mem,
3288                         u64 size,
3289                         u32 alignment)
3290 {
3291         const struct rte_memzone *mz = NULL;
3292         char z_name[RTE_MEMZONE_NAMESIZE];
3293
3294         if (!mem)
3295                 return I40E_ERR_PARAM;
3296
3297         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3298         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3299                                          alignment, RTE_PGSIZE_2M);
3300         if (!mz)
3301                 return I40E_ERR_NO_MEMORY;
3302
3303         mem->size = size;
3304         mem->va = mz->addr;
3305         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3306         mem->zone = (const void *)mz;
3307         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3308                     "%"PRIu64, mz->name, mem->pa);
3309
3310         return I40E_SUCCESS;
3311 }
3312
3313 /**
3314  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3315  * @hw:   pointer to the HW structure
3316  * @mem:  ptr to mem struct to free
3317  **/
3318 enum i40e_status_code
3319 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3320                     struct i40e_dma_mem *mem)
3321 {
3322         if (!mem)
3323                 return I40E_ERR_PARAM;
3324
3325         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3326                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3327                     mem->pa);
3328         rte_memzone_free((const struct rte_memzone *)mem->zone);
3329         mem->zone = NULL;
3330         mem->va = NULL;
3331         mem->pa = (u64)0;
3332
3333         return I40E_SUCCESS;
3334 }
3335
3336 /**
3337  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3338  * @hw:   pointer to the HW structure
3339  * @mem:  pointer to mem struct to fill out
3340  * @size: size of memory requested
3341  **/
3342 enum i40e_status_code
3343 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3344                          struct i40e_virt_mem *mem,
3345                          u32 size)
3346 {
3347         if (!mem)
3348                 return I40E_ERR_PARAM;
3349
3350         mem->size = size;
3351         mem->va = rte_zmalloc("i40e", size, 0);
3352
3353         if (mem->va)
3354                 return I40E_SUCCESS;
3355         else
3356                 return I40E_ERR_NO_MEMORY;
3357 }
3358
3359 /**
3360  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3361  * @hw:   pointer to the HW structure
3362  * @mem:  pointer to mem struct to free
3363  **/
3364 enum i40e_status_code
3365 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3366                      struct i40e_virt_mem *mem)
3367 {
3368         if (!mem)
3369                 return I40E_ERR_PARAM;
3370
3371         rte_free(mem->va);
3372         mem->va = NULL;
3373
3374         return I40E_SUCCESS;
3375 }
3376
3377 void
3378 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3379 {
3380         rte_spinlock_init(&sp->spinlock);
3381 }
3382
3383 void
3384 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3385 {
3386         rte_spinlock_lock(&sp->spinlock);
3387 }
3388
3389 void
3390 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3391 {
3392         rte_spinlock_unlock(&sp->spinlock);
3393 }
3394
3395 void
3396 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3397 {
3398         return;
3399 }
3400
3401 /**
3402  * Get the hardware capabilities, which will be parsed
3403  * and saved into struct i40e_hw.
3404  */
3405 static int
3406 i40e_get_cap(struct i40e_hw *hw)
3407 {
3408         struct i40e_aqc_list_capabilities_element_resp *buf;
3409         uint16_t len, size = 0;
3410         int ret;
3411
3412         /* Calculate a huge enough buff for saving response data temporarily */
3413         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3414                                                 I40E_MAX_CAP_ELE_NUM;
3415         buf = rte_zmalloc("i40e", len, 0);
3416         if (!buf) {
3417                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3418                 return I40E_ERR_NO_MEMORY;
3419         }
3420
3421         /* Get, parse the capabilities and save it to hw */
3422         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3423                         i40e_aqc_opc_list_func_capabilities, NULL);
3424         if (ret != I40E_SUCCESS)
3425                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3426
3427         /* Free the temporary buffer after being used */
3428         rte_free(buf);
3429
3430         return ret;
3431 }
3432
3433 static int
3434 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3435 {
3436         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3437         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3438         uint16_t qp_count = 0, vsi_count = 0;
3439
3440         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3441                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3442                 return -EINVAL;
3443         }
3444         /* Add the parameter init for LFC */
3445         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3446         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3447         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3448
3449         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3450         pf->max_num_vsi = hw->func_caps.num_vsis;
3451         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3452         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3453         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3454
3455         /* FDir queue/VSI allocation */
3456         pf->fdir_qp_offset = 0;
3457         if (hw->func_caps.fd) {
3458                 pf->flags |= I40E_FLAG_FDIR;
3459                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3460         } else {
3461                 pf->fdir_nb_qps = 0;
3462         }
3463         qp_count += pf->fdir_nb_qps;
3464         vsi_count += 1;
3465
3466         /* LAN queue/VSI allocation */
3467         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3468         if (!hw->func_caps.rss) {
3469                 pf->lan_nb_qps = 1;
3470         } else {
3471                 pf->flags |= I40E_FLAG_RSS;
3472                 if (hw->mac.type == I40E_MAC_X722)
3473                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3474                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3475         }
3476         qp_count += pf->lan_nb_qps;
3477         vsi_count += 1;
3478
3479         /* VF queue/VSI allocation */
3480         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3481         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3482                 pf->flags |= I40E_FLAG_SRIOV;
3483                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3484                 pf->vf_num = dev->pci_dev->max_vfs;
3485                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3486                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3487                             pf->vf_nb_qps * pf->vf_num);
3488         } else {
3489                 pf->vf_nb_qps = 0;
3490                 pf->vf_num = 0;
3491         }
3492         qp_count += pf->vf_nb_qps * pf->vf_num;
3493         vsi_count += pf->vf_num;
3494
3495         /* VMDq queue/VSI allocation */
3496         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3497         pf->vmdq_nb_qps = 0;
3498         pf->max_nb_vmdq_vsi = 0;
3499         if (hw->func_caps.vmdq) {
3500                 if (qp_count < hw->func_caps.num_tx_qp &&
3501                         vsi_count < hw->func_caps.num_vsis) {
3502                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3503                                 qp_count) / pf->vmdq_nb_qp_max;
3504
3505                         /* Limit the maximum number of VMDq vsi to the maximum
3506                          * ethdev can support
3507                          */
3508                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3509                                 hw->func_caps.num_vsis - vsi_count);
3510                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3511                                 ETH_64_POOLS);
3512                         if (pf->max_nb_vmdq_vsi) {
3513                                 pf->flags |= I40E_FLAG_VMDQ;
3514                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3515                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3516                                             "per VMDQ VSI, in total %u queues",
3517                                             pf->max_nb_vmdq_vsi,
3518                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3519                                             pf->max_nb_vmdq_vsi);
3520                         } else {
3521                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3522                                             "VMDq");
3523                         }
3524                 } else {
3525                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3526                 }
3527         }
3528         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3529         vsi_count += pf->max_nb_vmdq_vsi;
3530
3531         if (hw->func_caps.dcb)
3532                 pf->flags |= I40E_FLAG_DCB;
3533
3534         if (qp_count > hw->func_caps.num_tx_qp) {
3535                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3536                             "the hardware maximum %u", qp_count,
3537                             hw->func_caps.num_tx_qp);
3538                 return -EINVAL;
3539         }
3540         if (vsi_count > hw->func_caps.num_vsis) {
3541                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3542                             "the hardware maximum %u", vsi_count,
3543                             hw->func_caps.num_vsis);
3544                 return -EINVAL;
3545         }
3546
3547         return 0;
3548 }
3549
3550 static int
3551 i40e_pf_get_switch_config(struct i40e_pf *pf)
3552 {
3553         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3554         struct i40e_aqc_get_switch_config_resp *switch_config;
3555         struct i40e_aqc_switch_config_element_resp *element;
3556         uint16_t start_seid = 0, num_reported;
3557         int ret;
3558
3559         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3560                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3561         if (!switch_config) {
3562                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3563                 return -ENOMEM;
3564         }
3565
3566         /* Get the switch configurations */
3567         ret = i40e_aq_get_switch_config(hw, switch_config,
3568                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3569         if (ret != I40E_SUCCESS) {
3570                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3571                 goto fail;
3572         }
3573         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3574         if (num_reported != 1) { /* The number should be 1 */
3575                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3576                 goto fail;
3577         }
3578
3579         /* Parse the switch configuration elements */
3580         element = &(switch_config->element[0]);
3581         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3582                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3583                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3584         } else
3585                 PMD_DRV_LOG(INFO, "Unknown element type");
3586
3587 fail:
3588         rte_free(switch_config);
3589
3590         return ret;
3591 }
3592
3593 static int
3594 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3595                         uint32_t num)
3596 {
3597         struct pool_entry *entry;
3598
3599         if (pool == NULL || num == 0)
3600                 return -EINVAL;
3601
3602         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3603         if (entry == NULL) {
3604                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3605                 return -ENOMEM;
3606         }
3607
3608         /* queue heap initialize */
3609         pool->num_free = num;
3610         pool->num_alloc = 0;
3611         pool->base = base;
3612         LIST_INIT(&pool->alloc_list);
3613         LIST_INIT(&pool->free_list);
3614
3615         /* Initialize element  */
3616         entry->base = 0;
3617         entry->len = num;
3618
3619         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3620         return 0;
3621 }
3622
3623 static void
3624 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3625 {
3626         struct pool_entry *entry, *next_entry;
3627
3628         if (pool == NULL)
3629                 return;
3630
3631         for (entry = LIST_FIRST(&pool->alloc_list);
3632                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3633                         entry = next_entry) {
3634                 LIST_REMOVE(entry, next);
3635                 rte_free(entry);
3636         }
3637
3638         for (entry = LIST_FIRST(&pool->free_list);
3639                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3640                         entry = next_entry) {
3641                 LIST_REMOVE(entry, next);
3642                 rte_free(entry);
3643         }
3644
3645         pool->num_free = 0;
3646         pool->num_alloc = 0;
3647         pool->base = 0;
3648         LIST_INIT(&pool->alloc_list);
3649         LIST_INIT(&pool->free_list);
3650 }
3651
3652 static int
3653 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3654                        uint32_t base)
3655 {
3656         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3657         uint32_t pool_offset;
3658         int insert;
3659
3660         if (pool == NULL) {
3661                 PMD_DRV_LOG(ERR, "Invalid parameter");
3662                 return -EINVAL;
3663         }
3664
3665         pool_offset = base - pool->base;
3666         /* Lookup in alloc list */
3667         LIST_FOREACH(entry, &pool->alloc_list, next) {
3668                 if (entry->base == pool_offset) {
3669                         valid_entry = entry;
3670                         LIST_REMOVE(entry, next);
3671                         break;
3672                 }
3673         }
3674
3675         /* Not find, return */
3676         if (valid_entry == NULL) {
3677                 PMD_DRV_LOG(ERR, "Failed to find entry");
3678                 return -EINVAL;
3679         }
3680
3681         /**
3682          * Found it, move it to free list  and try to merge.
3683          * In order to make merge easier, always sort it by qbase.
3684          * Find adjacent prev and last entries.
3685          */
3686         prev = next = NULL;
3687         LIST_FOREACH(entry, &pool->free_list, next) {
3688                 if (entry->base > valid_entry->base) {
3689                         next = entry;
3690                         break;
3691                 }
3692                 prev = entry;
3693         }
3694
3695         insert = 0;
3696         /* Try to merge with next one*/
3697         if (next != NULL) {
3698                 /* Merge with next one */
3699                 if (valid_entry->base + valid_entry->len == next->base) {
3700                         next->base = valid_entry->base;
3701                         next->len += valid_entry->len;
3702                         rte_free(valid_entry);
3703                         valid_entry = next;
3704                         insert = 1;
3705                 }
3706         }
3707
3708         if (prev != NULL) {
3709                 /* Merge with previous one */
3710                 if (prev->base + prev->len == valid_entry->base) {
3711                         prev->len += valid_entry->len;
3712                         /* If it merge with next one, remove next node */
3713                         if (insert == 1) {
3714                                 LIST_REMOVE(valid_entry, next);
3715                                 rte_free(valid_entry);
3716                         } else {
3717                                 rte_free(valid_entry);
3718                                 insert = 1;
3719                         }
3720                 }
3721         }
3722
3723         /* Not find any entry to merge, insert */
3724         if (insert == 0) {
3725                 if (prev != NULL)
3726                         LIST_INSERT_AFTER(prev, valid_entry, next);
3727                 else if (next != NULL)
3728                         LIST_INSERT_BEFORE(next, valid_entry, next);
3729                 else /* It's empty list, insert to head */
3730                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3731         }
3732
3733         pool->num_free += valid_entry->len;
3734         pool->num_alloc -= valid_entry->len;
3735
3736         return 0;
3737 }
3738
3739 static int
3740 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3741                        uint16_t num)
3742 {
3743         struct pool_entry *entry, *valid_entry;
3744
3745         if (pool == NULL || num == 0) {
3746                 PMD_DRV_LOG(ERR, "Invalid parameter");
3747                 return -EINVAL;
3748         }
3749
3750         if (pool->num_free < num) {
3751                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3752                             num, pool->num_free);
3753                 return -ENOMEM;
3754         }
3755
3756         valid_entry = NULL;
3757         /* Lookup  in free list and find most fit one */
3758         LIST_FOREACH(entry, &pool->free_list, next) {
3759                 if (entry->len >= num) {
3760                         /* Find best one */
3761                         if (entry->len == num) {
3762                                 valid_entry = entry;
3763                                 break;
3764                         }
3765                         if (valid_entry == NULL || valid_entry->len > entry->len)
3766                                 valid_entry = entry;
3767                 }
3768         }
3769
3770         /* Not find one to satisfy the request, return */
3771         if (valid_entry == NULL) {
3772                 PMD_DRV_LOG(ERR, "No valid entry found");
3773                 return -ENOMEM;
3774         }
3775         /**
3776          * The entry have equal queue number as requested,
3777          * remove it from alloc_list.
3778          */
3779         if (valid_entry->len == num) {
3780                 LIST_REMOVE(valid_entry, next);
3781         } else {
3782                 /**
3783                  * The entry have more numbers than requested,
3784                  * create a new entry for alloc_list and minus its
3785                  * queue base and number in free_list.
3786                  */
3787                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3788                 if (entry == NULL) {
3789                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3790                                     "resource pool");
3791                         return -ENOMEM;
3792                 }
3793                 entry->base = valid_entry->base;
3794                 entry->len = num;
3795                 valid_entry->base += num;
3796                 valid_entry->len -= num;
3797                 valid_entry = entry;
3798         }
3799
3800         /* Insert it into alloc list, not sorted */
3801         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3802
3803         pool->num_free -= valid_entry->len;
3804         pool->num_alloc += valid_entry->len;
3805
3806         return valid_entry->base + pool->base;
3807 }
3808
3809 /**
3810  * bitmap_is_subset - Check whether src2 is subset of src1
3811  **/
3812 static inline int
3813 bitmap_is_subset(uint8_t src1, uint8_t src2)
3814 {
3815         return !((src1 ^ src2) & src2);
3816 }
3817
3818 static enum i40e_status_code
3819 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3820 {
3821         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3822
3823         /* If DCB is not supported, only default TC is supported */
3824         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3825                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3826                 return I40E_NOT_SUPPORTED;
3827         }
3828
3829         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3830                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3831                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3832                             enabled_tcmap);
3833                 return I40E_NOT_SUPPORTED;
3834         }
3835         return I40E_SUCCESS;
3836 }
3837
3838 int
3839 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3840                                 struct i40e_vsi_vlan_pvid_info *info)
3841 {
3842         struct i40e_hw *hw;
3843         struct i40e_vsi_context ctxt;
3844         uint8_t vlan_flags = 0;
3845         int ret;
3846
3847         if (vsi == NULL || info == NULL) {
3848                 PMD_DRV_LOG(ERR, "invalid parameters");
3849                 return I40E_ERR_PARAM;
3850         }
3851
3852         if (info->on) {
3853                 vsi->info.pvid = info->config.pvid;
3854                 /**
3855                  * If insert pvid is enabled, only tagged pkts are
3856                  * allowed to be sent out.
3857                  */
3858                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3859                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3860         } else {
3861                 vsi->info.pvid = 0;
3862                 if (info->config.reject.tagged == 0)
3863                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3864
3865                 if (info->config.reject.untagged == 0)
3866                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3867         }
3868         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3869                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3870         vsi->info.port_vlan_flags |= vlan_flags;
3871         vsi->info.valid_sections =
3872                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3873         memset(&ctxt, 0, sizeof(ctxt));
3874         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3875         ctxt.seid = vsi->seid;
3876
3877         hw = I40E_VSI_TO_HW(vsi);
3878         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3879         if (ret != I40E_SUCCESS)
3880                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3881
3882         return ret;
3883 }
3884
3885 static int
3886 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3887 {
3888         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3889         int i, ret;
3890         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3891
3892         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3893         if (ret != I40E_SUCCESS)
3894                 return ret;
3895
3896         if (!vsi->seid) {
3897                 PMD_DRV_LOG(ERR, "seid not valid");
3898                 return -EINVAL;
3899         }
3900
3901         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3902         tc_bw_data.tc_valid_bits = enabled_tcmap;
3903         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3904                 tc_bw_data.tc_bw_credits[i] =
3905                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3906
3907         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3908         if (ret != I40E_SUCCESS) {
3909                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3910                 return ret;
3911         }
3912
3913         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3914                                         sizeof(vsi->info.qs_handle));
3915         return I40E_SUCCESS;
3916 }
3917
3918 static enum i40e_status_code
3919 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3920                                  struct i40e_aqc_vsi_properties_data *info,
3921                                  uint8_t enabled_tcmap)
3922 {
3923         enum i40e_status_code ret;
3924         int i, total_tc = 0;
3925         uint16_t qpnum_per_tc, bsf, qp_idx;
3926
3927         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3928         if (ret != I40E_SUCCESS)
3929                 return ret;
3930
3931         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3932                 if (enabled_tcmap & (1 << i))
3933                         total_tc++;
3934         vsi->enabled_tc = enabled_tcmap;
3935
3936         /* Number of queues per enabled TC */
3937         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3938         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3939         bsf = rte_bsf32(qpnum_per_tc);
3940
3941         /* Adjust the queue number to actual queues that can be applied */
3942         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3943                 vsi->nb_qps = qpnum_per_tc * total_tc;
3944
3945         /**
3946          * Configure TC and queue mapping parameters, for enabled TC,
3947          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3948          * default queue will serve it.
3949          */
3950         qp_idx = 0;
3951         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3952                 if (vsi->enabled_tc & (1 << i)) {
3953                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3954                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3955                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3956                         qp_idx += qpnum_per_tc;
3957                 } else
3958                         info->tc_mapping[i] = 0;
3959         }
3960
3961         /* Associate queue number with VSI */
3962         if (vsi->type == I40E_VSI_SRIOV) {
3963                 info->mapping_flags |=
3964                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3965                 for (i = 0; i < vsi->nb_qps; i++)
3966                         info->queue_mapping[i] =
3967                                 rte_cpu_to_le_16(vsi->base_queue + i);
3968         } else {
3969                 info->mapping_flags |=
3970                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3971                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3972         }
3973         info->valid_sections |=
3974                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3975
3976         return I40E_SUCCESS;
3977 }
3978
3979 static int
3980 i40e_veb_release(struct i40e_veb *veb)
3981 {
3982         struct i40e_vsi *vsi;
3983         struct i40e_hw *hw;
3984
3985         if (veb == NULL)
3986                 return -EINVAL;
3987
3988         if (!TAILQ_EMPTY(&veb->head)) {
3989                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3990                 return -EACCES;
3991         }
3992         /* associate_vsi field is NULL for floating VEB */
3993         if (veb->associate_vsi != NULL) {
3994                 vsi = veb->associate_vsi;
3995                 hw = I40E_VSI_TO_HW(vsi);
3996
3997                 vsi->uplink_seid = veb->uplink_seid;
3998                 vsi->veb = NULL;
3999         } else {
4000                 veb->associate_pf->main_vsi->floating_veb = NULL;
4001                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4002         }
4003
4004         i40e_aq_delete_element(hw, veb->seid, NULL);
4005         rte_free(veb);
4006         return I40E_SUCCESS;
4007 }
4008
4009 /* Setup a veb */
4010 static struct i40e_veb *
4011 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4012 {
4013         struct i40e_veb *veb;
4014         int ret;
4015         struct i40e_hw *hw;
4016
4017         if (pf == NULL) {
4018                 PMD_DRV_LOG(ERR,
4019                             "veb setup failed, associated PF shouldn't null");
4020                 return NULL;
4021         }
4022         hw = I40E_PF_TO_HW(pf);
4023
4024         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4025         if (!veb) {
4026                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4027                 goto fail;
4028         }
4029
4030         veb->associate_vsi = vsi;
4031         veb->associate_pf = pf;
4032         TAILQ_INIT(&veb->head);
4033         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4034
4035         /* create floating veb if vsi is NULL */
4036         if (vsi != NULL) {
4037                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4038                                       I40E_DEFAULT_TCMAP, false,
4039                                       &veb->seid, false, NULL);
4040         } else {
4041                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4042                                       true, &veb->seid, false, NULL);
4043         }
4044
4045         if (ret != I40E_SUCCESS) {
4046                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4047                             hw->aq.asq_last_status);
4048                 goto fail;
4049         }
4050
4051         /* get statistics index */
4052         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4053                                 &veb->stats_idx, NULL, NULL, NULL);
4054         if (ret != I40E_SUCCESS) {
4055                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4056                             hw->aq.asq_last_status);
4057                 goto fail;
4058         }
4059         /* Get VEB bandwidth, to be implemented */
4060         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4061         if (vsi)
4062                 vsi->uplink_seid = veb->seid;
4063
4064         return veb;
4065 fail:
4066         rte_free(veb);
4067         return NULL;
4068 }
4069
4070 int
4071 i40e_vsi_release(struct i40e_vsi *vsi)
4072 {
4073         struct i40e_pf *pf;
4074         struct i40e_hw *hw;
4075         struct i40e_vsi_list *vsi_list;
4076         int ret;
4077         struct i40e_mac_filter *f;
4078         uint16_t user_param = vsi->user_param;
4079
4080         if (!vsi)
4081                 return I40E_SUCCESS;
4082
4083         pf = I40E_VSI_TO_PF(vsi);
4084         hw = I40E_VSI_TO_HW(vsi);
4085
4086         /* VSI has child to attach, release child first */
4087         if (vsi->veb) {
4088                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
4089                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4090                                 return -1;
4091                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
4092                 }
4093                 i40e_veb_release(vsi->veb);
4094         }
4095
4096         if (vsi->floating_veb) {
4097                 TAILQ_FOREACH(vsi_list, &vsi->floating_veb->head, list) {
4098                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4099                                 return -1;
4100                         TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
4101                 }
4102         }
4103
4104         /* Remove all macvlan filters of the VSI */
4105         i40e_vsi_remove_all_macvlan_filter(vsi);
4106         TAILQ_FOREACH(f, &vsi->mac_list, next)
4107                 rte_free(f);
4108
4109         if (vsi->type != I40E_VSI_MAIN &&
4110             ((vsi->type != I40E_VSI_SRIOV) ||
4111             !pf->floating_veb_list[user_param])) {
4112                 /* Remove vsi from parent's sibling list */
4113                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4114                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4115                         return I40E_ERR_PARAM;
4116                 }
4117                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4118                                 &vsi->sib_vsi_list, list);
4119
4120                 /* Remove all switch element of the VSI */
4121                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4122                 if (ret != I40E_SUCCESS)
4123                         PMD_DRV_LOG(ERR, "Failed to delete element");
4124         }
4125
4126         if ((vsi->type == I40E_VSI_SRIOV) &&
4127             pf->floating_veb_list[user_param]) {
4128                 /* Remove vsi from parent's sibling list */
4129                 if (vsi->parent_vsi == NULL ||
4130                     vsi->parent_vsi->floating_veb == NULL) {
4131                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4132                         return I40E_ERR_PARAM;
4133                 }
4134                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4135                              &vsi->sib_vsi_list, list);
4136
4137                 /* Remove all switch element of the VSI */
4138                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4139                 if (ret != I40E_SUCCESS)
4140                         PMD_DRV_LOG(ERR, "Failed to delete element");
4141         }
4142
4143         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4144
4145         if (vsi->type != I40E_VSI_SRIOV)
4146                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4147         rte_free(vsi);
4148
4149         return I40E_SUCCESS;
4150 }
4151
4152 static int
4153 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4154 {
4155         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4156         struct i40e_aqc_remove_macvlan_element_data def_filter;
4157         struct i40e_mac_filter_info filter;
4158         int ret;
4159
4160         if (vsi->type != I40E_VSI_MAIN)
4161                 return I40E_ERR_CONFIG;
4162         memset(&def_filter, 0, sizeof(def_filter));
4163         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4164                                         ETH_ADDR_LEN);
4165         def_filter.vlan_tag = 0;
4166         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4167                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4168         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4169         if (ret != I40E_SUCCESS) {
4170                 struct i40e_mac_filter *f;
4171                 struct ether_addr *mac;
4172
4173                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4174                             "macvlan filter");
4175                 /* It needs to add the permanent mac into mac list */
4176                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4177                 if (f == NULL) {
4178                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4179                         return I40E_ERR_NO_MEMORY;
4180                 }
4181                 mac = &f->mac_info.mac_addr;
4182                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4183                                 ETH_ADDR_LEN);
4184                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4185                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4186                 vsi->mac_num++;
4187
4188                 return ret;
4189         }
4190         (void)rte_memcpy(&filter.mac_addr,
4191                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4192         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4193         return i40e_vsi_add_mac(vsi, &filter);
4194 }
4195
4196 /*
4197  * i40e_vsi_get_bw_config - Query VSI BW Information
4198  * @vsi: the VSI to be queried
4199  *
4200  * Returns 0 on success, negative value on failure
4201  */
4202 static enum i40e_status_code
4203 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4204 {
4205         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4206         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4207         struct i40e_hw *hw = &vsi->adapter->hw;
4208         i40e_status ret;
4209         int i;
4210         uint32_t bw_max;
4211
4212         memset(&bw_config, 0, sizeof(bw_config));
4213         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4214         if (ret != I40E_SUCCESS) {
4215                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4216                             hw->aq.asq_last_status);
4217                 return ret;
4218         }
4219
4220         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4221         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4222                                         &ets_sla_config, NULL);
4223         if (ret != I40E_SUCCESS) {
4224                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4225                             "configuration %u", hw->aq.asq_last_status);
4226                 return ret;
4227         }
4228
4229         /* store and print out BW info */
4230         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4231         vsi->bw_info.bw_max = bw_config.max_bw;
4232         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4233         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4234         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4235                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4236                      I40E_16_BIT_WIDTH);
4237         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4238                 vsi->bw_info.bw_ets_share_credits[i] =
4239                                 ets_sla_config.share_credits[i];
4240                 vsi->bw_info.bw_ets_credits[i] =
4241                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4242                 /* 4 bits per TC, 4th bit is reserved */
4243                 vsi->bw_info.bw_ets_max[i] =
4244                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4245                                   RTE_LEN2MASK(3, uint8_t));
4246                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4247                             vsi->bw_info.bw_ets_share_credits[i]);
4248                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4249                             vsi->bw_info.bw_ets_credits[i]);
4250                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4251                             vsi->bw_info.bw_ets_max[i]);
4252         }
4253
4254         return I40E_SUCCESS;
4255 }
4256
4257 /* i40e_enable_pf_lb
4258  * @pf: pointer to the pf structure
4259  *
4260  * allow loopback on pf
4261  */
4262 static inline void
4263 i40e_enable_pf_lb(struct i40e_pf *pf)
4264 {
4265         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4266         struct i40e_vsi_context ctxt;
4267         int ret;
4268
4269         /* Use the FW API if FW >= v5.0 */
4270         if (hw->aq.fw_maj_ver < 5) {
4271                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4272                 return;
4273         }
4274
4275         memset(&ctxt, 0, sizeof(ctxt));
4276         ctxt.seid = pf->main_vsi_seid;
4277         ctxt.pf_num = hw->pf_id;
4278         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4279         if (ret) {
4280                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4281                             ret, hw->aq.asq_last_status);
4282                 return;
4283         }
4284         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4285         ctxt.info.valid_sections =
4286                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4287         ctxt.info.switch_id |=
4288                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4289
4290         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4291         if (ret)
4292                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4293                             hw->aq.asq_last_status);
4294 }
4295
4296 /* Setup a VSI */
4297 struct i40e_vsi *
4298 i40e_vsi_setup(struct i40e_pf *pf,
4299                enum i40e_vsi_type type,
4300                struct i40e_vsi *uplink_vsi,
4301                uint16_t user_param)
4302 {
4303         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4304         struct i40e_vsi *vsi;
4305         struct i40e_mac_filter_info filter;
4306         int ret;
4307         struct i40e_vsi_context ctxt;
4308         struct ether_addr broadcast =
4309                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4310
4311         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4312             uplink_vsi == NULL) {
4313                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4314                             "VSI link shouldn't be NULL");
4315                 return NULL;
4316         }
4317
4318         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4319                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4320                             "uplink VSI should be NULL");
4321                 return NULL;
4322         }
4323
4324         /* two situations
4325          * 1.type is not MAIN and uplink vsi is not NULL
4326          * If uplink vsi didn't setup VEB, create one first under veb field
4327          * 2.type is SRIOV and the uplink is NULL
4328          * If floating VEB is NULL, create one veb under floating veb field
4329          */
4330
4331         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4332             uplink_vsi->veb == NULL) {
4333                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4334
4335                 if (uplink_vsi->veb == NULL) {
4336                         PMD_DRV_LOG(ERR, "VEB setup failed");
4337                         return NULL;
4338                 }
4339                 /* set ALLOWLOOPBACk on pf, when veb is created */
4340                 i40e_enable_pf_lb(pf);
4341         }
4342
4343         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4344             pf->main_vsi->floating_veb == NULL) {
4345                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4346
4347                 if (pf->main_vsi->floating_veb == NULL) {
4348                         PMD_DRV_LOG(ERR, "VEB setup failed");
4349                         return NULL;
4350                 }
4351         }
4352
4353         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4354         if (!vsi) {
4355                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4356                 return NULL;
4357         }
4358         TAILQ_INIT(&vsi->mac_list);
4359         vsi->type = type;
4360         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4361         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4362         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4363         vsi->user_param = user_param;
4364         /* Allocate queues */
4365         switch (vsi->type) {
4366         case I40E_VSI_MAIN  :
4367                 vsi->nb_qps = pf->lan_nb_qps;
4368                 break;
4369         case I40E_VSI_SRIOV :
4370                 vsi->nb_qps = pf->vf_nb_qps;
4371                 break;
4372         case I40E_VSI_VMDQ2:
4373                 vsi->nb_qps = pf->vmdq_nb_qps;
4374                 break;
4375         case I40E_VSI_FDIR:
4376                 vsi->nb_qps = pf->fdir_nb_qps;
4377                 break;
4378         default:
4379                 goto fail_mem;
4380         }
4381         /*
4382          * The filter status descriptor is reported in rx queue 0,
4383          * while the tx queue for fdir filter programming has no
4384          * such constraints, can be non-zero queues.
4385          * To simplify it, choose FDIR vsi use queue 0 pair.
4386          * To make sure it will use queue 0 pair, queue allocation
4387          * need be done before this function is called
4388          */
4389         if (type != I40E_VSI_FDIR) {
4390                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4391                         if (ret < 0) {
4392                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4393                                                 vsi->seid, ret);
4394                                 goto fail_mem;
4395                         }
4396                         vsi->base_queue = ret;
4397         } else
4398                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4399
4400         /* VF has MSIX interrupt in VF range, don't allocate here */
4401         if (type == I40E_VSI_MAIN) {
4402                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4403                                           RTE_MIN(vsi->nb_qps,
4404                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4405                 if (ret < 0) {
4406                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4407                                     vsi->seid, ret);
4408                         goto fail_queue_alloc;
4409                 }
4410                 vsi->msix_intr = ret;
4411                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4412         } else if (type != I40E_VSI_SRIOV) {
4413                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4414                 if (ret < 0) {
4415                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4416                         goto fail_queue_alloc;
4417                 }
4418                 vsi->msix_intr = ret;
4419                 vsi->nb_msix = 1;
4420         } else {
4421                 vsi->msix_intr = 0;
4422                 vsi->nb_msix = 0;
4423         }
4424
4425         /* Add VSI */
4426         if (type == I40E_VSI_MAIN) {
4427                 /* For main VSI, no need to add since it's default one */
4428                 vsi->uplink_seid = pf->mac_seid;
4429                 vsi->seid = pf->main_vsi_seid;
4430                 /* Bind queues with specific MSIX interrupt */
4431                 /**
4432                  * Needs 2 interrupt at least, one for misc cause which will
4433                  * enabled from OS side, Another for queues binding the
4434                  * interrupt from device side only.
4435                  */
4436
4437                 /* Get default VSI parameters from hardware */
4438                 memset(&ctxt, 0, sizeof(ctxt));
4439                 ctxt.seid = vsi->seid;
4440                 ctxt.pf_num = hw->pf_id;
4441                 ctxt.uplink_seid = vsi->uplink_seid;
4442                 ctxt.vf_num = 0;
4443                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4444                 if (ret != I40E_SUCCESS) {
4445                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4446                         goto fail_msix_alloc;
4447                 }
4448                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4449                         sizeof(struct i40e_aqc_vsi_properties_data));
4450                 vsi->vsi_id = ctxt.vsi_number;
4451                 vsi->info.valid_sections = 0;
4452
4453                 /* Configure tc, enabled TC0 only */
4454                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4455                         I40E_SUCCESS) {
4456                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4457                         goto fail_msix_alloc;
4458                 }
4459
4460                 /* TC, queue mapping */
4461                 memset(&ctxt, 0, sizeof(ctxt));
4462                 vsi->info.valid_sections |=
4463                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4464                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4465                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4466                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4467                         sizeof(struct i40e_aqc_vsi_properties_data));
4468                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4469                                                 I40E_DEFAULT_TCMAP);
4470                 if (ret != I40E_SUCCESS) {
4471                         PMD_DRV_LOG(ERR, "Failed to configure "
4472                                     "TC queue mapping");
4473                         goto fail_msix_alloc;
4474                 }
4475                 ctxt.seid = vsi->seid;
4476                 ctxt.pf_num = hw->pf_id;
4477                 ctxt.uplink_seid = vsi->uplink_seid;
4478                 ctxt.vf_num = 0;
4479
4480                 /* Update VSI parameters */
4481                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4482                 if (ret != I40E_SUCCESS) {
4483                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4484                         goto fail_msix_alloc;
4485                 }
4486
4487                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4488                                                 sizeof(vsi->info.tc_mapping));
4489                 (void)rte_memcpy(&vsi->info.queue_mapping,
4490                                 &ctxt.info.queue_mapping,
4491                         sizeof(vsi->info.queue_mapping));
4492                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4493                 vsi->info.valid_sections = 0;
4494
4495                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4496                                 ETH_ADDR_LEN);
4497
4498                 /**
4499                  * Updating default filter settings are necessary to prevent
4500                  * reception of tagged packets.
4501                  * Some old firmware configurations load a default macvlan
4502                  * filter which accepts both tagged and untagged packets.
4503                  * The updating is to use a normal filter instead if needed.
4504                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4505                  * The firmware with correct configurations load the default
4506                  * macvlan filter which is expected and cannot be removed.
4507                  */
4508                 i40e_update_default_filter_setting(vsi);
4509                 i40e_config_qinq(hw, vsi);
4510         } else if (type == I40E_VSI_SRIOV) {
4511                 memset(&ctxt, 0, sizeof(ctxt));
4512                 /**
4513                  * For other VSI, the uplink_seid equals to uplink VSI's
4514                  * uplink_seid since they share same VEB
4515                  */
4516                 if (uplink_vsi == NULL)
4517                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4518                 else
4519                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4520                 ctxt.pf_num = hw->pf_id;
4521                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4522                 ctxt.uplink_seid = vsi->uplink_seid;
4523                 ctxt.connection_type = 0x1;
4524                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4525
4526                 /* Use the VEB configuration if FW >= v5.0 */
4527                 if (hw->aq.fw_maj_ver >= 5) {
4528                         /* Configure switch ID */
4529                         ctxt.info.valid_sections |=
4530                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4531                         ctxt.info.switch_id =
4532                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4533                 }
4534
4535                 /* Configure port/vlan */
4536                 ctxt.info.valid_sections |=
4537                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4538                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4539                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4540                                                 I40E_DEFAULT_TCMAP);
4541                 if (ret != I40E_SUCCESS) {
4542                         PMD_DRV_LOG(ERR, "Failed to configure "
4543                                     "TC queue mapping");
4544                         goto fail_msix_alloc;
4545                 }
4546                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4547                 ctxt.info.valid_sections |=
4548                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4549                 /**
4550                  * Since VSI is not created yet, only configure parameter,
4551                  * will add vsi below.
4552                  */
4553
4554                 i40e_config_qinq(hw, vsi);
4555         } else if (type == I40E_VSI_VMDQ2) {
4556                 memset(&ctxt, 0, sizeof(ctxt));
4557                 /*
4558                  * For other VSI, the uplink_seid equals to uplink VSI's
4559                  * uplink_seid since they share same VEB
4560                  */
4561                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4562                 ctxt.pf_num = hw->pf_id;
4563                 ctxt.vf_num = 0;
4564                 ctxt.uplink_seid = vsi->uplink_seid;
4565                 ctxt.connection_type = 0x1;
4566                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4567
4568                 ctxt.info.valid_sections |=
4569                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4570                 /* user_param carries flag to enable loop back */
4571                 if (user_param) {
4572                         ctxt.info.switch_id =
4573                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4574                         ctxt.info.switch_id |=
4575                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4576                 }
4577
4578                 /* Configure port/vlan */
4579                 ctxt.info.valid_sections |=
4580                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4581                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4582                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4583                                                 I40E_DEFAULT_TCMAP);
4584                 if (ret != I40E_SUCCESS) {
4585                         PMD_DRV_LOG(ERR, "Failed to configure "
4586                                         "TC queue mapping");
4587                         goto fail_msix_alloc;
4588                 }
4589                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4590                 ctxt.info.valid_sections |=
4591                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4592         } else if (type == I40E_VSI_FDIR) {
4593                 memset(&ctxt, 0, sizeof(ctxt));
4594                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4595                 ctxt.pf_num = hw->pf_id;
4596                 ctxt.vf_num = 0;
4597                 ctxt.uplink_seid = vsi->uplink_seid;
4598                 ctxt.connection_type = 0x1;     /* regular data port */
4599                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4600                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4601                                                 I40E_DEFAULT_TCMAP);
4602                 if (ret != I40E_SUCCESS) {
4603                         PMD_DRV_LOG(ERR, "Failed to configure "
4604                                         "TC queue mapping.");
4605                         goto fail_msix_alloc;
4606                 }
4607                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4608                 ctxt.info.valid_sections |=
4609                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4610         } else {
4611                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4612                 goto fail_msix_alloc;
4613         }
4614
4615         if (vsi->type != I40E_VSI_MAIN) {
4616                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4617                 if (ret != I40E_SUCCESS) {
4618                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4619                                     hw->aq.asq_last_status);
4620                         goto fail_msix_alloc;
4621                 }
4622                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4623                 vsi->info.valid_sections = 0;
4624                 vsi->seid = ctxt.seid;
4625                 vsi->vsi_id = ctxt.vsi_number;
4626                 vsi->sib_vsi_list.vsi = vsi;
4627                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4628                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4629                                           &vsi->sib_vsi_list, list);
4630                 } else {
4631                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4632                                           &vsi->sib_vsi_list, list);
4633                 }
4634         }
4635
4636         /* MAC/VLAN configuration */
4637         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4638         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4639
4640         ret = i40e_vsi_add_mac(vsi, &filter);
4641         if (ret != I40E_SUCCESS) {
4642                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4643                 goto fail_msix_alloc;
4644         }
4645
4646         /* Get VSI BW information */
4647         i40e_vsi_get_bw_config(vsi);
4648         return vsi;
4649 fail_msix_alloc:
4650         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4651 fail_queue_alloc:
4652         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4653 fail_mem:
4654         rte_free(vsi);
4655         return NULL;
4656 }
4657
4658 /* Configure vlan filter on or off */
4659 int
4660 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4661 {
4662         int i, num;
4663         struct i40e_mac_filter *f;
4664         struct i40e_mac_filter_info *mac_filter;
4665         enum rte_mac_filter_type desired_filter;
4666         int ret = I40E_SUCCESS;
4667
4668         if (on) {
4669                 /* Filter to match MAC and VLAN */
4670                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4671         } else {
4672                 /* Filter to match only MAC */
4673                 desired_filter = RTE_MAC_PERFECT_MATCH;
4674         }
4675
4676         num = vsi->mac_num;
4677
4678         mac_filter = rte_zmalloc("mac_filter_info_data",
4679                                  num * sizeof(*mac_filter), 0);
4680         if (mac_filter == NULL) {
4681                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4682                 return I40E_ERR_NO_MEMORY;
4683         }
4684
4685         i = 0;
4686
4687         /* Remove all existing mac */
4688         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4689                 mac_filter[i] = f->mac_info;
4690                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4691                 if (ret) {
4692                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4693                                     on ? "enable" : "disable");
4694                         goto DONE;
4695                 }
4696                 i++;
4697         }
4698
4699         /* Override with new filter */
4700         for (i = 0; i < num; i++) {
4701                 mac_filter[i].filter_type = desired_filter;
4702                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4703                 if (ret) {
4704                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4705                                     on ? "enable" : "disable");
4706                         goto DONE;
4707                 }
4708         }
4709
4710 DONE:
4711         rte_free(mac_filter);
4712         return ret;
4713 }
4714
4715 /* Configure vlan stripping on or off */
4716 int
4717 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4718 {
4719         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4720         struct i40e_vsi_context ctxt;
4721         uint8_t vlan_flags;
4722         int ret = I40E_SUCCESS;
4723
4724         /* Check if it has been already on or off */
4725         if (vsi->info.valid_sections &
4726                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4727                 if (on) {
4728                         if ((vsi->info.port_vlan_flags &
4729                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4730                                 return 0; /* already on */
4731                 } else {
4732                         if ((vsi->info.port_vlan_flags &
4733                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4734                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4735                                 return 0; /* already off */
4736                 }
4737         }
4738
4739         if (on)
4740                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4741         else
4742                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4743         vsi->info.valid_sections =
4744                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4745         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4746         vsi->info.port_vlan_flags |= vlan_flags;
4747         ctxt.seid = vsi->seid;
4748         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4749         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4750         if (ret)
4751                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4752                             on ? "enable" : "disable");
4753
4754         return ret;
4755 }
4756
4757 static int
4758 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4759 {
4760         struct rte_eth_dev_data *data = dev->data;
4761         int ret;
4762         int mask = 0;
4763
4764         /* Apply vlan offload setting */
4765         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4766         i40e_vlan_offload_set(dev, mask);
4767
4768         /* Apply double-vlan setting, not implemented yet */
4769
4770         /* Apply pvid setting */
4771         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4772                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4773         if (ret)
4774                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4775
4776         return ret;
4777 }
4778
4779 static int
4780 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4781 {
4782         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4783
4784         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4785 }
4786
4787 static int
4788 i40e_update_flow_control(struct i40e_hw *hw)
4789 {
4790 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4791         struct i40e_link_status link_status;
4792         uint32_t rxfc = 0, txfc = 0, reg;
4793         uint8_t an_info;
4794         int ret;
4795
4796         memset(&link_status, 0, sizeof(link_status));
4797         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4798         if (ret != I40E_SUCCESS) {
4799                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4800                 goto write_reg; /* Disable flow control */
4801         }
4802
4803         an_info = hw->phy.link_info.an_info;
4804         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4805                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4806                 ret = I40E_ERR_NOT_READY;
4807                 goto write_reg; /* Disable flow control */
4808         }
4809         /**
4810          * If link auto negotiation is enabled, flow control needs to
4811          * be configured according to it
4812          */
4813         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4814         case I40E_LINK_PAUSE_RXTX:
4815                 rxfc = 1;
4816                 txfc = 1;
4817                 hw->fc.current_mode = I40E_FC_FULL;
4818                 break;
4819         case I40E_AQ_LINK_PAUSE_RX:
4820                 rxfc = 1;
4821                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4822                 break;
4823         case I40E_AQ_LINK_PAUSE_TX:
4824                 txfc = 1;
4825                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4826                 break;
4827         default:
4828                 hw->fc.current_mode = I40E_FC_NONE;
4829                 break;
4830         }
4831
4832 write_reg:
4833         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4834                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4835         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4836         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4837         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4838         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4839
4840         return ret;
4841 }
4842
4843 /* PF setup */
4844 static int
4845 i40e_pf_setup(struct i40e_pf *pf)
4846 {
4847         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4848         struct i40e_filter_control_settings settings;
4849         struct i40e_vsi *vsi;
4850         int ret;
4851
4852         /* Clear all stats counters */
4853         pf->offset_loaded = FALSE;
4854         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4855         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4856
4857         ret = i40e_pf_get_switch_config(pf);
4858         if (ret != I40E_SUCCESS) {
4859                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4860                 return ret;
4861         }
4862         if (pf->flags & I40E_FLAG_FDIR) {
4863                 /* make queue allocated first, let FDIR use queue pair 0*/
4864                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4865                 if (ret != I40E_FDIR_QUEUE_ID) {
4866                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4867                                     " ret =%d", ret);
4868                         pf->flags &= ~I40E_FLAG_FDIR;
4869                 }
4870         }
4871         /*  main VSI setup */
4872         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4873         if (!vsi) {
4874                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4875                 return I40E_ERR_NOT_READY;
4876         }
4877         pf->main_vsi = vsi;
4878
4879         /* Configure filter control */
4880         memset(&settings, 0, sizeof(settings));
4881         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4882                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4883         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4884                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4885         else {
4886                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4887                                                 hw->func_caps.rss_table_size);
4888                 return I40E_ERR_PARAM;
4889         }
4890         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4891                         "size: %u\n", hw->func_caps.rss_table_size);
4892         pf->hash_lut_size = hw->func_caps.rss_table_size;
4893
4894         /* Enable ethtype and macvlan filters */
4895         settings.enable_ethtype = TRUE;
4896         settings.enable_macvlan = TRUE;
4897         ret = i40e_set_filter_control(hw, &settings);
4898         if (ret)
4899                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4900                                                                 ret);
4901
4902         /* Update flow control according to the auto negotiation */
4903         i40e_update_flow_control(hw);
4904
4905         return I40E_SUCCESS;
4906 }
4907
4908 int
4909 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4910 {
4911         uint32_t reg;
4912         uint16_t j;
4913
4914         /**
4915          * Set or clear TX Queue Disable flags,
4916          * which is required by hardware.
4917          */
4918         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4919         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4920
4921         /* Wait until the request is finished */
4922         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4923                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4924                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4925                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4926                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4927                                                         & 0x1))) {
4928                         break;
4929                 }
4930         }
4931         if (on) {
4932                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4933                         return I40E_SUCCESS; /* already on, skip next steps */
4934
4935                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4936                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4937         } else {
4938                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4939                         return I40E_SUCCESS; /* already off, skip next steps */
4940                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4941         }
4942         /* Write the register */
4943         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4944         /* Check the result */
4945         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4946                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4947                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4948                 if (on) {
4949                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4950                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4951                                 break;
4952                 } else {
4953                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4954                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4955                                 break;
4956                 }
4957         }
4958         /* Check if it is timeout */
4959         if (j >= I40E_CHK_Q_ENA_COUNT) {
4960                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4961                             (on ? "enable" : "disable"), q_idx);
4962                 return I40E_ERR_TIMEOUT;
4963         }
4964
4965         return I40E_SUCCESS;
4966 }
4967
4968 /* Swith on or off the tx queues */
4969 static int
4970 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4971 {
4972         struct rte_eth_dev_data *dev_data = pf->dev_data;
4973         struct i40e_tx_queue *txq;
4974         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4975         uint16_t i;
4976         int ret;
4977
4978         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4979                 txq = dev_data->tx_queues[i];
4980                 /* Don't operate the queue if not configured or
4981                  * if starting only per queue */
4982                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4983                         continue;
4984                 if (on)
4985                         ret = i40e_dev_tx_queue_start(dev, i);
4986                 else
4987                         ret = i40e_dev_tx_queue_stop(dev, i);
4988                 if ( ret != I40E_SUCCESS)
4989                         return ret;
4990         }
4991
4992         return I40E_SUCCESS;
4993 }
4994
4995 int
4996 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4997 {
4998         uint32_t reg;
4999         uint16_t j;
5000
5001         /* Wait until the request is finished */
5002         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5003                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5004                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5005                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5006                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5007                         break;
5008         }
5009
5010         if (on) {
5011                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5012                         return I40E_SUCCESS; /* Already on, skip next steps */
5013                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5014         } else {
5015                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5016                         return I40E_SUCCESS; /* Already off, skip next steps */
5017                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5018         }
5019
5020         /* Write the register */
5021         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5022         /* Check the result */
5023         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5024                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5025                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5026                 if (on) {
5027                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5028                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5029                                 break;
5030                 } else {
5031                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5032                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5033                                 break;
5034                 }
5035         }
5036
5037         /* Check if it is timeout */
5038         if (j >= I40E_CHK_Q_ENA_COUNT) {
5039                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5040                             (on ? "enable" : "disable"), q_idx);
5041                 return I40E_ERR_TIMEOUT;
5042         }
5043
5044         return I40E_SUCCESS;
5045 }
5046 /* Switch on or off the rx queues */
5047 static int
5048 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5049 {
5050         struct rte_eth_dev_data *dev_data = pf->dev_data;
5051         struct i40e_rx_queue *rxq;
5052         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5053         uint16_t i;
5054         int ret;
5055
5056         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5057                 rxq = dev_data->rx_queues[i];
5058                 /* Don't operate the queue if not configured or
5059                  * if starting only per queue */
5060                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5061                         continue;
5062                 if (on)
5063                         ret = i40e_dev_rx_queue_start(dev, i);
5064                 else
5065                         ret = i40e_dev_rx_queue_stop(dev, i);
5066                 if (ret != I40E_SUCCESS)
5067                         return ret;
5068         }
5069
5070         return I40E_SUCCESS;
5071 }
5072
5073 /* Switch on or off all the rx/tx queues */
5074 int
5075 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5076 {
5077         int ret;
5078
5079         if (on) {
5080                 /* enable rx queues before enabling tx queues */
5081                 ret = i40e_dev_switch_rx_queues(pf, on);
5082                 if (ret) {
5083                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5084                         return ret;
5085                 }
5086                 ret = i40e_dev_switch_tx_queues(pf, on);
5087         } else {
5088                 /* Stop tx queues before stopping rx queues */
5089                 ret = i40e_dev_switch_tx_queues(pf, on);
5090                 if (ret) {
5091                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5092                         return ret;
5093                 }
5094                 ret = i40e_dev_switch_rx_queues(pf, on);
5095         }
5096
5097         return ret;
5098 }
5099
5100 /* Initialize VSI for TX */
5101 static int
5102 i40e_dev_tx_init(struct i40e_pf *pf)
5103 {
5104         struct rte_eth_dev_data *data = pf->dev_data;
5105         uint16_t i;
5106         uint32_t ret = I40E_SUCCESS;
5107         struct i40e_tx_queue *txq;
5108
5109         for (i = 0; i < data->nb_tx_queues; i++) {
5110                 txq = data->tx_queues[i];
5111                 if (!txq || !txq->q_set)
5112                         continue;
5113                 ret = i40e_tx_queue_init(txq);
5114                 if (ret != I40E_SUCCESS)
5115                         break;
5116         }
5117         if (ret == I40E_SUCCESS)
5118                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5119                                      ->eth_dev);
5120
5121         return ret;
5122 }
5123
5124 /* Initialize VSI for RX */
5125 static int
5126 i40e_dev_rx_init(struct i40e_pf *pf)
5127 {
5128         struct rte_eth_dev_data *data = pf->dev_data;
5129         int ret = I40E_SUCCESS;
5130         uint16_t i;
5131         struct i40e_rx_queue *rxq;
5132
5133         i40e_pf_config_mq_rx(pf);
5134         for (i = 0; i < data->nb_rx_queues; i++) {
5135                 rxq = data->rx_queues[i];
5136                 if (!rxq || !rxq->q_set)
5137                         continue;
5138
5139                 ret = i40e_rx_queue_init(rxq);
5140                 if (ret != I40E_SUCCESS) {
5141                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5142                                     "initialization");
5143                         break;
5144                 }
5145         }
5146         if (ret == I40E_SUCCESS)
5147                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5148                                      ->eth_dev);
5149
5150         return ret;
5151 }
5152
5153 static int
5154 i40e_dev_rxtx_init(struct i40e_pf *pf)
5155 {
5156         int err;
5157
5158         err = i40e_dev_tx_init(pf);
5159         if (err) {
5160                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5161                 return err;
5162         }
5163         err = i40e_dev_rx_init(pf);
5164         if (err) {
5165                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5166                 return err;
5167         }
5168
5169         return err;
5170 }
5171
5172 static int
5173 i40e_vmdq_setup(struct rte_eth_dev *dev)
5174 {
5175         struct rte_eth_conf *conf = &dev->data->dev_conf;
5176         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5177         int i, err, conf_vsis, j, loop;
5178         struct i40e_vsi *vsi;
5179         struct i40e_vmdq_info *vmdq_info;
5180         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5181         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5182
5183         /*
5184          * Disable interrupt to avoid message from VF. Furthermore, it will
5185          * avoid race condition in VSI creation/destroy.
5186          */
5187         i40e_pf_disable_irq0(hw);
5188
5189         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5190                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5191                 return -ENOTSUP;
5192         }
5193
5194         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5195         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5196                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5197                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5198                         pf->max_nb_vmdq_vsi);
5199                 return -ENOTSUP;
5200         }
5201
5202         if (pf->vmdq != NULL) {
5203                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5204                 return 0;
5205         }
5206
5207         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5208                                 sizeof(*vmdq_info) * conf_vsis, 0);
5209
5210         if (pf->vmdq == NULL) {
5211                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5212                 return -ENOMEM;
5213         }
5214
5215         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5216
5217         /* Create VMDQ VSI */
5218         for (i = 0; i < conf_vsis; i++) {
5219                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5220                                 vmdq_conf->enable_loop_back);
5221                 if (vsi == NULL) {
5222                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5223                         err = -1;
5224                         goto err_vsi_setup;
5225                 }
5226                 vmdq_info = &pf->vmdq[i];
5227                 vmdq_info->pf = pf;
5228                 vmdq_info->vsi = vsi;
5229         }
5230         pf->nb_cfg_vmdq_vsi = conf_vsis;
5231
5232         /* Configure Vlan */
5233         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5234         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5235                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5236                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5237                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5238                                         vmdq_conf->pool_map[i].vlan_id, j);
5239
5240                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5241                                                 vmdq_conf->pool_map[i].vlan_id);
5242                                 if (err) {
5243                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5244                                         err = -1;
5245                                         goto err_vsi_setup;
5246                                 }
5247                         }
5248                 }
5249         }
5250
5251         i40e_pf_enable_irq0(hw);
5252
5253         return 0;
5254
5255 err_vsi_setup:
5256         for (i = 0; i < conf_vsis; i++)
5257                 if (pf->vmdq[i].vsi == NULL)
5258                         break;
5259                 else
5260                         i40e_vsi_release(pf->vmdq[i].vsi);
5261
5262         rte_free(pf->vmdq);
5263         pf->vmdq = NULL;
5264         i40e_pf_enable_irq0(hw);
5265         return err;
5266 }
5267
5268 static void
5269 i40e_stat_update_32(struct i40e_hw *hw,
5270                    uint32_t reg,
5271                    bool offset_loaded,
5272                    uint64_t *offset,
5273                    uint64_t *stat)
5274 {
5275         uint64_t new_data;
5276
5277         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5278         if (!offset_loaded)
5279                 *offset = new_data;
5280
5281         if (new_data >= *offset)
5282                 *stat = (uint64_t)(new_data - *offset);
5283         else
5284                 *stat = (uint64_t)((new_data +
5285                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5286 }
5287
5288 static void
5289 i40e_stat_update_48(struct i40e_hw *hw,
5290                    uint32_t hireg,
5291                    uint32_t loreg,
5292                    bool offset_loaded,
5293                    uint64_t *offset,
5294                    uint64_t *stat)
5295 {
5296         uint64_t new_data;
5297
5298         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5299         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5300                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5301
5302         if (!offset_loaded)
5303                 *offset = new_data;
5304
5305         if (new_data >= *offset)
5306                 *stat = new_data - *offset;
5307         else
5308                 *stat = (uint64_t)((new_data +
5309                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5310
5311         *stat &= I40E_48_BIT_MASK;
5312 }
5313
5314 /* Disable IRQ0 */
5315 void
5316 i40e_pf_disable_irq0(struct i40e_hw *hw)
5317 {
5318         /* Disable all interrupt types */
5319         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5320         I40E_WRITE_FLUSH(hw);
5321 }
5322
5323 /* Enable IRQ0 */
5324 void
5325 i40e_pf_enable_irq0(struct i40e_hw *hw)
5326 {
5327         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5328                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5329                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5330                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5331         I40E_WRITE_FLUSH(hw);
5332 }
5333
5334 static void
5335 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5336 {
5337         /* read pending request and disable first */
5338         i40e_pf_disable_irq0(hw);
5339         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5340         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5341                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5342
5343         if (no_queue)
5344                 /* Link no queues with irq0 */
5345                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5346                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5347 }
5348
5349 static void
5350 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5351 {
5352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5353         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5354         int i;
5355         uint16_t abs_vf_id;
5356         uint32_t index, offset, val;
5357
5358         if (!pf->vfs)
5359                 return;
5360         /**
5361          * Try to find which VF trigger a reset, use absolute VF id to access
5362          * since the reg is global register.
5363          */
5364         for (i = 0; i < pf->vf_num; i++) {
5365                 abs_vf_id = hw->func_caps.vf_base_id + i;
5366                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5367                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5368                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5369                 /* VFR event occured */
5370                 if (val & (0x1 << offset)) {
5371                         int ret;
5372
5373                         /* Clear the event first */
5374                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5375                                                         (0x1 << offset));
5376                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5377                         /**
5378                          * Only notify a VF reset event occured,
5379                          * don't trigger another SW reset
5380                          */
5381                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5382                         if (ret != I40E_SUCCESS)
5383                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5384                 }
5385         }
5386 }
5387
5388 static void
5389 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5390 {
5391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5392         struct i40e_arq_event_info info;
5393         uint16_t pending, opcode;
5394         int ret;
5395
5396         info.buf_len = I40E_AQ_BUF_SZ;
5397         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5398         if (!info.msg_buf) {
5399                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5400                 return;
5401         }
5402
5403         pending = 1;
5404         while (pending) {
5405                 ret = i40e_clean_arq_element(hw, &info, &pending);
5406
5407                 if (ret != I40E_SUCCESS) {
5408                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5409                                     "aq_err: %u", hw->aq.asq_last_status);
5410                         break;
5411                 }
5412                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5413
5414                 switch (opcode) {
5415                 case i40e_aqc_opc_send_msg_to_pf:
5416                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5417                         i40e_pf_host_handle_vf_msg(dev,
5418                                         rte_le_to_cpu_16(info.desc.retval),
5419                                         rte_le_to_cpu_32(info.desc.cookie_high),
5420                                         rte_le_to_cpu_32(info.desc.cookie_low),
5421                                         info.msg_buf,
5422                                         info.msg_len);
5423                         break;
5424                 default:
5425                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5426                                     opcode);
5427                         break;
5428                 }
5429         }
5430         rte_free(info.msg_buf);
5431 }
5432
5433 /*
5434  * Interrupt handler is registered as the alarm callback for handling LSC
5435  * interrupt in a definite of time, in order to wait the NIC into a stable
5436  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5437  * no need for link down interrupt.
5438  */
5439 static void
5440 i40e_dev_interrupt_delayed_handler(void *param)
5441 {
5442         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5443         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5444         uint32_t icr0;
5445
5446         /* read interrupt causes again */
5447         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5448
5449 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5450         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5451                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5452         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5453                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5454         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5455                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5456         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5457                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5458         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5459                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5460                                                                 "state\n");
5461         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5462                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5463         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5464                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5465 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5466
5467         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5468                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5469                 i40e_dev_handle_vfr_event(dev);
5470         }
5471         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5472                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5473                 i40e_dev_handle_aq_msg(dev);
5474         }
5475
5476         /* handle the link up interrupt in an alarm callback */
5477         i40e_dev_link_update(dev, 0);
5478         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5479
5480         i40e_pf_enable_irq0(hw);
5481         rte_intr_enable(&(dev->pci_dev->intr_handle));
5482 }
5483
5484 /**
5485  * Interrupt handler triggered by NIC  for handling
5486  * specific interrupt.
5487  *
5488  * @param handle
5489  *  Pointer to interrupt handle.
5490  * @param param
5491  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5492  *
5493  * @return
5494  *  void
5495  */
5496 static void
5497 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5498                            void *param)
5499 {
5500         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5501         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5502         uint32_t icr0;
5503
5504         /* Disable interrupt */
5505         i40e_pf_disable_irq0(hw);
5506
5507         /* read out interrupt causes */
5508         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5509
5510         /* No interrupt event indicated */
5511         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5512                 PMD_DRV_LOG(INFO, "No interrupt event");
5513                 goto done;
5514         }
5515 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5516         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5517                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5518         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5519                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5520         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5521                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5522         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5523                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5524         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5525                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5526         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5527                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5528         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5529                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5530 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5531
5532         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5533                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5534                 i40e_dev_handle_vfr_event(dev);
5535         }
5536         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5537                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5538                 i40e_dev_handle_aq_msg(dev);
5539         }
5540
5541         /* Link Status Change interrupt */
5542         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5543 #define I40E_US_PER_SECOND 1000000
5544                 struct rte_eth_link link;
5545
5546                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5547                 memset(&link, 0, sizeof(link));
5548                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5549                 i40e_dev_link_update(dev, 0);
5550
5551                 /*
5552                  * For link up interrupt, it needs to wait 1 second to let the
5553                  * hardware be a stable state. Otherwise several consecutive
5554                  * interrupts can be observed.
5555                  * For link down interrupt, no need to wait.
5556                  */
5557                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5558                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5559                         return;
5560                 else
5561                         _rte_eth_dev_callback_process(dev,
5562                                 RTE_ETH_EVENT_INTR_LSC);
5563         }
5564
5565 done:
5566         /* Enable interrupt */
5567         i40e_pf_enable_irq0(hw);
5568         rte_intr_enable(&(dev->pci_dev->intr_handle));
5569 }
5570
5571 static int
5572 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5573                          struct i40e_macvlan_filter *filter,
5574                          int total)
5575 {
5576         int ele_num, ele_buff_size;
5577         int num, actual_num, i;
5578         uint16_t flags;
5579         int ret = I40E_SUCCESS;
5580         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5581         struct i40e_aqc_add_macvlan_element_data *req_list;
5582
5583         if (filter == NULL  || total == 0)
5584                 return I40E_ERR_PARAM;
5585         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5586         ele_buff_size = hw->aq.asq_buf_size;
5587
5588         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5589         if (req_list == NULL) {
5590                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5591                 return I40E_ERR_NO_MEMORY;
5592         }
5593
5594         num = 0;
5595         do {
5596                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5597                 memset(req_list, 0, ele_buff_size);
5598
5599                 for (i = 0; i < actual_num; i++) {
5600                         (void)rte_memcpy(req_list[i].mac_addr,
5601                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5602                         req_list[i].vlan_tag =
5603                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5604
5605                         switch (filter[num + i].filter_type) {
5606                         case RTE_MAC_PERFECT_MATCH:
5607                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5608                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5609                                 break;
5610                         case RTE_MACVLAN_PERFECT_MATCH:
5611                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5612                                 break;
5613                         case RTE_MAC_HASH_MATCH:
5614                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5615                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5616                                 break;
5617                         case RTE_MACVLAN_HASH_MATCH:
5618                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5619                                 break;
5620                         default:
5621                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5622                                 ret = I40E_ERR_PARAM;
5623                                 goto DONE;
5624                         }
5625
5626                         req_list[i].queue_number = 0;
5627
5628                         req_list[i].flags = rte_cpu_to_le_16(flags);
5629                 }
5630
5631                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5632                                                 actual_num, NULL);
5633                 if (ret != I40E_SUCCESS) {
5634                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5635                         goto DONE;
5636                 }
5637                 num += actual_num;
5638         } while (num < total);
5639
5640 DONE:
5641         rte_free(req_list);
5642         return ret;
5643 }
5644
5645 static int
5646 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5647                             struct i40e_macvlan_filter *filter,
5648                             int total)
5649 {
5650         int ele_num, ele_buff_size;
5651         int num, actual_num, i;
5652         uint16_t flags;
5653         int ret = I40E_SUCCESS;
5654         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5655         struct i40e_aqc_remove_macvlan_element_data *req_list;
5656
5657         if (filter == NULL  || total == 0)
5658                 return I40E_ERR_PARAM;
5659
5660         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5661         ele_buff_size = hw->aq.asq_buf_size;
5662
5663         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5664         if (req_list == NULL) {
5665                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5666                 return I40E_ERR_NO_MEMORY;
5667         }
5668
5669         num = 0;
5670         do {
5671                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5672                 memset(req_list, 0, ele_buff_size);
5673
5674                 for (i = 0; i < actual_num; i++) {
5675                         (void)rte_memcpy(req_list[i].mac_addr,
5676                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5677                         req_list[i].vlan_tag =
5678                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5679
5680                         switch (filter[num + i].filter_type) {
5681                         case RTE_MAC_PERFECT_MATCH:
5682                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5683                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5684                                 break;
5685                         case RTE_MACVLAN_PERFECT_MATCH:
5686                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5687                                 break;
5688                         case RTE_MAC_HASH_MATCH:
5689                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5690                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5691                                 break;
5692                         case RTE_MACVLAN_HASH_MATCH:
5693                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5694                                 break;
5695                         default:
5696                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5697                                 ret = I40E_ERR_PARAM;
5698                                 goto DONE;
5699                         }
5700                         req_list[i].flags = rte_cpu_to_le_16(flags);
5701                 }
5702
5703                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5704                                                 actual_num, NULL);
5705                 if (ret != I40E_SUCCESS) {
5706                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5707                         goto DONE;
5708                 }
5709                 num += actual_num;
5710         } while (num < total);
5711
5712 DONE:
5713         rte_free(req_list);
5714         return ret;
5715 }
5716
5717 /* Find out specific MAC filter */
5718 static struct i40e_mac_filter *
5719 i40e_find_mac_filter(struct i40e_vsi *vsi,
5720                          struct ether_addr *macaddr)
5721 {
5722         struct i40e_mac_filter *f;
5723
5724         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5725                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5726                         return f;
5727         }
5728
5729         return NULL;
5730 }
5731
5732 static bool
5733 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5734                          uint16_t vlan_id)
5735 {
5736         uint32_t vid_idx, vid_bit;
5737
5738         if (vlan_id > ETH_VLAN_ID_MAX)
5739                 return 0;
5740
5741         vid_idx = I40E_VFTA_IDX(vlan_id);
5742         vid_bit = I40E_VFTA_BIT(vlan_id);
5743
5744         if (vsi->vfta[vid_idx] & vid_bit)
5745                 return 1;
5746         else
5747                 return 0;
5748 }
5749
5750 static void
5751 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5752                          uint16_t vlan_id, bool on)
5753 {
5754         uint32_t vid_idx, vid_bit;
5755
5756         if (vlan_id > ETH_VLAN_ID_MAX)
5757                 return;
5758
5759         vid_idx = I40E_VFTA_IDX(vlan_id);
5760         vid_bit = I40E_VFTA_BIT(vlan_id);
5761
5762         if (on)
5763                 vsi->vfta[vid_idx] |= vid_bit;
5764         else
5765                 vsi->vfta[vid_idx] &= ~vid_bit;
5766 }
5767
5768 /**
5769  * Find all vlan options for specific mac addr,
5770  * return with actual vlan found.
5771  */
5772 static inline int
5773 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5774                            struct i40e_macvlan_filter *mv_f,
5775                            int num, struct ether_addr *addr)
5776 {
5777         int i;
5778         uint32_t j, k;
5779
5780         /**
5781          * Not to use i40e_find_vlan_filter to decrease the loop time,
5782          * although the code looks complex.
5783           */
5784         if (num < vsi->vlan_num)
5785                 return I40E_ERR_PARAM;
5786
5787         i = 0;
5788         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5789                 if (vsi->vfta[j]) {
5790                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5791                                 if (vsi->vfta[j] & (1 << k)) {
5792                                         if (i > num - 1) {
5793                                                 PMD_DRV_LOG(ERR, "vlan number "
5794                                                             "not match");
5795                                                 return I40E_ERR_PARAM;
5796                                         }
5797                                         (void)rte_memcpy(&mv_f[i].macaddr,
5798                                                         addr, ETH_ADDR_LEN);
5799                                         mv_f[i].vlan_id =
5800                                                 j * I40E_UINT32_BIT_SIZE + k;
5801                                         i++;
5802                                 }
5803                         }
5804                 }
5805         }
5806         return I40E_SUCCESS;
5807 }
5808
5809 static inline int
5810 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5811                            struct i40e_macvlan_filter *mv_f,
5812                            int num,
5813                            uint16_t vlan)
5814 {
5815         int i = 0;
5816         struct i40e_mac_filter *f;
5817
5818         if (num < vsi->mac_num)
5819                 return I40E_ERR_PARAM;
5820
5821         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5822                 if (i > num - 1) {
5823                         PMD_DRV_LOG(ERR, "buffer number not match");
5824                         return I40E_ERR_PARAM;
5825                 }
5826                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5827                                 ETH_ADDR_LEN);
5828                 mv_f[i].vlan_id = vlan;
5829                 mv_f[i].filter_type = f->mac_info.filter_type;
5830                 i++;
5831         }
5832
5833         return I40E_SUCCESS;
5834 }
5835
5836 static int
5837 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5838 {
5839         int i, num;
5840         struct i40e_mac_filter *f;
5841         struct i40e_macvlan_filter *mv_f;
5842         int ret = I40E_SUCCESS;
5843
5844         if (vsi == NULL || vsi->mac_num == 0)
5845                 return I40E_ERR_PARAM;
5846
5847         /* Case that no vlan is set */
5848         if (vsi->vlan_num == 0)
5849                 num = vsi->mac_num;
5850         else
5851                 num = vsi->mac_num * vsi->vlan_num;
5852
5853         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5854         if (mv_f == NULL) {
5855                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5856                 return I40E_ERR_NO_MEMORY;
5857         }
5858
5859         i = 0;
5860         if (vsi->vlan_num == 0) {
5861                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5862                         (void)rte_memcpy(&mv_f[i].macaddr,
5863                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5864                         mv_f[i].vlan_id = 0;
5865                         i++;
5866                 }
5867         } else {
5868                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5869                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5870                                         vsi->vlan_num, &f->mac_info.mac_addr);
5871                         if (ret != I40E_SUCCESS)
5872                                 goto DONE;
5873                         i += vsi->vlan_num;
5874                 }
5875         }
5876
5877         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5878 DONE:
5879         rte_free(mv_f);
5880
5881         return ret;
5882 }
5883
5884 int
5885 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5886 {
5887         struct i40e_macvlan_filter *mv_f;
5888         int mac_num;
5889         int ret = I40E_SUCCESS;
5890
5891         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5892                 return I40E_ERR_PARAM;
5893
5894         /* If it's already set, just return */
5895         if (i40e_find_vlan_filter(vsi,vlan))
5896                 return I40E_SUCCESS;
5897
5898         mac_num = vsi->mac_num;
5899
5900         if (mac_num == 0) {
5901                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5902                 return I40E_ERR_PARAM;
5903         }
5904
5905         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5906
5907         if (mv_f == NULL) {
5908                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5909                 return I40E_ERR_NO_MEMORY;
5910         }
5911
5912         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5913
5914         if (ret != I40E_SUCCESS)
5915                 goto DONE;
5916
5917         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5918
5919         if (ret != I40E_SUCCESS)
5920                 goto DONE;
5921
5922         i40e_set_vlan_filter(vsi, vlan, 1);
5923
5924         vsi->vlan_num++;
5925         ret = I40E_SUCCESS;
5926 DONE:
5927         rte_free(mv_f);
5928         return ret;
5929 }
5930
5931 int
5932 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5933 {
5934         struct i40e_macvlan_filter *mv_f;
5935         int mac_num;
5936         int ret = I40E_SUCCESS;
5937
5938         /**
5939          * Vlan 0 is the generic filter for untagged packets
5940          * and can't be removed.
5941          */
5942         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5943                 return I40E_ERR_PARAM;
5944
5945         /* If can't find it, just return */
5946         if (!i40e_find_vlan_filter(vsi, vlan))
5947                 return I40E_ERR_PARAM;
5948
5949         mac_num = vsi->mac_num;
5950
5951         if (mac_num == 0) {
5952                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5953                 return I40E_ERR_PARAM;
5954         }
5955
5956         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5957
5958         if (mv_f == NULL) {
5959                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5960                 return I40E_ERR_NO_MEMORY;
5961         }
5962
5963         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5964
5965         if (ret != I40E_SUCCESS)
5966                 goto DONE;
5967
5968         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5969
5970         if (ret != I40E_SUCCESS)
5971                 goto DONE;
5972
5973         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5974         if (vsi->vlan_num == 1) {
5975                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5976                 if (ret != I40E_SUCCESS)
5977                         goto DONE;
5978
5979                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5980                 if (ret != I40E_SUCCESS)
5981                         goto DONE;
5982         }
5983
5984         i40e_set_vlan_filter(vsi, vlan, 0);
5985
5986         vsi->vlan_num--;
5987         ret = I40E_SUCCESS;
5988 DONE:
5989         rte_free(mv_f);
5990         return ret;
5991 }
5992
5993 int
5994 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5995 {
5996         struct i40e_mac_filter *f;
5997         struct i40e_macvlan_filter *mv_f;
5998         int i, vlan_num = 0;
5999         int ret = I40E_SUCCESS;
6000
6001         /* If it's add and we've config it, return */
6002         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6003         if (f != NULL)
6004                 return I40E_SUCCESS;
6005         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6006                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6007
6008                 /**
6009                  * If vlan_num is 0, that's the first time to add mac,
6010                  * set mask for vlan_id 0.
6011                  */
6012                 if (vsi->vlan_num == 0) {
6013                         i40e_set_vlan_filter(vsi, 0, 1);
6014                         vsi->vlan_num = 1;
6015                 }
6016                 vlan_num = vsi->vlan_num;
6017         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6018                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6019                 vlan_num = 1;
6020
6021         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6022         if (mv_f == NULL) {
6023                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6024                 return I40E_ERR_NO_MEMORY;
6025         }
6026
6027         for (i = 0; i < vlan_num; i++) {
6028                 mv_f[i].filter_type = mac_filter->filter_type;
6029                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6030                                 ETH_ADDR_LEN);
6031         }
6032
6033         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6034                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6035                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6036                                         &mac_filter->mac_addr);
6037                 if (ret != I40E_SUCCESS)
6038                         goto DONE;
6039         }
6040
6041         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6042         if (ret != I40E_SUCCESS)
6043                 goto DONE;
6044
6045         /* Add the mac addr into mac list */
6046         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6047         if (f == NULL) {
6048                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6049                 ret = I40E_ERR_NO_MEMORY;
6050                 goto DONE;
6051         }
6052         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6053                         ETH_ADDR_LEN);
6054         f->mac_info.filter_type = mac_filter->filter_type;
6055         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6056         vsi->mac_num++;
6057
6058         ret = I40E_SUCCESS;
6059 DONE:
6060         rte_free(mv_f);
6061
6062         return ret;
6063 }
6064
6065 int
6066 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6067 {
6068         struct i40e_mac_filter *f;
6069         struct i40e_macvlan_filter *mv_f;
6070         int i, vlan_num;
6071         enum rte_mac_filter_type filter_type;
6072         int ret = I40E_SUCCESS;
6073
6074         /* Can't find it, return an error */
6075         f = i40e_find_mac_filter(vsi, addr);
6076         if (f == NULL)
6077                 return I40E_ERR_PARAM;
6078
6079         vlan_num = vsi->vlan_num;
6080         filter_type = f->mac_info.filter_type;
6081         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6082                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6083                 if (vlan_num == 0) {
6084                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6085                         return I40E_ERR_PARAM;
6086                 }
6087         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6088                         filter_type == RTE_MAC_HASH_MATCH)
6089                 vlan_num = 1;
6090
6091         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6092         if (mv_f == NULL) {
6093                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6094                 return I40E_ERR_NO_MEMORY;
6095         }
6096
6097         for (i = 0; i < vlan_num; i++) {
6098                 mv_f[i].filter_type = filter_type;
6099                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6100                                 ETH_ADDR_LEN);
6101         }
6102         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6103                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6104                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6105                 if (ret != I40E_SUCCESS)
6106                         goto DONE;
6107         }
6108
6109         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6110         if (ret != I40E_SUCCESS)
6111                 goto DONE;
6112
6113         /* Remove the mac addr into mac list */
6114         TAILQ_REMOVE(&vsi->mac_list, f, next);
6115         rte_free(f);
6116         vsi->mac_num--;
6117
6118         ret = I40E_SUCCESS;
6119 DONE:
6120         rte_free(mv_f);
6121         return ret;
6122 }
6123
6124 /* Configure hash enable flags for RSS */
6125 uint64_t
6126 i40e_config_hena(uint64_t flags)
6127 {
6128         uint64_t hena = 0;
6129
6130         if (!flags)
6131                 return hena;
6132
6133         if (flags & ETH_RSS_FRAG_IPV4)
6134                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6135         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6136                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6137         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6138                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6139         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6140                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6141         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6142                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6143         if (flags & ETH_RSS_FRAG_IPV6)
6144                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6145         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6146                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6147         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6148                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6149         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6150                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6151         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6152                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6153         if (flags & ETH_RSS_L2_PAYLOAD)
6154                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6155
6156         return hena;
6157 }
6158
6159 /* Parse the hash enable flags */
6160 uint64_t
6161 i40e_parse_hena(uint64_t flags)
6162 {
6163         uint64_t rss_hf = 0;
6164
6165         if (!flags)
6166                 return rss_hf;
6167         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6168                 rss_hf |= ETH_RSS_FRAG_IPV4;
6169         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6170                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6171         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6172                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6173         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6174                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6175         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6176                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6177         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6178                 rss_hf |= ETH_RSS_FRAG_IPV6;
6179         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6180                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6181         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6182                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6183         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6184                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6185         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6186                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6187         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6188                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6189
6190         return rss_hf;
6191 }
6192
6193 /* Disable RSS */
6194 static void
6195 i40e_pf_disable_rss(struct i40e_pf *pf)
6196 {
6197         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6198         uint64_t hena;
6199
6200         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6201         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6202         hena &= ~I40E_RSS_HENA_ALL;
6203         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6204         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6205         I40E_WRITE_FLUSH(hw);
6206 }
6207
6208 static int
6209 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6210 {
6211         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6212         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6213         int ret = 0;
6214
6215         if (!key || key_len == 0) {
6216                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6217                 return 0;
6218         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6219                 sizeof(uint32_t)) {
6220                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6221                 return -EINVAL;
6222         }
6223
6224         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6225                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6226                         (struct i40e_aqc_get_set_rss_key_data *)key;
6227
6228                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6229                 if (ret)
6230                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6231                                      "via AQ");
6232         } else {
6233                 uint32_t *hash_key = (uint32_t *)key;
6234                 uint16_t i;
6235
6236                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6237                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6238                 I40E_WRITE_FLUSH(hw);
6239         }
6240
6241         return ret;
6242 }
6243
6244 static int
6245 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6246 {
6247         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6248         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6249         int ret;
6250
6251         if (!key || !key_len)
6252                 return -EINVAL;
6253
6254         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6255                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6256                         (struct i40e_aqc_get_set_rss_key_data *)key);
6257                 if (ret) {
6258                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6259                         return ret;
6260                 }
6261         } else {
6262                 uint32_t *key_dw = (uint32_t *)key;
6263                 uint16_t i;
6264
6265                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6266                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6267         }
6268         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6269
6270         return 0;
6271 }
6272
6273 static int
6274 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6275 {
6276         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6277         uint64_t rss_hf;
6278         uint64_t hena;
6279         int ret;
6280
6281         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6282                                rss_conf->rss_key_len);
6283         if (ret)
6284                 return ret;
6285
6286         rss_hf = rss_conf->rss_hf;
6287         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6288         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6289         hena &= ~I40E_RSS_HENA_ALL;
6290         hena |= i40e_config_hena(rss_hf);
6291         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6292         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6293         I40E_WRITE_FLUSH(hw);
6294
6295         return 0;
6296 }
6297
6298 static int
6299 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6300                          struct rte_eth_rss_conf *rss_conf)
6301 {
6302         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6304         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6305         uint64_t hena;
6306
6307         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6308         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6309         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6310                 if (rss_hf != 0) /* Enable RSS */
6311                         return -EINVAL;
6312                 return 0; /* Nothing to do */
6313         }
6314         /* RSS enabled */
6315         if (rss_hf == 0) /* Disable RSS */
6316                 return -EINVAL;
6317
6318         return i40e_hw_rss_hash_set(pf, rss_conf);
6319 }
6320
6321 static int
6322 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6323                            struct rte_eth_rss_conf *rss_conf)
6324 {
6325         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6327         uint64_t hena;
6328
6329         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6330                          &rss_conf->rss_key_len);
6331
6332         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6333         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6334         rss_conf->rss_hf = i40e_parse_hena(hena);
6335
6336         return 0;
6337 }
6338
6339 static int
6340 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6341 {
6342         switch (filter_type) {
6343         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6344                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6345                 break;
6346         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6347                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6348                 break;
6349         case RTE_TUNNEL_FILTER_IMAC_TENID:
6350                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6351                 break;
6352         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6353                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6354                 break;
6355         case ETH_TUNNEL_FILTER_IMAC:
6356                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6357                 break;
6358         case ETH_TUNNEL_FILTER_OIP:
6359                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6360                 break;
6361         case ETH_TUNNEL_FILTER_IIP:
6362                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6363                 break;
6364         default:
6365                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6366                 return -EINVAL;
6367         }
6368
6369         return 0;
6370 }
6371
6372 static int
6373 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6374                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6375                         uint8_t add)
6376 {
6377         uint16_t ip_type;
6378         uint32_t ipv4_addr;
6379         uint8_t i, tun_type = 0;
6380         /* internal varialbe to convert ipv6 byte order */
6381         uint32_t convert_ipv6[4];
6382         int val, ret = 0;
6383         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6384         struct i40e_vsi *vsi = pf->main_vsi;
6385         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6386         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6387
6388         cld_filter = rte_zmalloc("tunnel_filter",
6389                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6390                 0);
6391
6392         if (NULL == cld_filter) {
6393                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6394                 return -EINVAL;
6395         }
6396         pfilter = cld_filter;
6397
6398         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6399         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6400
6401         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6402         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6403                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6404                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6405                 rte_memcpy(&pfilter->ipaddr.v4.data,
6406                                 &rte_cpu_to_le_32(ipv4_addr),
6407                                 sizeof(pfilter->ipaddr.v4.data));
6408         } else {
6409                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6410                 for (i = 0; i < 4; i++) {
6411                         convert_ipv6[i] =
6412                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6413                 }
6414                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6415                                 sizeof(pfilter->ipaddr.v6.data));
6416         }
6417
6418         /* check tunneled type */
6419         switch (tunnel_filter->tunnel_type) {
6420         case RTE_TUNNEL_TYPE_VXLAN:
6421                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6422                 break;
6423         case RTE_TUNNEL_TYPE_NVGRE:
6424                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6425                 break;
6426         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6427                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6428                 break;
6429         default:
6430                 /* Other tunnel types is not supported. */
6431                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6432                 rte_free(cld_filter);
6433                 return -EINVAL;
6434         }
6435
6436         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6437                                                 &pfilter->flags);
6438         if (val < 0) {
6439                 rte_free(cld_filter);
6440                 return -EINVAL;
6441         }
6442
6443         pfilter->flags |= rte_cpu_to_le_16(
6444                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6445                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6446         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6447         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6448
6449         if (add)
6450                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6451         else
6452                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6453                                                 cld_filter, 1);
6454
6455         rte_free(cld_filter);
6456         return ret;
6457 }
6458
6459 static int
6460 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6461 {
6462         uint8_t i;
6463
6464         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6465                 if (pf->vxlan_ports[i] == port)
6466                         return i;
6467         }
6468
6469         return -1;
6470 }
6471
6472 static int
6473 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6474 {
6475         int  idx, ret;
6476         uint8_t filter_idx;
6477         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6478
6479         idx = i40e_get_vxlan_port_idx(pf, port);
6480
6481         /* Check if port already exists */
6482         if (idx >= 0) {
6483                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6484                 return -EINVAL;
6485         }
6486
6487         /* Now check if there is space to add the new port */
6488         idx = i40e_get_vxlan_port_idx(pf, 0);
6489         if (idx < 0) {
6490                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6491                         "not adding port %d", port);
6492                 return -ENOSPC;
6493         }
6494
6495         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6496                                         &filter_idx, NULL);
6497         if (ret < 0) {
6498                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6499                 return -1;
6500         }
6501
6502         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6503                          port,  filter_idx);
6504
6505         /* New port: add it and mark its index in the bitmap */
6506         pf->vxlan_ports[idx] = port;
6507         pf->vxlan_bitmap |= (1 << idx);
6508
6509         if (!(pf->flags & I40E_FLAG_VXLAN))
6510                 pf->flags |= I40E_FLAG_VXLAN;
6511
6512         return 0;
6513 }
6514
6515 static int
6516 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6517 {
6518         int idx;
6519         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6520
6521         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6522                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6523                 return -EINVAL;
6524         }
6525
6526         idx = i40e_get_vxlan_port_idx(pf, port);
6527
6528         if (idx < 0) {
6529                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6530                 return -EINVAL;
6531         }
6532
6533         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6534                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6535                 return -1;
6536         }
6537
6538         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6539                         port, idx);
6540
6541         pf->vxlan_ports[idx] = 0;
6542         pf->vxlan_bitmap &= ~(1 << idx);
6543
6544         if (!pf->vxlan_bitmap)
6545                 pf->flags &= ~I40E_FLAG_VXLAN;
6546
6547         return 0;
6548 }
6549
6550 /* Add UDP tunneling port */
6551 static int
6552 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6553                              struct rte_eth_udp_tunnel *udp_tunnel)
6554 {
6555         int ret = 0;
6556         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6557
6558         if (udp_tunnel == NULL)
6559                 return -EINVAL;
6560
6561         switch (udp_tunnel->prot_type) {
6562         case RTE_TUNNEL_TYPE_VXLAN:
6563                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6564                 break;
6565
6566         case RTE_TUNNEL_TYPE_GENEVE:
6567         case RTE_TUNNEL_TYPE_TEREDO:
6568                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6569                 ret = -1;
6570                 break;
6571
6572         default:
6573                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6574                 ret = -1;
6575                 break;
6576         }
6577
6578         return ret;
6579 }
6580
6581 /* Remove UDP tunneling port */
6582 static int
6583 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6584                              struct rte_eth_udp_tunnel *udp_tunnel)
6585 {
6586         int ret = 0;
6587         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6588
6589         if (udp_tunnel == NULL)
6590                 return -EINVAL;
6591
6592         switch (udp_tunnel->prot_type) {
6593         case RTE_TUNNEL_TYPE_VXLAN:
6594                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6595                 break;
6596         case RTE_TUNNEL_TYPE_GENEVE:
6597         case RTE_TUNNEL_TYPE_TEREDO:
6598                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6599                 ret = -1;
6600                 break;
6601         default:
6602                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6603                 ret = -1;
6604                 break;
6605         }
6606
6607         return ret;
6608 }
6609
6610 /* Calculate the maximum number of contiguous PF queues that are configured */
6611 static int
6612 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6613 {
6614         struct rte_eth_dev_data *data = pf->dev_data;
6615         int i, num;
6616         struct i40e_rx_queue *rxq;
6617
6618         num = 0;
6619         for (i = 0; i < pf->lan_nb_qps; i++) {
6620                 rxq = data->rx_queues[i];
6621                 if (rxq && rxq->q_set)
6622                         num++;
6623                 else
6624                         break;
6625         }
6626
6627         return num;
6628 }
6629
6630 /* Configure RSS */
6631 static int
6632 i40e_pf_config_rss(struct i40e_pf *pf)
6633 {
6634         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6635         struct rte_eth_rss_conf rss_conf;
6636         uint32_t i, lut = 0;
6637         uint16_t j, num;
6638
6639         /*
6640          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6641          * It's necessary to calulate the actual PF queues that are configured.
6642          */
6643         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6644                 num = i40e_pf_calc_configured_queues_num(pf);
6645         else
6646                 num = pf->dev_data->nb_rx_queues;
6647
6648         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6649         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6650                         num);
6651
6652         if (num == 0) {
6653                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6654                 return -ENOTSUP;
6655         }
6656
6657         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6658                 if (j == num)
6659                         j = 0;
6660                 lut = (lut << 8) | (j & ((0x1 <<
6661                         hw->func_caps.rss_table_entry_width) - 1));
6662                 if ((i & 3) == 3)
6663                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6664         }
6665
6666         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6667         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6668                 i40e_pf_disable_rss(pf);
6669                 return 0;
6670         }
6671         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6672                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6673                 /* Random default keys */
6674                 static uint32_t rss_key_default[] = {0x6b793944,
6675                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6676                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6677                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6678
6679                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6680                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6681                                                         sizeof(uint32_t);
6682         }
6683
6684         return i40e_hw_rss_hash_set(pf, &rss_conf);
6685 }
6686
6687 static int
6688 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6689                                struct rte_eth_tunnel_filter_conf *filter)
6690 {
6691         if (pf == NULL || filter == NULL) {
6692                 PMD_DRV_LOG(ERR, "Invalid parameter");
6693                 return -EINVAL;
6694         }
6695
6696         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6697                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6698                 return -EINVAL;
6699         }
6700
6701         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6702                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6703                 return -EINVAL;
6704         }
6705
6706         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6707                 (is_zero_ether_addr(&filter->outer_mac))) {
6708                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6709                 return -EINVAL;
6710         }
6711
6712         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6713                 (is_zero_ether_addr(&filter->inner_mac))) {
6714                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6715                 return -EINVAL;
6716         }
6717
6718         return 0;
6719 }
6720
6721 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6722 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6723 static int
6724 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6725 {
6726         uint32_t val, reg;
6727         int ret = -EINVAL;
6728
6729         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6730         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6731
6732         if (len == 3) {
6733                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6734         } else if (len == 4) {
6735                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6736         } else {
6737                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6738                 return ret;
6739         }
6740
6741         if (reg != val) {
6742                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6743                                                    reg, NULL);
6744                 if (ret != 0)
6745                         return ret;
6746         } else {
6747                 ret = 0;
6748         }
6749         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6750                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6751
6752         return ret;
6753 }
6754
6755 static int
6756 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6757 {
6758         int ret = -EINVAL;
6759
6760         if (!hw || !cfg)
6761                 return -EINVAL;
6762
6763         switch (cfg->cfg_type) {
6764         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6765                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6766                 break;
6767         default:
6768                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6769                 break;
6770         }
6771
6772         return ret;
6773 }
6774
6775 static int
6776 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6777                                enum rte_filter_op filter_op,
6778                                void *arg)
6779 {
6780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6781         int ret = I40E_ERR_PARAM;
6782
6783         switch (filter_op) {
6784         case RTE_ETH_FILTER_SET:
6785                 ret = i40e_dev_global_config_set(hw,
6786                         (struct rte_eth_global_cfg *)arg);
6787                 break;
6788         default:
6789                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6790                 break;
6791         }
6792
6793         return ret;
6794 }
6795
6796 static int
6797 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6798                           enum rte_filter_op filter_op,
6799                           void *arg)
6800 {
6801         struct rte_eth_tunnel_filter_conf *filter;
6802         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6803         int ret = I40E_SUCCESS;
6804
6805         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6806
6807         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6808                 return I40E_ERR_PARAM;
6809
6810         switch (filter_op) {
6811         case RTE_ETH_FILTER_NOP:
6812                 if (!(pf->flags & I40E_FLAG_VXLAN))
6813                         ret = I40E_NOT_SUPPORTED;
6814                 break;
6815         case RTE_ETH_FILTER_ADD:
6816                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6817                 break;
6818         case RTE_ETH_FILTER_DELETE:
6819                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6820                 break;
6821         default:
6822                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6823                 ret = I40E_ERR_PARAM;
6824                 break;
6825         }
6826
6827         return ret;
6828 }
6829
6830 static int
6831 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6832 {
6833         int ret = 0;
6834         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6835
6836         /* RSS setup */
6837         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6838                 ret = i40e_pf_config_rss(pf);
6839         else
6840                 i40e_pf_disable_rss(pf);
6841
6842         return ret;
6843 }
6844
6845 /* Get the symmetric hash enable configurations per port */
6846 static void
6847 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6848 {
6849         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6850
6851         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6852 }
6853
6854 /* Set the symmetric hash enable configurations per port */
6855 static void
6856 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6857 {
6858         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6859
6860         if (enable > 0) {
6861                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6862                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6863                                                         "been enabled");
6864                         return;
6865                 }
6866                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6867         } else {
6868                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6869                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6870                                                         "been disabled");
6871                         return;
6872                 }
6873                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6874         }
6875         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6876         I40E_WRITE_FLUSH(hw);
6877 }
6878
6879 /*
6880  * Get global configurations of hash function type and symmetric hash enable
6881  * per flow type (pctype). Note that global configuration means it affects all
6882  * the ports on the same NIC.
6883  */
6884 static int
6885 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6886                                    struct rte_eth_hash_global_conf *g_cfg)
6887 {
6888         uint32_t reg, mask = I40E_FLOW_TYPES;
6889         uint16_t i;
6890         enum i40e_filter_pctype pctype;
6891
6892         memset(g_cfg, 0, sizeof(*g_cfg));
6893         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6894         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6895                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6896         else
6897                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6898         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6899                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6900
6901         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6902                 if (!(mask & (1UL << i)))
6903                         continue;
6904                 mask &= ~(1UL << i);
6905                 /* Bit set indicats the coresponding flow type is supported */
6906                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6907                 pctype = i40e_flowtype_to_pctype(i);
6908                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6909                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6910                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6911         }
6912
6913         return 0;
6914 }
6915
6916 static int
6917 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6918 {
6919         uint32_t i;
6920         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6921
6922         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6923                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6924                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6925                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6926                                                 g_cfg->hash_func);
6927                 return -EINVAL;
6928         }
6929
6930         /*
6931          * As i40e supports less than 32 flow types, only first 32 bits need to
6932          * be checked.
6933          */
6934         mask0 = g_cfg->valid_bit_mask[0];
6935         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6936                 if (i == 0) {
6937                         /* Check if any unsupported flow type configured */
6938                         if ((mask0 | i40e_mask) ^ i40e_mask)
6939                                 goto mask_err;
6940                 } else {
6941                         if (g_cfg->valid_bit_mask[i])
6942                                 goto mask_err;
6943                 }
6944         }
6945
6946         return 0;
6947
6948 mask_err:
6949         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6950
6951         return -EINVAL;
6952 }
6953
6954 /*
6955  * Set global configurations of hash function type and symmetric hash enable
6956  * per flow type (pctype). Note any modifying global configuration will affect
6957  * all the ports on the same NIC.
6958  */
6959 static int
6960 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6961                                    struct rte_eth_hash_global_conf *g_cfg)
6962 {
6963         int ret;
6964         uint16_t i;
6965         uint32_t reg;
6966         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6967         enum i40e_filter_pctype pctype;
6968
6969         /* Check the input parameters */
6970         ret = i40e_hash_global_config_check(g_cfg);
6971         if (ret < 0)
6972                 return ret;
6973
6974         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6975                 if (!(mask0 & (1UL << i)))
6976                         continue;
6977                 mask0 &= ~(1UL << i);
6978                 pctype = i40e_flowtype_to_pctype(i);
6979                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6980                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6981                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6982         }
6983
6984         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6985         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6986                 /* Toeplitz */
6987                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6988                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6989                                                                 "Toeplitz");
6990                         goto out;
6991                 }
6992                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6993         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6994                 /* Simple XOR */
6995                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6996                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6997                                                         "Simple XOR");
6998                         goto out;
6999                 }
7000                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7001         } else
7002                 /* Use the default, and keep it as it is */
7003                 goto out;
7004
7005         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7006
7007 out:
7008         I40E_WRITE_FLUSH(hw);
7009
7010         return 0;
7011 }
7012
7013 /**
7014  * Valid input sets for hash and flow director filters per PCTYPE
7015  */
7016 static uint64_t
7017 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7018                 enum rte_filter_type filter)
7019 {
7020         uint64_t valid;
7021
7022         static const uint64_t valid_hash_inset_table[] = {
7023                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7024                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7025                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7026                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7027                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7028                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7029                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7030                         I40E_INSET_FLEX_PAYLOAD,
7031                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7032                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7033                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7034                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7035                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7036                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7037                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7038                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7039                         I40E_INSET_FLEX_PAYLOAD,
7040                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7041                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7042                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7043                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7044                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7045                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7046                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7047                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7048                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7049                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7050                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7051                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7052                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7053                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7054                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7055                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7056                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7057                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7058                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7059                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7060                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7061                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7062                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7063                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7064                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7065                         I40E_INSET_FLEX_PAYLOAD,
7066                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7067                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7068                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7069                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7070                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7071                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7072                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7073                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7074                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7075                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7076                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7077                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7078                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7079                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7080                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7081                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7082                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7083                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7084                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7085                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7086                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7087                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7088                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7089                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7090                         I40E_INSET_FLEX_PAYLOAD,
7091                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7092                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7093                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7094                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7095                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7096                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7097                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7098                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7099                         I40E_INSET_FLEX_PAYLOAD,
7100                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7101                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7102                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7103                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7104                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7105                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7106                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7107                         I40E_INSET_FLEX_PAYLOAD,
7108                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7109                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7110                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7111                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7112                         I40E_INSET_FLEX_PAYLOAD,
7113         };
7114
7115         /**
7116          * Flow director supports only fields defined in
7117          * union rte_eth_fdir_flow.
7118          */
7119         static const uint64_t valid_fdir_inset_table[] = {
7120                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7121                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7122                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7123                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7124                 I40E_INSET_IPV4_TTL,
7125                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7126                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7127                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7128                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7129                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7130                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7131                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7132                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7133                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7134                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7135                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7136                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7137                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7138                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7139                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7140                 I40E_INSET_SCTP_VT,
7141                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7142                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7143                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7144                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7145                 I40E_INSET_IPV4_TTL,
7146                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7147                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7148                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7149                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7150                 I40E_INSET_IPV6_HOP_LIMIT,
7151                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7152                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7153                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7154                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7155                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7156                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7157                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7158                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7159                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7160                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7161                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7162                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7163                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7164                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7165                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7166                 I40E_INSET_SCTP_VT,
7167                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7168                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7169                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7170                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7171                 I40E_INSET_IPV6_HOP_LIMIT,
7172                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7173                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7174                 I40E_INSET_LAST_ETHER_TYPE,
7175         };
7176
7177         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7178                 return 0;
7179         if (filter == RTE_ETH_FILTER_HASH)
7180                 valid = valid_hash_inset_table[pctype];
7181         else
7182                 valid = valid_fdir_inset_table[pctype];
7183
7184         return valid;
7185 }
7186
7187 /**
7188  * Validate if the input set is allowed for a specific PCTYPE
7189  */
7190 static int
7191 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7192                 enum rte_filter_type filter, uint64_t inset)
7193 {
7194         uint64_t valid;
7195
7196         valid = i40e_get_valid_input_set(pctype, filter);
7197         if (inset & (~valid))
7198                 return -EINVAL;
7199
7200         return 0;
7201 }
7202
7203 /* default input set fields combination per pctype */
7204 static uint64_t
7205 i40e_get_default_input_set(uint16_t pctype)
7206 {
7207         static const uint64_t default_inset_table[] = {
7208                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7209                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7210                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7211                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7212                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7213                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7214                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7215                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7216                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7217                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7218                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7219                         I40E_INSET_SCTP_VT,
7220                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7221                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7222                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7223                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7224                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7225                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7226                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7227                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7228                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7229                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7230                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7231                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7232                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7233                         I40E_INSET_SCTP_VT,
7234                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7235                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7236                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7237                         I40E_INSET_LAST_ETHER_TYPE,
7238         };
7239
7240         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7241                 return 0;
7242
7243         return default_inset_table[pctype];
7244 }
7245
7246 /**
7247  * Parse the input set from index to logical bit masks
7248  */
7249 static int
7250 i40e_parse_input_set(uint64_t *inset,
7251                      enum i40e_filter_pctype pctype,
7252                      enum rte_eth_input_set_field *field,
7253                      uint16_t size)
7254 {
7255         uint16_t i, j;
7256         int ret = -EINVAL;
7257
7258         static const struct {
7259                 enum rte_eth_input_set_field field;
7260                 uint64_t inset;
7261         } inset_convert_table[] = {
7262                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7263                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7264                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7265                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7266                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7267                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7268                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7269                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7270                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7271                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7272                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7273                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7274                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7275                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7276                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7277                         I40E_INSET_IPV6_NEXT_HDR},
7278                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7279                         I40E_INSET_IPV6_HOP_LIMIT},
7280                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7281                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7282                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7283                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7284                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7285                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7286                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7287                         I40E_INSET_SCTP_VT},
7288                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7289                         I40E_INSET_TUNNEL_DMAC},
7290                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7291                         I40E_INSET_VLAN_TUNNEL},
7292                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7293                         I40E_INSET_TUNNEL_ID},
7294                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7295                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7296                         I40E_INSET_FLEX_PAYLOAD_W1},
7297                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7298                         I40E_INSET_FLEX_PAYLOAD_W2},
7299                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7300                         I40E_INSET_FLEX_PAYLOAD_W3},
7301                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7302                         I40E_INSET_FLEX_PAYLOAD_W4},
7303                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7304                         I40E_INSET_FLEX_PAYLOAD_W5},
7305                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7306                         I40E_INSET_FLEX_PAYLOAD_W6},
7307                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7308                         I40E_INSET_FLEX_PAYLOAD_W7},
7309                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7310                         I40E_INSET_FLEX_PAYLOAD_W8},
7311         };
7312
7313         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7314                 return ret;
7315
7316         /* Only one item allowed for default or all */
7317         if (size == 1) {
7318                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7319                         *inset = i40e_get_default_input_set(pctype);
7320                         return 0;
7321                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7322                         *inset = I40E_INSET_NONE;
7323                         return 0;
7324                 }
7325         }
7326
7327         for (i = 0, *inset = 0; i < size; i++) {
7328                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7329                         if (field[i] == inset_convert_table[j].field) {
7330                                 *inset |= inset_convert_table[j].inset;
7331                                 break;
7332                         }
7333                 }
7334
7335                 /* It contains unsupported input set, return immediately */
7336                 if (j == RTE_DIM(inset_convert_table))
7337                         return ret;
7338         }
7339
7340         return 0;
7341 }
7342
7343 /**
7344  * Translate the input set from bit masks to register aware bit masks
7345  * and vice versa
7346  */
7347 static uint64_t
7348 i40e_translate_input_set_reg(uint64_t input)
7349 {
7350         uint64_t val = 0;
7351         uint16_t i;
7352
7353         static const struct {
7354                 uint64_t inset;
7355                 uint64_t inset_reg;
7356         } inset_map[] = {
7357                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7358                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7359                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7360                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7361                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7362                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7363                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7364                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7365                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7366                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7367                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7368                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7369                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7370                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7371                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7372                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7373                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7374                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7375                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7376                 {I40E_INSET_TUNNEL_DMAC,
7377                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7378                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7379                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7380                 {I40E_INSET_TUNNEL_SRC_PORT,
7381                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7382                 {I40E_INSET_TUNNEL_DST_PORT,
7383                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7384                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7385                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7386                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7387                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7388                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7389                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7390                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7391                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7392                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7393         };
7394
7395         if (input == 0)
7396                 return val;
7397
7398         /* Translate input set to register aware inset */
7399         for (i = 0; i < RTE_DIM(inset_map); i++) {
7400                 if (input & inset_map[i].inset)
7401                         val |= inset_map[i].inset_reg;
7402         }
7403
7404         return val;
7405 }
7406
7407 static int
7408 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7409 {
7410         uint8_t i, idx = 0;
7411         uint64_t inset_need_mask = inset;
7412
7413         static const struct {
7414                 uint64_t inset;
7415                 uint32_t mask;
7416         } inset_mask_map[] = {
7417                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7418                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7419                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7420                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7421                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7422                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7423                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7424                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7425         };
7426
7427         if (!inset || !mask || !nb_elem)
7428                 return 0;
7429
7430         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7431                 /* Clear the inset bit, if no MASK is required,
7432                  * for example proto + ttl
7433                  */
7434                 if ((inset & inset_mask_map[i].inset) ==
7435                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7436                         inset_need_mask &= ~inset_mask_map[i].inset;
7437                 if (!inset_need_mask)
7438                         return 0;
7439         }
7440         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7441                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7442                     inset_mask_map[i].inset) {
7443                         if (idx >= nb_elem) {
7444                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7445                                 return -EINVAL;
7446                         }
7447                         mask[idx] = inset_mask_map[i].mask;
7448                         idx++;
7449                 }
7450         }
7451
7452         return idx;
7453 }
7454
7455 static void
7456 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7457 {
7458         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7459
7460         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7461         if (reg != val)
7462                 i40e_write_rx_ctl(hw, addr, val);
7463         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7464                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7465 }
7466
7467 static void
7468 i40e_filter_input_set_init(struct i40e_pf *pf)
7469 {
7470         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7471         enum i40e_filter_pctype pctype;
7472         uint64_t input_set, inset_reg;
7473         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7474         int num, i;
7475
7476         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7477              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7478                 if (!I40E_VALID_PCTYPE(pctype))
7479                         continue;
7480                 input_set = i40e_get_default_input_set(pctype);
7481
7482                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7483                                                    I40E_INSET_MASK_NUM_REG);
7484                 if (num < 0)
7485                         return;
7486                 inset_reg = i40e_translate_input_set_reg(input_set);
7487
7488                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7489                                       (uint32_t)(inset_reg & UINT32_MAX));
7490                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7491                                      (uint32_t)((inset_reg >>
7492                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7493                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7494                                       (uint32_t)(inset_reg & UINT32_MAX));
7495                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7496                                      (uint32_t)((inset_reg >>
7497                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7498
7499                 for (i = 0; i < num; i++) {
7500                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7501                                              mask_reg[i]);
7502                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7503                                              mask_reg[i]);
7504                 }
7505                 /*clear unused mask registers of the pctype */
7506                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7507                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7508                                              0);
7509                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7510                                              0);
7511                 }
7512                 I40E_WRITE_FLUSH(hw);
7513
7514                 /* store the default input set */
7515                 pf->hash_input_set[pctype] = input_set;
7516                 pf->fdir.input_set[pctype] = input_set;
7517         }
7518 }
7519
7520 int
7521 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7522                          struct rte_eth_input_set_conf *conf)
7523 {
7524         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7525         enum i40e_filter_pctype pctype;
7526         uint64_t input_set, inset_reg = 0;
7527         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7528         int ret, i, num;
7529
7530         if (!conf) {
7531                 PMD_DRV_LOG(ERR, "Invalid pointer");
7532                 return -EFAULT;
7533         }
7534         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7535             conf->op != RTE_ETH_INPUT_SET_ADD) {
7536                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7537                 return -EINVAL;
7538         }
7539
7540         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7541         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7542                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7543                             conf->flow_type);
7544                 return -EINVAL;
7545         }
7546
7547         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7548                                    conf->inset_size);
7549         if (ret) {
7550                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7551                 return -EINVAL;
7552         }
7553         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7554                                     input_set) != 0) {
7555                 PMD_DRV_LOG(ERR, "Invalid input set");
7556                 return -EINVAL;
7557         }
7558         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7559                 /* get inset value in register */
7560                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7561                 inset_reg <<= I40E_32_BIT_WIDTH;
7562                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7563                 input_set |= pf->hash_input_set[pctype];
7564         }
7565         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7566                                            I40E_INSET_MASK_NUM_REG);
7567         if (num < 0)
7568                 return -EINVAL;
7569
7570         inset_reg |= i40e_translate_input_set_reg(input_set);
7571
7572         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7573                               (uint32_t)(inset_reg & UINT32_MAX));
7574         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7575                              (uint32_t)((inset_reg >>
7576                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7577
7578         for (i = 0; i < num; i++)
7579                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7580                                      mask_reg[i]);
7581         /*clear unused mask registers of the pctype */
7582         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7583                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7584                                      0);
7585         I40E_WRITE_FLUSH(hw);
7586
7587         pf->hash_input_set[pctype] = input_set;
7588         return 0;
7589 }
7590
7591 int
7592 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7593                          struct rte_eth_input_set_conf *conf)
7594 {
7595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7596         enum i40e_filter_pctype pctype;
7597         uint64_t input_set, inset_reg = 0;
7598         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7599         int ret, i, num;
7600
7601         if (!hw || !conf) {
7602                 PMD_DRV_LOG(ERR, "Invalid pointer");
7603                 return -EFAULT;
7604         }
7605         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7606             conf->op != RTE_ETH_INPUT_SET_ADD) {
7607                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7608                 return -EINVAL;
7609         }
7610
7611         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7612         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7613                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7614                             conf->flow_type);
7615                 return -EINVAL;
7616         }
7617         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7618                                    conf->inset_size);
7619         if (ret) {
7620                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7621                 return -EINVAL;
7622         }
7623         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7624                                     input_set) != 0) {
7625                 PMD_DRV_LOG(ERR, "Invalid input set");
7626                 return -EINVAL;
7627         }
7628
7629         /* get inset value in register */
7630         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7631         inset_reg <<= I40E_32_BIT_WIDTH;
7632         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7633
7634         /* Can not change the inset reg for flex payload for fdir,
7635          * it is done by writing I40E_PRTQF_FD_FLXINSET
7636          * in i40e_set_flex_mask_on_pctype.
7637          */
7638         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7639                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7640         else
7641                 input_set |= pf->fdir.input_set[pctype];
7642         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7643                                            I40E_INSET_MASK_NUM_REG);
7644         if (num < 0)
7645                 return -EINVAL;
7646
7647         inset_reg |= i40e_translate_input_set_reg(input_set);
7648
7649         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7650                               (uint32_t)(inset_reg & UINT32_MAX));
7651         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7652                              (uint32_t)((inset_reg >>
7653                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7654
7655         for (i = 0; i < num; i++)
7656                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7657                                      mask_reg[i]);
7658         /*clear unused mask registers of the pctype */
7659         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7660                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7661                                      0);
7662         I40E_WRITE_FLUSH(hw);
7663
7664         pf->fdir.input_set[pctype] = input_set;
7665         return 0;
7666 }
7667
7668 static int
7669 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7670 {
7671         int ret = 0;
7672
7673         if (!hw || !info) {
7674                 PMD_DRV_LOG(ERR, "Invalid pointer");
7675                 return -EFAULT;
7676         }
7677
7678         switch (info->info_type) {
7679         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7680                 i40e_get_symmetric_hash_enable_per_port(hw,
7681                                         &(info->info.enable));
7682                 break;
7683         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7684                 ret = i40e_get_hash_filter_global_config(hw,
7685                                 &(info->info.global_conf));
7686                 break;
7687         default:
7688                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7689                                                         info->info_type);
7690                 ret = -EINVAL;
7691                 break;
7692         }
7693
7694         return ret;
7695 }
7696
7697 static int
7698 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7699 {
7700         int ret = 0;
7701
7702         if (!hw || !info) {
7703                 PMD_DRV_LOG(ERR, "Invalid pointer");
7704                 return -EFAULT;
7705         }
7706
7707         switch (info->info_type) {
7708         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7709                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7710                 break;
7711         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7712                 ret = i40e_set_hash_filter_global_config(hw,
7713                                 &(info->info.global_conf));
7714                 break;
7715         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7716                 ret = i40e_hash_filter_inset_select(hw,
7717                                                &(info->info.input_set_conf));
7718                 break;
7719
7720         default:
7721                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7722                                                         info->info_type);
7723                 ret = -EINVAL;
7724                 break;
7725         }
7726
7727         return ret;
7728 }
7729
7730 /* Operations for hash function */
7731 static int
7732 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7733                       enum rte_filter_op filter_op,
7734                       void *arg)
7735 {
7736         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7737         int ret = 0;
7738
7739         switch (filter_op) {
7740         case RTE_ETH_FILTER_NOP:
7741                 break;
7742         case RTE_ETH_FILTER_GET:
7743                 ret = i40e_hash_filter_get(hw,
7744                         (struct rte_eth_hash_filter_info *)arg);
7745                 break;
7746         case RTE_ETH_FILTER_SET:
7747                 ret = i40e_hash_filter_set(hw,
7748                         (struct rte_eth_hash_filter_info *)arg);
7749                 break;
7750         default:
7751                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7752                                                                 filter_op);
7753                 ret = -ENOTSUP;
7754                 break;
7755         }
7756
7757         return ret;
7758 }
7759
7760 /*
7761  * Configure ethertype filter, which can director packet by filtering
7762  * with mac address and ether_type or only ether_type
7763  */
7764 static int
7765 i40e_ethertype_filter_set(struct i40e_pf *pf,
7766                         struct rte_eth_ethertype_filter *filter,
7767                         bool add)
7768 {
7769         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7770         struct i40e_control_filter_stats stats;
7771         uint16_t flags = 0;
7772         int ret;
7773
7774         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7775                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7776                 return -EINVAL;
7777         }
7778         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7779                 filter->ether_type == ETHER_TYPE_IPv6) {
7780                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7781                         " control packet filter.", filter->ether_type);
7782                 return -EINVAL;
7783         }
7784         if (filter->ether_type == ETHER_TYPE_VLAN)
7785                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7786                         " not supported.");
7787
7788         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7789                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7790         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7791                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7792         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7793
7794         memset(&stats, 0, sizeof(stats));
7795         ret = i40e_aq_add_rem_control_packet_filter(hw,
7796                         filter->mac_addr.addr_bytes,
7797                         filter->ether_type, flags,
7798                         pf->main_vsi->seid,
7799                         filter->queue, add, &stats, NULL);
7800
7801         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7802                          " mac_etype_used = %u, etype_used = %u,"
7803                          " mac_etype_free = %u, etype_free = %u\n",
7804                          ret, stats.mac_etype_used, stats.etype_used,
7805                          stats.mac_etype_free, stats.etype_free);
7806         if (ret < 0)
7807                 return -ENOSYS;
7808         return 0;
7809 }
7810
7811 /*
7812  * Handle operations for ethertype filter.
7813  */
7814 static int
7815 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7816                                 enum rte_filter_op filter_op,
7817                                 void *arg)
7818 {
7819         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7820         int ret = 0;
7821
7822         if (filter_op == RTE_ETH_FILTER_NOP)
7823                 return ret;
7824
7825         if (arg == NULL) {
7826                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7827                             filter_op);
7828                 return -EINVAL;
7829         }
7830
7831         switch (filter_op) {
7832         case RTE_ETH_FILTER_ADD:
7833                 ret = i40e_ethertype_filter_set(pf,
7834                         (struct rte_eth_ethertype_filter *)arg,
7835                         TRUE);
7836                 break;
7837         case RTE_ETH_FILTER_DELETE:
7838                 ret = i40e_ethertype_filter_set(pf,
7839                         (struct rte_eth_ethertype_filter *)arg,
7840                         FALSE);
7841                 break;
7842         default:
7843                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7844                 ret = -ENOSYS;
7845                 break;
7846         }
7847         return ret;
7848 }
7849
7850 static int
7851 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7852                      enum rte_filter_type filter_type,
7853                      enum rte_filter_op filter_op,
7854                      void *arg)
7855 {
7856         int ret = 0;
7857
7858         if (dev == NULL)
7859                 return -EINVAL;
7860
7861         switch (filter_type) {
7862         case RTE_ETH_FILTER_NONE:
7863                 /* For global configuration */
7864                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7865                 break;
7866         case RTE_ETH_FILTER_HASH:
7867                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7868                 break;
7869         case RTE_ETH_FILTER_MACVLAN:
7870                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7871                 break;
7872         case RTE_ETH_FILTER_ETHERTYPE:
7873                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7874                 break;
7875         case RTE_ETH_FILTER_TUNNEL:
7876                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7877                 break;
7878         case RTE_ETH_FILTER_FDIR:
7879                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7880                 break;
7881         default:
7882                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7883                                                         filter_type);
7884                 ret = -EINVAL;
7885                 break;
7886         }
7887
7888         return ret;
7889 }
7890
7891 /*
7892  * Check and enable Extended Tag.
7893  * Enabling Extended Tag is important for 40G performance.
7894  */
7895 static void
7896 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7897 {
7898         uint32_t buf = 0;
7899         int ret;
7900
7901         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7902                                       PCI_DEV_CAP_REG);
7903         if (ret < 0) {
7904                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7905                             PCI_DEV_CAP_REG);
7906                 return;
7907         }
7908         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7909                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7910                 return;
7911         }
7912
7913         buf = 0;
7914         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7915                                       PCI_DEV_CTRL_REG);
7916         if (ret < 0) {
7917                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7918                             PCI_DEV_CTRL_REG);
7919                 return;
7920         }
7921         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7922                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7923                 return;
7924         }
7925         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7926         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7927                                        PCI_DEV_CTRL_REG);
7928         if (ret < 0) {
7929                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7930                             PCI_DEV_CTRL_REG);
7931                 return;
7932         }
7933 }
7934
7935 /*
7936  * As some registers wouldn't be reset unless a global hardware reset,
7937  * hardware initialization is needed to put those registers into an
7938  * expected initial state.
7939  */
7940 static void
7941 i40e_hw_init(struct rte_eth_dev *dev)
7942 {
7943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7944
7945         i40e_enable_extended_tag(dev);
7946
7947         /* clear the PF Queue Filter control register */
7948         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7949
7950         /* Disable symmetric hash per port */
7951         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7952 }
7953
7954 enum i40e_filter_pctype
7955 i40e_flowtype_to_pctype(uint16_t flow_type)
7956 {
7957         static const enum i40e_filter_pctype pctype_table[] = {
7958                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7959                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7960                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7961                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7962                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7963                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7964                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7965                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7966                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7967                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7968                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7969                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7970                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7971                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7972                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7973                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7974                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7975                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7976                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7977         };
7978
7979         return pctype_table[flow_type];
7980 }
7981
7982 uint16_t
7983 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7984 {
7985         static const uint16_t flowtype_table[] = {
7986                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7987                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7988                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7989                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7990                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7991                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7992                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7993                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7994                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7995                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7996                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7997                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7998                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7999                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8000                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8001                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8002                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8003                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8004                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8005         };
8006
8007         return flowtype_table[pctype];
8008 }
8009
8010 /*
8011  * On X710, performance number is far from the expectation on recent firmware
8012  * versions; on XL710, performance number is also far from the expectation on
8013  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8014  * mode is enabled and port MAC address is equal to the packet destination MAC
8015  * address. The fix for this issue may not be integrated in the following
8016  * firmware version. So the workaround in software driver is needed. It needs
8017  * to modify the initial values of 3 internal only registers for both X710 and
8018  * XL710. Note that the values for X710 or XL710 could be different, and the
8019  * workaround can be removed when it is fixed in firmware in the future.
8020  */
8021
8022 /* For both X710 and XL710 */
8023 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8024 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8025
8026 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8027 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8028
8029 /* For X710 */
8030 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8031 /* For XL710 */
8032 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8033 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8034
8035 static void
8036 i40e_configure_registers(struct i40e_hw *hw)
8037 {
8038         static struct {
8039                 uint32_t addr;
8040                 uint64_t val;
8041         } reg_table[] = {
8042                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8043                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8044                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8045         };
8046         uint64_t reg;
8047         uint32_t i;
8048         int ret;
8049
8050         for (i = 0; i < RTE_DIM(reg_table); i++) {
8051                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8052                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8053                                 reg_table[i].val =
8054                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8055                         else /* For X710 */
8056                                 reg_table[i].val =
8057                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8058                 }
8059
8060                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8061                                                         &reg, NULL);
8062                 if (ret < 0) {
8063                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8064                                                         reg_table[i].addr);
8065                         break;
8066                 }
8067                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8068                                                 reg_table[i].addr, reg);
8069                 if (reg == reg_table[i].val)
8070                         continue;
8071
8072                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8073                                                 reg_table[i].val, NULL);
8074                 if (ret < 0) {
8075                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8076                                 "address of 0x%"PRIx32, reg_table[i].val,
8077                                                         reg_table[i].addr);
8078                         break;
8079                 }
8080                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8081                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8082         }
8083 }
8084
8085 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8086 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8087 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8088 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8089 static int
8090 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8091 {
8092         uint32_t reg;
8093         int ret;
8094
8095         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8096                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8097                 return -EINVAL;
8098         }
8099
8100         /* Configure for double VLAN RX stripping */
8101         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8102         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8103                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8104                 ret = i40e_aq_debug_write_register(hw,
8105                                                    I40E_VSI_TSR(vsi->vsi_id),
8106                                                    reg, NULL);
8107                 if (ret < 0) {
8108                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8109                                     vsi->vsi_id);
8110                         return I40E_ERR_CONFIG;
8111                 }
8112         }
8113
8114         /* Configure for double VLAN TX insertion */
8115         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8116         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8117                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8118                 ret = i40e_aq_debug_write_register(hw,
8119                                                    I40E_VSI_L2TAGSTXVALID(
8120                                                    vsi->vsi_id), reg, NULL);
8121                 if (ret < 0) {
8122                         PMD_DRV_LOG(ERR, "Failed to update "
8123                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8124                         return I40E_ERR_CONFIG;
8125                 }
8126         }
8127
8128         return 0;
8129 }
8130
8131 /**
8132  * i40e_aq_add_mirror_rule
8133  * @hw: pointer to the hardware structure
8134  * @seid: VEB seid to add mirror rule to
8135  * @dst_id: destination vsi seid
8136  * @entries: Buffer which contains the entities to be mirrored
8137  * @count: number of entities contained in the buffer
8138  * @rule_id:the rule_id of the rule to be added
8139  *
8140  * Add a mirror rule for a given veb.
8141  *
8142  **/
8143 static enum i40e_status_code
8144 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8145                         uint16_t seid, uint16_t dst_id,
8146                         uint16_t rule_type, uint16_t *entries,
8147                         uint16_t count, uint16_t *rule_id)
8148 {
8149         struct i40e_aq_desc desc;
8150         struct i40e_aqc_add_delete_mirror_rule cmd;
8151         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8152                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8153                 &desc.params.raw;
8154         uint16_t buff_len;
8155         enum i40e_status_code status;
8156
8157         i40e_fill_default_direct_cmd_desc(&desc,
8158                                           i40e_aqc_opc_add_mirror_rule);
8159         memset(&cmd, 0, sizeof(cmd));
8160
8161         buff_len = sizeof(uint16_t) * count;
8162         desc.datalen = rte_cpu_to_le_16(buff_len);
8163         if (buff_len > 0)
8164                 desc.flags |= rte_cpu_to_le_16(
8165                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8166         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8167                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8168         cmd.num_entries = rte_cpu_to_le_16(count);
8169         cmd.seid = rte_cpu_to_le_16(seid);
8170         cmd.destination = rte_cpu_to_le_16(dst_id);
8171
8172         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8173         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8174         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8175                          "rule_id = %u"
8176                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8177                          hw->aq.asq_last_status, resp->rule_id,
8178                          resp->mirror_rules_used, resp->mirror_rules_free);
8179         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8180
8181         return status;
8182 }
8183
8184 /**
8185  * i40e_aq_del_mirror_rule
8186  * @hw: pointer to the hardware structure
8187  * @seid: VEB seid to add mirror rule to
8188  * @entries: Buffer which contains the entities to be mirrored
8189  * @count: number of entities contained in the buffer
8190  * @rule_id:the rule_id of the rule to be delete
8191  *
8192  * Delete a mirror rule for a given veb.
8193  *
8194  **/
8195 static enum i40e_status_code
8196 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8197                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8198                 uint16_t count, uint16_t rule_id)
8199 {
8200         struct i40e_aq_desc desc;
8201         struct i40e_aqc_add_delete_mirror_rule cmd;
8202         uint16_t buff_len = 0;
8203         enum i40e_status_code status;
8204         void *buff = NULL;
8205
8206         i40e_fill_default_direct_cmd_desc(&desc,
8207                                           i40e_aqc_opc_delete_mirror_rule);
8208         memset(&cmd, 0, sizeof(cmd));
8209         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8210                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8211                                                           I40E_AQ_FLAG_RD));
8212                 cmd.num_entries = count;
8213                 buff_len = sizeof(uint16_t) * count;
8214                 desc.datalen = rte_cpu_to_le_16(buff_len);
8215                 buff = (void *)entries;
8216         } else
8217                 /* rule id is filled in destination field for deleting mirror rule */
8218                 cmd.destination = rte_cpu_to_le_16(rule_id);
8219
8220         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8221                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8222         cmd.seid = rte_cpu_to_le_16(seid);
8223
8224         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8225         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8226
8227         return status;
8228 }
8229
8230 /**
8231  * i40e_mirror_rule_set
8232  * @dev: pointer to the hardware structure
8233  * @mirror_conf: mirror rule info
8234  * @sw_id: mirror rule's sw_id
8235  * @on: enable/disable
8236  *
8237  * set a mirror rule.
8238  *
8239  **/
8240 static int
8241 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8242                         struct rte_eth_mirror_conf *mirror_conf,
8243                         uint8_t sw_id, uint8_t on)
8244 {
8245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8247         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8248         struct i40e_mirror_rule *parent = NULL;
8249         uint16_t seid, dst_seid, rule_id;
8250         uint16_t i, j = 0;
8251         int ret;
8252
8253         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8254
8255         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8256                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8257                         " without veb or vfs.");
8258                 return -ENOSYS;
8259         }
8260         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8261                 PMD_DRV_LOG(ERR, "mirror table is full.");
8262                 return -ENOSPC;
8263         }
8264         if (mirror_conf->dst_pool > pf->vf_num) {
8265                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8266                                  mirror_conf->dst_pool);
8267                 return -EINVAL;
8268         }
8269
8270         seid = pf->main_vsi->veb->seid;
8271
8272         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8273                 if (sw_id <= it->index) {
8274                         mirr_rule = it;
8275                         break;
8276                 }
8277                 parent = it;
8278         }
8279         if (mirr_rule && sw_id == mirr_rule->index) {
8280                 if (on) {
8281                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8282                         return -EEXIST;
8283                 } else {
8284                         ret = i40e_aq_del_mirror_rule(hw, seid,
8285                                         mirr_rule->rule_type,
8286                                         mirr_rule->entries,
8287                                         mirr_rule->num_entries, mirr_rule->id);
8288                         if (ret < 0) {
8289                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8290                                                    " ret = %d, aq_err = %d.",
8291                                                    ret, hw->aq.asq_last_status);
8292                                 return -ENOSYS;
8293                         }
8294                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8295                         rte_free(mirr_rule);
8296                         pf->nb_mirror_rule--;
8297                         return 0;
8298                 }
8299         } else if (!on) {
8300                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8301                 return -ENOENT;
8302         }
8303
8304         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8305                                 sizeof(struct i40e_mirror_rule) , 0);
8306         if (!mirr_rule) {
8307                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8308                 return I40E_ERR_NO_MEMORY;
8309         }
8310         switch (mirror_conf->rule_type) {
8311         case ETH_MIRROR_VLAN:
8312                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8313                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8314                                 mirr_rule->entries[j] =
8315                                         mirror_conf->vlan.vlan_id[i];
8316                                 j++;
8317                         }
8318                 }
8319                 if (j == 0) {
8320                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8321                         rte_free(mirr_rule);
8322                         return -EINVAL;
8323                 }
8324                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8325                 break;
8326         case ETH_MIRROR_VIRTUAL_POOL_UP:
8327         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8328                 /* check if the specified pool bit is out of range */
8329                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8330                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8331                         rte_free(mirr_rule);
8332                         return -EINVAL;
8333                 }
8334                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8335                         if (mirror_conf->pool_mask & (1ULL << i)) {
8336                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8337                                 j++;
8338                         }
8339                 }
8340                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8341                         /* add pf vsi to entries */
8342                         mirr_rule->entries[j] = pf->main_vsi_seid;
8343                         j++;
8344                 }
8345                 if (j == 0) {
8346                         PMD_DRV_LOG(ERR, "pool is not specified.");
8347                         rte_free(mirr_rule);
8348                         return -EINVAL;
8349                 }
8350                 /* egress and ingress in aq commands means from switch but not port */
8351                 mirr_rule->rule_type =
8352                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8353                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8354                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8355                 break;
8356         case ETH_MIRROR_UPLINK_PORT:
8357                 /* egress and ingress in aq commands means from switch but not port*/
8358                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8359                 break;
8360         case ETH_MIRROR_DOWNLINK_PORT:
8361                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8362                 break;
8363         default:
8364                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8365                         mirror_conf->rule_type);
8366                 rte_free(mirr_rule);
8367                 return -EINVAL;
8368         }
8369
8370         /* If the dst_pool is equal to vf_num, consider it as PF */
8371         if (mirror_conf->dst_pool == pf->vf_num)
8372                 dst_seid = pf->main_vsi_seid;
8373         else
8374                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8375
8376         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8377                                       mirr_rule->rule_type, mirr_rule->entries,
8378                                       j, &rule_id);
8379         if (ret < 0) {
8380                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8381                                    " ret = %d, aq_err = %d.",
8382                                    ret, hw->aq.asq_last_status);
8383                 rte_free(mirr_rule);
8384                 return -ENOSYS;
8385         }
8386
8387         mirr_rule->index = sw_id;
8388         mirr_rule->num_entries = j;
8389         mirr_rule->id = rule_id;
8390         mirr_rule->dst_vsi_seid = dst_seid;
8391
8392         if (parent)
8393                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8394         else
8395                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8396
8397         pf->nb_mirror_rule++;
8398         return 0;
8399 }
8400
8401 /**
8402  * i40e_mirror_rule_reset
8403  * @dev: pointer to the device
8404  * @sw_id: mirror rule's sw_id
8405  *
8406  * reset a mirror rule.
8407  *
8408  **/
8409 static int
8410 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8411 {
8412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8414         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8415         uint16_t seid;
8416         int ret;
8417
8418         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8419
8420         seid = pf->main_vsi->veb->seid;
8421
8422         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8423                 if (sw_id == it->index) {
8424                         mirr_rule = it;
8425                         break;
8426                 }
8427         }
8428         if (mirr_rule) {
8429                 ret = i40e_aq_del_mirror_rule(hw, seid,
8430                                 mirr_rule->rule_type,
8431                                 mirr_rule->entries,
8432                                 mirr_rule->num_entries, mirr_rule->id);
8433                 if (ret < 0) {
8434                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8435                                            " status = %d, aq_err = %d.",
8436                                            ret, hw->aq.asq_last_status);
8437                         return -ENOSYS;
8438                 }
8439                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8440                 rte_free(mirr_rule);
8441                 pf->nb_mirror_rule--;
8442         } else {
8443                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8444                 return -ENOENT;
8445         }
8446         return 0;
8447 }
8448
8449 static uint64_t
8450 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8451 {
8452         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8453         uint64_t systim_cycles;
8454
8455         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8456         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8457                         << 32;
8458
8459         return systim_cycles;
8460 }
8461
8462 static uint64_t
8463 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8464 {
8465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8466         uint64_t rx_tstamp;
8467
8468         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8469         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8470                         << 32;
8471
8472         return rx_tstamp;
8473 }
8474
8475 static uint64_t
8476 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8477 {
8478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8479         uint64_t tx_tstamp;
8480
8481         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8482         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8483                         << 32;
8484
8485         return tx_tstamp;
8486 }
8487
8488 static void
8489 i40e_start_timecounters(struct rte_eth_dev *dev)
8490 {
8491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8492         struct i40e_adapter *adapter =
8493                         (struct i40e_adapter *)dev->data->dev_private;
8494         struct rte_eth_link link;
8495         uint32_t tsync_inc_l;
8496         uint32_t tsync_inc_h;
8497
8498         /* Get current link speed. */
8499         memset(&link, 0, sizeof(link));
8500         i40e_dev_link_update(dev, 1);
8501         rte_i40e_dev_atomic_read_link_status(dev, &link);
8502
8503         switch (link.link_speed) {
8504         case ETH_SPEED_NUM_40G:
8505                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8506                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8507                 break;
8508         case ETH_SPEED_NUM_10G:
8509                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8510                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8511                 break;
8512         case ETH_SPEED_NUM_1G:
8513                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8514                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8515                 break;
8516         default:
8517                 tsync_inc_l = 0x0;
8518                 tsync_inc_h = 0x0;
8519         }
8520
8521         /* Set the timesync increment value. */
8522         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8523         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8524
8525         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8526         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8527         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8528
8529         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8530         adapter->systime_tc.cc_shift = 0;
8531         adapter->systime_tc.nsec_mask = 0;
8532
8533         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8534         adapter->rx_tstamp_tc.cc_shift = 0;
8535         adapter->rx_tstamp_tc.nsec_mask = 0;
8536
8537         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8538         adapter->tx_tstamp_tc.cc_shift = 0;
8539         adapter->tx_tstamp_tc.nsec_mask = 0;
8540 }
8541
8542 static int
8543 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8544 {
8545         struct i40e_adapter *adapter =
8546                         (struct i40e_adapter *)dev->data->dev_private;
8547
8548         adapter->systime_tc.nsec += delta;
8549         adapter->rx_tstamp_tc.nsec += delta;
8550         adapter->tx_tstamp_tc.nsec += delta;
8551
8552         return 0;
8553 }
8554
8555 static int
8556 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8557 {
8558         uint64_t ns;
8559         struct i40e_adapter *adapter =
8560                         (struct i40e_adapter *)dev->data->dev_private;
8561
8562         ns = rte_timespec_to_ns(ts);
8563
8564         /* Set the timecounters to a new value. */
8565         adapter->systime_tc.nsec = ns;
8566         adapter->rx_tstamp_tc.nsec = ns;
8567         adapter->tx_tstamp_tc.nsec = ns;
8568
8569         return 0;
8570 }
8571
8572 static int
8573 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8574 {
8575         uint64_t ns, systime_cycles;
8576         struct i40e_adapter *adapter =
8577                         (struct i40e_adapter *)dev->data->dev_private;
8578
8579         systime_cycles = i40e_read_systime_cyclecounter(dev);
8580         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8581         *ts = rte_ns_to_timespec(ns);
8582
8583         return 0;
8584 }
8585
8586 static int
8587 i40e_timesync_enable(struct rte_eth_dev *dev)
8588 {
8589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8590         uint32_t tsync_ctl_l;
8591         uint32_t tsync_ctl_h;
8592
8593         /* Stop the timesync system time. */
8594         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8595         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8596         /* Reset the timesync system time value. */
8597         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8598         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8599
8600         i40e_start_timecounters(dev);
8601
8602         /* Clear timesync registers. */
8603         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8604         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8605         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8606         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8607         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8608         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8609
8610         /* Enable timestamping of PTP packets. */
8611         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8612         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8613
8614         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8615         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8616         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8617
8618         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8619         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8620
8621         return 0;
8622 }
8623
8624 static int
8625 i40e_timesync_disable(struct rte_eth_dev *dev)
8626 {
8627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8628         uint32_t tsync_ctl_l;
8629         uint32_t tsync_ctl_h;
8630
8631         /* Disable timestamping of transmitted PTP packets. */
8632         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8633         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8634
8635         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8636         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8637
8638         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8639         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8640
8641         /* Reset the timesync increment value. */
8642         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8643         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8644
8645         return 0;
8646 }
8647
8648 static int
8649 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8650                                 struct timespec *timestamp, uint32_t flags)
8651 {
8652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8653         struct i40e_adapter *adapter =
8654                 (struct i40e_adapter *)dev->data->dev_private;
8655
8656         uint32_t sync_status;
8657         uint32_t index = flags & 0x03;
8658         uint64_t rx_tstamp_cycles;
8659         uint64_t ns;
8660
8661         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8662         if ((sync_status & (1 << index)) == 0)
8663                 return -EINVAL;
8664
8665         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8666         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8667         *timestamp = rte_ns_to_timespec(ns);
8668
8669         return 0;
8670 }
8671
8672 static int
8673 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8674                                 struct timespec *timestamp)
8675 {
8676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8677         struct i40e_adapter *adapter =
8678                 (struct i40e_adapter *)dev->data->dev_private;
8679
8680         uint32_t sync_status;
8681         uint64_t tx_tstamp_cycles;
8682         uint64_t ns;
8683
8684         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8685         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8686                 return -EINVAL;
8687
8688         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8689         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8690         *timestamp = rte_ns_to_timespec(ns);
8691
8692         return 0;
8693 }
8694
8695 /*
8696  * i40e_parse_dcb_configure - parse dcb configure from user
8697  * @dev: the device being configured
8698  * @dcb_cfg: pointer of the result of parse
8699  * @*tc_map: bit map of enabled traffic classes
8700  *
8701  * Returns 0 on success, negative value on failure
8702  */
8703 static int
8704 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8705                          struct i40e_dcbx_config *dcb_cfg,
8706                          uint8_t *tc_map)
8707 {
8708         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8709         uint8_t i, tc_bw, bw_lf;
8710
8711         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8712
8713         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8714         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8715                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8716                 return -EINVAL;
8717         }
8718
8719         /* assume each tc has the same bw */
8720         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8721         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8722                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8723         /* to ensure the sum of tcbw is equal to 100 */
8724         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8725         for (i = 0; i < bw_lf; i++)
8726                 dcb_cfg->etscfg.tcbwtable[i]++;
8727
8728         /* assume each tc has the same Transmission Selection Algorithm */
8729         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8730                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8731
8732         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8733                 dcb_cfg->etscfg.prioritytable[i] =
8734                                 dcb_rx_conf->dcb_tc[i];
8735
8736         /* FW needs one App to configure HW */
8737         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8738         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8739         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8740         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8741
8742         if (dcb_rx_conf->nb_tcs == 0)
8743                 *tc_map = 1; /* tc0 only */
8744         else
8745                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8746
8747         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8748                 dcb_cfg->pfc.willing = 0;
8749                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8750                 dcb_cfg->pfc.pfcenable = *tc_map;
8751         }
8752         return 0;
8753 }
8754
8755
8756 static enum i40e_status_code
8757 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8758                               struct i40e_aqc_vsi_properties_data *info,
8759                               uint8_t enabled_tcmap)
8760 {
8761         enum i40e_status_code ret;
8762         int i, total_tc = 0;
8763         uint16_t qpnum_per_tc, bsf, qp_idx;
8764         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8765         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8766         uint16_t used_queues;
8767
8768         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8769         if (ret != I40E_SUCCESS)
8770                 return ret;
8771
8772         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8773                 if (enabled_tcmap & (1 << i))
8774                         total_tc++;
8775         }
8776         if (total_tc == 0)
8777                 total_tc = 1;
8778         vsi->enabled_tc = enabled_tcmap;
8779
8780         /* different VSI has different queues assigned */
8781         if (vsi->type == I40E_VSI_MAIN)
8782                 used_queues = dev_data->nb_rx_queues -
8783                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8784         else if (vsi->type == I40E_VSI_VMDQ2)
8785                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8786         else {
8787                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8788                 return I40E_ERR_NO_AVAILABLE_VSI;
8789         }
8790
8791         qpnum_per_tc = used_queues / total_tc;
8792         /* Number of queues per enabled TC */
8793         if (qpnum_per_tc == 0) {
8794                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8795                 return I40E_ERR_INVALID_QP_ID;
8796         }
8797         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8798                                 I40E_MAX_Q_PER_TC);
8799         bsf = rte_bsf32(qpnum_per_tc);
8800
8801         /**
8802          * Configure TC and queue mapping parameters, for enabled TC,
8803          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8804          * default queue will serve it.
8805          */
8806         qp_idx = 0;
8807         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8808                 if (vsi->enabled_tc & (1 << i)) {
8809                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8810                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8811                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8812                         qp_idx += qpnum_per_tc;
8813                 } else
8814                         info->tc_mapping[i] = 0;
8815         }
8816
8817         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8818         if (vsi->type == I40E_VSI_SRIOV) {
8819                 info->mapping_flags |=
8820                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8821                 for (i = 0; i < vsi->nb_qps; i++)
8822                         info->queue_mapping[i] =
8823                                 rte_cpu_to_le_16(vsi->base_queue + i);
8824         } else {
8825                 info->mapping_flags |=
8826                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8827                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8828         }
8829         info->valid_sections |=
8830                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8831
8832         return I40E_SUCCESS;
8833 }
8834
8835 /*
8836  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8837  * @veb: VEB to be configured
8838  * @tc_map: enabled TC bitmap
8839  *
8840  * Returns 0 on success, negative value on failure
8841  */
8842 static enum i40e_status_code
8843 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8844 {
8845         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8846         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8847         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8848         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8849         enum i40e_status_code ret = I40E_SUCCESS;
8850         int i;
8851         uint32_t bw_max;
8852
8853         /* Check if enabled_tc is same as existing or new TCs */
8854         if (veb->enabled_tc == tc_map)
8855                 return ret;
8856
8857         /* configure tc bandwidth */
8858         memset(&veb_bw, 0, sizeof(veb_bw));
8859         veb_bw.tc_valid_bits = tc_map;
8860         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8861         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8862                 if (tc_map & BIT_ULL(i))
8863                         veb_bw.tc_bw_share_credits[i] = 1;
8864         }
8865         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8866                                                    &veb_bw, NULL);
8867         if (ret) {
8868                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8869                                   " per TC failed = %d",
8870                                   hw->aq.asq_last_status);
8871                 return ret;
8872         }
8873
8874         memset(&ets_query, 0, sizeof(ets_query));
8875         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8876                                                    &ets_query, NULL);
8877         if (ret != I40E_SUCCESS) {
8878                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8879                                  " configuration %u", hw->aq.asq_last_status);
8880                 return ret;
8881         }
8882         memset(&bw_query, 0, sizeof(bw_query));
8883         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8884                                                   &bw_query, NULL);
8885         if (ret != I40E_SUCCESS) {
8886                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8887                                  " configuration %u", hw->aq.asq_last_status);
8888                 return ret;
8889         }
8890
8891         /* store and print out BW info */
8892         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8893         veb->bw_info.bw_max = ets_query.tc_bw_max;
8894         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8895         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8896         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8897                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8898                      I40E_16_BIT_WIDTH);
8899         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8900                 veb->bw_info.bw_ets_share_credits[i] =
8901                                 bw_query.tc_bw_share_credits[i];
8902                 veb->bw_info.bw_ets_credits[i] =
8903                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8904                 /* 4 bits per TC, 4th bit is reserved */
8905                 veb->bw_info.bw_ets_max[i] =
8906                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8907                                   RTE_LEN2MASK(3, uint8_t));
8908                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8909                             veb->bw_info.bw_ets_share_credits[i]);
8910                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8911                             veb->bw_info.bw_ets_credits[i]);
8912                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8913                             veb->bw_info.bw_ets_max[i]);
8914         }
8915
8916         veb->enabled_tc = tc_map;
8917
8918         return ret;
8919 }
8920
8921
8922 /*
8923  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8924  * @vsi: VSI to be configured
8925  * @tc_map: enabled TC bitmap
8926  *
8927  * Returns 0 on success, negative value on failure
8928  */
8929 static enum i40e_status_code
8930 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8931 {
8932         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8933         struct i40e_vsi_context ctxt;
8934         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8935         enum i40e_status_code ret = I40E_SUCCESS;
8936         int i;
8937
8938         /* Check if enabled_tc is same as existing or new TCs */
8939         if (vsi->enabled_tc == tc_map)
8940                 return ret;
8941
8942         /* configure tc bandwidth */
8943         memset(&bw_data, 0, sizeof(bw_data));
8944         bw_data.tc_valid_bits = tc_map;
8945         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8946         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8947                 if (tc_map & BIT_ULL(i))
8948                         bw_data.tc_bw_credits[i] = 1;
8949         }
8950         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8951         if (ret) {
8952                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8953                         " per TC failed = %d",
8954                         hw->aq.asq_last_status);
8955                 goto out;
8956         }
8957         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8958                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8959
8960         /* Update Queue Pairs Mapping for currently enabled UPs */
8961         ctxt.seid = vsi->seid;
8962         ctxt.pf_num = hw->pf_id;
8963         ctxt.vf_num = 0;
8964         ctxt.uplink_seid = vsi->uplink_seid;
8965         ctxt.info = vsi->info;
8966         i40e_get_cap(hw);
8967         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8968         if (ret)
8969                 goto out;
8970
8971         /* Update the VSI after updating the VSI queue-mapping information */
8972         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8973         if (ret) {
8974                 PMD_INIT_LOG(ERR, "Failed to configure "
8975                             "TC queue mapping = %d",
8976                             hw->aq.asq_last_status);
8977                 goto out;
8978         }
8979         /* update the local VSI info with updated queue map */
8980         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8981                                         sizeof(vsi->info.tc_mapping));
8982         (void)rte_memcpy(&vsi->info.queue_mapping,
8983                         &ctxt.info.queue_mapping,
8984                 sizeof(vsi->info.queue_mapping));
8985         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8986         vsi->info.valid_sections = 0;
8987
8988         /* query and update current VSI BW information */
8989         ret = i40e_vsi_get_bw_config(vsi);
8990         if (ret) {
8991                 PMD_INIT_LOG(ERR,
8992                          "Failed updating vsi bw info, err %s aq_err %s",
8993                          i40e_stat_str(hw, ret),
8994                          i40e_aq_str(hw, hw->aq.asq_last_status));
8995                 goto out;
8996         }
8997
8998         vsi->enabled_tc = tc_map;
8999
9000 out:
9001         return ret;
9002 }
9003
9004 /*
9005  * i40e_dcb_hw_configure - program the dcb setting to hw
9006  * @pf: pf the configuration is taken on
9007  * @new_cfg: new configuration
9008  * @tc_map: enabled TC bitmap
9009  *
9010  * Returns 0 on success, negative value on failure
9011  */
9012 static enum i40e_status_code
9013 i40e_dcb_hw_configure(struct i40e_pf *pf,
9014                       struct i40e_dcbx_config *new_cfg,
9015                       uint8_t tc_map)
9016 {
9017         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9018         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9019         struct i40e_vsi *main_vsi = pf->main_vsi;
9020         struct i40e_vsi_list *vsi_list;
9021         enum i40e_status_code ret;
9022         int i;
9023         uint32_t val;
9024
9025         /* Use the FW API if FW > v4.4*/
9026         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9027               (hw->aq.fw_maj_ver >= 5))) {
9028                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9029                                   " to configure DCB");
9030                 return I40E_ERR_FIRMWARE_API_VERSION;
9031         }
9032
9033         /* Check if need reconfiguration */
9034         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9035                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9036                 return I40E_SUCCESS;
9037         }
9038
9039         /* Copy the new config to the current config */
9040         *old_cfg = *new_cfg;
9041         old_cfg->etsrec = old_cfg->etscfg;
9042         ret = i40e_set_dcb_config(hw);
9043         if (ret) {
9044                 PMD_INIT_LOG(ERR,
9045                          "Set DCB Config failed, err %s aq_err %s\n",
9046                          i40e_stat_str(hw, ret),
9047                          i40e_aq_str(hw, hw->aq.asq_last_status));
9048                 return ret;
9049         }
9050         /* set receive Arbiter to RR mode and ETS scheme by default */
9051         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9052                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9053                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9054                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9055                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9056                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9057                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9058                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9059                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9060                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9061                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9062                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9063                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9064         }
9065         /* get local mib to check whether it is configured correctly */
9066         /* IEEE mode */
9067         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9068         /* Get Local DCB Config */
9069         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9070                                      &hw->local_dcbx_config);
9071
9072         /* if Veb is created, need to update TC of it at first */
9073         if (main_vsi->veb) {
9074                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9075                 if (ret)
9076                         PMD_INIT_LOG(WARNING,
9077                                  "Failed configuring TC for VEB seid=%d\n",
9078                                  main_vsi->veb->seid);
9079         }
9080         /* Update each VSI */
9081         i40e_vsi_config_tc(main_vsi, tc_map);
9082         if (main_vsi->veb) {
9083                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9084                         /* Beside main VSI and VMDQ VSIs, only enable default
9085                          * TC for other VSIs
9086                          */
9087                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9088                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9089                                                          tc_map);
9090                         else
9091                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9092                                                          I40E_DEFAULT_TCMAP);
9093                         if (ret)
9094                                 PMD_INIT_LOG(WARNING,
9095                                          "Failed configuring TC for VSI seid=%d\n",
9096                                          vsi_list->vsi->seid);
9097                         /* continue */
9098                 }
9099         }
9100         return I40E_SUCCESS;
9101 }
9102
9103 /*
9104  * i40e_dcb_init_configure - initial dcb config
9105  * @dev: device being configured
9106  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9107  *
9108  * Returns 0 on success, negative value on failure
9109  */
9110 static int
9111 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9112 {
9113         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9115         int ret = 0;
9116
9117         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9118                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9119                 return -ENOTSUP;
9120         }
9121
9122         /* DCB initialization:
9123          * Update DCB configuration from the Firmware and configure
9124          * LLDP MIB change event.
9125          */
9126         if (sw_dcb == TRUE) {
9127                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9128                 if (ret != I40E_SUCCESS)
9129                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9130
9131                 ret = i40e_init_dcb(hw);
9132                 /* if sw_dcb, lldp agent is stopped, the return from
9133                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9134                  * adminq status.
9135                  */
9136                 if (ret != I40E_SUCCESS &&
9137                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9138                         memset(&hw->local_dcbx_config, 0,
9139                                 sizeof(struct i40e_dcbx_config));
9140                         /* set dcb default configuration */
9141                         hw->local_dcbx_config.etscfg.willing = 0;
9142                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9143                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9144                         hw->local_dcbx_config.etscfg.tsatable[0] =
9145                                                 I40E_IEEE_TSA_ETS;
9146                         hw->local_dcbx_config.etsrec =
9147                                 hw->local_dcbx_config.etscfg;
9148                         hw->local_dcbx_config.pfc.willing = 0;
9149                         hw->local_dcbx_config.pfc.pfccap =
9150                                                 I40E_MAX_TRAFFIC_CLASS;
9151                         /* FW needs one App to configure HW */
9152                         hw->local_dcbx_config.numapps = 1;
9153                         hw->local_dcbx_config.app[0].selector =
9154                                                 I40E_APP_SEL_ETHTYPE;
9155                         hw->local_dcbx_config.app[0].priority = 3;
9156                         hw->local_dcbx_config.app[0].protocolid =
9157                                                 I40E_APP_PROTOID_FCOE;
9158                         ret = i40e_set_dcb_config(hw);
9159                         if (ret) {
9160                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9161                                         " err = %d, aq_err = %d.", ret,
9162                                           hw->aq.asq_last_status);
9163                                 return -ENOSYS;
9164                         }
9165                 } else {
9166                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9167                                           " aq_err = %d.", ret,
9168                                           hw->aq.asq_last_status);
9169                         return -ENOTSUP;
9170                 }
9171         } else {
9172                 ret = i40e_aq_start_lldp(hw, NULL);
9173                 if (ret != I40E_SUCCESS)
9174                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9175
9176                 ret = i40e_init_dcb(hw);
9177                 if (!ret) {
9178                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9179                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9180                                                   " DCBX offload.");
9181                                 return -ENOTSUP;
9182                         }
9183                 } else {
9184                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9185                                           " aq_err = %d.", ret,
9186                                           hw->aq.asq_last_status);
9187                         return -ENOTSUP;
9188                 }
9189         }
9190         return 0;
9191 }
9192
9193 /*
9194  * i40e_dcb_setup - setup dcb related config
9195  * @dev: device being configured
9196  *
9197  * Returns 0 on success, negative value on failure
9198  */
9199 static int
9200 i40e_dcb_setup(struct rte_eth_dev *dev)
9201 {
9202         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9203         struct i40e_dcbx_config dcb_cfg;
9204         uint8_t tc_map = 0;
9205         int ret = 0;
9206
9207         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9208                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9209                 return -ENOTSUP;
9210         }
9211
9212         if (pf->vf_num != 0)
9213                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9214
9215         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9216         if (ret) {
9217                 PMD_INIT_LOG(ERR, "invalid dcb config");
9218                 return -EINVAL;
9219         }
9220         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9221         if (ret) {
9222                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9223                 return -ENOSYS;
9224         }
9225
9226         return 0;
9227 }
9228
9229 static int
9230 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9231                       struct rte_eth_dcb_info *dcb_info)
9232 {
9233         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9234         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9235         struct i40e_vsi *vsi = pf->main_vsi;
9236         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9237         uint16_t bsf, tc_mapping;
9238         int i, j = 0;
9239
9240         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9241                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9242         else
9243                 dcb_info->nb_tcs = 1;
9244         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9245                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9246         for (i = 0; i < dcb_info->nb_tcs; i++)
9247                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9248
9249         /* get queue mapping if vmdq is disabled */
9250         if (!pf->nb_cfg_vmdq_vsi) {
9251                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9252                         if (!(vsi->enabled_tc & (1 << i)))
9253                                 continue;
9254                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9255                         dcb_info->tc_queue.tc_rxq[j][i].base =
9256                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9257                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9258                         dcb_info->tc_queue.tc_txq[j][i].base =
9259                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9260                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9261                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9262                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9263                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9264                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9265                 }
9266                 return 0;
9267         }
9268
9269         /* get queue mapping if vmdq is enabled */
9270         do {
9271                 vsi = pf->vmdq[j].vsi;
9272                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9273                         if (!(vsi->enabled_tc & (1 << i)))
9274                                 continue;
9275                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9276                         dcb_info->tc_queue.tc_rxq[j][i].base =
9277                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9278                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9279                         dcb_info->tc_queue.tc_txq[j][i].base =
9280                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9281                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9282                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9283                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9284                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9285                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9286                 }
9287                 j++;
9288         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9289         return 0;
9290 }
9291
9292 static int
9293 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9294 {
9295         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9296         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9297         uint16_t interval =
9298                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9299         uint16_t msix_intr;
9300
9301         msix_intr = intr_handle->intr_vec[queue_id];
9302         if (msix_intr == I40E_MISC_VEC_ID)
9303                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9304                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9305                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9306                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9307                                (interval <<
9308                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9309         else
9310                 I40E_WRITE_REG(hw,
9311                                I40E_PFINT_DYN_CTLN(msix_intr -
9312                                                    I40E_RX_VEC_START),
9313                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9314                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9315                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9316                                (interval <<
9317                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9318
9319         I40E_WRITE_FLUSH(hw);
9320         rte_intr_enable(&dev->pci_dev->intr_handle);
9321
9322         return 0;
9323 }
9324
9325 static int
9326 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9327 {
9328         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9329         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9330         uint16_t msix_intr;
9331
9332         msix_intr = intr_handle->intr_vec[queue_id];
9333         if (msix_intr == I40E_MISC_VEC_ID)
9334                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9335         else
9336                 I40E_WRITE_REG(hw,
9337                                I40E_PFINT_DYN_CTLN(msix_intr -
9338                                                    I40E_RX_VEC_START),
9339                                0);
9340         I40E_WRITE_FLUSH(hw);
9341
9342         return 0;
9343 }
9344
9345 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9346 {
9347         /* Highest base addr + 32-bit word */
9348         return I40E_GLGEN_STAT_CLEAR + 4;
9349 }
9350
9351 static int i40e_get_regs(struct rte_eth_dev *dev,
9352                          struct rte_dev_reg_info *regs)
9353 {
9354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9355         uint32_t *ptr_data = regs->data;
9356         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9357         const struct i40e_reg_info *reg_info;
9358
9359         /* The first few registers have to be read using AQ operations */
9360         reg_idx = 0;
9361         while (i40e_regs_adminq[reg_idx].name) {
9362                 reg_info = &i40e_regs_adminq[reg_idx++];
9363                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9364                         for (arr_idx2 = 0;
9365                                         arr_idx2 <= reg_info->count2;
9366                                         arr_idx2++) {
9367                                 reg_offset = arr_idx * reg_info->stride1 +
9368                                         arr_idx2 * reg_info->stride2;
9369                                 reg_offset += reg_info->base_addr;
9370                                 ptr_data[reg_offset >> 2] =
9371                                         i40e_read_rx_ctl(hw, reg_offset);
9372                         }
9373         }
9374
9375         /* The remaining registers can be read using primitives */
9376         reg_idx = 0;
9377         while (i40e_regs_others[reg_idx].name) {
9378                 reg_info = &i40e_regs_others[reg_idx++];
9379                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9380                         for (arr_idx2 = 0;
9381                                         arr_idx2 <= reg_info->count2;
9382                                         arr_idx2++) {
9383                                 reg_offset = arr_idx * reg_info->stride1 +
9384                                         arr_idx2 * reg_info->stride2;
9385                                 reg_offset += reg_info->base_addr;
9386                                 ptr_data[reg_offset >> 2] =
9387                                         I40E_READ_REG(hw, reg_offset);
9388                         }
9389         }
9390
9391         return 0;
9392 }
9393
9394 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9395 {
9396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9397
9398         /* Convert word count to byte count */
9399         return hw->nvm.sr_size << 1;
9400 }
9401
9402 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9403                            struct rte_dev_eeprom_info *eeprom)
9404 {
9405         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9406         uint16_t *data = eeprom->data;
9407         uint16_t offset, length, cnt_words;
9408         int ret_code;
9409
9410         offset = eeprom->offset >> 1;
9411         length = eeprom->length >> 1;
9412         cnt_words = length;
9413
9414         if (offset > hw->nvm.sr_size ||
9415                 offset + length > hw->nvm.sr_size) {
9416                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9417                 return -EINVAL;
9418         }
9419
9420         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9421
9422         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9423         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9424                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9425                 return -EIO;
9426         }
9427
9428         return 0;
9429 }
9430
9431 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9432                                       struct ether_addr *mac_addr)
9433 {
9434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9435
9436         if (!is_valid_assigned_ether_addr(mac_addr)) {
9437                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9438                 return;
9439         }
9440
9441         /* Flags: 0x3 updates port address */
9442         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9443 }
9444
9445 static int
9446 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9447 {
9448         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9449         struct rte_eth_dev_data *dev_data = pf->dev_data;
9450         uint32_t frame_size = mtu + ETHER_HDR_LEN
9451                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9452         int ret = 0;
9453
9454         /* check if mtu is within the allowed range */
9455         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9456                 return -EINVAL;
9457
9458         /* mtu setting is forbidden if port is start */
9459         if (dev_data->dev_started) {
9460                 PMD_DRV_LOG(ERR,
9461                             "port %d must be stopped before configuration\n",
9462                             dev_data->port_id);
9463                 return -EBUSY;
9464         }
9465
9466         if (frame_size > ETHER_MAX_LEN)
9467                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9468         else
9469                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9470
9471         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9472
9473         return ret;
9474 }