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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
41 #include <rte_flow_driver.h>
42 #include <rte_tm_driver.h>
44 #define I40E_VLAN_TAG_SIZE 4
46 #define I40E_AQ_LEN 32
47 #define I40E_AQ_BUF_SZ 4096
48 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
49 #define I40E_MAX_Q_PER_TC 64
50 #define I40E_NUM_DESC_DEFAULT 512
51 #define I40E_NUM_DESC_ALIGN 32
52 #define I40E_BUF_SIZE_MIN 1024
53 #define I40E_FRAME_SIZE_MAX 9728
54 #define I40E_QUEUE_BASE_ADDR_UNIT 128
55 /* number of VSIs and queue default setting */
56 #define I40E_MAX_QP_NUM_PER_VF 16
57 #define I40E_DEFAULT_QP_NUM_FDIR 1
58 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
59 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
60 /* Maximun number of MAC addresses */
61 #define I40E_NUM_MACADDR_MAX 64
62 /* Maximum number of VFs */
63 #define I40E_MAX_VF 128
66 * vlan_id is a 12 bit number.
67 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
68 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
69 * The higher 7 bit val specifies VFTA array index.
71 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
72 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
74 /* Default TC traffic in case DCB is not enabled */
75 #define I40E_DEFAULT_TCMAP 0x1
76 #define I40E_FDIR_QUEUE_ID 0
78 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
79 #define I40E_VMDQ_POOL_BASE 1
81 #define I40E_DEFAULT_RX_FREE_THRESH 32
82 #define I40E_DEFAULT_RX_PTHRESH 8
83 #define I40E_DEFAULT_RX_HTHRESH 8
84 #define I40E_DEFAULT_RX_WTHRESH 0
86 #define I40E_DEFAULT_TX_FREE_THRESH 32
87 #define I40E_DEFAULT_TX_PTHRESH 32
88 #define I40E_DEFAULT_TX_HTHRESH 0
89 #define I40E_DEFAULT_TX_WTHRESH 0
90 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
95 #define I40E_8_BIT_WIDTH CHAR_BIT
96 #define I40E_8_BIT_MASK UINT8_MAX
97 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
98 #define I40E_16_BIT_MASK UINT16_MAX
99 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
100 #define I40E_32_BIT_MASK UINT32_MAX
101 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
102 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
104 /* Linux PF host with virtchnl version 1.1 */
105 #define PF_IS_V11(vf) \
106 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
107 ((vf)->version_minor == 1))
109 #define I40E_WRITE_GLB_REG(hw, reg, value) \
111 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
113 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
114 "with value 0x%08x", \
118 /* index flex payload per layer */
119 enum i40e_flxpld_layer_idx {
120 I40E_FLXPLD_L2_IDX = 0,
121 I40E_FLXPLD_L3_IDX = 1,
122 I40E_FLXPLD_L4_IDX = 2,
123 I40E_MAX_FLXPLD_LAYER = 3,
125 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
126 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
127 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
128 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
129 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
132 #define I40E_FLAG_RSS (1ULL << 0)
133 #define I40E_FLAG_DCB (1ULL << 1)
134 #define I40E_FLAG_VMDQ (1ULL << 2)
135 #define I40E_FLAG_SRIOV (1ULL << 3)
136 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
137 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
138 #define I40E_FLAG_FDIR (1ULL << 6)
139 #define I40E_FLAG_VXLAN (1ULL << 7)
140 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
141 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
142 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
146 I40E_FLAG_HEADER_SPLIT_DISABLED | \
147 I40E_FLAG_HEADER_SPLIT_ENABLED | \
150 I40E_FLAG_RSS_AQ_CAPABLE | \
151 I40E_FLAG_VF_MAC_BY_PF)
153 #define I40E_RSS_OFFLOAD_ALL ( \
154 ETH_RSS_FRAG_IPV4 | \
155 ETH_RSS_NONFRAG_IPV4_TCP | \
156 ETH_RSS_NONFRAG_IPV4_UDP | \
157 ETH_RSS_NONFRAG_IPV4_SCTP | \
158 ETH_RSS_NONFRAG_IPV4_OTHER | \
159 ETH_RSS_FRAG_IPV6 | \
160 ETH_RSS_NONFRAG_IPV6_TCP | \
161 ETH_RSS_NONFRAG_IPV6_UDP | \
162 ETH_RSS_NONFRAG_IPV6_SCTP | \
163 ETH_RSS_NONFRAG_IPV6_OTHER | \
166 /* All bits of RSS hash enable for X722*/
167 #define I40E_RSS_HENA_ALL_X722 ( \
168 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
173 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
176 /* All bits of RSS hash enable */
177 #define I40E_RSS_HENA_ALL ( \
178 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
179 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
180 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
181 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
182 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
183 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
184 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
185 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
186 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
187 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
188 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
189 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
190 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
191 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
193 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
194 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
196 /* Default queue interrupt throttling time in microseconds */
197 #define I40E_ITR_INDEX_DEFAULT 0
198 #define I40E_ITR_INDEX_NONE 3
199 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
200 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
201 /* Special FW support this floating VEB feature */
202 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
203 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
205 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
206 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
207 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
208 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
210 #define I40E_INSET_NONE 0x00000000000000000ULL
213 #define I40E_INSET_DMAC 0x0000000000000001ULL
214 #define I40E_INSET_SMAC 0x0000000000000002ULL
215 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
216 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
217 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
220 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
221 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
222 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
223 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
224 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
225 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
226 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
228 /* bit 16 ~ bit 31 */
229 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
230 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
231 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
232 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
233 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
234 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
235 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
236 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
238 /* bit 32 ~ bit 47, tunnel fields */
239 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
240 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
241 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
242 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
243 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
244 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
246 /* bit 48 ~ bit 55 */
247 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
249 /* bit 56 ~ bit 63, Flex Payload */
250 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
251 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
252 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
253 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
254 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
255 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
256 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
257 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
258 #define I40E_INSET_FLEX_PAYLOAD \
259 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
260 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
261 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
262 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
264 /* The max bandwidth of i40e is 40Gbps. */
265 #define I40E_QOS_BW_MAX 40000
266 /* The bandwidth should be the multiple of 50Mbps. */
267 #define I40E_QOS_BW_GRANULARITY 50
268 /* The min bandwidth weight is 1. */
269 #define I40E_QOS_BW_WEIGHT_MIN 1
270 /* The max bandwidth weight is 127. */
271 #define I40E_QOS_BW_WEIGHT_MAX 127
272 /* The max queue region index is 7. */
273 #define I40E_REGION_MAX_INDEX 7
275 #define I40E_MAX_PERCENT 100
276 #define I40E_DEFAULT_DCB_APP_NUM 1
277 #define I40E_DEFAULT_DCB_APP_PRIO 3
280 * The overhead from MTU to max frame size.
281 * Considering QinQ packet, the VLAN tag needs to be counted twice.
283 #define I40E_ETH_OVERHEAD \
284 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
289 * MAC filter structure
291 struct i40e_mac_filter_info {
292 enum rte_mac_filter_type filter_type;
293 struct ether_addr mac_addr;
296 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
298 /* MAC filter list structure */
299 struct i40e_mac_filter {
300 TAILQ_ENTRY(i40e_mac_filter) next;
301 struct i40e_mac_filter_info mac_info;
304 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
308 /* VSI list structure */
309 struct i40e_vsi_list {
310 TAILQ_ENTRY(i40e_vsi_list) list;
311 struct i40e_vsi *vsi;
314 struct i40e_rx_queue;
315 struct i40e_tx_queue;
317 /* Bandwidth limit information */
318 struct i40e_bw_info {
319 uint16_t bw_limit; /* BW Limit (0 = disabled) */
320 uint8_t bw_max; /* Max BW limit if enabled */
322 /* Relative credits within same TC with respect to other VSIs or Comps */
323 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
324 /* Bandwidth limit per TC */
325 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
326 /* Max bandwidth limit per TC */
327 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
330 /* Structure that defines a VEB */
332 struct i40e_vsi_list_head head;
333 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
334 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
335 uint16_t seid; /* The seid of VEB itself */
336 uint16_t uplink_seid; /* The uplink seid of this VEB */
338 struct i40e_eth_stats stats;
339 uint8_t enabled_tc; /* The traffic class enabled */
340 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
341 struct i40e_bw_info bw_info; /* VEB bandwidth information */
344 /* i40e MACVLAN filter structure */
345 struct i40e_macvlan_filter {
346 struct ether_addr macaddr;
347 enum rte_mac_filter_type filter_type;
352 * Structure that defines a VSI, associated with a adapter.
355 struct i40e_adapter *adapter; /* Backreference to associated adapter */
356 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
358 struct i40e_eth_stats eth_stats_offset;
359 struct i40e_eth_stats eth_stats;
361 * When drivers loaded, only a default main VSI exists. In case new VSI
362 * needs to add, HW needs to know the layout that VSIs are organized.
363 * Besides that, VSI isan element and can't switch packets, which needs
364 * to add new component VEB to perform switching. So, a new VSI needs
365 * to specify the the uplink VSI (Parent VSI) before created. The
366 * uplink VSI will check whether it had a VEB to switch packets. If no,
367 * it will try to create one. Then, uplink VSI will move the new VSI
368 * into its' sib_vsi_list to manage all the downlink VSI.
369 * sib_vsi_list: the VSI list that shared the same uplink VSI.
370 * parent_vsi : the uplink VSI. It's NULL for main VSI.
371 * veb : the VEB associates with the VSI.
373 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
374 struct i40e_vsi *parent_vsi;
375 struct i40e_veb *veb; /* Associated veb, could be null */
376 struct i40e_veb *floating_veb; /* Associated floating veb */
378 enum i40e_vsi_type type; /* VSI types */
379 uint16_t vlan_num; /* Total VLAN number */
380 uint16_t mac_num; /* Total mac number */
381 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
382 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
383 /* specific VSI-defined parameters, SRIOV stored the vf_id */
385 uint16_t seid; /* The seid of VSI itself */
386 uint16_t uplink_seid; /* The uplink seid of this VSI */
387 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
388 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
389 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
390 uint16_t base_queue; /* The first queue index of this VSI */
392 * The offset to visit VSI related register, assigned by HW when
396 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
397 uint16_t nb_msix; /* The max number of msix vector */
398 uint8_t enabled_tc; /* The traffic class enabled */
399 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
400 uint8_t vlan_filter_on; /* The VLAN filter enabled */
401 struct i40e_bw_info bw_info; /* VSI bandwidth information */
405 LIST_ENTRY(pool_entry) next;
410 LIST_HEAD(res_list, pool_entry);
412 struct i40e_res_pool_info {
413 uint32_t base; /* Resource start index */
414 uint32_t num_alloc; /* Allocated resource number */
415 uint32_t num_free; /* Total available resource number */
416 struct res_list alloc_list; /* Allocated resource list */
417 struct res_list free_list; /* Available resource list */
421 I40E_VF_INACTIVE = 0,
428 * Structure to store private data for PF host.
432 struct i40e_vsi *vsi;
433 enum I40E_VF_STATE state; /* The number of queue pairs available */
434 uint16_t vf_idx; /* VF index in pf->vfs */
435 uint16_t lan_nb_qps; /* Actual queues allocated */
436 uint16_t reset_cnt; /* Total vf reset times */
437 struct ether_addr mac_addr; /* Default MAC address */
441 * Structure to store private data for flow control.
443 struct i40e_fc_conf {
444 uint16_t pause_time; /* Flow control pause timer */
445 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
446 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
447 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
448 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
452 * Structure to store private data for VMDQ instance
454 struct i40e_vmdq_info {
456 struct i40e_vsi *vsi;
459 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
460 #define I40E_MAX_FLX_SOURCE_OFF 480
461 #define NONUSE_FLX_PIT_DEST_OFF 63
462 #define NONUSE_FLX_PIT_FSIZE 1
463 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
464 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
465 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
466 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
467 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
468 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
469 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
470 NONUSE_FLX_PIT_DEST_OFF : \
471 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
472 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
473 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
474 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
475 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
476 #define I40E_FDIR_IPv6_TC_OFFSET 20
478 /* A structure used to define the input for GTP flow */
479 struct i40e_gtp_flow {
480 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
481 uint8_t msg_type; /* Message type. */
482 uint32_t teid; /* TEID in big endian. */
485 /* A structure used to define the input for GTP IPV4 flow */
486 struct i40e_gtp_ipv4_flow {
487 struct i40e_gtp_flow gtp;
488 struct rte_eth_ipv4_flow ip4;
491 /* A structure used to define the input for GTP IPV6 flow */
492 struct i40e_gtp_ipv6_flow {
493 struct i40e_gtp_flow gtp;
494 struct rte_eth_ipv6_flow ip6;
497 /* A structure used to define the input for raw type flow */
498 struct i40e_raw_flow {
505 * A union contains the inputs for all types of flow
506 * items in flows need to be in big endian
508 union i40e_fdir_flow {
509 struct rte_eth_l2_flow l2_flow;
510 struct rte_eth_udpv4_flow udp4_flow;
511 struct rte_eth_tcpv4_flow tcp4_flow;
512 struct rte_eth_sctpv4_flow sctp4_flow;
513 struct rte_eth_ipv4_flow ip4_flow;
514 struct rte_eth_udpv6_flow udp6_flow;
515 struct rte_eth_tcpv6_flow tcp6_flow;
516 struct rte_eth_sctpv6_flow sctp6_flow;
517 struct rte_eth_ipv6_flow ipv6_flow;
518 struct i40e_gtp_flow gtp_flow;
519 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
520 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
521 struct i40e_raw_flow raw_flow;
524 enum i40e_fdir_ip_type {
525 I40E_FDIR_IPTYPE_IPV4,
526 I40E_FDIR_IPTYPE_IPV6,
529 /* A structure used to contain extend input of flow */
530 struct i40e_fdir_flow_ext {
532 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
533 /* It is filled by the flexible payload to match. */
534 uint8_t is_vf; /* 1 for VF, 0 for port dev */
535 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
536 bool inner_ip; /* If there is inner ip */
537 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
538 bool customized_pctype; /* If customized pctype is used */
539 bool pkt_template; /* If raw packet template is used */
542 /* A structure used to define the input for a flow director filter entry */
543 struct i40e_fdir_input {
544 enum i40e_filter_pctype pctype;
545 union i40e_fdir_flow flow;
546 /* Flow fields to match, dependent on flow_type */
547 struct i40e_fdir_flow_ext flow_ext;
548 /* Additional fields to match */
551 /* Behavior will be taken if FDIR match */
552 enum i40e_fdir_behavior {
553 I40E_FDIR_ACCEPT = 0,
558 /* Flow director report status
559 * It defines what will be reported if FDIR entry is matched.
561 enum i40e_fdir_status {
562 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
563 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
564 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
565 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
568 /* A structure used to define an action when match FDIR packet filter. */
569 struct i40e_fdir_action {
570 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
571 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
572 enum i40e_fdir_status report_status; /* Status report option */
573 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
574 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
575 * flex bytes start from in flexible payload.
580 /* A structure used to define the flow director filter entry by filter_ctrl API
581 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
582 * RTE_ETH_FILTER_DELETE operations.
584 struct i40e_fdir_filter_conf {
586 /* ID, an unique value is required when deal with FDIR entry */
587 struct i40e_fdir_input input; /* Input set */
588 struct i40e_fdir_action action; /* Action taken when match */
592 * Structure to store flex pit for flow diretor.
594 struct i40e_fdir_flex_pit {
595 uint8_t src_offset; /* offset in words from the beginning of payload */
596 uint8_t size; /* size in words */
597 uint8_t dst_offset; /* offset in words of flexible payload */
600 struct i40e_fdir_flex_mask {
601 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
606 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
609 #define I40E_FILTER_PCTYPE_INVALID 0
610 #define I40E_FILTER_PCTYPE_MAX 64
611 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
613 struct i40e_fdir_filter {
614 TAILQ_ENTRY(i40e_fdir_filter) rules;
615 struct i40e_fdir_filter_conf fdir;
618 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
620 * A structure used to define fields of a FDIR related info.
622 struct i40e_fdir_info {
623 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
624 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
625 struct i40e_tx_queue *txq;
626 struct i40e_rx_queue *rxq;
627 void *prg_pkt; /* memory for fdir program packet */
628 uint64_t dma_addr; /* physic address of packet memory*/
629 /* input set bits for each pctype */
630 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
632 * the rule how bytes stream is extracted as flexible payload
633 * for each payload layer, the setting can up to three elements
635 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
636 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
638 struct i40e_fdir_filter_list fdir_list;
639 struct i40e_fdir_filter **hash_map;
640 struct rte_hash *hash_table;
642 /* Mark if flex pit and mask is set */
643 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
644 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
646 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
649 /* Ethertype filter number HW supports */
650 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
652 /* Ethertype filter struct */
653 struct i40e_ethertype_filter_input {
654 struct ether_addr mac_addr; /* Mac address to match */
655 uint16_t ether_type; /* Ether type to match */
658 struct i40e_ethertype_filter {
659 TAILQ_ENTRY(i40e_ethertype_filter) rules;
660 struct i40e_ethertype_filter_input input;
661 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
662 uint16_t queue; /* Queue assigned to when match */
665 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
667 struct i40e_ethertype_rule {
668 struct i40e_ethertype_filter_list ethertype_list;
669 struct i40e_ethertype_filter **hash_map;
670 struct rte_hash *hash_table;
673 /* queue region info */
674 struct i40e_queue_region_info {
675 /* the region id for this configuration */
677 /* the start queue index for this region */
678 uint8_t queue_start_index;
679 /* the total queue number of this queue region */
681 /* the total number of user priority for this region */
682 uint8_t user_priority_num;
683 /* the packet's user priority for this region */
684 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
685 /* the total number of flowtype for this region */
686 uint8_t flowtype_num;
688 * the pctype or hardware flowtype of packet,
689 * the specific index for each type has been defined
690 * in file i40e_type.h as enum i40e_filter_pctype.
692 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
695 struct i40e_queue_regions {
696 /* the total number of queue region for this port */
697 uint16_t queue_region_number;
698 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
701 /* Tunnel filter number HW supports */
702 #define I40E_MAX_TUNNEL_FILTER_NUM 400
704 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
705 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
706 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
707 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
708 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
709 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
710 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
711 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
712 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
713 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
714 #define I40E_AQC_NEW_TR_21 21
715 #define I40E_AQC_NEW_TR_22 22
717 enum i40e_tunnel_iptype {
718 I40E_TUNNEL_IPTYPE_IPV4,
719 I40E_TUNNEL_IPTYPE_IPV6,
722 /* Tunnel filter struct */
723 struct i40e_tunnel_filter_input {
724 uint8_t outer_mac[6]; /* Outer mac address to match */
725 uint8_t inner_mac[6]; /* Inner mac address to match */
726 uint16_t inner_vlan; /* Inner vlan address to match */
727 enum i40e_tunnel_iptype ip_type;
728 uint16_t flags; /* Filter type flag */
729 uint32_t tenant_id; /* Tenant id to match */
730 uint16_t general_fields[32]; /* Big buffer */
733 struct i40e_tunnel_filter {
734 TAILQ_ENTRY(i40e_tunnel_filter) rules;
735 struct i40e_tunnel_filter_input input;
736 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
737 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
738 uint16_t queue; /* Queue assigned to when match */
741 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
743 struct i40e_tunnel_rule {
744 struct i40e_tunnel_filter_list tunnel_list;
745 struct i40e_tunnel_filter **hash_map;
746 struct rte_hash *hash_table;
752 enum i40e_tunnel_type {
753 I40E_TUNNEL_TYPE_NONE = 0,
754 I40E_TUNNEL_TYPE_VXLAN,
755 I40E_TUNNEL_TYPE_GENEVE,
756 I40E_TUNNEL_TYPE_TEREDO,
757 I40E_TUNNEL_TYPE_NVGRE,
758 I40E_TUNNEL_TYPE_IP_IN_GRE,
759 I40E_L2_TUNNEL_TYPE_E_TAG,
760 I40E_TUNNEL_TYPE_MPLSoUDP,
761 I40E_TUNNEL_TYPE_MPLSoGRE,
762 I40E_TUNNEL_TYPE_QINQ,
763 I40E_TUNNEL_TYPE_GTPC,
764 I40E_TUNNEL_TYPE_GTPU,
765 I40E_TUNNEL_TYPE_MAX,
769 * Tunneling Packet filter configuration.
771 struct i40e_tunnel_filter_conf {
772 struct ether_addr outer_mac; /**< Outer MAC address to match. */
773 struct ether_addr inner_mac; /**< Inner MAC address to match. */
774 uint16_t inner_vlan; /**< Inner VLAN to match. */
775 uint32_t outer_vlan; /**< Outer VLAN to match */
776 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
778 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
779 * is set in filter_type, or inner destination IP address to match
780 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
783 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
784 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
786 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
787 uint16_t filter_type;
788 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
789 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
790 uint16_t queue_id; /**< Queue assigned to if match. */
791 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
792 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
795 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
796 #define I40E_MAX_MIRROR_RULES 64
798 * Mirror rule structure
800 struct i40e_mirror_rule {
801 TAILQ_ENTRY(i40e_mirror_rule) rules;
803 uint16_t index; /* the sw index of mirror rule */
804 uint16_t id; /* the rule id assigned by firmware */
805 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
806 uint16_t num_entries;
807 /* the info stores depend on the rule type.
808 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
809 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
811 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
814 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
817 * Struct to store flow created.
820 TAILQ_ENTRY(rte_flow) node;
821 enum rte_filter_type filter_type;
825 TAILQ_HEAD(i40e_flow_list, rte_flow);
827 /* Struct to store Traffic Manager shaper profile. */
828 struct i40e_tm_shaper_profile {
829 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
830 uint32_t shaper_profile_id;
831 uint32_t reference_count;
832 struct rte_tm_shaper_params profile;
835 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
837 /* node type of Traffic Manager */
838 enum i40e_tm_node_type {
839 I40E_TM_NODE_TYPE_PORT,
840 I40E_TM_NODE_TYPE_TC,
841 I40E_TM_NODE_TYPE_QUEUE,
842 I40E_TM_NODE_TYPE_MAX,
845 /* Struct to store Traffic Manager node configuration. */
846 struct i40e_tm_node {
847 TAILQ_ENTRY(i40e_tm_node) node;
851 uint32_t reference_count;
852 struct i40e_tm_node *parent;
853 struct i40e_tm_shaper_profile *shaper_profile;
854 struct rte_tm_node_params params;
857 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
859 /* Struct to store all the Traffic Manager configuration. */
860 struct i40e_tm_conf {
861 struct i40e_shaper_profile_list shaper_profile_list;
862 struct i40e_tm_node *root; /* root node - port */
863 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
864 struct i40e_tm_node_list queue_list; /* node list for all the queues */
866 * The number of added TC nodes.
867 * It should be no more than the TC number of this port.
871 * The number of added queue nodes.
872 * It should be no more than the queue number of this port.
874 uint32_t nb_queue_node;
876 * This flag is used to check if APP can change the TM node
878 * When it's true, means the configuration is applied to HW,
879 * APP should not change the configuration.
880 * As we don't support on-the-fly configuration, when starting
881 * the port, APP should call the hierarchy_commit API to set this
882 * flag to true. When stopping the port, this flag should be set
888 enum i40e_new_pctype {
889 I40E_CUSTOMIZED_GTPC = 0,
890 I40E_CUSTOMIZED_GTPU_IPV4,
891 I40E_CUSTOMIZED_GTPU_IPV6,
892 I40E_CUSTOMIZED_GTPU,
896 #define I40E_FILTER_PCTYPE_INVALID 0
897 struct i40e_customized_pctype {
898 enum i40e_new_pctype index; /* Indicate which customized pctype */
899 uint8_t pctype; /* New pctype value */
900 bool valid; /* Check if it's valid */
904 * Structure to store private data specific for PF instance.
907 struct i40e_adapter *adapter; /* The adapter this PF associate to */
908 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
909 uint16_t mac_seid; /* The seid of the MAC of this PF */
910 uint16_t main_vsi_seid; /* The seid of the main VSI */
911 uint16_t max_num_vsi;
912 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
913 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
915 struct i40e_hw_port_stats stats_offset;
916 struct i40e_hw_port_stats stats;
917 /* internal packet statistics, it should be excluded from the total */
918 struct i40e_eth_stats internal_stats_offset;
919 struct i40e_eth_stats internal_stats;
922 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
923 struct ether_addr dev_addr; /* PF device mac address */
924 uint64_t flags; /* PF feature flags */
925 /* All kinds of queue pair setting for different VSIs */
926 struct i40e_pf_vf *vfs;
928 /* Each of below queue pairs should be power of 2 since it's the
929 precondition after TC configuration applied */
930 uint16_t lan_nb_qp_max;
931 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
932 uint16_t lan_qp_offset;
933 uint16_t vmdq_nb_qp_max;
934 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
935 uint16_t vmdq_qp_offset;
936 uint16_t vf_nb_qp_max;
937 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
938 uint16_t vf_qp_offset;
939 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
940 uint16_t fdir_qp_offset;
942 uint16_t hash_lut_size; /* The size of hash lookup table */
943 /* input set bits for each pctype */
944 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
945 /* store VXLAN UDP ports */
946 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
947 uint16_t vxlan_bitmap; /* Vxlan bit mask */
949 /* VMDQ related info */
950 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
951 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
952 struct i40e_vmdq_info *vmdq;
954 struct i40e_fdir_info fdir; /* flow director info */
955 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
956 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
957 struct i40e_queue_regions queue_region; /* queue region info */
958 struct i40e_fc_conf fc_conf; /* Flow control conf */
959 struct i40e_mirror_rule_list mirror_list;
960 uint16_t nb_mirror_rule; /* The number of mirror rules */
961 bool floating_veb; /* The flag to use the floating VEB */
962 /* The floating enable flag for the specific VF */
963 bool floating_veb_list[I40E_MAX_VF];
964 struct i40e_flow_list flow_list;
965 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
966 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
967 bool qinq_replace_flag; /* QINQ filter replace is done */
968 struct i40e_tm_conf tm_conf;
969 bool support_multi_driver; /* 1 - support multiple driver */
971 /* Dynamic Device Personalization */
972 bool gtp_support; /* 1 - support GTP-C and GTP-U */
973 /* customer customized pctype */
974 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
978 PFMSG_LINK_CHANGE = 0x1,
979 PFMSG_RESET_IMPENDING = 0x2,
980 PFMSG_DRIVER_CLOSE = 0x4,
983 struct i40e_vsi_vlan_pvid_info {
984 uint16_t on; /* Enable or disable pvid */
986 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
988 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
989 * while 'untagged' will reject untagged packets.
997 struct i40e_vf_rx_queues {
998 uint64_t rx_dma_addr;
999 uint32_t rx_ring_len;
1003 struct i40e_vf_tx_queues {
1004 uint64_t tx_dma_addr;
1005 uint32_t tx_ring_len;
1009 * Structure to store private data specific for VF instance.
1012 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1013 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1014 uint16_t num_queue_pairs;
1015 uint16_t max_pkt_len; /* Maximum packet length */
1016 bool promisc_unicast_enabled;
1017 bool promisc_multicast_enabled;
1019 uint32_t version_major; /* Major version number */
1020 uint32_t version_minor; /* Minor version number */
1021 uint16_t promisc_flags; /* Promiscuous setting */
1022 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1027 enum virtchnl_link_speed link_speed;
1029 volatile uint32_t pend_cmd; /* pending command not finished yet */
1030 int32_t cmd_retval; /* return value of the cmd response from PF */
1031 u16 pend_msg; /* flags indicates events from pf not handled yet */
1032 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1035 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1036 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1037 struct i40e_vsi vsi;
1041 #define I40E_MAX_PKT_TYPE 256
1042 #define I40E_FLOW_TYPE_MAX 64
1045 * Structure to store private data for each PF/VF instance.
1047 struct i40e_adapter {
1048 /* Common for both PF and VF */
1050 struct rte_eth_dev *eth_dev;
1052 /* Specific for PF or VF */
1058 /* For vector PMD */
1059 bool rx_bulk_alloc_allowed;
1060 bool rx_vec_allowed;
1061 bool tx_simple_allowed;
1062 bool tx_vec_allowed;
1065 struct rte_timecounter systime_tc;
1066 struct rte_timecounter rx_tstamp_tc;
1067 struct rte_timecounter tx_tstamp_tc;
1069 /* ptype mapping table */
1070 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1071 /* flow type to pctype mapping table */
1072 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1073 uint64_t flow_types_mask;
1074 uint64_t pctypes_mask;
1077 extern const struct rte_flow_ops i40e_flow_ops;
1079 union i40e_filter_t {
1080 struct rte_eth_ethertype_filter ethertype_filter;
1081 struct i40e_fdir_filter_conf fdir_filter;
1082 struct rte_eth_tunnel_filter_conf tunnel_filter;
1083 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1086 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1087 const struct rte_flow_attr *attr,
1088 const struct rte_flow_item pattern[],
1089 const struct rte_flow_action actions[],
1090 struct rte_flow_error *error,
1091 union i40e_filter_t *filter);
1092 struct i40e_valid_pattern {
1093 enum rte_flow_item_type *items;
1094 parse_filter_t parse_filter;
1097 enum I40E_WARNING_IDX {
1098 I40E_WARNING_DIS_FLX_PLD,
1099 I40E_WARNING_ENA_FLX_PLD,
1100 I40E_WARNING_QINQ_PARSER,
1101 I40E_WARNING_QINQ_CLOUD_FILTER,
1103 I40E_WARNING_FLOW_CTL,
1104 I40E_WARNING_GRE_KEY_LEN,
1105 I40E_WARNING_QF_CTL,
1106 I40E_WARNING_HASH_INSET,
1108 I40E_WARNING_HASH_MSK,
1109 I40E_WARNING_FD_MSK,
1110 I40E_WARNING_RPL_CLD_FILTER,
1113 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1114 int i40e_vsi_release(struct i40e_vsi *vsi);
1115 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1116 enum i40e_vsi_type type,
1117 struct i40e_vsi *uplink_vsi,
1118 uint16_t user_param);
1119 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1120 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1121 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1122 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1123 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1124 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1125 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1126 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1127 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1128 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1129 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1130 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1131 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1132 struct i40e_vsi_vlan_pvid_info *info);
1133 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1134 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1135 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1136 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1137 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1138 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1139 int i40e_fdir_setup(struct i40e_pf *pf);
1140 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1143 int i40e_fdir_configure(struct rte_eth_dev *dev);
1144 void i40e_fdir_teardown(struct i40e_pf *pf);
1145 enum i40e_filter_pctype
1146 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1147 uint16_t flow_type);
1148 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1149 enum i40e_filter_pctype pctype);
1150 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1151 enum rte_filter_op filter_op,
1153 int i40e_select_filter_input_set(struct i40e_hw *hw,
1154 struct rte_eth_input_set_conf *conf,
1155 enum rte_filter_type filter);
1156 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1157 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1158 struct rte_eth_input_set_conf *conf);
1159 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1160 struct rte_eth_input_set_conf *conf);
1161 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1162 uint32_t retval, uint8_t *msg,
1164 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1165 struct rte_eth_rxq_info *qinfo);
1166 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1167 struct rte_eth_txq_info *qinfo);
1168 struct i40e_ethertype_filter *
1169 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1170 const struct i40e_ethertype_filter_input *input);
1171 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1172 struct i40e_ethertype_filter_input *input);
1173 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1174 struct i40e_fdir_input *input);
1175 struct i40e_tunnel_filter *
1176 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1177 const struct i40e_tunnel_filter_input *input);
1178 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1179 struct i40e_tunnel_filter_input *input);
1180 uint64_t i40e_get_default_input_set(uint16_t pctype);
1181 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1182 struct rte_eth_ethertype_filter *filter,
1184 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1185 const struct rte_eth_fdir_filter *filter,
1187 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1188 const struct i40e_fdir_filter_conf *filter,
1190 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1191 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1193 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1194 struct i40e_tunnel_filter_conf *tunnel_filter,
1196 int i40e_fdir_flush(struct rte_eth_dev *dev);
1197 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1198 struct i40e_macvlan_filter *mv_f,
1199 int num, struct ether_addr *addr);
1200 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1201 struct i40e_macvlan_filter *filter,
1203 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1204 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1205 struct i40e_macvlan_filter *filter,
1207 bool is_i40e_supported(struct rte_eth_dev *dev);
1209 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1210 enum rte_filter_type filter, uint64_t inset);
1211 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1213 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1214 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1215 void i40e_check_write_global_reg(struct i40e_hw *hw,
1216 uint32_t addr, uint32_t val);
1218 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1219 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1220 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1221 struct i40e_customized_pctype*
1222 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1223 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1225 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1226 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1227 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1228 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1230 #define I40E_DEV_TO_PCI(eth_dev) \
1231 RTE_DEV_TO_PCI((eth_dev)->device)
1233 /* I40E_DEV_PRIVATE_TO */
1234 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1235 (&((struct i40e_adapter *)adapter)->pf)
1236 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1237 (&((struct i40e_adapter *)adapter)->hw)
1238 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1239 ((struct i40e_adapter *)adapter)
1241 /* I40EVF_DEV_PRIVATE_TO */
1242 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1243 (&((struct i40e_adapter *)adapter)->vf)
1245 static inline struct i40e_vsi *
1246 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1253 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1254 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1255 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1258 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1259 return pf->main_vsi;
1262 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1263 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1266 #define I40E_VSI_TO_HW(vsi) \
1267 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1268 #define I40E_VSI_TO_PF(vsi) \
1269 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1270 #define I40E_VSI_TO_VF(vsi) \
1271 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1272 #define I40E_VSI_TO_DEV_DATA(vsi) \
1273 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1274 #define I40E_VSI_TO_ETH_DEV(vsi) \
1275 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1278 #define I40E_PF_TO_HW(pf) \
1279 (&(((struct i40e_pf *)pf)->adapter->hw))
1280 #define I40E_PF_TO_ADAPTER(pf) \
1281 ((struct i40e_adapter *)pf->adapter)
1284 #define I40E_VF_TO_HW(vf) \
1285 (&(((struct i40e_vf *)vf)->adapter->hw))
1288 i40e_init_adminq_parameter(struct i40e_hw *hw)
1290 hw->aq.num_arq_entries = I40E_AQ_LEN;
1291 hw->aq.num_asq_entries = I40E_AQ_LEN;
1292 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1293 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1297 i40e_align_floor(int n)
1301 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1304 static inline uint16_t
1305 i40e_calc_itr_interval(int16_t interval, bool is_multi_drv)
1308 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1309 else if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
1310 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1312 /* Convert to hardware count, as writing each 1 represents 2 us */
1313 return interval / 2;
1317 i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
1319 const char *warning;
1320 static const char *const warning_list[] = {
1321 [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
1322 [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
1323 [I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
1324 [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
1325 [I40E_WARNING_TPID] = "support TPID configuration",
1326 [I40E_WARNING_FLOW_CTL] = "configure water marker",
1327 [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
1328 [I40E_WARNING_QF_CTL] = "support hash function setting",
1329 [I40E_WARNING_HASH_INSET] = "configure hash input set",
1330 [I40E_WARNING_HSYM] = "set symmetric hash",
1331 [I40E_WARNING_HASH_MSK] = "configure hash mask",
1332 [I40E_WARNING_FD_MSK] = "configure fdir mask",
1333 [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
1336 warning = warning_list[idx];
1338 RTE_LOG(WARNING, PMD,
1339 "Global register is changed during %s\n",
1343 #define I40E_VALID_FLOW(flow_type) \
1344 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1345 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1346 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1347 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1348 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1349 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1350 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1351 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1352 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1353 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1354 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1356 #define I40E_VALID_PCTYPE_X722(pctype) \
1357 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1358 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1359 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1360 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1361 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1362 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1363 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1364 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1365 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1366 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1367 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1368 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1369 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1370 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1371 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1372 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1373 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1375 #define I40E_VALID_PCTYPE(pctype) \
1376 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1377 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1378 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1379 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1380 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1381 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1382 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1383 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1384 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1385 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1386 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1388 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1389 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1390 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1391 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1392 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1393 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1394 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1396 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1397 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1398 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1399 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1400 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1402 #endif /* _I40E_ETHDEV_H_ */