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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #include <rte_kvargs.h>
41 #include <rte_flow_driver.h>
42 #include <rte_tm_driver.h>
43 #include "rte_pmd_i40e.h"
45 #define I40E_VLAN_TAG_SIZE 4
47 #define I40E_AQ_LEN 32
48 #define I40E_AQ_BUF_SZ 4096
49 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
50 #define I40E_MAX_Q_PER_TC 64
51 #define I40E_NUM_DESC_DEFAULT 512
52 #define I40E_NUM_DESC_ALIGN 32
53 #define I40E_BUF_SIZE_MIN 1024
54 #define I40E_FRAME_SIZE_MAX 9728
55 #define I40E_QUEUE_BASE_ADDR_UNIT 128
56 /* number of VSIs and queue default setting */
57 #define I40E_MAX_QP_NUM_PER_VF 16
58 #define I40E_DEFAULT_QP_NUM_FDIR 1
59 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
60 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
61 /* Maximun number of MAC addresses */
62 #define I40E_NUM_MACADDR_MAX 64
63 /* Maximum number of VFs */
64 #define I40E_MAX_VF 128
67 * vlan_id is a 12 bit number.
68 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
69 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
70 * The higher 7 bit val specifies VFTA array index.
72 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
73 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
75 /* Default TC traffic in case DCB is not enabled */
76 #define I40E_DEFAULT_TCMAP 0x1
77 #define I40E_FDIR_QUEUE_ID 0
79 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
80 #define I40E_VMDQ_POOL_BASE 1
82 #define I40E_DEFAULT_RX_FREE_THRESH 32
83 #define I40E_DEFAULT_RX_PTHRESH 8
84 #define I40E_DEFAULT_RX_HTHRESH 8
85 #define I40E_DEFAULT_RX_WTHRESH 0
87 #define I40E_DEFAULT_TX_FREE_THRESH 32
88 #define I40E_DEFAULT_TX_PTHRESH 32
89 #define I40E_DEFAULT_TX_HTHRESH 0
90 #define I40E_DEFAULT_TX_WTHRESH 0
91 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
93 /* Bit shift and mask */
94 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
95 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
96 #define I40E_8_BIT_WIDTH CHAR_BIT
97 #define I40E_8_BIT_MASK UINT8_MAX
98 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
99 #define I40E_16_BIT_MASK UINT16_MAX
100 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
101 #define I40E_32_BIT_MASK UINT32_MAX
102 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
103 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
105 /* Linux PF host with virtchnl version 1.1 */
106 #define PF_IS_V11(vf) \
107 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
108 ((vf)->version_minor == 1))
110 #define I40E_WRITE_GLB_REG(hw, reg, value) \
112 I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
114 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
115 "with value 0x%08x", \
119 /* index flex payload per layer */
120 enum i40e_flxpld_layer_idx {
121 I40E_FLXPLD_L2_IDX = 0,
122 I40E_FLXPLD_L3_IDX = 1,
123 I40E_FLXPLD_L4_IDX = 2,
124 I40E_MAX_FLXPLD_LAYER = 3,
126 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
127 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
128 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
129 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
130 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
133 #define I40E_FLAG_RSS (1ULL << 0)
134 #define I40E_FLAG_DCB (1ULL << 1)
135 #define I40E_FLAG_VMDQ (1ULL << 2)
136 #define I40E_FLAG_SRIOV (1ULL << 3)
137 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
138 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
139 #define I40E_FLAG_FDIR (1ULL << 6)
140 #define I40E_FLAG_VXLAN (1ULL << 7)
141 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
142 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
143 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
147 I40E_FLAG_HEADER_SPLIT_DISABLED | \
148 I40E_FLAG_HEADER_SPLIT_ENABLED | \
151 I40E_FLAG_RSS_AQ_CAPABLE | \
152 I40E_FLAG_VF_MAC_BY_PF)
154 #define I40E_RSS_OFFLOAD_ALL ( \
155 ETH_RSS_FRAG_IPV4 | \
156 ETH_RSS_NONFRAG_IPV4_TCP | \
157 ETH_RSS_NONFRAG_IPV4_UDP | \
158 ETH_RSS_NONFRAG_IPV4_SCTP | \
159 ETH_RSS_NONFRAG_IPV4_OTHER | \
160 ETH_RSS_FRAG_IPV6 | \
161 ETH_RSS_NONFRAG_IPV6_TCP | \
162 ETH_RSS_NONFRAG_IPV6_UDP | \
163 ETH_RSS_NONFRAG_IPV6_SCTP | \
164 ETH_RSS_NONFRAG_IPV6_OTHER | \
167 /* All bits of RSS hash enable for X722*/
168 #define I40E_RSS_HENA_ALL_X722 ( \
169 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
170 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
171 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
172 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
173 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
174 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
177 /* All bits of RSS hash enable */
178 #define I40E_RSS_HENA_ALL ( \
179 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
180 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
181 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
182 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
183 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
184 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
185 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
186 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
187 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
188 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
189 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
190 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
191 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
192 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
194 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
195 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
197 /* Default queue interrupt throttling time in microseconds */
198 #define I40E_ITR_INDEX_DEFAULT 0
199 #define I40E_ITR_INDEX_NONE 3
200 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
201 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
202 /* Special FW support this floating VEB feature */
203 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
204 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
206 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
207 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
208 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
209 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
211 #define I40E_INSET_NONE 0x00000000000000000ULL
214 #define I40E_INSET_DMAC 0x0000000000000001ULL
215 #define I40E_INSET_SMAC 0x0000000000000002ULL
216 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
217 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
218 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
221 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
222 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
223 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
224 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
225 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
226 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
227 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
229 /* bit 16 ~ bit 31 */
230 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
231 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
232 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
233 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
234 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
235 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
236 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
237 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
239 /* bit 32 ~ bit 47, tunnel fields */
240 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
241 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
242 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
243 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
244 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
245 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
247 /* bit 48 ~ bit 55 */
248 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
250 /* bit 56 ~ bit 63, Flex Payload */
251 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
252 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
253 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
254 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
255 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
256 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
257 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
258 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
259 #define I40E_INSET_FLEX_PAYLOAD \
260 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
261 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
262 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
263 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
265 /* The max bandwidth of i40e is 40Gbps. */
266 #define I40E_QOS_BW_MAX 40000
267 /* The bandwidth should be the multiple of 50Mbps. */
268 #define I40E_QOS_BW_GRANULARITY 50
269 /* The min bandwidth weight is 1. */
270 #define I40E_QOS_BW_WEIGHT_MIN 1
271 /* The max bandwidth weight is 127. */
272 #define I40E_QOS_BW_WEIGHT_MAX 127
273 /* The max queue region index is 7. */
274 #define I40E_REGION_MAX_INDEX 7
276 #define I40E_MAX_PERCENT 100
277 #define I40E_DEFAULT_DCB_APP_NUM 1
278 #define I40E_DEFAULT_DCB_APP_PRIO 3
281 * The overhead from MTU to max frame size.
282 * Considering QinQ packet, the VLAN tag needs to be counted twice.
284 #define I40E_ETH_OVERHEAD \
285 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
290 * MAC filter structure
292 struct i40e_mac_filter_info {
293 enum rte_mac_filter_type filter_type;
294 struct ether_addr mac_addr;
297 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
299 /* MAC filter list structure */
300 struct i40e_mac_filter {
301 TAILQ_ENTRY(i40e_mac_filter) next;
302 struct i40e_mac_filter_info mac_info;
305 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
309 /* VSI list structure */
310 struct i40e_vsi_list {
311 TAILQ_ENTRY(i40e_vsi_list) list;
312 struct i40e_vsi *vsi;
315 struct i40e_rx_queue;
316 struct i40e_tx_queue;
318 /* Bandwidth limit information */
319 struct i40e_bw_info {
320 uint16_t bw_limit; /* BW Limit (0 = disabled) */
321 uint8_t bw_max; /* Max BW limit if enabled */
323 /* Relative credits within same TC with respect to other VSIs or Comps */
324 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
325 /* Bandwidth limit per TC */
326 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
327 /* Max bandwidth limit per TC */
328 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
331 /* Structure that defines a VEB */
333 struct i40e_vsi_list_head head;
334 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
335 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
336 uint16_t seid; /* The seid of VEB itself */
337 uint16_t uplink_seid; /* The uplink seid of this VEB */
339 struct i40e_eth_stats stats;
340 uint8_t enabled_tc; /* The traffic class enabled */
341 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
342 struct i40e_bw_info bw_info; /* VEB bandwidth information */
345 /* i40e MACVLAN filter structure */
346 struct i40e_macvlan_filter {
347 struct ether_addr macaddr;
348 enum rte_mac_filter_type filter_type;
353 * Structure that defines a VSI, associated with a adapter.
356 struct i40e_adapter *adapter; /* Backreference to associated adapter */
357 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
359 struct i40e_eth_stats eth_stats_offset;
360 struct i40e_eth_stats eth_stats;
362 * When drivers loaded, only a default main VSI exists. In case new VSI
363 * needs to add, HW needs to know the layout that VSIs are organized.
364 * Besides that, VSI isan element and can't switch packets, which needs
365 * to add new component VEB to perform switching. So, a new VSI needs
366 * to specify the the uplink VSI (Parent VSI) before created. The
367 * uplink VSI will check whether it had a VEB to switch packets. If no,
368 * it will try to create one. Then, uplink VSI will move the new VSI
369 * into its' sib_vsi_list to manage all the downlink VSI.
370 * sib_vsi_list: the VSI list that shared the same uplink VSI.
371 * parent_vsi : the uplink VSI. It's NULL for main VSI.
372 * veb : the VEB associates with the VSI.
374 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
375 struct i40e_vsi *parent_vsi;
376 struct i40e_veb *veb; /* Associated veb, could be null */
377 struct i40e_veb *floating_veb; /* Associated floating veb */
379 enum i40e_vsi_type type; /* VSI types */
380 uint16_t vlan_num; /* Total VLAN number */
381 uint16_t mac_num; /* Total mac number */
382 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
383 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
384 /* specific VSI-defined parameters, SRIOV stored the vf_id */
386 uint16_t seid; /* The seid of VSI itself */
387 uint16_t uplink_seid; /* The uplink seid of this VSI */
388 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
389 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
390 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
391 uint16_t base_queue; /* The first queue index of this VSI */
393 * The offset to visit VSI related register, assigned by HW when
397 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
398 uint16_t nb_msix; /* The max number of msix vector */
399 uint8_t enabled_tc; /* The traffic class enabled */
400 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
401 uint8_t vlan_filter_on; /* The VLAN filter enabled */
402 struct i40e_bw_info bw_info; /* VSI bandwidth information */
406 LIST_ENTRY(pool_entry) next;
411 LIST_HEAD(res_list, pool_entry);
413 struct i40e_res_pool_info {
414 uint32_t base; /* Resource start index */
415 uint32_t num_alloc; /* Allocated resource number */
416 uint32_t num_free; /* Total available resource number */
417 struct res_list alloc_list; /* Allocated resource list */
418 struct res_list free_list; /* Available resource list */
422 I40E_VF_INACTIVE = 0,
429 * Structure to store private data for PF host.
433 struct i40e_vsi *vsi;
434 enum I40E_VF_STATE state; /* The number of queue pairs available */
435 uint16_t vf_idx; /* VF index in pf->vfs */
436 uint16_t lan_nb_qps; /* Actual queues allocated */
437 uint16_t reset_cnt; /* Total vf reset times */
438 struct ether_addr mac_addr; /* Default MAC address */
442 * Structure to store private data for flow control.
444 struct i40e_fc_conf {
445 uint16_t pause_time; /* Flow control pause timer */
446 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
447 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
448 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
449 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
453 * Structure to store private data for VMDQ instance
455 struct i40e_vmdq_info {
457 struct i40e_vsi *vsi;
460 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
461 #define I40E_MAX_FLX_SOURCE_OFF 480
462 #define NONUSE_FLX_PIT_DEST_OFF 63
463 #define NONUSE_FLX_PIT_FSIZE 1
464 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
465 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
466 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
467 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
468 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
469 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
470 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
471 NONUSE_FLX_PIT_DEST_OFF : \
472 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
473 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
474 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
475 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
476 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
477 #define I40E_FDIR_IPv6_TC_OFFSET 20
479 /* A structure used to define the input for GTP flow */
480 struct i40e_gtp_flow {
481 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
482 uint8_t msg_type; /* Message type. */
483 uint32_t teid; /* TEID in big endian. */
486 /* A structure used to define the input for GTP IPV4 flow */
487 struct i40e_gtp_ipv4_flow {
488 struct i40e_gtp_flow gtp;
489 struct rte_eth_ipv4_flow ip4;
492 /* A structure used to define the input for GTP IPV6 flow */
493 struct i40e_gtp_ipv6_flow {
494 struct i40e_gtp_flow gtp;
495 struct rte_eth_ipv6_flow ip6;
498 /* A structure used to define the input for raw type flow */
499 struct i40e_raw_flow {
506 * A union contains the inputs for all types of flow
507 * items in flows need to be in big endian
509 union i40e_fdir_flow {
510 struct rte_eth_l2_flow l2_flow;
511 struct rte_eth_udpv4_flow udp4_flow;
512 struct rte_eth_tcpv4_flow tcp4_flow;
513 struct rte_eth_sctpv4_flow sctp4_flow;
514 struct rte_eth_ipv4_flow ip4_flow;
515 struct rte_eth_udpv6_flow udp6_flow;
516 struct rte_eth_tcpv6_flow tcp6_flow;
517 struct rte_eth_sctpv6_flow sctp6_flow;
518 struct rte_eth_ipv6_flow ipv6_flow;
519 struct i40e_gtp_flow gtp_flow;
520 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
521 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
522 struct i40e_raw_flow raw_flow;
525 enum i40e_fdir_ip_type {
526 I40E_FDIR_IPTYPE_IPV4,
527 I40E_FDIR_IPTYPE_IPV6,
530 /* A structure used to contain extend input of flow */
531 struct i40e_fdir_flow_ext {
533 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
534 /* It is filled by the flexible payload to match. */
535 uint8_t is_vf; /* 1 for VF, 0 for port dev */
536 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
537 bool inner_ip; /* If there is inner ip */
538 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
539 bool customized_pctype; /* If customized pctype is used */
540 bool pkt_template; /* If raw packet template is used */
543 /* A structure used to define the input for a flow director filter entry */
544 struct i40e_fdir_input {
545 enum i40e_filter_pctype pctype;
546 union i40e_fdir_flow flow;
547 /* Flow fields to match, dependent on flow_type */
548 struct i40e_fdir_flow_ext flow_ext;
549 /* Additional fields to match */
552 /* Behavior will be taken if FDIR match */
553 enum i40e_fdir_behavior {
554 I40E_FDIR_ACCEPT = 0,
559 /* Flow director report status
560 * It defines what will be reported if FDIR entry is matched.
562 enum i40e_fdir_status {
563 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
564 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
565 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
566 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
569 /* A structure used to define an action when match FDIR packet filter. */
570 struct i40e_fdir_action {
571 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
572 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
573 enum i40e_fdir_status report_status; /* Status report option */
574 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
575 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
576 * flex bytes start from in flexible payload.
581 /* A structure used to define the flow director filter entry by filter_ctrl API
582 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
583 * RTE_ETH_FILTER_DELETE operations.
585 struct i40e_fdir_filter_conf {
587 /* ID, an unique value is required when deal with FDIR entry */
588 struct i40e_fdir_input input; /* Input set */
589 struct i40e_fdir_action action; /* Action taken when match */
593 * Structure to store flex pit for flow diretor.
595 struct i40e_fdir_flex_pit {
596 uint8_t src_offset; /* offset in words from the beginning of payload */
597 uint8_t size; /* size in words */
598 uint8_t dst_offset; /* offset in words of flexible payload */
601 struct i40e_fdir_flex_mask {
602 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
607 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
610 #define I40E_FILTER_PCTYPE_INVALID 0
611 #define I40E_FILTER_PCTYPE_MAX 64
612 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
614 struct i40e_fdir_filter {
615 TAILQ_ENTRY(i40e_fdir_filter) rules;
616 struct i40e_fdir_filter_conf fdir;
619 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
621 * A structure used to define fields of a FDIR related info.
623 struct i40e_fdir_info {
624 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
625 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
626 struct i40e_tx_queue *txq;
627 struct i40e_rx_queue *rxq;
628 void *prg_pkt; /* memory for fdir program packet */
629 uint64_t dma_addr; /* physic address of packet memory*/
630 /* input set bits for each pctype */
631 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
633 * the rule how bytes stream is extracted as flexible payload
634 * for each payload layer, the setting can up to three elements
636 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
637 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
639 struct i40e_fdir_filter_list fdir_list;
640 struct i40e_fdir_filter **hash_map;
641 struct rte_hash *hash_table;
643 /* Mark if flex pit and mask is set */
644 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
645 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
647 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
650 /* Ethertype filter number HW supports */
651 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
653 /* Ethertype filter struct */
654 struct i40e_ethertype_filter_input {
655 struct ether_addr mac_addr; /* Mac address to match */
656 uint16_t ether_type; /* Ether type to match */
659 struct i40e_ethertype_filter {
660 TAILQ_ENTRY(i40e_ethertype_filter) rules;
661 struct i40e_ethertype_filter_input input;
662 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
663 uint16_t queue; /* Queue assigned to when match */
666 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
668 struct i40e_ethertype_rule {
669 struct i40e_ethertype_filter_list ethertype_list;
670 struct i40e_ethertype_filter **hash_map;
671 struct rte_hash *hash_table;
674 /* queue region info */
675 struct i40e_queue_region_info {
676 /* the region id for this configuration */
678 /* the start queue index for this region */
679 uint8_t queue_start_index;
680 /* the total queue number of this queue region */
682 /* the total number of user priority for this region */
683 uint8_t user_priority_num;
684 /* the packet's user priority for this region */
685 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
686 /* the total number of flowtype for this region */
687 uint8_t flowtype_num;
689 * the pctype or hardware flowtype of packet,
690 * the specific index for each type has been defined
691 * in file i40e_type.h as enum i40e_filter_pctype.
693 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
696 struct i40e_queue_regions {
697 /* the total number of queue region for this port */
698 uint16_t queue_region_number;
699 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
702 /* Tunnel filter number HW supports */
703 #define I40E_MAX_TUNNEL_FILTER_NUM 400
705 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
706 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
707 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
708 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
709 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
710 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
711 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
712 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
713 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
714 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
715 #define I40E_AQC_NEW_TR_21 21
716 #define I40E_AQC_NEW_TR_22 22
718 enum i40e_tunnel_iptype {
719 I40E_TUNNEL_IPTYPE_IPV4,
720 I40E_TUNNEL_IPTYPE_IPV6,
723 /* Tunnel filter struct */
724 struct i40e_tunnel_filter_input {
725 uint8_t outer_mac[6]; /* Outer mac address to match */
726 uint8_t inner_mac[6]; /* Inner mac address to match */
727 uint16_t inner_vlan; /* Inner vlan address to match */
728 enum i40e_tunnel_iptype ip_type;
729 uint16_t flags; /* Filter type flag */
730 uint32_t tenant_id; /* Tenant id to match */
731 uint16_t general_fields[32]; /* Big buffer */
734 struct i40e_tunnel_filter {
735 TAILQ_ENTRY(i40e_tunnel_filter) rules;
736 struct i40e_tunnel_filter_input input;
737 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
738 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
739 uint16_t queue; /* Queue assigned to when match */
742 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
744 struct i40e_tunnel_rule {
745 struct i40e_tunnel_filter_list tunnel_list;
746 struct i40e_tunnel_filter **hash_map;
747 struct rte_hash *hash_table;
753 enum i40e_tunnel_type {
754 I40E_TUNNEL_TYPE_NONE = 0,
755 I40E_TUNNEL_TYPE_VXLAN,
756 I40E_TUNNEL_TYPE_GENEVE,
757 I40E_TUNNEL_TYPE_TEREDO,
758 I40E_TUNNEL_TYPE_NVGRE,
759 I40E_TUNNEL_TYPE_IP_IN_GRE,
760 I40E_L2_TUNNEL_TYPE_E_TAG,
761 I40E_TUNNEL_TYPE_MPLSoUDP,
762 I40E_TUNNEL_TYPE_MPLSoGRE,
763 I40E_TUNNEL_TYPE_QINQ,
764 I40E_TUNNEL_TYPE_GTPC,
765 I40E_TUNNEL_TYPE_GTPU,
766 I40E_TUNNEL_TYPE_MAX,
770 * Tunneling Packet filter configuration.
772 struct i40e_tunnel_filter_conf {
773 struct ether_addr outer_mac; /**< Outer MAC address to match. */
774 struct ether_addr inner_mac; /**< Inner MAC address to match. */
775 uint16_t inner_vlan; /**< Inner VLAN to match. */
776 uint32_t outer_vlan; /**< Outer VLAN to match */
777 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
779 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
780 * is set in filter_type, or inner destination IP address to match
781 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
784 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
785 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
787 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
788 uint16_t filter_type;
789 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
790 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
791 uint16_t queue_id; /**< Queue assigned to if match. */
792 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
793 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
796 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
797 #define I40E_MAX_MIRROR_RULES 64
799 * Mirror rule structure
801 struct i40e_mirror_rule {
802 TAILQ_ENTRY(i40e_mirror_rule) rules;
804 uint16_t index; /* the sw index of mirror rule */
805 uint16_t id; /* the rule id assigned by firmware */
806 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
807 uint16_t num_entries;
808 /* the info stores depend on the rule type.
809 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
810 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
812 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
815 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
818 * Struct to store flow created.
821 TAILQ_ENTRY(rte_flow) node;
822 enum rte_filter_type filter_type;
826 TAILQ_HEAD(i40e_flow_list, rte_flow);
828 /* Struct to store Traffic Manager shaper profile. */
829 struct i40e_tm_shaper_profile {
830 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
831 uint32_t shaper_profile_id;
832 uint32_t reference_count;
833 struct rte_tm_shaper_params profile;
836 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
838 /* node type of Traffic Manager */
839 enum i40e_tm_node_type {
840 I40E_TM_NODE_TYPE_PORT,
841 I40E_TM_NODE_TYPE_TC,
842 I40E_TM_NODE_TYPE_QUEUE,
843 I40E_TM_NODE_TYPE_MAX,
846 /* Struct to store Traffic Manager node configuration. */
847 struct i40e_tm_node {
848 TAILQ_ENTRY(i40e_tm_node) node;
852 uint32_t reference_count;
853 struct i40e_tm_node *parent;
854 struct i40e_tm_shaper_profile *shaper_profile;
855 struct rte_tm_node_params params;
858 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
860 /* Struct to store all the Traffic Manager configuration. */
861 struct i40e_tm_conf {
862 struct i40e_shaper_profile_list shaper_profile_list;
863 struct i40e_tm_node *root; /* root node - port */
864 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
865 struct i40e_tm_node_list queue_list; /* node list for all the queues */
867 * The number of added TC nodes.
868 * It should be no more than the TC number of this port.
872 * The number of added queue nodes.
873 * It should be no more than the queue number of this port.
875 uint32_t nb_queue_node;
877 * This flag is used to check if APP can change the TM node
879 * When it's true, means the configuration is applied to HW,
880 * APP should not change the configuration.
881 * As we don't support on-the-fly configuration, when starting
882 * the port, APP should call the hierarchy_commit API to set this
883 * flag to true. When stopping the port, this flag should be set
889 enum i40e_new_pctype {
890 I40E_CUSTOMIZED_GTPC = 0,
891 I40E_CUSTOMIZED_GTPU_IPV4,
892 I40E_CUSTOMIZED_GTPU_IPV6,
893 I40E_CUSTOMIZED_GTPU,
897 #define I40E_FILTER_PCTYPE_INVALID 0
898 struct i40e_customized_pctype {
899 enum i40e_new_pctype index; /* Indicate which customized pctype */
900 uint8_t pctype; /* New pctype value */
901 bool valid; /* Check if it's valid */
905 * Structure to store private data specific for PF instance.
908 struct i40e_adapter *adapter; /* The adapter this PF associate to */
909 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
910 uint16_t mac_seid; /* The seid of the MAC of this PF */
911 uint16_t main_vsi_seid; /* The seid of the main VSI */
912 uint16_t max_num_vsi;
913 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
914 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
916 struct i40e_hw_port_stats stats_offset;
917 struct i40e_hw_port_stats stats;
918 /* internal packet statistics, it should be excluded from the total */
919 struct i40e_eth_stats internal_stats_offset;
920 struct i40e_eth_stats internal_stats;
923 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
924 struct ether_addr dev_addr; /* PF device mac address */
925 uint64_t flags; /* PF feature flags */
926 /* All kinds of queue pair setting for different VSIs */
927 struct i40e_pf_vf *vfs;
929 /* Each of below queue pairs should be power of 2 since it's the
930 precondition after TC configuration applied */
931 uint16_t lan_nb_qp_max;
932 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
933 uint16_t lan_qp_offset;
934 uint16_t vmdq_nb_qp_max;
935 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
936 uint16_t vmdq_qp_offset;
937 uint16_t vf_nb_qp_max;
938 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
939 uint16_t vf_qp_offset;
940 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
941 uint16_t fdir_qp_offset;
943 uint16_t hash_lut_size; /* The size of hash lookup table */
944 /* input set bits for each pctype */
945 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
946 /* store VXLAN UDP ports */
947 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
948 uint16_t vxlan_bitmap; /* Vxlan bit mask */
950 /* VMDQ related info */
951 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
952 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
953 struct i40e_vmdq_info *vmdq;
955 struct i40e_fdir_info fdir; /* flow director info */
956 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
957 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
958 struct i40e_queue_regions queue_region; /* queue region info */
959 struct i40e_fc_conf fc_conf; /* Flow control conf */
960 struct i40e_mirror_rule_list mirror_list;
961 uint16_t nb_mirror_rule; /* The number of mirror rules */
962 bool floating_veb; /* The flag to use the floating VEB */
963 /* The floating enable flag for the specific VF */
964 bool floating_veb_list[I40E_MAX_VF];
965 struct i40e_flow_list flow_list;
966 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
967 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
968 bool qinq_replace_flag; /* QINQ filter replace is done */
969 struct i40e_tm_conf tm_conf;
970 bool support_multi_driver; /* 1 - support multiple driver */
972 /* Dynamic Device Personalization */
973 bool gtp_support; /* 1 - support GTP-C and GTP-U */
974 /* customer customized pctype */
975 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
979 PFMSG_LINK_CHANGE = 0x1,
980 PFMSG_RESET_IMPENDING = 0x2,
981 PFMSG_DRIVER_CLOSE = 0x4,
984 struct i40e_vsi_vlan_pvid_info {
985 uint16_t on; /* Enable or disable pvid */
987 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
989 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
990 * while 'untagged' will reject untagged packets.
998 struct i40e_vf_rx_queues {
999 uint64_t rx_dma_addr;
1000 uint32_t rx_ring_len;
1004 struct i40e_vf_tx_queues {
1005 uint64_t tx_dma_addr;
1006 uint32_t tx_ring_len;
1010 * Structure to store private data specific for VF instance.
1013 struct i40e_adapter *adapter; /* The adapter this VF associate to */
1014 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
1015 uint16_t num_queue_pairs;
1016 uint16_t max_pkt_len; /* Maximum packet length */
1017 bool promisc_unicast_enabled;
1018 bool promisc_multicast_enabled;
1020 uint32_t version_major; /* Major version number */
1021 uint32_t version_minor; /* Minor version number */
1022 uint16_t promisc_flags; /* Promiscuous setting */
1023 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
1028 enum virtchnl_link_speed link_speed;
1030 volatile uint32_t pend_cmd; /* pending command not finished yet */
1031 int32_t cmd_retval; /* return value of the cmd response from PF */
1032 u16 pend_msg; /* flags indicates events from pf not handled yet */
1033 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
1036 struct virtchnl_vf_resource *vf_res; /* All VSIs */
1037 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1038 struct i40e_vsi vsi;
1042 #define I40E_MAX_PKT_TYPE 256
1043 #define I40E_FLOW_TYPE_MAX 64
1046 * Structure to store private data for each PF/VF instance.
1048 struct i40e_adapter {
1049 /* Common for both PF and VF */
1051 struct rte_eth_dev *eth_dev;
1053 /* Specific for PF or VF */
1059 /* For vector PMD */
1060 bool rx_bulk_alloc_allowed;
1061 bool rx_vec_allowed;
1062 bool tx_simple_allowed;
1063 bool tx_vec_allowed;
1066 struct rte_timecounter systime_tc;
1067 struct rte_timecounter rx_tstamp_tc;
1068 struct rte_timecounter tx_tstamp_tc;
1070 /* ptype mapping table */
1071 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1072 /* flow type to pctype mapping table */
1073 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1074 uint64_t flow_types_mask;
1075 uint64_t pctypes_mask;
1078 extern const struct rte_flow_ops i40e_flow_ops;
1080 union i40e_filter_t {
1081 struct rte_eth_ethertype_filter ethertype_filter;
1082 struct i40e_fdir_filter_conf fdir_filter;
1083 struct rte_eth_tunnel_filter_conf tunnel_filter;
1084 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1087 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1088 const struct rte_flow_attr *attr,
1089 const struct rte_flow_item pattern[],
1090 const struct rte_flow_action actions[],
1091 struct rte_flow_error *error,
1092 union i40e_filter_t *filter);
1093 struct i40e_valid_pattern {
1094 enum rte_flow_item_type *items;
1095 parse_filter_t parse_filter;
1098 enum I40E_WARNING_IDX {
1099 I40E_WARNING_DIS_FLX_PLD,
1100 I40E_WARNING_ENA_FLX_PLD,
1101 I40E_WARNING_QINQ_PARSER,
1102 I40E_WARNING_QINQ_CLOUD_FILTER,
1104 I40E_WARNING_FLOW_CTL,
1105 I40E_WARNING_GRE_KEY_LEN,
1106 I40E_WARNING_QF_CTL,
1107 I40E_WARNING_HASH_INSET,
1109 I40E_WARNING_HASH_MSK,
1110 I40E_WARNING_FD_MSK,
1111 I40E_WARNING_RPL_CLD_FILTER,
1114 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1115 int i40e_vsi_release(struct i40e_vsi *vsi);
1116 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1117 enum i40e_vsi_type type,
1118 struct i40e_vsi *uplink_vsi,
1119 uint16_t user_param);
1120 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1121 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1122 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1123 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1124 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1125 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1126 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1127 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1128 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1129 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1130 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1131 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1132 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1133 struct i40e_vsi_vlan_pvid_info *info);
1134 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1135 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1136 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1137 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1138 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1139 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1140 int i40e_fdir_setup(struct i40e_pf *pf);
1141 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1144 int i40e_fdir_configure(struct rte_eth_dev *dev);
1145 void i40e_fdir_teardown(struct i40e_pf *pf);
1146 enum i40e_filter_pctype
1147 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1148 uint16_t flow_type);
1149 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1150 enum i40e_filter_pctype pctype);
1151 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1152 enum rte_filter_op filter_op,
1154 int i40e_select_filter_input_set(struct i40e_hw *hw,
1155 struct rte_eth_input_set_conf *conf,
1156 enum rte_filter_type filter);
1157 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1158 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1159 struct rte_eth_input_set_conf *conf);
1160 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1161 struct rte_eth_input_set_conf *conf);
1162 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1163 uint32_t retval, uint8_t *msg,
1165 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1166 struct rte_eth_rxq_info *qinfo);
1167 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1168 struct rte_eth_txq_info *qinfo);
1169 struct i40e_ethertype_filter *
1170 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1171 const struct i40e_ethertype_filter_input *input);
1172 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1173 struct i40e_ethertype_filter_input *input);
1174 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1175 struct i40e_fdir_input *input);
1176 struct i40e_tunnel_filter *
1177 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1178 const struct i40e_tunnel_filter_input *input);
1179 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1180 struct i40e_tunnel_filter_input *input);
1181 uint64_t i40e_get_default_input_set(uint16_t pctype);
1182 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1183 struct rte_eth_ethertype_filter *filter,
1185 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1186 const struct rte_eth_fdir_filter *filter,
1188 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1189 const struct i40e_fdir_filter_conf *filter,
1191 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1192 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1194 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1195 struct i40e_tunnel_filter_conf *tunnel_filter,
1197 int i40e_fdir_flush(struct rte_eth_dev *dev);
1198 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1199 struct i40e_macvlan_filter *mv_f,
1200 int num, struct ether_addr *addr);
1201 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1202 struct i40e_macvlan_filter *filter,
1204 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1205 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1206 struct i40e_macvlan_filter *filter,
1208 bool is_i40e_supported(struct rte_eth_dev *dev);
1210 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1211 enum rte_filter_type filter, uint64_t inset);
1212 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1214 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1215 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1216 void i40e_check_write_global_reg(struct i40e_hw *hw,
1217 uint32_t addr, uint32_t val);
1219 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1220 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1221 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1222 struct i40e_customized_pctype*
1223 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1224 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1226 enum rte_pmd_i40e_package_op op);
1227 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1228 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1229 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1230 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1232 #define I40E_DEV_TO_PCI(eth_dev) \
1233 RTE_DEV_TO_PCI((eth_dev)->device)
1235 /* I40E_DEV_PRIVATE_TO */
1236 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1237 (&((struct i40e_adapter *)adapter)->pf)
1238 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1239 (&((struct i40e_adapter *)adapter)->hw)
1240 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1241 ((struct i40e_adapter *)adapter)
1243 /* I40EVF_DEV_PRIVATE_TO */
1244 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1245 (&((struct i40e_adapter *)adapter)->vf)
1247 static inline struct i40e_vsi *
1248 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1255 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1256 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1257 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1260 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1261 return pf->main_vsi;
1264 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1265 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1268 #define I40E_VSI_TO_HW(vsi) \
1269 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1270 #define I40E_VSI_TO_PF(vsi) \
1271 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1272 #define I40E_VSI_TO_VF(vsi) \
1273 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1274 #define I40E_VSI_TO_DEV_DATA(vsi) \
1275 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1276 #define I40E_VSI_TO_ETH_DEV(vsi) \
1277 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1280 #define I40E_PF_TO_HW(pf) \
1281 (&(((struct i40e_pf *)pf)->adapter->hw))
1282 #define I40E_PF_TO_ADAPTER(pf) \
1283 ((struct i40e_adapter *)pf->adapter)
1286 #define I40E_VF_TO_HW(vf) \
1287 (&(((struct i40e_vf *)vf)->adapter->hw))
1290 i40e_init_adminq_parameter(struct i40e_hw *hw)
1292 hw->aq.num_arq_entries = I40E_AQ_LEN;
1293 hw->aq.num_asq_entries = I40E_AQ_LEN;
1294 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1295 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1299 i40e_align_floor(int n)
1303 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1306 static inline uint16_t
1307 i40e_calc_itr_interval(int16_t interval, bool is_multi_drv)
1310 interval = I40E_QUEUE_ITR_INTERVAL_MAX;
1311 else if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
1312 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1314 /* Convert to hardware count, as writing each 1 represents 2 us */
1315 return interval / 2;
1319 i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
1321 const char *warning;
1322 static const char *const warning_list[] = {
1323 [I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
1324 [I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
1325 [I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
1326 [I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
1327 [I40E_WARNING_TPID] = "support TPID configuration",
1328 [I40E_WARNING_FLOW_CTL] = "configure water marker",
1329 [I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
1330 [I40E_WARNING_QF_CTL] = "support hash function setting",
1331 [I40E_WARNING_HASH_INSET] = "configure hash input set",
1332 [I40E_WARNING_HSYM] = "set symmetric hash",
1333 [I40E_WARNING_HASH_MSK] = "configure hash mask",
1334 [I40E_WARNING_FD_MSK] = "configure fdir mask",
1335 [I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
1338 warning = warning_list[idx];
1340 RTE_LOG(WARNING, PMD,
1341 "Global register is changed during %s\n",
1345 #define I40E_VALID_FLOW(flow_type) \
1346 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1347 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1348 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1349 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1350 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1351 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1352 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1353 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1354 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1355 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1356 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1358 #define I40E_VALID_PCTYPE_X722(pctype) \
1359 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1360 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1361 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1362 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1363 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1364 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1365 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1366 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1367 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1368 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1369 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1370 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1371 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1372 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1373 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1374 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1375 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1377 #define I40E_VALID_PCTYPE(pctype) \
1378 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1379 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1380 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1381 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1382 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1383 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1384 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1385 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1386 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1387 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1388 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1390 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1391 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1392 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1393 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1394 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1395 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1396 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1398 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1399 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1400 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1401 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1402 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1404 #endif /* _I40E_ETHDEV_H_ */