drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_atomic.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71
  72 /* busy wait delay in msec */
  73 #define I40EVF_BUSY_WAIT_DELAY 10
  74 #define I40EVF_BUSY_WAIT_COUNT 50
  75 #define MAX_RESET_WAIT_CNT     20
  76
  77 struct i40evf_arq_msg_info {
  78         enum i40e_virtchnl_ops ops;
  79         enum i40e_status_code result;
  80         uint16_t buf_len;
  81         uint16_t msg_len;
  82         uint8_t *msg;
  83 };
  84
  85 struct vf_cmd_info {
  86         enum i40e_virtchnl_ops ops;
  87         uint8_t *in_args;
  88         uint32_t in_args_size;
  89         uint8_t *out_buffer;
  90         /* Input & output type. pass in buffer size and pass out
  91          * actual return result
  92          */
  93         uint32_t out_size;
  94 };
  95
  96 enum i40evf_aq_result {
  97         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  98         I40EVF_MSG_NON,      /* Read nothing from admin queue */
  99         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 100         I40EVF_MSG_CMD,      /* Read async command result */
 101 };
 102
 103 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 104 static int i40evf_dev_start(struct rte_eth_dev *dev);
 105 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 106 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_dev_info *dev_info);
 108 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 109                                   __rte_unused int wait_to_complete);
 110 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_stats *stats);
 112 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 113                                  struct rte_eth_xstat *xstats, unsigned n);
 114 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 115                                        struct rte_eth_xstat_name *xstats_names,
 116                                        unsigned limit);
 117 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 118 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 119                                   uint16_t vlan_id, int on);
 120 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 121 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
 122                                 int on);
 123 static void i40evf_dev_close(struct rte_eth_dev *dev);
 124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 130                                      uint16_t rx_queue_id);
 131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 132                                     uint16_t rx_queue_id);
 133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 134                                      uint16_t tx_queue_id);
 135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 136                                     uint16_t tx_queue_id);
 137 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
 138                                 struct ether_addr *addr,
 139                                 uint32_t index,
 140                                 uint32_t pool);
 141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 143                         struct rte_eth_rss_reta_entry64 *reta_conf,
 144                         uint16_t reta_size);
 145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                         struct rte_eth_rss_reta_entry64 *reta_conf,
 147                         uint16_t reta_size);
 148 static int i40evf_config_rss(struct i40e_vf *vf);
 149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 150                                       struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 152                                         struct rte_eth_rss_conf *rss_conf);
 153 static int
 154 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 155 static int
 156 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 157 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
 158                                    uint8_t *msg,
 159                                    uint16_t msglen);
 160
 161 /* Default hash key buffer for RSS */
 162 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 163
 164 struct rte_i40evf_xstats_name_off {
 165         char name[RTE_ETH_XSTATS_NAME_SIZE];
 166         unsigned offset;
 167 };
 168
 169 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 170         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 171         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 172         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 173         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 174         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 175         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 176                 rx_unknown_protocol)},
 177         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 178         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 179         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 180         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 181         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 182         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 183 };
 184
 185 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 186                 sizeof(rte_i40evf_stats_strings[0]))
 187
 188 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 189         .dev_configure        = i40evf_dev_configure,
 190         .dev_start            = i40evf_dev_start,
 191         .dev_stop             = i40evf_dev_stop,
 192         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 193         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 194         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 195         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 196         .link_update          = i40evf_dev_link_update,
 197         .stats_get            = i40evf_dev_stats_get,
 198         .xstats_get           = i40evf_dev_xstats_get,
 199         .xstats_get_names     = i40evf_dev_xstats_get_names,
 200         .xstats_reset         = i40evf_dev_xstats_reset,
 201         .dev_close            = i40evf_dev_close,
 202         .dev_infos_get        = i40evf_dev_info_get,
 203         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 204         .vlan_filter_set      = i40evf_vlan_filter_set,
 205         .vlan_offload_set     = i40evf_vlan_offload_set,
 206         .vlan_pvid_set        = i40evf_vlan_pvid_set,
 207         .rx_queue_start       = i40evf_dev_rx_queue_start,
 208         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 209         .tx_queue_start       = i40evf_dev_tx_queue_start,
 210         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 211         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 212         .rx_queue_release     = i40e_dev_rx_queue_release,
 213         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 214         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 215         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 216         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 217         .tx_queue_release     = i40e_dev_tx_queue_release,
 218         .rx_queue_count       = i40e_dev_rx_queue_count,
 219         .rxq_info_get         = i40e_rxq_info_get,
 220         .txq_info_get         = i40e_txq_info_get,
 221         .mac_addr_add         = i40evf_add_mac_addr,
 222         .mac_addr_remove      = i40evf_del_mac_addr,
 223         .reta_update          = i40evf_dev_rss_reta_update,
 224         .reta_query           = i40evf_dev_rss_reta_query,
 225         .rss_hash_update      = i40evf_dev_rss_hash_update,
 226         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 227 };
 228
 229 /*
 230  * Read data in admin queue to get msg from pf driver
 231  */
 232 static enum i40evf_aq_result
 233 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 234 {
 235         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 236         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 237         struct i40e_arq_event_info event;
 238         enum i40e_virtchnl_ops opcode;
 239         enum i40e_status_code retval;
 240         int ret;
 241         enum i40evf_aq_result result = I40EVF_MSG_NON;
 242
 243         event.buf_len = data->buf_len;
 244         event.msg_buf = data->msg;
 245         ret = i40e_clean_arq_element(hw, &event, NULL);
 246         /* Can't read any msg from adminQ */
 247         if (ret) {
 248                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 249                         result = I40EVF_MSG_ERR;
 250                 return result;
 251         }
 252
 253         opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 254         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 255         /* pf sys event */
 256         if (opcode == I40E_VIRTCHNL_OP_EVENT) {
 257                 struct i40e_virtchnl_pf_event *vpe =
 258                         (struct i40e_virtchnl_pf_event *)event.msg_buf;
 259
 260                 result = I40EVF_MSG_SYS;
 261                 switch (vpe->event) {
 262                 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
 263                         vf->link_up =
 264                                 vpe->event_data.link_event.link_status;
 265                         vf->link_speed =
 266                                 vpe->event_data.link_event.link_speed;
 267                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 268                         PMD_DRV_LOG(INFO, "Link status update:%s",
 269                                     vf->link_up ? "up" : "down");
 270                         break;
 271                 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
 272                         vf->vf_reset = true;
 273                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 274                         PMD_DRV_LOG(INFO, "vf is reseting");
 275                         break;
 276                 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 277                         vf->dev_closed = true;
 278                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 279                         PMD_DRV_LOG(INFO, "PF driver closed");
 280                         break;
 281                 default:
 282                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 283                                     __func__, vpe->event);
 284                 }
 285         } else {
 286                 /* async reply msg on command issued by vf previously */
 287                 result = I40EVF_MSG_CMD;
 288                 /* Actual data length read from PF */
 289                 data->msg_len = event.msg_len;
 290         }
 291
 292         data->result = retval;
 293         data->ops = opcode;
 294
 295         return result;
 296 }
 297
 298 /**
 299  * clear current command. Only call in case execute
 300  * _atomic_set_cmd successfully.
 301  */
 302 static inline void
 303 _clear_cmd(struct i40e_vf *vf)
 304 {
 305         rte_wmb();
 306         vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
 307 }
 308
 309 /*
 310  * Check there is pending cmd in execution. If none, set new command.
 311  */
 312 static inline int
 313 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
 314 {
 315         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 316                         I40E_VIRTCHNL_OP_UNKNOWN, ops);
 317
 318         if (!ret)
 319                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 320
 321         return !ret;
 322 }
 323
 324 #define MAX_TRY_TIMES 200
 325 #define ASQ_DELAY_MS  10
 326
 327 static int
 328 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 329 {
 330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 331         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 332         struct i40evf_arq_msg_info info;
 333         enum i40evf_aq_result ret;
 334         int err, i = 0;
 335
 336         if (_atomic_set_cmd(vf, args->ops))
 337                 return -1;
 338
 339         info.msg = args->out_buffer;
 340         info.buf_len = args->out_size;
 341         info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
 342         info.result = I40E_SUCCESS;
 343
 344         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 345                      args->in_args, args->in_args_size, NULL);
 346         if (err) {
 347                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 348                 _clear_cmd(vf);
 349                 return err;
 350         }
 351
 352         switch (args->ops) {
 353         case I40E_VIRTCHNL_OP_RESET_VF:
 354                 /*no need to process in this function */
 355                 err = 0;
 356                 break;
 357         case I40E_VIRTCHNL_OP_VERSION:
 358         case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
 359                 /* for init adminq commands, need to poll the response */
 360                 err = -1;
 361                 do {
 362                         ret = i40evf_read_pfmsg(dev, &info);
 363                         vf->cmd_retval = info.result;
 364                         if (ret == I40EVF_MSG_CMD) {
 365                                 err = 0;
 366                                 break;
 367                         } else if (ret == I40EVF_MSG_ERR)
 368                                 break;
 369                         rte_delay_ms(ASQ_DELAY_MS);
 370                         /* If don't read msg or read sys event, continue */
 371                 } while (i++ < MAX_TRY_TIMES);
 372                 _clear_cmd(vf);
 373                 break;
 374
 375         default:
 376                 /* for other adminq in running time, waiting the cmd done flag */
 377                 err = -1;
 378                 do {
 379                         if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
 380                                 err = 0;
 381                                 break;
 382                         }
 383                         rte_delay_ms(ASQ_DELAY_MS);
 384                         /* If don't read msg or read sys event, continue */
 385                 } while (i++ < MAX_TRY_TIMES);
 386                 break;
 387         }
 388
 389         return err | vf->cmd_retval;
 390 }
 391
 392 /*
 393  * Check API version with sync wait until version read or fail from admin queue
 394  */
 395 static int
 396 i40evf_check_api_version(struct rte_eth_dev *dev)
 397 {
 398         struct i40e_virtchnl_version_info version, *pver;
 399         int err;
 400         struct vf_cmd_info args;
 401         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 402
 403         version.major = I40E_VIRTCHNL_VERSION_MAJOR;
 404         version.minor = I40E_VIRTCHNL_VERSION_MINOR;
 405
 406         args.ops = I40E_VIRTCHNL_OP_VERSION;
 407         args.in_args = (uint8_t *)&version;
 408         args.in_args_size = sizeof(version);
 409         args.out_buffer = vf->aq_resp;
 410         args.out_size = I40E_AQ_BUF_SZ;
 411
 412         err = i40evf_execute_vf_cmd(dev, &args);
 413         if (err) {
 414                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 415                 return err;
 416         }
 417
 418         pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
 419         vf->version_major = pver->major;
 420         vf->version_minor = pver->minor;
 421         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 422                 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
 423         else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
 424                 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
 425                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 426         else {
 427                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 428                                         vf->version_major, vf->version_minor,
 429                                                 I40E_VIRTCHNL_VERSION_MAJOR,
 430                                                 I40E_VIRTCHNL_VERSION_MINOR);
 431                 return -1;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int
 438 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 439 {
 440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 441         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 442         int err;
 443         struct vf_cmd_info args;
 444         uint32_t caps, len;
 445
 446         args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
 447         args.out_buffer = vf->aq_resp;
 448         args.out_size = I40E_AQ_BUF_SZ;
 449         if (PF_IS_V11(vf)) {
 450                 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
 451                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 452                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
 453                        I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
 454                        I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 455                 args.in_args = (uint8_t *)&caps;
 456                 args.in_args_size = sizeof(caps);
 457         } else {
 458                 args.in_args = NULL;
 459                 args.in_args_size = 0;
 460         }
 461         err = i40evf_execute_vf_cmd(dev, &args);
 462
 463         if (err) {
 464                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 465                 return err;
 466         }
 467
 468         len =  sizeof(struct i40e_virtchnl_vf_resource) +
 469                 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
 470
 471         (void)rte_memcpy(vf->vf_res, args.out_buffer,
 472                         RTE_MIN(args.out_size, len));
 473         i40e_vf_parse_hw_config(hw, vf->vf_res);
 474
 475         return 0;
 476 }
 477
 478 static int
 479 i40evf_config_promisc(struct rte_eth_dev *dev,
 480                       bool enable_unicast,
 481                       bool enable_multicast)
 482 {
 483         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 484         int err;
 485         struct vf_cmd_info args;
 486         struct i40e_virtchnl_promisc_info promisc;
 487
 488         promisc.flags = 0;
 489         promisc.vsi_id = vf->vsi_res->vsi_id;
 490
 491         if (enable_unicast)
 492                 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
 493
 494         if (enable_multicast)
 495                 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
 496
 497         args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 498         args.in_args = (uint8_t *)&promisc;
 499         args.in_args_size = sizeof(promisc);
 500         args.out_buffer = vf->aq_resp;
 501         args.out_size = I40E_AQ_BUF_SZ;
 502
 503         err = i40evf_execute_vf_cmd(dev, &args);
 504
 505         if (err)
 506                 PMD_DRV_LOG(ERR, "fail to execute command "
 507                             "CONFIG_PROMISCUOUS_MODE");
 508         return err;
 509 }
 510
 511 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
 512 static int
 513 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
 514                                 bool enable_vlan_strip)
 515 {
 516         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 517         int err;
 518         struct vf_cmd_info args;
 519         struct i40e_virtchnl_vlan_offload_info offload;
 520
 521         offload.vsi_id = vf->vsi_res->vsi_id;
 522         offload.enable_vlan_strip = enable_vlan_strip;
 523
 524         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
 525         args.in_args = (uint8_t *)&offload;
 526         args.in_args_size = sizeof(offload);
 527         args.out_buffer = vf->aq_resp;
 528         args.out_size = I40E_AQ_BUF_SZ;
 529
 530         err = i40evf_execute_vf_cmd(dev, &args);
 531         if (err)
 532                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
 533
 534         return err;
 535 }
 536
 537 static int
 538 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
 539                                 struct i40e_vsi_vlan_pvid_info *info)
 540 {
 541         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 542         int err;
 543         struct vf_cmd_info args;
 544         struct i40e_virtchnl_pvid_info tpid_info;
 545
 546         if (info == NULL) {
 547                 PMD_DRV_LOG(ERR, "invalid parameters");
 548                 return I40E_ERR_PARAM;
 549         }
 550
 551         memset(&tpid_info, 0, sizeof(tpid_info));
 552         tpid_info.vsi_id = vf->vsi_res->vsi_id;
 553         (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
 554
 555         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
 556         args.in_args = (uint8_t *)&tpid_info;
 557         args.in_args_size = sizeof(tpid_info);
 558         args.out_buffer = vf->aq_resp;
 559         args.out_size = I40E_AQ_BUF_SZ;
 560
 561         err = i40evf_execute_vf_cmd(dev, &args);
 562         if (err)
 563                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
 564
 565         return err;
 566 }
 567
 568 static void
 569 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
 570                                   uint16_t vsi_id,
 571                                   uint16_t queue_id,
 572                                   uint16_t nb_txq,
 573                                   struct i40e_tx_queue *txq)
 574 {
 575         txq_info->vsi_id = vsi_id;
 576         txq_info->queue_id = queue_id;
 577         if (queue_id < nb_txq) {
 578                 txq_info->ring_len = txq->nb_tx_desc;
 579                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 580         }
 581 }
 582
 583 static void
 584 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
 585                                   uint16_t vsi_id,
 586                                   uint16_t queue_id,
 587                                   uint16_t nb_rxq,
 588                                   uint32_t max_pkt_size,
 589                                   struct i40e_rx_queue *rxq)
 590 {
 591         rxq_info->vsi_id = vsi_id;
 592         rxq_info->queue_id = queue_id;
 593         rxq_info->max_pkt_size = max_pkt_size;
 594         if (queue_id < nb_rxq) {
 595                 rxq_info->ring_len = rxq->nb_rx_desc;
 596                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 597                 rxq_info->databuffer_size =
 598                         (rte_pktmbuf_data_room_size(rxq->mp) -
 599                                 RTE_PKTMBUF_HEADROOM);
 600         }
 601 }
 602
 603 /* It configures VSI queues to co-work with Linux PF host */
 604 static int
 605 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 606 {
 607         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 608         struct i40e_rx_queue **rxq =
 609                 (struct i40e_rx_queue **)dev->data->rx_queues;
 610         struct i40e_tx_queue **txq =
 611                 (struct i40e_tx_queue **)dev->data->tx_queues;
 612         struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
 613         struct i40e_virtchnl_queue_pair_info *vc_qpi;
 614         struct vf_cmd_info args;
 615         uint16_t i, nb_qp = vf->num_queue_pairs;
 616         const uint32_t size =
 617                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 618         uint8_t buff[size];
 619         int ret;
 620
 621         memset(buff, 0, sizeof(buff));
 622         vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
 623         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 624         vc_vqci->num_queue_pairs = nb_qp;
 625
 626         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 627                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 628                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 629                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 630                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 631                                         vf->max_pkt_len, rxq[i]);
 632         }
 633         memset(&args, 0, sizeof(args));
 634         args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 635         args.in_args = (uint8_t *)vc_vqci;
 636         args.in_args_size = size;
 637         args.out_buffer = vf->aq_resp;
 638         args.out_size = I40E_AQ_BUF_SZ;
 639         ret = i40evf_execute_vf_cmd(dev, &args);
 640         if (ret)
 641                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 642                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
 643
 644         return ret;
 645 }
 646
 647 /* It configures VSI queues to co-work with DPDK PF host */
 648 static int
 649 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
 650 {
 651         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 652         struct i40e_rx_queue **rxq =
 653                 (struct i40e_rx_queue **)dev->data->rx_queues;
 654         struct i40e_tx_queue **txq =
 655                 (struct i40e_tx_queue **)dev->data->tx_queues;
 656         struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
 657         struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
 658         struct vf_cmd_info args;
 659         uint16_t i, nb_qp = vf->num_queue_pairs;
 660         const uint32_t size =
 661                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
 662         uint8_t buff[size];
 663         int ret;
 664
 665         memset(buff, 0, sizeof(buff));
 666         vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
 667         vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
 668         vc_vqcei->num_queue_pairs = nb_qp;
 669         vc_qpei = vc_vqcei->qpair;
 670         for (i = 0; i < nb_qp; i++, vc_qpei++) {
 671                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
 672                         vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 673                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
 674                         vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
 675                                         vf->max_pkt_len, rxq[i]);
 676                 if (i < dev->data->nb_rx_queues)
 677                         /*
 678                          * It adds extra info for configuring VSI queues, which
 679                          * is needed to enable the configurable crc stripping
 680                          * in VF.
 681                          */
 682                         vc_qpei->rxq_ext.crcstrip =
 683                                 dev->data->dev_conf.rxmode.hw_strip_crc;
 684         }
 685         memset(&args, 0, sizeof(args));
 686         args.ops =
 687                 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
 688         args.in_args = (uint8_t *)vc_vqcei;
 689         args.in_args_size = size;
 690         args.out_buffer = vf->aq_resp;
 691         args.out_size = I40E_AQ_BUF_SZ;
 692         ret = i40evf_execute_vf_cmd(dev, &args);
 693         if (ret)
 694                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 695                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
 696
 697         return ret;
 698 }
 699
 700 static int
 701 i40evf_configure_queues(struct rte_eth_dev *dev)
 702 {
 703         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 704
 705         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 706                 /* To support DPDK PF host */
 707                 return i40evf_configure_vsi_queues_ext(dev);
 708         else
 709                 /* To support Linux PF host */
 710                 return i40evf_configure_vsi_queues(dev);
 711 }
 712
 713 static int
 714 i40evf_config_irq_map(struct rte_eth_dev *dev)
 715 {
 716         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 717         struct vf_cmd_info args;
 718         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
 719                 sizeof(struct i40e_virtchnl_vector_map)];
 720         struct i40e_virtchnl_irq_map_info *map_info;
 721         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 722         uint32_t vector_id;
 723         int i, err;
 724
 725         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
 726             rte_intr_allow_others(intr_handle)) {
 727                 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 728                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
 729                 else
 730                         vector_id = I40E_RX_VEC_START;
 731         } else {
 732                 vector_id = I40E_MISC_VEC_ID;
 733         }
 734
 735         map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
 736         map_info->num_vectors = 1;
 737         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 738         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 739         /* Alway use default dynamic MSIX interrupt */
 740         map_info->vecmap[0].vector_id = vector_id;
 741         /* Don't map any tx queue */
 742         map_info->vecmap[0].txq_map = 0;
 743         map_info->vecmap[0].rxq_map = 0;
 744         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 745                 map_info->vecmap[0].rxq_map |= 1 << i;
 746                 if (rte_intr_dp_is_en(intr_handle))
 747                         intr_handle->intr_vec[i] = vector_id;
 748         }
 749
 750         args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
 751         args.in_args = (u8 *)cmd_buffer;
 752         args.in_args_size = sizeof(cmd_buffer);
 753         args.out_buffer = vf->aq_resp;
 754         args.out_size = I40E_AQ_BUF_SZ;
 755         err = i40evf_execute_vf_cmd(dev, &args);
 756         if (err)
 757                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 758
 759         return err;
 760 }
 761
 762 static int
 763 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 764                                 bool on)
 765 {
 766         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 767         struct i40e_virtchnl_queue_select queue_select;
 768         int err;
 769         struct vf_cmd_info args;
 770         memset(&queue_select, 0, sizeof(queue_select));
 771         queue_select.vsi_id = vf->vsi_res->vsi_id;
 772
 773         if (isrx)
 774                 queue_select.rx_queues |= 1 << qid;
 775         else
 776                 queue_select.tx_queues |= 1 << qid;
 777
 778         if (on)
 779                 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
 780         else
 781                 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
 782         args.in_args = (u8 *)&queue_select;
 783         args.in_args_size = sizeof(queue_select);
 784         args.out_buffer = vf->aq_resp;
 785         args.out_size = I40E_AQ_BUF_SZ;
 786         err = i40evf_execute_vf_cmd(dev, &args);
 787         if (err)
 788                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 789                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 790
 791         return err;
 792 }
 793
 794 static int
 795 i40evf_start_queues(struct rte_eth_dev *dev)
 796 {
 797         struct rte_eth_dev_data *dev_data = dev->data;
 798         int i;
 799         struct i40e_rx_queue *rxq;
 800         struct i40e_tx_queue *txq;
 801
 802         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 803                 rxq = dev_data->rx_queues[i];
 804                 if (rxq->rx_deferred_start)
 805                         continue;
 806                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 807                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 808                         return -1;
 809                 }
 810         }
 811
 812         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 813                 txq = dev_data->tx_queues[i];
 814                 if (txq->tx_deferred_start)
 815                         continue;
 816                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 817                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 818                         return -1;
 819                 }
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int
 826 i40evf_stop_queues(struct rte_eth_dev *dev)
 827 {
 828         int i;
 829
 830         /* Stop TX queues first */
 831         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 832                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 833                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 834                         return -1;
 835                 }
 836         }
 837
 838         /* Then stop RX queues */
 839         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 840                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 841                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 842                         return -1;
 843                 }
 844         }
 845
 846         return 0;
 847 }
 848
 849 static void
 850 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 851                     struct ether_addr *addr,
 852                     __rte_unused uint32_t index,
 853                     __rte_unused uint32_t pool)
 854 {
 855         struct i40e_virtchnl_ether_addr_list *list;
 856         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 857         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 858                         sizeof(struct i40e_virtchnl_ether_addr)];
 859         int err;
 860         struct vf_cmd_info args;
 861
 862         if (is_zero_ether_addr(addr)) {
 863                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 864                             addr->addr_bytes[0], addr->addr_bytes[1],
 865                             addr->addr_bytes[2], addr->addr_bytes[3],
 866                             addr->addr_bytes[4], addr->addr_bytes[5]);
 867                 return;
 868         }
 869
 870         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 871         list->vsi_id = vf->vsi_res->vsi_id;
 872         list->num_elements = 1;
 873         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 874                                         sizeof(addr->addr_bytes));
 875
 876         args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
 877         args.in_args = cmd_buffer;
 878         args.in_args_size = sizeof(cmd_buffer);
 879         args.out_buffer = vf->aq_resp;
 880         args.out_size = I40E_AQ_BUF_SZ;
 881         err = i40evf_execute_vf_cmd(dev, &args);
 882         if (err)
 883                 PMD_DRV_LOG(ERR, "fail to execute command "
 884                             "OP_ADD_ETHER_ADDRESS");
 885
 886         return;
 887 }
 888
 889 static void
 890 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 891 {
 892         struct i40e_virtchnl_ether_addr_list *list;
 893         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 894         struct rte_eth_dev_data *data = dev->data;
 895         struct ether_addr *addr;
 896         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 897                         sizeof(struct i40e_virtchnl_ether_addr)];
 898         int err;
 899         struct vf_cmd_info args;
 900
 901         addr = &(data->mac_addrs[index]);
 902
 903         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 904                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 905                             addr->addr_bytes[0], addr->addr_bytes[1],
 906                             addr->addr_bytes[2], addr->addr_bytes[3],
 907                             addr->addr_bytes[4], addr->addr_bytes[5]);
 908                 return;
 909         }
 910
 911         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 912         list->vsi_id = vf->vsi_res->vsi_id;
 913         list->num_elements = 1;
 914         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 915                         sizeof(addr->addr_bytes));
 916
 917         args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
 918         args.in_args = cmd_buffer;
 919         args.in_args_size = sizeof(cmd_buffer);
 920         args.out_buffer = vf->aq_resp;
 921         args.out_size = I40E_AQ_BUF_SZ;
 922         err = i40evf_execute_vf_cmd(dev, &args);
 923         if (err)
 924                 PMD_DRV_LOG(ERR, "fail to execute command "
 925                             "OP_DEL_ETHER_ADDRESS");
 926         return;
 927 }
 928
 929 static int
 930 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 931 {
 932         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 933         struct i40e_virtchnl_queue_select q_stats;
 934         int err;
 935         struct vf_cmd_info args;
 936
 937         memset(&q_stats, 0, sizeof(q_stats));
 938         q_stats.vsi_id = vf->vsi_res->vsi_id;
 939         args.ops = I40E_VIRTCHNL_OP_GET_STATS;
 940         args.in_args = (u8 *)&q_stats;
 941         args.in_args_size = sizeof(q_stats);
 942         args.out_buffer = vf->aq_resp;
 943         args.out_size = I40E_AQ_BUF_SZ;
 944
 945         err = i40evf_execute_vf_cmd(dev, &args);
 946         if (err) {
 947                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 948                 *pstats = NULL;
 949                 return err;
 950         }
 951         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 952         return 0;
 953 }
 954
 955 static void
 956 i40evf_stat_update_48(uint64_t *offset,
 957                    uint64_t *stat)
 958 {
 959         if (*stat >= *offset)
 960                 *stat = *stat - *offset;
 961         else
 962                 *stat = (uint64_t)((*stat +
 963                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
 964
 965         *stat &= I40E_48_BIT_MASK;
 966 }
 967
 968 static void
 969 i40evf_stat_update_32(uint64_t *offset,
 970                    uint64_t *stat)
 971 {
 972         if (*stat >= *offset)
 973                 *stat = (uint64_t)(*stat - *offset);
 974         else
 975                 *stat = (uint64_t)((*stat +
 976                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
 977 }
 978
 979 static void
 980 i40evf_update_vsi_stats(struct i40e_vsi *vsi,
 981                                         struct i40e_eth_stats *nes)
 982 {
 983         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 984
 985         i40evf_stat_update_48(&oes->rx_bytes,
 986                             &nes->rx_bytes);
 987         i40evf_stat_update_48(&oes->rx_unicast,
 988                             &nes->rx_unicast);
 989         i40evf_stat_update_48(&oes->rx_multicast,
 990                             &nes->rx_multicast);
 991         i40evf_stat_update_48(&oes->rx_broadcast,
 992                             &nes->rx_broadcast);
 993         i40evf_stat_update_32(&oes->rx_discards,
 994                                 &nes->rx_discards);
 995         i40evf_stat_update_32(&oes->rx_unknown_protocol,
 996                             &nes->rx_unknown_protocol);
 997         i40evf_stat_update_48(&oes->tx_bytes,
 998                             &nes->tx_bytes);
 999         i40evf_stat_update_48(&oes->tx_unicast,
1000                             &nes->tx_unicast);
1001         i40evf_stat_update_48(&oes->tx_multicast,
1002                             &nes->tx_multicast);
1003         i40evf_stat_update_48(&oes->tx_broadcast,
1004                             &nes->tx_broadcast);
1005         i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
1006         i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
1007 }
1008
1009 static int
1010 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1011 {
1012         int ret;
1013         struct i40e_eth_stats *pstats = NULL;
1014         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1015         struct i40e_vsi *vsi = &vf->vsi;
1016
1017         ret = i40evf_update_stats(dev, &pstats);
1018         if (ret != 0)
1019                 return 0;
1020
1021         i40evf_update_vsi_stats(vsi, pstats);
1022
1023         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
1024                                                 pstats->rx_broadcast;
1025         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
1026                                                 pstats->tx_unicast;
1027         stats->imissed = pstats->rx_discards;
1028         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
1029         stats->ibytes = pstats->rx_bytes;
1030         stats->obytes = pstats->tx_bytes;
1031
1032         return 0;
1033 }
1034
1035 static void
1036 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
1037 {
1038         int ret;
1039         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1040         struct i40e_eth_stats *pstats = NULL;
1041
1042         /* read stat values to clear hardware registers */
1043         ret = i40evf_update_stats(dev, &pstats);
1044
1045         /* set stats offset base on current values */
1046         if (ret == 0)
1047                 vf->vsi.eth_stats_offset = *pstats;
1048 }
1049
1050 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1051                                       struct rte_eth_xstat_name *xstats_names,
1052                                       __rte_unused unsigned limit)
1053 {
1054         unsigned i;
1055
1056         if (xstats_names != NULL)
1057                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1058                         snprintf(xstats_names[i].name,
1059                                 sizeof(xstats_names[i].name),
1060                                 "%s", rte_i40evf_stats_strings[i].name);
1061                 }
1062         return I40EVF_NB_XSTATS;
1063 }
1064
1065 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1066                                  struct rte_eth_xstat *xstats, unsigned n)
1067 {
1068         int ret;
1069         unsigned i;
1070         struct i40e_eth_stats *pstats = NULL;
1071         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1072         struct i40e_vsi *vsi = &vf->vsi;
1073
1074         if (n < I40EVF_NB_XSTATS)
1075                 return I40EVF_NB_XSTATS;
1076
1077         ret = i40evf_update_stats(dev, &pstats);
1078         if (ret != 0)
1079                 return 0;
1080
1081         if (!xstats)
1082                 return 0;
1083
1084         i40evf_update_vsi_stats(vsi, pstats);
1085
1086         /* loop over xstats array and values from pstats */
1087         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1088                 xstats[i].id = i;
1089                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1090                         rte_i40evf_stats_strings[i].offset);
1091         }
1092
1093         return I40EVF_NB_XSTATS;
1094 }
1095
1096 static int
1097 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1098 {
1099         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1100         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1101         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1102                                                         sizeof(uint16_t)];
1103         int err;
1104         struct vf_cmd_info args;
1105
1106         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1107         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1108         vlan_list->num_elements = 1;
1109         vlan_list->vlan_id[0] = vlanid;
1110
1111         args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1112         args.in_args = (u8 *)&cmd_buffer;
1113         args.in_args_size = sizeof(cmd_buffer);
1114         args.out_buffer = vf->aq_resp;
1115         args.out_size = I40E_AQ_BUF_SZ;
1116         err = i40evf_execute_vf_cmd(dev, &args);
1117         if (err)
1118                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1119
1120         return err;
1121 }
1122
1123 static int
1124 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1125 {
1126         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1127         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1128         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1129                                                         sizeof(uint16_t)];
1130         int err;
1131         struct vf_cmd_info args;
1132
1133         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1134         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1135         vlan_list->num_elements = 1;
1136         vlan_list->vlan_id[0] = vlanid;
1137
1138         args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1139         args.in_args = (u8 *)&cmd_buffer;
1140         args.in_args_size = sizeof(cmd_buffer);
1141         args.out_buffer = vf->aq_resp;
1142         args.out_size = I40E_AQ_BUF_SZ;
1143         err = i40evf_execute_vf_cmd(dev, &args);
1144         if (err)
1145                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1146
1147         return err;
1148 }
1149
1150 static const struct rte_pci_id pci_id_i40evf_map[] = {
1151         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1152         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1153         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1154         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1155         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
1156         { .vendor_id = 0, /* sentinel */ },
1157 };
1158
1159 static inline int
1160 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1161                                     struct rte_eth_link *link)
1162 {
1163         struct rte_eth_link *dst = &(dev->data->dev_link);
1164         struct rte_eth_link *src = link;
1165
1166         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1167                                         *(uint64_t *)src) == 0)
1168                 return -1;
1169
1170         return 0;
1171 }
1172
1173 /* Disable IRQ0 */
1174 static inline void
1175 i40evf_disable_irq0(struct i40e_hw *hw)
1176 {
1177         /* Disable all interrupt types */
1178         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1179         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1180                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1181         I40EVF_WRITE_FLUSH(hw);
1182 }
1183
1184 /* Enable IRQ0 */
1185 static inline void
1186 i40evf_enable_irq0(struct i40e_hw *hw)
1187 {
1188         /* Enable admin queue interrupt trigger */
1189         uint32_t val;
1190
1191         i40evf_disable_irq0(hw);
1192         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1193         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1194                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1195         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1196
1197         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1198                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1199                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1200                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1201
1202         I40EVF_WRITE_FLUSH(hw);
1203 }
1204
1205 static int
1206 i40evf_reset_vf(struct i40e_hw *hw)
1207 {
1208         int i, reset;
1209
1210         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1211                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1212                 return -1;
1213         }
1214         /**
1215           * After issuing vf reset command to pf, pf won't necessarily
1216           * reset vf, it depends on what state it exactly is. If it's not
1217           * initialized yet, it won't have vf reset since it's in a certain
1218           * state. If not, it will try to reset. Even vf is reset, pf will
1219           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1220           * it to ACTIVE. In this duration, vf may not catch the moment that
1221           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1222           */
1223         rte_delay_ms(200);
1224
1225         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1226                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1227                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1228                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1229                 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1230                         break;
1231                 else
1232                         rte_delay_ms(50);
1233         }
1234
1235         if (i >= MAX_RESET_WAIT_CNT) {
1236                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1237                 return -1;
1238         }
1239
1240         return 0;
1241 }
1242
1243 static int
1244 i40evf_init_vf(struct rte_eth_dev *dev)
1245 {
1246         int i, err, bufsz;
1247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1249         struct ether_addr *p_mac_addr;
1250         uint16_t interval =
1251                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX, 0);
1252
1253         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1254         vf->dev_data = dev->data;
1255         err = i40e_set_mac_type(hw);
1256         if (err) {
1257                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1258                 goto err;
1259         }
1260
1261         i40e_init_adminq_parameter(hw);
1262         err = i40e_init_adminq(hw);
1263         if (err) {
1264                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1265                 goto err;
1266         }
1267
1268         /* Reset VF and wait until it's complete */
1269         if (i40evf_reset_vf(hw)) {
1270                 PMD_INIT_LOG(ERR, "reset NIC failed");
1271                 goto err_aq;
1272         }
1273
1274         /* VF reset, shutdown admin queue and initialize again */
1275         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1276                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1277                 goto err;
1278         }
1279
1280         i40e_init_adminq_parameter(hw);
1281         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1282                 PMD_INIT_LOG(ERR, "init_adminq failed");
1283                 goto err;
1284         }
1285         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1286         if (!vf->aq_resp) {
1287                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1288                 goto err_aq;
1289         }
1290         if (i40evf_check_api_version(dev) != 0) {
1291                 PMD_INIT_LOG(ERR, "check_api version failed");
1292                 goto err_api;
1293         }
1294         bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1295                 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1296         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1297         if (!vf->vf_res) {
1298                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1299                 goto err_api;
1300         }
1301
1302         if (i40evf_get_vf_resource(dev) != 0) {
1303                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1304                 goto err_alloc;
1305         }
1306
1307         /* got VF config message back from PF, now we can parse it */
1308         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1309                 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1310                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1311         }
1312
1313         if (!vf->vsi_res) {
1314                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1315                 goto err_alloc;
1316         }
1317
1318         if (hw->mac.type == I40E_MAC_X722_VF)
1319                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1320         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1321         vf->vsi.type = vf->vsi_res->vsi_type;
1322         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1323         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1324
1325         /* Store the MAC address configured by host, or generate random one */
1326         p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1327         if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1328                 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1329         else
1330                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1331
1332         /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1333         if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1334                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1335                                (I40E_ITR_INDEX_DEFAULT <<
1336                                 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1337                                (interval <<
1338                                 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1339                 I40EVF_WRITE_FLUSH(hw);
1340         }
1341
1342         return 0;
1343
1344 err_alloc:
1345         rte_free(vf->vf_res);
1346         vf->vsi_res = NULL;
1347 err_api:
1348         rte_free(vf->aq_resp);
1349 err_aq:
1350         i40e_shutdown_adminq(hw); /* ignore error */
1351 err:
1352         return -1;
1353 }
1354
1355 static int
1356 i40evf_uninit_vf(struct rte_eth_dev *dev)
1357 {
1358         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1360
1361         PMD_INIT_FUNC_TRACE();
1362
1363         if (hw->adapter_stopped == 0)
1364                 i40evf_dev_close(dev);
1365         rte_free(vf->vf_res);
1366         vf->vf_res = NULL;
1367         rte_free(vf->aq_resp);
1368         vf->aq_resp = NULL;
1369
1370         return 0;
1371 }
1372
1373 static void
1374 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1375                            uint8_t *msg,
1376                            __rte_unused uint16_t msglen)
1377 {
1378         struct i40e_virtchnl_pf_event *pf_msg =
1379                         (struct i40e_virtchnl_pf_event *)msg;
1380         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1381
1382         switch (pf_msg->event) {
1383         case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1384                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1385                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1386                 break;
1387         case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1388                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1389                 vf->link_up = pf_msg->event_data.link_event.link_status;
1390                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1391                 break;
1392         case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1393                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1394                 break;
1395         default:
1396                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1397                 break;
1398         }
1399 }
1400
1401 static void
1402 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1403 {
1404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1406         struct i40e_arq_event_info info;
1407         uint16_t pending, aq_opc;
1408         enum i40e_virtchnl_ops msg_opc;
1409         enum i40e_status_code msg_ret;
1410         int ret;
1411
1412         info.buf_len = I40E_AQ_BUF_SZ;
1413         if (!vf->aq_resp) {
1414                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1415                 return;
1416         }
1417         info.msg_buf = vf->aq_resp;
1418
1419         pending = 1;
1420         while (pending) {
1421                 ret = i40e_clean_arq_element(hw, &info, &pending);
1422
1423                 if (ret != I40E_SUCCESS) {
1424                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1425                                     "ret: %d", ret);
1426                         break;
1427                 }
1428                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1429                 /* For the message sent from pf to vf, opcode is stored in
1430                  * cookie_high of struct i40e_aq_desc, while return error code
1431                  * are stored in cookie_low, Which is done by
1432                  * i40e_aq_send_msg_to_vf in PF driver.*/
1433                 msg_opc = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(
1434                                                   info.desc.cookie_high);
1435                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1436                                                   info.desc.cookie_low);
1437                 switch (aq_opc) {
1438                 case i40e_aqc_opc_send_msg_to_vf:
1439                         if (msg_opc == I40E_VIRTCHNL_OP_EVENT)
1440                                 /* process event*/
1441                                 i40evf_handle_pf_event(dev, info.msg_buf,
1442                                                        info.msg_len);
1443                         else {
1444                                 /* read message and it's expected one */
1445                                 if (msg_opc == vf->pend_cmd) {
1446                                         vf->cmd_retval = msg_ret;
1447                                         /* prevent compiler reordering */
1448                                         rte_compiler_barrier();
1449                                         _clear_cmd(vf);
1450                                 } else
1451                                         PMD_DRV_LOG(ERR, "command mismatch,"
1452                                                 "expect %u, get %u",
1453                                                 vf->pend_cmd, msg_opc);
1454                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1455                                              " opcode = %d\n", msg_opc);
1456                         }
1457                         break;
1458                 default:
1459                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1460                                     aq_opc);
1461                         break;
1462                 }
1463         }
1464 }
1465
1466 /**
1467  * Interrupt handler triggered by NIC  for handling
1468  * specific interrupt. Only adminq interrupt is processed in VF.
1469  *
1470  * @param handle
1471  *  Pointer to interrupt handle.
1472  * @param param
1473  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1474  *
1475  * @return
1476  *  void
1477  */
1478 static void
1479 i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1480                              void *param)
1481 {
1482         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484         uint32_t icr0;
1485
1486         i40evf_disable_irq0(hw);
1487
1488         /* read out interrupt causes */
1489         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1490
1491         /* No interrupt event indicated */
1492         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1493                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1494                 goto done;
1495         }
1496
1497         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1498                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1499                 i40evf_handle_aq_msg(dev);
1500         }
1501
1502         /* Link Status Change interrupt */
1503         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1504                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1505                                    " do nothing\n");
1506
1507 done:
1508         i40evf_enable_irq0(hw);
1509 }
1510
1511 static int
1512 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1513 {
1514         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1515                         eth_dev->data->dev_private);
1516         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1517
1518         PMD_INIT_FUNC_TRACE();
1519
1520         /* assign ops func pointer */
1521         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1522         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1523         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1524
1525         /*
1526          * For secondary processes, we don't initialise any further as primary
1527          * has already done this work.
1528          */
1529         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1530                 i40e_set_rx_function(eth_dev);
1531                 i40e_set_tx_function(eth_dev);
1532                 return 0;
1533         }
1534
1535         rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1536
1537         hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1538         hw->device_id = eth_dev->pci_dev->id.device_id;
1539         hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1540         hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1541         hw->bus.device = eth_dev->pci_dev->addr.devid;
1542         hw->bus.func = eth_dev->pci_dev->addr.function;
1543         hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1544         hw->adapter_stopped = 0;
1545
1546         if(i40evf_init_vf(eth_dev) != 0) {
1547                 PMD_INIT_LOG(ERR, "Init vf failed");
1548                 return -1;
1549         }
1550
1551         /* register callback func to eal lib */
1552         rte_intr_callback_register(&pci_dev->intr_handle,
1553                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1554
1555         /* enable uio intr after callback register */
1556         rte_intr_enable(&pci_dev->intr_handle);
1557
1558         /* configure and enable device interrupt */
1559         i40evf_enable_irq0(hw);
1560
1561         /* copy mac addr */
1562         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1563                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1564                                         0);
1565         if (eth_dev->data->mac_addrs == NULL) {
1566                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1567                                 " store MAC addresses",
1568                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1569                 return -ENOMEM;
1570         }
1571         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1572                         &eth_dev->data->mac_addrs[0]);
1573
1574         return 0;
1575 }
1576
1577 static int
1578 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1579 {
1580         PMD_INIT_FUNC_TRACE();
1581
1582         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1583                 return -EPERM;
1584
1585         eth_dev->dev_ops = NULL;
1586         eth_dev->rx_pkt_burst = NULL;
1587         eth_dev->tx_pkt_burst = NULL;
1588
1589         if (i40evf_uninit_vf(eth_dev) != 0) {
1590                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1591                 return -1;
1592         }
1593
1594         rte_free(eth_dev->data->mac_addrs);
1595         eth_dev->data->mac_addrs = NULL;
1596
1597         return 0;
1598 }
1599 /*
1600  * virtual function driver struct
1601  */
1602 static struct eth_driver rte_i40evf_pmd = {
1603         .pci_drv = {
1604                 .id_table = pci_id_i40evf_map,
1605                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1606                 .probe = rte_eth_dev_pci_probe,
1607                 .remove = rte_eth_dev_pci_remove,
1608         },
1609         .eth_dev_init = i40evf_dev_init,
1610         .eth_dev_uninit = i40evf_dev_uninit,
1611         .dev_private_size = sizeof(struct i40e_adapter),
1612 };
1613
1614 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv);
1615 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1616
1617 static int
1618 i40evf_dev_configure(struct rte_eth_dev *dev)
1619 {
1620         struct i40e_adapter *ad =
1621                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1622         struct rte_eth_conf *conf = &dev->data->dev_conf;
1623         struct i40e_vf *vf;
1624
1625         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1626          * allocation or vector Rx preconditions we will reset it.
1627          */
1628         ad->rx_bulk_alloc_allowed = true;
1629         ad->rx_vec_allowed = true;
1630         ad->tx_simple_allowed = true;
1631         ad->tx_vec_allowed = true;
1632
1633         /* For non-DPDK PF drivers, VF has no ability to disable HW
1634          * CRC strip, and is implicitly enabled by the PF.
1635          */
1636         if (!conf->rxmode.hw_strip_crc) {
1637                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1638                 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1639                     (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1640                         /* Peer is running non-DPDK PF driver. */
1641                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1642                         return -EINVAL;
1643                 }
1644         }
1645
1646         return i40evf_init_vlan(dev);
1647 }
1648
1649 static int
1650 i40evf_init_vlan(struct rte_eth_dev *dev)
1651 {
1652         struct rte_eth_dev_data *data = dev->data;
1653         int ret;
1654
1655         /* Apply vlan offload setting */
1656         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1657
1658         /* Apply pvid setting */
1659         ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1660                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
1661         return ret;
1662 }
1663
1664 static void
1665 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1666 {
1667         bool enable_vlan_strip = 0;
1668         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1669         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1670
1671         /* Linux pf host doesn't support vlan offload yet */
1672         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1673                 /* Vlan stripping setting */
1674                 if (mask & ETH_VLAN_STRIP_MASK) {
1675                         /* Enable or disable VLAN stripping */
1676                         if (dev_conf->rxmode.hw_vlan_strip)
1677                                 enable_vlan_strip = 1;
1678                         else
1679                                 enable_vlan_strip = 0;
1680
1681                         i40evf_config_vlan_offload(dev, enable_vlan_strip);
1682                 }
1683         }
1684 }
1685
1686 static int
1687 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1688 {
1689         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1690         struct i40e_vsi_vlan_pvid_info info;
1691         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1692
1693         memset(&info, 0, sizeof(info));
1694         info.on = on;
1695
1696         /* Linux pf host don't support vlan offload yet */
1697         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1698                 if (info.on)
1699                         info.config.pvid = pvid;
1700                 else {
1701                         info.config.reject.tagged =
1702                                 dev_conf->txmode.hw_vlan_reject_tagged;
1703                         info.config.reject.untagged =
1704                                 dev_conf->txmode.hw_vlan_reject_untagged;
1705                 }
1706                 return i40evf_config_vlan_pvid(dev, &info);
1707         }
1708
1709         return 0;
1710 }
1711
1712 static int
1713 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1714 {
1715         struct i40e_rx_queue *rxq;
1716         int err = 0;
1717         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718
1719         PMD_INIT_FUNC_TRACE();
1720
1721         if (rx_queue_id < dev->data->nb_rx_queues) {
1722                 rxq = dev->data->rx_queues[rx_queue_id];
1723
1724                 err = i40e_alloc_rx_queue_mbufs(rxq);
1725                 if (err) {
1726                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1727                         return err;
1728                 }
1729
1730                 rte_wmb();
1731
1732                 /* Init the RX tail register. */
1733                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1734                 I40EVF_WRITE_FLUSH(hw);
1735
1736                 /* Ready to switch the queue on */
1737                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1738
1739                 if (err)
1740                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1741                                     rx_queue_id);
1742                 else
1743                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1744         }
1745
1746         return err;
1747 }
1748
1749 static int
1750 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1751 {
1752         struct i40e_rx_queue *rxq;
1753         int err;
1754
1755         if (rx_queue_id < dev->data->nb_rx_queues) {
1756                 rxq = dev->data->rx_queues[rx_queue_id];
1757
1758                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1759
1760                 if (err) {
1761                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1762                                     rx_queue_id);
1763                         return err;
1764                 }
1765
1766                 i40e_rx_queue_release_mbufs(rxq);
1767                 i40e_reset_rx_queue(rxq);
1768                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1769         }
1770
1771         return 0;
1772 }
1773
1774 static int
1775 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1776 {
1777         int err = 0;
1778
1779         PMD_INIT_FUNC_TRACE();
1780
1781         if (tx_queue_id < dev->data->nb_tx_queues) {
1782
1783                 /* Ready to switch the queue on */
1784                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1785
1786                 if (err)
1787                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1788                                     tx_queue_id);
1789                 else
1790                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1791         }
1792
1793         return err;
1794 }
1795
1796 static int
1797 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1798 {
1799         struct i40e_tx_queue *txq;
1800         int err;
1801
1802         if (tx_queue_id < dev->data->nb_tx_queues) {
1803                 txq = dev->data->tx_queues[tx_queue_id];
1804
1805                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1806
1807                 if (err) {
1808                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1809                                     tx_queue_id);
1810                         return err;
1811                 }
1812
1813                 i40e_tx_queue_release_mbufs(txq);
1814                 i40e_reset_tx_queue(txq);
1815                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1816         }
1817
1818         return 0;
1819 }
1820
1821 static int
1822 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1823 {
1824         int ret;
1825
1826         if (on)
1827                 ret = i40evf_add_vlan(dev, vlan_id);
1828         else
1829                 ret = i40evf_del_vlan(dev,vlan_id);
1830
1831         return ret;
1832 }
1833
1834 static int
1835 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1836 {
1837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838         struct rte_eth_dev_data *dev_data = dev->data;
1839         struct rte_pktmbuf_pool_private *mbp_priv;
1840         uint16_t buf_size, len;
1841
1842         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1843         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1844         I40EVF_WRITE_FLUSH(hw);
1845
1846         /* Calculate the maximum packet length allowed */
1847         mbp_priv = rte_mempool_get_priv(rxq->mp);
1848         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1849                                         RTE_PKTMBUF_HEADROOM);
1850         rxq->hs_mode = i40e_header_split_none;
1851         rxq->rx_hdr_len = 0;
1852         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1853         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1854         rxq->max_pkt_len = RTE_MIN(len,
1855                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1856
1857         /**
1858          * Check if the jumbo frame and maximum packet length are set correctly
1859          */
1860         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1861                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1862                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1863                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1864                                 "larger than %u and smaller than %u, as jumbo "
1865                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1866                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1867                         return I40E_ERR_CONFIG;
1868                 }
1869         } else {
1870                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1871                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1872                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1873                                 "larger than %u and smaller than %u, as jumbo "
1874                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1875                                                 (uint32_t)ETHER_MAX_LEN);
1876                         return I40E_ERR_CONFIG;
1877                 }
1878         }
1879
1880         if (dev_data->dev_conf.rxmode.enable_scatter ||
1881             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1882                 dev_data->scattered_rx = 1;
1883         }
1884
1885         return 0;
1886 }
1887
1888 static int
1889 i40evf_rx_init(struct rte_eth_dev *dev)
1890 {
1891         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1892         uint16_t i;
1893         int ret = I40E_SUCCESS;
1894         struct i40e_rx_queue **rxq =
1895                 (struct i40e_rx_queue **)dev->data->rx_queues;
1896
1897         i40evf_config_rss(vf);
1898         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1899                 if (!rxq[i] || !rxq[i]->q_set)
1900                         continue;
1901                 ret = i40evf_rxq_init(dev, rxq[i]);
1902                 if (ret != I40E_SUCCESS)
1903                         break;
1904         }
1905         if (ret == I40E_SUCCESS)
1906                 i40e_set_rx_function(dev);
1907
1908         return ret;
1909 }
1910
1911 static void
1912 i40evf_tx_init(struct rte_eth_dev *dev)
1913 {
1914         uint16_t i;
1915         struct i40e_tx_queue **txq =
1916                 (struct i40e_tx_queue **)dev->data->tx_queues;
1917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918
1919         for (i = 0; i < dev->data->nb_tx_queues; i++)
1920                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1921
1922         i40e_set_tx_function(dev);
1923 }
1924
1925 static inline void
1926 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1927 {
1928         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1929         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1931
1932         if (!rte_intr_allow_others(intr_handle)) {
1933                 I40E_WRITE_REG(hw,
1934                                I40E_VFINT_DYN_CTL01,
1935                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1936                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1937                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1938                 I40EVF_WRITE_FLUSH(hw);
1939                 return;
1940         }
1941
1942         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1943                 /* To support DPDK PF host */
1944                 I40E_WRITE_REG(hw,
1945                         I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1946                         I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1947                         I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1948         /* If host driver is kernel driver, do nothing.
1949          * Interrupt 0 is used for rx packets, but don't set
1950          * I40E_VFINT_DYN_CTL01,
1951          * because it is already done in i40evf_enable_irq0.
1952          */
1953
1954         I40EVF_WRITE_FLUSH(hw);
1955 }
1956
1957 static inline void
1958 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1959 {
1960         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1963
1964         if (!rte_intr_allow_others(intr_handle)) {
1965                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1966                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1967                 I40EVF_WRITE_FLUSH(hw);
1968                 return;
1969         }
1970
1971         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1972                 I40E_WRITE_REG(hw,
1973                                I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1974                                                     - 1),
1975                                0);
1976         /* If host driver is kernel driver, do nothing.
1977          * Interrupt 0 is used for rx packets, but don't zero
1978          * I40E_VFINT_DYN_CTL01,
1979          * because interrupt 0 is also used for adminq processing.
1980          */
1981
1982         I40EVF_WRITE_FLUSH(hw);
1983 }
1984
1985 static int
1986 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1987 {
1988         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1989         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1990         uint16_t interval =
1991                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 0);
1992         uint16_t msix_intr;
1993
1994         msix_intr = intr_handle->intr_vec[queue_id];
1995         if (msix_intr == I40E_MISC_VEC_ID)
1996                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1997                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1998                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1999                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
2000                                (interval <<
2001                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
2002         else
2003                 I40E_WRITE_REG(hw,
2004                                I40E_VFINT_DYN_CTLN1(msix_intr -
2005                                                     I40E_RX_VEC_START),
2006                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
2007                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
2008                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
2009                                (interval <<
2010                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
2011
2012         I40EVF_WRITE_FLUSH(hw);
2013
2014         rte_intr_enable(&dev->pci_dev->intr_handle);
2015
2016         return 0;
2017 }
2018
2019 static int
2020 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2021 {
2022         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2023         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024         uint16_t msix_intr;
2025
2026         msix_intr = intr_handle->intr_vec[queue_id];
2027         if (msix_intr == I40E_MISC_VEC_ID)
2028                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
2029         else
2030                 I40E_WRITE_REG(hw,
2031                                I40E_VFINT_DYN_CTLN1(msix_intr -
2032                                                     I40E_RX_VEC_START),
2033                                0);
2034
2035         I40EVF_WRITE_FLUSH(hw);
2036
2037         return 0;
2038 }
2039
2040 static void
2041 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
2042 {
2043         struct i40e_virtchnl_ether_addr_list *list;
2044         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2045         int err, i, j;
2046         int next_begin = 0;
2047         int begin = 0;
2048         uint32_t len;
2049         struct ether_addr *addr;
2050         struct vf_cmd_info args;
2051
2052         do {
2053                 j = 0;
2054                 len = sizeof(struct i40e_virtchnl_ether_addr_list);
2055                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2056                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2057                                 continue;
2058                         len += sizeof(struct i40e_virtchnl_ether_addr);
2059                         if (len >= I40E_AQ_BUF_SZ) {
2060                                 next_begin = i + 1;
2061                                 break;
2062                         }
2063                 }
2064
2065                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2066                 if (!list) {
2067                         PMD_DRV_LOG(ERR, "fail to allocate memory");
2068                         return;
2069                 }
2070
2071                 for (i = begin; i < next_begin; i++) {
2072                         addr = &dev->data->mac_addrs[i];
2073                         if (is_zero_ether_addr(addr))
2074                                 continue;
2075                         (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2076                                          sizeof(addr->addr_bytes));
2077                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2078                                     addr->addr_bytes[0], addr->addr_bytes[1],
2079                                     addr->addr_bytes[2], addr->addr_bytes[3],
2080                                     addr->addr_bytes[4], addr->addr_bytes[5]);
2081                         j++;
2082                 }
2083                 list->vsi_id = vf->vsi_res->vsi_id;
2084                 list->num_elements = j;
2085                 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2086                            I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2087                 args.in_args = (uint8_t *)list;
2088                 args.in_args_size = len;
2089                 args.out_buffer = vf->aq_resp;
2090                 args.out_size = I40E_AQ_BUF_SZ;
2091                 err = i40evf_execute_vf_cmd(dev, &args);
2092                 if (err)
2093                         PMD_DRV_LOG(ERR, "fail to execute command %s",
2094                                     add ? "OP_ADD_ETHER_ADDRESS" :
2095                                     "OP_DEL_ETHER_ADDRESS");
2096                 rte_free(list);
2097                 begin = next_begin;
2098         } while (begin < I40E_NUM_MACADDR_MAX);
2099 }
2100
2101 static int
2102 i40evf_dev_start(struct rte_eth_dev *dev)
2103 {
2104         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2107         uint32_t intr_vector = 0;
2108
2109         PMD_INIT_FUNC_TRACE();
2110
2111         hw->adapter_stopped = 0;
2112
2113         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2114         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2115                                         dev->data->nb_tx_queues);
2116
2117         /* check and configure queue intr-vector mapping */
2118         if (rte_intr_cap_multiple(intr_handle) &&
2119             dev->data->dev_conf.intr_conf.rxq) {
2120                 intr_vector = dev->data->nb_rx_queues;
2121                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2122                         return -1;
2123         }
2124
2125         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2126                 intr_handle->intr_vec =
2127                         rte_zmalloc("intr_vec",
2128                                     dev->data->nb_rx_queues * sizeof(int), 0);
2129                 if (!intr_handle->intr_vec) {
2130                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2131                                      " intr_vec\n", dev->data->nb_rx_queues);
2132                         return -ENOMEM;
2133                 }
2134         }
2135
2136         if (i40evf_rx_init(dev) != 0){
2137                 PMD_DRV_LOG(ERR, "failed to do RX init");
2138                 return -1;
2139         }
2140
2141         i40evf_tx_init(dev);
2142
2143         if (i40evf_configure_queues(dev) != 0) {
2144                 PMD_DRV_LOG(ERR, "configure queues failed");
2145                 goto err_queue;
2146         }
2147         if (i40evf_config_irq_map(dev)) {
2148                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2149                 goto err_queue;
2150         }
2151
2152         /* Set all mac addrs */
2153         i40evf_add_del_all_mac_addr(dev, TRUE);
2154
2155         if (i40evf_start_queues(dev) != 0) {
2156                 PMD_DRV_LOG(ERR, "enable queues failed");
2157                 goto err_mac;
2158         }
2159
2160         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
2161          * is mapped to VFIO vector 0 in i40evf_dev_init( ).
2162          * If previous VFIO interrupt mapping set in i40evf_dev_init( ) is
2163          * not cleared, it will fail when rte_intr_enable( ) tries to map Rx
2164          * queue interrupt to other VFIO vectors.
2165          * So clear uio/vfio intr/evevnfd first to avoid failure.
2166          */
2167         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2168                 rte_intr_disable(intr_handle);
2169                 rte_intr_enable(intr_handle);
2170         }
2171
2172         i40evf_enable_queues_intr(dev);
2173
2174         return 0;
2175
2176 err_mac:
2177         i40evf_add_del_all_mac_addr(dev, FALSE);
2178 err_queue:
2179         return -1;
2180 }
2181
2182 static void
2183 i40evf_dev_stop(struct rte_eth_dev *dev)
2184 {
2185         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2186
2187         PMD_INIT_FUNC_TRACE();
2188
2189         i40evf_stop_queues(dev);
2190         i40evf_disable_queues_intr(dev);
2191         i40e_dev_clear_queues(dev);
2192
2193         /* Clean datapath event and queue/vec mapping */
2194         rte_intr_efd_disable(intr_handle);
2195         if (intr_handle->intr_vec) {
2196                 rte_free(intr_handle->intr_vec);
2197                 intr_handle->intr_vec = NULL;
2198         }
2199         /* remove all mac addrs */
2200         i40evf_add_del_all_mac_addr(dev, FALSE);
2201
2202 }
2203
2204 static int
2205 i40evf_dev_link_update(struct rte_eth_dev *dev,
2206                        __rte_unused int wait_to_complete)
2207 {
2208         struct rte_eth_link new_link;
2209         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2210         /*
2211          * DPDK pf host provide interfacet to acquire link status
2212          * while Linux driver does not
2213          */
2214
2215         /* Linux driver PF host */
2216         switch (vf->link_speed) {
2217         case I40E_LINK_SPEED_100MB:
2218                 new_link.link_speed = ETH_SPEED_NUM_100M;
2219                 break;
2220         case I40E_LINK_SPEED_1GB:
2221                 new_link.link_speed = ETH_SPEED_NUM_1G;
2222                 break;
2223         case I40E_LINK_SPEED_10GB:
2224                 new_link.link_speed = ETH_SPEED_NUM_10G;
2225                 break;
2226         case I40E_LINK_SPEED_20GB:
2227                 new_link.link_speed = ETH_SPEED_NUM_20G;
2228                 break;
2229         case I40E_LINK_SPEED_25GB:
2230                 new_link.link_speed = ETH_SPEED_NUM_25G;
2231                 break;
2232         case I40E_LINK_SPEED_40GB:
2233                 new_link.link_speed = ETH_SPEED_NUM_40G;
2234                 break;
2235         default:
2236                 new_link.link_speed = ETH_SPEED_NUM_100M;
2237                 break;
2238         }
2239         /* full duplex only */
2240         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2241         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2242                                              ETH_LINK_DOWN;
2243         new_link.link_autoneg =
2244                 dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED;
2245
2246         i40evf_dev_atomic_write_link_status(dev, &new_link);
2247
2248         return 0;
2249 }
2250
2251 static void
2252 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2253 {
2254         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2255         int ret;
2256
2257         /* If enabled, just return */
2258         if (vf->promisc_unicast_enabled)
2259                 return;
2260
2261         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2262         if (ret == 0)
2263                 vf->promisc_unicast_enabled = TRUE;
2264 }
2265
2266 static void
2267 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2268 {
2269         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2270         int ret;
2271
2272         /* If disabled, just return */
2273         if (!vf->promisc_unicast_enabled)
2274                 return;
2275
2276         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2277         if (ret == 0)
2278                 vf->promisc_unicast_enabled = FALSE;
2279 }
2280
2281 static void
2282 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2283 {
2284         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2285         int ret;
2286
2287         /* If enabled, just return */
2288         if (vf->promisc_multicast_enabled)
2289                 return;
2290
2291         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2292         if (ret == 0)
2293                 vf->promisc_multicast_enabled = TRUE;
2294 }
2295
2296 static void
2297 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2298 {
2299         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2300         int ret;
2301
2302         /* If enabled, just return */
2303         if (!vf->promisc_multicast_enabled)
2304                 return;
2305
2306         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2307         if (ret == 0)
2308                 vf->promisc_multicast_enabled = FALSE;
2309 }
2310
2311 static void
2312 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2313 {
2314         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2315
2316         memset(dev_info, 0, sizeof(*dev_info));
2317         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2318         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2319         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2320         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2321         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2322         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2323         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2324         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2325         dev_info->rx_offload_capa =
2326                 DEV_RX_OFFLOAD_VLAN_STRIP |
2327                 DEV_RX_OFFLOAD_QINQ_STRIP |
2328                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2329                 DEV_RX_OFFLOAD_UDP_CKSUM |
2330                 DEV_RX_OFFLOAD_TCP_CKSUM;
2331         dev_info->tx_offload_capa =
2332                 DEV_TX_OFFLOAD_VLAN_INSERT |
2333                 DEV_TX_OFFLOAD_QINQ_INSERT |
2334                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2335                 DEV_TX_OFFLOAD_UDP_CKSUM |
2336                 DEV_TX_OFFLOAD_TCP_CKSUM |
2337                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2338
2339         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2340                 .rx_thresh = {
2341                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2342                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2343                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2344                 },
2345                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2346                 .rx_drop_en = 0,
2347         };
2348
2349         dev_info->default_txconf = (struct rte_eth_txconf) {
2350                 .tx_thresh = {
2351                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2352                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2353                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2354                 },
2355                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2356                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2357                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2358                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2359         };
2360
2361         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2362                 .nb_max = I40E_MAX_RING_DESC,
2363                 .nb_min = I40E_MIN_RING_DESC,
2364                 .nb_align = I40E_ALIGN_RING_DESC,
2365         };
2366
2367         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2368                 .nb_max = I40E_MAX_RING_DESC,
2369                 .nb_min = I40E_MIN_RING_DESC,
2370                 .nb_align = I40E_ALIGN_RING_DESC,
2371         };
2372 }
2373
2374 static void
2375 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2376 {
2377         if (i40evf_get_statics(dev, stats))
2378                 PMD_DRV_LOG(ERR, "Get statics failed");
2379 }
2380
2381 static void
2382 i40evf_dev_close(struct rte_eth_dev *dev)
2383 {
2384         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2385         struct rte_pci_device *pci_dev = dev->pci_dev;
2386
2387         i40evf_dev_stop(dev);
2388         hw->adapter_stopped = 1;
2389         i40e_dev_free_queues(dev);
2390         i40evf_reset_vf(hw);
2391         i40e_shutdown_adminq(hw);
2392         /* disable uio intr before callback unregister */
2393         rte_intr_disable(&pci_dev->intr_handle);
2394
2395         /* unregister callback func from eal lib */
2396         rte_intr_callback_unregister(&pci_dev->intr_handle,
2397                 i40evf_dev_interrupt_handler, (void *)dev);
2398         i40evf_disable_irq0(hw);
2399 }
2400
2401 static int
2402 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2403 {
2404         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2405         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2406         int ret;
2407
2408         if (!lut)
2409                 return -EINVAL;
2410
2411         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2412                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2413                                           lut, lut_size);
2414                 if (ret) {
2415                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2416                         return ret;
2417                 }
2418         } else {
2419                 uint32_t *lut_dw = (uint32_t *)lut;
2420                 uint16_t i, lut_size_dw = lut_size / 4;
2421
2422                 for (i = 0; i < lut_size_dw; i++)
2423                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2424         }
2425
2426         return 0;
2427 }
2428
2429 static int
2430 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2431 {
2432         struct i40e_vf *vf;
2433         struct i40e_hw *hw;
2434         int ret;
2435
2436         if (!vsi || !lut)
2437                 return -EINVAL;
2438
2439         vf = I40E_VSI_TO_VF(vsi);
2440         hw = I40E_VSI_TO_HW(vsi);
2441
2442         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2443                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2444                                           lut, lut_size);
2445                 if (ret) {
2446                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2447                         return ret;
2448                 }
2449         } else {
2450                 uint32_t *lut_dw = (uint32_t *)lut;
2451                 uint16_t i, lut_size_dw = lut_size / 4;
2452
2453                 for (i = 0; i < lut_size_dw; i++)
2454                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2455                 I40EVF_WRITE_FLUSH(hw);
2456         }
2457
2458         return 0;
2459 }
2460
2461 static int
2462 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2463                            struct rte_eth_rss_reta_entry64 *reta_conf,
2464                            uint16_t reta_size)
2465 {
2466         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2467         uint8_t *lut;
2468         uint16_t i, idx, shift;
2469         int ret;
2470
2471         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2472                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2473                         "(%d) doesn't match the number of hardware can "
2474                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2475                 return -EINVAL;
2476         }
2477
2478         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2479         if (!lut) {
2480                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2481                 return -ENOMEM;
2482         }
2483         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2484         if (ret)
2485                 goto out;
2486         for (i = 0; i < reta_size; i++) {
2487                 idx = i / RTE_RETA_GROUP_SIZE;
2488                 shift = i % RTE_RETA_GROUP_SIZE;
2489                 if (reta_conf[idx].mask & (1ULL << shift))
2490                         lut[i] = reta_conf[idx].reta[shift];
2491         }
2492         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2493
2494 out:
2495         rte_free(lut);
2496
2497         return ret;
2498 }
2499
2500 static int
2501 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2502                           struct rte_eth_rss_reta_entry64 *reta_conf,
2503                           uint16_t reta_size)
2504 {
2505         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2506         uint16_t i, idx, shift;
2507         uint8_t *lut;
2508         int ret;
2509
2510         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2511                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2512                         "(%d) doesn't match the number of hardware can "
2513                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2514                 return -EINVAL;
2515         }
2516
2517         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2518         if (!lut) {
2519                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2520                 return -ENOMEM;
2521         }
2522
2523         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2524         if (ret)
2525                 goto out;
2526         for (i = 0; i < reta_size; i++) {
2527                 idx = i / RTE_RETA_GROUP_SIZE;
2528                 shift = i % RTE_RETA_GROUP_SIZE;
2529                 if (reta_conf[idx].mask & (1ULL << shift))
2530                         reta_conf[idx].reta[shift] = lut[i];
2531         }
2532
2533 out:
2534         rte_free(lut);
2535
2536         return ret;
2537 }
2538
2539 static int
2540 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2541 {
2542         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2543         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2544         int ret = 0;
2545
2546         if (!key || key_len == 0) {
2547                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2548                 return 0;
2549         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2550                 sizeof(uint32_t)) {
2551                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2552                 return -EINVAL;
2553         }
2554
2555         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2556                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2557                         (struct i40e_aqc_get_set_rss_key_data *)key;
2558
2559                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2560                 if (ret)
2561                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2562                                      "via AQ");
2563         } else {
2564                 uint32_t *hash_key = (uint32_t *)key;
2565                 uint16_t i;
2566
2567                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2568                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2569                 I40EVF_WRITE_FLUSH(hw);
2570         }
2571
2572         return ret;
2573 }
2574
2575 static int
2576 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2577 {
2578         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2579         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2580         int ret;
2581
2582         if (!key || !key_len)
2583                 return -EINVAL;
2584
2585         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2586                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2587                         (struct i40e_aqc_get_set_rss_key_data *)key);
2588                 if (ret) {
2589                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2590                         return ret;
2591                 }
2592         } else {
2593                 uint32_t *key_dw = (uint32_t *)key;
2594                 uint16_t i;
2595
2596                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2597                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2598         }
2599         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2600
2601         return 0;
2602 }
2603
2604 static int
2605 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2606 {
2607         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2608         uint64_t rss_hf, hena;
2609         int ret;
2610
2611         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2612                                  rss_conf->rss_key_len);
2613         if (ret)
2614                 return ret;
2615
2616         rss_hf = rss_conf->rss_hf;
2617         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2618         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2619         if (hw->mac.type == I40E_MAC_X722)
2620                 hena &= ~I40E_RSS_HENA_ALL_X722;
2621         else
2622                 hena &= ~I40E_RSS_HENA_ALL;
2623         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2624         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2625         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2626         I40EVF_WRITE_FLUSH(hw);
2627
2628         return 0;
2629 }
2630
2631 static void
2632 i40evf_disable_rss(struct i40e_vf *vf)
2633 {
2634         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2635         uint64_t hena;
2636
2637         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2638         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2639         if (hw->mac.type == I40E_MAC_X722)
2640                 hena &= ~I40E_RSS_HENA_ALL_X722;
2641         else
2642                 hena &= ~I40E_RSS_HENA_ALL;
2643         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2644         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2645         I40EVF_WRITE_FLUSH(hw);
2646 }
2647
2648 static int
2649 i40evf_config_rss(struct i40e_vf *vf)
2650 {
2651         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2652         struct rte_eth_rss_conf rss_conf;
2653         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2654         uint16_t num;
2655
2656         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2657                 i40evf_disable_rss(vf);
2658                 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2659                 return 0;
2660         }
2661
2662         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2663         /* Fill out the look up table */
2664         for (i = 0, j = 0; i < nb_q; i++, j++) {
2665                 if (j >= num)
2666                         j = 0;
2667                 lut = (lut << 8) | j;
2668                 if ((i & 3) == 3)
2669                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2670         }
2671
2672         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2673         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2674                 i40evf_disable_rss(vf);
2675                 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2676                 return 0;
2677         }
2678
2679         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2680                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2681                 /* Calculate the default hash key */
2682                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2683                         rss_key_default[i] = (uint32_t)rte_rand();
2684                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2685                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2686                         sizeof(uint32_t);
2687         }
2688
2689         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2690 }
2691
2692 static int
2693 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2694                            struct rte_eth_rss_conf *rss_conf)
2695 {
2696         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2698         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2699         uint64_t hena;
2700
2701         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2702         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2703         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2704                  ? I40E_RSS_HENA_ALL_X722
2705                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2706                 if (rss_hf != 0) /* Enable RSS */
2707                         return -EINVAL;
2708                 return 0;
2709         }
2710
2711         /* RSS enabled */
2712         if (rss_hf == 0) /* Disable RSS */
2713                 return -EINVAL;
2714
2715         return i40evf_hw_rss_hash_set(vf, rss_conf);
2716 }
2717
2718 static int
2719 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2720                              struct rte_eth_rss_conf *rss_conf)
2721 {
2722         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2723         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724         uint64_t hena;
2725
2726         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2727                            &rss_conf->rss_key_len);
2728
2729         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2730         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2731         rss_conf->rss_hf = i40e_parse_hena(hena);
2732
2733         return 0;
2734 }