drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_bus_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70
  71 /* busy wait delay in msec */
  72 #define I40EVF_BUSY_WAIT_DELAY 10
  73 #define I40EVF_BUSY_WAIT_COUNT 50
  74 #define MAX_RESET_WAIT_CNT     20
  75
  76 struct i40evf_arq_msg_info {
  77         enum virtchnl_ops ops;
  78         enum i40e_status_code result;
  79         uint16_t buf_len;
  80         uint16_t msg_len;
  81         uint8_t *msg;
  82 };
  83
  84 struct vf_cmd_info {
  85         enum virtchnl_ops ops;
  86         uint8_t *in_args;
  87         uint32_t in_args_size;
  88         uint8_t *out_buffer;
  89         /* Input & output type. pass in buffer size and pass out
  90          * actual return result
  91          */
  92         uint32_t out_size;
  93 };
  94
  95 enum i40evf_aq_result {
  96         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  97         I40EVF_MSG_NON,      /* Read nothing from admin queue */
  98         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
  99         I40EVF_MSG_CMD,      /* Read async command result */
 100 };
 101
 102 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 103 static int i40evf_dev_start(struct rte_eth_dev *dev);
 104 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 105 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 108                                   int wait_to_complete);
 109 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
 110                                 struct rte_eth_stats *stats);
 111 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 112                                  struct rte_eth_xstat *xstats, unsigned n);
 113 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 114                                        struct rte_eth_xstat_name *xstats_names,
 115                                        unsigned limit);
 116 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 117 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 118                                   uint16_t vlan_id, int on);
 119 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 120 static void i40evf_dev_close(struct rte_eth_dev *dev);
 121 static int  i40evf_dev_reset(struct rte_eth_dev *dev);
 122 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 123 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 124 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 126 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 127 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 128                                      uint16_t rx_queue_id);
 129 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 130                                     uint16_t rx_queue_id);
 131 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 132                                      uint16_t tx_queue_id);
 133 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 134                                     uint16_t tx_queue_id);
 135 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 136                                struct ether_addr *addr,
 137                                uint32_t index,
 138                                uint32_t pool);
 139 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 140 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 141                         struct rte_eth_rss_reta_entry64 *reta_conf,
 142                         uint16_t reta_size);
 143 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 144                         struct rte_eth_rss_reta_entry64 *reta_conf,
 145                         uint16_t reta_size);
 146 static int i40evf_config_rss(struct i40e_vf *vf);
 147 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 148                                       struct rte_eth_rss_conf *rss_conf);
 149 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 150                                         struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 152 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 153                                         struct ether_addr *mac_addr);
 154 static int
 155 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 156 static int
 157 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 159                                    uint8_t *msg,
 160                                    uint16_t msglen);
 161
 162 /* Default hash key buffer for RSS */
 163 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 164
 165 struct rte_i40evf_xstats_name_off {
 166         char name[RTE_ETH_XSTATS_NAME_SIZE];
 167         unsigned offset;
 168 };
 169
 170 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 171         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 172         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 173         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 174         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 175         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 176         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 177                 rx_unknown_protocol)},
 178         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 179         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 180         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 181         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 182         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 183         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 184 };
 185
 186 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 187                 sizeof(rte_i40evf_stats_strings[0]))
 188
 189 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 190         .dev_configure        = i40evf_dev_configure,
 191         .dev_start            = i40evf_dev_start,
 192         .dev_stop             = i40evf_dev_stop,
 193         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 194         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 195         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 196         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 197         .link_update          = i40evf_dev_link_update,
 198         .stats_get            = i40evf_dev_stats_get,
 199         .stats_reset          = i40evf_dev_xstats_reset,
 200         .xstats_get           = i40evf_dev_xstats_get,
 201         .xstats_get_names     = i40evf_dev_xstats_get_names,
 202         .xstats_reset         = i40evf_dev_xstats_reset,
 203         .dev_close            = i40evf_dev_close,
 204         .dev_reset            = i40evf_dev_reset,
 205         .dev_infos_get        = i40evf_dev_info_get,
 206         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 207         .vlan_filter_set      = i40evf_vlan_filter_set,
 208         .vlan_offload_set     = i40evf_vlan_offload_set,
 209         .rx_queue_start       = i40evf_dev_rx_queue_start,
 210         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 211         .tx_queue_start       = i40evf_dev_tx_queue_start,
 212         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 213         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 214         .rx_queue_release     = i40e_dev_rx_queue_release,
 215         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 216         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 217         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 218         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 219         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 220         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 221         .tx_queue_release     = i40e_dev_tx_queue_release,
 222         .rx_queue_count       = i40e_dev_rx_queue_count,
 223         .rxq_info_get         = i40e_rxq_info_get,
 224         .txq_info_get         = i40e_txq_info_get,
 225         .mac_addr_add         = i40evf_add_mac_addr,
 226         .mac_addr_remove      = i40evf_del_mac_addr,
 227         .reta_update          = i40evf_dev_rss_reta_update,
 228         .reta_query           = i40evf_dev_rss_reta_query,
 229         .rss_hash_update      = i40evf_dev_rss_hash_update,
 230         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 231         .mtu_set              = i40evf_dev_mtu_set,
 232         .mac_addr_set         = i40evf_set_default_mac_addr,
 233 };
 234
 235 /*
 236  * Read data in admin queue to get msg from pf driver
 237  */
 238 static enum i40evf_aq_result
 239 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 240 {
 241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 242         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 243         struct i40e_arq_event_info event;
 244         enum virtchnl_ops opcode;
 245         enum i40e_status_code retval;
 246         int ret;
 247         enum i40evf_aq_result result = I40EVF_MSG_NON;
 248
 249         event.buf_len = data->buf_len;
 250         event.msg_buf = data->msg;
 251         ret = i40e_clean_arq_element(hw, &event, NULL);
 252         /* Can't read any msg from adminQ */
 253         if (ret) {
 254                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 255                         result = I40EVF_MSG_ERR;
 256                 return result;
 257         }
 258
 259         opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 260         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 261         /* pf sys event */
 262         if (opcode == VIRTCHNL_OP_EVENT) {
 263                 struct virtchnl_pf_event *vpe =
 264                         (struct virtchnl_pf_event *)event.msg_buf;
 265
 266                 result = I40EVF_MSG_SYS;
 267                 switch (vpe->event) {
 268                 case VIRTCHNL_EVENT_LINK_CHANGE:
 269                         vf->link_up =
 270                                 vpe->event_data.link_event.link_status;
 271                         vf->link_speed =
 272                                 vpe->event_data.link_event.link_speed;
 273                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 274                         PMD_DRV_LOG(INFO, "Link status update:%s",
 275                                     vf->link_up ? "up" : "down");
 276                         break;
 277                 case VIRTCHNL_EVENT_RESET_IMPENDING:
 278                         vf->vf_reset = true;
 279                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 280                         PMD_DRV_LOG(INFO, "vf is reseting");
 281                         break;
 282                 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 283                         vf->dev_closed = true;
 284                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 285                         PMD_DRV_LOG(INFO, "PF driver closed");
 286                         break;
 287                 default:
 288                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 289                                     __func__, vpe->event);
 290                 }
 291         } else {
 292                 /* async reply msg on command issued by vf previously */
 293                 result = I40EVF_MSG_CMD;
 294                 /* Actual data length read from PF */
 295                 data->msg_len = event.msg_len;
 296         }
 297
 298         data->result = retval;
 299         data->ops = opcode;
 300
 301         return result;
 302 }
 303
 304 /**
 305  * clear current command. Only call in case execute
 306  * _atomic_set_cmd successfully.
 307  */
 308 static inline void
 309 _clear_cmd(struct i40e_vf *vf)
 310 {
 311         rte_wmb();
 312         vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
 313 }
 314
 315 /*
 316  * Check there is pending cmd in execution. If none, set new command.
 317  */
 318 static inline int
 319 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
 320 {
 321         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 322                         VIRTCHNL_OP_UNKNOWN, ops);
 323
 324         if (!ret)
 325                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 326
 327         return !ret;
 328 }
 329
 330 #define MAX_TRY_TIMES 200
 331 #define ASQ_DELAY_MS  10
 332
 333 static int
 334 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 335 {
 336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 337         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 338         struct i40evf_arq_msg_info info;
 339         enum i40evf_aq_result ret;
 340         int err, i = 0;
 341
 342         if (_atomic_set_cmd(vf, args->ops))
 343                 return -1;
 344
 345         info.msg = args->out_buffer;
 346         info.buf_len = args->out_size;
 347         info.ops = VIRTCHNL_OP_UNKNOWN;
 348         info.result = I40E_SUCCESS;
 349
 350         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 351                      args->in_args, args->in_args_size, NULL);
 352         if (err) {
 353                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 354                 _clear_cmd(vf);
 355                 return err;
 356         }
 357
 358         switch (args->ops) {
 359         case VIRTCHNL_OP_RESET_VF:
 360                 /*no need to process in this function */
 361                 err = 0;
 362                 break;
 363         case VIRTCHNL_OP_VERSION:
 364         case VIRTCHNL_OP_GET_VF_RESOURCES:
 365                 /* for init adminq commands, need to poll the response */
 366                 err = -1;
 367                 do {
 368                         ret = i40evf_read_pfmsg(dev, &info);
 369                         vf->cmd_retval = info.result;
 370                         if (ret == I40EVF_MSG_CMD) {
 371                                 err = 0;
 372                                 break;
 373                         } else if (ret == I40EVF_MSG_ERR)
 374                                 break;
 375                         rte_delay_ms(ASQ_DELAY_MS);
 376                         /* If don't read msg or read sys event, continue */
 377                 } while (i++ < MAX_TRY_TIMES);
 378                 _clear_cmd(vf);
 379                 break;
 380
 381         default:
 382                 /* for other adminq in running time, waiting the cmd done flag */
 383                 err = -1;
 384                 do {
 385                         if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
 386                                 err = 0;
 387                                 break;
 388                         }
 389                         rte_delay_ms(ASQ_DELAY_MS);
 390                         /* If don't read msg or read sys event, continue */
 391                 } while (i++ < MAX_TRY_TIMES);
 392                 /* If there's no response is received, clear command */
 393                 if (i >= MAX_TRY_TIMES) {
 394                         PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
 395                         _clear_cmd(vf);
 396                 }
 397                 break;
 398         }
 399
 400         return err | vf->cmd_retval;
 401 }
 402
 403 /*
 404  * Check API version with sync wait until version read or fail from admin queue
 405  */
 406 static int
 407 i40evf_check_api_version(struct rte_eth_dev *dev)
 408 {
 409         struct virtchnl_version_info version, *pver;
 410         int err;
 411         struct vf_cmd_info args;
 412         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 413
 414         version.major = VIRTCHNL_VERSION_MAJOR;
 415         version.minor = VIRTCHNL_VERSION_MINOR;
 416
 417         args.ops = VIRTCHNL_OP_VERSION;
 418         args.in_args = (uint8_t *)&version;
 419         args.in_args_size = sizeof(version);
 420         args.out_buffer = vf->aq_resp;
 421         args.out_size = I40E_AQ_BUF_SZ;
 422
 423         err = i40evf_execute_vf_cmd(dev, &args);
 424         if (err) {
 425                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 426                 return err;
 427         }
 428
 429         pver = (struct virtchnl_version_info *)args.out_buffer;
 430         vf->version_major = pver->major;
 431         vf->version_minor = pver->minor;
 432         if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
 433                 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
 434                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 435         else {
 436                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 437                                         vf->version_major, vf->version_minor,
 438                                                 VIRTCHNL_VERSION_MAJOR,
 439                                                 VIRTCHNL_VERSION_MINOR);
 440                 return -1;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int
 447 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 448 {
 449         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 450         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 451         int err;
 452         struct vf_cmd_info args;
 453         uint32_t caps, len;
 454
 455         args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
 456         args.out_buffer = vf->aq_resp;
 457         args.out_size = I40E_AQ_BUF_SZ;
 458         if (PF_IS_V11(vf)) {
 459                 caps = VIRTCHNL_VF_OFFLOAD_L2 |
 460                        VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 461                        VIRTCHNL_VF_OFFLOAD_RSS_REG |
 462                        VIRTCHNL_VF_OFFLOAD_VLAN |
 463                        VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 464                 args.in_args = (uint8_t *)&caps;
 465                 args.in_args_size = sizeof(caps);
 466         } else {
 467                 args.in_args = NULL;
 468                 args.in_args_size = 0;
 469         }
 470         err = i40evf_execute_vf_cmd(dev, &args);
 471
 472         if (err) {
 473                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 474                 return err;
 475         }
 476
 477         len =  sizeof(struct virtchnl_vf_resource) +
 478                 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
 479
 480         rte_memcpy(vf->vf_res, args.out_buffer,
 481                         RTE_MIN(args.out_size, len));
 482         i40e_vf_parse_hw_config(hw, vf->vf_res);
 483
 484         return 0;
 485 }
 486
 487 static int
 488 i40evf_config_promisc(struct rte_eth_dev *dev,
 489                       bool enable_unicast,
 490                       bool enable_multicast)
 491 {
 492         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 493         int err;
 494         struct vf_cmd_info args;
 495         struct virtchnl_promisc_info promisc;
 496
 497         promisc.flags = 0;
 498         promisc.vsi_id = vf->vsi_res->vsi_id;
 499
 500         if (enable_unicast)
 501                 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
 502
 503         if (enable_multicast)
 504                 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
 505
 506         args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 507         args.in_args = (uint8_t *)&promisc;
 508         args.in_args_size = sizeof(promisc);
 509         args.out_buffer = vf->aq_resp;
 510         args.out_size = I40E_AQ_BUF_SZ;
 511
 512         err = i40evf_execute_vf_cmd(dev, &args);
 513
 514         if (err)
 515                 PMD_DRV_LOG(ERR, "fail to execute command "
 516                             "CONFIG_PROMISCUOUS_MODE");
 517         return err;
 518 }
 519
 520 static int
 521 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
 522 {
 523         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 524         struct vf_cmd_info args;
 525         int ret;
 526
 527         memset(&args, 0, sizeof(args));
 528         args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
 529         args.in_args = NULL;
 530         args.in_args_size = 0;
 531         args.out_buffer = vf->aq_resp;
 532         args.out_size = I40E_AQ_BUF_SZ;
 533         ret = i40evf_execute_vf_cmd(dev, &args);
 534         if (ret)
 535                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 536                             "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
 537
 538         return ret;
 539 }
 540
 541 static int
 542 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
 543 {
 544         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 545         struct vf_cmd_info args;
 546         int ret;
 547
 548         memset(&args, 0, sizeof(args));
 549         args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
 550         args.in_args = NULL;
 551         args.in_args_size = 0;
 552         args.out_buffer = vf->aq_resp;
 553         args.out_size = I40E_AQ_BUF_SZ;
 554         ret = i40evf_execute_vf_cmd(dev, &args);
 555         if (ret)
 556                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 557                             "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
 558
 559         return ret;
 560 }
 561
 562 static void
 563 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
 564                                   uint16_t vsi_id,
 565                                   uint16_t queue_id,
 566                                   uint16_t nb_txq,
 567                                   struct i40e_tx_queue *txq)
 568 {
 569         txq_info->vsi_id = vsi_id;
 570         txq_info->queue_id = queue_id;
 571         if (queue_id < nb_txq) {
 572                 txq_info->ring_len = txq->nb_tx_desc;
 573                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 574         }
 575 }
 576
 577 static void
 578 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
 579                                   uint16_t vsi_id,
 580                                   uint16_t queue_id,
 581                                   uint16_t nb_rxq,
 582                                   uint32_t max_pkt_size,
 583                                   struct i40e_rx_queue *rxq)
 584 {
 585         rxq_info->vsi_id = vsi_id;
 586         rxq_info->queue_id = queue_id;
 587         rxq_info->max_pkt_size = max_pkt_size;
 588         if (queue_id < nb_rxq) {
 589                 rxq_info->ring_len = rxq->nb_rx_desc;
 590                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 591                 rxq_info->databuffer_size =
 592                         (rte_pktmbuf_data_room_size(rxq->mp) -
 593                                 RTE_PKTMBUF_HEADROOM);
 594         }
 595 }
 596
 597 static int
 598 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 599 {
 600         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 601         struct i40e_rx_queue **rxq =
 602                 (struct i40e_rx_queue **)dev->data->rx_queues;
 603         struct i40e_tx_queue **txq =
 604                 (struct i40e_tx_queue **)dev->data->tx_queues;
 605         struct virtchnl_vsi_queue_config_info *vc_vqci;
 606         struct virtchnl_queue_pair_info *vc_qpi;
 607         struct vf_cmd_info args;
 608         uint16_t i, nb_qp = vf->num_queue_pairs;
 609         const uint32_t size =
 610                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 611         uint8_t buff[size];
 612         int ret;
 613
 614         memset(buff, 0, sizeof(buff));
 615         vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
 616         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 617         vc_vqci->num_queue_pairs = nb_qp;
 618
 619         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 620                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 621                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 622                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 623                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 624                                         vf->max_pkt_len, rxq[i]);
 625         }
 626         memset(&args, 0, sizeof(args));
 627         args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 628         args.in_args = (uint8_t *)vc_vqci;
 629         args.in_args_size = size;
 630         args.out_buffer = vf->aq_resp;
 631         args.out_size = I40E_AQ_BUF_SZ;
 632         ret = i40evf_execute_vf_cmd(dev, &args);
 633         if (ret)
 634                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 635                         "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 636
 637         return ret;
 638 }
 639
 640 static int
 641 i40evf_config_irq_map(struct rte_eth_dev *dev)
 642 {
 643         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 644         struct vf_cmd_info args;
 645         uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
 646                 sizeof(struct virtchnl_vector_map)];
 647         struct virtchnl_irq_map_info *map_info;
 648         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 649         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 650         uint32_t vector_id;
 651         int i, err;
 652
 653         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
 654             rte_intr_allow_others(intr_handle))
 655                 vector_id = I40E_RX_VEC_START;
 656         else
 657                 vector_id = I40E_MISC_VEC_ID;
 658
 659         map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
 660         map_info->num_vectors = 1;
 661         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 662         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 663         /* Alway use default dynamic MSIX interrupt */
 664         map_info->vecmap[0].vector_id = vector_id;
 665         /* Don't map any tx queue */
 666         map_info->vecmap[0].txq_map = 0;
 667         map_info->vecmap[0].rxq_map = 0;
 668         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 669                 map_info->vecmap[0].rxq_map |= 1 << i;
 670                 if (rte_intr_dp_is_en(intr_handle))
 671                         intr_handle->intr_vec[i] = vector_id;
 672         }
 673
 674         args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
 675         args.in_args = (u8 *)cmd_buffer;
 676         args.in_args_size = sizeof(cmd_buffer);
 677         args.out_buffer = vf->aq_resp;
 678         args.out_size = I40E_AQ_BUF_SZ;
 679         err = i40evf_execute_vf_cmd(dev, &args);
 680         if (err)
 681                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 682
 683         return err;
 684 }
 685
 686 static int
 687 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 688                                 bool on)
 689 {
 690         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 691         struct virtchnl_queue_select queue_select;
 692         int err;
 693         struct vf_cmd_info args;
 694         memset(&queue_select, 0, sizeof(queue_select));
 695         queue_select.vsi_id = vf->vsi_res->vsi_id;
 696
 697         if (isrx)
 698                 queue_select.rx_queues |= 1 << qid;
 699         else
 700                 queue_select.tx_queues |= 1 << qid;
 701
 702         if (on)
 703                 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
 704         else
 705                 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
 706         args.in_args = (u8 *)&queue_select;
 707         args.in_args_size = sizeof(queue_select);
 708         args.out_buffer = vf->aq_resp;
 709         args.out_size = I40E_AQ_BUF_SZ;
 710         err = i40evf_execute_vf_cmd(dev, &args);
 711         if (err)
 712                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 713                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 714
 715         return err;
 716 }
 717
 718 static int
 719 i40evf_start_queues(struct rte_eth_dev *dev)
 720 {
 721         struct rte_eth_dev_data *dev_data = dev->data;
 722         int i;
 723         struct i40e_rx_queue *rxq;
 724         struct i40e_tx_queue *txq;
 725
 726         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 727                 rxq = dev_data->rx_queues[i];
 728                 if (rxq->rx_deferred_start)
 729                         continue;
 730                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 731                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 732                         return -1;
 733                 }
 734         }
 735
 736         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 737                 txq = dev_data->tx_queues[i];
 738                 if (txq->tx_deferred_start)
 739                         continue;
 740                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 741                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 742                         return -1;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 i40evf_stop_queues(struct rte_eth_dev *dev)
 751 {
 752         int i;
 753
 754         /* Stop TX queues first */
 755         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 756                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 757                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 758                         return -1;
 759                 }
 760         }
 761
 762         /* Then stop RX queues */
 763         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 764                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 765                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 766                         return -1;
 767                 }
 768         }
 769
 770         return 0;
 771 }
 772
 773 static int
 774 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 775                     struct ether_addr *addr,
 776                     __rte_unused uint32_t index,
 777                     __rte_unused uint32_t pool)
 778 {
 779         struct virtchnl_ether_addr_list *list;
 780         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 781         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 782                         sizeof(struct virtchnl_ether_addr)];
 783         int err;
 784         struct vf_cmd_info args;
 785
 786         if (is_zero_ether_addr(addr)) {
 787                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 788                             addr->addr_bytes[0], addr->addr_bytes[1],
 789                             addr->addr_bytes[2], addr->addr_bytes[3],
 790                             addr->addr_bytes[4], addr->addr_bytes[5]);
 791                 return I40E_ERR_INVALID_MAC_ADDR;
 792         }
 793
 794         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 795         list->vsi_id = vf->vsi_res->vsi_id;
 796         list->num_elements = 1;
 797         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 798                                         sizeof(addr->addr_bytes));
 799
 800         args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
 801         args.in_args = cmd_buffer;
 802         args.in_args_size = sizeof(cmd_buffer);
 803         args.out_buffer = vf->aq_resp;
 804         args.out_size = I40E_AQ_BUF_SZ;
 805         err = i40evf_execute_vf_cmd(dev, &args);
 806         if (err)
 807                 PMD_DRV_LOG(ERR, "fail to execute command "
 808                             "OP_ADD_ETHER_ADDRESS");
 809         else
 810                 vf->vsi.mac_num++;
 811
 812         return err;
 813 }
 814
 815 static void
 816 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 817                             struct ether_addr *addr)
 818 {
 819         struct virtchnl_ether_addr_list *list;
 820         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 821         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 822                         sizeof(struct virtchnl_ether_addr)];
 823         int err;
 824         struct vf_cmd_info args;
 825
 826         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 827                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 828                             addr->addr_bytes[0], addr->addr_bytes[1],
 829                             addr->addr_bytes[2], addr->addr_bytes[3],
 830                             addr->addr_bytes[4], addr->addr_bytes[5]);
 831                 return;
 832         }
 833
 834         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 835         list->vsi_id = vf->vsi_res->vsi_id;
 836         list->num_elements = 1;
 837         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 838                         sizeof(addr->addr_bytes));
 839
 840         args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
 841         args.in_args = cmd_buffer;
 842         args.in_args_size = sizeof(cmd_buffer);
 843         args.out_buffer = vf->aq_resp;
 844         args.out_size = I40E_AQ_BUF_SZ;
 845         err = i40evf_execute_vf_cmd(dev, &args);
 846         if (err)
 847                 PMD_DRV_LOG(ERR, "fail to execute command "
 848                             "OP_DEL_ETHER_ADDRESS");
 849         else
 850                 vf->vsi.mac_num--;
 851         return;
 852 }
 853
 854 static void
 855 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 856 {
 857         struct rte_eth_dev_data *data = dev->data;
 858         struct ether_addr *addr;
 859
 860         addr = &data->mac_addrs[index];
 861
 862         i40evf_del_mac_addr_by_addr(dev, addr);
 863 }
 864
 865 static int
 866 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 867 {
 868         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 869         struct virtchnl_queue_select q_stats;
 870         int err;
 871         struct vf_cmd_info args;
 872
 873         memset(&q_stats, 0, sizeof(q_stats));
 874         q_stats.vsi_id = vf->vsi_res->vsi_id;
 875         args.ops = VIRTCHNL_OP_GET_STATS;
 876         args.in_args = (u8 *)&q_stats;
 877         args.in_args_size = sizeof(q_stats);
 878         args.out_buffer = vf->aq_resp;
 879         args.out_size = I40E_AQ_BUF_SZ;
 880
 881         err = i40evf_execute_vf_cmd(dev, &args);
 882         if (err) {
 883                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 884                 *pstats = NULL;
 885                 return err;
 886         }
 887         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 888         return 0;
 889 }
 890
 891 static void
 892 i40evf_stat_update_48(uint64_t *offset,
 893                    uint64_t *stat)
 894 {
 895         if (*stat >= *offset)
 896                 *stat = *stat - *offset;
 897         else
 898                 *stat = (uint64_t)((*stat +
 899                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
 900
 901         *stat &= I40E_48_BIT_MASK;
 902 }
 903
 904 static void
 905 i40evf_stat_update_32(uint64_t *offset,
 906                    uint64_t *stat)
 907 {
 908         if (*stat >= *offset)
 909                 *stat = (uint64_t)(*stat - *offset);
 910         else
 911                 *stat = (uint64_t)((*stat +
 912                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
 913 }
 914
 915 static void
 916 i40evf_update_stats(struct i40e_vsi *vsi,
 917                                         struct i40e_eth_stats *nes)
 918 {
 919         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 920
 921         i40evf_stat_update_48(&oes->rx_bytes,
 922                             &nes->rx_bytes);
 923         i40evf_stat_update_48(&oes->rx_unicast,
 924                             &nes->rx_unicast);
 925         i40evf_stat_update_48(&oes->rx_multicast,
 926                             &nes->rx_multicast);
 927         i40evf_stat_update_48(&oes->rx_broadcast,
 928                             &nes->rx_broadcast);
 929         i40evf_stat_update_32(&oes->rx_discards,
 930                                 &nes->rx_discards);
 931         i40evf_stat_update_32(&oes->rx_unknown_protocol,
 932                             &nes->rx_unknown_protocol);
 933         i40evf_stat_update_48(&oes->tx_bytes,
 934                             &nes->tx_bytes);
 935         i40evf_stat_update_48(&oes->tx_unicast,
 936                             &nes->tx_unicast);
 937         i40evf_stat_update_48(&oes->tx_multicast,
 938                             &nes->tx_multicast);
 939         i40evf_stat_update_48(&oes->tx_broadcast,
 940                             &nes->tx_broadcast);
 941         i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
 942         i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
 943 }
 944
 945 static void
 946 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 947 {
 948         int ret;
 949         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 950         struct i40e_eth_stats *pstats = NULL;
 951
 952         /* read stat values to clear hardware registers */
 953         ret = i40evf_query_stats(dev, &pstats);
 954
 955         /* set stats offset base on current values */
 956         if (ret == 0)
 957                 vf->vsi.eth_stats_offset = *pstats;
 958 }
 959
 960 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 961                                       struct rte_eth_xstat_name *xstats_names,
 962                                       __rte_unused unsigned limit)
 963 {
 964         unsigned i;
 965
 966         if (xstats_names != NULL)
 967                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 968                         snprintf(xstats_names[i].name,
 969                                 sizeof(xstats_names[i].name),
 970                                 "%s", rte_i40evf_stats_strings[i].name);
 971                 }
 972         return I40EVF_NB_XSTATS;
 973 }
 974
 975 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 976                                  struct rte_eth_xstat *xstats, unsigned n)
 977 {
 978         int ret;
 979         unsigned i;
 980         struct i40e_eth_stats *pstats = NULL;
 981         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 982         struct i40e_vsi *vsi = &vf->vsi;
 983
 984         if (n < I40EVF_NB_XSTATS)
 985                 return I40EVF_NB_XSTATS;
 986
 987         ret = i40evf_query_stats(dev, &pstats);
 988         if (ret != 0)
 989                 return 0;
 990
 991         if (!xstats)
 992                 return 0;
 993
 994         i40evf_update_stats(vsi, pstats);
 995
 996         /* loop over xstats array and values from pstats */
 997         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 998                 xstats[i].id = i;
 999                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1000                         rte_i40evf_stats_strings[i].offset);
1001         }
1002
1003         return I40EVF_NB_XSTATS;
1004 }
1005
1006 static int
1007 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1008 {
1009         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1010         struct virtchnl_vlan_filter_list *vlan_list;
1011         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1012                                                         sizeof(uint16_t)];
1013         int err;
1014         struct vf_cmd_info args;
1015
1016         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1017         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1018         vlan_list->num_elements = 1;
1019         vlan_list->vlan_id[0] = vlanid;
1020
1021         args.ops = VIRTCHNL_OP_ADD_VLAN;
1022         args.in_args = (u8 *)&cmd_buffer;
1023         args.in_args_size = sizeof(cmd_buffer);
1024         args.out_buffer = vf->aq_resp;
1025         args.out_size = I40E_AQ_BUF_SZ;
1026         err = i40evf_execute_vf_cmd(dev, &args);
1027         if (err)
1028                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1029
1030         return err;
1031 }
1032
1033 static int
1034 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1035 {
1036         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1037         struct virtchnl_vlan_filter_list *vlan_list;
1038         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1039                                                         sizeof(uint16_t)];
1040         int err;
1041         struct vf_cmd_info args;
1042
1043         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1044         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1045         vlan_list->num_elements = 1;
1046         vlan_list->vlan_id[0] = vlanid;
1047
1048         args.ops = VIRTCHNL_OP_DEL_VLAN;
1049         args.in_args = (u8 *)&cmd_buffer;
1050         args.in_args_size = sizeof(cmd_buffer);
1051         args.out_buffer = vf->aq_resp;
1052         args.out_size = I40E_AQ_BUF_SZ;
1053         err = i40evf_execute_vf_cmd(dev, &args);
1054         if (err)
1055                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1056
1057         return err;
1058 }
1059
1060 static const struct rte_pci_id pci_id_i40evf_map[] = {
1061         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1062         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1063         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1064         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1065         { .vendor_id = 0, /* sentinel */ },
1066 };
1067
1068 static inline int
1069 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1070                                     struct rte_eth_link *link)
1071 {
1072         struct rte_eth_link *dst = &(dev->data->dev_link);
1073         struct rte_eth_link *src = link;
1074
1075         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1076                                         *(uint64_t *)src) == 0)
1077                 return -1;
1078
1079         return 0;
1080 }
1081
1082 /* Disable IRQ0 */
1083 static inline void
1084 i40evf_disable_irq0(struct i40e_hw *hw)
1085 {
1086         /* Disable all interrupt types */
1087         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1088         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1089                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1090         I40EVF_WRITE_FLUSH(hw);
1091 }
1092
1093 /* Enable IRQ0 */
1094 static inline void
1095 i40evf_enable_irq0(struct i40e_hw *hw)
1096 {
1097         /* Enable admin queue interrupt trigger */
1098         uint32_t val;
1099
1100         i40evf_disable_irq0(hw);
1101         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1102         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1103                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1104         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1105
1106         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1107                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1108                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1109                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1110
1111         I40EVF_WRITE_FLUSH(hw);
1112 }
1113
1114 static int
1115 i40evf_check_vf_reset_done(struct i40e_hw *hw)
1116 {
1117         int i, reset;
1118
1119         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1120                 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1121                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1122                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1123                 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1124                     reset == VIRTCHNL_VFR_COMPLETED)
1125                         break;
1126                 rte_delay_ms(50);
1127         }
1128
1129         if (i >= MAX_RESET_WAIT_CNT)
1130                 return -1;
1131
1132         return 0;
1133 }
1134 static int
1135 i40evf_reset_vf(struct i40e_hw *hw)
1136 {
1137         int ret;
1138
1139         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1140                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1141                 return -1;
1142         }
1143         /**
1144           * After issuing vf reset command to pf, pf won't necessarily
1145           * reset vf, it depends on what state it exactly is. If it's not
1146           * initialized yet, it won't have vf reset since it's in a certain
1147           * state. If not, it will try to reset. Even vf is reset, pf will
1148           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1149           * it to ACTIVE. In this duration, vf may not catch the moment that
1150           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1151           */
1152         rte_delay_ms(200);
1153
1154         ret = i40evf_check_vf_reset_done(hw);
1155         if (ret) {
1156                 PMD_INIT_LOG(ERR, "VF is still resetting");
1157                 return ret;
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int
1164 i40evf_init_vf(struct rte_eth_dev *dev)
1165 {
1166         int i, err, bufsz;
1167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1169         uint16_t interval =
1170                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX, 0);
1171
1172         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1173         vf->dev_data = dev->data;
1174         err = i40e_set_mac_type(hw);
1175         if (err) {
1176                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1177                 goto err;
1178         }
1179
1180         err = i40evf_check_vf_reset_done(hw);
1181         if (err)
1182                 goto err;
1183
1184         i40e_init_adminq_parameter(hw);
1185         err = i40e_init_adminq(hw);
1186         if (err) {
1187                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1188                 goto err;
1189         }
1190
1191         /* Reset VF and wait until it's complete */
1192         if (i40evf_reset_vf(hw)) {
1193                 PMD_INIT_LOG(ERR, "reset NIC failed");
1194                 goto err_aq;
1195         }
1196
1197         /* VF reset, shutdown admin queue and initialize again */
1198         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1199                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1200                 goto err;
1201         }
1202
1203         i40e_init_adminq_parameter(hw);
1204         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1205                 PMD_INIT_LOG(ERR, "init_adminq failed");
1206                 goto err;
1207         }
1208
1209         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1210         if (!vf->aq_resp) {
1211                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1212                 goto err_aq;
1213         }
1214         if (i40evf_check_api_version(dev) != 0) {
1215                 PMD_INIT_LOG(ERR, "check_api version failed");
1216                 goto err_api;
1217         }
1218         bufsz = sizeof(struct virtchnl_vf_resource) +
1219                 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1220         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1221         if (!vf->vf_res) {
1222                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1223                 goto err_api;
1224         }
1225
1226         if (i40evf_get_vf_resource(dev) != 0) {
1227                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1228                 goto err_alloc;
1229         }
1230
1231         /* got VF config message back from PF, now we can parse it */
1232         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1233                 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1234                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1235         }
1236
1237         if (!vf->vsi_res) {
1238                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1239                 goto err_alloc;
1240         }
1241
1242         if (hw->mac.type == I40E_MAC_X722_VF)
1243                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1244         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1245
1246         switch (vf->vsi_res->vsi_type) {
1247         case VIRTCHNL_VSI_SRIOV:
1248                 vf->vsi.type = I40E_VSI_SRIOV;
1249                 break;
1250         default:
1251                 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1252                 break;
1253         }
1254         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1255         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1256
1257         /* Store the MAC address configured by host, or generate random one */
1258         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1259                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1260         else
1261                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1262
1263         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1264                        (I40E_ITR_INDEX_DEFAULT <<
1265                         I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1266                        (interval <<
1267                         I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1268         I40EVF_WRITE_FLUSH(hw);
1269
1270         return 0;
1271
1272 err_alloc:
1273         rte_free(vf->vf_res);
1274         vf->vsi_res = NULL;
1275 err_api:
1276         rte_free(vf->aq_resp);
1277 err_aq:
1278         i40e_shutdown_adminq(hw); /* ignore error */
1279 err:
1280         return -1;
1281 }
1282
1283 static int
1284 i40evf_uninit_vf(struct rte_eth_dev *dev)
1285 {
1286         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1288
1289         PMD_INIT_FUNC_TRACE();
1290
1291         if (hw->adapter_stopped == 0)
1292                 i40evf_dev_close(dev);
1293         rte_free(vf->vf_res);
1294         vf->vf_res = NULL;
1295         rte_free(vf->aq_resp);
1296         vf->aq_resp = NULL;
1297
1298         return 0;
1299 }
1300
1301 static void
1302 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1303                 __rte_unused uint16_t msglen)
1304 {
1305         struct virtchnl_pf_event *pf_msg =
1306                         (struct virtchnl_pf_event *)msg;
1307         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1308
1309         switch (pf_msg->event) {
1310         case VIRTCHNL_EVENT_RESET_IMPENDING:
1311                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1312                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1313                                               NULL, NULL);
1314                 break;
1315         case VIRTCHNL_EVENT_LINK_CHANGE:
1316                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1317                 vf->link_up = pf_msg->event_data.link_event.link_status;
1318                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1319                 break;
1320         case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1321                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1322                 break;
1323         default:
1324                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1325                 break;
1326         }
1327 }
1328
1329 static void
1330 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1331 {
1332         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1333         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1334         struct i40e_arq_event_info info;
1335         uint16_t pending, aq_opc;
1336         enum virtchnl_ops msg_opc;
1337         enum i40e_status_code msg_ret;
1338         int ret;
1339
1340         info.buf_len = I40E_AQ_BUF_SZ;
1341         if (!vf->aq_resp) {
1342                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1343                 return;
1344         }
1345         info.msg_buf = vf->aq_resp;
1346
1347         pending = 1;
1348         while (pending) {
1349                 ret = i40e_clean_arq_element(hw, &info, &pending);
1350
1351                 if (ret != I40E_SUCCESS) {
1352                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1353                                     "ret: %d", ret);
1354                         break;
1355                 }
1356                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1357                 /* For the message sent from pf to vf, opcode is stored in
1358                  * cookie_high of struct i40e_aq_desc, while return error code
1359                  * are stored in cookie_low, Which is done by
1360                  * i40e_aq_send_msg_to_vf in PF driver.*/
1361                 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1362                                                   info.desc.cookie_high);
1363                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1364                                                   info.desc.cookie_low);
1365                 switch (aq_opc) {
1366                 case i40e_aqc_opc_send_msg_to_vf:
1367                         if (msg_opc == VIRTCHNL_OP_EVENT)
1368                                 /* process event*/
1369                                 i40evf_handle_pf_event(dev, info.msg_buf,
1370                                                        info.msg_len);
1371                         else {
1372                                 /* read message and it's expected one */
1373                                 if (msg_opc == vf->pend_cmd) {
1374                                         vf->cmd_retval = msg_ret;
1375                                         /* prevent compiler reordering */
1376                                         rte_compiler_barrier();
1377                                         _clear_cmd(vf);
1378                                 } else
1379                                         PMD_DRV_LOG(ERR, "command mismatch,"
1380                                                 "expect %u, get %u",
1381                                                 vf->pend_cmd, msg_opc);
1382                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1383                                              " opcode = %d", msg_opc);
1384                         }
1385                         break;
1386                 default:
1387                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1388                                     aq_opc);
1389                         break;
1390                 }
1391         }
1392 }
1393
1394 /**
1395  * Interrupt handler triggered by NIC  for handling
1396  * specific interrupt. Only adminq interrupt is processed in VF.
1397  *
1398  * @param handle
1399  *  Pointer to interrupt handle.
1400  * @param param
1401  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1402  *
1403  * @return
1404  *  void
1405  */
1406 static void
1407 i40evf_dev_interrupt_handler(void *param)
1408 {
1409         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411         uint32_t icr0;
1412
1413         i40evf_disable_irq0(hw);
1414
1415         /* read out interrupt causes */
1416         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1417
1418         /* No interrupt event indicated */
1419         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1420                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1421                 goto done;
1422         }
1423
1424         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1425                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1426                 i40evf_handle_aq_msg(dev);
1427         }
1428
1429         /* Link Status Change interrupt */
1430         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1431                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1432                                    " do nothing");
1433
1434 done:
1435         i40evf_enable_irq0(hw);
1436 }
1437
1438 static int
1439 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1440 {
1441         struct i40e_hw *hw
1442                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1443         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1444
1445         PMD_INIT_FUNC_TRACE();
1446
1447         /* assign ops func pointer */
1448         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1449         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1450         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1451
1452         /*
1453          * For secondary processes, we don't initialise any further as primary
1454          * has already done this work.
1455          */
1456         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1457                 i40e_set_rx_function(eth_dev);
1458                 i40e_set_tx_function(eth_dev);
1459                 return 0;
1460         }
1461         i40e_set_default_ptype_table(eth_dev);
1462         i40e_set_default_pctype_table(eth_dev);
1463         rte_eth_copy_pci_info(eth_dev, pci_dev);
1464
1465         hw->vendor_id = pci_dev->id.vendor_id;
1466         hw->device_id = pci_dev->id.device_id;
1467         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1468         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1469         hw->bus.device = pci_dev->addr.devid;
1470         hw->bus.func = pci_dev->addr.function;
1471         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1472         hw->adapter_stopped = 0;
1473
1474         if(i40evf_init_vf(eth_dev) != 0) {
1475                 PMD_INIT_LOG(ERR, "Init vf failed");
1476                 return -1;
1477         }
1478
1479         /* register callback func to eal lib */
1480         rte_intr_callback_register(&pci_dev->intr_handle,
1481                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1482
1483         /* enable uio intr after callback register */
1484         rte_intr_enable(&pci_dev->intr_handle);
1485
1486         /* configure and enable device interrupt */
1487         i40evf_enable_irq0(hw);
1488
1489         /* copy mac addr */
1490         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1491                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1492                                         0);
1493         if (eth_dev->data->mac_addrs == NULL) {
1494                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1495                                 " store MAC addresses",
1496                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1497                 return -ENOMEM;
1498         }
1499         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1500                         &eth_dev->data->mac_addrs[0]);
1501
1502         return 0;
1503 }
1504
1505 static int
1506 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1507 {
1508         PMD_INIT_FUNC_TRACE();
1509
1510         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1511                 return -EPERM;
1512
1513         eth_dev->dev_ops = NULL;
1514         eth_dev->rx_pkt_burst = NULL;
1515         eth_dev->tx_pkt_burst = NULL;
1516
1517         if (i40evf_uninit_vf(eth_dev) != 0) {
1518                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1519                 return -1;
1520         }
1521
1522         rte_free(eth_dev->data->mac_addrs);
1523         eth_dev->data->mac_addrs = NULL;
1524
1525         return 0;
1526 }
1527
1528 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1529         struct rte_pci_device *pci_dev)
1530 {
1531         return rte_eth_dev_pci_generic_probe(pci_dev,
1532                 sizeof(struct i40e_adapter), i40evf_dev_init);
1533 }
1534
1535 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1536 {
1537         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1538 }
1539
1540 /*
1541  * virtual function driver struct
1542  */
1543 static struct rte_pci_driver rte_i40evf_pmd = {
1544         .id_table = pci_id_i40evf_map,
1545         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1546         .probe = eth_i40evf_pci_probe,
1547         .remove = eth_i40evf_pci_remove,
1548 };
1549
1550 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1551 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1552 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1553
1554 static int
1555 i40evf_dev_configure(struct rte_eth_dev *dev)
1556 {
1557         struct i40e_adapter *ad =
1558                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1559         struct rte_eth_conf *conf = &dev->data->dev_conf;
1560         struct i40e_vf *vf;
1561
1562         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1563          * allocation or vector Rx preconditions we will reset it.
1564          */
1565         ad->rx_bulk_alloc_allowed = true;
1566         ad->rx_vec_allowed = true;
1567         ad->tx_simple_allowed = true;
1568         ad->tx_vec_allowed = true;
1569
1570         /* For non-DPDK PF drivers, VF has no ability to disable HW
1571          * CRC strip, and is implicitly enabled by the PF.
1572          */
1573         if (!conf->rxmode.hw_strip_crc) {
1574                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1575                 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1576                     (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1577                         /* Peer is running non-DPDK PF driver. */
1578                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1579                         return -EINVAL;
1580                 }
1581         }
1582
1583         return i40evf_init_vlan(dev);
1584 }
1585
1586 static int
1587 i40evf_init_vlan(struct rte_eth_dev *dev)
1588 {
1589         /* Apply vlan offload setting */
1590         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1591
1592         return 0;
1593 }
1594
1595 static int
1596 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1597 {
1598         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1599         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1600
1601         if (!(vf->vf_res->vf_offload_flags & VIRTCHNL_VF_OFFLOAD_VLAN))
1602                 return -ENOTSUP;
1603
1604         /* Vlan stripping setting */
1605         if (mask & ETH_VLAN_STRIP_MASK) {
1606                 /* Enable or disable VLAN stripping */
1607                 if (dev_conf->rxmode.hw_vlan_strip)
1608                         i40evf_enable_vlan_strip(dev);
1609                 else
1610                         i40evf_disable_vlan_strip(dev);
1611         }
1612
1613         return 0;
1614 }
1615
1616 static int
1617 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1618 {
1619         struct i40e_rx_queue *rxq;
1620         int err = 0;
1621         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1622
1623         PMD_INIT_FUNC_TRACE();
1624
1625         if (rx_queue_id < dev->data->nb_rx_queues) {
1626                 rxq = dev->data->rx_queues[rx_queue_id];
1627
1628                 err = i40e_alloc_rx_queue_mbufs(rxq);
1629                 if (err) {
1630                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1631                         return err;
1632                 }
1633
1634                 rte_wmb();
1635
1636                 /* Init the RX tail register. */
1637                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1638                 I40EVF_WRITE_FLUSH(hw);
1639
1640                 /* Ready to switch the queue on */
1641                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1642
1643                 if (err)
1644                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1645                                     rx_queue_id);
1646                 else
1647                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1648         }
1649
1650         return err;
1651 }
1652
1653 static int
1654 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1655 {
1656         struct i40e_rx_queue *rxq;
1657         int err;
1658
1659         if (rx_queue_id < dev->data->nb_rx_queues) {
1660                 rxq = dev->data->rx_queues[rx_queue_id];
1661
1662                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1663
1664                 if (err) {
1665                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1666                                     rx_queue_id);
1667                         return err;
1668                 }
1669
1670                 i40e_rx_queue_release_mbufs(rxq);
1671                 i40e_reset_rx_queue(rxq);
1672                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1673         }
1674
1675         return 0;
1676 }
1677
1678 static int
1679 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1680 {
1681         int err = 0;
1682
1683         PMD_INIT_FUNC_TRACE();
1684
1685         if (tx_queue_id < dev->data->nb_tx_queues) {
1686
1687                 /* Ready to switch the queue on */
1688                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1689
1690                 if (err)
1691                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1692                                     tx_queue_id);
1693                 else
1694                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1695         }
1696
1697         return err;
1698 }
1699
1700 static int
1701 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1702 {
1703         struct i40e_tx_queue *txq;
1704         int err;
1705
1706         if (tx_queue_id < dev->data->nb_tx_queues) {
1707                 txq = dev->data->tx_queues[tx_queue_id];
1708
1709                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1710
1711                 if (err) {
1712                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1713                                     tx_queue_id);
1714                         return err;
1715                 }
1716
1717                 i40e_tx_queue_release_mbufs(txq);
1718                 i40e_reset_tx_queue(txq);
1719                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1720         }
1721
1722         return 0;
1723 }
1724
1725 static int
1726 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1727 {
1728         int ret;
1729
1730         if (on)
1731                 ret = i40evf_add_vlan(dev, vlan_id);
1732         else
1733                 ret = i40evf_del_vlan(dev,vlan_id);
1734
1735         return ret;
1736 }
1737
1738 static int
1739 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1740 {
1741         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742         struct rte_eth_dev_data *dev_data = dev->data;
1743         struct rte_pktmbuf_pool_private *mbp_priv;
1744         uint16_t buf_size, len;
1745
1746         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1747         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1748         I40EVF_WRITE_FLUSH(hw);
1749
1750         /* Calculate the maximum packet length allowed */
1751         mbp_priv = rte_mempool_get_priv(rxq->mp);
1752         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1753                                         RTE_PKTMBUF_HEADROOM);
1754         rxq->hs_mode = i40e_header_split_none;
1755         rxq->rx_hdr_len = 0;
1756         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1757         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1758         rxq->max_pkt_len = RTE_MIN(len,
1759                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1760
1761         /**
1762          * Check if the jumbo frame and maximum packet length are set correctly
1763          */
1764         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1765                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1766                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1767                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1768                                 "larger than %u and smaller than %u, as jumbo "
1769                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1770                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1771                         return I40E_ERR_CONFIG;
1772                 }
1773         } else {
1774                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1775                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1776                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1777                                 "larger than %u and smaller than %u, as jumbo "
1778                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1779                                                 (uint32_t)ETHER_MAX_LEN);
1780                         return I40E_ERR_CONFIG;
1781                 }
1782         }
1783
1784         if (dev_data->dev_conf.rxmode.enable_scatter ||
1785             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1786                 dev_data->scattered_rx = 1;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int
1793 i40evf_rx_init(struct rte_eth_dev *dev)
1794 {
1795         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1796         uint16_t i;
1797         int ret = I40E_SUCCESS;
1798         struct i40e_rx_queue **rxq =
1799                 (struct i40e_rx_queue **)dev->data->rx_queues;
1800
1801         i40evf_config_rss(vf);
1802         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1803                 if (!rxq[i] || !rxq[i]->q_set)
1804                         continue;
1805                 ret = i40evf_rxq_init(dev, rxq[i]);
1806                 if (ret != I40E_SUCCESS)
1807                         break;
1808         }
1809         if (ret == I40E_SUCCESS)
1810                 i40e_set_rx_function(dev);
1811
1812         return ret;
1813 }
1814
1815 static void
1816 i40evf_tx_init(struct rte_eth_dev *dev)
1817 {
1818         uint16_t i;
1819         struct i40e_tx_queue **txq =
1820                 (struct i40e_tx_queue **)dev->data->tx_queues;
1821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822
1823         for (i = 0; i < dev->data->nb_tx_queues; i++)
1824                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1825
1826         i40e_set_tx_function(dev);
1827 }
1828
1829 static inline void
1830 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1831 {
1832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1834         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1835
1836         if (!rte_intr_allow_others(intr_handle)) {
1837                 I40E_WRITE_REG(hw,
1838                                I40E_VFINT_DYN_CTL01,
1839                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1840                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1841                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1842                 I40EVF_WRITE_FLUSH(hw);
1843                 return;
1844         }
1845
1846         I40EVF_WRITE_FLUSH(hw);
1847 }
1848
1849 static inline void
1850 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1851 {
1852         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1854         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1855
1856         if (!rte_intr_allow_others(intr_handle)) {
1857                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1858                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1859                 I40EVF_WRITE_FLUSH(hw);
1860                 return;
1861         }
1862
1863         I40EVF_WRITE_FLUSH(hw);
1864 }
1865
1866 static int
1867 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1868 {
1869         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1870         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         uint16_t interval =
1873                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 0);
1874         uint16_t msix_intr;
1875
1876         msix_intr = intr_handle->intr_vec[queue_id];
1877         if (msix_intr == I40E_MISC_VEC_ID)
1878                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1879                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1880                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1881                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1882                                (interval <<
1883                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1884         else
1885                 I40E_WRITE_REG(hw,
1886                                I40E_VFINT_DYN_CTLN1(msix_intr -
1887                                                     I40E_RX_VEC_START),
1888                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1889                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1890                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1891                                (interval <<
1892                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1893
1894         I40EVF_WRITE_FLUSH(hw);
1895
1896         rte_intr_enable(&pci_dev->intr_handle);
1897
1898         return 0;
1899 }
1900
1901 static int
1902 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1903 {
1904         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1905         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1906         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907         uint16_t msix_intr;
1908
1909         msix_intr = intr_handle->intr_vec[queue_id];
1910         if (msix_intr == I40E_MISC_VEC_ID)
1911                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1912         else
1913                 I40E_WRITE_REG(hw,
1914                                I40E_VFINT_DYN_CTLN1(msix_intr -
1915                                                     I40E_RX_VEC_START),
1916                                0);
1917
1918         I40EVF_WRITE_FLUSH(hw);
1919
1920         return 0;
1921 }
1922
1923 static void
1924 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1925 {
1926         struct virtchnl_ether_addr_list *list;
1927         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1928         int err, i, j;
1929         int next_begin = 0;
1930         int begin = 0;
1931         uint32_t len;
1932         struct ether_addr *addr;
1933         struct vf_cmd_info args;
1934
1935         do {
1936                 j = 0;
1937                 len = sizeof(struct virtchnl_ether_addr_list);
1938                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1939                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1940                                 continue;
1941                         len += sizeof(struct virtchnl_ether_addr);
1942                         if (len >= I40E_AQ_BUF_SZ) {
1943                                 next_begin = i + 1;
1944                                 break;
1945                         }
1946                 }
1947
1948                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1949                 if (!list) {
1950                         PMD_DRV_LOG(ERR, "fail to allocate memory");
1951                         return;
1952                 }
1953
1954                 for (i = begin; i < next_begin; i++) {
1955                         addr = &dev->data->mac_addrs[i];
1956                         if (is_zero_ether_addr(addr))
1957                                 continue;
1958                         rte_memcpy(list->list[j].addr, addr->addr_bytes,
1959                                          sizeof(addr->addr_bytes));
1960                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1961                                     addr->addr_bytes[0], addr->addr_bytes[1],
1962                                     addr->addr_bytes[2], addr->addr_bytes[3],
1963                                     addr->addr_bytes[4], addr->addr_bytes[5]);
1964                         j++;
1965                 }
1966                 list->vsi_id = vf->vsi_res->vsi_id;
1967                 list->num_elements = j;
1968                 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1969                            VIRTCHNL_OP_DEL_ETH_ADDR;
1970                 args.in_args = (uint8_t *)list;
1971                 args.in_args_size = len;
1972                 args.out_buffer = vf->aq_resp;
1973                 args.out_size = I40E_AQ_BUF_SZ;
1974                 err = i40evf_execute_vf_cmd(dev, &args);
1975                 if (err) {
1976                         PMD_DRV_LOG(ERR, "fail to execute command %s",
1977                                     add ? "OP_ADD_ETHER_ADDRESS" :
1978                                     "OP_DEL_ETHER_ADDRESS");
1979                 } else {
1980                         if (add)
1981                                 vf->vsi.mac_num++;
1982                         else
1983                                 vf->vsi.mac_num--;
1984                 }
1985                 rte_free(list);
1986                 begin = next_begin;
1987         } while (begin < I40E_NUM_MACADDR_MAX);
1988 }
1989
1990 static int
1991 i40evf_dev_start(struct rte_eth_dev *dev)
1992 {
1993         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1994         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1996         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1997         uint32_t intr_vector = 0;
1998
1999         PMD_INIT_FUNC_TRACE();
2000
2001         hw->adapter_stopped = 0;
2002
2003         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2004         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2005                                         dev->data->nb_tx_queues);
2006
2007         /* check and configure queue intr-vector mapping */
2008         if (rte_intr_cap_multiple(intr_handle) &&
2009             dev->data->dev_conf.intr_conf.rxq) {
2010                 intr_vector = dev->data->nb_rx_queues;
2011                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2012                         return -1;
2013         }
2014
2015         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2016                 intr_handle->intr_vec =
2017                         rte_zmalloc("intr_vec",
2018                                     dev->data->nb_rx_queues * sizeof(int), 0);
2019                 if (!intr_handle->intr_vec) {
2020                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2021                                      " intr_vec", dev->data->nb_rx_queues);
2022                         return -ENOMEM;
2023                 }
2024         }
2025
2026         if (i40evf_rx_init(dev) != 0){
2027                 PMD_DRV_LOG(ERR, "failed to do RX init");
2028                 return -1;
2029         }
2030
2031         i40evf_tx_init(dev);
2032
2033         if (i40evf_configure_vsi_queues(dev) != 0) {
2034                 PMD_DRV_LOG(ERR, "configure queues failed");
2035                 goto err_queue;
2036         }
2037         if (i40evf_config_irq_map(dev)) {
2038                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2039                 goto err_queue;
2040         }
2041
2042         /* Set all mac addrs */
2043         i40evf_add_del_all_mac_addr(dev, TRUE);
2044
2045         if (i40evf_start_queues(dev) != 0) {
2046                 PMD_DRV_LOG(ERR, "enable queues failed");
2047                 goto err_mac;
2048         }
2049
2050         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
2051          * is mapped to VFIO vector 0 in i40evf_dev_init( ).
2052          * If previous VFIO interrupt mapping set in i40evf_dev_init( ) is
2053          * not cleared, it will fail when rte_intr_enable( ) tries to map Rx
2054          * queue interrupt to other VFIO vectors.
2055          * So clear uio/vfio intr/evevnfd first to avoid failure.
2056          */
2057         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2058                 rte_intr_disable(intr_handle);
2059                 rte_intr_enable(intr_handle);
2060         }
2061
2062         i40evf_enable_queues_intr(dev);
2063
2064         return 0;
2065
2066 err_mac:
2067         i40evf_add_del_all_mac_addr(dev, FALSE);
2068 err_queue:
2069         return -1;
2070 }
2071
2072 static void
2073 i40evf_dev_stop(struct rte_eth_dev *dev)
2074 {
2075         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2076         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078
2079         PMD_INIT_FUNC_TRACE();
2080
2081         if (hw->adapter_stopped == 1)
2082                 return;
2083         i40evf_stop_queues(dev);
2084         i40evf_disable_queues_intr(dev);
2085         i40e_dev_clear_queues(dev);
2086
2087         /* Clean datapath event and queue/vec mapping */
2088         rte_intr_efd_disable(intr_handle);
2089         if (intr_handle->intr_vec) {
2090                 rte_free(intr_handle->intr_vec);
2091                 intr_handle->intr_vec = NULL;
2092         }
2093         /* remove all mac addrs */
2094         i40evf_add_del_all_mac_addr(dev, FALSE);
2095         hw->adapter_stopped = 1;
2096
2097 }
2098
2099 static int
2100 i40evf_dev_link_update(struct rte_eth_dev *dev,
2101                        __rte_unused int wait_to_complete)
2102 {
2103         struct rte_eth_link new_link;
2104         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2105         /*
2106          * DPDK pf host provide interfacet to acquire link status
2107          * while Linux driver does not
2108          */
2109
2110         /* Linux driver PF host */
2111         switch (vf->link_speed) {
2112         case I40E_LINK_SPEED_100MB:
2113                 new_link.link_speed = ETH_SPEED_NUM_100M;
2114                 break;
2115         case I40E_LINK_SPEED_1GB:
2116                 new_link.link_speed = ETH_SPEED_NUM_1G;
2117                 break;
2118         case I40E_LINK_SPEED_10GB:
2119                 new_link.link_speed = ETH_SPEED_NUM_10G;
2120                 break;
2121         case I40E_LINK_SPEED_20GB:
2122                 new_link.link_speed = ETH_SPEED_NUM_20G;
2123                 break;
2124         case I40E_LINK_SPEED_25GB:
2125                 new_link.link_speed = ETH_SPEED_NUM_25G;
2126                 break;
2127         case I40E_LINK_SPEED_40GB:
2128                 new_link.link_speed = ETH_SPEED_NUM_40G;
2129                 break;
2130         default:
2131                 new_link.link_speed = ETH_SPEED_NUM_100M;
2132                 break;
2133         }
2134         /* full duplex only */
2135         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2136         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2137                                              ETH_LINK_DOWN;
2138         new_link.link_autoneg =
2139                 dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED;
2140
2141         i40evf_dev_atomic_write_link_status(dev, &new_link);
2142
2143         return 0;
2144 }
2145
2146 static void
2147 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2148 {
2149         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2150         int ret;
2151
2152         /* If enabled, just return */
2153         if (vf->promisc_unicast_enabled)
2154                 return;
2155
2156         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2157         if (ret == 0)
2158                 vf->promisc_unicast_enabled = TRUE;
2159 }
2160
2161 static void
2162 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2163 {
2164         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2165         int ret;
2166
2167         /* If disabled, just return */
2168         if (!vf->promisc_unicast_enabled)
2169                 return;
2170
2171         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2172         if (ret == 0)
2173                 vf->promisc_unicast_enabled = FALSE;
2174 }
2175
2176 static void
2177 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2178 {
2179         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2180         int ret;
2181
2182         /* If enabled, just return */
2183         if (vf->promisc_multicast_enabled)
2184                 return;
2185
2186         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2187         if (ret == 0)
2188                 vf->promisc_multicast_enabled = TRUE;
2189 }
2190
2191 static void
2192 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2193 {
2194         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2195         int ret;
2196
2197         /* If enabled, just return */
2198         if (!vf->promisc_multicast_enabled)
2199                 return;
2200
2201         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2202         if (ret == 0)
2203                 vf->promisc_multicast_enabled = FALSE;
2204 }
2205
2206 static void
2207 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2208 {
2209         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2210
2211         memset(dev_info, 0, sizeof(*dev_info));
2212         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2213         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2214         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2215         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2216         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2217         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2218         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2219         dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2220         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2221         dev_info->rx_offload_capa =
2222                 DEV_RX_OFFLOAD_VLAN_STRIP |
2223                 DEV_RX_OFFLOAD_QINQ_STRIP |
2224                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2225                 DEV_RX_OFFLOAD_UDP_CKSUM |
2226                 DEV_RX_OFFLOAD_TCP_CKSUM;
2227         dev_info->tx_offload_capa =
2228                 DEV_TX_OFFLOAD_VLAN_INSERT |
2229                 DEV_TX_OFFLOAD_QINQ_INSERT |
2230                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2231                 DEV_TX_OFFLOAD_UDP_CKSUM |
2232                 DEV_TX_OFFLOAD_TCP_CKSUM |
2233                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2234
2235         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2236                 .rx_thresh = {
2237                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2238                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2239                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2240                 },
2241                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2242                 .rx_drop_en = 0,
2243         };
2244
2245         dev_info->default_txconf = (struct rte_eth_txconf) {
2246                 .tx_thresh = {
2247                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2248                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2249                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2250                 },
2251                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2252                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2253                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2254                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2255         };
2256
2257         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2258                 .nb_max = I40E_MAX_RING_DESC,
2259                 .nb_min = I40E_MIN_RING_DESC,
2260                 .nb_align = I40E_ALIGN_RING_DESC,
2261         };
2262
2263         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2264                 .nb_max = I40E_MAX_RING_DESC,
2265                 .nb_min = I40E_MIN_RING_DESC,
2266                 .nb_align = I40E_ALIGN_RING_DESC,
2267         };
2268 }
2269
2270 static int
2271 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2272 {
2273         int ret;
2274         struct i40e_eth_stats *pstats = NULL;
2275         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2276         struct i40e_vsi *vsi = &vf->vsi;
2277
2278         ret = i40evf_query_stats(dev, &pstats);
2279         if (ret == 0) {
2280                 i40evf_update_stats(vsi, pstats);
2281
2282                 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2283                                                 pstats->rx_broadcast;
2284                 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2285                                                 pstats->tx_unicast;
2286                 stats->imissed = pstats->rx_discards;
2287                 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2288                 stats->ibytes = pstats->rx_bytes;
2289                 stats->obytes = pstats->tx_bytes;
2290         } else {
2291                 PMD_DRV_LOG(ERR, "Get statistics failed");
2292         }
2293         return ret;
2294 }
2295
2296 static void
2297 i40evf_dev_close(struct rte_eth_dev *dev)
2298 {
2299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2300         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2301         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2302
2303         i40evf_dev_stop(dev);
2304         i40e_dev_free_queues(dev);
2305         i40evf_reset_vf(hw);
2306         i40e_shutdown_adminq(hw);
2307         /* disable uio intr before callback unregister */
2308         rte_intr_disable(intr_handle);
2309
2310         /* unregister callback func from eal lib */
2311         rte_intr_callback_unregister(intr_handle,
2312                                      i40evf_dev_interrupt_handler, dev);
2313         i40evf_disable_irq0(hw);
2314 }
2315
2316 /*
2317  * Reset VF device only to re-initialize resources in PMD layer
2318  */
2319 static int
2320 i40evf_dev_reset(struct rte_eth_dev *dev)
2321 {
2322         int ret;
2323
2324         ret = i40evf_dev_uninit(dev);
2325         if (ret)
2326                 return ret;
2327
2328         ret = i40evf_dev_init(dev);
2329
2330         return ret;
2331 }
2332
2333 static int
2334 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2335 {
2336         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2337         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2338         int ret;
2339
2340         if (!lut)
2341                 return -EINVAL;
2342
2343         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2344                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2345                                           lut, lut_size);
2346                 if (ret) {
2347                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2348                         return ret;
2349                 }
2350         } else {
2351                 uint32_t *lut_dw = (uint32_t *)lut;
2352                 uint16_t i, lut_size_dw = lut_size / 4;
2353
2354                 for (i = 0; i < lut_size_dw; i++)
2355                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2356         }
2357
2358         return 0;
2359 }
2360
2361 static int
2362 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2363 {
2364         struct i40e_vf *vf;
2365         struct i40e_hw *hw;
2366         int ret;
2367
2368         if (!vsi || !lut)
2369                 return -EINVAL;
2370
2371         vf = I40E_VSI_TO_VF(vsi);
2372         hw = I40E_VSI_TO_HW(vsi);
2373
2374         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2375                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2376                                           lut, lut_size);
2377                 if (ret) {
2378                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2379                         return ret;
2380                 }
2381         } else {
2382                 uint32_t *lut_dw = (uint32_t *)lut;
2383                 uint16_t i, lut_size_dw = lut_size / 4;
2384
2385                 for (i = 0; i < lut_size_dw; i++)
2386                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2387                 I40EVF_WRITE_FLUSH(hw);
2388         }
2389
2390         return 0;
2391 }
2392
2393 static int
2394 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2395                            struct rte_eth_rss_reta_entry64 *reta_conf,
2396                            uint16_t reta_size)
2397 {
2398         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2399         uint8_t *lut;
2400         uint16_t i, idx, shift;
2401         int ret;
2402
2403         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2404                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2405                         "(%d) doesn't match the number of hardware can "
2406                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2407                 return -EINVAL;
2408         }
2409
2410         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2411         if (!lut) {
2412                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2413                 return -ENOMEM;
2414         }
2415         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2416         if (ret)
2417                 goto out;
2418         for (i = 0; i < reta_size; i++) {
2419                 idx = i / RTE_RETA_GROUP_SIZE;
2420                 shift = i % RTE_RETA_GROUP_SIZE;
2421                 if (reta_conf[idx].mask & (1ULL << shift))
2422                         lut[i] = reta_conf[idx].reta[shift];
2423         }
2424         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2425
2426 out:
2427         rte_free(lut);
2428
2429         return ret;
2430 }
2431
2432 static int
2433 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2434                           struct rte_eth_rss_reta_entry64 *reta_conf,
2435                           uint16_t reta_size)
2436 {
2437         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2438         uint16_t i, idx, shift;
2439         uint8_t *lut;
2440         int ret;
2441
2442         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2443                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2444                         "(%d) doesn't match the number of hardware can "
2445                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2446                 return -EINVAL;
2447         }
2448
2449         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2450         if (!lut) {
2451                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2452                 return -ENOMEM;
2453         }
2454
2455         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2456         if (ret)
2457                 goto out;
2458         for (i = 0; i < reta_size; i++) {
2459                 idx = i / RTE_RETA_GROUP_SIZE;
2460                 shift = i % RTE_RETA_GROUP_SIZE;
2461                 if (reta_conf[idx].mask & (1ULL << shift))
2462                         reta_conf[idx].reta[shift] = lut[i];
2463         }
2464
2465 out:
2466         rte_free(lut);
2467
2468         return ret;
2469 }
2470
2471 static int
2472 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2473 {
2474         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2475         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2476         int ret = 0;
2477
2478         if (!key || key_len == 0) {
2479                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2480                 return 0;
2481         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2482                 sizeof(uint32_t)) {
2483                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2484                 return -EINVAL;
2485         }
2486
2487         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2488                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2489                         (struct i40e_aqc_get_set_rss_key_data *)key;
2490
2491                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2492                 if (ret)
2493                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2494                                      "via AQ");
2495         } else {
2496                 uint32_t *hash_key = (uint32_t *)key;
2497                 uint16_t i;
2498
2499                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2500                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2501                 I40EVF_WRITE_FLUSH(hw);
2502         }
2503
2504         return ret;
2505 }
2506
2507 static int
2508 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2509 {
2510         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2511         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2512         int ret;
2513
2514         if (!key || !key_len)
2515                 return -EINVAL;
2516
2517         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2518                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2519                         (struct i40e_aqc_get_set_rss_key_data *)key);
2520                 if (ret) {
2521                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2522                         return ret;
2523                 }
2524         } else {
2525                 uint32_t *key_dw = (uint32_t *)key;
2526                 uint16_t i;
2527
2528                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2529                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2530         }
2531         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2532
2533         return 0;
2534 }
2535
2536 static int
2537 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2538 {
2539         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2540         uint64_t hena;
2541         int ret;
2542
2543         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2544                                  rss_conf->rss_key_len);
2545         if (ret)
2546                 return ret;
2547
2548         hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2549         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2550         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2551         I40EVF_WRITE_FLUSH(hw);
2552
2553         return 0;
2554 }
2555
2556 static void
2557 i40evf_disable_rss(struct i40e_vf *vf)
2558 {
2559         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2560
2561         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2562         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2563         I40EVF_WRITE_FLUSH(hw);
2564 }
2565
2566 static int
2567 i40evf_config_rss(struct i40e_vf *vf)
2568 {
2569         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2570         struct rte_eth_rss_conf rss_conf;
2571         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2572         uint16_t num;
2573
2574         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2575                 i40evf_disable_rss(vf);
2576                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2577                 return 0;
2578         }
2579
2580         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2581         /* Fill out the look up table */
2582         for (i = 0, j = 0; i < nb_q; i++, j++) {
2583                 if (j >= num)
2584                         j = 0;
2585                 lut = (lut << 8) | j;
2586                 if ((i & 3) == 3)
2587                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2588         }
2589
2590         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2591         if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2592                 i40evf_disable_rss(vf);
2593                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2594                 return 0;
2595         }
2596
2597         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2598                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2599                 /* Calculate the default hash key */
2600                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2601                         rss_key_default[i] = (uint32_t)rte_rand();
2602                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2603                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2604                         sizeof(uint32_t);
2605         }
2606
2607         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2608 }
2609
2610 static int
2611 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2612                            struct rte_eth_rss_conf *rss_conf)
2613 {
2614         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2617         uint64_t hena;
2618
2619         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2620         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2621
2622         if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2623                 if (rss_hf != 0) /* Enable RSS */
2624                         return -EINVAL;
2625                 return 0;
2626         }
2627
2628         /* RSS enabled */
2629         if (rss_hf == 0) /* Disable RSS */
2630                 return -EINVAL;
2631
2632         return i40evf_hw_rss_hash_set(vf, rss_conf);
2633 }
2634
2635 static int
2636 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2637                              struct rte_eth_rss_conf *rss_conf)
2638 {
2639         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641         uint64_t hena;
2642
2643         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2644                            &rss_conf->rss_key_len);
2645
2646         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2647         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2648         rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2649
2650         return 0;
2651 }
2652
2653 static int
2654 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2655 {
2656         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2657         struct rte_eth_dev_data *dev_data = vf->dev_data;
2658         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2659         int ret = 0;
2660
2661         /* check if mtu is within the allowed range */
2662         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2663                 return -EINVAL;
2664
2665         /* mtu setting is forbidden if port is start */
2666         if (dev_data->dev_started) {
2667                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2668                             dev_data->port_id);
2669                 return -EBUSY;
2670         }
2671
2672         if (frame_size > ETHER_MAX_LEN)
2673                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2674         else
2675                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2676
2677         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2678
2679         return ret;
2680 }
2681
2682 static void
2683 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2684                             struct ether_addr *mac_addr)
2685 {
2686         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688
2689         if (!is_valid_assigned_ether_addr(mac_addr)) {
2690                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2691                 return;
2692         }
2693
2694         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2695                 return;
2696
2697         i40evf_del_mac_addr_by_addr(dev, (struct ether_addr *)hw->mac.addr);
2698
2699         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2700
2701         ether_addr_copy(mac_addr, (struct ether_addr *)hw->mac.addr);
2702 }