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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
55 #include <rte_alarm.h>
56 #include <rte_ether.h>
57 #include <rte_ethdev.h>
58 #include <rte_atomic.h>
59 #include <rte_malloc.h>
62 #include "i40e_logs.h"
63 #include "base/i40e_prototype.h"
64 #include "base/i40e_adminq_cmd.h"
65 #include "base/i40e_type.h"
67 #include "i40e_rxtx.h"
68 #include "i40e_ethdev.h"
70 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
73 /* busy wait delay in msec */
74 #define I40EVF_BUSY_WAIT_DELAY 10
75 #define I40EVF_BUSY_WAIT_COUNT 50
76 #define MAX_RESET_WAIT_CNT 20
78 struct i40evf_arq_msg_info {
79 enum i40e_virtchnl_ops ops;
80 enum i40e_status_code result;
87 enum i40e_virtchnl_ops ops;
89 uint32_t in_args_size;
91 /* Input & output type. pass in buffer size and pass out
92 * actual return result
97 enum i40evf_aq_result {
98 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
99 I40EVF_MSG_NON, /* Read nothing from admin queue */
100 I40EVF_MSG_SYS, /* Read system msg from admin queue */
101 I40EVF_MSG_CMD, /* Read async command result */
104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
105 static int i40evf_dev_start(struct rte_eth_dev *dev);
106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
108 struct rte_eth_dev_info *dev_info);
109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
110 __rte_unused int wait_to_complete);
111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
112 struct rte_eth_stats *stats);
113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstat *xstats, unsigned n);
115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
116 struct rte_eth_xstat_name *xstats_names,
118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
120 uint16_t vlan_id, int on);
121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
124 static void i40evf_dev_close(struct rte_eth_dev *dev);
125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
129 static int i40evf_init_vlan(struct rte_eth_dev *dev);
130 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
131 uint16_t rx_queue_id);
132 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
133 uint16_t rx_queue_id);
134 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
135 uint16_t tx_queue_id);
136 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
137 uint16_t tx_queue_id);
138 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
139 struct ether_addr *addr,
142 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
143 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
144 struct rte_eth_rss_reta_entry64 *reta_conf,
146 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
147 struct rte_eth_rss_reta_entry64 *reta_conf,
149 static int i40evf_config_rss(struct i40e_vf *vf);
150 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
151 struct rte_eth_rss_conf *rss_conf);
152 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
153 struct rte_eth_rss_conf *rss_conf);
155 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
157 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
158 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
162 /* Default hash key buffer for RSS */
163 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
165 struct rte_i40evf_xstats_name_off {
166 char name[RTE_ETH_XSTATS_NAME_SIZE];
170 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
171 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
172 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
173 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
174 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
175 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
176 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
177 rx_unknown_protocol)},
178 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
179 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
180 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
181 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
182 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
183 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
186 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
187 sizeof(rte_i40evf_stats_strings[0]))
189 static const struct eth_dev_ops i40evf_eth_dev_ops = {
190 .dev_configure = i40evf_dev_configure,
191 .dev_start = i40evf_dev_start,
192 .dev_stop = i40evf_dev_stop,
193 .promiscuous_enable = i40evf_dev_promiscuous_enable,
194 .promiscuous_disable = i40evf_dev_promiscuous_disable,
195 .allmulticast_enable = i40evf_dev_allmulticast_enable,
196 .allmulticast_disable = i40evf_dev_allmulticast_disable,
197 .link_update = i40evf_dev_link_update,
198 .stats_get = i40evf_dev_stats_get,
199 .xstats_get = i40evf_dev_xstats_get,
200 .xstats_get_names = i40evf_dev_xstats_get_names,
201 .xstats_reset = i40evf_dev_xstats_reset,
202 .dev_close = i40evf_dev_close,
203 .dev_infos_get = i40evf_dev_info_get,
204 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
205 .vlan_filter_set = i40evf_vlan_filter_set,
206 .vlan_offload_set = i40evf_vlan_offload_set,
207 .vlan_pvid_set = i40evf_vlan_pvid_set,
208 .rx_queue_start = i40evf_dev_rx_queue_start,
209 .rx_queue_stop = i40evf_dev_rx_queue_stop,
210 .tx_queue_start = i40evf_dev_tx_queue_start,
211 .tx_queue_stop = i40evf_dev_tx_queue_stop,
212 .rx_queue_setup = i40e_dev_rx_queue_setup,
213 .rx_queue_release = i40e_dev_rx_queue_release,
214 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
215 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
216 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
217 .tx_queue_setup = i40e_dev_tx_queue_setup,
218 .tx_queue_release = i40e_dev_tx_queue_release,
219 .rx_queue_count = i40e_dev_rx_queue_count,
220 .rxq_info_get = i40e_rxq_info_get,
221 .txq_info_get = i40e_txq_info_get,
222 .mac_addr_add = i40evf_add_mac_addr,
223 .mac_addr_remove = i40evf_del_mac_addr,
224 .reta_update = i40evf_dev_rss_reta_update,
225 .reta_query = i40evf_dev_rss_reta_query,
226 .rss_hash_update = i40evf_dev_rss_hash_update,
227 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
231 * Read data in admin queue to get msg from pf driver
233 static enum i40evf_aq_result
234 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
236 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
237 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
238 struct i40e_arq_event_info event;
239 enum i40e_virtchnl_ops opcode;
240 enum i40e_status_code retval;
242 enum i40evf_aq_result result = I40EVF_MSG_NON;
244 event.buf_len = data->buf_len;
245 event.msg_buf = data->msg;
246 ret = i40e_clean_arq_element(hw, &event, NULL);
247 /* Can't read any msg from adminQ */
249 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
250 result = I40EVF_MSG_ERR;
254 opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
255 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
257 if (opcode == I40E_VIRTCHNL_OP_EVENT) {
258 struct i40e_virtchnl_pf_event *vpe =
259 (struct i40e_virtchnl_pf_event *)event.msg_buf;
261 result = I40EVF_MSG_SYS;
262 switch (vpe->event) {
263 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
265 vpe->event_data.link_event.link_status;
267 vpe->event_data.link_event.link_speed;
268 vf->pend_msg |= PFMSG_LINK_CHANGE;
269 PMD_DRV_LOG(INFO, "Link status update:%s",
270 vf->link_up ? "up" : "down");
272 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
274 vf->pend_msg |= PFMSG_RESET_IMPENDING;
275 PMD_DRV_LOG(INFO, "vf is reseting");
277 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
278 vf->dev_closed = true;
279 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
280 PMD_DRV_LOG(INFO, "PF driver closed");
283 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
284 __func__, vpe->event);
287 /* async reply msg on command issued by vf previously */
288 result = I40EVF_MSG_CMD;
289 /* Actual data length read from PF */
290 data->msg_len = event.msg_len;
293 data->result = retval;
300 * clear current command. Only call in case execute
301 * _atomic_set_cmd successfully.
304 _clear_cmd(struct i40e_vf *vf)
307 vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
311 * Check there is pending cmd in execution. If none, set new command.
314 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
316 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
317 I40E_VIRTCHNL_OP_UNKNOWN, ops);
320 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
325 #define MAX_TRY_TIMES 200
326 #define ASQ_DELAY_MS 10
329 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
331 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
332 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
333 struct i40evf_arq_msg_info info;
334 enum i40evf_aq_result ret;
337 if (_atomic_set_cmd(vf, args->ops))
340 info.msg = args->out_buffer;
341 info.buf_len = args->out_size;
342 info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
343 info.result = I40E_SUCCESS;
345 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
346 args->in_args, args->in_args_size, NULL);
348 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
354 case I40E_VIRTCHNL_OP_RESET_VF:
355 /*no need to process in this function */
358 case I40E_VIRTCHNL_OP_VERSION:
359 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
360 /* for init adminq commands, need to poll the response */
363 ret = i40evf_read_pfmsg(dev, &info);
364 if (ret == I40EVF_MSG_CMD) {
367 } else if (ret == I40EVF_MSG_ERR)
369 rte_delay_ms(ASQ_DELAY_MS);
370 /* If don't read msg or read sys event, continue */
371 } while (i++ < MAX_TRY_TIMES);
376 /* for other adminq in running time, waiting the cmd done flag */
379 if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
383 rte_delay_ms(ASQ_DELAY_MS);
384 /* If don't read msg or read sys event, continue */
385 } while (i++ < MAX_TRY_TIMES);
389 return err | vf->cmd_retval;
393 * Check API version with sync wait until version read or fail from admin queue
396 i40evf_check_api_version(struct rte_eth_dev *dev)
398 struct i40e_virtchnl_version_info version, *pver;
400 struct vf_cmd_info args;
401 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
403 version.major = I40E_VIRTCHNL_VERSION_MAJOR;
404 version.minor = I40E_VIRTCHNL_VERSION_MINOR;
406 args.ops = I40E_VIRTCHNL_OP_VERSION;
407 args.in_args = (uint8_t *)&version;
408 args.in_args_size = sizeof(version);
409 args.out_buffer = vf->aq_resp;
410 args.out_size = I40E_AQ_BUF_SZ;
412 err = i40evf_execute_vf_cmd(dev, &args);
414 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
418 pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
419 vf->version_major = pver->major;
420 vf->version_minor = pver->minor;
421 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
422 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
423 else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
424 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
425 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
427 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
428 vf->version_major, vf->version_minor,
429 I40E_VIRTCHNL_VERSION_MAJOR,
430 I40E_VIRTCHNL_VERSION_MINOR);
438 i40evf_get_vf_resource(struct rte_eth_dev *dev)
440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
441 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
443 struct vf_cmd_info args;
446 args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
447 args.out_buffer = vf->aq_resp;
448 args.out_size = I40E_AQ_BUF_SZ;
450 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
451 I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
452 I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
453 I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
454 I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
455 args.in_args = (uint8_t *)∩︀
456 args.in_args_size = sizeof(caps);
459 args.in_args_size = 0;
461 err = i40evf_execute_vf_cmd(dev, &args);
464 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
468 len = sizeof(struct i40e_virtchnl_vf_resource) +
469 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
471 (void)rte_memcpy(vf->vf_res, args.out_buffer,
472 RTE_MIN(args.out_size, len));
473 i40e_vf_parse_hw_config(hw, vf->vf_res);
479 i40evf_config_promisc(struct rte_eth_dev *dev,
481 bool enable_multicast)
483 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
485 struct vf_cmd_info args;
486 struct i40e_virtchnl_promisc_info promisc;
489 promisc.vsi_id = vf->vsi_res->vsi_id;
492 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
494 if (enable_multicast)
495 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
497 args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
498 args.in_args = (uint8_t *)&promisc;
499 args.in_args_size = sizeof(promisc);
500 args.out_buffer = vf->aq_resp;
501 args.out_size = I40E_AQ_BUF_SZ;
503 err = i40evf_execute_vf_cmd(dev, &args);
506 PMD_DRV_LOG(ERR, "fail to execute command "
507 "CONFIG_PROMISCUOUS_MODE");
511 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
513 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
514 bool enable_vlan_strip)
516 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
518 struct vf_cmd_info args;
519 struct i40e_virtchnl_vlan_offload_info offload;
521 offload.vsi_id = vf->vsi_res->vsi_id;
522 offload.enable_vlan_strip = enable_vlan_strip;
524 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
525 args.in_args = (uint8_t *)&offload;
526 args.in_args_size = sizeof(offload);
527 args.out_buffer = vf->aq_resp;
528 args.out_size = I40E_AQ_BUF_SZ;
530 err = i40evf_execute_vf_cmd(dev, &args);
532 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
538 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
539 struct i40e_vsi_vlan_pvid_info *info)
541 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
543 struct vf_cmd_info args;
544 struct i40e_virtchnl_pvid_info tpid_info;
547 PMD_DRV_LOG(ERR, "invalid parameters");
548 return I40E_ERR_PARAM;
551 memset(&tpid_info, 0, sizeof(tpid_info));
552 tpid_info.vsi_id = vf->vsi_res->vsi_id;
553 (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
555 args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
556 args.in_args = (uint8_t *)&tpid_info;
557 args.in_args_size = sizeof(tpid_info);
558 args.out_buffer = vf->aq_resp;
559 args.out_size = I40E_AQ_BUF_SZ;
561 err = i40evf_execute_vf_cmd(dev, &args);
563 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
569 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
573 struct i40e_tx_queue *txq)
575 txq_info->vsi_id = vsi_id;
576 txq_info->queue_id = queue_id;
577 if (queue_id < nb_txq) {
578 txq_info->ring_len = txq->nb_tx_desc;
579 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
584 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
588 uint32_t max_pkt_size,
589 struct i40e_rx_queue *rxq)
591 rxq_info->vsi_id = vsi_id;
592 rxq_info->queue_id = queue_id;
593 rxq_info->max_pkt_size = max_pkt_size;
594 if (queue_id < nb_rxq) {
595 rxq_info->ring_len = rxq->nb_rx_desc;
596 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
597 rxq_info->databuffer_size =
598 (rte_pktmbuf_data_room_size(rxq->mp) -
599 RTE_PKTMBUF_HEADROOM);
603 /* It configures VSI queues to co-work with Linux PF host */
605 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
607 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
608 struct i40e_rx_queue **rxq =
609 (struct i40e_rx_queue **)dev->data->rx_queues;
610 struct i40e_tx_queue **txq =
611 (struct i40e_tx_queue **)dev->data->tx_queues;
612 struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
613 struct i40e_virtchnl_queue_pair_info *vc_qpi;
614 struct vf_cmd_info args;
615 uint16_t i, nb_qp = vf->num_queue_pairs;
616 const uint32_t size =
617 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
621 memset(buff, 0, sizeof(buff));
622 vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
623 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
624 vc_vqci->num_queue_pairs = nb_qp;
626 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
627 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
628 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
629 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
630 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
631 vf->max_pkt_len, rxq[i]);
633 memset(&args, 0, sizeof(args));
634 args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
635 args.in_args = (uint8_t *)vc_vqci;
636 args.in_args_size = size;
637 args.out_buffer = vf->aq_resp;
638 args.out_size = I40E_AQ_BUF_SZ;
639 ret = i40evf_execute_vf_cmd(dev, &args);
641 PMD_DRV_LOG(ERR, "Failed to execute command of "
642 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
647 /* It configures VSI queues to co-work with DPDK PF host */
649 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
651 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
652 struct i40e_rx_queue **rxq =
653 (struct i40e_rx_queue **)dev->data->rx_queues;
654 struct i40e_tx_queue **txq =
655 (struct i40e_tx_queue **)dev->data->tx_queues;
656 struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
657 struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
658 struct vf_cmd_info args;
659 uint16_t i, nb_qp = vf->num_queue_pairs;
660 const uint32_t size =
661 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
665 memset(buff, 0, sizeof(buff));
666 vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
667 vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
668 vc_vqcei->num_queue_pairs = nb_qp;
669 vc_qpei = vc_vqcei->qpair;
670 for (i = 0; i < nb_qp; i++, vc_qpei++) {
671 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
672 vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
673 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
674 vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
675 vf->max_pkt_len, rxq[i]);
676 if (i < dev->data->nb_rx_queues)
678 * It adds extra info for configuring VSI queues, which
679 * is needed to enable the configurable crc stripping
682 vc_qpei->rxq_ext.crcstrip =
683 dev->data->dev_conf.rxmode.hw_strip_crc;
685 memset(&args, 0, sizeof(args));
687 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
688 args.in_args = (uint8_t *)vc_vqcei;
689 args.in_args_size = size;
690 args.out_buffer = vf->aq_resp;
691 args.out_size = I40E_AQ_BUF_SZ;
692 ret = i40evf_execute_vf_cmd(dev, &args);
694 PMD_DRV_LOG(ERR, "Failed to execute command of "
695 "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
701 i40evf_configure_queues(struct rte_eth_dev *dev)
703 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
705 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
706 /* To support DPDK PF host */
707 return i40evf_configure_vsi_queues_ext(dev);
709 /* To support Linux PF host */
710 return i40evf_configure_vsi_queues(dev);
714 i40evf_config_irq_map(struct rte_eth_dev *dev)
716 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
717 struct vf_cmd_info args;
718 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
719 sizeof(struct i40e_virtchnl_vector_map)];
720 struct i40e_virtchnl_irq_map_info *map_info;
721 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
725 if (rte_intr_allow_others(intr_handle)) {
726 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
727 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
729 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
731 vector_id = I40E_MISC_VEC_ID;
734 map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
735 map_info->num_vectors = 1;
736 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
737 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
738 /* Alway use default dynamic MSIX interrupt */
739 map_info->vecmap[0].vector_id = vector_id;
740 /* Don't map any tx queue */
741 map_info->vecmap[0].txq_map = 0;
742 map_info->vecmap[0].rxq_map = 0;
743 for (i = 0; i < dev->data->nb_rx_queues; i++) {
744 map_info->vecmap[0].rxq_map |= 1 << i;
745 if (rte_intr_dp_is_en(intr_handle))
746 intr_handle->intr_vec[i] = vector_id;
749 args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
750 args.in_args = (u8 *)cmd_buffer;
751 args.in_args_size = sizeof(cmd_buffer);
752 args.out_buffer = vf->aq_resp;
753 args.out_size = I40E_AQ_BUF_SZ;
754 err = i40evf_execute_vf_cmd(dev, &args);
756 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
762 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
765 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
766 struct i40e_virtchnl_queue_select queue_select;
768 struct vf_cmd_info args;
769 memset(&queue_select, 0, sizeof(queue_select));
770 queue_select.vsi_id = vf->vsi_res->vsi_id;
773 queue_select.rx_queues |= 1 << qid;
775 queue_select.tx_queues |= 1 << qid;
778 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
780 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
781 args.in_args = (u8 *)&queue_select;
782 args.in_args_size = sizeof(queue_select);
783 args.out_buffer = vf->aq_resp;
784 args.out_size = I40E_AQ_BUF_SZ;
785 err = i40evf_execute_vf_cmd(dev, &args);
787 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
788 isrx ? "RX" : "TX", qid, on ? "on" : "off");
794 i40evf_start_queues(struct rte_eth_dev *dev)
796 struct rte_eth_dev_data *dev_data = dev->data;
798 struct i40e_rx_queue *rxq;
799 struct i40e_tx_queue *txq;
801 for (i = 0; i < dev->data->nb_rx_queues; i++) {
802 rxq = dev_data->rx_queues[i];
803 if (rxq->rx_deferred_start)
805 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
806 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
811 for (i = 0; i < dev->data->nb_tx_queues; i++) {
812 txq = dev_data->tx_queues[i];
813 if (txq->tx_deferred_start)
815 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
816 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
825 i40evf_stop_queues(struct rte_eth_dev *dev)
829 /* Stop TX queues first */
830 for (i = 0; i < dev->data->nb_tx_queues; i++) {
831 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
832 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
837 /* Then stop RX queues */
838 for (i = 0; i < dev->data->nb_rx_queues; i++) {
839 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
840 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
849 i40evf_add_mac_addr(struct rte_eth_dev *dev,
850 struct ether_addr *addr,
851 __rte_unused uint32_t index,
852 __rte_unused uint32_t pool)
854 struct i40e_virtchnl_ether_addr_list *list;
855 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
856 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
857 sizeof(struct i40e_virtchnl_ether_addr)];
859 struct vf_cmd_info args;
861 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
862 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
863 addr->addr_bytes[0], addr->addr_bytes[1],
864 addr->addr_bytes[2], addr->addr_bytes[3],
865 addr->addr_bytes[4], addr->addr_bytes[5]);
869 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
870 list->vsi_id = vf->vsi_res->vsi_id;
871 list->num_elements = 1;
872 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
873 sizeof(addr->addr_bytes));
875 args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
876 args.in_args = cmd_buffer;
877 args.in_args_size = sizeof(cmd_buffer);
878 args.out_buffer = vf->aq_resp;
879 args.out_size = I40E_AQ_BUF_SZ;
880 err = i40evf_execute_vf_cmd(dev, &args);
882 PMD_DRV_LOG(ERR, "fail to execute command "
883 "OP_ADD_ETHER_ADDRESS");
889 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
891 struct i40e_virtchnl_ether_addr_list *list;
892 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
893 struct rte_eth_dev_data *data = dev->data;
894 struct ether_addr *addr;
895 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
896 sizeof(struct i40e_virtchnl_ether_addr)];
898 struct vf_cmd_info args;
900 addr = &(data->mac_addrs[index]);
902 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
903 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
904 addr->addr_bytes[0], addr->addr_bytes[1],
905 addr->addr_bytes[2], addr->addr_bytes[3],
906 addr->addr_bytes[4], addr->addr_bytes[5]);
910 list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
911 list->vsi_id = vf->vsi_res->vsi_id;
912 list->num_elements = 1;
913 (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
914 sizeof(addr->addr_bytes));
916 args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
917 args.in_args = cmd_buffer;
918 args.in_args_size = sizeof(cmd_buffer);
919 args.out_buffer = vf->aq_resp;
920 args.out_size = I40E_AQ_BUF_SZ;
921 err = i40evf_execute_vf_cmd(dev, &args);
923 PMD_DRV_LOG(ERR, "fail to execute command "
924 "OP_DEL_ETHER_ADDRESS");
929 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
931 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
932 struct i40e_virtchnl_queue_select q_stats;
934 struct vf_cmd_info args;
936 memset(&q_stats, 0, sizeof(q_stats));
937 q_stats.vsi_id = vf->vsi_res->vsi_id;
938 args.ops = I40E_VIRTCHNL_OP_GET_STATS;
939 args.in_args = (u8 *)&q_stats;
940 args.in_args_size = sizeof(q_stats);
941 args.out_buffer = vf->aq_resp;
942 args.out_size = I40E_AQ_BUF_SZ;
944 err = i40evf_execute_vf_cmd(dev, &args);
946 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
950 *pstats = (struct i40e_eth_stats *)args.out_buffer;
955 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
958 struct i40e_eth_stats *pstats = NULL;
960 ret = i40evf_update_stats(dev, &pstats);
964 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
965 pstats->rx_broadcast;
966 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
968 stats->ierrors = pstats->rx_discards;
969 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
970 stats->ibytes = pstats->rx_bytes;
971 stats->obytes = pstats->tx_bytes;
977 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
979 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
980 struct i40e_eth_stats *pstats = NULL;
982 /* read stat values to clear hardware registers */
983 i40evf_update_stats(dev, &pstats);
985 /* set stats offset base on current values */
986 vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
989 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
990 struct rte_eth_xstat_name *xstats_names,
991 __rte_unused unsigned limit)
995 if (xstats_names != NULL)
996 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
997 snprintf(xstats_names[i].name,
998 sizeof(xstats_names[i].name),
999 "%s", rte_i40evf_stats_strings[i].name);
1001 return I40EVF_NB_XSTATS;
1004 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1005 struct rte_eth_xstat *xstats, unsigned n)
1009 struct i40e_eth_stats *pstats = NULL;
1011 if (n < I40EVF_NB_XSTATS)
1012 return I40EVF_NB_XSTATS;
1014 ret = i40evf_update_stats(dev, &pstats);
1021 /* loop over xstats array and values from pstats */
1022 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1024 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1025 rte_i40evf_stats_strings[i].offset);
1028 return I40EVF_NB_XSTATS;
1032 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1034 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1035 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1036 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1039 struct vf_cmd_info args;
1041 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1042 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1043 vlan_list->num_elements = 1;
1044 vlan_list->vlan_id[0] = vlanid;
1046 args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1047 args.in_args = (u8 *)&cmd_buffer;
1048 args.in_args_size = sizeof(cmd_buffer);
1049 args.out_buffer = vf->aq_resp;
1050 args.out_size = I40E_AQ_BUF_SZ;
1051 err = i40evf_execute_vf_cmd(dev, &args);
1053 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1059 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1061 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1062 struct i40e_virtchnl_vlan_filter_list *vlan_list;
1063 uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1066 struct vf_cmd_info args;
1068 vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1069 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1070 vlan_list->num_elements = 1;
1071 vlan_list->vlan_id[0] = vlanid;
1073 args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1074 args.in_args = (u8 *)&cmd_buffer;
1075 args.in_args_size = sizeof(cmd_buffer);
1076 args.out_buffer = vf->aq_resp;
1077 args.out_size = I40E_AQ_BUF_SZ;
1078 err = i40evf_execute_vf_cmd(dev, &args);
1080 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1085 static const struct rte_pci_id pci_id_i40evf_map[] = {
1086 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1087 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1088 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1089 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1090 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
1091 { .vendor_id = 0, /* sentinel */ },
1095 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1096 struct rte_eth_link *link)
1098 struct rte_eth_link *dst = &(dev->data->dev_link);
1099 struct rte_eth_link *src = link;
1101 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1102 *(uint64_t *)src) == 0)
1110 i40evf_disable_irq0(struct i40e_hw *hw)
1112 /* Disable all interrupt types */
1113 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1114 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1115 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1116 I40EVF_WRITE_FLUSH(hw);
1121 i40evf_enable_irq0(struct i40e_hw *hw)
1123 /* Enable admin queue interrupt trigger */
1126 i40evf_disable_irq0(hw);
1127 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1128 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1129 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1130 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1132 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1133 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1134 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1135 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1137 I40EVF_WRITE_FLUSH(hw);
1141 i40evf_reset_vf(struct i40e_hw *hw)
1145 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1146 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1150 * After issuing vf reset command to pf, pf won't necessarily
1151 * reset vf, it depends on what state it exactly is. If it's not
1152 * initialized yet, it won't have vf reset since it's in a certain
1153 * state. If not, it will try to reset. Even vf is reset, pf will
1154 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1155 * it to ACTIVE. In this duration, vf may not catch the moment that
1156 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1160 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1161 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1162 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1163 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1164 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1170 if (i >= MAX_RESET_WAIT_CNT) {
1171 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1179 i40evf_init_vf(struct rte_eth_dev *dev)
1182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1184 struct ether_addr *p_mac_addr;
1186 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1188 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1189 vf->dev_data = dev->data;
1190 err = i40e_set_mac_type(hw);
1192 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1196 i40e_init_adminq_parameter(hw);
1197 err = i40e_init_adminq(hw);
1199 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1203 /* Reset VF and wait until it's complete */
1204 if (i40evf_reset_vf(hw)) {
1205 PMD_INIT_LOG(ERR, "reset NIC failed");
1209 /* VF reset, shutdown admin queue and initialize again */
1210 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1211 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1215 i40e_init_adminq_parameter(hw);
1216 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1217 PMD_INIT_LOG(ERR, "init_adminq failed");
1220 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1222 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1225 if (i40evf_check_api_version(dev) != 0) {
1226 PMD_INIT_LOG(ERR, "check_api version failed");
1229 bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1230 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1231 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1233 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1237 if (i40evf_get_vf_resource(dev) != 0) {
1238 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1242 /* got VF config message back from PF, now we can parse it */
1243 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1244 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1245 vf->vsi_res = &vf->vf_res->vsi_res[i];
1249 PMD_INIT_LOG(ERR, "no LAN VSI found");
1253 if (hw->mac.type == I40E_MAC_X722_VF)
1254 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1255 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1256 vf->vsi.type = vf->vsi_res->vsi_type;
1257 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1258 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1260 /* Store the MAC address configured by host, or generate random one */
1261 p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1262 if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1263 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1265 eth_random_addr(hw->mac.addr); /* Generate a random one */
1267 /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1268 if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1269 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1270 (I40E_ITR_INDEX_DEFAULT <<
1271 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1273 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1274 I40EVF_WRITE_FLUSH(hw);
1280 rte_free(vf->vf_res);
1282 i40e_shutdown_adminq(hw); /* ignore error */
1288 i40evf_uninit_vf(struct rte_eth_dev *dev)
1290 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1291 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293 PMD_INIT_FUNC_TRACE();
1295 if (hw->adapter_stopped == 0)
1296 i40evf_dev_close(dev);
1297 rte_free(vf->vf_res);
1299 rte_free(vf->aq_resp);
1306 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1308 __rte_unused uint16_t msglen)
1310 struct i40e_virtchnl_pf_event *pf_msg =
1311 (struct i40e_virtchnl_pf_event *)msg;
1312 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1314 switch (pf_msg->event) {
1315 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1316 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1317 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
1319 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1320 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1321 vf->link_up = pf_msg->event_data.link_event.link_status;
1322 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1324 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1325 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1328 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1334 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1338 struct i40e_arq_event_info info;
1339 struct i40e_virtchnl_msg *v_msg;
1340 uint16_t pending, opcode;
1343 info.buf_len = I40E_AQ_BUF_SZ;
1345 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1348 info.msg_buf = vf->aq_resp;
1349 v_msg = (struct i40e_virtchnl_msg *)&info.desc;
1353 ret = i40e_clean_arq_element(hw, &info, &pending);
1355 if (ret != I40E_SUCCESS) {
1356 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1360 opcode = rte_le_to_cpu_16(info.desc.opcode);
1363 case i40e_aqc_opc_send_msg_to_vf:
1364 if (v_msg->v_opcode == I40E_VIRTCHNL_OP_EVENT)
1366 i40evf_handle_pf_event(dev, info.msg_buf,
1369 /* read message and it's expected one */
1370 if (v_msg->v_opcode == vf->pend_cmd) {
1371 vf->cmd_retval = v_msg->v_retval;
1372 /* prevent compiler reordering */
1373 rte_compiler_barrier();
1376 PMD_DRV_LOG(ERR, "command mismatch,"
1377 "expect %u, get %u",
1378 vf->pend_cmd, v_msg->v_opcode);
1379 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1380 " opcode = %d\n", v_msg->v_opcode);
1384 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1392 * Interrupt handler triggered by NIC for handling
1393 * specific interrupt. Only adminq interrupt is processed in VF.
1396 * Pointer to interrupt handle.
1398 * The address of parameter (struct rte_eth_dev *) regsitered before.
1404 i40evf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
1407 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1408 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411 i40evf_disable_irq0(hw);
1413 /* read out interrupt causes */
1414 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1416 /* No interrupt event indicated */
1417 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1418 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1422 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1423 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1424 i40evf_handle_aq_msg(dev);
1427 /* Link Status Change interrupt */
1428 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1429 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1433 i40evf_enable_irq0(hw);
1434 rte_intr_enable(&dev->pci_dev->intr_handle);
1438 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\
1441 eth_dev->data->dev_private);
1442 struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1444 PMD_INIT_FUNC_TRACE();
1446 /* assign ops func pointer */
1447 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1448 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1449 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1452 * For secondary processes, we don't initialise any further as primary
1453 * has already done this work.
1455 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1456 i40e_set_rx_function(eth_dev);
1457 i40e_set_tx_function(eth_dev);
1461 rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1463 hw->vendor_id = eth_dev->pci_dev->id.vendor_id;
1464 hw->device_id = eth_dev->pci_dev->id.device_id;
1465 hw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;
1466 hw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;
1467 hw->bus.device = eth_dev->pci_dev->addr.devid;
1468 hw->bus.func = eth_dev->pci_dev->addr.function;
1469 hw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;
1470 hw->adapter_stopped = 0;
1472 if(i40evf_init_vf(eth_dev) != 0) {
1473 PMD_INIT_LOG(ERR, "Init vf failed");
1477 /* register callback func to eal lib */
1478 rte_intr_callback_register(&pci_dev->intr_handle,
1479 i40evf_dev_interrupt_handler, (void *)eth_dev);
1481 /* enable uio intr after callback register */
1482 rte_intr_enable(&pci_dev->intr_handle);
1484 /* configure and enable device interrupt */
1485 i40evf_enable_irq0(hw);
1488 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1489 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1491 if (eth_dev->data->mac_addrs == NULL) {
1492 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1493 " store MAC addresses",
1494 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1497 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1498 ð_dev->data->mac_addrs[0]);
1504 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1506 PMD_INIT_FUNC_TRACE();
1508 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1511 eth_dev->dev_ops = NULL;
1512 eth_dev->rx_pkt_burst = NULL;
1513 eth_dev->tx_pkt_burst = NULL;
1515 if (i40evf_uninit_vf(eth_dev) != 0) {
1516 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1520 rte_free(eth_dev->data->mac_addrs);
1521 eth_dev->data->mac_addrs = NULL;
1526 * virtual function driver struct
1528 static struct eth_driver rte_i40evf_pmd = {
1530 .name = "rte_i40evf_pmd",
1531 .id_table = pci_id_i40evf_map,
1532 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1534 .eth_dev_init = i40evf_dev_init,
1535 .eth_dev_uninit = i40evf_dev_uninit,
1536 .dev_private_size = sizeof(struct i40e_adapter),
1540 * VF Driver initialization routine.
1541 * Invoked one at EAL init time.
1542 * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.
1545 rte_i40evf_pmd_init(const char *name __rte_unused,
1546 const char *params __rte_unused)
1548 PMD_INIT_FUNC_TRACE();
1550 rte_eth_driver_register(&rte_i40evf_pmd);
1555 static struct rte_driver rte_i40evf_driver = {
1557 .init = rte_i40evf_pmd_init,
1560 PMD_REGISTER_DRIVER(rte_i40evf_driver, i40evf);
1561 DRIVER_REGISTER_PCI_TABLE(i40evf, pci_id_i40evf_map);
1564 i40evf_dev_configure(struct rte_eth_dev *dev)
1566 struct i40e_adapter *ad =
1567 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1568 struct rte_eth_conf *conf = &dev->data->dev_conf;
1571 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1572 * allocation or vector Rx preconditions we will reset it.
1574 ad->rx_bulk_alloc_allowed = true;
1575 ad->rx_vec_allowed = true;
1576 ad->tx_simple_allowed = true;
1577 ad->tx_vec_allowed = true;
1579 /* For non-DPDK PF drivers, VF has no ability to disable HW
1580 * CRC strip, and is implicitly enabled by the PF.
1582 if (!conf->rxmode.hw_strip_crc) {
1583 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1584 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1585 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1586 /* Peer is running non-DPDK PF driver. */
1587 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1592 return i40evf_init_vlan(dev);
1596 i40evf_init_vlan(struct rte_eth_dev *dev)
1598 struct rte_eth_dev_data *data = dev->data;
1601 /* Apply vlan offload setting */
1602 i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1604 /* Apply pvid setting */
1605 ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1606 data->dev_conf.txmode.hw_vlan_insert_pvid);
1611 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1613 bool enable_vlan_strip = 0;
1614 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1615 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1617 /* Linux pf host doesn't support vlan offload yet */
1618 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1619 /* Vlan stripping setting */
1620 if (mask & ETH_VLAN_STRIP_MASK) {
1621 /* Enable or disable VLAN stripping */
1622 if (dev_conf->rxmode.hw_vlan_strip)
1623 enable_vlan_strip = 1;
1625 enable_vlan_strip = 0;
1627 i40evf_config_vlan_offload(dev, enable_vlan_strip);
1633 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1635 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1636 struct i40e_vsi_vlan_pvid_info info;
1637 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1639 memset(&info, 0, sizeof(info));
1642 /* Linux pf host don't support vlan offload yet */
1643 if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1645 info.config.pvid = pvid;
1647 info.config.reject.tagged =
1648 dev_conf->txmode.hw_vlan_reject_tagged;
1649 info.config.reject.untagged =
1650 dev_conf->txmode.hw_vlan_reject_untagged;
1652 return i40evf_config_vlan_pvid(dev, &info);
1659 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1661 struct i40e_rx_queue *rxq;
1663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665 PMD_INIT_FUNC_TRACE();
1667 if (rx_queue_id < dev->data->nb_rx_queues) {
1668 rxq = dev->data->rx_queues[rx_queue_id];
1670 err = i40e_alloc_rx_queue_mbufs(rxq);
1672 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1678 /* Init the RX tail register. */
1679 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1680 I40EVF_WRITE_FLUSH(hw);
1682 /* Ready to switch the queue on */
1683 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1686 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1689 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1696 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1698 struct i40e_rx_queue *rxq;
1701 if (rx_queue_id < dev->data->nb_rx_queues) {
1702 rxq = dev->data->rx_queues[rx_queue_id];
1704 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1707 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1712 i40e_rx_queue_release_mbufs(rxq);
1713 i40e_reset_rx_queue(rxq);
1714 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1721 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1725 PMD_INIT_FUNC_TRACE();
1727 if (tx_queue_id < dev->data->nb_tx_queues) {
1729 /* Ready to switch the queue on */
1730 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1733 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1736 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1743 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1745 struct i40e_tx_queue *txq;
1748 if (tx_queue_id < dev->data->nb_tx_queues) {
1749 txq = dev->data->tx_queues[tx_queue_id];
1751 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1754 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1759 i40e_tx_queue_release_mbufs(txq);
1760 i40e_reset_tx_queue(txq);
1761 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1768 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1773 ret = i40evf_add_vlan(dev, vlan_id);
1775 ret = i40evf_del_vlan(dev,vlan_id);
1781 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784 struct rte_eth_dev_data *dev_data = dev->data;
1785 struct rte_pktmbuf_pool_private *mbp_priv;
1786 uint16_t buf_size, len;
1788 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1789 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1790 I40EVF_WRITE_FLUSH(hw);
1792 /* Calculate the maximum packet length allowed */
1793 mbp_priv = rte_mempool_get_priv(rxq->mp);
1794 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1795 RTE_PKTMBUF_HEADROOM);
1796 rxq->hs_mode = i40e_header_split_none;
1797 rxq->rx_hdr_len = 0;
1798 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1799 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1800 rxq->max_pkt_len = RTE_MIN(len,
1801 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1804 * Check if the jumbo frame and maximum packet length are set correctly
1806 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1807 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1808 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1809 PMD_DRV_LOG(ERR, "maximum packet length must be "
1810 "larger than %u and smaller than %u, as jumbo "
1811 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1812 (uint32_t)I40E_FRAME_SIZE_MAX);
1813 return I40E_ERR_CONFIG;
1816 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1817 rxq->max_pkt_len > ETHER_MAX_LEN) {
1818 PMD_DRV_LOG(ERR, "maximum packet length must be "
1819 "larger than %u and smaller than %u, as jumbo "
1820 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1821 (uint32_t)ETHER_MAX_LEN);
1822 return I40E_ERR_CONFIG;
1826 if (dev_data->dev_conf.rxmode.enable_scatter ||
1827 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1828 dev_data->scattered_rx = 1;
1835 i40evf_rx_init(struct rte_eth_dev *dev)
1837 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1839 int ret = I40E_SUCCESS;
1840 struct i40e_rx_queue **rxq =
1841 (struct i40e_rx_queue **)dev->data->rx_queues;
1843 i40evf_config_rss(vf);
1844 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1845 if (!rxq[i] || !rxq[i]->q_set)
1847 ret = i40evf_rxq_init(dev, rxq[i]);
1848 if (ret != I40E_SUCCESS)
1851 if (ret == I40E_SUCCESS)
1852 i40e_set_rx_function(dev);
1858 i40evf_tx_init(struct rte_eth_dev *dev)
1861 struct i40e_tx_queue **txq =
1862 (struct i40e_tx_queue **)dev->data->tx_queues;
1863 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865 for (i = 0; i < dev->data->nb_tx_queues; i++)
1866 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1868 i40e_set_tx_function(dev);
1872 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1874 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1875 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1878 if (!rte_intr_allow_others(intr_handle)) {
1880 I40E_VFINT_DYN_CTL01,
1881 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1882 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1883 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1884 I40EVF_WRITE_FLUSH(hw);
1888 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1889 /* To support DPDK PF host */
1891 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1892 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1893 I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1894 /* If host driver is kernel driver, do nothing.
1895 * Interrupt 0 is used for rx packets, but don't set
1896 * I40E_VFINT_DYN_CTL01,
1897 * because it is already done in i40evf_enable_irq0.
1900 I40EVF_WRITE_FLUSH(hw);
1904 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1906 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1907 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1910 if (!rte_intr_allow_others(intr_handle)) {
1911 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1912 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1913 I40EVF_WRITE_FLUSH(hw);
1917 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1919 I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1922 /* If host driver is kernel driver, do nothing.
1923 * Interrupt 0 is used for rx packets, but don't zero
1924 * I40E_VFINT_DYN_CTL01,
1925 * because interrupt 0 is also used for adminq processing.
1928 I40EVF_WRITE_FLUSH(hw);
1932 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1934 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1940 msix_intr = intr_handle->intr_vec[queue_id];
1941 if (msix_intr == I40E_MISC_VEC_ID)
1942 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1943 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1944 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1945 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1947 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1950 I40E_VFINT_DYN_CTLN1(msix_intr -
1952 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1953 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1954 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1956 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1958 I40EVF_WRITE_FLUSH(hw);
1960 rte_intr_enable(&dev->pci_dev->intr_handle);
1966 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1968 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1969 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972 msix_intr = intr_handle->intr_vec[queue_id];
1973 if (msix_intr == I40E_MISC_VEC_ID)
1974 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1977 I40E_VFINT_DYN_CTLN1(msix_intr -
1981 I40EVF_WRITE_FLUSH(hw);
1987 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1989 struct i40e_virtchnl_ether_addr_list *list;
1990 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1995 struct ether_addr *addr;
1996 struct vf_cmd_info args;
2000 len = sizeof(struct i40e_virtchnl_ether_addr_list);
2001 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2002 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2004 len += sizeof(struct i40e_virtchnl_ether_addr);
2005 if (len >= I40E_AQ_BUF_SZ) {
2011 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2013 for (i = begin; i < next_begin; i++) {
2014 addr = &dev->data->mac_addrs[i];
2015 if (is_zero_ether_addr(addr))
2017 (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2018 sizeof(addr->addr_bytes));
2019 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2020 addr->addr_bytes[0], addr->addr_bytes[1],
2021 addr->addr_bytes[2], addr->addr_bytes[3],
2022 addr->addr_bytes[4], addr->addr_bytes[5]);
2025 list->vsi_id = vf->vsi_res->vsi_id;
2026 list->num_elements = j;
2027 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2028 I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2029 args.in_args = (uint8_t *)list;
2030 args.in_args_size = len;
2031 args.out_buffer = vf->aq_resp;
2032 args.out_size = I40E_AQ_BUF_SZ;
2033 err = i40evf_execute_vf_cmd(dev, &args);
2035 PMD_DRV_LOG(ERR, "fail to execute command %s",
2036 add ? "OP_ADD_ETHER_ADDRESS" :
2037 "OP_DEL_ETHER_ADDRESS");
2040 } while (begin < I40E_NUM_MACADDR_MAX);
2044 i40evf_dev_start(struct rte_eth_dev *dev)
2046 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2047 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2049 uint32_t intr_vector = 0;
2051 PMD_INIT_FUNC_TRACE();
2053 hw->adapter_stopped = 0;
2055 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2056 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2057 dev->data->nb_tx_queues);
2059 /* check and configure queue intr-vector mapping */
2060 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2061 intr_vector = dev->data->nb_rx_queues;
2062 if (rte_intr_efd_enable(intr_handle, intr_vector))
2066 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2067 intr_handle->intr_vec =
2068 rte_zmalloc("intr_vec",
2069 dev->data->nb_rx_queues * sizeof(int), 0);
2070 if (!intr_handle->intr_vec) {
2071 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2072 " intr_vec\n", dev->data->nb_rx_queues);
2077 if (i40evf_rx_init(dev) != 0){
2078 PMD_DRV_LOG(ERR, "failed to do RX init");
2082 i40evf_tx_init(dev);
2084 if (i40evf_configure_queues(dev) != 0) {
2085 PMD_DRV_LOG(ERR, "configure queues failed");
2088 if (i40evf_config_irq_map(dev)) {
2089 PMD_DRV_LOG(ERR, "config_irq_map failed");
2093 /* Set all mac addrs */
2094 i40evf_add_del_all_mac_addr(dev, TRUE);
2096 if (i40evf_start_queues(dev) != 0) {
2097 PMD_DRV_LOG(ERR, "enable queues failed");
2101 i40evf_enable_queues_intr(dev);
2105 i40evf_add_del_all_mac_addr(dev, FALSE);
2111 i40evf_dev_stop(struct rte_eth_dev *dev)
2113 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2115 PMD_INIT_FUNC_TRACE();
2117 i40evf_stop_queues(dev);
2118 i40evf_disable_queues_intr(dev);
2119 i40e_dev_clear_queues(dev);
2121 /* Clean datapath event and queue/vec mapping */
2122 rte_intr_efd_disable(intr_handle);
2123 if (intr_handle->intr_vec) {
2124 rte_free(intr_handle->intr_vec);
2125 intr_handle->intr_vec = NULL;
2127 /* remove all mac addrs */
2128 i40evf_add_del_all_mac_addr(dev, FALSE);
2133 i40evf_dev_link_update(struct rte_eth_dev *dev,
2134 __rte_unused int wait_to_complete)
2136 struct rte_eth_link new_link;
2137 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2139 * DPDK pf host provide interfacet to acquire link status
2140 * while Linux driver does not
2143 /* Linux driver PF host */
2144 switch (vf->link_speed) {
2145 case I40E_LINK_SPEED_100MB:
2146 new_link.link_speed = ETH_SPEED_NUM_100M;
2148 case I40E_LINK_SPEED_1GB:
2149 new_link.link_speed = ETH_SPEED_NUM_1G;
2151 case I40E_LINK_SPEED_10GB:
2152 new_link.link_speed = ETH_SPEED_NUM_10G;
2154 case I40E_LINK_SPEED_20GB:
2155 new_link.link_speed = ETH_SPEED_NUM_20G;
2157 case I40E_LINK_SPEED_40GB:
2158 new_link.link_speed = ETH_SPEED_NUM_40G;
2161 new_link.link_speed = ETH_SPEED_NUM_100M;
2164 /* full duplex only */
2165 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2166 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2169 i40evf_dev_atomic_write_link_status(dev, &new_link);
2175 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2177 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2180 /* If enabled, just return */
2181 if (vf->promisc_unicast_enabled)
2184 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2186 vf->promisc_unicast_enabled = TRUE;
2190 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2192 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2195 /* If disabled, just return */
2196 if (!vf->promisc_unicast_enabled)
2199 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2201 vf->promisc_unicast_enabled = FALSE;
2205 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2207 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2210 /* If enabled, just return */
2211 if (vf->promisc_multicast_enabled)
2214 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2216 vf->promisc_multicast_enabled = TRUE;
2220 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2222 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2225 /* If enabled, just return */
2226 if (!vf->promisc_multicast_enabled)
2229 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2231 vf->promisc_multicast_enabled = FALSE;
2235 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2237 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2239 memset(dev_info, 0, sizeof(*dev_info));
2240 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2241 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2242 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2243 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2244 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2245 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2246 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2247 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2248 dev_info->rx_offload_capa =
2249 DEV_RX_OFFLOAD_VLAN_STRIP |
2250 DEV_RX_OFFLOAD_QINQ_STRIP |
2251 DEV_RX_OFFLOAD_IPV4_CKSUM |
2252 DEV_RX_OFFLOAD_UDP_CKSUM |
2253 DEV_RX_OFFLOAD_TCP_CKSUM;
2254 dev_info->tx_offload_capa =
2255 DEV_TX_OFFLOAD_VLAN_INSERT |
2256 DEV_TX_OFFLOAD_QINQ_INSERT |
2257 DEV_TX_OFFLOAD_IPV4_CKSUM |
2258 DEV_TX_OFFLOAD_UDP_CKSUM |
2259 DEV_TX_OFFLOAD_TCP_CKSUM |
2260 DEV_TX_OFFLOAD_SCTP_CKSUM;
2262 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2264 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2265 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2266 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2268 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2272 dev_info->default_txconf = (struct rte_eth_txconf) {
2274 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2275 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2276 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2278 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2279 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2280 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2281 ETH_TXQ_FLAGS_NOOFFLOADS,
2284 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2285 .nb_max = I40E_MAX_RING_DESC,
2286 .nb_min = I40E_MIN_RING_DESC,
2287 .nb_align = I40E_ALIGN_RING_DESC,
2290 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2291 .nb_max = I40E_MAX_RING_DESC,
2292 .nb_min = I40E_MIN_RING_DESC,
2293 .nb_align = I40E_ALIGN_RING_DESC,
2298 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2300 if (i40evf_get_statics(dev, stats))
2301 PMD_DRV_LOG(ERR, "Get statics failed");
2305 i40evf_dev_close(struct rte_eth_dev *dev)
2307 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2308 struct rte_pci_device *pci_dev = dev->pci_dev;
2310 i40evf_dev_stop(dev);
2311 hw->adapter_stopped = 1;
2312 i40e_dev_free_queues(dev);
2313 i40evf_reset_vf(hw);
2314 i40e_shutdown_adminq(hw);
2315 /* disable uio intr before callback unregister */
2316 rte_intr_disable(&pci_dev->intr_handle);
2318 /* unregister callback func from eal lib */
2319 rte_intr_callback_unregister(&pci_dev->intr_handle,
2320 i40evf_dev_interrupt_handler, (void *)dev);
2321 i40evf_disable_irq0(hw);
2325 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2327 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2328 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2334 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2335 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2338 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2342 uint32_t *lut_dw = (uint32_t *)lut;
2343 uint16_t i, lut_size_dw = lut_size / 4;
2345 for (i = 0; i < lut_size_dw; i++)
2346 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2353 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2362 vf = I40E_VSI_TO_VF(vsi);
2363 hw = I40E_VSI_TO_HW(vsi);
2365 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2366 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2369 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2373 uint32_t *lut_dw = (uint32_t *)lut;
2374 uint16_t i, lut_size_dw = lut_size / 4;
2376 for (i = 0; i < lut_size_dw; i++)
2377 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2378 I40EVF_WRITE_FLUSH(hw);
2385 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2386 struct rte_eth_rss_reta_entry64 *reta_conf,
2389 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2391 uint16_t i, idx, shift;
2394 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2395 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2396 "(%d) doesn't match the number of hardware can "
2397 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2401 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2403 PMD_DRV_LOG(ERR, "No memory can be allocated");
2406 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2409 for (i = 0; i < reta_size; i++) {
2410 idx = i / RTE_RETA_GROUP_SIZE;
2411 shift = i % RTE_RETA_GROUP_SIZE;
2412 if (reta_conf[idx].mask & (1ULL << shift))
2413 lut[i] = reta_conf[idx].reta[shift];
2415 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2424 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2425 struct rte_eth_rss_reta_entry64 *reta_conf,
2428 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2429 uint16_t i, idx, shift;
2433 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2434 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2435 "(%d) doesn't match the number of hardware can "
2436 "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2440 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2442 PMD_DRV_LOG(ERR, "No memory can be allocated");
2446 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2449 for (i = 0; i < reta_size; i++) {
2450 idx = i / RTE_RETA_GROUP_SIZE;
2451 shift = i % RTE_RETA_GROUP_SIZE;
2452 if (reta_conf[idx].mask & (1ULL << shift))
2453 reta_conf[idx].reta[shift] = lut[i];
2463 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2465 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2466 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2469 if (!key || key_len == 0) {
2470 PMD_DRV_LOG(DEBUG, "No key to be configured");
2472 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2474 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2478 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2479 struct i40e_aqc_get_set_rss_key_data *key_dw =
2480 (struct i40e_aqc_get_set_rss_key_data *)key;
2482 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2484 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2487 uint32_t *hash_key = (uint32_t *)key;
2490 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2491 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2492 I40EVF_WRITE_FLUSH(hw);
2499 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2501 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2502 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2505 if (!key || !key_len)
2508 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2509 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2510 (struct i40e_aqc_get_set_rss_key_data *)key);
2512 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2516 uint32_t *key_dw = (uint32_t *)key;
2519 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2520 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2522 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2528 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2530 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2531 uint64_t rss_hf, hena;
2534 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2535 rss_conf->rss_key_len);
2539 rss_hf = rss_conf->rss_hf;
2540 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2541 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2542 hena &= ~I40E_RSS_HENA_ALL;
2543 hena |= i40e_config_hena(rss_hf);
2544 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2545 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2546 I40EVF_WRITE_FLUSH(hw);
2552 i40evf_disable_rss(struct i40e_vf *vf)
2554 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2557 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2558 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2559 hena &= ~I40E_RSS_HENA_ALL;
2560 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2561 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2562 I40EVF_WRITE_FLUSH(hw);
2566 i40evf_config_rss(struct i40e_vf *vf)
2568 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2569 struct rte_eth_rss_conf rss_conf;
2570 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2573 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2574 i40evf_disable_rss(vf);
2575 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2579 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2580 /* Fill out the look up table */
2581 for (i = 0, j = 0; i < nb_q; i++, j++) {
2584 lut = (lut << 8) | j;
2586 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2589 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2590 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2591 i40evf_disable_rss(vf);
2592 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2596 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2597 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2598 /* Calculate the default hash key */
2599 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2600 rss_key_default[i] = (uint32_t)rte_rand();
2601 rss_conf.rss_key = (uint8_t *)rss_key_default;
2602 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2606 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2610 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2611 struct rte_eth_rss_conf *rss_conf)
2613 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2618 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2619 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2620 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
2621 if (rss_hf != 0) /* Enable RSS */
2627 if (rss_hf == 0) /* Disable RSS */
2630 return i40evf_hw_rss_hash_set(vf, rss_conf);
2634 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2635 struct rte_eth_rss_conf *rss_conf)
2637 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2638 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2642 &rss_conf->rss_key_len);
2644 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2645 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2646 rss_conf->rss_hf = i40e_parse_hena(hena);