drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_arp.h>
  48 #include <rte_ip.h>
  49 #include <rte_udp.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52
  53 #include "i40e_logs.h"
  54 #include "base/i40e_type.h"
  55 #include "base/i40e_prototype.h"
  56 #include "i40e_ethdev.h"
  57 #include "i40e_rxtx.h"
  58
  59 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  60 #ifndef IPV6_ADDR_LEN
  61 #define IPV6_ADDR_LEN              16
  62 #endif
  63
  64 #define I40E_FDIR_PKT_LEN                   512
  65 #define I40E_FDIR_IP_DEFAULT_LEN            420
  66 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  70 #define I40E_FDIR_IPv6_TC_OFFSET            20
  71
  72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  73 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  74 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  75
  76 /* Wait count and interval for fdir filter programming */
  77 #define I40E_FDIR_WAIT_COUNT       10
  78 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  79
  80 /* Wait count and interval for fdir filter flush */
  81 #define I40E_FDIR_FLUSH_RETRY       50
  82 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  83
  84 #define I40E_COUNTER_PF           2
  85 /* Statistic counter index for one pf */
  86 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  87 #define I40E_MAX_FLX_SOURCE_OFF           480
  88 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  89
  90 #define NONUSE_FLX_PIT_DEST_OFF 63
  91 #define NONUSE_FLX_PIT_FSIZE    1
  92 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  93         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  94                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  95         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  96                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  97         ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
  98                         NONUSE_FLX_PIT_DEST_OFF : \
  99                         ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
 100                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
 101                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
 102
 103 #define I40E_FDIR_FLOWS ( \
 104         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
 105         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 106         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 107         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 108         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 109         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
 110         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 111         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 112         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 113         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 114         (1 << RTE_ETH_FLOW_L2_PAYLOAD))
 115
 116 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 117
 118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 119                         enum i40e_filter_pctype pctype,
 120                         const struct rte_eth_fdir_filter *filter,
 121                         bool add);
 122 static int i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
 123                          struct i40e_fdir_filter *filter);
 124 static struct i40e_fdir_filter *
 125 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
 126                         const struct rte_eth_fdir_input *input);
 127 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
 128                                    struct i40e_fdir_filter *filter);
 129
 130 static int
 131 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 132 {
 133         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 134         struct i40e_hmc_obj_rxq rx_ctx;
 135         int err = I40E_SUCCESS;
 136
 137         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 138         /* Init the RX queue in hardware */
 139         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 140         rx_ctx.hbuff = 0;
 141         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 142         rx_ctx.qlen = rxq->nb_rx_desc;
 143 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 144         rx_ctx.dsize = 1;
 145 #endif
 146         rx_ctx.dtype = i40e_header_split_none;
 147         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 148         rx_ctx.rxmax = ETHER_MAX_LEN;
 149         rx_ctx.tphrdesc_ena = 1;
 150         rx_ctx.tphwdesc_ena = 1;
 151         rx_ctx.tphdata_ena = 1;
 152         rx_ctx.tphhead_ena = 1;
 153         rx_ctx.lrxqthresh = 2;
 154         rx_ctx.crcstrip = 0;
 155         rx_ctx.l2tsel = 1;
 156         rx_ctx.showiv = 0;
 157         rx_ctx.prefena = 1;
 158
 159         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 160         if (err != I40E_SUCCESS) {
 161                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 162                 return err;
 163         }
 164         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 165         if (err != I40E_SUCCESS) {
 166                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 167                 return err;
 168         }
 169         rxq->qrx_tail = hw->hw_addr +
 170                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 171
 172         rte_wmb();
 173         /* Init the RX tail regieter. */
 174         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 175         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 176
 177         return err;
 178 }
 179
 180 /*
 181  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 182  * @pf: board private structure
 183  */
 184 int
 185 i40e_fdir_setup(struct i40e_pf *pf)
 186 {
 187         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 188         struct i40e_vsi *vsi;
 189         int err = I40E_SUCCESS;
 190         char z_name[RTE_MEMZONE_NAMESIZE];
 191         const struct rte_memzone *mz = NULL;
 192         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 193
 194         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 195                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 196                 return I40E_NOT_SUPPORTED;
 197         }
 198
 199         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 200                         " num_filters_best_effort = %u.",
 201                         hw->func_caps.fd_filters_guaranteed,
 202                         hw->func_caps.fd_filters_best_effort);
 203
 204         vsi = pf->fdir.fdir_vsi;
 205         if (vsi) {
 206                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 207                 return I40E_SUCCESS;
 208         }
 209         /* make new FDIR VSI */
 210         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 211         if (!vsi) {
 212                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 213                 return I40E_ERR_NO_AVAILABLE_VSI;
 214         }
 215         pf->fdir.fdir_vsi = vsi;
 216
 217         /*Fdir tx queue setup*/
 218         err = i40e_fdir_setup_tx_resources(pf);
 219         if (err) {
 220                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 221                 goto fail_setup_tx;
 222         }
 223
 224         /*Fdir rx queue setup*/
 225         err = i40e_fdir_setup_rx_resources(pf);
 226         if (err) {
 227                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 228                 goto fail_setup_rx;
 229         }
 230
 231         err = i40e_tx_queue_init(pf->fdir.txq);
 232         if (err) {
 233                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 234                 goto fail_mem;
 235         }
 236
 237         /* need switch on before dev start*/
 238         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 239         if (err) {
 240                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 241                 goto fail_mem;
 242         }
 243
 244         /* Init the rx queue in hardware */
 245         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 246         if (err) {
 247                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 248                 goto fail_mem;
 249         }
 250
 251         /* switch on rx queue */
 252         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 253         if (err) {
 254                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 255                 goto fail_mem;
 256         }
 257
 258         /* reserve memory for the fdir programming packet */
 259         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 260                         eth_dev->data->drv_name,
 261                         I40E_FDIR_MZ_NAME,
 262                         eth_dev->data->port_id);
 263         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 264         if (!mz) {
 265                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 266                                  "flow director program packet.");
 267                 err = I40E_ERR_NO_MEMORY;
 268                 goto fail_mem;
 269         }
 270         pf->fdir.prg_pkt = mz->addr;
 271         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 272
 273         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 274         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 275                     vsi->base_queue);
 276         return I40E_SUCCESS;
 277
 278 fail_mem:
 279         i40e_dev_rx_queue_release(pf->fdir.rxq);
 280         pf->fdir.rxq = NULL;
 281 fail_setup_rx:
 282         i40e_dev_tx_queue_release(pf->fdir.txq);
 283         pf->fdir.txq = NULL;
 284 fail_setup_tx:
 285         i40e_vsi_release(vsi);
 286         pf->fdir.fdir_vsi = NULL;
 287         return err;
 288 }
 289
 290 /*
 291  * i40e_fdir_teardown - release the Flow Director resources
 292  * @pf: board private structure
 293  */
 294 void
 295 i40e_fdir_teardown(struct i40e_pf *pf)
 296 {
 297         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 298         struct i40e_vsi *vsi;
 299
 300         vsi = pf->fdir.fdir_vsi;
 301         if (!vsi)
 302                 return;
 303         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 304         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 305         i40e_dev_rx_queue_release(pf->fdir.rxq);
 306         pf->fdir.rxq = NULL;
 307         i40e_dev_tx_queue_release(pf->fdir.txq);
 308         pf->fdir.txq = NULL;
 309         i40e_vsi_release(vsi);
 310         pf->fdir.fdir_vsi = NULL;
 311 }
 312
 313 /* check whether the flow director table in empty */
 314 static inline int
 315 i40e_fdir_empty(struct i40e_hw *hw)
 316 {
 317         uint32_t guarant_cnt, best_cnt;
 318
 319         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 320                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 321                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 322         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 323                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 324                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 325         if (best_cnt + guarant_cnt > 0)
 326                 return -1;
 327
 328         return 0;
 329 }
 330
 331 /*
 332  * Initialize the configuration about bytes stream extracted as flexible payload
 333  * and mask setting
 334  */
 335 static inline void
 336 i40e_init_flx_pld(struct i40e_pf *pf)
 337 {
 338         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 339         uint8_t pctype;
 340         int i, index;
 341
 342         /*
 343          * Define the bytes stream extracted as flexible payload in
 344          * field vector. By default, select 8 words from the beginning
 345          * of payload as flexible payload.
 346          */
 347         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 348                 index = i * I40E_MAX_FLXPLD_FIED;
 349                 pf->fdir.flex_set[index].src_offset = 0;
 350                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 351                 pf->fdir.flex_set[index].dst_offset = 0;
 352                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 353                 I40E_WRITE_REG(hw,
 354                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 355                 I40E_WRITE_REG(hw,
 356                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 357         }
 358
 359         /* initialize the masks */
 360         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 361              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 362                 if (hw->mac.type == I40E_MAC_X722) {
 363                         if (!I40E_VALID_PCTYPE_X722(
 364                                  (enum i40e_filter_pctype)pctype))
 365                                 continue;
 366                 } else {
 367                         if (!I40E_VALID_PCTYPE(
 368                                  (enum i40e_filter_pctype)pctype))
 369                                 continue;
 370                 }
 371                 pf->fdir.flex_mask[pctype].word_mask = 0;
 372                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 373                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 374                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 375                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 376                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 377                 }
 378         }
 379 }
 380
 381 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 382
 383 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 384         if ((flex_pit2).src_offset < \
 385                 (flex_pit1).src_offset + (flex_pit1).size) { \
 386                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 387                         " less than than previous offset" \
 388                         " + previous FSIZE."); \
 389                 return -EINVAL; \
 390         } \
 391 } while (0)
 392
 393 /*
 394  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 395  * and the flex_pit will be sorted by it's src_offset value
 396  */
 397 static inline uint16_t
 398 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 399                         struct i40e_fdir_flex_pit *flex_pit)
 400 {
 401         uint16_t src_tmp, size, num = 0;
 402         uint16_t i, k, j = 0;
 403
 404         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 405                 size = 1;
 406                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 407                         if (src_offset[j + 1] == src_offset[j] + 1)
 408                                 size++;
 409                         else
 410                                 break;
 411                 }
 412                 src_tmp = src_offset[j] + 1 - size;
 413                 /* the flex_pit need to be sort by src_offset */
 414                 for (i = 0; i < num; i++) {
 415                         if (src_tmp < flex_pit[i].src_offset)
 416                                 break;
 417                 }
 418                 /* if insert required, move backward */
 419                 for (k = num; k > i; k--)
 420                         flex_pit[k] = flex_pit[k - 1];
 421                 /* insert */
 422                 flex_pit[i].dst_offset = j + 1 - size;
 423                 flex_pit[i].src_offset = src_tmp;
 424                 flex_pit[i].size = size;
 425                 j++;
 426                 num++;
 427         }
 428         return num;
 429 }
 430
 431 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 432 static inline int
 433 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 434 {
 435         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 436         uint16_t num, i;
 437
 438         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 439                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 440                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 441                         return -EINVAL;
 442                 }
 443         }
 444
 445         memset(flex_pit, 0, sizeof(flex_pit));
 446         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 447         if (num > I40E_MAX_FLXPLD_FIED) {
 448                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 449                 return -EINVAL;
 450         }
 451         for (i = 0; i < num; i++) {
 452                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 453                         flex_pit[i].src_offset & 0x01) {
 454                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 455                                 " in word");
 456                         return -EINVAL;
 457                 }
 458                 if (i != num - 1)
 459                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 460         }
 461         return 0;
 462 }
 463
 464 /*
 465  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 466  * arguments are valid
 467  */
 468 static int
 469 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 470 {
 471         const struct rte_eth_flex_payload_cfg *flex_cfg;
 472         const struct rte_eth_fdir_flex_mask *flex_mask;
 473         uint16_t mask_tmp;
 474         uint8_t nb_bitmask;
 475         uint16_t i, j;
 476         int ret = 0;
 477
 478         if (conf == NULL) {
 479                 PMD_DRV_LOG(INFO, "NULL pointer.");
 480                 return -EINVAL;
 481         }
 482         /* check flexible payload setting configuration */
 483         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 484                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 485                 return -EINVAL;
 486         }
 487         for (i = 0; i < conf->nb_payloads; i++) {
 488                 flex_cfg = &conf->flex_set[i];
 489                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 490                         PMD_DRV_LOG(ERR, "invalid payload type.");
 491                         return -EINVAL;
 492                 }
 493                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 494                 if (ret < 0) {
 495                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 496                         return -EINVAL;
 497                 }
 498         }
 499
 500         /* check flex mask setting configuration */
 501         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 502                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 503                 return -EINVAL;
 504         }
 505         for (i = 0; i < conf->nb_flexmasks; i++) {
 506                 flex_mask = &conf->flex_mask[i];
 507                 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
 508                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 509                         return -EINVAL;
 510                 }
 511                 nb_bitmask = 0;
 512                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 513                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 514                                              flex_mask->mask[j + 1]);
 515                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 516                                 nb_bitmask++;
 517                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 518                                         PMD_DRV_LOG(ERR, " exceed maximal"
 519                                                 " number of bitmasks.");
 520                                         return -EINVAL;
 521                                 }
 522                         }
 523                 }
 524         }
 525         return 0;
 526 }
 527
 528 /*
 529  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 530  * @pf: board private structure
 531  * @cfg: the rule how bytes stream is extracted as flexible payload
 532  */
 533 static void
 534 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 535                          const struct rte_eth_flex_payload_cfg *cfg)
 536 {
 537         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 538         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 539         uint32_t flx_pit;
 540         uint16_t num, min_next_off;  /* in words */
 541         uint8_t field_idx = 0;
 542         uint8_t layer_idx = 0;
 543         uint16_t i;
 544
 545         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 546                 layer_idx = I40E_FLXPLD_L2_IDX;
 547         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 548                 layer_idx = I40E_FLXPLD_L3_IDX;
 549         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 550                 layer_idx = I40E_FLXPLD_L4_IDX;
 551
 552         memset(flex_pit, 0, sizeof(flex_pit));
 553         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 554
 555         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 556                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 557                 /* record the info in fdir structure */
 558                 pf->fdir.flex_set[field_idx].src_offset =
 559                         flex_pit[i].src_offset / sizeof(uint16_t);
 560                 pf->fdir.flex_set[field_idx].size =
 561                         flex_pit[i].size / sizeof(uint16_t);
 562                 pf->fdir.flex_set[field_idx].dst_offset =
 563                         flex_pit[i].dst_offset / sizeof(uint16_t);
 564                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 565                                 pf->fdir.flex_set[field_idx].size,
 566                                 pf->fdir.flex_set[field_idx].dst_offset);
 567
 568                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 569         }
 570         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 571                                 pf->fdir.flex_set[field_idx].size;
 572
 573         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 574                 /* set the non-used register obeying register's constrain */
 575                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 576                            NONUSE_FLX_PIT_DEST_OFF);
 577                 I40E_WRITE_REG(hw,
 578                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 579                         flx_pit);
 580                 min_next_off++;
 581         }
 582 }
 583
 584 /*
 585  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 586  * @pf: board private structure
 587  * @pctype: packet classify type
 588  * @flex_masks: mask for flexible payload
 589  */
 590 static void
 591 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 592                 enum i40e_filter_pctype pctype,
 593                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 594 {
 595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 596         struct i40e_fdir_flex_mask *flex_mask;
 597         uint32_t flxinset, fd_mask;
 598         uint16_t mask_tmp;
 599         uint8_t i, nb_bitmask = 0;
 600
 601         flex_mask = &pf->fdir.flex_mask[pctype];
 602         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 603         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 604                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 605                 if (mask_tmp != 0x0) {
 606                         flex_mask->word_mask |=
 607                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 608                         if (mask_tmp != UINT16_MAX) {
 609                                 /* set bit mask */
 610                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 611                                 flex_mask->bitmask[nb_bitmask].offset =
 612                                         i / sizeof(uint16_t);
 613                                 nb_bitmask++;
 614                         }
 615                 }
 616         }
 617         /* write mask to hw */
 618         flxinset = (flex_mask->word_mask <<
 619                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 620                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 621         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 622
 623         for (i = 0; i < nb_bitmask; i++) {
 624                 fd_mask = (flex_mask->bitmask[i].mask <<
 625                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 626                         I40E_PRTQF_FD_MSK_MASK_MASK;
 627                 fd_mask |= ((flex_mask->bitmask[i].offset +
 628                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 629                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 630                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 631                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 632         }
 633 }
 634
 635 /*
 636  * Configure flow director related setting
 637  */
 638 int
 639 i40e_fdir_configure(struct rte_eth_dev *dev)
 640 {
 641         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 642         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 643         struct rte_eth_fdir_flex_conf *conf;
 644         enum i40e_filter_pctype pctype;
 645         uint32_t val;
 646         uint8_t i;
 647         int ret = 0;
 648
 649         /*
 650         * configuration need to be done before
 651         * flow director filters are added
 652         * If filters exist, flush them.
 653         */
 654         if (i40e_fdir_empty(hw) < 0) {
 655                 ret = i40e_fdir_flush(dev);
 656                 if (ret) {
 657                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 658                         return ret;
 659                 }
 660         }
 661
 662         /* enable FDIR filter */
 663         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 664         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 665         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 666
 667         i40e_init_flx_pld(pf); /* set flex config to default value */
 668
 669         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 670         ret = i40e_check_fdir_flex_conf(conf);
 671         if (ret < 0) {
 672                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 673                 return -EINVAL;
 674         }
 675         /* configure flex payload */
 676         for (i = 0; i < conf->nb_payloads; i++)
 677                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 678         /* configure flex mask*/
 679         for (i = 0; i < conf->nb_flexmasks; i++) {
 680                 if (hw->mac.type == I40E_MAC_X722) {
 681                         /* get translated pctype value in fd pctype register */
 682                         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
 683                                 hw, I40E_GLQF_FD_PCTYPES(
 684                                 (int)i40e_flowtype_to_pctype(
 685                                 conf->flex_mask[i].flow_type)));
 686                 } else
 687                         pctype = i40e_flowtype_to_pctype(
 688                                 conf->flex_mask[i].flow_type);
 689
 690                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 691         }
 692
 693         return ret;
 694 }
 695
 696 static inline int
 697 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 698                            unsigned char *raw_pkt,
 699                            bool vlan)
 700 {
 701         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 702         uint16_t *ether_type;
 703         uint8_t len = 2 * sizeof(struct ether_addr);
 704         struct ipv4_hdr *ip;
 705         struct ipv6_hdr *ip6;
 706         static const uint8_t next_proto[] = {
 707                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 708                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 709                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 710                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 711                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 712                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 713                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 714                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 715                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 716                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 717         };
 718
 719         raw_pkt += 2 * sizeof(struct ether_addr);
 720         if (vlan && fdir_input->flow_ext.vlan_tci) {
 721                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 722                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 723                            &fdir_input->flow_ext.vlan_tci,
 724                            sizeof(uint16_t));
 725                 raw_pkt += sizeof(vlan_frame);
 726                 len += sizeof(vlan_frame);
 727         }
 728         ether_type = (uint16_t *)raw_pkt;
 729         raw_pkt += sizeof(uint16_t);
 730         len += sizeof(uint16_t);
 731
 732         switch (fdir_input->flow_type) {
 733         case RTE_ETH_FLOW_L2_PAYLOAD:
 734                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 735                 break;
 736         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 737         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 738         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 739         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 740         case RTE_ETH_FLOW_FRAG_IPV4:
 741                 ip = (struct ipv4_hdr *)raw_pkt;
 742
 743                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 744                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 745                 /* set len to by default */
 746                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 747                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 748                                         fdir_input->flow.ip4_flow.proto :
 749                                         next_proto[fdir_input->flow_type];
 750                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 751                                         fdir_input->flow.ip4_flow.ttl :
 752                                         I40E_FDIR_IP_DEFAULT_TTL;
 753                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 754                 /*
 755                  * The source and destination fields in the transmitted packet
 756                  * need to be presented in a reversed order with respect
 757                  * to the expected received packets.
 758                  */
 759                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 760                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 761                 len += sizeof(struct ipv4_hdr);
 762                 break;
 763         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 764         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 765         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 766         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 767         case RTE_ETH_FLOW_FRAG_IPV6:
 768                 ip6 = (struct ipv6_hdr *)raw_pkt;
 769
 770                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 771                 ip6->vtc_flow =
 772                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 773                                          (fdir_input->flow.ipv6_flow.tc <<
 774                                           I40E_FDIR_IPv6_TC_OFFSET));
 775                 ip6->payload_len =
 776                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 777                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 778                                         fdir_input->flow.ipv6_flow.proto :
 779                                         next_proto[fdir_input->flow_type];
 780                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 781                                         fdir_input->flow.ipv6_flow.hop_limits :
 782                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 783                 /*
 784                  * The source and destination fields in the transmitted packet
 785                  * need to be presented in a reversed order with respect
 786                  * to the expected received packets.
 787                  */
 788                 rte_memcpy(&(ip6->src_addr),
 789                            &(fdir_input->flow.ipv6_flow.dst_ip),
 790                            IPV6_ADDR_LEN);
 791                 rte_memcpy(&(ip6->dst_addr),
 792                            &(fdir_input->flow.ipv6_flow.src_ip),
 793                            IPV6_ADDR_LEN);
 794                 len += sizeof(struct ipv6_hdr);
 795                 break;
 796         default:
 797                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 798                             fdir_input->flow_type);
 799                 return -1;
 800         }
 801         return len;
 802 }
 803
 804
 805 /*
 806  * i40e_fdir_construct_pkt - construct packet based on fields in input
 807  * @pf: board private structure
 808  * @fdir_input: input set of the flow director entry
 809  * @raw_pkt: a packet to be constructed
 810  */
 811 static int
 812 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 813                              const struct rte_eth_fdir_input *fdir_input,
 814                              unsigned char *raw_pkt)
 815 {
 816         unsigned char *payload, *ptr;
 817         struct udp_hdr *udp;
 818         struct tcp_hdr *tcp;
 819         struct sctp_hdr *sctp;
 820         uint8_t size, dst = 0;
 821         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 822         int len;
 823
 824         /* fill the ethernet and IP head */
 825         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 826                                          !!fdir_input->flow_ext.vlan_tci);
 827         if (len < 0)
 828                 return -EINVAL;
 829
 830         /* fill the L4 head */
 831         switch (fdir_input->flow_type) {
 832         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 833                 udp = (struct udp_hdr *)(raw_pkt + len);
 834                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 835                 /*
 836                  * The source and destination fields in the transmitted packet
 837                  * need to be presented in a reversed order with respect
 838                  * to the expected received packets.
 839                  */
 840                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 841                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 842                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 843                 break;
 844
 845         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 846                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 847                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 848                 /*
 849                  * The source and destination fields in the transmitted packet
 850                  * need to be presented in a reversed order with respect
 851                  * to the expected received packets.
 852                  */
 853                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 854                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 855                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 856                 break;
 857
 858         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 859                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 860                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 861                 /*
 862                  * The source and destination fields in the transmitted packet
 863                  * need to be presented in a reversed order with respect
 864                  * to the expected received packets.
 865                  */
 866                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 867                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 868                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 869                 break;
 870
 871         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 872         case RTE_ETH_FLOW_FRAG_IPV4:
 873                 payload = raw_pkt + len;
 874                 set_idx = I40E_FLXPLD_L3_IDX;
 875                 break;
 876
 877         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 878                 udp = (struct udp_hdr *)(raw_pkt + len);
 879                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 880                 /*
 881                  * The source and destination fields in the transmitted packet
 882                  * need to be presented in a reversed order with respect
 883                  * to the expected received packets.
 884                  */
 885                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 886                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 887                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 888                 break;
 889
 890         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 891                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 892                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 893                 /*
 894                  * The source and destination fields in the transmitted packet
 895                  * need to be presented in a reversed order with respect
 896                  * to the expected received packets.
 897                  */
 898                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 899                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 900                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 901                 break;
 902
 903         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 904                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 905                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 906                 /*
 907                  * The source and destination fields in the transmitted packet
 908                  * need to be presented in a reversed order with respect
 909                  * to the expected received packets.
 910                  */
 911                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 912                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 913                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 914                 break;
 915
 916         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 917         case RTE_ETH_FLOW_FRAG_IPV6:
 918                 payload = raw_pkt + len;
 919                 set_idx = I40E_FLXPLD_L3_IDX;
 920                 break;
 921         case RTE_ETH_FLOW_L2_PAYLOAD:
 922                 payload = raw_pkt + len;
 923                 /*
 924                  * ARP packet is a special case on which the payload
 925                  * starts after the whole ARP header
 926                  */
 927                 if (fdir_input->flow.l2_flow.ether_type ==
 928                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 929                         payload += sizeof(struct arp_hdr);
 930                 set_idx = I40E_FLXPLD_L2_IDX;
 931                 break;
 932         default:
 933                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 934                 return -EINVAL;
 935         }
 936
 937         /* fill the flexbytes to payload */
 938         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 939                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 940                 size = pf->fdir.flex_set[pit_idx].size;
 941                 if (size == 0)
 942                         continue;
 943                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 944                 ptr = payload +
 945                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 946                 (void)rte_memcpy(ptr,
 947                                  &fdir_input->flow_ext.flexbytes[dst],
 948                                  size * sizeof(uint16_t));
 949         }
 950
 951         return 0;
 952 }
 953
 954 /* Construct the tx flags */
 955 static inline uint64_t
 956 i40e_build_ctob(uint32_t td_cmd,
 957                 uint32_t td_offset,
 958                 unsigned int size,
 959                 uint32_t td_tag)
 960 {
 961         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 962                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 963                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 964                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 965                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 966 }
 967
 968 /*
 969  * check the programming status descriptor in rx queue.
 970  * done after Programming Flow Director is programmed on
 971  * tx queue
 972  */
 973 static inline int
 974 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 975 {
 976         volatile union i40e_rx_desc *rxdp;
 977         uint64_t qword1;
 978         uint32_t rx_status;
 979         uint32_t len, id;
 980         uint32_t error;
 981         int ret = 0;
 982
 983         rxdp = &rxq->rx_ring[rxq->rx_tail];
 984         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 985         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 986                         >> I40E_RXD_QW1_STATUS_SHIFT;
 987
 988         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 989                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 990                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 991                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 992
 993                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 994                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 995                         error = (qword1 &
 996                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 997                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 998                         if (error == (0x1 <<
 999                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1000                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1001                                             " (FD_ID %u): programming status"
1002                                             " reported.",
1003                                             rxdp->wb.qword0.hi_dword.fd_id);
1004                                 ret = -1;
1005                         } else if (error == (0x1 <<
1006                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1007                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1008                                             " (FD_ID %u): programming status"
1009                                             " reported.",
1010                                             rxdp->wb.qword0.hi_dword.fd_id);
1011                                 ret = -1;
1012                         } else
1013                                 PMD_DRV_LOG(ERR, "invalid programming status"
1014                                             " reported, error = %u.", error);
1015                 } else
1016                         PMD_DRV_LOG(ERR, "unknown programming status"
1017                                     " reported, len = %d, id = %u.", len, id);
1018                 rxdp->wb.qword1.status_error_len = 0;
1019                 rxq->rx_tail++;
1020                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1021                         rxq->rx_tail = 0;
1022         }
1023         return ret;
1024 }
1025
1026 static int
1027 i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
1028                          struct i40e_fdir_filter *filter)
1029 {
1030         rte_memcpy(&filter->fdir, input, sizeof(struct rte_eth_fdir_filter));
1031         return 0;
1032 }
1033
1034 /* Check if there exists the flow director filter */
1035 static struct i40e_fdir_filter *
1036 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1037                         const struct rte_eth_fdir_input *input)
1038 {
1039         int ret;
1040
1041         ret = rte_hash_lookup(fdir_info->hash_table, (const void *)input);
1042         if (ret < 0)
1043                 return NULL;
1044
1045         return fdir_info->hash_map[ret];
1046 }
1047
1048 /* Add a flow director filter into the SW list */
1049 static int
1050 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1051 {
1052         struct i40e_fdir_info *fdir_info = &pf->fdir;
1053         int ret;
1054
1055         ret = rte_hash_add_key(fdir_info->hash_table,
1056                                &filter->fdir.input);
1057         if (ret < 0) {
1058                 PMD_DRV_LOG(ERR,
1059                             "Failed to insert fdir filter to hash table %d!",
1060                             ret);
1061                 return ret;
1062         }
1063         fdir_info->hash_map[ret] = filter;
1064
1065         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1066
1067         return 0;
1068 }
1069
1070 /* Delete a flow director filter from the SW list */
1071 int
1072 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct rte_eth_fdir_input *input)
1073 {
1074         struct i40e_fdir_info *fdir_info = &pf->fdir;
1075         struct i40e_fdir_filter *filter;
1076         int ret;
1077
1078         ret = rte_hash_del_key(fdir_info->hash_table, input);
1079         if (ret < 0) {
1080                 PMD_DRV_LOG(ERR,
1081                             "Failed to delete fdir filter to hash table %d!",
1082                             ret);
1083                 return ret;
1084         }
1085         filter = fdir_info->hash_map[ret];
1086         fdir_info->hash_map[ret] = NULL;
1087
1088         TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1089         rte_free(filter);
1090
1091         return 0;
1092 }
1093
1094 /*
1095  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1096  * @pf: board private structure
1097  * @filter: fdir filter entry
1098  * @add: 0 - delete, 1 - add
1099  */
1100 int
1101 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1102                             const struct rte_eth_fdir_filter *filter,
1103                             bool add)
1104 {
1105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1106         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1107         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1108         enum i40e_filter_pctype pctype;
1109         struct i40e_fdir_info *fdir_info = &pf->fdir;
1110         struct i40e_fdir_filter *fdir_filter, *node;
1111         struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1112         int ret = 0;
1113
1114         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1115                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1116                         " check the mode in fdir_conf.");
1117                 return -ENOTSUP;
1118         }
1119
1120         if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1121                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1122                 return -EINVAL;
1123         }
1124         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1125                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1126                 return -EINVAL;
1127         }
1128         if (filter->input.flow_ext.is_vf &&
1129                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1130                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1131                 return -EINVAL;
1132         }
1133
1134         /* Check if there is the filter in SW list */
1135         memset(&check_filter, 0, sizeof(check_filter));
1136         i40e_fdir_filter_convert(filter, &check_filter);
1137         node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1138         if (add && node) {
1139                 PMD_DRV_LOG(ERR,
1140                             "Conflict with existing flow director rules!");
1141                 return -EINVAL;
1142         }
1143
1144         if (!add && !node) {
1145                 PMD_DRV_LOG(ERR,
1146                             "There's no corresponding flow firector filter!");
1147                 return -EINVAL;
1148         }
1149
1150         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1151
1152         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1153         if (ret < 0) {
1154                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1155                 return ret;
1156         }
1157
1158         if (hw->mac.type == I40E_MAC_X722) {
1159                 /* get translated pctype value in fd pctype register */
1160                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1161                         hw, I40E_GLQF_FD_PCTYPES(
1162                         (int)i40e_flowtype_to_pctype(
1163                         filter->input.flow_type)));
1164         } else
1165                 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1166
1167         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1168         if (ret < 0) {
1169                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1170                             pctype);
1171                 return ret;
1172         }
1173
1174         if (add) {
1175                 fdir_filter = rte_zmalloc("fdir_filter",
1176                                           sizeof(*fdir_filter), 0);
1177                 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1178                 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1179         } else {
1180                 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1181         }
1182
1183         return ret;
1184 }
1185
1186 /*
1187  * i40e_fdir_filter_programming - Program a flow director filter rule.
1188  * Is done by Flow Director Programming Descriptor followed by packet
1189  * structure that contains the filter fields need to match.
1190  * @pf: board private structure
1191  * @pctype: pctype
1192  * @filter: fdir filter entry
1193  * @add: 0 - delete, 1 - add
1194  */
1195 static int
1196 i40e_fdir_filter_programming(struct i40e_pf *pf,
1197                         enum i40e_filter_pctype pctype,
1198                         const struct rte_eth_fdir_filter *filter,
1199                         bool add)
1200 {
1201         struct i40e_tx_queue *txq = pf->fdir.txq;
1202         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1203         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1204         volatile struct i40e_tx_desc *txdp;
1205         volatile struct i40e_filter_program_desc *fdirdp;
1206         uint32_t td_cmd;
1207         uint16_t vsi_id, i;
1208         uint8_t dest;
1209
1210         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1211         fdirdp = (volatile struct i40e_filter_program_desc *)
1212                         (&(txq->tx_ring[txq->tx_tail]));
1213
1214         fdirdp->qindex_flex_ptype_vsi =
1215                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1216                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1217                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1218
1219         fdirdp->qindex_flex_ptype_vsi |=
1220                         rte_cpu_to_le_32((fdir_action->flex_off <<
1221                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1222                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1223
1224         fdirdp->qindex_flex_ptype_vsi |=
1225                         rte_cpu_to_le_32((pctype <<
1226                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1227                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1228
1229         if (filter->input.flow_ext.is_vf)
1230                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1231         else
1232                 /* Use LAN VSI Id by default */
1233                 vsi_id = pf->main_vsi->vsi_id;
1234         fdirdp->qindex_flex_ptype_vsi |=
1235                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1236                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1237                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1238
1239         fdirdp->dtype_cmd_cntindex =
1240                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1241
1242         if (add)
1243                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1244                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1245                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1246         else
1247                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1248                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1249                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1250
1251         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1252                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1253         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1254                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1255         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1256                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1257         else {
1258                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1259                             " unsupported fdir behavior.");
1260                 return -EINVAL;
1261         }
1262
1263         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1264                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1265                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1266
1267         fdirdp->dtype_cmd_cntindex |=
1268                 rte_cpu_to_le_32((fdir_action->report_status<<
1269                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1270                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1271
1272         fdirdp->dtype_cmd_cntindex |=
1273                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1274         fdirdp->dtype_cmd_cntindex |=
1275                         rte_cpu_to_le_32(
1276                         ((uint32_t)pf->fdir.match_counter_index <<
1277                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1278                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1279
1280         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1281
1282         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1283         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1284         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1285         td_cmd = I40E_TX_DESC_CMD_EOP |
1286                  I40E_TX_DESC_CMD_RS  |
1287                  I40E_TX_DESC_CMD_DUMMY;
1288
1289         txdp->cmd_type_offset_bsz =
1290                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1291
1292         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1293         if (txq->tx_tail >= txq->nb_tx_desc)
1294                 txq->tx_tail = 0;
1295         /* Update the tx tail register */
1296         rte_wmb();
1297         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1298
1299         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1300                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1301                 if ((txdp->cmd_type_offset_bsz &
1302                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1303                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1304                         break;
1305         }
1306         if (i >= I40E_FDIR_WAIT_COUNT) {
1307                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1308                             " time out to get DD on tx queue.");
1309                 return -ETIMEDOUT;
1310         }
1311         /* totally delay 10 ms to check programming status*/
1312         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1313         if (i40e_check_fdir_programming_status(rxq) < 0) {
1314                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1315                             " programming status reported.");
1316                 return -ENOSYS;
1317         }
1318
1319         return 0;
1320 }
1321
1322 /*
1323  * i40e_fdir_flush - clear all filters of Flow Director table
1324  * @pf: board private structure
1325  */
1326 int
1327 i40e_fdir_flush(struct rte_eth_dev *dev)
1328 {
1329         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1330         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1331         uint32_t reg;
1332         uint16_t guarant_cnt, best_cnt;
1333         uint16_t i;
1334
1335         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1336         I40E_WRITE_FLUSH(hw);
1337
1338         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1339                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1340                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1341                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1342                         break;
1343         }
1344         if (i >= I40E_FDIR_FLUSH_RETRY) {
1345                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1346                 return -ETIMEDOUT;
1347         }
1348         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1349                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1350                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1351         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1352                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1353                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1354         if (guarant_cnt != 0 || best_cnt != 0) {
1355                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1356                 return -ENOSYS;
1357         } else
1358                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1359         return 0;
1360 }
1361
1362 static inline void
1363 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1364                         struct rte_eth_flex_payload_cfg *flex_set,
1365                         uint16_t *num)
1366 {
1367         struct i40e_fdir_flex_pit *flex_pit;
1368         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1369         uint16_t src, dst, size, j, k;
1370         uint8_t i, layer_idx;
1371
1372         for (layer_idx = I40E_FLXPLD_L2_IDX;
1373              layer_idx <= I40E_FLXPLD_L4_IDX;
1374              layer_idx++) {
1375                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1376                         ptr->type = RTE_ETH_L2_PAYLOAD;
1377                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1378                         ptr->type = RTE_ETH_L3_PAYLOAD;
1379                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1380                         ptr->type = RTE_ETH_L4_PAYLOAD;
1381
1382                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1383                         flex_pit = &pf->fdir.flex_set[layer_idx *
1384                                 I40E_MAX_FLXPLD_FIED + i];
1385                         if (flex_pit->size == 0)
1386                                 continue;
1387                         src = flex_pit->src_offset * sizeof(uint16_t);
1388                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1389                         size = flex_pit->size * sizeof(uint16_t);
1390                         for (j = src, k = dst; j < src + size; j++, k++)
1391                                 ptr->src_offset[k] = j;
1392                 }
1393                 (*num)++;
1394                 ptr++;
1395         }
1396 }
1397
1398 static inline void
1399 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1400                         struct rte_eth_fdir_flex_mask *flex_mask,
1401                         uint16_t *num)
1402 {
1403         struct i40e_fdir_flex_mask *mask;
1404         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1405         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1406         uint16_t flow_type;
1407         uint8_t i, j;
1408         uint16_t off_bytes, mask_tmp;
1409
1410         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1411              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1412              i++) {
1413                 mask =  &pf->fdir.flex_mask[i];
1414                 if (hw->mac.type == I40E_MAC_X722) {
1415                         if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1416                                 continue;
1417                 } else {
1418                         if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1419                                 continue;
1420                 }
1421                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1422                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1423                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1424                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1425                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1426                         } else {
1427                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1428                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1429                         }
1430                 }
1431                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1432                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1433                         mask_tmp = ~mask->bitmask[j].mask;
1434                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1435                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1436                 }
1437                 ptr->flow_type = flow_type;
1438                 ptr++;
1439                 (*num)++;
1440         }
1441 }
1442
1443 /*
1444  * i40e_fdir_info_get - get information of Flow Director
1445  * @pf: ethernet device to get info from
1446  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1447  *    the flow director information.
1448  */
1449 static void
1450 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1451 {
1452         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1453         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1454         uint16_t num_flex_set = 0;
1455         uint16_t num_flex_mask = 0;
1456
1457         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1458                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1459         else
1460                 fdir->mode = RTE_FDIR_MODE_NONE;
1461
1462         fdir->guarant_spc =
1463                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1464         fdir->best_spc =
1465                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1466         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1467         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1468         fdir->flex_payload_unit = sizeof(uint16_t);
1469         fdir->flex_bitmask_unit = sizeof(uint16_t);
1470         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1471         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1472         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1473
1474         i40e_fdir_info_get_flex_set(pf,
1475                                 fdir->flex_conf.flex_set,
1476                                 &num_flex_set);
1477         i40e_fdir_info_get_flex_mask(pf,
1478                                 fdir->flex_conf.flex_mask,
1479                                 &num_flex_mask);
1480
1481         fdir->flex_conf.nb_payloads = num_flex_set;
1482         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1483 }
1484
1485 /*
1486  * i40e_fdir_stat_get - get statistics of Flow Director
1487  * @pf: ethernet device to get info from
1488  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1489  *    the flow director statistics.
1490  */
1491 static void
1492 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1493 {
1494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1496         uint32_t fdstat;
1497
1498         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1499         stat->guarant_cnt =
1500                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1501                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1502         stat->best_cnt =
1503                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1504                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1505 }
1506
1507 static int
1508 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1509                      struct rte_eth_fdir_filter_info *info)
1510 {
1511         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1512         int ret = 0;
1513
1514         if (!info) {
1515                 PMD_DRV_LOG(ERR, "Invalid pointer");
1516                 return -EFAULT;
1517         }
1518
1519         switch (info->info_type) {
1520         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1521                 ret = i40e_fdir_filter_inset_select(pf,
1522                                 &(info->info.input_set_conf));
1523                 break;
1524         default:
1525                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1526                             info->info_type);
1527                 return -EINVAL;
1528         }
1529
1530         return ret;
1531 }
1532
1533 /*
1534  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1535  * @pf: board private structure
1536  * @filter_op:operation will be taken.
1537  * @arg: a pointer to specific structure corresponding to the filter_op
1538  */
1539 int
1540 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1541                        enum rte_filter_op filter_op,
1542                        void *arg)
1543 {
1544         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1545         int ret = 0;
1546
1547         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1548                 return -ENOTSUP;
1549
1550         if (filter_op == RTE_ETH_FILTER_NOP)
1551                 return 0;
1552
1553         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1554                 return -EINVAL;
1555
1556         switch (filter_op) {
1557         case RTE_ETH_FILTER_ADD:
1558                 ret = i40e_add_del_fdir_filter(dev,
1559                         (struct rte_eth_fdir_filter *)arg,
1560                         TRUE);
1561                 break;
1562         case RTE_ETH_FILTER_DELETE:
1563                 ret = i40e_add_del_fdir_filter(dev,
1564                         (struct rte_eth_fdir_filter *)arg,
1565                         FALSE);
1566                 break;
1567         case RTE_ETH_FILTER_FLUSH:
1568                 ret = i40e_fdir_flush(dev);
1569                 break;
1570         case RTE_ETH_FILTER_INFO:
1571                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1572                 break;
1573         case RTE_ETH_FILTER_SET:
1574                 ret = i40e_fdir_filter_set(dev,
1575                         (struct rte_eth_fdir_filter_info *)arg);
1576                 break;
1577         case RTE_ETH_FILTER_STATS:
1578                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1579                 break;
1580         default:
1581                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1582                 ret = -EINVAL;
1583                 break;
1584         }
1585         return ret;
1586 }
1587
1588 /* Restore flow director filter */
1589 void
1590 i40e_fdir_filter_restore(struct i40e_pf *pf)
1591 {
1592         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
1593         struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
1594         struct i40e_fdir_filter *f;
1595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1596         uint32_t fdstat;
1597         uint32_t guarant_cnt;  /**< Number of filters in guaranteed spaces. */
1598         uint32_t best_cnt;     /**< Number of filters in best effort spaces. */
1599
1600         TAILQ_FOREACH(f, fdir_list, rules)
1601                 i40e_add_del_fdir_filter(dev, &f->fdir, TRUE);
1602
1603         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1604         guarant_cnt =
1605                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1606                            I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1607         best_cnt =
1608                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1609                            I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1610
1611         PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d,  Best count: %d",
1612                     guarant_cnt, best_cnt);
1613 }