drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_arp.h>
  48 #include <rte_ip.h>
  49 #include <rte_udp.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52
  53 #include "i40e_logs.h"
  54 #include "base/i40e_type.h"
  55 #include "base/i40e_prototype.h"
  56 #include "i40e_ethdev.h"
  57 #include "i40e_rxtx.h"
  58
  59 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  60 #ifndef IPV6_ADDR_LEN
  61 #define IPV6_ADDR_LEN              16
  62 #endif
  63
  64 #define I40E_FDIR_PKT_LEN                   512
  65 #define I40E_FDIR_IP_DEFAULT_LEN            420
  66 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  70 #define I40E_FDIR_IPv6_TC_OFFSET            20
  71
  72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  73 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  74 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  75
  76 /* Wait count and interval for fdir filter programming */
  77 #define I40E_FDIR_WAIT_COUNT       10
  78 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  79
  80 /* Wait count and interval for fdir filter flush */
  81 #define I40E_FDIR_FLUSH_RETRY       50
  82 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  83
  84 #define I40E_COUNTER_PF           2
  85 /* Statistic counter index for one pf */
  86 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  87 #define I40E_MAX_FLX_SOURCE_OFF           480
  88 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  89
  90 #define NONUSE_FLX_PIT_DEST_OFF 63
  91 #define NONUSE_FLX_PIT_FSIZE    1
  92 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  93         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  94                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  95         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  96                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  97         ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
  98                         NONUSE_FLX_PIT_DEST_OFF : \
  99                         ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
 100                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
 101                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
 102
 103 #define I40E_FDIR_FLOWS ( \
 104         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
 105         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 106         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 107         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 108         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 109         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
 110         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 111         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 112         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 113         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 114         (1 << RTE_ETH_FLOW_L2_PAYLOAD))
 115
 116 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 117
 118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 119                         enum i40e_filter_pctype pctype,
 120                         const struct rte_eth_fdir_filter *filter,
 121                         bool add);
 122 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 123
 124 static int
 125 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 126 {
 127         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 128         struct i40e_hmc_obj_rxq rx_ctx;
 129         int err = I40E_SUCCESS;
 130
 131         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 132         /* Init the RX queue in hardware */
 133         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 134         rx_ctx.hbuff = 0;
 135         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 136         rx_ctx.qlen = rxq->nb_rx_desc;
 137 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 138         rx_ctx.dsize = 1;
 139 #endif
 140         rx_ctx.dtype = i40e_header_split_none;
 141         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 142         rx_ctx.rxmax = ETHER_MAX_LEN;
 143         rx_ctx.tphrdesc_ena = 1;
 144         rx_ctx.tphwdesc_ena = 1;
 145         rx_ctx.tphdata_ena = 1;
 146         rx_ctx.tphhead_ena = 1;
 147         rx_ctx.lrxqthresh = 2;
 148         rx_ctx.crcstrip = 0;
 149         rx_ctx.l2tsel = 1;
 150         rx_ctx.showiv = 0;
 151         rx_ctx.prefena = 1;
 152
 153         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 154         if (err != I40E_SUCCESS) {
 155                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 156                 return err;
 157         }
 158         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 159         if (err != I40E_SUCCESS) {
 160                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 161                 return err;
 162         }
 163         rxq->qrx_tail = hw->hw_addr +
 164                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 165
 166         rte_wmb();
 167         /* Init the RX tail regieter. */
 168         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 169         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 170
 171         return err;
 172 }
 173
 174 /*
 175  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 176  * @pf: board private structure
 177  */
 178 int
 179 i40e_fdir_setup(struct i40e_pf *pf)
 180 {
 181         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 182         struct i40e_vsi *vsi;
 183         int err = I40E_SUCCESS;
 184         char z_name[RTE_MEMZONE_NAMESIZE];
 185         const struct rte_memzone *mz = NULL;
 186         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 187
 188         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 189                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 190                 return I40E_NOT_SUPPORTED;
 191         }
 192
 193         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 194                         " num_filters_best_effort = %u.",
 195                         hw->func_caps.fd_filters_guaranteed,
 196                         hw->func_caps.fd_filters_best_effort);
 197
 198         vsi = pf->fdir.fdir_vsi;
 199         if (vsi) {
 200                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 201                 return I40E_SUCCESS;
 202         }
 203         /* make new FDIR VSI */
 204         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 205         if (!vsi) {
 206                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 207                 return I40E_ERR_NO_AVAILABLE_VSI;
 208         }
 209         pf->fdir.fdir_vsi = vsi;
 210
 211         /*Fdir tx queue setup*/
 212         err = i40e_fdir_setup_tx_resources(pf);
 213         if (err) {
 214                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 215                 goto fail_setup_tx;
 216         }
 217
 218         /*Fdir rx queue setup*/
 219         err = i40e_fdir_setup_rx_resources(pf);
 220         if (err) {
 221                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 222                 goto fail_setup_rx;
 223         }
 224
 225         err = i40e_tx_queue_init(pf->fdir.txq);
 226         if (err) {
 227                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 228                 goto fail_mem;
 229         }
 230
 231         /* need switch on before dev start*/
 232         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 233         if (err) {
 234                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 235                 goto fail_mem;
 236         }
 237
 238         /* Init the rx queue in hardware */
 239         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 240         if (err) {
 241                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 242                 goto fail_mem;
 243         }
 244
 245         /* switch on rx queue */
 246         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 247         if (err) {
 248                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 249                 goto fail_mem;
 250         }
 251
 252         /* reserve memory for the fdir programming packet */
 253         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 254                         eth_dev->driver->pci_drv.driver.name,
 255                         I40E_FDIR_MZ_NAME,
 256                         eth_dev->data->port_id);
 257         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 258         if (!mz) {
 259                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 260                                  "flow director program packet.");
 261                 err = I40E_ERR_NO_MEMORY;
 262                 goto fail_mem;
 263         }
 264         pf->fdir.prg_pkt = mz->addr;
 265         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 266
 267         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 268         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 269                     vsi->base_queue);
 270         return I40E_SUCCESS;
 271
 272 fail_mem:
 273         i40e_dev_rx_queue_release(pf->fdir.rxq);
 274         pf->fdir.rxq = NULL;
 275 fail_setup_rx:
 276         i40e_dev_tx_queue_release(pf->fdir.txq);
 277         pf->fdir.txq = NULL;
 278 fail_setup_tx:
 279         i40e_vsi_release(vsi);
 280         pf->fdir.fdir_vsi = NULL;
 281         return err;
 282 }
 283
 284 /*
 285  * i40e_fdir_teardown - release the Flow Director resources
 286  * @pf: board private structure
 287  */
 288 void
 289 i40e_fdir_teardown(struct i40e_pf *pf)
 290 {
 291         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 292         struct i40e_vsi *vsi;
 293
 294         vsi = pf->fdir.fdir_vsi;
 295         if (!vsi)
 296                 return;
 297         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 298         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 299         i40e_dev_rx_queue_release(pf->fdir.rxq);
 300         pf->fdir.rxq = NULL;
 301         i40e_dev_tx_queue_release(pf->fdir.txq);
 302         pf->fdir.txq = NULL;
 303         i40e_vsi_release(vsi);
 304         pf->fdir.fdir_vsi = NULL;
 305 }
 306
 307 /* check whether the flow director table in empty */
 308 static inline int
 309 i40e_fdir_empty(struct i40e_hw *hw)
 310 {
 311         uint32_t guarant_cnt, best_cnt;
 312
 313         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 314                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 315                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 316         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 317                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 318                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 319         if (best_cnt + guarant_cnt > 0)
 320                 return -1;
 321
 322         return 0;
 323 }
 324
 325 /*
 326  * Initialize the configuration about bytes stream extracted as flexible payload
 327  * and mask setting
 328  */
 329 static inline void
 330 i40e_init_flx_pld(struct i40e_pf *pf)
 331 {
 332         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 333         uint8_t pctype;
 334         int i, index;
 335
 336         /*
 337          * Define the bytes stream extracted as flexible payload in
 338          * field vector. By default, select 8 words from the beginning
 339          * of payload as flexible payload.
 340          */
 341         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 342                 index = i * I40E_MAX_FLXPLD_FIED;
 343                 pf->fdir.flex_set[index].src_offset = 0;
 344                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 345                 pf->fdir.flex_set[index].dst_offset = 0;
 346                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 347                 I40E_WRITE_REG(hw,
 348                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 349                 I40E_WRITE_REG(hw,
 350                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 351         }
 352
 353         /* initialize the masks */
 354         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 355              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 356                 if (hw->mac.type == I40E_MAC_X722) {
 357                         if (!I40E_VALID_PCTYPE_X722(
 358                                  (enum i40e_filter_pctype)pctype))
 359                                 continue;
 360                 } else {
 361                         if (!I40E_VALID_PCTYPE(
 362                                  (enum i40e_filter_pctype)pctype))
 363                                 continue;
 364                 }
 365                 pf->fdir.flex_mask[pctype].word_mask = 0;
 366                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 367                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 368                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 369                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 370                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 371                 }
 372         }
 373 }
 374
 375 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 376
 377 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 378         if ((flex_pit2).src_offset < \
 379                 (flex_pit1).src_offset + (flex_pit1).size) { \
 380                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 381                         " less than than previous offset" \
 382                         " + previous FSIZE."); \
 383                 return -EINVAL; \
 384         } \
 385 } while (0)
 386
 387 /*
 388  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 389  * and the flex_pit will be sorted by it's src_offset value
 390  */
 391 static inline uint16_t
 392 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 393                         struct i40e_fdir_flex_pit *flex_pit)
 394 {
 395         uint16_t src_tmp, size, num = 0;
 396         uint16_t i, k, j = 0;
 397
 398         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 399                 size = 1;
 400                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 401                         if (src_offset[j + 1] == src_offset[j] + 1)
 402                                 size++;
 403                         else
 404                                 break;
 405                 }
 406                 src_tmp = src_offset[j] + 1 - size;
 407                 /* the flex_pit need to be sort by src_offset */
 408                 for (i = 0; i < num; i++) {
 409                         if (src_tmp < flex_pit[i].src_offset)
 410                                 break;
 411                 }
 412                 /* if insert required, move backward */
 413                 for (k = num; k > i; k--)
 414                         flex_pit[k] = flex_pit[k - 1];
 415                 /* insert */
 416                 flex_pit[i].dst_offset = j + 1 - size;
 417                 flex_pit[i].src_offset = src_tmp;
 418                 flex_pit[i].size = size;
 419                 j++;
 420                 num++;
 421         }
 422         return num;
 423 }
 424
 425 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 426 static inline int
 427 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 428 {
 429         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 430         uint16_t num, i;
 431
 432         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 433                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 434                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 435                         return -EINVAL;
 436                 }
 437         }
 438
 439         memset(flex_pit, 0, sizeof(flex_pit));
 440         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 441         if (num > I40E_MAX_FLXPLD_FIED) {
 442                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 443                 return -EINVAL;
 444         }
 445         for (i = 0; i < num; i++) {
 446                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 447                         flex_pit[i].src_offset & 0x01) {
 448                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 449                                 " in word");
 450                         return -EINVAL;
 451                 }
 452                 if (i != num - 1)
 453                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 454         }
 455         return 0;
 456 }
 457
 458 /*
 459  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 460  * arguments are valid
 461  */
 462 static int
 463 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 464 {
 465         const struct rte_eth_flex_payload_cfg *flex_cfg;
 466         const struct rte_eth_fdir_flex_mask *flex_mask;
 467         uint16_t mask_tmp;
 468         uint8_t nb_bitmask;
 469         uint16_t i, j;
 470         int ret = 0;
 471
 472         if (conf == NULL) {
 473                 PMD_DRV_LOG(INFO, "NULL pointer.");
 474                 return -EINVAL;
 475         }
 476         /* check flexible payload setting configuration */
 477         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 478                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 479                 return -EINVAL;
 480         }
 481         for (i = 0; i < conf->nb_payloads; i++) {
 482                 flex_cfg = &conf->flex_set[i];
 483                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 484                         PMD_DRV_LOG(ERR, "invalid payload type.");
 485                         return -EINVAL;
 486                 }
 487                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 488                 if (ret < 0) {
 489                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 490                         return -EINVAL;
 491                 }
 492         }
 493
 494         /* check flex mask setting configuration */
 495         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 496                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 497                 return -EINVAL;
 498         }
 499         for (i = 0; i < conf->nb_flexmasks; i++) {
 500                 flex_mask = &conf->flex_mask[i];
 501                 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
 502                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 503                         return -EINVAL;
 504                 }
 505                 nb_bitmask = 0;
 506                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 507                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 508                                              flex_mask->mask[j + 1]);
 509                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 510                                 nb_bitmask++;
 511                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 512                                         PMD_DRV_LOG(ERR, " exceed maximal"
 513                                                 " number of bitmasks.");
 514                                         return -EINVAL;
 515                                 }
 516                         }
 517                 }
 518         }
 519         return 0;
 520 }
 521
 522 /*
 523  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 524  * @pf: board private structure
 525  * @cfg: the rule how bytes stream is extracted as flexible payload
 526  */
 527 static void
 528 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 529                          const struct rte_eth_flex_payload_cfg *cfg)
 530 {
 531         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 532         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 533         uint32_t flx_pit;
 534         uint16_t num, min_next_off;  /* in words */
 535         uint8_t field_idx = 0;
 536         uint8_t layer_idx = 0;
 537         uint16_t i;
 538
 539         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 540                 layer_idx = I40E_FLXPLD_L2_IDX;
 541         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 542                 layer_idx = I40E_FLXPLD_L3_IDX;
 543         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 544                 layer_idx = I40E_FLXPLD_L4_IDX;
 545
 546         memset(flex_pit, 0, sizeof(flex_pit));
 547         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 548
 549         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 550                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 551                 /* record the info in fdir structure */
 552                 pf->fdir.flex_set[field_idx].src_offset =
 553                         flex_pit[i].src_offset / sizeof(uint16_t);
 554                 pf->fdir.flex_set[field_idx].size =
 555                         flex_pit[i].size / sizeof(uint16_t);
 556                 pf->fdir.flex_set[field_idx].dst_offset =
 557                         flex_pit[i].dst_offset / sizeof(uint16_t);
 558                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 559                                 pf->fdir.flex_set[field_idx].size,
 560                                 pf->fdir.flex_set[field_idx].dst_offset);
 561
 562                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 563         }
 564         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 565                                 pf->fdir.flex_set[field_idx].size;
 566
 567         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 568                 /* set the non-used register obeying register's constrain */
 569                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 570                            NONUSE_FLX_PIT_DEST_OFF);
 571                 I40E_WRITE_REG(hw,
 572                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 573                         flx_pit);
 574                 min_next_off++;
 575         }
 576 }
 577
 578 /*
 579  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 580  * @pf: board private structure
 581  * @pctype: packet classify type
 582  * @flex_masks: mask for flexible payload
 583  */
 584 static void
 585 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 586                 enum i40e_filter_pctype pctype,
 587                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 588 {
 589         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 590         struct i40e_fdir_flex_mask *flex_mask;
 591         uint32_t flxinset, fd_mask;
 592         uint16_t mask_tmp;
 593         uint8_t i, nb_bitmask = 0;
 594
 595         flex_mask = &pf->fdir.flex_mask[pctype];
 596         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 597         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 598                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 599                 if (mask_tmp != 0x0) {
 600                         flex_mask->word_mask |=
 601                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 602                         if (mask_tmp != UINT16_MAX) {
 603                                 /* set bit mask */
 604                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 605                                 flex_mask->bitmask[nb_bitmask].offset =
 606                                         i / sizeof(uint16_t);
 607                                 nb_bitmask++;
 608                         }
 609                 }
 610         }
 611         /* write mask to hw */
 612         flxinset = (flex_mask->word_mask <<
 613                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 614                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 615         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 616
 617         for (i = 0; i < nb_bitmask; i++) {
 618                 fd_mask = (flex_mask->bitmask[i].mask <<
 619                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 620                         I40E_PRTQF_FD_MSK_MASK_MASK;
 621                 fd_mask |= ((flex_mask->bitmask[i].offset +
 622                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 623                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 624                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 625                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 626         }
 627 }
 628
 629 /*
 630  * Configure flow director related setting
 631  */
 632 int
 633 i40e_fdir_configure(struct rte_eth_dev *dev)
 634 {
 635         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 637         struct rte_eth_fdir_flex_conf *conf;
 638         enum i40e_filter_pctype pctype;
 639         uint32_t val;
 640         uint8_t i;
 641         int ret = 0;
 642
 643         /*
 644         * configuration need to be done before
 645         * flow director filters are added
 646         * If filters exist, flush them.
 647         */
 648         if (i40e_fdir_empty(hw) < 0) {
 649                 ret = i40e_fdir_flush(dev);
 650                 if (ret) {
 651                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 652                         return ret;
 653                 }
 654         }
 655
 656         /* enable FDIR filter */
 657         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 658         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 659         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 660
 661         i40e_init_flx_pld(pf); /* set flex config to default value */
 662
 663         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 664         ret = i40e_check_fdir_flex_conf(conf);
 665         if (ret < 0) {
 666                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 667                 return -EINVAL;
 668         }
 669         /* configure flex payload */
 670         for (i = 0; i < conf->nb_payloads; i++)
 671                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 672         /* configure flex mask*/
 673         for (i = 0; i < conf->nb_flexmasks; i++) {
 674                 if (hw->mac.type == I40E_MAC_X722) {
 675                         /* get translated pctype value in fd pctype register */
 676                         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
 677                                 hw, I40E_GLQF_FD_PCTYPES(
 678                                 (int)i40e_flowtype_to_pctype(
 679                                 conf->flex_mask[i].flow_type)));
 680                 } else
 681                         pctype = i40e_flowtype_to_pctype(
 682                                 conf->flex_mask[i].flow_type);
 683
 684                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 685         }
 686
 687         return ret;
 688 }
 689
 690 static inline int
 691 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 692                            unsigned char *raw_pkt,
 693                            bool vlan)
 694 {
 695         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 696         uint16_t *ether_type;
 697         uint8_t len = 2 * sizeof(struct ether_addr);
 698         struct ipv4_hdr *ip;
 699         struct ipv6_hdr *ip6;
 700         static const uint8_t next_proto[] = {
 701                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 702                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 703                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 704                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 705                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 706                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 707                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 708                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 709                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 710                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 711         };
 712
 713         raw_pkt += 2 * sizeof(struct ether_addr);
 714         if (vlan && fdir_input->flow_ext.vlan_tci) {
 715                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 716                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 717                            &fdir_input->flow_ext.vlan_tci,
 718                            sizeof(uint16_t));
 719                 raw_pkt += sizeof(vlan_frame);
 720                 len += sizeof(vlan_frame);
 721         }
 722         ether_type = (uint16_t *)raw_pkt;
 723         raw_pkt += sizeof(uint16_t);
 724         len += sizeof(uint16_t);
 725
 726         switch (fdir_input->flow_type) {
 727         case RTE_ETH_FLOW_L2_PAYLOAD:
 728                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 729                 break;
 730         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 731         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 732         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 733         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 734         case RTE_ETH_FLOW_FRAG_IPV4:
 735                 ip = (struct ipv4_hdr *)raw_pkt;
 736
 737                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 738                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 739                 /* set len to by default */
 740                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 741                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 742                                         fdir_input->flow.ip4_flow.proto :
 743                                         next_proto[fdir_input->flow_type];
 744                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 745                                         fdir_input->flow.ip4_flow.ttl :
 746                                         I40E_FDIR_IP_DEFAULT_TTL;
 747                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 748                 /*
 749                  * The source and destination fields in the transmitted packet
 750                  * need to be presented in a reversed order with respect
 751                  * to the expected received packets.
 752                  */
 753                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 754                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 755                 len += sizeof(struct ipv4_hdr);
 756                 break;
 757         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 758         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 759         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 760         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 761         case RTE_ETH_FLOW_FRAG_IPV6:
 762                 ip6 = (struct ipv6_hdr *)raw_pkt;
 763
 764                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 765                 ip6->vtc_flow =
 766                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 767                                          (fdir_input->flow.ipv6_flow.tc <<
 768                                           I40E_FDIR_IPv6_TC_OFFSET));
 769                 ip6->payload_len =
 770                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 771                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 772                                         fdir_input->flow.ipv6_flow.proto :
 773                                         next_proto[fdir_input->flow_type];
 774                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 775                                         fdir_input->flow.ipv6_flow.hop_limits :
 776                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 777                 /*
 778                  * The source and destination fields in the transmitted packet
 779                  * need to be presented in a reversed order with respect
 780                  * to the expected received packets.
 781                  */
 782                 rte_memcpy(&(ip6->src_addr),
 783                            &(fdir_input->flow.ipv6_flow.dst_ip),
 784                            IPV6_ADDR_LEN);
 785                 rte_memcpy(&(ip6->dst_addr),
 786                            &(fdir_input->flow.ipv6_flow.src_ip),
 787                            IPV6_ADDR_LEN);
 788                 len += sizeof(struct ipv6_hdr);
 789                 break;
 790         default:
 791                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 792                             fdir_input->flow_type);
 793                 return -1;
 794         }
 795         return len;
 796 }
 797
 798
 799 /*
 800  * i40e_fdir_construct_pkt - construct packet based on fields in input
 801  * @pf: board private structure
 802  * @fdir_input: input set of the flow director entry
 803  * @raw_pkt: a packet to be constructed
 804  */
 805 static int
 806 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 807                              const struct rte_eth_fdir_input *fdir_input,
 808                              unsigned char *raw_pkt)
 809 {
 810         unsigned char *payload, *ptr;
 811         struct udp_hdr *udp;
 812         struct tcp_hdr *tcp;
 813         struct sctp_hdr *sctp;
 814         uint8_t size, dst = 0;
 815         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 816         int len;
 817
 818         /* fill the ethernet and IP head */
 819         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 820                                          !!fdir_input->flow_ext.vlan_tci);
 821         if (len < 0)
 822                 return -EINVAL;
 823
 824         /* fill the L4 head */
 825         switch (fdir_input->flow_type) {
 826         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 827                 udp = (struct udp_hdr *)(raw_pkt + len);
 828                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 829                 /*
 830                  * The source and destination fields in the transmitted packet
 831                  * need to be presented in a reversed order with respect
 832                  * to the expected received packets.
 833                  */
 834                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 835                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 836                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 837                 break;
 838
 839         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 840                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 841                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 842                 /*
 843                  * The source and destination fields in the transmitted packet
 844                  * need to be presented in a reversed order with respect
 845                  * to the expected received packets.
 846                  */
 847                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 848                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 849                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 850                 break;
 851
 852         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 853                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 854                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 855                 /*
 856                  * The source and destination fields in the transmitted packet
 857                  * need to be presented in a reversed order with respect
 858                  * to the expected received packets.
 859                  */
 860                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 861                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 862                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 863                 break;
 864
 865         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 866         case RTE_ETH_FLOW_FRAG_IPV4:
 867                 payload = raw_pkt + len;
 868                 set_idx = I40E_FLXPLD_L3_IDX;
 869                 break;
 870
 871         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 872                 udp = (struct udp_hdr *)(raw_pkt + len);
 873                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 874                 /*
 875                  * The source and destination fields in the transmitted packet
 876                  * need to be presented in a reversed order with respect
 877                  * to the expected received packets.
 878                  */
 879                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 880                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 881                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 882                 break;
 883
 884         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 885                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 886                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 887                 /*
 888                  * The source and destination fields in the transmitted packet
 889                  * need to be presented in a reversed order with respect
 890                  * to the expected received packets.
 891                  */
 892                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 893                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 894                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 895                 break;
 896
 897         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 898                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 899                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 900                 /*
 901                  * The source and destination fields in the transmitted packet
 902                  * need to be presented in a reversed order with respect
 903                  * to the expected received packets.
 904                  */
 905                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 906                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 907                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 908                 break;
 909
 910         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 911         case RTE_ETH_FLOW_FRAG_IPV6:
 912                 payload = raw_pkt + len;
 913                 set_idx = I40E_FLXPLD_L3_IDX;
 914                 break;
 915         case RTE_ETH_FLOW_L2_PAYLOAD:
 916                 payload = raw_pkt + len;
 917                 /*
 918                  * ARP packet is a special case on which the payload
 919                  * starts after the whole ARP header
 920                  */
 921                 if (fdir_input->flow.l2_flow.ether_type ==
 922                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 923                         payload += sizeof(struct arp_hdr);
 924                 set_idx = I40E_FLXPLD_L2_IDX;
 925                 break;
 926         default:
 927                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 928                 return -EINVAL;
 929         }
 930
 931         /* fill the flexbytes to payload */
 932         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 933                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 934                 size = pf->fdir.flex_set[pit_idx].size;
 935                 if (size == 0)
 936                         continue;
 937                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 938                 ptr = payload +
 939                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 940                 (void)rte_memcpy(ptr,
 941                                  &fdir_input->flow_ext.flexbytes[dst],
 942                                  size * sizeof(uint16_t));
 943         }
 944
 945         return 0;
 946 }
 947
 948 /* Construct the tx flags */
 949 static inline uint64_t
 950 i40e_build_ctob(uint32_t td_cmd,
 951                 uint32_t td_offset,
 952                 unsigned int size,
 953                 uint32_t td_tag)
 954 {
 955         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 956                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 957                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 958                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 959                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 960 }
 961
 962 /*
 963  * check the programming status descriptor in rx queue.
 964  * done after Programming Flow Director is programmed on
 965  * tx queue
 966  */
 967 static inline int
 968 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 969 {
 970         volatile union i40e_rx_desc *rxdp;
 971         uint64_t qword1;
 972         uint32_t rx_status;
 973         uint32_t len, id;
 974         uint32_t error;
 975         int ret = 0;
 976
 977         rxdp = &rxq->rx_ring[rxq->rx_tail];
 978         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 979         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 980                         >> I40E_RXD_QW1_STATUS_SHIFT;
 981
 982         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 983                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 984                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 985                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 986
 987                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 988                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 989                         error = (qword1 &
 990                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 991                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 992                         if (error == (0x1 <<
 993                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 994                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 995                                             " (FD_ID %u): programming status"
 996                                             " reported.",
 997                                             rxdp->wb.qword0.hi_dword.fd_id);
 998                                 ret = -1;
 999                         } else if (error == (0x1 <<
1000                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1001                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1002                                             " (FD_ID %u): programming status"
1003                                             " reported.",
1004                                             rxdp->wb.qword0.hi_dword.fd_id);
1005                                 ret = -1;
1006                         } else
1007                                 PMD_DRV_LOG(ERR, "invalid programming status"
1008                                             " reported, error = %u.", error);
1009                 } else
1010                         PMD_DRV_LOG(ERR, "unknown programming status"
1011                                     " reported, len = %d, id = %u.", len, id);
1012                 rxdp->wb.qword1.status_error_len = 0;
1013                 rxq->rx_tail++;
1014                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1015                         rxq->rx_tail = 0;
1016         }
1017         return ret;
1018 }
1019
1020 /*
1021  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1022  * @pf: board private structure
1023  * @filter: fdir filter entry
1024  * @add: 0 - delete, 1 - add
1025  */
1026 static int
1027 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1028                             const struct rte_eth_fdir_filter *filter,
1029                             bool add)
1030 {
1031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1033         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1034         enum i40e_filter_pctype pctype;
1035         int ret = 0;
1036
1037         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1038                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1039                         " check the mode in fdir_conf.");
1040                 return -ENOTSUP;
1041         }
1042
1043         if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1044                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1045                 return -EINVAL;
1046         }
1047         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1048                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1049                 return -EINVAL;
1050         }
1051         if (filter->input.flow_ext.is_vf &&
1052                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1053                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1054                 return -EINVAL;
1055         }
1056
1057         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1058
1059         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1060         if (ret < 0) {
1061                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1062                 return ret;
1063         }
1064
1065         if (hw->mac.type == I40E_MAC_X722) {
1066                 /* get translated pctype value in fd pctype register */
1067                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1068                         hw, I40E_GLQF_FD_PCTYPES(
1069                         (int)i40e_flowtype_to_pctype(
1070                         filter->input.flow_type)));
1071         } else
1072                 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1073
1074         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1075         if (ret < 0) {
1076                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1077                             pctype);
1078                 return ret;
1079         }
1080         return ret;
1081 }
1082
1083 /*
1084  * i40e_fdir_filter_programming - Program a flow director filter rule.
1085  * Is done by Flow Director Programming Descriptor followed by packet
1086  * structure that contains the filter fields need to match.
1087  * @pf: board private structure
1088  * @pctype: pctype
1089  * @filter: fdir filter entry
1090  * @add: 0 - delete, 1 - add
1091  */
1092 static int
1093 i40e_fdir_filter_programming(struct i40e_pf *pf,
1094                         enum i40e_filter_pctype pctype,
1095                         const struct rte_eth_fdir_filter *filter,
1096                         bool add)
1097 {
1098         struct i40e_tx_queue *txq = pf->fdir.txq;
1099         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1100         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1101         volatile struct i40e_tx_desc *txdp;
1102         volatile struct i40e_filter_program_desc *fdirdp;
1103         uint32_t td_cmd;
1104         uint16_t vsi_id, i;
1105         uint8_t dest;
1106
1107         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1108         fdirdp = (volatile struct i40e_filter_program_desc *)
1109                         (&(txq->tx_ring[txq->tx_tail]));
1110
1111         fdirdp->qindex_flex_ptype_vsi =
1112                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1113                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1114                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1115
1116         fdirdp->qindex_flex_ptype_vsi |=
1117                         rte_cpu_to_le_32((fdir_action->flex_off <<
1118                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1119                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1120
1121         fdirdp->qindex_flex_ptype_vsi |=
1122                         rte_cpu_to_le_32((pctype <<
1123                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1124                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1125
1126         if (filter->input.flow_ext.is_vf)
1127                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1128         else
1129                 /* Use LAN VSI Id by default */
1130                 vsi_id = pf->main_vsi->vsi_id;
1131         fdirdp->qindex_flex_ptype_vsi |=
1132                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1133                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1134                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1135
1136         fdirdp->dtype_cmd_cntindex =
1137                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1138
1139         if (add)
1140                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1141                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1142                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1143         else
1144                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1145                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1146                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1147
1148         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1149                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1150         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1151                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1152         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1153                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1154         else {
1155                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1156                             " unsupported fdir behavior.");
1157                 return -EINVAL;
1158         }
1159
1160         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1161                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1162                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1163
1164         fdirdp->dtype_cmd_cntindex |=
1165                 rte_cpu_to_le_32((fdir_action->report_status<<
1166                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1167                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1168
1169         fdirdp->dtype_cmd_cntindex |=
1170                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1171         fdirdp->dtype_cmd_cntindex |=
1172                         rte_cpu_to_le_32(
1173                         ((uint32_t)pf->fdir.match_counter_index <<
1174                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1175                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1176
1177         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1178
1179         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1180         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1181         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1182         td_cmd = I40E_TX_DESC_CMD_EOP |
1183                  I40E_TX_DESC_CMD_RS  |
1184                  I40E_TX_DESC_CMD_DUMMY;
1185
1186         txdp->cmd_type_offset_bsz =
1187                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1188
1189         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1190         if (txq->tx_tail >= txq->nb_tx_desc)
1191                 txq->tx_tail = 0;
1192         /* Update the tx tail register */
1193         rte_wmb();
1194         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1195
1196         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1197                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1198                 if ((txdp->cmd_type_offset_bsz &
1199                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1200                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1201                         break;
1202         }
1203         if (i >= I40E_FDIR_WAIT_COUNT) {
1204                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1205                             " time out to get DD on tx queue.");
1206                 return -ETIMEDOUT;
1207         }
1208         /* totally delay 10 ms to check programming status*/
1209         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1210         if (i40e_check_fdir_programming_status(rxq) < 0) {
1211                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1212                             " programming status reported.");
1213                 return -ENOSYS;
1214         }
1215
1216         return 0;
1217 }
1218
1219 /*
1220  * i40e_fdir_flush - clear all filters of Flow Director table
1221  * @pf: board private structure
1222  */
1223 static int
1224 i40e_fdir_flush(struct rte_eth_dev *dev)
1225 {
1226         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1227         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1228         uint32_t reg;
1229         uint16_t guarant_cnt, best_cnt;
1230         uint16_t i;
1231
1232         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1233         I40E_WRITE_FLUSH(hw);
1234
1235         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1236                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1237                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1238                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1239                         break;
1240         }
1241         if (i >= I40E_FDIR_FLUSH_RETRY) {
1242                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1243                 return -ETIMEDOUT;
1244         }
1245         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1246                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1247                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1248         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1249                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1250                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1251         if (guarant_cnt != 0 || best_cnt != 0) {
1252                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1253                 return -ENOSYS;
1254         } else
1255                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1256         return 0;
1257 }
1258
1259 static inline void
1260 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1261                         struct rte_eth_flex_payload_cfg *flex_set,
1262                         uint16_t *num)
1263 {
1264         struct i40e_fdir_flex_pit *flex_pit;
1265         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1266         uint16_t src, dst, size, j, k;
1267         uint8_t i, layer_idx;
1268
1269         for (layer_idx = I40E_FLXPLD_L2_IDX;
1270              layer_idx <= I40E_FLXPLD_L4_IDX;
1271              layer_idx++) {
1272                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1273                         ptr->type = RTE_ETH_L2_PAYLOAD;
1274                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1275                         ptr->type = RTE_ETH_L3_PAYLOAD;
1276                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1277                         ptr->type = RTE_ETH_L4_PAYLOAD;
1278
1279                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1280                         flex_pit = &pf->fdir.flex_set[layer_idx *
1281                                 I40E_MAX_FLXPLD_FIED + i];
1282                         if (flex_pit->size == 0)
1283                                 continue;
1284                         src = flex_pit->src_offset * sizeof(uint16_t);
1285                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1286                         size = flex_pit->size * sizeof(uint16_t);
1287                         for (j = src, k = dst; j < src + size; j++, k++)
1288                                 ptr->src_offset[k] = j;
1289                 }
1290                 (*num)++;
1291                 ptr++;
1292         }
1293 }
1294
1295 static inline void
1296 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1297                         struct rte_eth_fdir_flex_mask *flex_mask,
1298                         uint16_t *num)
1299 {
1300         struct i40e_fdir_flex_mask *mask;
1301         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1302         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1303         uint16_t flow_type;
1304         uint8_t i, j;
1305         uint16_t off_bytes, mask_tmp;
1306
1307         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1308              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1309              i++) {
1310                 mask =  &pf->fdir.flex_mask[i];
1311                 if (hw->mac.type == I40E_MAC_X722) {
1312                         if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1313                                 continue;
1314                 } else {
1315                         if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1316                                 continue;
1317                 }
1318                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1319                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1320                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1321                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1322                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1323                         } else {
1324                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1325                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1326                         }
1327                 }
1328                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1329                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1330                         mask_tmp = ~mask->bitmask[j].mask;
1331                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1332                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1333                 }
1334                 ptr->flow_type = flow_type;
1335                 ptr++;
1336                 (*num)++;
1337         }
1338 }
1339
1340 /*
1341  * i40e_fdir_info_get - get information of Flow Director
1342  * @pf: ethernet device to get info from
1343  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1344  *    the flow director information.
1345  */
1346 static void
1347 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1348 {
1349         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1350         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1351         uint16_t num_flex_set = 0;
1352         uint16_t num_flex_mask = 0;
1353
1354         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1355                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1356         else
1357                 fdir->mode = RTE_FDIR_MODE_NONE;
1358
1359         fdir->guarant_spc =
1360                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1361         fdir->best_spc =
1362                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1363         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1364         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1365         fdir->flex_payload_unit = sizeof(uint16_t);
1366         fdir->flex_bitmask_unit = sizeof(uint16_t);
1367         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1368         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1369         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1370
1371         i40e_fdir_info_get_flex_set(pf,
1372                                 fdir->flex_conf.flex_set,
1373                                 &num_flex_set);
1374         i40e_fdir_info_get_flex_mask(pf,
1375                                 fdir->flex_conf.flex_mask,
1376                                 &num_flex_mask);
1377
1378         fdir->flex_conf.nb_payloads = num_flex_set;
1379         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1380 }
1381
1382 /*
1383  * i40e_fdir_stat_get - get statistics of Flow Director
1384  * @pf: ethernet device to get info from
1385  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1386  *    the flow director statistics.
1387  */
1388 static void
1389 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1390 {
1391         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1392         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1393         uint32_t fdstat;
1394
1395         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1396         stat->guarant_cnt =
1397                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1398                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1399         stat->best_cnt =
1400                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1401                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1402 }
1403
1404 static int
1405 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1406                      struct rte_eth_fdir_filter_info *info)
1407 {
1408         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1409         int ret = 0;
1410
1411         if (!info) {
1412                 PMD_DRV_LOG(ERR, "Invalid pointer");
1413                 return -EFAULT;
1414         }
1415
1416         switch (info->info_type) {
1417         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1418                 ret = i40e_fdir_filter_inset_select(pf,
1419                                 &(info->info.input_set_conf));
1420                 break;
1421         default:
1422                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1423                             info->info_type);
1424                 return -EINVAL;
1425         }
1426
1427         return ret;
1428 }
1429
1430 /*
1431  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1432  * @pf: board private structure
1433  * @filter_op:operation will be taken.
1434  * @arg: a pointer to specific structure corresponding to the filter_op
1435  */
1436 int
1437 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1438                        enum rte_filter_op filter_op,
1439                        void *arg)
1440 {
1441         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1442         int ret = 0;
1443
1444         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1445                 return -ENOTSUP;
1446
1447         if (filter_op == RTE_ETH_FILTER_NOP)
1448                 return 0;
1449
1450         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1451                 return -EINVAL;
1452
1453         switch (filter_op) {
1454         case RTE_ETH_FILTER_ADD:
1455                 ret = i40e_add_del_fdir_filter(dev,
1456                         (struct rte_eth_fdir_filter *)arg,
1457                         TRUE);
1458                 break;
1459         case RTE_ETH_FILTER_DELETE:
1460                 ret = i40e_add_del_fdir_filter(dev,
1461                         (struct rte_eth_fdir_filter *)arg,
1462                         FALSE);
1463                 break;
1464         case RTE_ETH_FILTER_FLUSH:
1465                 ret = i40e_fdir_flush(dev);
1466                 break;
1467         case RTE_ETH_FILTER_INFO:
1468                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1469                 break;
1470         case RTE_ETH_FILTER_SET:
1471                 ret = i40e_fdir_filter_set(dev,
1472                         (struct rte_eth_fdir_filter_info *)arg);
1473                 break;
1474         case RTE_ETH_FILTER_STATS:
1475                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1476                 break;
1477         default:
1478                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1479                 ret = -EINVAL;
1480                 break;
1481         }
1482         return ret;
1483 }