drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_arp.h>
  48 #include <rte_ip.h>
  49 #include <rte_udp.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52
  53 #include "i40e_logs.h"
  54 #include "base/i40e_type.h"
  55 #include "base/i40e_prototype.h"
  56 #include "i40e_ethdev.h"
  57 #include "i40e_rxtx.h"
  58
  59 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  60 #ifndef IPV6_ADDR_LEN
  61 #define IPV6_ADDR_LEN              16
  62 #endif
  63
  64 #define I40E_FDIR_PKT_LEN                   512
  65 #define I40E_FDIR_IP_DEFAULT_LEN            420
  66 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  70 #define I40E_FDIR_IPv6_TC_OFFSET            20
  71
  72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  73 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  74 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  75
  76 /* Wait count and interval for fdir filter programming */
  77 #define I40E_FDIR_WAIT_COUNT       10
  78 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  79
  80 /* Wait count and interval for fdir filter flush */
  81 #define I40E_FDIR_FLUSH_RETRY       50
  82 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  83
  84 #define I40E_COUNTER_PF           2
  85 /* Statistic counter index for one pf */
  86 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  87 #define I40E_MAX_FLX_SOURCE_OFF           480
  88 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  89
  90 #define NONUSE_FLX_PIT_DEST_OFF 63
  91 #define NONUSE_FLX_PIT_FSIZE    1
  92 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  93         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  94                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  95         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  96                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  97         ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
  98                         NONUSE_FLX_PIT_DEST_OFF : \
  99                         ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
 100                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
 101                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
 102
 103 #define I40E_FDIR_FLOWS ( \
 104         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
 105         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 106         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 107         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 108         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 109         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
 110         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 111         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 112         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 113         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 114         (1 << RTE_ETH_FLOW_L2_PAYLOAD))
 115
 116 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 117
 118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 119                         enum i40e_filter_pctype pctype,
 120                         const struct rte_eth_fdir_filter *filter,
 121                         bool add);
 122 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 123
 124 static int
 125 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 126 {
 127         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 128         struct i40e_hmc_obj_rxq rx_ctx;
 129         int err = I40E_SUCCESS;
 130
 131         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 132         /* Init the RX queue in hardware */
 133         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 134         rx_ctx.hbuff = 0;
 135         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 136         rx_ctx.qlen = rxq->nb_rx_desc;
 137 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 138         rx_ctx.dsize = 1;
 139 #endif
 140         rx_ctx.dtype = i40e_header_split_none;
 141         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 142         rx_ctx.rxmax = ETHER_MAX_LEN;
 143         rx_ctx.tphrdesc_ena = 1;
 144         rx_ctx.tphwdesc_ena = 1;
 145         rx_ctx.tphdata_ena = 1;
 146         rx_ctx.tphhead_ena = 1;
 147         rx_ctx.lrxqthresh = 2;
 148         rx_ctx.crcstrip = 0;
 149         rx_ctx.l2tsel = 1;
 150         rx_ctx.showiv = 0;
 151         rx_ctx.prefena = 1;
 152
 153         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 154         if (err != I40E_SUCCESS) {
 155                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 156                 return err;
 157         }
 158         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 159         if (err != I40E_SUCCESS) {
 160                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 161                 return err;
 162         }
 163         rxq->qrx_tail = hw->hw_addr +
 164                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 165
 166         rte_wmb();
 167         /* Init the RX tail regieter. */
 168         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 169
 170         return err;
 171 }
 172
 173 /*
 174  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 175  * @pf: board private structure
 176  */
 177 int
 178 i40e_fdir_setup(struct i40e_pf *pf)
 179 {
 180         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 181         struct i40e_vsi *vsi;
 182         int err = I40E_SUCCESS;
 183         char z_name[RTE_MEMZONE_NAMESIZE];
 184         const struct rte_memzone *mz = NULL;
 185         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 186
 187         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 188                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 189                 return I40E_NOT_SUPPORTED;
 190         }
 191
 192         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 193                         " num_filters_best_effort = %u.",
 194                         hw->func_caps.fd_filters_guaranteed,
 195                         hw->func_caps.fd_filters_best_effort);
 196
 197         vsi = pf->fdir.fdir_vsi;
 198         if (vsi) {
 199                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 200                 return I40E_SUCCESS;
 201         }
 202         /* make new FDIR VSI */
 203         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 204         if (!vsi) {
 205                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 206                 return I40E_ERR_NO_AVAILABLE_VSI;
 207         }
 208         pf->fdir.fdir_vsi = vsi;
 209
 210         /*Fdir tx queue setup*/
 211         err = i40e_fdir_setup_tx_resources(pf);
 212         if (err) {
 213                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 214                 goto fail_setup_tx;
 215         }
 216
 217         /*Fdir rx queue setup*/
 218         err = i40e_fdir_setup_rx_resources(pf);
 219         if (err) {
 220                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 221                 goto fail_setup_rx;
 222         }
 223
 224         err = i40e_tx_queue_init(pf->fdir.txq);
 225         if (err) {
 226                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 227                 goto fail_mem;
 228         }
 229
 230         /* need switch on before dev start*/
 231         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 232         if (err) {
 233                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 234                 goto fail_mem;
 235         }
 236
 237         /* Init the rx queue in hardware */
 238         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 239         if (err) {
 240                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 241                 goto fail_mem;
 242         }
 243
 244         /* switch on rx queue */
 245         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 246         if (err) {
 247                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 248                 goto fail_mem;
 249         }
 250
 251         /* reserve memory for the fdir programming packet */
 252         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 253                         eth_dev->driver->pci_drv.driver.name,
 254                         I40E_FDIR_MZ_NAME,
 255                         eth_dev->data->port_id);
 256         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 257         if (!mz) {
 258                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 259                                  "flow director program packet.");
 260                 err = I40E_ERR_NO_MEMORY;
 261                 goto fail_mem;
 262         }
 263         pf->fdir.prg_pkt = mz->addr;
 264         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 265
 266         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 267         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 268                     vsi->base_queue);
 269         return I40E_SUCCESS;
 270
 271 fail_mem:
 272         i40e_dev_rx_queue_release(pf->fdir.rxq);
 273         pf->fdir.rxq = NULL;
 274 fail_setup_rx:
 275         i40e_dev_tx_queue_release(pf->fdir.txq);
 276         pf->fdir.txq = NULL;
 277 fail_setup_tx:
 278         i40e_vsi_release(vsi);
 279         pf->fdir.fdir_vsi = NULL;
 280         return err;
 281 }
 282
 283 /*
 284  * i40e_fdir_teardown - release the Flow Director resources
 285  * @pf: board private structure
 286  */
 287 void
 288 i40e_fdir_teardown(struct i40e_pf *pf)
 289 {
 290         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 291         struct i40e_vsi *vsi;
 292
 293         vsi = pf->fdir.fdir_vsi;
 294         if (!vsi)
 295                 return;
 296         int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 297         if (err)
 298                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
 299         err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 300         if (err)
 301                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
 302         i40e_dev_rx_queue_release(pf->fdir.rxq);
 303         pf->fdir.rxq = NULL;
 304         i40e_dev_tx_queue_release(pf->fdir.txq);
 305         pf->fdir.txq = NULL;
 306         i40e_vsi_release(vsi);
 307         pf->fdir.fdir_vsi = NULL;
 308 }
 309
 310 /* check whether the flow director table in empty */
 311 static inline int
 312 i40e_fdir_empty(struct i40e_hw *hw)
 313 {
 314         uint32_t guarant_cnt, best_cnt;
 315
 316         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 317                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 318                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 319         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 320                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 321                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 322         if (best_cnt + guarant_cnt > 0)
 323                 return -1;
 324
 325         return 0;
 326 }
 327
 328 /*
 329  * Initialize the configuration about bytes stream extracted as flexible payload
 330  * and mask setting
 331  */
 332 static inline void
 333 i40e_init_flx_pld(struct i40e_pf *pf)
 334 {
 335         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 336         uint8_t pctype;
 337         int i, index;
 338
 339         /*
 340          * Define the bytes stream extracted as flexible payload in
 341          * field vector. By default, select 8 words from the beginning
 342          * of payload as flexible payload.
 343          */
 344         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 345                 index = i * I40E_MAX_FLXPLD_FIED;
 346                 pf->fdir.flex_set[index].src_offset = 0;
 347                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 348                 pf->fdir.flex_set[index].dst_offset = 0;
 349                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 350                 I40E_WRITE_REG(hw,
 351                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 352                 I40E_WRITE_REG(hw,
 353                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 354         }
 355
 356         /* initialize the masks */
 357         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 358              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 359                 if (hw->mac.type == I40E_MAC_X722) {
 360                         if (!I40E_VALID_PCTYPE_X722(
 361                                  (enum i40e_filter_pctype)pctype))
 362                                 continue;
 363                 } else {
 364                         if (!I40E_VALID_PCTYPE(
 365                                  (enum i40e_filter_pctype)pctype))
 366                                 continue;
 367                 }
 368                 pf->fdir.flex_mask[pctype].word_mask = 0;
 369                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 370                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 371                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 372                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 373                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 374                 }
 375         }
 376 }
 377
 378 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 379
 380 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 381         if ((flex_pit2).src_offset < \
 382                 (flex_pit1).src_offset + (flex_pit1).size) { \
 383                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 384                         " less than than previous offset" \
 385                         " + previous FSIZE."); \
 386                 return -EINVAL; \
 387         } \
 388 } while (0)
 389
 390 /*
 391  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 392  * and the flex_pit will be sorted by it's src_offset value
 393  */
 394 static inline uint16_t
 395 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 396                         struct i40e_fdir_flex_pit *flex_pit)
 397 {
 398         uint16_t src_tmp, size, num = 0;
 399         uint16_t i, k, j = 0;
 400
 401         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 402                 size = 1;
 403                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 404                         if (src_offset[j + 1] == src_offset[j] + 1)
 405                                 size++;
 406                         else
 407                                 break;
 408                 }
 409                 src_tmp = src_offset[j] + 1 - size;
 410                 /* the flex_pit need to be sort by src_offset */
 411                 for (i = 0; i < num; i++) {
 412                         if (src_tmp < flex_pit[i].src_offset)
 413                                 break;
 414                 }
 415                 /* if insert required, move backward */
 416                 for (k = num; k > i; k--)
 417                         flex_pit[k] = flex_pit[k - 1];
 418                 /* insert */
 419                 flex_pit[i].dst_offset = j + 1 - size;
 420                 flex_pit[i].src_offset = src_tmp;
 421                 flex_pit[i].size = size;
 422                 j++;
 423                 num++;
 424         }
 425         return num;
 426 }
 427
 428 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 429 static inline int
 430 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 431 {
 432         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 433         uint16_t num, i;
 434
 435         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 436                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 437                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 438                         return -EINVAL;
 439                 }
 440         }
 441
 442         memset(flex_pit, 0, sizeof(flex_pit));
 443         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 444         if (num > I40E_MAX_FLXPLD_FIED) {
 445                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 446                 return -EINVAL;
 447         }
 448         for (i = 0; i < num; i++) {
 449                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 450                         flex_pit[i].src_offset & 0x01) {
 451                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 452                                 " in word");
 453                         return -EINVAL;
 454                 }
 455                 if (i != num - 1)
 456                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 457         }
 458         return 0;
 459 }
 460
 461 /*
 462  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 463  * arguments are valid
 464  */
 465 static int
 466 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 467 {
 468         const struct rte_eth_flex_payload_cfg *flex_cfg;
 469         const struct rte_eth_fdir_flex_mask *flex_mask;
 470         uint16_t mask_tmp;
 471         uint8_t nb_bitmask;
 472         uint16_t i, j;
 473         int ret = 0;
 474
 475         if (conf == NULL) {
 476                 PMD_DRV_LOG(INFO, "NULL pointer.");
 477                 return -EINVAL;
 478         }
 479         /* check flexible payload setting configuration */
 480         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 481                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 482                 return -EINVAL;
 483         }
 484         for (i = 0; i < conf->nb_payloads; i++) {
 485                 flex_cfg = &conf->flex_set[i];
 486                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 487                         PMD_DRV_LOG(ERR, "invalid payload type.");
 488                         return -EINVAL;
 489                 }
 490                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 491                 if (ret < 0) {
 492                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 493                         return -EINVAL;
 494                 }
 495         }
 496
 497         /* check flex mask setting configuration */
 498         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 499                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 500                 return -EINVAL;
 501         }
 502         for (i = 0; i < conf->nb_flexmasks; i++) {
 503                 flex_mask = &conf->flex_mask[i];
 504                 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
 505                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 506                         return -EINVAL;
 507                 }
 508                 nb_bitmask = 0;
 509                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 510                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 511                                              flex_mask->mask[j + 1]);
 512                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 513                                 nb_bitmask++;
 514                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 515                                         PMD_DRV_LOG(ERR, " exceed maximal"
 516                                                 " number of bitmasks.");
 517                                         return -EINVAL;
 518                                 }
 519                         }
 520                 }
 521         }
 522         return 0;
 523 }
 524
 525 /*
 526  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 527  * @pf: board private structure
 528  * @cfg: the rule how bytes stream is extracted as flexible payload
 529  */
 530 static void
 531 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 532                          const struct rte_eth_flex_payload_cfg *cfg)
 533 {
 534         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 535         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 536         uint32_t flx_pit;
 537         uint16_t num, min_next_off;  /* in words */
 538         uint8_t field_idx = 0;
 539         uint8_t layer_idx = 0;
 540         uint16_t i;
 541
 542         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 543                 layer_idx = I40E_FLXPLD_L2_IDX;
 544         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 545                 layer_idx = I40E_FLXPLD_L3_IDX;
 546         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 547                 layer_idx = I40E_FLXPLD_L4_IDX;
 548
 549         memset(flex_pit, 0, sizeof(flex_pit));
 550         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 551
 552         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 553                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 554                 /* record the info in fdir structure */
 555                 pf->fdir.flex_set[field_idx].src_offset =
 556                         flex_pit[i].src_offset / sizeof(uint16_t);
 557                 pf->fdir.flex_set[field_idx].size =
 558                         flex_pit[i].size / sizeof(uint16_t);
 559                 pf->fdir.flex_set[field_idx].dst_offset =
 560                         flex_pit[i].dst_offset / sizeof(uint16_t);
 561                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 562                                 pf->fdir.flex_set[field_idx].size,
 563                                 pf->fdir.flex_set[field_idx].dst_offset);
 564
 565                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 566         }
 567         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 568                                 pf->fdir.flex_set[field_idx].size;
 569
 570         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 571                 /* set the non-used register obeying register's constrain */
 572                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 573                            NONUSE_FLX_PIT_DEST_OFF);
 574                 I40E_WRITE_REG(hw,
 575                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 576                         flx_pit);
 577                 min_next_off++;
 578         }
 579 }
 580
 581 /*
 582  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 583  * @pf: board private structure
 584  * @pctype: packet classify type
 585  * @flex_masks: mask for flexible payload
 586  */
 587 static void
 588 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 589                 enum i40e_filter_pctype pctype,
 590                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 591 {
 592         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 593         struct i40e_fdir_flex_mask *flex_mask;
 594         uint32_t flxinset, fd_mask;
 595         uint16_t mask_tmp;
 596         uint8_t i, nb_bitmask = 0;
 597
 598         flex_mask = &pf->fdir.flex_mask[pctype];
 599         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 600         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 601                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 602                 if (mask_tmp != 0x0) {
 603                         flex_mask->word_mask |=
 604                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 605                         if (mask_tmp != UINT16_MAX) {
 606                                 /* set bit mask */
 607                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 608                                 flex_mask->bitmask[nb_bitmask].offset =
 609                                         i / sizeof(uint16_t);
 610                                 nb_bitmask++;
 611                         }
 612                 }
 613         }
 614         /* write mask to hw */
 615         flxinset = (flex_mask->word_mask <<
 616                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 617                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 618         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 619
 620         for (i = 0; i < nb_bitmask; i++) {
 621                 fd_mask = (flex_mask->bitmask[i].mask <<
 622                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 623                         I40E_PRTQF_FD_MSK_MASK_MASK;
 624                 fd_mask |= ((flex_mask->bitmask[i].offset +
 625                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 626                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 627                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 628                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 629         }
 630 }
 631
 632 /*
 633  * Configure flow director related setting
 634  */
 635 int
 636 i40e_fdir_configure(struct rte_eth_dev *dev)
 637 {
 638         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640         struct rte_eth_fdir_flex_conf *conf;
 641         enum i40e_filter_pctype pctype;
 642         uint32_t val;
 643         uint8_t i;
 644         int ret = 0;
 645
 646         /*
 647         * configuration need to be done before
 648         * flow director filters are added
 649         * If filters exist, flush them.
 650         */
 651         if (i40e_fdir_empty(hw) < 0) {
 652                 ret = i40e_fdir_flush(dev);
 653                 if (ret) {
 654                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 655                         return ret;
 656                 }
 657         }
 658
 659         /* enable FDIR filter */
 660         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 661         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 662         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 663
 664         i40e_init_flx_pld(pf); /* set flex config to default value */
 665
 666         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 667         ret = i40e_check_fdir_flex_conf(conf);
 668         if (ret < 0) {
 669                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 670                 return -EINVAL;
 671         }
 672         /* configure flex payload */
 673         for (i = 0; i < conf->nb_payloads; i++)
 674                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 675         /* configure flex mask*/
 676         for (i = 0; i < conf->nb_flexmasks; i++) {
 677                 if (hw->mac.type == I40E_MAC_X722) {
 678                         /* get translated pctype value in fd pctype register */
 679                         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
 680                                 hw, I40E_GLQF_FD_PCTYPES(
 681                                 (int)i40e_flowtype_to_pctype(
 682                                 conf->flex_mask[i].flow_type)));
 683                 } else
 684                         pctype = i40e_flowtype_to_pctype(
 685                                 conf->flex_mask[i].flow_type);
 686
 687                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 688         }
 689
 690         return ret;
 691 }
 692
 693 static inline int
 694 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 695                            unsigned char *raw_pkt,
 696                            bool vlan)
 697 {
 698         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 699         uint16_t *ether_type;
 700         uint8_t len = 2 * sizeof(struct ether_addr);
 701         struct ipv4_hdr *ip;
 702         struct ipv6_hdr *ip6;
 703         static const uint8_t next_proto[] = {
 704                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 705                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 706                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 707                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 708                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 709                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 710                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 711                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 712                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 713                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 714         };
 715
 716         raw_pkt += 2 * sizeof(struct ether_addr);
 717         if (vlan && fdir_input->flow_ext.vlan_tci) {
 718                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 719                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 720                            &fdir_input->flow_ext.vlan_tci,
 721                            sizeof(uint16_t));
 722                 raw_pkt += sizeof(vlan_frame);
 723                 len += sizeof(vlan_frame);
 724         }
 725         ether_type = (uint16_t *)raw_pkt;
 726         raw_pkt += sizeof(uint16_t);
 727         len += sizeof(uint16_t);
 728
 729         switch (fdir_input->flow_type) {
 730         case RTE_ETH_FLOW_L2_PAYLOAD:
 731                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 732                 break;
 733         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 734         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 735         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 736         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 737         case RTE_ETH_FLOW_FRAG_IPV4:
 738                 ip = (struct ipv4_hdr *)raw_pkt;
 739
 740                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 741                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 742                 /* set len to by default */
 743                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 744                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 745                                         fdir_input->flow.ip4_flow.proto :
 746                                         next_proto[fdir_input->flow_type];
 747                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 748                                         fdir_input->flow.ip4_flow.ttl :
 749                                         I40E_FDIR_IP_DEFAULT_TTL;
 750                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 751                 /*
 752                  * The source and destination fields in the transmitted packet
 753                  * need to be presented in a reversed order with respect
 754                  * to the expected received packets.
 755                  */
 756                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 757                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 758                 len += sizeof(struct ipv4_hdr);
 759                 break;
 760         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 761         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 762         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 763         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 764         case RTE_ETH_FLOW_FRAG_IPV6:
 765                 ip6 = (struct ipv6_hdr *)raw_pkt;
 766
 767                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 768                 ip6->vtc_flow =
 769                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 770                                          (fdir_input->flow.ipv6_flow.tc <<
 771                                           I40E_FDIR_IPv6_TC_OFFSET));
 772                 ip6->payload_len =
 773                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 774                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 775                                         fdir_input->flow.ipv6_flow.proto :
 776                                         next_proto[fdir_input->flow_type];
 777                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 778                                         fdir_input->flow.ipv6_flow.hop_limits :
 779                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 780                 /*
 781                  * The source and destination fields in the transmitted packet
 782                  * need to be presented in a reversed order with respect
 783                  * to the expected received packets.
 784                  */
 785                 rte_memcpy(&(ip6->src_addr),
 786                            &(fdir_input->flow.ipv6_flow.dst_ip),
 787                            IPV6_ADDR_LEN);
 788                 rte_memcpy(&(ip6->dst_addr),
 789                            &(fdir_input->flow.ipv6_flow.src_ip),
 790                            IPV6_ADDR_LEN);
 791                 len += sizeof(struct ipv6_hdr);
 792                 break;
 793         default:
 794                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 795                             fdir_input->flow_type);
 796                 return -1;
 797         }
 798         return len;
 799 }
 800
 801
 802 /*
 803  * i40e_fdir_construct_pkt - construct packet based on fields in input
 804  * @pf: board private structure
 805  * @fdir_input: input set of the flow director entry
 806  * @raw_pkt: a packet to be constructed
 807  */
 808 static int
 809 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 810                              const struct rte_eth_fdir_input *fdir_input,
 811                              unsigned char *raw_pkt)
 812 {
 813         unsigned char *payload, *ptr;
 814         struct udp_hdr *udp;
 815         struct tcp_hdr *tcp;
 816         struct sctp_hdr *sctp;
 817         uint8_t size, dst = 0;
 818         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 819         int len;
 820
 821         /* fill the ethernet and IP head */
 822         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 823                                          !!fdir_input->flow_ext.vlan_tci);
 824         if (len < 0)
 825                 return -EINVAL;
 826
 827         /* fill the L4 head */
 828         switch (fdir_input->flow_type) {
 829         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 830                 udp = (struct udp_hdr *)(raw_pkt + len);
 831                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 832                 /*
 833                  * The source and destination fields in the transmitted packet
 834                  * need to be presented in a reversed order with respect
 835                  * to the expected received packets.
 836                  */
 837                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 838                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 839                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 840                 break;
 841
 842         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 843                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 844                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 845                 /*
 846                  * The source and destination fields in the transmitted packet
 847                  * need to be presented in a reversed order with respect
 848                  * to the expected received packets.
 849                  */
 850                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 851                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 852                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 853                 break;
 854
 855         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 856                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 857                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 858                 /*
 859                  * The source and destination fields in the transmitted packet
 860                  * need to be presented in a reversed order with respect
 861                  * to the expected received packets.
 862                  */
 863                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 864                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 865                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 866                 break;
 867
 868         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 869         case RTE_ETH_FLOW_FRAG_IPV4:
 870                 payload = raw_pkt + len;
 871                 set_idx = I40E_FLXPLD_L3_IDX;
 872                 break;
 873
 874         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 875                 udp = (struct udp_hdr *)(raw_pkt + len);
 876                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 877                 /*
 878                  * The source and destination fields in the transmitted packet
 879                  * need to be presented in a reversed order with respect
 880                  * to the expected received packets.
 881                  */
 882                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 883                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 884                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 885                 break;
 886
 887         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 888                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 889                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 890                 /*
 891                  * The source and destination fields in the transmitted packet
 892                  * need to be presented in a reversed order with respect
 893                  * to the expected received packets.
 894                  */
 895                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 896                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 897                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 898                 break;
 899
 900         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 901                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 902                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 903                 /*
 904                  * The source and destination fields in the transmitted packet
 905                  * need to be presented in a reversed order with respect
 906                  * to the expected received packets.
 907                  */
 908                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 909                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 910                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 911                 break;
 912
 913         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 914         case RTE_ETH_FLOW_FRAG_IPV6:
 915                 payload = raw_pkt + len;
 916                 set_idx = I40E_FLXPLD_L3_IDX;
 917                 break;
 918         case RTE_ETH_FLOW_L2_PAYLOAD:
 919                 payload = raw_pkt + len;
 920                 /*
 921                  * ARP packet is a special case on which the payload
 922                  * starts after the whole ARP header
 923                  */
 924                 if (fdir_input->flow.l2_flow.ether_type ==
 925                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 926                         payload += sizeof(struct arp_hdr);
 927                 set_idx = I40E_FLXPLD_L2_IDX;
 928                 break;
 929         default:
 930                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 931                 return -EINVAL;
 932         }
 933
 934         /* fill the flexbytes to payload */
 935         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 936                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 937                 size = pf->fdir.flex_set[pit_idx].size;
 938                 if (size == 0)
 939                         continue;
 940                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 941                 ptr = payload +
 942                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 943                 (void)rte_memcpy(ptr,
 944                                  &fdir_input->flow_ext.flexbytes[dst],
 945                                  size * sizeof(uint16_t));
 946         }
 947
 948         return 0;
 949 }
 950
 951 /* Construct the tx flags */
 952 static inline uint64_t
 953 i40e_build_ctob(uint32_t td_cmd,
 954                 uint32_t td_offset,
 955                 unsigned int size,
 956                 uint32_t td_tag)
 957 {
 958         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 959                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 960                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 961                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 962                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 963 }
 964
 965 /*
 966  * check the programming status descriptor in rx queue.
 967  * done after Programming Flow Director is programmed on
 968  * tx queue
 969  */
 970 static inline int
 971 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 972 {
 973         volatile union i40e_rx_desc *rxdp;
 974         uint64_t qword1;
 975         uint32_t rx_status;
 976         uint32_t len, id;
 977         uint32_t error;
 978         int ret = 0;
 979
 980         rxdp = &rxq->rx_ring[rxq->rx_tail];
 981         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 982         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 983                         >> I40E_RXD_QW1_STATUS_SHIFT;
 984
 985         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 986                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 987                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 988                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 989
 990                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 991                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 992                         error = (qword1 &
 993                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 994                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 995                         if (error == (0x1 <<
 996                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 997                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 998                                             " (FD_ID %u): programming status"
 999                                             " reported.",
1000                                             rxdp->wb.qword0.hi_dword.fd_id);
1001                                 ret = -1;
1002                         } else if (error == (0x1 <<
1003                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1004                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1005                                             " (FD_ID %u): programming status"
1006                                             " reported.",
1007                                             rxdp->wb.qword0.hi_dword.fd_id);
1008                                 ret = -1;
1009                         } else
1010                                 PMD_DRV_LOG(ERR, "invalid programming status"
1011                                             " reported, error = %u.", error);
1012                 } else
1013                         PMD_DRV_LOG(INFO, "unknown programming status"
1014                                     " reported, len = %d, id = %u.", len, id);
1015                 rxdp->wb.qword1.status_error_len = 0;
1016                 rxq->rx_tail++;
1017                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1018                         rxq->rx_tail = 0;
1019                 if (rxq->rx_tail == 0)
1020                         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1021                 else
1022                         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
1023         }
1024
1025         return ret;
1026 }
1027
1028 /*
1029  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1030  * @pf: board private structure
1031  * @filter: fdir filter entry
1032  * @add: 0 - delete, 1 - add
1033  */
1034 static int
1035 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1036                             const struct rte_eth_fdir_filter *filter,
1037                             bool add)
1038 {
1039         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1041         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1042         enum i40e_filter_pctype pctype;
1043         int ret = 0;
1044
1045         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1046                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1047                         " check the mode in fdir_conf.");
1048                 return -ENOTSUP;
1049         }
1050
1051         if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1052                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1053                 return -EINVAL;
1054         }
1055         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1056                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1057                 return -EINVAL;
1058         }
1059         if (filter->input.flow_ext.is_vf &&
1060                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1061                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1062                 return -EINVAL;
1063         }
1064
1065         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1066
1067         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1068         if (ret < 0) {
1069                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1070                 return ret;
1071         }
1072
1073         if (hw->mac.type == I40E_MAC_X722) {
1074                 /* get translated pctype value in fd pctype register */
1075                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1076                         hw, I40E_GLQF_FD_PCTYPES(
1077                         (int)i40e_flowtype_to_pctype(
1078                         filter->input.flow_type)));
1079         } else
1080                 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1081
1082         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1083         if (ret < 0) {
1084                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1085                             pctype);
1086                 return ret;
1087         }
1088         return ret;
1089 }
1090
1091 /*
1092  * i40e_fdir_filter_programming - Program a flow director filter rule.
1093  * Is done by Flow Director Programming Descriptor followed by packet
1094  * structure that contains the filter fields need to match.
1095  * @pf: board private structure
1096  * @pctype: pctype
1097  * @filter: fdir filter entry
1098  * @add: 0 - delete, 1 - add
1099  */
1100 static int
1101 i40e_fdir_filter_programming(struct i40e_pf *pf,
1102                         enum i40e_filter_pctype pctype,
1103                         const struct rte_eth_fdir_filter *filter,
1104                         bool add)
1105 {
1106         struct i40e_tx_queue *txq = pf->fdir.txq;
1107         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1108         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1109         volatile struct i40e_tx_desc *txdp;
1110         volatile struct i40e_filter_program_desc *fdirdp;
1111         uint32_t td_cmd;
1112         uint16_t vsi_id, i;
1113         uint8_t dest;
1114
1115         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1116         fdirdp = (volatile struct i40e_filter_program_desc *)
1117                         (&(txq->tx_ring[txq->tx_tail]));
1118
1119         fdirdp->qindex_flex_ptype_vsi =
1120                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1121                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1122                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1123
1124         fdirdp->qindex_flex_ptype_vsi |=
1125                         rte_cpu_to_le_32((fdir_action->flex_off <<
1126                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1127                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1128
1129         fdirdp->qindex_flex_ptype_vsi |=
1130                         rte_cpu_to_le_32((pctype <<
1131                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1132                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1133
1134         if (filter->input.flow_ext.is_vf)
1135                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1136         else
1137                 /* Use LAN VSI Id by default */
1138                 vsi_id = pf->main_vsi->vsi_id;
1139         fdirdp->qindex_flex_ptype_vsi |=
1140                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1141                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1142                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1143
1144         fdirdp->dtype_cmd_cntindex =
1145                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1146
1147         if (add)
1148                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1149                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1150                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1151         else
1152                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1153                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1154                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1155
1156         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1157                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1158         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1159                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1160         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1161                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1162         else {
1163                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1164                             " unsupported fdir behavior.");
1165                 return -EINVAL;
1166         }
1167
1168         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1169                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1170                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1171
1172         fdirdp->dtype_cmd_cntindex |=
1173                 rte_cpu_to_le_32((fdir_action->report_status<<
1174                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1175                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1176
1177         fdirdp->dtype_cmd_cntindex |=
1178                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1179         fdirdp->dtype_cmd_cntindex |=
1180                         rte_cpu_to_le_32(
1181                         ((uint32_t)pf->fdir.match_counter_index <<
1182                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1183                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1184
1185         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1186
1187         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1188         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1189         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1190         td_cmd = I40E_TX_DESC_CMD_EOP |
1191                  I40E_TX_DESC_CMD_RS  |
1192                  I40E_TX_DESC_CMD_DUMMY;
1193
1194         txdp->cmd_type_offset_bsz =
1195                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1196
1197         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1198         if (txq->tx_tail >= txq->nb_tx_desc)
1199                 txq->tx_tail = 0;
1200         /* Update the tx tail register */
1201         rte_wmb();
1202         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1203
1204         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1205                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1206                 if ((txdp->cmd_type_offset_bsz &
1207                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1208                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1209                         break;
1210         }
1211         if (i >= I40E_FDIR_WAIT_COUNT) {
1212                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1213                             " time out to get DD on tx queue.");
1214                 return -ETIMEDOUT;
1215         }
1216         /* totally delay 10 ms to check programming status*/
1217         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1218         if (i40e_check_fdir_programming_status(rxq) < 0) {
1219                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1220                             " programming status reported.");
1221                 return -ENOSYS;
1222         }
1223
1224         return 0;
1225 }
1226
1227 /*
1228  * i40e_fdir_flush - clear all filters of Flow Director table
1229  * @pf: board private structure
1230  */
1231 static int
1232 i40e_fdir_flush(struct rte_eth_dev *dev)
1233 {
1234         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1235         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1236         uint32_t reg;
1237         uint16_t guarant_cnt, best_cnt;
1238         uint16_t i;
1239
1240         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1241         I40E_WRITE_FLUSH(hw);
1242
1243         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1244                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1245                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1246                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1247                         break;
1248         }
1249         if (i >= I40E_FDIR_FLUSH_RETRY) {
1250                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1251                 return -ETIMEDOUT;
1252         }
1253         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1254                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1255                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1256         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1257                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1258                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1259         if (guarant_cnt != 0 || best_cnt != 0) {
1260                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1261                 return -ENOSYS;
1262         } else
1263                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1264         return 0;
1265 }
1266
1267 static inline void
1268 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1269                         struct rte_eth_flex_payload_cfg *flex_set,
1270                         uint16_t *num)
1271 {
1272         struct i40e_fdir_flex_pit *flex_pit;
1273         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1274         uint16_t src, dst, size, j, k;
1275         uint8_t i, layer_idx;
1276
1277         for (layer_idx = I40E_FLXPLD_L2_IDX;
1278              layer_idx <= I40E_FLXPLD_L4_IDX;
1279              layer_idx++) {
1280                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1281                         ptr->type = RTE_ETH_L2_PAYLOAD;
1282                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1283                         ptr->type = RTE_ETH_L3_PAYLOAD;
1284                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1285                         ptr->type = RTE_ETH_L4_PAYLOAD;
1286
1287                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1288                         flex_pit = &pf->fdir.flex_set[layer_idx *
1289                                 I40E_MAX_FLXPLD_FIED + i];
1290                         if (flex_pit->size == 0)
1291                                 continue;
1292                         src = flex_pit->src_offset * sizeof(uint16_t);
1293                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1294                         size = flex_pit->size * sizeof(uint16_t);
1295                         for (j = src, k = dst; j < src + size; j++, k++)
1296                                 ptr->src_offset[k] = j;
1297                 }
1298                 (*num)++;
1299                 ptr++;
1300         }
1301 }
1302
1303 static inline void
1304 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1305                         struct rte_eth_fdir_flex_mask *flex_mask,
1306                         uint16_t *num)
1307 {
1308         struct i40e_fdir_flex_mask *mask;
1309         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1310         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1311         uint16_t flow_type;
1312         uint8_t i, j;
1313         uint16_t off_bytes, mask_tmp;
1314
1315         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1316              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1317              i++) {
1318                 mask =  &pf->fdir.flex_mask[i];
1319                 if (hw->mac.type == I40E_MAC_X722) {
1320                         if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1321                                 continue;
1322                 } else {
1323                         if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1324                                 continue;
1325                 }
1326                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1327                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1328                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1329                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1330                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1331                         } else {
1332                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1333                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1334                         }
1335                 }
1336                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1337                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1338                         mask_tmp = ~mask->bitmask[j].mask;
1339                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1340                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1341                 }
1342                 ptr->flow_type = flow_type;
1343                 ptr++;
1344                 (*num)++;
1345         }
1346 }
1347
1348 /*
1349  * i40e_fdir_info_get - get information of Flow Director
1350  * @pf: ethernet device to get info from
1351  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1352  *    the flow director information.
1353  */
1354 static void
1355 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1356 {
1357         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1358         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1359         uint16_t num_flex_set = 0;
1360         uint16_t num_flex_mask = 0;
1361
1362         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1363                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1364         else
1365                 fdir->mode = RTE_FDIR_MODE_NONE;
1366
1367         fdir->guarant_spc =
1368                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1369         fdir->best_spc =
1370                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1371         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1372         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1373         fdir->flex_payload_unit = sizeof(uint16_t);
1374         fdir->flex_bitmask_unit = sizeof(uint16_t);
1375         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1376         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1377         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1378
1379         i40e_fdir_info_get_flex_set(pf,
1380                                 fdir->flex_conf.flex_set,
1381                                 &num_flex_set);
1382         i40e_fdir_info_get_flex_mask(pf,
1383                                 fdir->flex_conf.flex_mask,
1384                                 &num_flex_mask);
1385
1386         fdir->flex_conf.nb_payloads = num_flex_set;
1387         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1388 }
1389
1390 /*
1391  * i40e_fdir_stat_get - get statistics of Flow Director
1392  * @pf: ethernet device to get info from
1393  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1394  *    the flow director statistics.
1395  */
1396 static void
1397 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1398 {
1399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1400         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1401         uint32_t fdstat;
1402
1403         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1404         stat->guarant_cnt =
1405                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1406                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1407         stat->best_cnt =
1408                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1409                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1410 }
1411
1412 static int
1413 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1414                      struct rte_eth_fdir_filter_info *info)
1415 {
1416         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1417         int ret = 0;
1418
1419         if (!info) {
1420                 PMD_DRV_LOG(ERR, "Invalid pointer");
1421                 return -EFAULT;
1422         }
1423
1424         switch (info->info_type) {
1425         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1426                 ret = i40e_fdir_filter_inset_select(pf,
1427                                 &(info->info.input_set_conf));
1428                 break;
1429         default:
1430                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1431                             info->info_type);
1432                 return -EINVAL;
1433         }
1434
1435         return ret;
1436 }
1437
1438 /*
1439  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1440  * @pf: board private structure
1441  * @filter_op:operation will be taken.
1442  * @arg: a pointer to specific structure corresponding to the filter_op
1443  */
1444 int
1445 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1446                        enum rte_filter_op filter_op,
1447                        void *arg)
1448 {
1449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1450         int ret = 0;
1451
1452         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1453                 return -ENOTSUP;
1454
1455         if (filter_op == RTE_ETH_FILTER_NOP)
1456                 return 0;
1457
1458         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1459                 return -EINVAL;
1460
1461         switch (filter_op) {
1462         case RTE_ETH_FILTER_ADD:
1463                 ret = i40e_add_del_fdir_filter(dev,
1464                         (struct rte_eth_fdir_filter *)arg,
1465                         TRUE);
1466                 break;
1467         case RTE_ETH_FILTER_DELETE:
1468                 ret = i40e_add_del_fdir_filter(dev,
1469                         (struct rte_eth_fdir_filter *)arg,
1470                         FALSE);
1471                 break;
1472         case RTE_ETH_FILTER_FLUSH:
1473                 ret = i40e_fdir_flush(dev);
1474                 break;
1475         case RTE_ETH_FILTER_INFO:
1476                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1477                 break;
1478         case RTE_ETH_FILTER_SET:
1479                 ret = i40e_fdir_filter_set(dev,
1480                         (struct rte_eth_fdir_filter_info *)arg);
1481                 break;
1482         case RTE_ETH_FILTER_STATS:
1483                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1484                 break;
1485         default:
1486                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1487                 ret = -EINVAL;
1488                 break;
1489         }
1490         return ret;
1491 }